From c41564d33ea835e844833dbf79b65bc9f3eed2d4 Mon Sep 17 00:00:00 2001 From: rtel Date: Mon, 14 Jul 2014 13:00:18 +0000 Subject: [PATCH] Add back Zynq demo - this time using SDK V14.2. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2278 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- .../CORTEX_A9_Zynq_ZC702/RTOSDemo/.cproject | 112 + .../CORTEX_A9_Zynq_ZC702/RTOSDemo/.project | 215 + .../RTOSDemo/src/Blinky_Demo/main_blinky.c | 226 + .../RTOSDemo/src/FreeRTOSConfig.h | 243 + .../RTOSDemo/src/FreeRTOS_asm_vectors.S | 144 + .../RTOSDemo/src/FreeRTOS_tick_config.c | 165 + .../RTOSDemo/src/Full_Demo/IntQueueTimer.c | 261 + .../RTOSDemo/src/Full_Demo/IntQueueTimer.h | 74 + .../RTOSDemo/src/Full_Demo/main_full.c | 504 + .../RTOSDemo/src/Full_Demo/reg_test.S | 658 + .../RTOSDemo/src/Full_Demo/serial.c | 321 + .../RTOSDemo/src/ParTest.c | 129 + .../RTOSDemo/src/lscript.ld | 285 + .../BasicSocketCommandServer.c | 203 + .../httpserver_raw_from_lwIP_download/fs.c | 177 + .../httpserver_raw_from_lwIP_download/fs.h | 100 + .../fsdata.c | 2068 + .../fsdata.h | 50 + .../httpserver_raw_from_lwIP_download/httpd.c | 2184 + .../httpserver_raw_from_lwIP_download/httpd.h | 236 + .../httpd_structs.h | 115 + .../makefsdata/MakeFSData_proj.sln | 20 + .../makefsdata/MakeFSData_proj.suo | Bin 0 -> 11264 bytes .../makefsdata/MakeFSData_proj.vcxproj | 91 + .../MakeFSData_proj.vcxproj.filters | 36 + .../makefsdata/MakeFSData_proj.vcxproj.user | 3 + .../makefsdata/fs/404.html | 21 + .../makefsdata/fs/index.shtml | 20 + .../makefsdata/fs/logo.jpg | Bin 0 -> 28602 bytes .../makefsdata/fs/runtime.shtml | 20 + .../makefsdata/fsdata.c | 2068 + .../makefsdata/makefsdata | 97 + .../makefsdata/makefsdata.c | 610 + .../makefsdata/makefsdata.exe | Bin 0 -> 46592 bytes .../makefsdata/stdafx.cpp | 8 + .../makefsdata/stdafx.h | 15 + .../makefsdata/targetver.h | 8 + .../src/lwIP_Demo/lwIP_Apps/lwIP_Apps.c | 262 + .../src/lwIP_Demo/lwIP_Apps/lwIP_Apps.h | 62 + .../src/lwIP_Demo/lwIP_Apps/lwipcfg_msvc.h | 46 + .../lwIP_port/include/arch/bpstruct.h | 1 + .../src/lwIP_Demo/lwIP_port/include/arch/cc.h | 109 + .../lwIP_port/include/arch/epstruct.h | 1 + .../lwIP_Demo/lwIP_port/include/arch/perf.h | 40 + .../lwIP_port/include/arch/sys_arch.h | 58 + .../lwIP_port/include/netif/xadapter.h | 67 + .../lwIP_port/include/netif/xaxiemacif.h | 94 + .../lwIP_port/include/netif/xemacliteif.h | 53 + .../lwIP_port/include/netif/xemacpsif.h | 109 + .../lwIP_port/include/netif/xlltemacif.h | 80 + .../lwIP_port/include/netif/xpqueue.h | 42 + .../lwIP_port/include/netif/xtopology.h | 46 + .../lwIP_Demo/lwIP_port/include/xlwipconfig.h | 12 + .../src/lwIP_Demo/lwIP_port/netif/xadapter.c | 274 + .../src/lwIP_Demo/lwIP_port/netif/xemacpsif.c | 458 + .../lwIP_Demo/lwIP_port/netif/xemacpsif_dma.c | 622 + .../lwIP_Demo/lwIP_port/netif/xemacpsif_hw.c | 208 + .../lwIP_Demo/lwIP_port/netif/xemacpsif_hw.h | 37 + .../lwIP_port/netif/xemacpsif_physpeed.c | 558 + .../src/lwIP_Demo/lwIP_port/netif/xpqueue.c | 80 + .../lwIP_Demo/lwIP_port/netif/xtopology_g.c | 15 + .../src/lwIP_Demo/lwIP_port/sys_arch.c | 603 + .../RTOSDemo/src/lwIP_Demo/main_lwIP.c | 184 + .../RTOSDemo/src/lwipopts.h | 312 + .../CORTEX_A9_Zynq_ZC702/RTOSDemo/src/main.c | 388 + .../RTOSDemo/src/platform.c | 112 + .../RTOSDemo/src/platform.h | 27 + .../RTOSDemo/src/platform_config.h | 6 + .../RTOSDemo/src/printf-stdarg.c | 285 + .../RTOSDemo_bsp/.cproject | 13 + .../RTOSDemo_bsp/.project | 76 + .../RTOSDemo_bsp/.sdkproject | 3 + .../RTOSDemo_bsp/Makefile | 31 + .../include/_profile_timer_hw.h | 292 + .../ps7_cortexa9_0/include/bspconfig.h | 16 + .../ps7_cortexa9_0/include/mblaze_nt_types.h | 42 + .../ps7_cortexa9_0/include/profile.h | 130 + .../ps7_cortexa9_0/include/sleep.h | 58 + .../RTOSDemo_bsp/ps7_cortexa9_0/include/smc.h | 124 + .../ps7_cortexa9_0/include/vectors.h | 90 + .../ps7_cortexa9_0/include/xadcps.h | 568 + .../ps7_cortexa9_0/include/xadcps_hw.h | 508 + .../ps7_cortexa9_0/include/xbasic_types.h | 128 + .../ps7_cortexa9_0/include/xcanps.h | 570 + .../ps7_cortexa9_0/include/xcanps_hw.h | 375 + .../ps7_cortexa9_0/include/xcpu_cortexa9.h | 49 + .../ps7_cortexa9_0/include/xdebug.h | 61 + .../ps7_cortexa9_0/include/xdevcfg.h | 389 + .../ps7_cortexa9_0/include/xdevcfg_hw.h | 401 + .../ps7_cortexa9_0/include/xdmaps.h | 325 + .../ps7_cortexa9_0/include/xdmaps_hw.h | 299 + .../ps7_cortexa9_0/include/xemacps.h | 721 + .../ps7_cortexa9_0/include/xemacps_bd.h | 737 + .../ps7_cortexa9_0/include/xemacps_bdring.h | 242 + .../ps7_cortexa9_0/include/xemacps_hw.h | 605 + .../ps7_cortexa9_0/include/xenv.h | 177 + .../ps7_cortexa9_0/include/xenv_standalone.h | 356 + .../ps7_cortexa9_0/include/xgpiops.h | 264 + .../ps7_cortexa9_0/include/xgpiops_hw.h | 159 + .../ps7_cortexa9_0/include/xiicps.h | 410 + .../ps7_cortexa9_0/include/xiicps_hw.h | 388 + .../ps7_cortexa9_0/include/xil_assert.h | 196 + .../ps7_cortexa9_0/include/xil_cache.h | 84 + .../ps7_cortexa9_0/include/xil_cache_l.h | 103 + .../include/xil_cache_vxworks.h | 103 + .../ps7_cortexa9_0/include/xil_errata.h | 117 + .../ps7_cortexa9_0/include/xil_exception.h | 231 + .../ps7_cortexa9_0/include/xil_hal.h | 71 + .../ps7_cortexa9_0/include/xil_io.h | 254 + .../ps7_cortexa9_0/include/xil_macroback.h | 1069 + .../include/xil_misc_psreset_api.h | 286 + .../ps7_cortexa9_0/include/xil_mmu.h | 87 + .../ps7_cortexa9_0/include/xil_printf.h | 47 + .../ps7_cortexa9_0/include/xil_testcache.h | 71 + .../ps7_cortexa9_0/include/xil_testio.h | 101 + .../ps7_cortexa9_0/include/xil_testmem.h | 173 + .../ps7_cortexa9_0/include/xil_types.h | 173 + .../ps7_cortexa9_0/include/xl2cc.h | 180 + .../ps7_cortexa9_0/include/xl2cc_counter.h | 117 + .../ps7_cortexa9_0/include/xparameters.h | 475 + .../ps7_cortexa9_0/include/xparameters_ps.h | 334 + .../ps7_cortexa9_0/include/xpm_counter.h | 580 + .../ps7_cortexa9_0/include/xpseudo_asm.h | 62 + .../ps7_cortexa9_0/include/xpseudo_asm_gcc.h | 183 + .../ps7_cortexa9_0/include/xqspips.h | 790 + .../ps7_cortexa9_0/include/xqspips_hw.h | 381 + .../ps7_cortexa9_0/include/xreg_cortexa9.h | 599 + .../ps7_cortexa9_0/include/xscugic.h | 324 + .../ps7_cortexa9_0/include/xscugic_hw.h | 641 + .../ps7_cortexa9_0/include/xscutimer.h | 370 + .../ps7_cortexa9_0/include/xscutimer_hw.h | 292 + .../ps7_cortexa9_0/include/xscuwdt.h | 389 + .../ps7_cortexa9_0/include/xscuwdt_hw.h | 187 + .../ps7_cortexa9_0/include/xsdps.h | 192 + .../ps7_cortexa9_0/include/xsdps_hw.h | 614 + .../ps7_cortexa9_0/include/xstatus.h | 439 + .../ps7_cortexa9_0/include/xtime_l.h | 96 + .../ps7_cortexa9_0/include/xttcps.h | 417 + .../ps7_cortexa9_0/include/xttcps_hw.h | 218 + .../ps7_cortexa9_0/include/xuartps.h | 513 + .../ps7_cortexa9_0/include/xuartps_hw.h | 432 + .../ps7_cortexa9_0/include/xusbps.h | 1091 + .../ps7_cortexa9_0/include/xusbps_endpoint.h | 521 + .../ps7_cortexa9_0/include/xusbps_hw.h | 532 + .../libsrc/canps_v2_0/src/Makefile | 40 + .../libsrc/canps_v2_0/src/xcanps.c | 1164 + .../libsrc/canps_v2_0/src/xcanps.h | 570 + .../libsrc/canps_v2_0/src/xcanps_g.c | 31 + .../libsrc/canps_v2_0/src/xcanps_hw.c | 98 + .../libsrc/canps_v2_0/src/xcanps_hw.h | 375 + .../libsrc/canps_v2_0/src/xcanps_intr.c | 412 + .../libsrc/canps_v2_0/src/xcanps_selftest.c | 216 + .../libsrc/canps_v2_0/src/xcanps_sinit.c | 108 + .../libsrc/cpu_cortexa9_v2_0/src/Makefile | 23 + .../cpu_cortexa9_v2_0/src/xcpu_cortexa9.h | 49 + .../libsrc/devcfg_v3_1/src/Makefile | 41 + .../libsrc/devcfg_v3_1/src/xdevcfg.c | 941 + .../libsrc/devcfg_v3_1/src/xdevcfg.h | 389 + .../libsrc/devcfg_v3_1/src/xdevcfg_g.c | 31 + .../libsrc/devcfg_v3_1/src/xdevcfg_hw.c | 119 + .../libsrc/devcfg_v3_1/src/xdevcfg_hw.h | 401 + .../libsrc/devcfg_v3_1/src/xdevcfg_intr.c | 316 + .../libsrc/devcfg_v3_1/src/xdevcfg_selftest.c | 120 + .../libsrc/devcfg_v3_1/src/xdevcfg_sinit.c | 99 + .../libsrc/dmaps_v2_0/src/Makefile | 41 + .../libsrc/dmaps_v2_0/src/xdmaps.c | 1989 + .../libsrc/dmaps_v2_0/src/xdmaps.h | 325 + .../libsrc/dmaps_v2_0/src/xdmaps_g.c | 35 + .../libsrc/dmaps_v2_0/src/xdmaps_hw.c | 122 + .../libsrc/dmaps_v2_0/src/xdmaps_hw.h | 299 + .../libsrc/dmaps_v2_0/src/xdmaps_selftest.c | 116 + .../libsrc/dmaps_v2_0/src/xdmaps_sinit.c | 110 + .../libsrc/emacps_v2_0/src/Makefile | 41 + .../libsrc/emacps_v2_0/src/xemacps.c | 401 + .../libsrc/emacps_v2_0/src/xemacps.h | 721 + .../libsrc/emacps_v2_0/src/xemacps_bd.h | 737 + .../libsrc/emacps_v2_0/src/xemacps_bdring.c | 1010 + .../libsrc/emacps_v2_0/src/xemacps_bdring.h | 242 + .../libsrc/emacps_v2_0/src/xemacps_control.c | 1084 + .../libsrc/emacps_v2_0/src/xemacps_g.c | 31 + .../libsrc/emacps_v2_0/src/xemacps_hw.c | 132 + .../libsrc/emacps_v2_0/src/xemacps_hw.h | 605 + .../libsrc/emacps_v2_0/src/xemacps_intr.c | 229 + .../libsrc/emacps_v2_0/src/xemacps_sinit.c | 102 + .../libsrc/gpiops_v2_1/src/Makefile | 41 + .../libsrc/gpiops_v2_1/src/xgpiops.c | 606 + .../libsrc/gpiops_v2_1/src/xgpiops.h | 264 + .../libsrc/gpiops_v2_1/src/xgpiops_g.c | 31 + .../libsrc/gpiops_v2_1/src/xgpiops_hw.c | 171 + .../libsrc/gpiops_v2_1/src/xgpiops_hw.h | 159 + .../libsrc/gpiops_v2_1/src/xgpiops_intr.c | 741 + .../libsrc/gpiops_v2_1/src/xgpiops_selftest.c | 140 + .../libsrc/gpiops_v2_1/src/xgpiops_sinit.c | 106 + .../libsrc/iicps_v2_1/src/Makefile | 41 + .../libsrc/iicps_v2_1/src/xiicps.c | 331 + .../libsrc/iicps_v2_1/src/xiicps.h | 410 + .../libsrc/iicps_v2_1/src/xiicps_g.c | 32 + .../libsrc/iicps_v2_1/src/xiicps_hw.c | 116 + .../libsrc/iicps_v2_1/src/xiicps_hw.h | 388 + .../libsrc/iicps_v2_1/src/xiicps_intr.c | 106 + .../libsrc/iicps_v2_1/src/xiicps_master.c | 885 + .../libsrc/iicps_v2_1/src/xiicps_options.c | 495 + .../libsrc/iicps_v2_1/src/xiicps_selftest.c | 140 + .../libsrc/iicps_v2_1/src/xiicps_sinit.c | 107 + .../libsrc/iicps_v2_1/src/xiicps_slave.c | 585 + .../libsrc/qspips_v3_0/src/Makefile | 41 + .../libsrc/qspips_v3_0/src/xqspips.c | 1558 + .../libsrc/qspips_v3_0/src/xqspips.h | 790 + .../libsrc/qspips_v3_0/src/xqspips_g.c | 33 + .../libsrc/qspips_v3_0/src/xqspips_hw.c | 228 + .../libsrc/qspips_v3_0/src/xqspips_hw.h | 381 + .../libsrc/qspips_v3_0/src/xqspips_options.c | 434 + .../libsrc/qspips_v3_0/src/xqspips_selftest.c | 159 + .../libsrc/qspips_v3_0/src/xqspips_sinit.c | 106 + .../libsrc/scugic_v2_1/src/Makefile | 41 + .../libsrc/scugic_v2_1/src/xscugic.c | 719 + .../libsrc/scugic_v2_1/src/xscugic.h | 324 + .../libsrc/scugic_v2_1/src/xscugic_g.c | 32 + .../libsrc/scugic_v2_1/src/xscugic_hw.c | 567 + .../libsrc/scugic_v2_1/src/xscugic_hw.h | 641 + .../libsrc/scugic_v2_1/src/xscugic_intr.c | 176 + .../libsrc/scugic_v2_1/src/xscugic_selftest.c | 119 + .../libsrc/scugic_v2_1/src/xscugic_sinit.c | 109 + .../libsrc/scutimer_v2_0/src/Makefile | 41 + .../libsrc/scutimer_v2_0/src/xscutimer.c | 289 + .../libsrc/scutimer_v2_0/src/xscutimer.h | 370 + .../libsrc/scutimer_v2_0/src/xscutimer_g.c | 31 + .../libsrc/scutimer_v2_0/src/xscutimer_hw.h | 292 + .../scutimer_v2_0/src/xscutimer_selftest.c | 140 + .../scutimer_v2_0/src/xscutimer_sinit.c | 99 + .../libsrc/scuwdt_v2_0/src/Makefile | 41 + .../libsrc/scuwdt_v2_0/src/xscuwdt.c | 219 + .../libsrc/scuwdt_v2_0/src/xscuwdt.h | 389 + .../libsrc/scuwdt_v2_0/src/xscuwdt_g.c | 31 + .../libsrc/scuwdt_v2_0/src/xscuwdt_hw.h | 187 + .../libsrc/scuwdt_v2_0/src/xscuwdt_selftest.c | 132 + .../libsrc/scuwdt_v2_0/src/xscuwdt_sinit.c | 99 + .../libsrc/sdps_v2_1/src/Makefile | 41 + .../libsrc/sdps_v2_1/src/xsdps.c | 1109 + .../libsrc/sdps_v2_1/src/xsdps.h | 192 + .../libsrc/sdps_v2_1/src/xsdps_g.c | 32 + .../libsrc/sdps_v2_1/src/xsdps_hw.h | 614 + .../libsrc/sdps_v2_1/src/xsdps_options.c | 813 + .../libsrc/sdps_v2_1/src/xsdps_sinit.c | 105 + .../libsrc/standalone_v4_1/src/Makefile | 72 + .../libsrc/standalone_v4_1/src/_exit.c | 50 + .../libsrc/standalone_v4_1/src/_open.c | 62 + .../libsrc/standalone_v4_1/src/_sbrk.c | 70 + .../libsrc/standalone_v4_1/src/abort.c | 51 + .../libsrc/standalone_v4_1/src/asm_vectors.S | 208 + .../libsrc/standalone_v4_1/src/boot.S | 448 + .../libsrc/standalone_v4_1/src/bspconfig.h | 16 + .../libsrc/standalone_v4_1/src/changelog.txt | 175 + .../libsrc/standalone_v4_1/src/close.c | 55 + .../libsrc/standalone_v4_1/src/config.make | 3 + .../libsrc/standalone_v4_1/src/cpu_init.S | 88 + .../libsrc/standalone_v4_1/src/errno.c | 59 + .../libsrc/standalone_v4_1/src/fcntl.c | 54 + .../libsrc/standalone_v4_1/src/fstat.c | 58 + .../libsrc/standalone_v4_1/src/getpid.c | 59 + .../libsrc/standalone_v4_1/src/inbyte.c | 14 + .../libsrc/standalone_v4_1/src/isatty.c | 64 + .../libsrc/standalone_v4_1/src/kill.c | 67 + .../libsrc/standalone_v4_1/src/lseek.c | 69 + .../libsrc/standalone_v4_1/src/open.c | 61 + .../libsrc/standalone_v4_1/src/outbyte.c | 15 + .../libsrc/standalone_v4_1/src/print.c | 31 + .../standalone_v4_1/src/profile/Makefile | 65 + .../src/profile/_profile_clean.c | 33 + .../src/profile/_profile_init.c | 80 + .../src/profile/_profile_timer_hw.c | 346 + .../src/profile/_profile_timer_hw.h | 292 + .../standalone_v4_1/src/profile/dummy.S | 50 + .../src/profile/mblaze_nt_types.h | 42 + .../standalone_v4_1/src/profile/profile.h | 130 + .../standalone_v4_1/src/profile/profile_cg.c | 148 + .../src/profile/profile_config.h | 36 + .../src/profile/profile_hist.c | 58 + .../src/profile/profile_mcount_arm.S | 33 + .../src/profile/profile_mcount_mb.S | 55 + .../src/profile/profile_mcount_ppc.S | 58 + .../libsrc/standalone_v4_1/src/putnum.c | 41 + .../libsrc/standalone_v4_1/src/read.c | 106 + .../libsrc/standalone_v4_1/src/sbrk.c | 76 + .../libsrc/standalone_v4_1/src/sleep.c | 89 + .../libsrc/standalone_v4_1/src/sleep.h | 58 + .../libsrc/standalone_v4_1/src/smc.c | 146 + .../libsrc/standalone_v4_1/src/smc.h | 124 + .../standalone_v4_1/src/translation_table.s | 141 + .../libsrc/standalone_v4_1/src/uart.c | 159 + .../libsrc/standalone_v4_1/src/unlink.c | 58 + .../libsrc/standalone_v4_1/src/usleep.c | 113 + .../libsrc/standalone_v4_1/src/vectors.c | 177 + .../libsrc/standalone_v4_1/src/vectors.h | 90 + .../libsrc/standalone_v4_1/src/write.c | 103 + .../libsrc/standalone_v4_1/src/xbasic_types.h | 128 + .../libsrc/standalone_v4_1/src/xdebug.h | 61 + .../libsrc/standalone_v4_1/src/xenv.h | 177 + .../standalone_v4_1/src/xenv_standalone.h | 356 + .../libsrc/standalone_v4_1/src/xil-crt0.S | 166 + .../libsrc/standalone_v4_1/src/xil_assert.c | 157 + .../libsrc/standalone_v4_1/src/xil_assert.h | 196 + .../libsrc/standalone_v4_1/src/xil_cache.c | 1497 + .../libsrc/standalone_v4_1/src/xil_cache.h | 84 + .../libsrc/standalone_v4_1/src/xil_cache_l.h | 103 + .../standalone_v4_1/src/xil_cache_vxworks.h | 103 + .../libsrc/standalone_v4_1/src/xil_errata.h | 117 + .../standalone_v4_1/src/xil_exception.c | 188 + .../standalone_v4_1/src/xil_exception.h | 231 + .../libsrc/standalone_v4_1/src/xil_hal.h | 71 + .../libsrc/standalone_v4_1/src/xil_io.c | 350 + .../libsrc/standalone_v4_1/src/xil_io.h | 254 + .../standalone_v4_1/src/xil_macroback.h | 1069 + .../src/xil_misc_psreset_api.c | 531 + .../src/xil_misc_psreset_api.h | 286 + .../libsrc/standalone_v4_1/src/xil_mmu.c | 185 + .../libsrc/standalone_v4_1/src/xil_mmu.h | 87 + .../libsrc/standalone_v4_1/src/xil_printf.c | 281 + .../libsrc/standalone_v4_1/src/xil_printf.h | 47 + .../standalone_v4_1/src/xil_testcache.c | 225 + .../standalone_v4_1/src/xil_testcache.h | 71 + .../libsrc/standalone_v4_1/src/xil_testio.c | 304 + .../libsrc/standalone_v4_1/src/xil_testio.h | 101 + .../libsrc/standalone_v4_1/src/xil_testmem.c | 1004 + .../libsrc/standalone_v4_1/src/xil_testmem.h | 173 + .../libsrc/standalone_v4_1/src/xil_types.h | 173 + .../libsrc/standalone_v4_1/src/xl2cc.h | 180 + .../standalone_v4_1/src/xl2cc_counter.c | 174 + .../standalone_v4_1/src/xl2cc_counter.h | 117 + .../standalone_v4_1/src/xparameters_ps.h | 334 + .../libsrc/standalone_v4_1/src/xpm_counter.c | 300 + .../libsrc/standalone_v4_1/src/xpm_counter.h | 580 + .../libsrc/standalone_v4_1/src/xpseudo_asm.h | 62 + .../standalone_v4_1/src/xpseudo_asm_gcc.h | 183 + .../standalone_v4_1/src/xreg_cortexa9.h | 599 + .../libsrc/standalone_v4_1/src/xstatus.h | 439 + .../libsrc/standalone_v4_1/src/xtime_l.c | 129 + .../libsrc/standalone_v4_1/src/xtime_l.h | 96 + .../libsrc/ttcps_v2_0/src/Makefile | 41 + .../libsrc/ttcps_v2_0/src/xttcps.c | 434 + .../libsrc/ttcps_v2_0/src/xttcps.h | 417 + .../libsrc/ttcps_v2_0/src/xttcps_g.c | 42 + .../libsrc/ttcps_v2_0/src/xttcps_hw.h | 218 + .../libsrc/ttcps_v2_0/src/xttcps_options.c | 242 + .../libsrc/ttcps_v2_0/src/xttcps_selftest.c | 112 + .../libsrc/ttcps_v2_0/src/xttcps_sinit.c | 104 + .../libsrc/uartps_v2_1/src/Makefile | 41 + .../libsrc/uartps_v2_1/src/xuartps.c | 673 + .../libsrc/uartps_v2_1/src/xuartps.h | 513 + .../libsrc/uartps_v2_1/src/xuartps_g.c | 33 + .../libsrc/uartps_v2_1/src/xuartps_hw.c | 201 + .../libsrc/uartps_v2_1/src/xuartps_hw.h | 432 + .../libsrc/uartps_v2_1/src/xuartps_intr.c | 452 + .../libsrc/uartps_v2_1/src/xuartps_options.c | 805 + .../libsrc/uartps_v2_1/src/xuartps_selftest.c | 176 + .../libsrc/uartps_v2_1/src/xuartps_sinit.c | 104 + .../libsrc/usbps_v2_1/src/Makefile | 41 + .../libsrc/usbps_v2_1/src/xusbps.c | 370 + .../libsrc/usbps_v2_1/src/xusbps.h | 1091 + .../libsrc/usbps_v2_1/src/xusbps_endpoint.c | 1455 + .../libsrc/usbps_v2_1/src/xusbps_endpoint.h | 521 + .../libsrc/usbps_v2_1/src/xusbps_g.c | 31 + .../libsrc/usbps_v2_1/src/xusbps_hw.c | 128 + .../libsrc/usbps_v2_1/src/xusbps_hw.h | 532 + .../libsrc/usbps_v2_1/src/xusbps_intr.c | 476 + .../libsrc/usbps_v2_1/src/xusbps_sinit.c | 105 + .../libsrc/xadcps_v2_0/src/Makefile | 41 + .../libsrc/xadcps_v2_0/src/xadcps.c | 1835 + .../libsrc/xadcps_v2_0/src/xadcps.h | 568 + .../libsrc/xadcps_v2_0/src/xadcps_g.c | 31 + .../libsrc/xadcps_v2_0/src/xadcps_hw.h | 508 + .../libsrc/xadcps_v2_0/src/xadcps_intr.c | 256 + .../libsrc/xadcps_v2_0/src/xadcps_selftest.c | 147 + .../libsrc/xadcps_v2_0/src/xadcps_sinit.c | 109 + .../RTOSDemo_bsp/system.mss | 239 + .../ZC702_hw_platform/.project | 12 + .../ZC702_hw_platform/ps7_init.c | 12955 ++ .../ZC702_hw_platform/ps7_init.h | 150 + .../ZC702_hw_platform/ps7_init.html | 147311 +++++++++++++++ .../ZC702_hw_platform/ps7_init.tcl | 887 + .../ZC702_hw_platform/system.xml | 7184 + 381 files changed, 269762 insertions(+) create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/.cproject create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/.project create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Blinky_Demo/main_blinky.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/FreeRTOSConfig.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/FreeRTOS_asm_vectors.S create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/FreeRTOS_tick_config.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/IntQueueTimer.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/IntQueueTimer.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/main_full.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/reg_test.S create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/serial.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/ParTest.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lscript.ld create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/BasicSocketCommandServer/BasicSocketCommandServer.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/fs.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/fs.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/fsdata.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/fsdata.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/httpd.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/httpd.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/httpd_structs.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/MakeFSData_proj.sln create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/MakeFSData_proj.suo create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/MakeFSData_proj.vcxproj create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/MakeFSData_proj.vcxproj.filters create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/MakeFSData_proj.vcxproj.user create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/fs/404.html create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/fs/index.shtml create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/fs/logo.jpg create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/fs/runtime.shtml create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/fsdata.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/makefsdata create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/makefsdata.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/makefsdata.exe create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/stdafx.cpp create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/stdafx.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/targetver.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/lwIP_Apps.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/lwIP_Apps.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/lwipcfg_msvc.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/arch/bpstruct.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/arch/cc.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/arch/epstruct.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/arch/perf.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/arch/sys_arch.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/netif/xadapter.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/netif/xaxiemacif.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/netif/xemacliteif.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/netif/xemacpsif.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/netif/xlltemacif.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/netif/xpqueue.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/netif/xtopology.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/xlwipconfig.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/netif/xadapter.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/netif/xemacpsif.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/netif/xemacpsif_dma.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/netif/xemacpsif_hw.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/netif/xemacpsif_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/netif/xemacpsif_physpeed.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/netif/xpqueue.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/netif/xtopology_g.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/sys_arch.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/main_lwIP.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwipopts.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/main.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/platform.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/platform.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/platform_config.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/printf-stdarg.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/.cproject create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/.project create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/.sdkproject create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/_profile_timer_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/bspconfig.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/mblaze_nt_types.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/profile.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/sleep.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/smc.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/vectors.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xadcps.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xadcps_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xbasic_types.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xcanps.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xcanps_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xdebug.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xdevcfg.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xdmaps.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xdmaps_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xemacps.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xemacps_bd.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xemacps_bdring.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xemacps_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xenv.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xenv_standalone.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xgpiops.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xgpiops_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xiicps.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xiicps_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_assert.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_cache.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_cache_l.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_errata.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_exception.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_hal.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_io.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_macroback.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_mmu.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_printf.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_testcache.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_testio.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_testmem.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_types.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xl2cc.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xl2cc_counter.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xparameters.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xparameters_ps.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xpm_counter.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xpseudo_asm.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xqspips.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xqspips_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xscugic.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xscugic_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xscutimer.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xscutimer_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xscuwdt.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xscuwdt_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xsdps.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xsdps_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xstatus.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xtime_l.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xttcps.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xttcps_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xuartps.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xuartps_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xusbps.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xusbps_endpoint.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xusbps_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/xcanps.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/xcanps.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/xcanps_g.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/xcanps_hw.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/xcanps_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/xcanps_intr.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/xcanps_selftest.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/xcanps_sinit.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_0/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_0/src/xcpu_cortexa9.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/xdevcfg.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/xdevcfg.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/xdevcfg_g.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/xdevcfg_hw.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/xdevcfg_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/xdevcfg_intr.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/xdevcfg_selftest.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/xdevcfg_sinit.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_0/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_0/src/xdmaps.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_0/src/xdmaps.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_0/src/xdmaps_g.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_0/src/xdmaps_hw.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_0/src/xdmaps_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_0/src/xdmaps_selftest.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_0/src/xdmaps_sinit.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_bd.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_bdring.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_bdring.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_control.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_g.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_hw.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_intr.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_sinit.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/xgpiops.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/xgpiops.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/xgpiops_g.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/xgpiops_hw.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/xgpiops_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/xgpiops_intr.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/xgpiops_selftest.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/xgpiops_sinit.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_g.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_hw.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_intr.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_master.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_options.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_selftest.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_sinit.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_slave.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/xqspips.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/xqspips.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/xqspips_g.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/xqspips_hw.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/xqspips_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/xqspips_options.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/xqspips_selftest.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/xqspips_sinit.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/xscugic.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/xscugic.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/xscugic_g.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/xscugic_hw.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/xscugic_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/xscugic_intr.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/xscugic_selftest.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/xscugic_sinit.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_0/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_0/src/xscutimer.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_0/src/xscutimer.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_0/src/xscutimer_g.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_0/src/xscutimer_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_0/src/xscutimer_selftest.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_0/src/xscutimer_sinit.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_0/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_0/src/xscuwdt.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_0/src/xscuwdt.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_0/src/xscuwdt_g.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_0/src/xscuwdt_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_0/src/xscuwdt_selftest.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_0/src/xscuwdt_sinit.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_1/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_1/src/xsdps.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_1/src/xsdps.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_1/src/xsdps_g.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_1/src/xsdps_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_1/src/xsdps_options.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_1/src/xsdps_sinit.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/_exit.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/_open.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/_sbrk.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/abort.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/asm_vectors.S create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/boot.S create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/bspconfig.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/changelog.txt create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/close.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/config.make create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/cpu_init.S create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/errno.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/fcntl.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/fstat.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/getpid.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/inbyte.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/isatty.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/kill.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/lseek.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/open.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/outbyte.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/print.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/_profile_clean.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/_profile_init.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/_profile_timer_hw.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/_profile_timer_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/dummy.S create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/mblaze_nt_types.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/profile.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/profile_cg.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/profile_config.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/profile_hist.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/profile_mcount_arm.S create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/profile_mcount_mb.S create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/profile_mcount_ppc.S create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/putnum.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/read.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/sbrk.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/sleep.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/sleep.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/smc.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/smc.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/translation_table.s create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/uart.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/unlink.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/usleep.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/vectors.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/vectors.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/write.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xbasic_types.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xdebug.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xenv.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xenv_standalone.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil-crt0.S create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_assert.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_assert.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_cache.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_cache.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_cache_l.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_cache_vxworks.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_errata.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_exception.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_exception.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_hal.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_io.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_io.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_macroback.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_misc_psreset_api.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_misc_psreset_api.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_mmu.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_mmu.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_printf.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_printf.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_testcache.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_testcache.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_testio.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_testio.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_testmem.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_testmem.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_types.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xl2cc.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xl2cc_counter.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xl2cc_counter.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xparameters_ps.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xpm_counter.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xpm_counter.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xpseudo_asm.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xpseudo_asm_gcc.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xreg_cortexa9.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xstatus.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xtime_l.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xtime_l.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v2_0/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v2_0/src/xttcps.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v2_0/src/xttcps.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v2_0/src/xttcps_g.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v2_0/src/xttcps_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v2_0/src/xttcps_options.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v2_0/src/xttcps_selftest.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v2_0/src/xttcps_sinit.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps_g.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps_hw.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps_intr.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps_options.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps_selftest.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps_sinit.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps_endpoint.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps_endpoint.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps_g.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps_hw.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps_intr.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps_sinit.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_0/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_0/src/xadcps.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_0/src/xadcps.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_0/src/xadcps_g.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_0/src/xadcps_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_0/src/xadcps_intr.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_0/src/xadcps_selftest.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_0/src/xadcps_sinit.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/system.mss create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/.project create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init.c create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init.h create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init.html create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init.tcl create mode 100644 FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/system.xml diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/.cproject b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/.cproject new file mode 100644 index 000000000..ae8e1ba1a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/.cproject @@ -0,0 +1,112 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/.project b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/.project new file mode 100644 index 000000000..9e078008b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/.project @@ -0,0 +1,215 @@ + + + RTOSDemo + Created by SDK v2014.2. RTOSDemo_bsp - ps7_cortexa9_0 + + RTOSDemo_bsp + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + src/FreeRTOS_Source + 2 + FREERTOS_ROOT/FreeRTOS/Source + + + src/Full_Demo/FreeRTOS-Plus-CLI + 2 + FREERTOS_ROOT/FreeRTOS-Plus/Source/FreeRTOS-Plus-CLI + + + src/Full_Demo/IntQueue.c + 1 + FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal/IntQueue.c + + + src/Full_Demo/Sample-CLI-commands.c + 1 + FREERTOS_ROOT/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/Sample-CLI-commands.c + + + src/Full_Demo/Standard-Demo-Tasks + 2 + FREERTOS_ROOT/FreeRTOS/Demo/Common + + + src/Full_Demo/UARTCommandConsole.c + 1 + FREERTOS_ROOT/FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_CLI_Demos/UARTCommandConsole.c + + + src/lwIP_Demo/lwip-1.4.0 + 2 + FREERTOS_ROOT/FreeRTOS/Demo/Common/ethernet/lwip-1.4.0 + + + + + 1405340171891 + src/FreeRTOS_Source/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-GCC + + + + 1405340171901 + src/FreeRTOS_Source/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-MemMang + + + + 1405340618192 + src/Full_Demo/Standard-Demo-Tasks + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-Minimal + + + + 1405340618202 + src/Full_Demo/Standard-Demo-Tasks + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-include + + + + 1405340618202 + src/Full_Demo/Standard-Demo-Tasks + 22 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-alt*.* + + + + 1405340618212 + src/Full_Demo/Standard-Demo-Tasks + 22 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-cr*.* + + + + 1405340618212 + src/Full_Demo/Standard-Demo-Tasks + 22 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-sp*.* + + + + 1405340618212 + src/Full_Demo/Standard-Demo-Tasks + 22 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-intq*.* + + + + 1405340618222 + src/Full_Demo/Standard-Demo-Tasks + 22 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-*strings*.* + + + + 1405340618222 + src/Full_Demo/Standard-Demo-Tasks + 22 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-copy*.* + + + + 1405341622717 + src/lwIP_Demo/lwip-1.4.0 + 10 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-ports + + + + 1405340232557 + src/FreeRTOS_Source/portable/GCC + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-ARM_CA9 + + + + 1405340216963 + src/FreeRTOS_Source/portable/MemMang + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-heap_4.c + + + + 1405341154152 + src/lwIP_Demo/lwip-1.4.0/src/core + 10 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-ipv6 + + + + 1405341154162 + src/lwIP_Demo/lwip-1.4.0/src/core + 10 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-snmp + + + + 1405341173635 + src/lwIP_Demo/lwip-1.4.0/src/netif + 10 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-ppp + + + + + + FREERTOS_ROOT + $%7BPARENT-4-PROJECT_LOC%7D + + + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Blinky_Demo/main_blinky.c new file mode 100644 index 000000000..2b4d9209d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Blinky_Demo/main_blinky.c @@ -0,0 +1,226 @@ +/* + FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides three demo applications. A simple blinky + * style project, a more comprehensive test and demo application, and an + * lwIP example. The mainSELECTED_APPLICATION setting in main.c is used to + * select between the three. See the notes on using mainSELECTED_APPLICATION + * in main.c. This file implements the simply blinky style version. + * + * NOTE 2: This file only contains the source code that is specific to the + * basic demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware are defined in main.c. + ****************************************************************************** + * + * main_blinky() creates one queue, and two tasks. It then starts the + * scheduler. + * + * The Queue Send Task: + * The queue send task is implemented by the prvQueueSendTask() function in + * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly + * block for 200 milliseconds, before sending the value 100 to the queue that + * was created within main_blinky(). Once the value is sent, the task loops + * back around to block for another 200 milliseconds...and so on. + * + * The Queue Receive Task: + * The queue receive task is implemented by the prvQueueReceiveTask() function + * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly + * blocks on attempts to read data from the queue that was created within + * main_blinky(). When data is received, the task checks the value of the + * data, and if the value equals the expected 100, toggles an LED. The 'block + * time' parameter passed to the queue receive function specifies that the + * task should be held in the Blocked state indefinitely to wait for data to + * be available on the queue. The queue receive task will only leave the + * Blocked state when the queue send task writes to the queue. As the queue + * send task writes to the queue every 200 milliseconds, the queue receive + * task leaves the Blocked state every 200 milliseconds, and therefore toggles + * the LED every 200 milliseconds. + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Standard demo includes. */ +#include "partest.h" + +/* Priorities at which the tasks are created. */ +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The rate at which data is sent to the queue. The 200ms value is converted +to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) + +/* The number of items the queue can hold. This is 1 as the receive task +will remove items as they are added, meaning the send task should always find +the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) + +/* The LED toggled by the Rx task. */ +#define mainTASK_LED ( 0 ) + +/*-----------------------------------------------------------*/ + +/* + * The tasks as described in the comments at the top of this file. + */ +static void prvQueueReceiveTask( void *pvParameters ); +static void prvQueueSendTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The queue used by both tasks. */ +static QueueHandle_t xQueue = NULL; + +/*-----------------------------------------------------------*/ + +void main_blinky( void ) +{ + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + NULL, /* The parameter passed to the task - not used in this case. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ + + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was either insufficient FreeRTOS heap memory available for the idle + and/or timer tasks to be created, or vTaskStartScheduler() was called from + User mode. See the memory management section on the FreeRTOS web site for + more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + mode from which main() is called is set in the C start up code and must be + a privileged mode (not user mode). */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvQueueSendTask( void *pvParameters ) +{ +TickType_t xNextWakeTime; +const unsigned long ulValueToSend = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Place this task in the blocked state until it is time to run again. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + toggle the LED. 0 is used as the block time so the sending operation + will not block - it shouldn't need to block as the queue should always + be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } +} +/*-----------------------------------------------------------*/ + +static void prvQueueReceiveTask( void *pvParameters ) +{ +unsigned long ulReceivedValue; +const unsigned long ulExpectedValue = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + for( ;; ) + { + /* Wait until something arrives in the queue - this task will block + indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + is it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == ulExpectedValue ) + { + vParTestToggleLED( mainTASK_LED ); + ulReceivedValue = 0U; + } + } +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/FreeRTOSConfig.h new file mode 100644 index 000000000..9bcfed81d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/FreeRTOSConfig.h @@ -0,0 +1,243 @@ +/* + FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include "xparameters.h" + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +/* + * The FreeRTOS Cortex-A port implements a full interrupt nesting model. + * + * Interrupts that are assigned a priority at or below + * configMAX_API_CALL_INTERRUPT_PRIORITY (which counter-intuitively in the ARM + * generic interrupt controller [GIC] means a priority that has a numerical + * value above configMAX_API_CALL_INTERRUPT_PRIORITY) can call FreeRTOS safe API + * functions and will nest. + * + * Interrupts that are assigned a priority above + * configMAX_API_CALL_INTERRUPT_PRIORITY (which in the GIC means a numerical + * value below configMAX_API_CALL_INTERRUPT_PRIORITY) cannot call any FreeRTOS + * API functions, will nest, and will not be masked by FreeRTOS critical + * sections (although it is necessary for interrupts to be globally disabled + * extremely briefly as the interrupt mask is updated in the GIC). + * + * FreeRTOS functions that can be called from an interrupt are those that end in + * "FromISR". FreeRTOS maintains a separate interrupt safe API to enable + * interrupt entry to be shorter, faster, simpler and smaller. + * + * The Zynq implements 256 unique interrupt priorities. For the purpose of + * setting configMAX_API_CALL_INTERRUPT_PRIORITY 255 represents the lowest + * priority. + */ +#define configMAX_API_CALL_INTERRUPT_PRIORITY 18 + + +#define configCPU_CLOCK_HZ 100000000UL +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) +#define configPERIPHERAL_CLOCK_HZ ( 33333000UL ) +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 1 +#define configMAX_PRIORITIES ( 7 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 200 ) +#define configTOTAL_HEAP_SIZE ( 80 * 1024 ) +#define configMAX_TASK_NAME_LEN ( 10 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 8 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_QUEUE_SETS 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_eTaskGetState 1 + +/* This demo makes use of one or more example stats formatting functions. These +format the raw data provided by the uxTaskGetSystemState() function in to human +readable ASCII form. See the notes in the implementation of vTaskList() within +FreeRTOS/Source/tasks.c for limitations. */ +#define configUSE_STATS_FORMATTING_FUNCTIONS 1 + +/* The private watchdog is used to generate run time stats. */ +#include "xscuwdt.h" +extern XScuWdt xWatchDogInstance; +extern void vInitialiseTimerForRunTimeStats( void ); +#define configGENERATE_RUN_TIME_STATS 1 +#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vInitialiseTimerForRunTimeStats() +#define portGET_RUN_TIME_COUNTER_VALUE() ( ( 0xffffffffUL - XScuWdt_ReadReg( xWatchDogInstance.Config.BaseAddr, XSCUWDT_COUNTER_OFFSET ) ) >> 1 ) + +/* The size of the global output buffer that is available for use when there +are multiple command interpreters running at once (for example, one on a UART +and one on TCP/IP). This is done to prevent an output buffer being defined by +each implementation - which would waste RAM. In this case, there is only one +command interpreter running. */ +#define configCOMMAND_INT_MAX_OUTPUT_SIZE 2096 + +/* Normal assert() semantics without relying on the provision of an assert.h +header file. */ +void vAssertCalled( const char * pcFile, unsigned long ulLine ); +#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled( __FILE__, __LINE__ ); + + + +/****** Hardware specific settings. *******************************************/ + +/* + * The application must provide a function that configures a peripheral to + * create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT() + * in FreeRTOSConfig.h to call the function. This file contains a function + * that is suitable for use on the Zynq MPU. FreeRTOS_Tick_Handler() must + * be installed as the peripheral's interrupt handler. + */ +void vConfigureTickInterrupt( void ); +#define configSETUP_TICK_INTERRUPT() vConfigureTickInterrupt() + +void vClearTickInterrupt( void ); +#define configCLEAR_TICK_INTERRUPT() vClearTickInterrupt() + +/* The following constant describe the hardware, and are correct for the +Zynq MPU. */ +#define configINTERRUPT_CONTROLLER_BASE_ADDRESS ( XPAR_PS7_SCUGIC_0_DIST_BASEADDR ) +#define configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ( -0xf00 ) +#define configUNIQUE_INTERRUPT_PRIORITIES 32 + + + +/****** Network configuration settings - only used when the lwIP example is +built. See the page that documents this demo on the http://www.FreeRTOS.org +website for more information. ***********************************************/ + +/* The priority for the task that unblocked by the MAC interrupt to process +received packets. */ +#define configMAC_INPUT_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) + +/* The priority of the task that runs the lwIP stack. */ +#define configLWIP_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) + +/* The priority of the task that uses lwIP sockets to provide a simple command +line interface. */ +#define configCLI_TASK_PRIORITY ( tskIDLE_PRIORITY ) + +/* MAC address configuration. */ +#define configMAC_ADDR0 0x00 +#define configMAC_ADDR1 0x13 +#define configMAC_ADDR2 0x14 +#define configMAC_ADDR3 0x15 +#define configMAC_ADDR4 0x15 +#define configMAC_ADDR5 0x16 + +/* IP address configuration. */ +#define configIP_ADDR0 172 +#define configIP_ADDR1 25 +#define configIP_ADDR2 218 +#define configIP_ADDR3 200 + +/* Netmask configuration. */ +#define configNET_MASK0 255 +#define configNET_MASK1 255 +#define configNET_MASK2 255 +#define configNET_MASK3 0 + +#endif /* FREERTOS_CONFIG_H */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/FreeRTOS_asm_vectors.S b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/FreeRTOS_asm_vectors.S new file mode 100644 index 000000000..f46de6e28 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/FreeRTOS_asm_vectors.S @@ -0,0 +1,144 @@ +/****************************************************************************** +* +* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file asm_vectors.s +* +* This file contains the initial vector table for the Cortex A9 processor +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 10/20/09 Initial version
+* 3.05a sdm	02/02/12 Save lr when profiling is enabled
+* 3.10a srt     04/18/13 Implemented ARM Erratas. Please refer to file
+*			 'xil_errata.h' for errata description
+*
+* +* @note +* +* None. +* +******************************************************************************/ + +#include "xil_errata.h" + +.org 0 +.text +.arm + +.global _boot +.global _freertos_vector_table + +.global FIQInterrupt +.global DataAbortInterrupt +.global PrefetchAbortInterrupt +.global vPortInstallFreeRTOSVectorTable + +.extern FreeRTOS_IRQ_Handler +.extern FreeRTOS_SWI_Handler + +.section .freertos_vectors +_freertos_vector_table: + B _boot + B FreeRTOS_Undefined + ldr pc, _swi + B FreeRTOS_PrefetchAbortHandler + B FreeRTOS_DataAbortHandler + NOP /* Placeholder for address exception vector*/ + LDR PC, _irq + B FreeRTOS_FIQHandler + +_irq: .word FreeRTOS_IRQ_Handler +_swi: .word FreeRTOS_SWI_Handler + + +.align 4 +FreeRTOS_FIQHandler: /* FIQ vector handler */ + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ +FIQLoop: + blx FIQInterrupt /* FIQ vector */ + ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ + subs pc, lr, #4 /* adjust return */ + +.align 4 +FreeRTOS_Undefined: /* Undefined handler */ + b . + +.align 4 +FreeRTOS_DataAbortHandler: /* Data Abort handler */ +#ifdef CONFIG_ARM_ERRATA_775420 + dsb +#endif + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ + blx DataAbortInterrupt /*DataAbortInterrupt :call C function here */ + ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ + subs pc, lr, #4 /* adjust return */ + +.align 4 +FreeRTOS_PrefetchAbortHandler: /* Prefetch Abort handler */ +#ifdef CONFIG_ARM_ERRATA_775420 + dsb +#endif + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ + blx PrefetchAbortInterrupt /* PrefetchAbortInterrupt: call C function here */ + ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ + subs pc, lr, #4 /* adjust return */ + +.align 4 +.type vPortInstallFreeRTOSVectorTable, %function +vPortInstallFreeRTOSVectorTable: + + /* Set VBAR to the vector table that contains the FreeRTOS handlers. */ + ldr r0, =_freertos_vector_table + mcr p15, 0, r0, c12, c0, 0 + dsb + isb + bx lr + + +.end + + + + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/FreeRTOS_tick_config.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/FreeRTOS_tick_config.c new file mode 100644 index 000000000..d2794ee22 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/FreeRTOS_tick_config.c @@ -0,0 +1,165 @@ +/* + FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "Task.h" + +/* Xilinx includes. */ +#include "xscutimer.h" +#include "xscugic.h" + +#define XSCUTIMER_CLOCK_HZ ( XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ / 2UL ) + +static XScuTimer xTimer; + +/* + * The application must provide a function that configures a peripheral to + * create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT() + * in FreeRTOSConfig.h to call the function. This file contains a function + * that is suitable for use on the Zynq SoC. + */ +void vConfigureTickInterrupt( void ) +{ +static XScuGic xInterruptController; /* Interrupt controller instance */ +BaseType_t xStatus; +extern void FreeRTOS_Tick_Handler( void ); +XScuTimer_Config *pxTimerConfig; +XScuGic_Config *pxGICConfig; +const uint8_t ucRisingEdge = 3; + + /* This function is called with the IRQ interrupt disabled, and the IRQ + interrupt should be left disabled. It is enabled automatically when the + scheduler is started. */ + + /* Ensure XScuGic_CfgInitialize() has been called. In this demo it has + already been called from prvSetupHardware() in main(). */ + pxGICConfig = XScuGic_LookupConfig( XPAR_SCUGIC_SINGLE_DEVICE_ID ); + xStatus = XScuGic_CfgInitialize( &xInterruptController, pxGICConfig, pxGICConfig->CpuBaseAddress ); + configASSERT( xStatus == XST_SUCCESS ); + ( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */ + + /* The priority must be the lowest possible. */ + XScuGic_SetPriorityTriggerType( &xInterruptController, XPAR_SCUTIMER_INTR, portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT, ucRisingEdge ); + + /* Install the FreeRTOS tick handler. */ + xStatus = XScuGic_Connect( &xInterruptController, XPAR_SCUTIMER_INTR, (Xil_ExceptionHandler) FreeRTOS_Tick_Handler, ( void * ) &xTimer ); + configASSERT( xStatus == XST_SUCCESS ); + ( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */ + + /* Initialise the timer. */ + pxTimerConfig = XScuTimer_LookupConfig( XPAR_SCUTIMER_DEVICE_ID ); + xStatus = XScuTimer_CfgInitialize( &xTimer, pxTimerConfig, pxTimerConfig->BaseAddr ); + configASSERT( xStatus == XST_SUCCESS ); + ( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */ + + /* Enable Auto reload mode. */ + XScuTimer_EnableAutoReload( &xTimer ); + + /* Load the timer counter register. */ + XScuTimer_LoadTimer( &xTimer, XSCUTIMER_CLOCK_HZ / configTICK_RATE_HZ ); + + /* Start the timer counter and then wait for it to timeout a number of + times. */ + XScuTimer_Start( &xTimer ); + + /* Enable the interrupt for the xTimer in the interrupt controller. */ + XScuGic_Enable( &xInterruptController, XPAR_SCUTIMER_INTR ); + + /* Enable the interrupt in the xTimer itself. */ + vClearTickInterrupt(); + XScuTimer_EnableInterrupt( &xTimer ); +} +/*-----------------------------------------------------------*/ + +void vClearTickInterrupt( void ) +{ + XScuTimer_ClearInterruptStatus( &xTimer ); +} +/*-----------------------------------------------------------*/ + +void vApplicationIRQHandler( uint32_t ulICCIAR ) +{ +extern const XScuGic_Config XScuGic_ConfigTable[]; +static const XScuGic_VectorTableEntry *pxVectorTable = XScuGic_ConfigTable[ XPAR_SCUGIC_SINGLE_DEVICE_ID ].HandlerTable; +uint32_t ulInterruptID; +const XScuGic_VectorTableEntry *pxVectorEntry; + + /* Re-enable interrupts. */ + __asm ( "cpsie i" ); + + /* The ID of the interrupt is obtained by bitwise anding the ICCIAR value + with 0x3FF. */ + ulInterruptID = ulICCIAR & 0x3FFUL; + if( ulInterruptID < XSCUGIC_MAX_NUM_INTR_INPUTS ) + { + /* Call the function installed in the array of installed handler functions. */ + pxVectorEntry = &( pxVectorTable[ ulInterruptID ] ); + pxVectorEntry->Handler( pxVectorEntry->CallBackRef ); + } +} + + + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/IntQueueTimer.c new file mode 100644 index 000000000..c03fd942a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/IntQueueTimer.c @@ -0,0 +1,261 @@ +/* + FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * This file initialises three timers as follows: + * + * Timer 0 and Timer 1 provide the interrupts that are used with the IntQ + * standard demo tasks, which test interrupt nesting and using queues from + * interrupts. Both these interrupts operate below the maximum syscall + * interrupt priority. + * + * Timer 2 is a much higher frequency timer that tests the nesting of interrupts + * that execute above the maximum syscall interrupt priority. + * + * All the timers can nest with the tick interrupt - creating a maximum + * interrupt nesting depth of 4. + * + * For convenience, the high frequency timer is also used to provide the time + * base for the run time stats. + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Demo includes. */ +#include "IntQueueTimer.h" +#include "IntQueue.h" + +/* Xilinx includes. */ +#include "xttcps.h" +#include "xscugic.h" + +/* The frequencies at which the first two timers expire are slightly offset to +ensure they don't remain synchronised. The frequency of the interrupt that +operates above the max syscall interrupt priority is 10 times faster so really +hammers the interrupt entry and exit code. */ +#define tmrTIMERS_USED 3 +#define tmrTIMER_0_FREQUENCY ( 2000UL ) +#define tmrTIMER_1_FREQUENCY ( 2001UL ) +#define tmrTIMER_2_FREQUENCY ( 20000UL ) + +/*-----------------------------------------------------------*/ + +/* + * The single interrupt service routines that is used to service all three + * timers. + */ +static void prvTimerHandler( void *CallBackRef ); + +/*-----------------------------------------------------------*/ + +/* Hardware constants. */ +static const BaseType_t xDeviceIDs[ tmrTIMERS_USED ] = { XPAR_XTTCPS_0_DEVICE_ID, XPAR_XTTCPS_1_DEVICE_ID, XPAR_XTTCPS_2_DEVICE_ID }; +static const BaseType_t xInterruptIDs[ tmrTIMERS_USED ] = { XPAR_XTTCPS_0_INTR, XPAR_XTTCPS_1_INTR, XPAR_XTTCPS_2_INTR }; + +/* Timer configuration settings. */ +typedef struct +{ + uint32_t OutputHz; /* Output frequency. */ + uint16_t Interval; /* Interval value. */ + uint8_t Prescaler; /* Prescaler value. */ + uint16_t Options; /* Option settings. */ +} TmrCntrSetup; + +static TmrCntrSetup xTimerSettings[ tmrTIMERS_USED ] = +{ + { tmrTIMER_0_FREQUENCY, 0, 0, XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE }, + { tmrTIMER_1_FREQUENCY, 0, 0, XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE }, + { tmrTIMER_2_FREQUENCY, 0, 0, XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE } +}; + +/* Lower priority number means higher logical priority, so +configMAX_API_CALL_INTERRUPT_PRIORITY - 1 is above the maximum system call +interrupt priority. */ +static const UBaseType_t uxInterruptPriorities[ tmrTIMERS_USED ] = +{ + configMAX_API_CALL_INTERRUPT_PRIORITY + 1, + configMAX_API_CALL_INTERRUPT_PRIORITY, + configMAX_API_CALL_INTERRUPT_PRIORITY - 1 +}; + +static XTtcPs xTimerInstances[ tmrTIMERS_USED ]; + +/* Used to provide a means of ensuring the intended interrupt nesting depth is +actually being reached. */ +extern uint32_t ulPortInterruptNesting; +static uint32_t ulMaxRecordedNesting = 0; + +/* Used to ensure the high frequency timer is running at the expected +frequency. */ +static volatile uint32_t ulHighFrequencyTimerCounts = 0; + +/*-----------------------------------------------------------*/ + +void vInitialiseTimerForIntQueueTest( void ) +{ +BaseType_t xStatus; +TmrCntrSetup *pxTimerSettings; +extern XScuGic xInterruptController; +BaseType_t xTimer; +XTtcPs *pxTimerInstance; +XTtcPs_Config *pxTimerConfiguration; +const uint8_t ucRisingEdge = 3; + + for( xTimer = 0; xTimer < tmrTIMERS_USED; xTimer++ ) + { + /* Look up the timer's configuration. */ + pxTimerInstance = &( xTimerInstances[ xTimer ] ); + pxTimerConfiguration = XTtcPs_LookupConfig( xDeviceIDs[ xTimer ] ); + configASSERT( pxTimerConfiguration ); + + pxTimerSettings = &( xTimerSettings[ xTimer ] ); + + /* Initialise the device. */ + xStatus = XTtcPs_CfgInitialize( pxTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress ); + if( xStatus != XST_SUCCESS ) + { + /* Not sure how to do this before XTtcPs_CfgInitialize is called + as pxTimerInstance is set within XTtcPs_CfgInitialize(). */ + XTtcPs_Stop( pxTimerInstance ); + xStatus = XTtcPs_CfgInitialize( pxTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress ); + configASSERT( xStatus == XST_SUCCESS ); + } + + /* Set the options. */ + XTtcPs_SetOptions( pxTimerInstance, pxTimerSettings->Options ); + + /* The timer frequency is preset in the pxTimerSettings structure. + Derive the values for the other structure members. */ + XTtcPs_CalcIntervalFromFreq( pxTimerInstance, pxTimerSettings->OutputHz, &( pxTimerSettings->Interval ), &( pxTimerSettings->Prescaler ) ); + + /* Set the interval and prescale. */ + XTtcPs_SetInterval( pxTimerInstance, pxTimerSettings->Interval ); + XTtcPs_SetPrescaler( pxTimerInstance, pxTimerSettings->Prescaler ); + + /* The priority must be the lowest possible. */ + XScuGic_SetPriorityTriggerType( &xInterruptController, xInterruptIDs[ xTimer ], uxInterruptPriorities[ xTimer ] << portPRIORITY_SHIFT, ucRisingEdge ); + + /* Connect to the interrupt controller. */ + xStatus = XScuGic_Connect( &xInterruptController, xInterruptIDs[ xTimer ], ( Xil_InterruptHandler ) prvTimerHandler, ( void * ) pxTimerInstance ); + configASSERT( xStatus == XST_SUCCESS); + + /* Enable the interrupt in the GIC. */ + XScuGic_Enable( &xInterruptController, xInterruptIDs[ xTimer ] ); + + /* Enable the interrupts in the timer. */ + XTtcPs_EnableInterrupts( pxTimerInstance, XTTCPS_IXR_INTERVAL_MASK ); + + /* Start the timer. */ + XTtcPs_Start( pxTimerInstance ); + } +} +/*-----------------------------------------------------------*/ + +static void prvTimerHandler( void *pvCallBackRef ) +{ +uint32_t ulInterruptStatus; +XTtcPs *pxTimer = ( XTtcPs * ) pvCallBackRef; +BaseType_t xYieldRequired; + + /* Read the interrupt status, then write it back to clear the interrupt. */ + ulInterruptStatus = XTtcPs_GetInterruptStatus( pxTimer ); + XTtcPs_ClearInterruptStatus( pxTimer, ulInterruptStatus ); + + /* Only one interrupt event type is expected. */ + configASSERT( ( XTTCPS_IXR_INTERVAL_MASK & ulInterruptStatus ) != 0 ); + + /* Check the device ID to know which IntQueue demo to call. */ + if( pxTimer->Config.DeviceId == xDeviceIDs[ 0 ] ) + { + xYieldRequired = xFirstTimerHandler(); + } + else if( pxTimer->Config.DeviceId == xDeviceIDs[ 1 ] ) + { + xYieldRequired = xSecondTimerHandler(); + } + else + { + /* Used to check the timer is running at the expected frequency. */ + ulHighFrequencyTimerCounts++; + + /* Latch the highest interrupt nesting count detected. */ + if( ulPortInterruptNesting > ulMaxRecordedNesting ) + { + ulMaxRecordedNesting = ulPortInterruptNesting; + } + + xYieldRequired = pdFALSE; + } + + /* If xYieldRequired is not pdFALSE then calling either xFirstTimerHandler() + or xSecondTimerHandler() resulted in a task leaving the blocked state and + the task that left the blocked state had a priority higher than the currently + running task (the task this interrupt interrupted) - so a context switch + should be performed so the interrupt returns directly to the higher priority + task. xYieldRequired is tested inside the following macro. */ + portYIELD_FROM_ISR( xYieldRequired ); +} + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/IntQueueTimer.h new file mode 100644 index 000000000..931d27322 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/IntQueueTimer.h @@ -0,0 +1,74 @@ +/* + FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef INT_QUEUE_TIMER_H +#define INT_QUEUE_TIMER_H + +void vInitialiseTimerForIntQueueTest( void ); +portBASE_TYPE xTimer0Handler( void ); +portBASE_TYPE xTimer1Handler( void ); + +#endif + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/main_full.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/main_full.c new file mode 100644 index 000000000..d940ff719 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/main_full.c @@ -0,0 +1,504 @@ +/* + FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides three demo applications. A simple blinky + * style project, a more comprehensive test and demo application, and an + * lwIP example. The mainSELECTED_APPLICATION setting in main.c is used to + * select between the three. See the notes on using mainSELECTED_APPLICATION + * in main.c. This file implements the simply blinky style version. + * + * NOTE 2: This file only contains the source code that is specific to the + * full demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware, are defined in main.c. + * + * NOTE 3: The full demo includes a test that checks the floating point context + * is maintained correctly across task switches. The standard GCC libraries can + * use floating point registers and made this test fail (unless the tasks that + * use the library are given a floating point context as described on the + * documentation page for this demo). printf-stdarg.c is included in this + * project to prevent the standard GCC libraries being linked into the project. + * + ****************************************************************************** + * + * main_full() creates all the demo application tasks and software timers, then + * starts the scheduler. The web documentation provides more details of the + * standard demo application tasks, which provide no particular functionality, + * but do provide a good example of how to use the FreeRTOS API. + * + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * FreeRTOS+CLI command console. The command console is access through the + * UART to USB connector on the ZC702 Zynq development board (marked J2). For + * reasons of robustness testing the UART driver is deliberately written to be + * inefficient and should not be used as a template for a production driver. + * Type "help" to see a list of registered commands. The FreeRTOS+CLI license + * is different to the FreeRTOS license, see http://www.FreeRTOS.org/cli for + * license and usage details. The default baud rate is 115200. + * + * "Reg test" tasks - These fill both the core and floating point registers with + * known values, then check that each register maintains its expected value for + * the lifetime of the task. Each task uses a different set of values. The reg + * test tasks execute with a very low priority, so get preempted very + * frequently. A register containing an unexpected value is indicative of an + * error in the context switching mechanism. + * + * "Check" task - The check task period is initially set to three seconds. The + * task checks that all the standard demo tasks, and the register check tasks, + * are not only still executing, but are executing without reporting any errors. + * If the check task discovers that a task has either stalled, or reported an + * error, then it changes its own execution period from the initial three + * seconds, to just 200ms. The check task also toggles an LED each time it is + * called. This provides a visual indication of the system status: If the LED + * toggles every three seconds, then no issues have been discovered. If the LED + * toggles every 200ms, then an issue has been discovered with at least one + * task. + */ + +/* Standard includes. */ +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "semphr.h" + +/* Standard demo application includes. */ +#include "flop.h" +#include "semtest.h" +#include "dynamic.h" +#include "BlockQ.h" +#include "blocktim.h" +#include "countsem.h" +#include "GenQTest.h" +#include "recmutex.h" +#include "death.h" +#include "partest.h" +#include "comtest2.h" +#include "serial.h" +#include "TimerDemo.h" +#include "QueueOverwrite.h" +#include "IntQueue.h" +#include "EventGroupsDemo.h" + +/* Priorities for the demo application tasks. */ +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) +#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3UL ) +#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY ) + +/* The priority used by the UART command console task. */ +#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) + +/* The LED used by the check timer. */ +#define mainCHECK_LED ( 0 ) + +/* A block time of zero simply means "don't block". */ +#define mainDONT_BLOCK ( 0UL ) + +/* The period after which the check timer will expire, in ms, provided no errors +have been reported by any of the standard demo tasks. ms are converted to the +equivalent in ticks using the portTICK_PERIOD_MS constant. */ +#define mainNO_ERROR_CHECK_TASK_PERIOD ( 3000UL / portTICK_PERIOD_MS ) + +/* The period at which the check timer will expire, in ms, if an error has been +reported in one of the standard demo tasks. ms are converted to the equivalent +in ticks using the portTICK_PERIOD_MS constant. */ +#define mainERROR_CHECK_TASK_PERIOD ( 200UL / portTICK_PERIOD_MS ) + +/* Parameters that are passed into the register check tasks solely for the +purpose of ensuring parameters are passed into tasks correctly. */ +#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 ) +#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 ) + +/* The base period used by the timer test tasks. */ +#define mainTIMER_TEST_PERIOD ( 50 ) + +/*-----------------------------------------------------------*/ + + +/* + * The check task, as described at the top of this file. + */ +static void prvCheckTask( void *pvParameters ); + +/* + * Register check tasks, and the tasks used to write over and check the contents + * of the FPU registers, as described at the top of this file. The nature of + * these files necessitates that they are written in an assembly file, but the + * entry points are kept in the C file for the convenience of checking the task + * parameter. + */ +static void prvRegTestTaskEntry1( void *pvParameters ); +extern void vRegTest1Implementation( void ); +static void prvRegTestTaskEntry2( void *pvParameters ); +extern void vRegTest2Implementation( void ); + +/* + * Register commands that can be used with FreeRTOS+CLI. The commands are + * defined in CLI-Commands.c and File-Related-CLI-Command.c respectively. + */ +extern void vRegisterSampleCLICommands( void ); + +/* + * The task that manages the FreeRTOS+CLI input and output. + */ +extern void vUARTCommandConsoleStart( uint16_t usStackSize, UBaseType_t uxPriority ); + +/* + * A high priority task that does nothing other than execute at a pseudo random + * time to ensure the other test tasks don't just execute in a repeating + * pattern. + */ +static void prvPseudoRandomiser( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The following two variables are used to communicate the status of the +register check tasks to the check task. If the variables keep incrementing, +then the register check tasks has not discovered any errors. If a variable +stops incrementing, then an error has been found. */ +volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; + +/* String for display in the web server. It is set to an error message if the +check task detects an error. */ +char *pcStatusMessage = "All tasks running without error"; +/*-----------------------------------------------------------*/ + +void main_full( void ) +{ + /* Start all the other standard demo/test tasks. They have not particular + functionality, but do demonstrate how to use the FreeRTOS API and test the + kernel port. */ + vStartInterruptQueueTasks(); + vStartDynamicPriorityTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vCreateBlockTimeTasks(); + vStartCountingSemaphoreTasks(); + vStartGenericQueueTasks( tskIDLE_PRIORITY ); + vStartRecursiveMutexTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartMathTasks( mainFLOP_TASK_PRIORITY ); + vStartTimerDemoTask( mainTIMER_TEST_PERIOD ); + vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY ); + vStartEventGroupTasks(); + + /* Start the tasks that implements the command console on the UART, as + described above. */ + vUARTCommandConsoleStart( mainUART_COMMAND_CONSOLE_STACK_SIZE, mainUART_COMMAND_CONSOLE_TASK_PRIORITY ); + + /* Register the standard CLI commands. */ + vRegisterSampleCLICommands(); + + /* Create the register check tasks, as described at the top of this file */ + xTaskCreate( prvRegTestTaskEntry1, "Reg1", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_1_PARAMETER, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvRegTestTaskEntry2, "Reg2", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL ); + + /* Create the task that just adds a little random behaviour. */ + xTaskCreate( prvPseudoRandomiser, "Rnd", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL ); + + /* Create the task that performs the 'check' functionality, as described at + the top of this file. */ + xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* The set of tasks created by the following function call have to be + created last as they keep account of the number of tasks they expect to see + running. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was either insufficient FreeRTOS heap memory available for the idle + and/or timer tasks to be created, or vTaskStartScheduler() was called from + User mode. See the memory management section on the FreeRTOS web site for + more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + mode from which main() is called is set in the C start up code and must be + a privileged mode (not user mode). */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvCheckTask( void *pvParameters ) +{ +TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD; +TickType_t xLastExecutionTime; +static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; +unsigned long ulErrorFound = pdFALSE; + + /* Just to stop compiler warnings. */ + ( void ) pvParameters; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. The onboard LED is toggled on each iteration. + If an error is detected then the delay period is decreased from + mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the + effect of increasing the rate at which the onboard LED toggles, and in so + doing gives visual feedback of the system status. */ + for( ;; ) + { + /* Delay until it is time to execute again. */ + vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod ); + + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none have detected an error. */ + if( xAreIntQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if ( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xAreTimerDemoTasksStillRunning( ( TickType_t ) mainNO_ERROR_CHECK_TASK_PERIOD ) != pdPASS ) + { + ulErrorFound = pdTRUE; + } + + if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xIsQueueOverwriteTaskStillRunning() != pdPASS ) + { + ulErrorFound = pdTRUE; + } + + if( xAreEventGroupTasksStillRunning() != pdPASS ) + { + ulErrorFound = pdTRUE; + } + + /* Check that the register test 1 task is still running. */ + if( ulLastRegTest1Value == ulRegTest1LoopCounter ) + { + ulErrorFound = pdTRUE; + } + ulLastRegTest1Value = ulRegTest1LoopCounter; + + /* Check that the register test 2 task is still running. */ + if( ulLastRegTest2Value == ulRegTest2LoopCounter ) + { + ulErrorFound = pdTRUE; + } + ulLastRegTest2Value = ulRegTest2LoopCounter; + + /* Toggle the check LED to give an indication of the system status. If + the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then + everything is ok. A faster toggle indicates an error. */ + vParTestToggleLED( mainCHECK_LED ); + + if( ulErrorFound != pdFALSE ) + { + /* An error has been detected in one of the tasks - flash the LED + at a higher frequency to give visible feedback that something has + gone wrong (it might just be that the loop back connector required + by the comtest tasks has not been fitted). */ + xDelayPeriod = mainERROR_CHECK_TASK_PERIOD; + pcStatusMessage = "Error found in at least one task."; + } + } +} +/*-----------------------------------------------------------*/ + +char *pcMainGetTaskStatusMessage( void ) +{ + return pcStatusMessage; +} +/*-----------------------------------------------------------*/ + +static void prvRegTestTaskEntry1( void *pvParameters ) +{ + /* Although the regtest task is written in assembler, its entry point is + written in C for convenience of checking the task parameter is being passed + in correctly. */ + if( pvParameters == mainREG_TEST_TASK_1_PARAMETER ) + { + /* The reg test task also tests the floating point registers. Tasks + that use the floating point unit must call vPortTaskUsesFPU() before + any floating point instructions are executed. */ + vPortTaskUsesFPU(); + + /* Start the part of the test that is written in assembler. */ + vRegTest1Implementation(); + } + + /* The following line will only execute if the task parameter is found to + be incorrect. The check timer will detect that the regtest loop counter is + not being incremented and flag an error. */ + vTaskDelete( NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvRegTestTaskEntry2( void *pvParameters ) +{ + /* Although the regtest task is written in assembler, its entry point is + written in C for convenience of checking the task parameter is being passed + in correctly. */ + if( pvParameters == mainREG_TEST_TASK_2_PARAMETER ) + { + /* The reg test task also tests the floating point registers. Tasks + that use the floating point unit must call vPortTaskUsesFPU() before + any floating point instructions are executed. */ + vPortTaskUsesFPU(); + + /* Start the part of the test that is written in assembler. */ + vRegTest2Implementation(); + } + + /* The following line will only execute if the task parameter is found to + be incorrect. The check timer will detect that the regtest loop counter is + not being incremented and flag an error. */ + vTaskDelete( NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvPseudoRandomiser( void *pvParameters ) +{ +const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL, ulMinDelay = ( 35 / portTICK_PERIOD_MS ); +volatile uint32_t ulNextRand = ( uint32_t ) &pvParameters, ulValue; + + /* This task does nothing other than ensure there is a little bit of + disruption in the scheduling pattern of the other tasks. Normally this is + done by generating interrupts at pseudo random times. */ + for( ;; ) + { + ulNextRand = ( ulMultiplier * ulNextRand ) + ulIncrement; + ulValue = ( ulNextRand >> 16UL ) & 0xffUL; + + if( ulValue < ulMinDelay ) + { + ulValue = ulMinDelay; + } + + vTaskDelay( ulValue ); + + while( ulValue > 0 ) + { + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + + ulValue--; + } + } +} + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/reg_test.S b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/reg_test.S new file mode 100644 index 000000000..20c4de57f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/reg_test.S @@ -0,0 +1,658 @@ +/* + FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd. + + FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT + http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS tutorial books are available in pdf and paperback. * + * Complete, revised, and edited pdf reference manuals are also * + * available. * + * * + * Purchasing FreeRTOS documentation will not only help you, by * + * ensuring you get running as quickly as possible and with an * + * in-depth knowledge of how to use FreeRTOS, it will also help * + * the FreeRTOS project to continue with its mission of providing * + * professional grade, cross platform, de facto standard solutions * + * for microcontrollers - completely free of charge! * + * * + * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * + * * + * Thank you for using FreeRTOS, and thank you for your support! * + * * + *************************************************************************** + + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + + >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to + distribute a combined work that includes FreeRTOS without being obliged to + provide the source code for proprietary components outside of the FreeRTOS + kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. See the GNU General Public License for more + details. You should have received a copy of the GNU General Public License + and the FreeRTOS license exception along with FreeRTOS; if not itcan be + viewed here: http://www.freertos.org/a00114.html and also obtained by + writing to Real Time Engineers Ltd., contact details for whom are available + on the FreeRTOS WEB site. + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, and our new + fully thread aware and reentrant UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems, who sell the code with commercial support, + indemnification and middleware, under the OpenRTOS brand. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. +*/ + + .global vRegTest1Implementation + .global vRegTest2Implementation + .extern ulRegTest1LoopCounter + .extern ulRegTest2LoopCounter + + .text + .arm + + /* This function is explained in the comments at the top of main-full.c. */ +.type vRegTest1Implementation, %function +vRegTest1Implementation: + + /* Fill each general purpose register with a known value. */ + mov r0, #0xFF + mov r1, #0x11 + mov r2, #0x22 + mov r3, #0x33 + mov r4, #0x44 + mov r5, #0x55 + mov r6, #0x66 + mov r7, #0x77 + mov r8, #0x88 + mov r9, #0x99 + mov r10, #0xAA + mov r11, #0xBB + mov r12, #0xCC + mov r14, #0xEE + + /* Fill each FPU register with a known value. */ + vmov d0, r0, r1 + vmov d1, r2, r3 + vmov d2, r4, r5 + vmov d3, r6, r7 + vmov d4, r8, r9 + vmov d5, r10, r11 + vmov d6, r0, r1 + vmov d7, r2, r3 + vmov d8, r4, r5 + vmov d9, r6, r7 + vmov d10, r8, r9 + vmov d11, r10, r11 + vmov d12, r0, r1 + vmov d13, r2, r3 + vmov d14, r4, r5 + vmov d15, r6, r7 + + vmov d16, r0, r1 + vmov d17, r2, r3 + vmov d18, r4, r5 + vmov d19, r6, r7 + vmov d20, r8, r9 + vmov d21, r10, r11 + vmov d22, r0, r1 + vmov d23, r2, r3 + vmov d24, r4, r5 + vmov d25, r6, r7 + vmov d26, r8, r9 + vmov d27, r10, r11 + vmov d28, r0, r1 + vmov d29, r2, r3 + vmov d30, r4, r5 + vmov d31, r6, r7 + + /* Loop, checking each itteration that each register still contains the + expected value. */ +reg1_loop: + /* Yield to increase test coverage */ + svc 0 + + /* Check all the VFP registers still contain the values set above. + First save registers that are clobbered by the test. */ + push { r0-r1 } + + vmov r0, r1, d0 + cmp r0, #0xFF + bne reg1_error_loopf + cmp r1, #0x11 + bne reg1_error_loopf + vmov r0, r1, d1 + cmp r0, #0x22 + bne reg1_error_loopf + cmp r1, #0x33 + bne reg1_error_loopf + vmov r0, r1, d2 + cmp r0, #0x44 + bne reg1_error_loopf + cmp r1, #0x55 + bne reg1_error_loopf + vmov r0, r1, d3 + cmp r0, #0x66 + bne reg1_error_loopf + cmp r1, #0x77 + bne reg1_error_loopf + vmov r0, r1, d4 + cmp r0, #0x88 + bne reg1_error_loopf + cmp r1, #0x99 + bne reg1_error_loopf + vmov r0, r1, d5 + cmp r0, #0xAA + bne reg1_error_loopf + cmp r1, #0xBB + bne reg1_error_loopf + vmov r0, r1, d6 + cmp r0, #0xFF + bne reg1_error_loopf + cmp r1, #0x11 + bne reg1_error_loopf + vmov r0, r1, d7 + cmp r0, #0x22 + bne reg1_error_loopf + cmp r1, #0x33 + bne reg1_error_loopf + vmov r0, r1, d8 + cmp r0, #0x44 + bne reg1_error_loopf + cmp r1, #0x55 + bne reg1_error_loopf + vmov r0, r1, d9 + cmp r0, #0x66 + bne reg1_error_loopf + cmp r1, #0x77 + bne reg1_error_loopf + vmov r0, r1, d10 + cmp r0, #0x88 + bne reg1_error_loopf + cmp r1, #0x99 + bne reg1_error_loopf + vmov r0, r1, d11 + cmp r0, #0xAA + bne reg1_error_loopf + cmp r1, #0xBB + bne reg1_error_loopf + vmov r0, r1, d12 + cmp r0, #0xFF + bne reg1_error_loopf + cmp r1, #0x11 + bne reg1_error_loopf + vmov r0, r1, d13 + cmp r0, #0x22 + bne reg1_error_loopf + cmp r1, #0x33 + bne reg1_error_loopf + vmov r0, r1, d14 + cmp r0, #0x44 + bne reg1_error_loopf + cmp r1, #0x55 + bne reg1_error_loopf + vmov r0, r1, d15 + cmp r0, #0x66 + bne reg1_error_loopf + cmp r1, #0x77 + bne reg1_error_loopf + + vmov r0, r1, d16 + cmp r0, #0xFF + bne reg1_error_loopf + cmp r1, #0x11 + bne reg1_error_loopf + vmov r0, r1, d17 + cmp r0, #0x22 + bne reg1_error_loopf + cmp r1, #0x33 + bne reg1_error_loopf + vmov r0, r1, d18 + cmp r0, #0x44 + bne reg1_error_loopf + cmp r1, #0x55 + bne reg1_error_loopf + vmov r0, r1, d19 + cmp r0, #0x66 + bne reg1_error_loopf + cmp r1, #0x77 + bne reg1_error_loopf + vmov r0, r1, d20 + cmp r0, #0x88 + bne reg1_error_loopf + cmp r1, #0x99 + bne reg1_error_loopf + vmov r0, r1, d21 + cmp r0, #0xAA + bne reg1_error_loopf + cmp r1, #0xBB + bne reg1_error_loopf + vmov r0, r1, d22 + cmp r0, #0xFF + bne reg1_error_loopf + cmp r1, #0x11 + bne reg1_error_loopf + vmov r0, r1, d23 + cmp r0, #0x22 + bne reg1_error_loopf + cmp r1, #0x33 + bne reg1_error_loopf + vmov r0, r1, d24 + cmp r0, #0x44 + bne reg1_error_loopf + cmp r1, #0x55 + bne reg1_error_loopf + vmov r0, r1, d25 + cmp r0, #0x66 + bne reg1_error_loopf + cmp r1, #0x77 + bne reg1_error_loopf + vmov r0, r1, d26 + cmp r0, #0x88 + bne reg1_error_loopf + cmp r1, #0x99 + bne reg1_error_loopf + vmov r0, r1, d27 + cmp r0, #0xAA + bne reg1_error_loopf + cmp r1, #0xBB + bne reg1_error_loopf + vmov r0, r1, d28 + cmp r0, #0xFF + bne reg1_error_loopf + cmp r1, #0x11 + bne reg1_error_loopf + vmov r0, r1, d29 + cmp r0, #0x22 + bne reg1_error_loopf + cmp r1, #0x33 + bne reg1_error_loopf + vmov r0, r1, d30 + cmp r0, #0x44 + bne reg1_error_loopf + cmp r1, #0x55 + bne reg1_error_loopf + vmov r0, r1, d31 + cmp r0, #0x66 + bne reg1_error_loopf + cmp r1, #0x77 + bne reg1_error_loopf + + /* Restore the registers that were clobbered by the test. */ + pop {r0-r1} + + /* VFP register test passed. Jump to the core register test. */ + b reg1_loopf_pass + +reg1_error_loopf: + /* If this line is hit then a VFP register value was found to be + incorrect. */ + b reg1_error_loopf + +reg1_loopf_pass: + + /* Test each general purpose register to check that it still contains the + expected known value, jumping to reg1_error_loop if any register contains + an unexpected value. */ + cmp r0, #0xFF + bne reg1_error_loop + cmp r1, #0x11 + bne reg1_error_loop + cmp r2, #0x22 + bne reg1_error_loop + cmp r3, #0x33 + bne reg1_error_loop + cmp r4, #0x44 + bne reg1_error_loop + cmp r5, #0x55 + bne reg1_error_loop + cmp r6, #0x66 + bne reg1_error_loop + cmp r7, #0x77 + bne reg1_error_loop + cmp r8, #0x88 + bne reg1_error_loop + cmp r9, #0x99 + bne reg1_error_loop + cmp r10, #0xAA + bne reg1_error_loop + cmp r11, #0xBB + bne reg1_error_loop + cmp r12, #0xCC + bne reg1_error_loop + cmp r14, #0xEE + bne reg1_error_loop + + /* Everything passed, increment the loop counter. */ + push { r0-r1 } + ldr r0, =ulRegTest1LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + pop { r0-r1 } + + /* Start again. */ + b reg1_loop + +reg1_error_loop: + /* If this line is hit then there was an error in a core register value. + The loop ensures the loop counter stops incrementing. */ + b reg1_error_loop + nop + +/*-----------------------------------------------------------*/ + +.type vRegTest2Implementation, %function +vRegTest2Implementation: + + /* Put a known value in each register. */ + mov r0, #0xFF000000 + mov r1, #0x11000000 + mov r2, #0x22000000 + mov r3, #0x33000000 + mov r4, #0x44000000 + mov r5, #0x55000000 + mov r6, #0x66000000 + mov r7, #0x77000000 + mov r8, #0x88000000 + mov r9, #0x99000000 + mov r10, #0xAA000000 + mov r11, #0xBB000000 + mov r12, #0xCC000000 + mov r14, #0xEE000000 + + /* Likewise the floating point registers */ + vmov d0, r0, r1 + vmov d1, r2, r3 + vmov d2, r4, r5 + vmov d3, r6, r7 + vmov d4, r8, r9 + vmov d5, r10, r11 + vmov d6, r0, r1 + vmov d7, r2, r3 + vmov d8, r4, r5 + vmov d9, r6, r7 + vmov d10, r8, r9 + vmov d11, r10, r11 + vmov d12, r0, r1 + vmov d13, r2, r3 + vmov d14, r4, r5 + vmov d15, r6, r7 + + vmov d16, r0, r1 + vmov d17, r2, r3 + vmov d18, r4, r5 + vmov d19, r6, r7 + vmov d20, r8, r9 + vmov d21, r10, r11 + vmov d22, r0, r1 + vmov d23, r2, r3 + vmov d24, r4, r5 + vmov d25, r6, r7 + vmov d26, r8, r9 + vmov d27, r10, r11 + vmov d28, r0, r1 + vmov d29, r2, r3 + vmov d30, r4, r5 + vmov d31, r6, r7 + + /* Loop, checking each itteration that each register still contains the + expected value. */ +reg2_loop: + /* Check all the VFP registers still contain the values set above. + First save registers that are clobbered by the test. */ + push { r0-r1 } + + vmov r0, r1, d0 + cmp r0, #0xFF000000 + bne reg2_error_loopf + cmp r1, #0x11000000 + bne reg2_error_loopf + vmov r0, r1, d1 + cmp r0, #0x22000000 + bne reg2_error_loopf + cmp r1, #0x33000000 + bne reg2_error_loopf + vmov r0, r1, d2 + cmp r0, #0x44000000 + bne reg2_error_loopf + cmp r1, #0x55000000 + bne reg2_error_loopf + vmov r0, r1, d3 + cmp r0, #0x66000000 + bne reg2_error_loopf + cmp r1, #0x77000000 + bne reg2_error_loopf + vmov r0, r1, d4 + cmp r0, #0x88000000 + bne reg2_error_loopf + cmp r1, #0x99000000 + bne reg2_error_loopf + vmov r0, r1, d5 + cmp r0, #0xAA000000 + bne reg2_error_loopf + cmp r1, #0xBB000000 + bne reg2_error_loopf + vmov r0, r1, d6 + cmp r0, #0xFF000000 + bne reg2_error_loopf + cmp r1, #0x11000000 + bne reg2_error_loopf + vmov r0, r1, d7 + cmp r0, #0x22000000 + bne reg2_error_loopf + cmp r1, #0x33000000 + bne reg2_error_loopf + vmov r0, r1, d8 + cmp r0, #0x44000000 + bne reg2_error_loopf + cmp r1, #0x55000000 + bne reg2_error_loopf + vmov r0, r1, d9 + cmp r0, #0x66000000 + bne reg2_error_loopf + cmp r1, #0x77000000 + bne reg2_error_loopf + vmov r0, r1, d10 + cmp r0, #0x88000000 + bne reg2_error_loopf + cmp r1, #0x99000000 + bne reg2_error_loopf + vmov r0, r1, d11 + cmp r0, #0xAA000000 + bne reg2_error_loopf + cmp r1, #0xBB000000 + bne reg2_error_loopf + vmov r0, r1, d12 + cmp r0, #0xFF000000 + bne reg2_error_loopf + cmp r1, #0x11000000 + bne reg2_error_loopf + vmov r0, r1, d13 + cmp r0, #0x22000000 + bne reg2_error_loopf + cmp r1, #0x33000000 + bne reg2_error_loopf + vmov r0, r1, d14 + cmp r0, #0x44000000 + bne reg2_error_loopf + cmp r1, #0x55000000 + bne reg2_error_loopf + vmov r0, r1, d15 + cmp r0, #0x66000000 + bne reg2_error_loopf + cmp r1, #0x77000000 + bne reg2_error_loopf + + vmov r0, r1, d16 + cmp r0, #0xFF000000 + bne reg2_error_loopf + cmp r1, #0x11000000 + bne reg2_error_loopf + vmov r0, r1, d17 + cmp r0, #0x22000000 + bne reg2_error_loopf + cmp r1, #0x33000000 + bne reg2_error_loopf + vmov r0, r1, d18 + cmp r0, #0x44000000 + bne reg2_error_loopf + cmp r1, #0x55000000 + bne reg2_error_loopf + vmov r0, r1, d19 + cmp r0, #0x66000000 + bne reg2_error_loopf + cmp r1, #0x77000000 + bne reg2_error_loopf + vmov r0, r1, d20 + cmp r0, #0x88000000 + bne reg2_error_loopf + cmp r1, #0x99000000 + bne reg2_error_loopf + vmov r0, r1, d21 + cmp r0, #0xAA000000 + bne reg2_error_loopf + cmp r1, #0xBB000000 + bne reg2_error_loopf + vmov r0, r1, d22 + cmp r0, #0xFF000000 + bne reg2_error_loopf + cmp r1, #0x11000000 + bne reg2_error_loopf + vmov r0, r1, d23 + cmp r0, #0x22000000 + bne reg2_error_loopf + cmp r1, #0x33000000 + bne reg2_error_loopf + vmov r0, r1, d24 + cmp r0, #0x44000000 + bne reg2_error_loopf + cmp r1, #0x55000000 + bne reg2_error_loopf + vmov r0, r1, d25 + cmp r0, #0x66000000 + bne reg2_error_loopf + cmp r1, #0x77000000 + bne reg2_error_loopf + vmov r0, r1, d26 + cmp r0, #0x88000000 + bne reg2_error_loopf + cmp r1, #0x99000000 + bne reg2_error_loopf + vmov r0, r1, d27 + cmp r0, #0xAA000000 + bne reg2_error_loopf + cmp r1, #0xBB000000 + bne reg2_error_loopf + vmov r0, r1, d28 + cmp r0, #0xFF000000 + bne reg2_error_loopf + cmp r1, #0x11000000 + bne reg2_error_loopf + vmov r0, r1, d29 + cmp r0, #0x22000000 + bne reg2_error_loopf + cmp r1, #0x33000000 + bne reg2_error_loopf + vmov r0, r1, d30 + cmp r0, #0x44000000 + bne reg2_error_loopf + cmp r1, #0x55000000 + bne reg2_error_loopf + vmov r0, r1, d31 + cmp r0, #0x66000000 + bne reg2_error_loopf + cmp r1, #0x77000000 + bne reg2_error_loopf + + /* Restore the registers that were clobbered by the test. */ + pop {r0-r1} + + /* VFP register test passed. Jump to the core register test. */ + b reg2_loopf_pass + +reg2_error_loopf: + /* If this line is hit then a VFP register value was found to be + incorrect. */ + b reg2_error_loopf + +reg2_loopf_pass: + + cmp r0, #0xFF000000 + bne reg2_error_loop + cmp r1, #0x11000000 + bne reg2_error_loop + cmp r2, #0x22000000 + bne reg2_error_loop + cmp r3, #0x33000000 + bne reg2_error_loop + cmp r4, #0x44000000 + bne reg2_error_loop + cmp r5, #0x55000000 + bne reg2_error_loop + cmp r6, #0x66000000 + bne reg2_error_loop + cmp r7, #0x77000000 + bne reg2_error_loop + cmp r8, #0x88000000 + bne reg2_error_loop + cmp r9, #0x99000000 + bne reg2_error_loop + cmp r10, #0xAA000000 + bne reg2_error_loop + cmp r11, #0xBB000000 + bne reg2_error_loop + cmp r12, #0xCC000000 + bne reg2_error_loop + cmp r14, #0xEE000000 + bne reg2_error_loop + + /* Everything passed, increment the loop counter. */ + push { r0-r1 } + ldr r0, =ulRegTest2LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + pop { r0-r1 } + + /* Start again. */ + b reg2_loop + +reg2_error_loop: + /* If this line is hit then there was an error in a core register value. + The loop ensures the loop counter stops incrementing. */ + b reg2_error_loop + nop + + + .end + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/serial.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/serial.c new file mode 100644 index 000000000..a3440bb0c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/Full_Demo/serial.c @@ -0,0 +1,321 @@ +/* + FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! + */ + +/* + BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER. + + Note1: This driver is used specifically to provide an interface to the + FreeRTOS+CLI command interpreter. It is *not* intended to be a generic + serial port driver. Nor is it intended to be used as an example of an + efficient implementation. In particular, a queue is used to buffer + received characters, which is fine in this case as key presses arrive + slowly, but a DMA and/or RAM buffer should be used in place of the queue in + applications that expect higher throughput. + + Note2: This driver does not attempt to handle UART errors. +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +/* Demo application includes. */ +#include "serial.h" + +/* Xilinx includes. */ +#include "xuartps.h" +#include "xscugic.h" +#include "xil_exception.h" + +/* The UART interrupts of interest when receiving. */ +#define serRECEIVE_INTERRUPT_MASK ( XUARTPS_IXR_RXOVR | XUARTPS_IXR_RXFULL | XUARTPS_IXR_TOUT ) + +/* The UART interrupts of interest when transmitting. */ +#define serTRANSMIT_IINTERRUPT_MASK ( XUARTPS_IXR_TXEMPTY ) + +/*-----------------------------------------------------------*/ + +/* The UART being used. */ +static XUartPs xUARTInstance; + +/* The interrupt controller, which is configred by the hardware setup routines +defined in main(). */ +extern XScuGic xInterruptController; + +/* The queue into which received key presses are placed. NOTE THE COMMENTS AT +THE TOP OF THIS FILE REGARDING THE USE OF QUEUES FOR THIS PURPOSE. */ +static QueueHandle_t xRxQueue = NULL; + +/* The semaphore used to indicate the end of a transmission. */ +static SemaphoreHandle_t xTxCompleteSemaphore = NULL; + +/*-----------------------------------------------------------*/ + +/* + * The UART interrupt handler is defined in this file to provide more control, + * but still uses parts of the Xilinx provided driver. + */ +void prvUART_Handler( void *pvNotUsed ); + +/*-----------------------------------------------------------*/ + +/* + * See the serial2.h header file. + */ +xComPortHandle xSerialPortInitMinimal( uint32_t ulWantedBaud, UBaseType_t uxQueueLength ) +{ +BaseType_t xStatus; +XUartPs_Config *pxConfig; + + /* Create the queue used to hold received characters. NOTE THE COMMENTS AT + THE TOP OF THIS FILE REGARDING THE QUEUE OF QUEUES FOR THIS PURPSOE. */ + xRxQueue = xQueueCreate( uxQueueLength, sizeof( char ) ); + configASSERT( xRxQueue ); + + /* Create the semaphore used to signal the end of a transmission, then take + the semaphore so it is in the correct state the first time + xSerialSendString() is called. A block time of zero is used when taking + the semaphore as it is guaranteed to be available (it was just created). */ + xTxCompleteSemaphore = xSemaphoreCreateBinary(); + configASSERT( xTxCompleteSemaphore ); + xSemaphoreTake( xTxCompleteSemaphore, 0 ); + + /* Look up the UART configuration then initialise the dirver. */ + pxConfig = XUartPs_LookupConfig( XPAR_XUARTPS_0_DEVICE_ID ); + + /* Initialise the driver. */ + xStatus = XUartPs_CfgInitialize( &xUARTInstance, pxConfig, XPAR_PS7_UART_1_BASEADDR ); + configASSERT( xStatus == XST_SUCCESS ); + ( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */ + + /* Misc. parameter configuration. */ + XUartPs_SetBaudRate( &xUARTInstance, ulWantedBaud ); + XUartPs_SetOperMode( &xUARTInstance, XUARTPS_OPER_MODE_NORMAL ); + + /* Install the interrupt service routine that is defined within this + file. */ + xStatus = XScuGic_Connect( &xInterruptController, XPAR_XUARTPS_1_INTR, (Xil_ExceptionHandler) prvUART_Handler, (void *) &xUARTInstance ); + configASSERT( xStatus == XST_SUCCESS ); + ( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */ + + /* Ensure interrupts start clear. */ + XUartPs_WriteReg( XPAR_PS7_UART_1_BASEADDR, XUARTPS_ISR_OFFSET, XUARTPS_IXR_MASK ); + + /* Enable the UART interrupt within the GIC. */ + XScuGic_Enable( &xInterruptController, XPAR_XUARTPS_1_INTR ); + + /* Enable the interrupts of interest in the UART. */ + XUartPs_SetInterruptMask( &xUARTInstance, XUARTPS_IXR_RXFULL | XUARTPS_IXR_RXOVR | XUARTPS_IXR_TOUT | XUARTPS_IXR_TXEMPTY ); + + /* Set the receive timeout. */ + XUartPs_SetRecvTimeout( &xUARTInstance, 8 ); + + return ( xComPortHandle ) 0; +} +/*-----------------------------------------------------------*/ + +BaseType_t xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, TickType_t xBlockTime ) +{ +BaseType_t xReturn; + + /* Only a single port is supported. */ + ( void ) pxPort; + + /* Obtain a received character from the queue - entering the Blocked state + (so not consuming any processing time) to wait for a character if one is not + already available. */ + xReturn = xQueueReceive( xRxQueue, pcRxedChar, xBlockTime ); + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength ) +{ +const TickType_t xMaxWait = 200UL / portTICK_PERIOD_MS; + + /* Only a single port is supported. */ + ( void ) pxPort; + + /* Start the transmission. The interrupt service routine will complete the + transmission if necessary. */ + XUartPs_Send( &xUARTInstance, ( void * ) pcString, usStringLength ); + + /* Wait until the string has been transmitted before exiting this function, + otherwise there is a risk the calling function will overwrite the string + pointed to by the pcString parameter while it is still being transmitted. + The calling task will wait in the Blocked state (so not consuming any + processing time) until the semaphore is available. */ + xSemaphoreTake( xTxCompleteSemaphore, xMaxWait ); +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, TickType_t xBlockTime ) +{ + /* Only a single port is supported. */ + ( void ) pxPort; + + /* Send the character. */ + XUartPs_Send( &xUARTInstance, ( void * ) &cOutChar, sizeof( cOutChar ) ); + + /* Wait for the transmission to be complete so the semaphore is left in the + correct state for the next time vSerialPutString() is called. */ + xSemaphoreTake( xTxCompleteSemaphore, xBlockTime ); + + return pdPASS; +} +/*-----------------------------------------------------------*/ + +void vSerialClose(xComPortHandle xPort) +{ + /* Not supported as not required by the demo application. */ + ( void ) xPort; +} +/*-----------------------------------------------------------*/ + +void prvUART_Handler( void *pvNotUsed ) +{ +extern unsigned int XUartPs_SendBuffer( XUartPs *InstancePtr ); +uint32_t ulActiveInterrupts, ulChannelStatusRegister; +BaseType_t xHigherPriorityTaskWoken = pdFALSE; +char cChar; + + configASSERT( pvNotUsed == &xUARTInstance ); + + /* Remove compile warnings if configASSERT() is not defined. */ + ( void ) pvNotUsed; + + /* Read the interrupt ID register to see which interrupt is active. */ + ulActiveInterrupts = XUartPs_ReadReg(XPAR_PS7_UART_1_BASEADDR, XUARTPS_IMR_OFFSET); + ulActiveInterrupts &= XUartPs_ReadReg(XPAR_PS7_UART_1_BASEADDR, XUARTPS_ISR_OFFSET); + + /* Are any receive events of interest active? */ + if( ( ulActiveInterrupts & serRECEIVE_INTERRUPT_MASK ) != 0 ) + { + /* Read the Channel Status Register to determine if there is any data in + the RX FIFO. */ + ulChannelStatusRegister = XUartPs_ReadReg( XPAR_PS7_UART_1_BASEADDR, XUARTPS_SR_OFFSET ); + + /* Move data from the Rx FIFO to the Rx queue. NOTE THE COMMENTS AT THE + TOP OF THIS FILE ABOUT USING QUEUES FOR THIS PURPSOE. */ + while( ( ulChannelStatusRegister & XUARTPS_SR_RXEMPTY ) == 0 ) + { + cChar = XUartPs_ReadReg( XPAR_PS7_UART_1_BASEADDR, XUARTPS_FIFO_OFFSET ); + + /* If writing to the queue unblocks a task, and the unblocked task + has a priority above the currently running task (the task that this + interrupt interrupted), then xHigherPriorityTaskWoken will be set + to pdTRUE inside the xQueueSendFromISR() function. + xHigherPriorityTaskWoken is then passed to portYIELD_FROM_ISR() at + the end of this interrupt handler to request a context switch so the + interrupt returns directly to the (higher priority) unblocked + task. */ + xQueueSendFromISR( xRxQueue, &cChar, &xHigherPriorityTaskWoken ); + ulChannelStatusRegister = XUartPs_ReadReg( XPAR_PS7_UART_1_BASEADDR, XUARTPS_SR_OFFSET ); + } + } + + /* Are any transmit events of interest active? */ + if( ( ulActiveInterrupts & serTRANSMIT_IINTERRUPT_MASK ) != 0 ) + { + if( xUARTInstance.SendBuffer.RemainingBytes == 0 ) + { + /* Give back the semaphore to indicate that the tranmission is + complete. If giving the semaphore unblocks a task, and the + unblocked task has a priority above the currently running task (the + task that this interrupt interrupted), then xHigherPriorityTaskWoken + will be set to pdTRUE inside the xSemaphoreGiveFromISR() function. + xHigherPriorityTaskWoken is then passed to portYIELD_FROM_ISR() at + the end of this interrupt handler to request a context switch so the + interrupt returns directly to the (higher priority) unblocked + task. */ + xSemaphoreGiveFromISR( xTxCompleteSemaphore, &xHigherPriorityTaskWoken ); + + /* No more data to transmit. */ + XUartPs_WriteReg( XPAR_PS7_UART_1_BASEADDR, XUARTPS_IDR_OFFSET, XUARTPS_IXR_TXEMPTY ); + } + else + { + /* More data to send. */ + XUartPs_SendBuffer( &xUARTInstance ); + } + } + + /* portYIELD_FROM_ISR() will request a context switch if executing this + interrupt handler caused a task to leave the blocked state, and the task + that left the blocked state has a higher priority than the currently running + task (the task this interrupt interrupted). See the comment above the calls + to xSemaphoreGiveFromISR() and xQueueSendFromISR() within this function. */ + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + + /* Clear the interrupt status. */ + XUartPs_WriteReg( XPAR_PS7_UART_1_BASEADDR, XUARTPS_ISR_OFFSET, ulActiveInterrupts ); +} + + + + + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/ParTest.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/ParTest.c new file mode 100644 index 000000000..8adb21e06 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/ParTest.c @@ -0,0 +1,129 @@ +/* + FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/*----------------------------------------------------------- + * Simple IO routines to control the LEDs. + * This file is called ParTest.c for historic reasons. Originally it stood for + * PARallel port TEST. + *-----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo includes. */ +#include "partest.h" + +/* Xilinx includes. */ +#include "xgpiops.h" + +#define partstNUM_LEDS ( 1 ) +#define partstDIRECTION_OUTPUT ( 1 ) +#define partstOUTPUT_ENABLED ( 1 ) +#define partstLED_OUTPUT ( 10 ) + +/*-----------------------------------------------------------*/ + +static XGpioPs xGpio; + +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ +XGpioPs_Config *pxConfigPtr; +BaseType_t xStatus; + + /* Initialise the GPIO driver. */ + pxConfigPtr = XGpioPs_LookupConfig( XPAR_XGPIOPS_0_DEVICE_ID ); + xStatus = XGpioPs_CfgInitialize( &xGpio, pxConfigPtr, pxConfigPtr->BaseAddr ); + configASSERT( xStatus == XST_SUCCESS ); + ( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */ + + /* Enable outputs and set low. */ + XGpioPs_SetDirectionPin( &xGpio, partstLED_OUTPUT, partstDIRECTION_OUTPUT ); + XGpioPs_SetOutputEnablePin( &xGpio, partstLED_OUTPUT, partstOUTPUT_ENABLED ); + XGpioPs_WritePin( &xGpio, partstLED_OUTPUT, 0x0 ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( UBaseType_t uxLED, BaseType_t xValue ) +{ + ( void ) uxLED; + XGpioPs_WritePin( &xGpio, partstLED_OUTPUT, xValue ); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +BaseType_t xLEDState; + + ( void ) uxLED; + + xLEDState = XGpioPs_ReadPin( &xGpio, partstLED_OUTPUT ); + XGpioPs_WritePin( &xGpio, partstLED_OUTPUT, !xLEDState ); +} + + + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lscript.ld b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lscript.ld new file mode 100644 index 000000000..8c0b95033 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lscript.ld @@ -0,0 +1,285 @@ +/*******************************************************************/ +/* */ +/* This file is automatically generated by linker script generator.*/ +/* */ +/* Version: */ +/* */ +/* Copyright (c) 2010 Xilinx, Inc. All rights reserved. */ +/* */ +/* Description : Cortex-A9 Linker Script */ +/* */ +/*******************************************************************/ + +_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000; +_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000; + +_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024; +_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048; +_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024; +_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024; + +/* Define Memories in the system */ + +MEMORY +{ + ps7_ddr_0_S_AXI_BASEADDR : ORIGIN = 0x00100000, LENGTH = 0x1FF00000 + ps7_ram_0_S_AXI_BASEADDR : ORIGIN = 0x00000000, LENGTH = 0x00030000 + ps7_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x0000FE00 +} + +/* Specify the default entry point to the program */ + +ENTRY(_freertos_vector_table) + +/* Define the sections, and where they are mapped in memory */ + +SECTIONS +{ +.text : { + *(.freertos_vectors) + *(.vectors) + *(.boot) + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + *(.plt) + *(.gnu_warning) + *(.gcc_execpt_table) + *(.glue_7) + *(.glue_7t) + *(.vfp11_veneer) + *(.ARM.extab) + *(.gnu.linkonce.armextab.*) +} > ps7_ddr_0_S_AXI_BASEADDR + +.init : { + KEEP (*(.init)) +} > ps7_ddr_0_S_AXI_BASEADDR + +.fini : { + KEEP (*(.fini)) +} > ps7_ddr_0_S_AXI_BASEADDR + +.rodata : { + __rodata_start = .; + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + __rodata_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.rodata1 : { + __rodata1_start = .; + *(.rodata1) + *(.rodata1.*) + __rodata1_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.sdata2 : { + __sdata2_start = .; + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + __sdata2_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.sbss2 : { + __sbss2_start = .; + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + __sbss2_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.data : { + __data_start = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.jcr) + *(.got) + *(.got.plt) + __data_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.data1 : { + __data1_start = .; + *(.data1) + *(.data1.*) + __data1_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.got : { + *(.got) +} > ps7_ddr_0_S_AXI_BASEADDR + +.ctors : { + __CTOR_LIST__ = .; + ___CTORS_LIST___ = .; + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + ___CTORS_END___ = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.dtors : { + __DTOR_LIST__ = .; + ___DTORS_LIST___ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + ___DTORS_END___ = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.fixup : { + __fixup_start = .; + *(.fixup) + __fixup_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.eh_frame : { + *(.eh_frame) +} > ps7_ddr_0_S_AXI_BASEADDR + +.eh_framehdr : { + __eh_framehdr_start = .; + *(.eh_framehdr) + __eh_framehdr_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.gcc_except_table : { + *(.gcc_except_table) +} > ps7_ddr_0_S_AXI_BASEADDR + +.mmu_tbl (ALIGN(16384)) : { + __mmu_tbl_start = .; + *(.mmu_tbl) + __mmu_tbl_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.ARM.exidx : { + __exidx_start = .; + *(.ARM.exidx*) + *(.gnu.linkonce.armexidix.*.*) + __exidx_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.preinit_array : { + __preinit_array_start = .; + KEEP (*(SORT(.preinit_array.*))) + KEEP (*(.preinit_array)) + __preinit_array_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.init_array : { + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.fini_array : { + __fini_array_start = .; + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array)) + __fini_array_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.ARM.attributes : { + __ARM.attributes_start = .; + *(.ARM.attributes) + __ARM.attributes_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.sdata : { + __sdata_start = .; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + __sdata_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.sbss (NOLOAD) : { + __sbss_start = .; + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + __sbss_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.tdata : { + __tdata_start = .; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __tdata_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.tbss : { + __tbss_start = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + __tbss_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.bss (NOLOAD) : { + __bss_start = .; + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + __bss_end = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 ); + +_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 ); + +/* Generate Stack and Heap definitions */ + +.heap (NOLOAD) : { + . = ALIGN(16); + _heap = .; + HeapBase = .; + _heap_start = .; + . += _HEAP_SIZE; + _heap_end = .; + HeapLimit = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +.stack (NOLOAD) : { + . = ALIGN(16); + _stack_end = .; + . += _STACK_SIZE; + _stack = .; + __stack = _stack; + . = ALIGN(16); + _irq_stack_end = .; + . += _STACK_SIZE; + __irq_stack = .; + _supervisor_stack_end = .; + . += _SUPERVISOR_STACK_SIZE; + . = ALIGN(16); + __supervisor_stack = .; + _abort_stack_end = .; + . += _ABORT_STACK_SIZE; + . = ALIGN(16); + __abort_stack = .; + _fiq_stack_end = .; + . += _FIQ_STACK_SIZE; + . = ALIGN(16); + __fiq_stack = .; + _undef_stack_end = .; + . += _UNDEF_STACK_SIZE; + . = ALIGN(16); + __undef_stack = .; +} > ps7_ddr_0_S_AXI_BASEADDR + +_end = .; +} + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/BasicSocketCommandServer/BasicSocketCommandServer.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/BasicSocketCommandServer/BasicSocketCommandServer.c new file mode 100644 index 000000000..c16580670 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/BasicSocketCommandServer/BasicSocketCommandServer.c @@ -0,0 +1,203 @@ +/* + FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. + + + *************************************************************************** + * * + * FreeRTOS tutorial books are available in pdf and paperback. * + * Complete, revised, and edited pdf reference manuals are also * + * available. * + * * + * Purchasing FreeRTOS documentation will not only help you, by * + * ensuring you get running as quickly as possible and with an * + * in-depth knowledge of how to use FreeRTOS, it will also help * + * the FreeRTOS project to continue with its mission of providing * + * professional grade, cross platform, de facto standard solutions * + * for microcontrollers - completely free of charge! * + * * + * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * + * * + * Thank you for using FreeRTOS, and thank you for your support! * + * * + *************************************************************************** + + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + >>>NOTE<<< The modification to the GPL is included to allow you to + distribute a combined work that includes FreeRTOS without being obliged to + provide the source code for proprietary components outside of the FreeRTOS + kernel. FreeRTOS is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/* Standard includes. */ +#include "stdlib.h" +#include "string.h" + +/* lwIP core includes */ +#include "lwip/opt.h" +#include "lwip/sockets.h" + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Utils includes. */ +#include "FreeRTOS_CLI.h" + +/* Dimensions the buffer into which input characters are placed. */ +#define cmdMAX_INPUT_SIZE 100 + +/* Dimensions the buffer into which string outputs can be placed. */ +#define cmdMAX_OUTPUT_SIZE 1024 + +/*-----------------------------------------------------------*/ + +void vBasicSocketsCommandInterpreterTask( void *pvParameters ) +{ +long lSocket, lClientFd, lBytes, lAddrLen = sizeof( struct sockaddr_in ), lInputIndex; +struct sockaddr_in sLocalAddr; +struct sockaddr_in client_addr; +const char *pcWelcomeMessage = "FreeRTOS command server - connection accepted.\r\nType Help to view a list of registered commands.\r\n\r\n>"; +char cInChar; +static char cInputString[ cmdMAX_INPUT_SIZE ], cOutputString[ cmdMAX_OUTPUT_SIZE ]; +portBASE_TYPE xReturned; +extern void vRegisterSampleCLICommands( void ); + + ( void ) pvParameters; + + /* Register the standard CLI commands. */ + vRegisterSampleCLICommands(); + + lSocket = lwip_socket(AF_INET, SOCK_STREAM, 0); + + if( lSocket >= 0 ) + { + memset((char *)&sLocalAddr, 0, sizeof(sLocalAddr)); + sLocalAddr.sin_family = AF_INET; + sLocalAddr.sin_len = sizeof(sLocalAddr); + sLocalAddr.sin_addr.s_addr = htonl(INADDR_ANY); + sLocalAddr.sin_port = ntohs( ( ( unsigned short ) 23 ) ); + + if( lwip_bind( lSocket, ( struct sockaddr *) &sLocalAddr, sizeof( sLocalAddr ) ) < 0 ) + { + lwip_close( lSocket ); + vTaskDelete( NULL ); + } + + if( lwip_listen( lSocket, 20 ) != 0 ) + { + lwip_close( lSocket ); + vTaskDelete( NULL ); + } + + for( ;; ) + { + + lClientFd = lwip_accept(lSocket, ( struct sockaddr * ) &client_addr, ( u32_t * ) &lAddrLen ); + + if( lClientFd > 0L ) + { + lwip_send( lClientFd, pcWelcomeMessage, strlen( ( const char * ) pcWelcomeMessage ), 0 ); + + lInputIndex = 0; + memset( cInputString, 0x00, cmdMAX_INPUT_SIZE ); + + do + { + lBytes = lwip_recv( lClientFd, &cInChar, sizeof( cInChar ), 0 ); + + if( lBytes > 0L ) + { + if( cInChar == '\n' ) + { + /* The input string has been terminated. Was the + input a quit command? */ + if( strcmp( "quit", ( const char * ) cInputString ) == 0 ) + { + /* Set lBytes to 0 to close the connection. */ + lBytes = 0L; + } + else + { + /* The input string was not a quit command. + Pass the string to the command interpreter. */ + do + { + /* Get the next output string from the command interpreter. */ + xReturned = FreeRTOS_CLIProcessCommand( cInputString, cOutputString, configCOMMAND_INT_MAX_OUTPUT_SIZE ); + lwip_send( lClientFd, cOutputString, strlen( ( const char * ) cOutputString ), 0 ); + + } while( xReturned != pdFALSE ); + + + /* All the strings generated by the input + command have been sent. Clear the input + string ready to receive the next command. */ + lInputIndex = 0; + memset( cInputString, 0x00, cmdMAX_INPUT_SIZE ); + lwip_send( lClientFd, "\r\n>", strlen( "\r\n>" ), 0 ); + } + } + else + { + if( cInChar == '\r' ) + { + /* Ignore the character. */ + } + else if( cInChar == '\b' ) + { + /* Backspace was pressed. Erase the last + character in the string - if any. */ + if( lInputIndex > 0 ) + { + lInputIndex--; + cInputString[ lInputIndex ] = '\0'; + } + } + else + { + /* A character was entered. Add it to the string + entered so far. When a \n is entered the complete + string will be passed to the command interpreter. */ + if( lInputIndex < cmdMAX_INPUT_SIZE ) + { + cInputString[ lInputIndex ] = cInChar; + lInputIndex++; + } + } + } + } + + } while( lBytes > 0L ); + + lwip_close( lClientFd ); + } + } + } + + /* Will only get here if a listening socket could not be created. */ + vTaskDelete( NULL ); +} + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/fs.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/fs.c new file mode 100644 index 000000000..993fffcdd --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/fs.c @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#include "lwip/opt.h" +#include "lwip/def.h" +#include "fs.h" +#include "fsdata.h" +#include + +/** Set this to 1 to include "fsdata_custom.c" instead of "fsdata.c" for the + * file system (to prevent changing the file included in CVS) */ +#ifndef HTTPD_USE_CUSTUM_FSDATA +#define HTTPD_USE_CUSTUM_FSDATA 0 +#endif + +#if HTTPD_USE_CUSTUM_FSDATA +#include "fsdata_custom.c" +#else /* HTTPD_USE_CUSTUM_FSDATA */ +#include "fsdata.c" +#endif /* HTTPD_USE_CUSTUM_FSDATA */ + +/*-----------------------------------------------------------------------------------*/ +/* Define the number of open files that we can support. */ +#ifndef LWIP_MAX_OPEN_FILES +#define LWIP_MAX_OPEN_FILES 10 +#endif + +/* Define the file system memory allocation structure. */ +struct fs_table { + struct fs_file file; + u8_t inuse; +}; + +/* Allocate file system memory */ +struct fs_table fs_memory[LWIP_MAX_OPEN_FILES]; + +#if LWIP_HTTPD_CUSTOM_FILES +int fs_open_custom(struct fs_file *file, const char *name); +void fs_close_custom(struct fs_file *file); +#endif /* LWIP_HTTPD_CUSTOM_FILES */ + +/*-----------------------------------------------------------------------------------*/ +static struct fs_file * +fs_malloc(void) +{ + int i; + for(i = 0; i < LWIP_MAX_OPEN_FILES; i++) { + if(fs_memory[i].inuse == 0) { + fs_memory[i].inuse = 1; + return(&fs_memory[i].file); + } + } + return(NULL); +} + +/*-----------------------------------------------------------------------------------*/ +static void +fs_free(struct fs_file *file) +{ + int i; + for(i = 0; i < LWIP_MAX_OPEN_FILES; i++) { + if(&fs_memory[i].file == file) { + fs_memory[i].inuse = 0; + break; + } + } + return; +} + +/*-----------------------------------------------------------------------------------*/ +struct fs_file * +fs_open(const char *name) +{ + struct fs_file *file; + const struct fsdata_file *f; + + file = fs_malloc(); + if(file == NULL) { + return NULL; + } + +#if LWIP_HTTPD_CUSTOM_FILES + if(fs_open_custom(file, name)) { + file->is_custom_file = 1; + return file; + } + file->is_custom_file = 0; +#endif /* LWIP_HTTPD_CUSTOM_FILES */ + + for(f = FS_ROOT; f != NULL; f = f->next) { + if (!strcmp(name, (char *)f->name)) { + file->data = (const char *)f->data; + file->len = f->len; + file->index = f->len; + file->pextension = NULL; + file->http_header_included = f->http_header_included; +#if HTTPD_PRECALCULATED_CHECKSUM + file->chksum_count = f->chksum_count; + file->chksum = f->chksum; +#endif /* HTTPD_PRECALCULATED_CHECKSUM */ +#if LWIP_HTTPD_FILE_STATE + file->state = fs_state_init(file, name); +#endif /* #if LWIP_HTTPD_FILE_STATE */ + return file; + } + } + fs_free(file); + return NULL; +} + +/*-----------------------------------------------------------------------------------*/ +void +fs_close(struct fs_file *file) +{ +#if LWIP_HTTPD_CUSTOM_FILES + if (file->is_custom_file) { + fs_close_custom(file); + } +#endif /* LWIP_HTTPD_CUSTOM_FILES */ +#if LWIP_HTTPD_FILE_STATE + fs_state_free(file, file->state); +#endif /* #if LWIP_HTTPD_FILE_STATE */ + fs_free(file); +} +/*-----------------------------------------------------------------------------------*/ +int +fs_read(struct fs_file *file, char *buffer, int count) +{ + int read; + + if(file->index == file->len) { + return -1; + } + + read = file->len - file->index; + if(read > count) { + read = count; + } + + MEMCPY(buffer, (file->data + file->index), read); + file->index += read; + + return(read); +} +/*-----------------------------------------------------------------------------------*/ +int fs_bytes_left(struct fs_file *file) +{ + return file->len - file->index; +} diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/fs.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/fs.h new file mode 100644 index 000000000..cd7675923 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/fs.h @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __FS_H__ +#define __FS_H__ + +#include "lwip/opt.h" + +/** Set this to 1 and provide the functions: + * - "int fs_open_custom(struct fs_file *file, const char *name)" + * Called first for every opened file to allow opening files + * that are not included in fsdata(_custom).c + * - "void fs_close_custom(struct fs_file *file)" + * Called to free resources allocated by fs_open_custom(). + */ +#ifndef LWIP_HTTPD_CUSTOM_FILES +#define LWIP_HTTPD_CUSTOM_FILES 0 +#endif + +/** Set this to 1 to include an application state argument per file + * that is opened. This allows to keep a state per connection/file. + */ +#ifndef LWIP_HTTPD_FILE_STATE +#define LWIP_HTTPD_FILE_STATE 0 +#endif + +/** HTTPD_PRECALCULATED_CHECKSUM==1: include precompiled checksums for + * predefined (MSS-sized) chunks of the files to prevent having to calculate + * the checksums at runtime. */ +#ifndef HTTPD_PRECALCULATED_CHECKSUM +#define HTTPD_PRECALCULATED_CHECKSUM 0 +#endif + +#if HTTPD_PRECALCULATED_CHECKSUM +struct fsdata_chksum { + u32_t offset; + u16_t chksum; + u16_t len; +}; +#endif /* HTTPD_PRECALCULATED_CHECKSUM */ + +struct fs_file { + const char *data; + int len; + int index; + void *pextension; +#if HTTPD_PRECALCULATED_CHECKSUM + const struct fsdata_chksum *chksum; + u16_t chksum_count; +#endif /* HTTPD_PRECALCULATED_CHECKSUM */ + u8_t http_header_included; +#if LWIP_HTTPD_CUSTOM_FILES + u8_t is_custom_file; +#endif /* LWIP_HTTPD_CUSTOM_FILES */ +#if LWIP_HTTPD_FILE_STATE + void *state; +#endif /* LWIP_HTTPD_FILE_STATE */ +}; + +struct fs_file *fs_open(const char *name); +void fs_close(struct fs_file *file); +int fs_read(struct fs_file *file, char *buffer, int count); +int fs_bytes_left(struct fs_file *file); + +#if LWIP_HTTPD_FILE_STATE +/** This user-defined function is called when a file is opened. */ +void *fs_state_init(struct fs_file *file, const char *name); +/** This user-defined function is called when a file is closed. */ +void fs_state_free(struct fs_file *file, void *state); +#endif /* #if LWIP_HTTPD_FILE_STATE */ + +#endif /* __FS_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/fsdata.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/fsdata.c new file mode 100644 index 000000000..f2ddfd935 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/fsdata.c @@ -0,0 +1,2068 @@ +#include "fs.h" +#include "lwip/def.h" +#include "fsdata.h" + + +#define file_NULL (struct fsdata_file *) NULL + + +static const unsigned int dummy_align__404_html = 0; +static const unsigned char data__404_html[] = { +/* /404.html (10 chars) */ +0x2f,0x34,0x30,0x34,0x2e,0x68,0x74,0x6d,0x6c,0x00,0x00,0x00, + +/* HTTP header */ +/* "HTTP/1.0 404 File not found +" (29 bytes) */ +0x48,0x54,0x54,0x50,0x2f,0x31,0x2e,0x30,0x20,0x34,0x30,0x34,0x20,0x46,0x69,0x6c, +0x65,0x20,0x6e,0x6f,0x74,0x20,0x66,0x6f,0x75,0x6e,0x64,0x0d,0x0a, +/* "Server: lwIP/1.3.1 (http://savannah.nongnu.org/projects/lwip) +" (63 bytes) */ +0x53,0x65,0x72,0x76,0x65,0x72,0x3a,0x20,0x6c,0x77,0x49,0x50,0x2f,0x31,0x2e,0x33, +0x2e,0x31,0x20,0x28,0x68,0x74,0x74,0x70,0x3a,0x2f,0x2f,0x73,0x61,0x76,0x61,0x6e, +0x6e,0x61,0x68,0x2e,0x6e,0x6f,0x6e,0x67,0x6e,0x75,0x2e,0x6f,0x72,0x67,0x2f,0x70, +0x72,0x6f,0x6a,0x65,0x63,0x74,0x73,0x2f,0x6c,0x77,0x69,0x70,0x29,0x0d,0x0a, +/* "Content-type: text/html + +" (27 bytes) */ +0x43,0x6f,0x6e,0x74,0x65,0x6e,0x74,0x2d,0x74,0x79,0x70,0x65,0x3a,0x20,0x74,0x65, +0x78,0x74,0x2f,0x68,0x74,0x6d,0x6c,0x0d,0x0a,0x0d,0x0a, +/* raw file data (544 bytes) */ +0x3c,0x68,0x74,0x6d,0x6c,0x3e,0x0a,0x3c,0x68,0x65,0x61,0x64,0x3e,0x3c,0x74,0x69, +0x74,0x6c,0x65,0x3e,0x6c,0x77,0x49,0x50,0x20,0x2d,0x20,0x41,0x20,0x4c,0x69,0x67, +0x68,0x74,0x77,0x65,0x69,0x67,0x68,0x74,0x20,0x54,0x43,0x50,0x2f,0x49,0x50,0x20, +0x53,0x74,0x61,0x63,0x6b,0x3c,0x2f,0x74,0x69,0x74,0x6c,0x65,0x3e,0x3c,0x2f,0x68, +0x65,0x61,0x64,0x3e,0x0a,0x3c,0x62,0x6f,0x64,0x79,0x20,0x62,0x67,0x63,0x6f,0x6c, +0x6f,0x72,0x3d,0x22,0x77,0x68,0x69,0x74,0x65,0x22,0x20,0x74,0x65,0x78,0x74,0x3d, +0x22,0x62,0x6c,0x61,0x63,0x6b,0x22,0x3e,0x0a,0x0a,0x20,0x20,0x20,0x20,0x3c,0x74, +0x61,0x62,0x6c,0x65,0x20,0x77,0x69,0x64,0x74,0x68,0x3d,0x22,0x31,0x30,0x30,0x25, +0x22,0x3e,0x0a,0x20,0x20,0x20,0x20,0x20,0x20,0x3c,0x74,0x72,0x20,0x76,0x61,0x6c, +0x69,0x67,0x6e,0x3d,0x22,0x74,0x6f,0x70,0x22,0x3e,0x3c,0x74,0x64,0x20,0x77,0x69, +0x64,0x74,0x68,0x3d,0x22,0x38,0x30,0x22,0x3e,0x09,0x20,0x20,0x0a,0x09,0x20,0x20, +0x3c,0x61,0x20,0x68,0x72,0x65,0x66,0x3d,0x22,0x68,0x74,0x74,0x70,0x3a,0x2f,0x2f, +0x77,0x77,0x77,0x2e,0x73,0x69,0x63,0x73,0x2e,0x73,0x65,0x2f,0x22,0x3e,0x3c,0x69, +0x6d,0x67,0x20,0x73,0x72,0x63,0x3d,0x22,0x2f,0x69,0x6d,0x67,0x2f,0x73,0x69,0x63, +0x73,0x2e,0x67,0x69,0x66,0x22,0x0a,0x09,0x20,0x20,0x62,0x6f,0x72,0x64,0x65,0x72, +0x3d,0x22,0x30,0x22,0x20,0x61,0x6c,0x74,0x3d,0x22,0x53,0x49,0x43,0x53,0x20,0x6c, +0x6f,0x67,0x6f,0x22,0x20,0x74,0x69,0x74,0x6c,0x65,0x3d,0x22,0x53,0x49,0x43,0x53, +0x20,0x6c,0x6f,0x67,0x6f,0x22,0x3e,0x3c,0x2f,0x61,0x3e,0x0a,0x09,0x3c,0x2f,0x74, +0x64,0x3e,0x3c,0x74,0x64,0x20,0x77,0x69,0x64,0x74,0x68,0x3d,0x22,0x35,0x30,0x30, +0x22,0x3e,0x09,0x20,0x20,0x0a,0x09,0x20,0x20,0x3c,0x68,0x31,0x3e,0x6c,0x77,0x49, +0x50,0x20,0x2d,0x20,0x41,0x20,0x4c,0x69,0x67,0x68,0x74,0x77,0x65,0x69,0x67,0x68, +0x74,0x20,0x54,0x43,0x50,0x2f,0x49,0x50,0x20,0x53,0x74,0x61,0x63,0x6b,0x3c,0x2f, +0x68,0x31,0x3e,0x0a,0x09,0x20,0x20,0x3c,0x68,0x32,0x3e,0x34,0x30,0x34,0x20,0x2d, +0x20,0x50,0x61,0x67,0x65,0x20,0x6e,0x6f,0x74,0x20,0x66,0x6f,0x75,0x6e,0x64,0x3c, +0x2f,0x68,0x32,0x3e,0x0a,0x09,0x20,0x20,0x3c,0x70,0x3e,0x0a,0x09,0x20,0x20,0x20, +0x20,0x53,0x6f,0x72,0x72,0x79,0x2c,0x20,0x74,0x68,0x65,0x20,0x70,0x61,0x67,0x65, +0x20,0x79,0x6f,0x75,0x20,0x61,0x72,0x65,0x20,0x72,0x65,0x71,0x75,0x65,0x73,0x74, +0x69,0x6e,0x67,0x20,0x77,0x61,0x73,0x20,0x6e,0x6f,0x74,0x20,0x66,0x6f,0x75,0x6e, +0x64,0x20,0x6f,0x6e,0x20,0x74,0x68,0x69,0x73,0x0a,0x09,0x20,0x20,0x20,0x20,0x73, +0x65,0x72,0x76,0x65,0x72,0x2e,0x20,0x0a,0x09,0x20,0x20,0x3c,0x2f,0x70,0x3e,0x0a, +0x09,0x3c,0x2f,0x74,0x64,0x3e,0x3c,0x74,0x64,0x3e,0x0a,0x09,0x20,0x20,0x26,0x6e, +0x62,0x73,0x70,0x3b,0x0a,0x09,0x3c,0x2f,0x74,0x64,0x3e,0x3c,0x2f,0x74,0x72,0x3e, +0x0a,0x20,0x20,0x20,0x20,0x20,0x20,0x3c,0x2f,0x74,0x61,0x62,0x6c,0x65,0x3e,0x0a, +0x3c,0x2f,0x62,0x6f,0x64,0x79,0x3e,0x0a,0x3c,0x2f,0x68,0x74,0x6d,0x6c,0x3e,0x0a, +}; + +static const unsigned int dummy_align__index_shtml = 1; +static const unsigned char data__index_shtml[] = { +/* /index.shtml (13 chars) */ +0x2f,0x69,0x6e,0x64,0x65,0x78,0x2e,0x73,0x68,0x74,0x6d,0x6c,0x00,0x00,0x00,0x00, + +/* HTTP header */ +/* "HTTP/1.0 200 OK +" (17 bytes) */ +0x48,0x54,0x54,0x50,0x2f,0x31,0x2e,0x30,0x20,0x32,0x30,0x30,0x20,0x4f,0x4b,0x0d, +0x0a, +/* "Server: lwIP/1.3.1 (http://savannah.nongnu.org/projects/lwip) +" (63 bytes) */ +0x53,0x65,0x72,0x76,0x65,0x72,0x3a,0x20,0x6c,0x77,0x49,0x50,0x2f,0x31,0x2e,0x33, +0x2e,0x31,0x20,0x28,0x68,0x74,0x74,0x70,0x3a,0x2f,0x2f,0x73,0x61,0x76,0x61,0x6e, +0x6e,0x61,0x68,0x2e,0x6e,0x6f,0x6e,0x67,0x6e,0x75,0x2e,0x6f,0x72,0x67,0x2f,0x70, +0x72,0x6f,0x6a,0x65,0x63,0x74,0x73,0x2f,0x6c,0x77,0x69,0x70,0x29,0x0d,0x0a, +/* "Content-type: text/html +Expires: Fri, 10 Apr 2008 14:00:00 GMT +Pragma: no-cache + +" (85 bytes) */ +0x43,0x6f,0x6e,0x74,0x65,0x6e,0x74,0x2d,0x74,0x79,0x70,0x65,0x3a,0x20,0x74,0x65, +0x78,0x74,0x2f,0x68,0x74,0x6d,0x6c,0x0d,0x0a,0x45,0x78,0x70,0x69,0x72,0x65,0x73, +0x3a,0x20,0x46,0x72,0x69,0x2c,0x20,0x31,0x30,0x20,0x41,0x70,0x72,0x20,0x32,0x30, +0x30,0x38,0x20,0x31,0x34,0x3a,0x30,0x30,0x3a,0x30,0x30,0x20,0x47,0x4d,0x54,0x0d, +0x0a,0x50,0x72,0x61,0x67,0x6d,0x61,0x3a,0x20,0x6e,0x6f,0x2d,0x63,0x61,0x63,0x68, +0x65,0x0d,0x0a,0x0d,0x0a, +/* raw file data (762 bytes) */ +0x3c,0x21,0x44,0x4f,0x43,0x54,0x59,0x50,0x45,0x20,0x48,0x54,0x4d,0x4c,0x20,0x50, +0x55,0x42,0x4c,0x49,0x43,0x20,0x22,0x2d,0x2f,0x2f,0x57,0x33,0x43,0x2f,0x2f,0x44, +0x54,0x44,0x20,0x48,0x54,0x4d,0x4c,0x20,0x34,0x2e,0x30,0x31,0x20,0x54,0x72,0x61, +0x6e,0x73,0x69,0x74,0x69,0x6f,0x6e,0x61,0x6c,0x2f,0x2f,0x45,0x4e,0x22,0x20,0x22, +0x68,0x74,0x74,0x70,0x3a,0x2f,0x2f,0x77,0x77,0x77,0x2e,0x77,0x33,0x2e,0x6f,0x72, +0x67,0x2f,0x54,0x52,0x2f,0x68,0x74,0x6d,0x6c,0x34,0x2f,0x6c,0x6f,0x6f,0x73,0x65, +0x2e,0x64,0x74,0x64,0x22,0x3e,0x0d,0x0a,0x3c,0x68,0x74,0x6d,0x6c,0x3e,0x0d,0x0a, +0x20,0x20,0x3c,0x68,0x65,0x61,0x64,0x3e,0x0d,0x0a,0x20,0x20,0x20,0x20,0x3c,0x74, +0x69,0x74,0x6c,0x65,0x3e,0x46,0x72,0x65,0x65,0x52,0x54,0x4f,0x53,0x2e,0x6f,0x72, +0x67,0x20,0x6c,0x77,0x49,0x50,0x20,0x57,0x45,0x42,0x20,0x73,0x65,0x72,0x76,0x65, +0x72,0x20,0x64,0x65,0x6d,0x6f,0x3c,0x2f,0x74,0x69,0x74,0x6c,0x65,0x3e,0x0d,0x0a, +0x20,0x20,0x3c,0x2f,0x68,0x65,0x61,0x64,0x3e,0x0d,0x0a,0x20,0x20,0x3c,0x42,0x4f, +0x44,0x59,0x20,0x6f,0x6e,0x4c,0x6f,0x61,0x64,0x3d,0x22,0x77,0x69,0x6e,0x64,0x6f, +0x77,0x2e,0x73,0x65,0x74,0x54,0x69,0x6d,0x65,0x6f,0x75,0x74,0x28,0x26,0x71,0x75, +0x6f,0x74,0x3b,0x6c,0x6f,0x63,0x61,0x74,0x69,0x6f,0x6e,0x2e,0x68,0x72,0x65,0x66, +0x3d,0x27,0x69,0x6e,0x64,0x65,0x78,0x2e,0x73,0x68,0x74,0x6d,0x6c,0x27,0x26,0x71, +0x75,0x6f,0x74,0x3b,0x2c,0x32,0x30,0x30,0x30,0x29,0x22,0x3e,0x0d,0x0a,0x3c,0x66, +0x6f,0x6e,0x74,0x20,0x66,0x61,0x63,0x65,0x3d,0x22,0x61,0x72,0x69,0x61,0x6c,0x22, +0x3e,0x0d,0x0a,0x3c,0x61,0x20,0x68,0x72,0x65,0x66,0x3d,0x22,0x69,0x6e,0x64,0x65, +0x78,0x2e,0x73,0x68,0x74,0x6d,0x6c,0x22,0x3e,0x54,0x61,0x73,0x6b,0x20,0x53,0x74, +0x61,0x74,0x73,0x3c,0x2f,0x61,0x3e,0x20,0x3c,0x62,0x3e,0x7c,0x3c,0x2f,0x62,0x3e, +0x20,0x3c,0x61,0x20,0x68,0x72,0x65,0x66,0x3d,0x22,0x72,0x75,0x6e,0x74,0x69,0x6d, +0x65,0x2e,0x73,0x68,0x74,0x6d,0x6c,0x22,0x3e,0x52,0x75,0x6e,0x20,0x54,0x69,0x6d, +0x65,0x20,0x53,0x74,0x61,0x74,0x73,0x3c,0x2f,0x61,0x3e,0x20,0x3c,0x62,0x3e,0x7c, +0x3c,0x2f,0x62,0x3e,0x20,0x3c,0x61,0x20,0x68,0x72,0x65,0x66,0x3d,0x22,0x68,0x74, +0x74,0x70,0x3a,0x2f,0x2f,0x77,0x77,0x77,0x2e,0x66,0x72,0x65,0x65,0x72,0x74,0x6f, +0x73,0x2e,0x6f,0x72,0x67,0x2f,0x22,0x3e,0x46,0x72,0x65,0x65,0x52,0x54,0x4f,0x53, +0x20,0x48,0x6f,0x6d,0x65,0x70,0x61,0x67,0x65,0x3c,0x2f,0x61,0x3e,0x20,0x3c,0x62, +0x3e,0x7c,0x3c,0x2f,0x62,0x3e,0x20,0x3c,0x61,0x20,0x68,0x72,0x65,0x66,0x3d,0x22, +0x6c,0x6f,0x67,0x6f,0x2e,0x6a,0x70,0x67,0x22,0x3e,0x33,0x37,0x4b,0x20,0x6a,0x70, +0x67,0x3c,0x2f,0x61,0x3e,0x0d,0x0a,0x3c,0x62,0x72,0x3e,0x3c,0x70,0x3e,0x0d,0x0a, +0x3c,0x68,0x72,0x3e,0x0d,0x0a,0x3c,0x62,0x72,0x3e,0x3c,0x70,0x3e,0x0d,0x0a,0x3c, +0x68,0x32,0x3e,0x54,0x61,0x73,0x6b,0x20,0x73,0x74,0x61,0x74,0x69,0x73,0x74,0x69, +0x63,0x73,0x3c,0x2f,0x68,0x32,0x3e,0x0d,0x0a,0x50,0x61,0x67,0x65,0x20,0x77,0x69, +0x6c,0x6c,0x20,0x72,0x65,0x66,0x72,0x65,0x73,0x68,0x20,0x65,0x76,0x65,0x72,0x79, +0x20,0x32,0x20,0x73,0x65,0x63,0x6f,0x6e,0x64,0x73,0x2e,0x3c,0x70,0x3e,0x0d,0x0a, +0x3c,0x66,0x6f,0x6e,0x74,0x20,0x66,0x61,0x63,0x65,0x3d,0x22,0x63,0x6f,0x75,0x72, +0x69,0x65,0x72,0x22,0x3e,0x3c,0x70,0x72,0x65,0x3e,0x54,0x61,0x73,0x6b,0x20,0x20, +0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x53,0x74,0x61,0x74,0x65,0x20,0x20,0x50, +0x72,0x69,0x6f,0x72,0x69,0x74,0x79,0x20,0x20,0x53,0x74,0x61,0x63,0x6b,0x09,0x23, +0x3c,0x62,0x72,0x3e,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a, +0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a, +0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a, +0x2a,0x2a,0x2a,0x2a,0x3c,0x62,0x72,0x3e,0x0d,0x0a,0x3c,0x21,0x2d,0x2d,0x23,0x72, +0x74,0x6f,0x73,0x5f,0x73,0x74,0x61,0x74,0x73,0x2d,0x2d,0x3e,0x0d,0x0a,0x3c,0x2f, +0x70,0x72,0x65,0x3e,0x3c,0x2f,0x66,0x6f,0x6e,0x74,0x3e,0x0d,0x0a,0x3c,0x2f,0x66, +0x6f,0x6e,0x74,0x3e,0x0d,0x0a,0x3c,0x2f,0x62,0x6f,0x64,0x79,0x3e,0x0d,0x0a,0x3c, +0x2f,0x68,0x74,0x6d,0x6c,0x3e,0x0d,0x0a,0x0d,0x0a,}; + +static const unsigned int dummy_align__logo_jpg = 2; +static const unsigned char data__logo_jpg[] = { +/* /logo.jpg (10 chars) */ +0x2f,0x6c,0x6f,0x67,0x6f,0x2e,0x6a,0x70,0x67,0x00,0x00,0x00, + +/* HTTP header */ +/* "HTTP/1.0 200 OK +" (17 bytes) */ +0x48,0x54,0x54,0x50,0x2f,0x31,0x2e,0x30,0x20,0x32,0x30,0x30,0x20,0x4f,0x4b,0x0d, +0x0a, +/* "Server: lwIP/1.3.1 (http://savannah.nongnu.org/projects/lwip) +" (63 bytes) */ +0x53,0x65,0x72,0x76,0x65,0x72,0x3a,0x20,0x6c,0x77,0x49,0x50,0x2f,0x31,0x2e,0x33, +0x2e,0x31,0x20,0x28,0x68,0x74,0x74,0x70,0x3a,0x2f,0x2f,0x73,0x61,0x76,0x61,0x6e, +0x6e,0x61,0x68,0x2e,0x6e,0x6f,0x6e,0x67,0x6e,0x75,0x2e,0x6f,0x72,0x67,0x2f,0x70, +0x72,0x6f,0x6a,0x65,0x63,0x74,0x73,0x2f,0x6c,0x77,0x69,0x70,0x29,0x0d,0x0a, +/* "Content-type: image/jpeg + +" (28 bytes) */ +0x43,0x6f,0x6e,0x74,0x65,0x6e,0x74,0x2d,0x74,0x79,0x70,0x65,0x3a,0x20,0x69,0x6d, +0x61,0x67,0x65,0x2f,0x6a,0x70,0x65,0x67,0x0d,0x0a,0x0d,0x0a, +/* raw file data (28602 bytes) */ +0xff,0xd8,0xff,0xe0,0x00,0x10,0x4a,0x46,0x49,0x46,0x00,0x01,0x01,0x00,0x00,0x01, +0x00,0x01,0x00,0x00,0xff,0xdb,0x00,0x43,0x00,0x03,0x02,0x02,0x03,0x02,0x02,0x03, +0x03,0x03,0x03,0x04,0x03,0x03,0x04,0x05,0x08,0x05,0x05,0x04,0x04,0x05,0x0a,0x07, +0x07,0x06,0x08,0x0c,0x0a,0x0c,0x0c,0x0b,0x0a,0x0b,0x0b,0x0d,0x0e,0x12,0x10,0x0d, +0x0e,0x11,0x0e,0x0b,0x0b,0x10,0x16,0x10,0x11,0x13,0x14,0x15,0x15,0x15,0x0c,0x0f, +0x17,0x18,0x16,0x14,0x18,0x12,0x14,0x15,0x14,0xff,0xdb,0x00,0x43,0x01,0x03,0x04, +0x04,0x05,0x04,0x05,0x09,0x05,0x05,0x09,0x14,0x0d,0x0b,0x0d,0x14,0x14,0x14,0x14, +0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14, +0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14, +0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0xff,0xc0, +0x00,0x11,0x08,0x00,0xea,0x02,0x71,0x03,0x01,0x22,0x00,0x02,0x11,0x01,0x03,0x11, +0x01,0xff,0xc4,0x00,0x1f,0x00,0x00,0x01,0x05,0x01,0x01,0x01,0x01,0x01,0x01,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09, +0x0a,0x0b,0xff,0xc4,0x00,0xb5,0x10,0x00,0x02,0x01,0x03,0x03,0x02,0x04,0x03,0x05, +0x05,0x04,0x04,0x00,0x00,0x01,0x7d,0x01,0x02,0x03,0x00,0x04,0x11,0x05,0x12,0x21, +0x31,0x41,0x06,0x13,0x51,0x61,0x07,0x22,0x71,0x14,0x32,0x81,0x91,0xa1,0x08,0x23, +0x42,0xb1,0xc1,0x15,0x52,0xd1,0xf0,0x24,0x33,0x62,0x72,0x82,0x09,0x0a,0x16,0x17, +0x18,0x19,0x1a,0x25,0x26,0x27,0x28,0x29,0x2a,0x34,0x35,0x36,0x37,0x38,0x39,0x3a, +0x43,0x44,0x45,0x46,0x47,0x48,0x49,0x4a,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5a, +0x63,0x64,0x65,0x66,0x67,0x68,0x69,0x6a,0x73,0x74,0x75,0x76,0x77,0x78,0x79,0x7a, +0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8a,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99, +0x9a,0xa2,0xa3,0xa4,0xa5,0xa6,0xa7,0xa8,0xa9,0xaa,0xb2,0xb3,0xb4,0xb5,0xb6,0xb7, +0xb8,0xb9,0xba,0xc2,0xc3,0xc4,0xc5,0xc6,0xc7,0xc8,0xc9,0xca,0xd2,0xd3,0xd4,0xd5, +0xd6,0xd7,0xd8,0xd9,0xda,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,0xea,0xf1, +0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xff,0xc4,0x00,0x1f,0x01,0x00,0x03, +0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01, +0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0xff,0xc4,0x00,0xb5,0x11,0x00, +0x02,0x01,0x02,0x04,0x04,0x03,0x04,0x07,0x05,0x04,0x04,0x00,0x01,0x02,0x77,0x00, +0x01,0x02,0x03,0x11,0x04,0x05,0x21,0x31,0x06,0x12,0x41,0x51,0x07,0x61,0x71,0x13, +0x22,0x32,0x81,0x08,0x14,0x42,0x91,0xa1,0xb1,0xc1,0x09,0x23,0x33,0x52,0xf0,0x15, +0x62,0x72,0xd1,0x0a,0x16,0x24,0x34,0xe1,0x25,0xf1,0x17,0x18,0x19,0x1a,0x26,0x27, +0x28,0x29,0x2a,0x35,0x36,0x37,0x38,0x39,0x3a,0x43,0x44,0x45,0x46,0x47,0x48,0x49, +0x4a,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5a,0x63,0x64,0x65,0x66,0x67,0x68,0x69, +0x6a,0x73,0x74,0x75,0x76,0x77,0x78,0x79,0x7a,0x82,0x83,0x84,0x85,0x86,0x87,0x88, +0x89,0x8a,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9a,0xa2,0xa3,0xa4,0xa5,0xa6, +0xa7,0xa8,0xa9,0xaa,0xb2,0xb3,0xb4,0xb5,0xb6,0xb7,0xb8,0xb9,0xba,0xc2,0xc3,0xc4, +0xc5,0xc6,0xc7,0xc8,0xc9,0xca,0xd2,0xd3,0xd4,0xd5,0xd6,0xd7,0xd8,0xd9,0xda,0xe2, +0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,0xea,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9, +0xfa,0xff,0xda,0x00,0x0c,0x03,0x01,0x00,0x02,0x11,0x03,0x11,0x00,0x3f,0x00,0xfd, +0x53,0xa2,0x8a,0x28,0x00,0xa2,0x8a,0x28,0x00,0xa2,0x8a,0x28,0x00,0xa4,0x34,0x8e, +0x70,0x09,0xaf,0x0b,0xf1,0xbf,0xc6,0x4b,0x8f,0x13,0x78,0xc2,0xdb,0xc1,0x7e,0x0f, +0xb8,0x2b,0x24,0x93,0x08,0xae,0xf5,0x48,0x88,0x3b,0x47,0xf1,0x2c,0x7f,0x4e,0x72, +0xdf,0x97,0xad,0x72,0x62,0x71,0x54,0xf0,0xb1,0xe6,0x9e,0xef,0x44,0xba,0xb6,0x73, +0x57,0xc4,0x43,0x0e,0x93,0x9e,0xef,0x44,0xba,0xb6,0x77,0xbe,0x3b,0xf8,0xb9,0xa1, +0xf8,0x16,0x39,0x23,0x9d,0xe4,0xd4,0x35,0x05,0x1c,0x58,0x59,0x2e,0xf9,0x3d,0xb7, +0x76,0x51,0xf5,0xfc,0x8d,0x78,0x07,0x8a,0xff,0x00,0x69,0x3f,0x1b,0x6a,0xb3,0x3a, +0x69,0x3a,0x7f,0xf6,0x2d,0xb7,0xf0,0x81,0x09,0x96,0x5f,0xc5,0x98,0x63,0xf2,0x15, +0xf4,0xde,0x83,0xe0,0xdd,0x27,0xc3,0xf6,0x62,0x0b,0x6b,0x38,0xc9,0x3f,0x33,0xcb, +0x20,0xde,0xf2,0x37,0x76,0x66,0x3c,0x92,0x6b,0x40,0xe9,0x16,0x47,0xad,0x9c,0x1f, +0xf7,0xec,0x57,0x9d,0x88,0xc2,0xe3,0x31,0x2b,0xf8,0xbc,0x8b,0xb2,0x5f,0xad,0xce, +0x3c,0x46,0x1b,0x13,0x88,0x56,0x8d,0x5e,0x45,0xe4,0xbf,0x53,0xe0,0x8d,0x4f,0xc6, +0xfe,0x33,0xd5,0x18,0x9b,0xcd,0x5f,0x56,0x90,0x93,0x9c,0x19,0xa4,0x0b,0xf9,0x0e, +0x2b,0x35,0x75,0xff,0x00,0x10,0xc7,0x9c,0x6a,0x3a,0x82,0xfa,0xfe,0xfa,0x41,0xfd, +0x6b,0xf4,0x19,0xb4,0x2d,0x39,0xba,0xd8,0x5b,0x7f,0xdf,0xa1,0xfe,0x15,0x19,0xf0, +0xce,0x94,0xff,0x00,0x7b,0x4d,0xb5,0x3f,0xf6,0xc5,0x7f,0xc2,0xbc,0x79,0x64,0x15, +0xa4,0xef,0xed,0xaf,0xf2,0x7f,0xe6,0x78,0x72,0xc8,0x6a,0x49,0xdd,0xd7,0x7f,0xd7, +0xcc,0xf8,0x0d,0x3c,0x5f,0xe2,0x68,0x94,0x05,0xd6,0x35,0x45,0x03,0xa0,0x17,0x32, +0x0f,0xeb,0x53,0x27,0x8f,0xbc,0x59,0x11,0x25,0x75,0xfd,0x59,0x33,0xe9,0x77,0x28, +0xfe,0xb5,0xf7,0x8b,0x78,0x3b,0x44,0x7e,0xba,0x4d,0x99,0xff,0x00,0xb6,0x2b,0x51, +0x37,0x81,0x7c,0x3c,0xf9,0xce,0x8d,0x66,0x73,0xff,0x00,0x4c,0x56,0xa5,0x64,0x58, +0x85,0xb5,0x6f,0xcc,0x9f,0xec,0x2a,0xeb,0x6a,0xef,0xf1,0xff,0x00,0x33,0xe1,0x6f, +0xf8,0x59,0x3e,0x2f,0x5f,0xf9,0x98,0xb5,0x7f,0xfc,0x0c,0x93,0xfc,0x69,0xeb,0xf1, +0x4f,0xc6,0x51,0x9c,0xaf,0x89,0x35,0x5c,0xfb,0xdd,0x3f,0xf8,0xd7,0xdc,0x0d,0xf0, +0xf3,0xc3,0x6f,0xd7,0x44,0xb2,0x3f,0xf6,0xc8,0x54,0x4f,0xf0,0xcb,0xc2,0xaf,0xf7, +0xb4,0x2b,0x23,0xff,0x00,0x6c,0x85,0x2f,0xec,0x4c,0x5f,0xfc,0xfe,0xfc,0xc5,0xfd, +0x89,0x8a,0x5b,0x57,0x7f,0x89,0xf1,0x54,0x7f,0x17,0xfc,0x6b,0x1f,0xfc,0xcc,0x9a, +0x99,0xfa,0xdc,0x35,0x58,0x8b,0xe3,0x87,0x8e,0xe1,0x6c,0xaf,0x89,0x2f,0x73,0xd3, +0xe6,0x21,0x87,0xe4,0x45,0x7d,0x8e,0xff,0x00,0x09,0x7c,0x20,0xfd,0x74,0x0b,0x3f, +0xc2,0x3c,0x54,0x2f,0xf0,0x6b,0xc1,0xaf,0xd7,0x41,0xb5,0x1f,0x45,0xa4,0xb2,0x7c, +0x72,0xda,0xb7,0xe2,0xc7,0xfd,0x8f,0x8d,0x5b,0x62,0x1f,0xe2,0x7c,0x8a,0x9f,0x1f, +0xbc,0x7e,0x83,0x1f,0xf0,0x91,0x5c,0x7d,0x4c,0x71,0x9f,0xfd,0x96,0xa6,0x1f,0xb4, +0x37,0x8f,0xc7,0xfc,0xcc,0x12,0xfe,0x30,0x45,0xff,0x00,0xc4,0x57,0xd5,0xaf,0xf0, +0x43,0xc1,0x4e,0x0f,0xfc,0x48,0xa0,0x1f,0x4a,0x89,0xbe,0x03,0xf8,0x21,0xf3,0xff, +0x00,0x12,0x48,0x86,0x7d,0x09,0xa7,0xfd,0x95,0x98,0xad,0xab,0x7e,0x2c,0x3f,0xb2, +0xb3,0x15,0xb6,0x21,0xfd,0xec,0xf9,0x69,0x7f,0x68,0xaf,0x1f,0x8f,0xf9,0x8f,0x39, +0xfa,0xdb,0xc5,0xff,0x00,0xc4,0xd4,0x89,0xfb,0x48,0x78,0xf9,0x08,0x3f,0xdb,0x59, +0xc7,0xad,0xb4,0x47,0xff,0x00,0x65,0xaf,0xa6,0x9f,0xf6,0x7d,0xf0,0x33,0x8e,0x74, +0x75,0x1e,0xe1,0x8d,0x42,0xff,0x00,0xb3,0x9f,0x81,0x9c,0x7f,0xc8,0x2d,0x97,0xe9, +0x21,0xa3,0xfb,0x33,0x34,0x5b,0x56,0xff,0x00,0xc9,0x98,0xbf,0xb3,0x33,0x35,0xb5, +0x7f,0xc5,0x9f,0x39,0xc7,0xfb,0x4d,0xf8,0xf1,0x17,0x07,0x52,0x85,0xcf,0xab,0x5a, +0xa6,0x7f,0x95,0x58,0x4f,0xda,0x9b,0xc7,0x49,0x8f,0xf4,0x9b,0x36,0xc7,0xad,0xaa, +0xf3,0xfa,0xd7,0xbe,0xbf,0xec,0xd5,0xe0,0x86,0xc9,0x16,0x32,0xaf,0xd2,0x43,0x50, +0x3f,0xec,0xc5,0xe0,0xa6,0xe9,0x6f,0x3a,0xff,0x00,0xdb,0x4a,0x5f,0xd9,0xf9,0xb2, +0xda,0xaf,0xfe,0x4c,0xc3,0xfb,0x3f,0x36,0x5b,0x57,0xfc,0x59,0xe2,0x0b,0xfb,0x57, +0x78,0xdd,0x7a,0x9d,0x39,0xbe,0xb6,0xc7,0xfa,0x35,0x3d,0x7f,0x6b,0x0f,0x1a,0x82, +0x32,0x9a,0x61,0xff,0x00,0xb7,0x66,0xff,0x00,0xe2,0xeb,0xd9,0xdb,0xf6,0x5a,0xf0, +0x63,0x0e,0x12,0xe5,0x7f,0xed,0xa5,0x42,0xff,0x00,0xb2,0xa7,0x83,0xcf,0x47,0xbb, +0x5f,0xfb,0x69,0x43,0xc1,0xe7,0x0b,0x6a,0x9f,0xf9,0x30,0x7d,0x4b,0x37,0x5b,0x56, +0xfc,0x4f,0x23,0x5f,0xda,0xd7,0xc6,0x43,0xad,0xbe,0x96,0xdf,0xf6,0xc1,0xff,0x00, +0xf8,0xba,0x91,0x3f,0x6b,0x8f,0x16,0x82,0x37,0x59,0x69,0x6d,0xeb,0xfb,0xa7,0xff, +0x00,0xe2,0xeb,0xd4,0x24,0xfd,0x93,0xbc,0x2a,0xd8,0xdb,0x75,0x78,0xbf,0xf0,0x20, +0x6a,0x07,0xfd,0x92,0x3c,0x34,0x73,0x8b,0xfb,0xb5,0xf4,0xe9,0x4b,0xea,0xb9,0xca, +0xfb,0x7f,0x88,0x7d,0x53,0x39,0x5b,0x55,0xfc,0x4f,0x3d,0x8b,0xf6,0xbe,0xf1,0x32, +0xe7,0xcc,0xd2,0xb4,0xc7,0xf4,0xc2,0xc8,0x3f,0xf6,0x6a,0xb0,0x9f,0xb6,0x16,0xbc, +0x31,0xbb,0x43,0xd3,0x5b,0xd7,0x0d,0x20,0xfe,0xb5,0xda,0xc9,0xfb,0x22,0xe8,0x19, +0xf9,0x75,0x3b,0xa0,0x3d,0xd4,0x54,0x0f,0xfb,0x21,0x68,0xe4,0x7c,0xba,0xbd,0xcf, +0xe2,0x82,0x9f,0xb1,0xce,0x97,0xda,0xfc,0x50,0x7b,0x0c,0xe9,0x7d,0xbf,0xc8,0xe6, +0x07,0xed,0x89,0xaa,0xf7,0xf0,0xf5,0x99,0xfa,0x4e,0xdf,0xe1,0x4f,0x5f,0xdb,0x1b, +0x50,0x1f,0x7b,0xc3,0x96,0xa7,0xe9,0x72,0xdf,0xfc,0x4d,0x6f,0x3f,0xec,0x7f,0xa6, +0x1c,0xed,0xd6,0xe7,0x5f,0xac,0x60,0xd4,0x12,0x7e,0xc7,0xb6,0x99,0x1b,0x35,0xd9, +0x31,0xef,0x17,0xff,0x00,0x5e,0x8e,0x4c,0xed,0x75,0xfc,0x85,0xec,0xf3,0xb5,0xf6, +0xbf,0x23,0x35,0x7f,0x6c,0x7b,0xc3,0xf7,0xbc,0x35,0x01,0x1e,0xd7,0x67,0xff,0x00, +0x89,0xa9,0x93,0xf6,0xc8,0x70,0x06,0xef,0x0b,0xa9,0x3d,0xf1,0x7b,0xff,0x00,0xd8, +0x54,0xaf,0xfb,0x1e,0xa0,0x5f,0x97,0x5d,0xe7,0xde,0x2a,0x85,0xbf,0x63,0xe9,0x32, +0x76,0xeb,0xa9,0xed,0x98,0x8d,0x2f,0xf8,0x5b,0x5d,0xff,0x00,0xf2,0x50,0xb6,0x76, +0xba,0xfe,0x44,0xeb,0xfb,0x64,0xc4,0x7e,0xf7,0x85,0xdf,0x1e,0xd7,0xa3,0xff,0x00, +0x8d,0xd4,0xcb,0xfb,0x63,0xda,0x63,0xe6,0xf0,0xcc,0xc0,0xfb,0x5e,0x03,0xff,0x00, +0xb2,0x56,0x63,0xfe,0xc7,0xd7,0x7d,0xb5,0xc8,0x4f,0xd5,0x0d,0x40,0xff,0x00,0xb2, +0x06,0xa6,0x01,0xdb,0xad,0x5b,0x13,0xee,0x84,0x53,0xf6,0x99,0xda,0xe8,0xfe,0xe8, +0x87,0x3e,0x78,0xbf,0xa4,0x6f,0x27,0xed,0x8b,0xa7,0x13,0xcf,0x87,0x2e,0x40,0xff, +0x00,0xaf,0x95,0x3f,0xfb,0x2d,0x48,0x3f,0x6c,0x3d,0x27,0x1f,0x37,0x87,0xaf,0x01, +0xf6,0x9d,0x0f,0xf4,0xae,0x59,0xbf,0x64,0x2d,0x68,0x1e,0x35,0x6b,0x53,0xef,0x83, +0x50,0x37,0xec,0x8d,0xe2,0x11,0xf7,0x75,0x0b,0x46,0xfc,0x4d,0x4f,0xb7,0xce,0x97, +0xd9,0x7f,0x72,0x17,0xb5,0xce,0xd7,0xd9,0xfc,0x11,0xdd,0x45,0xfb,0x5f,0xf8,0x74, +0xb7,0xcf,0xa3,0x6a,0x4a,0x3d,0x54,0xc6,0x7f,0xf6,0x6a,0xb3,0x1f,0xed,0x75,0xe1, +0x36,0x5c,0xbe,0x9b,0xab,0x2b,0x7a,0x08,0xe3,0x3f,0xfb,0x3d,0x79,0xb4,0x9f,0xb2, +0x67,0x89,0x54,0x1c,0x5e,0x5a,0x13,0xfe,0xf1,0xa8,0x1b,0xf6,0x50,0xf1,0x5f,0x69, +0xad,0x1b,0xfe,0x07,0x42,0xc5,0x67,0x0b,0xec,0x3f,0xb9,0x0f,0xeb,0x39,0xd2,0xfb, +0x1f,0x82,0x3d,0x54,0x7e,0xd6,0xfe,0x0e,0xce,0x0d,0x96,0xae,0x07,0xaf,0x93,0x1f, +0xff,0x00,0x17,0x4f,0x1f,0xb5,0xaf,0x83,0x31,0xff,0x00,0x1e,0xba,0xb7,0xfd,0xf8, +0x4f,0xfe,0x2e,0xbc,0x85,0xbf,0x65,0x4f,0x18,0x0f,0xbb,0xf6,0x46,0xff,0x00,0xb6, +0xb5,0x03,0xfe,0xcb,0xbe,0x34,0x4c,0xe2,0x0b,0x76,0x03,0xd2,0x51,0x43,0xc7,0x66, +0xeb,0x7a,0x7f,0xf9,0x28,0x7d,0x73,0x39,0x5f,0xf2,0xeb,0xf0,0x3d,0xa9,0x7f,0x6a, +0xff,0x00,0x05,0x36,0x3f,0x75,0xa9,0xaf,0xd6,0xdd,0x7f,0xf8,0xaa,0x91,0x7f,0x6a, +0xaf,0x04,0x11,0xc9,0xd4,0x53,0xeb,0x6c,0x3f,0xf8,0xaa,0xf0,0xb6,0xfd,0x99,0x7c, +0x6c,0xbd,0x2c,0xe2,0x3f,0x49,0x45,0x42,0xff,0x00,0xb3,0x67,0x8d,0xd4,0x7f,0xc8, +0x3d,0x4f,0xd1,0xc5,0x2f,0xed,0x1c,0xd5,0x7f,0xcb,0xbf,0xfc,0x95,0x8b,0xeb,0xf9, +0xba,0xff,0x00,0x97,0x5f,0x87,0xfc,0x13,0xe8,0x48,0xbf,0x69,0xef,0x01,0xc8,0xe0, +0x1b,0xeb,0xa8,0xc1,0xfe,0x26,0xb5,0x6c,0x0f,0xca,0xad,0x2f,0xed,0x27,0xf0,0xfd, +0x81,0x3f,0xdb,0x2e,0xbe,0xc6,0xd6,0x5f,0xfe,0x26,0xbe,0x6b,0x6f,0xd9,0xd7,0xc7, +0x0a,0x78,0xd2,0xc9,0xc7,0xa3,0x8a,0x81,0xff,0x00,0x67,0xef,0x1c,0xa9,0xff,0x00, +0x90,0x34,0x87,0xe8,0xc0,0xff,0x00,0x5a,0x7f,0xda,0x99,0x9c,0x77,0xa5,0xff,0x00, +0x92,0xb0,0xfe,0xd2,0xcd,0x56,0xf4,0x7f,0x06,0x7d,0x42,0x3f,0x68,0x9f,0x87,0xcd, +0xff,0x00,0x33,0x02,0x8f,0xad,0xb4,0xdf,0xfc,0x45,0x38,0x7e,0xd0,0x9f,0x0f,0xcf, +0x4f,0x11,0x47,0xff,0x00,0x80,0xf2,0x8f,0xfd,0x92,0xbe,0x55,0x6f,0x81,0x3e,0x37, +0x43,0xce,0x89,0x37,0xe1,0x51,0x3f,0xc1,0x4f,0x1a,0x27,0x5d,0x0e,0xe7,0x8f,0x6a, +0x6f,0x38,0xcc,0x16,0xf4,0xbf,0xf2,0x59,0x07,0xf6,0xae,0x64,0xb7,0xa1,0xf8,0x3f, +0xf3,0x3e,0xb2,0x1f,0x1f,0xfc,0x00,0xd8,0xff,0x00,0x8a,0x8e,0x1e,0x7d,0x62,0x93, +0xff,0x00,0x89,0xa9,0xd3,0xe3,0xaf,0x80,0xdc,0x64,0x78,0x92,0xd4,0x7d,0x43,0x8f, +0xe9,0x5f,0x1f,0xbf,0xc1,0xff,0x00,0x18,0xa0,0xe7,0x42,0xba,0xe7,0xfd,0x9a,0x85, +0xbe,0x14,0xf8,0xb9,0x3a,0xe8,0x77,0x7f,0xf7,0xc5,0x2f,0xed,0xac,0x72,0xff,0x00, +0x97,0x4b,0xee,0x62,0xfe,0xd8,0xc7,0xad,0xe8,0x7e,0x0c,0xfb,0x3d,0x3e,0x32,0xf8, +0x21,0xc0,0xc7,0x89,0xb4,0xfe,0x7d,0x65,0xc5,0x48,0x9f,0x17,0x7c,0x14,0xf9,0xc7, +0x89,0xf4,0xce,0x3d,0x6e,0x14,0x57,0xc4,0xef,0xf0,0xd3,0xc5,0x51,0x9f,0x9b,0x44, +0xbd,0x1f,0xf6,0xc8,0xd4,0x0d,0xe0,0x0f,0x12,0x27,0x5d,0x1e,0xf0,0x7f,0xdb,0x23, +0x47,0xf6,0xee,0x29,0x6f,0x49,0x7e,0x23,0xfe,0xdb,0xc6,0x2d,0xe8,0x7e,0x67,0xdc, +0x63,0xe2,0xbf,0x83,0x4f,0x4f,0x13,0xe9,0x7f,0xf8,0x16,0x9f,0xe3,0x52,0x2f,0xc4, +0xef,0x09,0x36,0x71,0xe2,0x5d,0x2f,0x8f,0xfa,0x7b,0x4f,0xf1,0xaf,0x85,0x1b,0xc1, +0x5e,0x20,0x5e,0xba,0x55,0xd0,0xff,0x00,0xb6,0x46,0xa2,0x6f,0x0a,0x6b,0x69,0xd7, +0x4c,0xba,0x1f,0xf6,0xc8,0xd1,0xfd,0xbf,0x89,0xeb,0x49,0x7e,0x22,0xfe,0xdd,0xc5, +0x2d,0xe8,0x7e,0x67,0xde,0xc9,0xf1,0x07,0xc2,0xf2,0x80,0x57,0xc4,0x3a,0x59,0x07, +0xa7,0xfa,0x64,0x7f,0xe3,0x56,0x13,0xc6,0x5a,0x04,0x9f,0x77,0x5a,0xd3,0x9b,0x1e, +0x97,0x49,0xfe,0x35,0xf9,0xfa,0xde,0x1c,0xd5,0xd7,0xae,0x9f,0x72,0x3f,0xed,0x91, +0xa8,0xce,0x89,0xa9,0x27,0x06,0xca,0xe0,0x7d,0x63,0x34,0xd7,0x10,0xd6,0x5b,0xd3, +0x5f,0x8f,0xf9,0x0f,0xfb,0x7e,0xbf,0x5a,0x1f,0x99,0xfa,0x1a,0x9e,0x23,0xd2,0x64, +0x50,0x57,0x54,0xb3,0x60,0x7a,0x62,0xe1,0x3f,0xc6,0x9f,0xfd,0xbb,0xa6,0x9e,0x9a, +0x8d,0xa9,0xff,0x00,0xb6,0xeb,0xfe,0x35,0xf9,0xd8,0x74,0xbb,0xe1,0xd6,0xd6,0x61, +0xff,0x00,0x00,0x34,0xc3,0x61,0x78,0xbd,0x60,0x90,0x7d,0x54,0xd3,0xff,0x00,0x58, +0xe7,0xd6,0x97,0xe3,0xff,0x00,0x00,0x7f,0xeb,0x0d,0x45,0xff,0x00,0x2e,0x7f,0x1f, +0xf8,0x07,0xe8,0xca,0x6a,0xf6,0x2e,0x32,0x2f,0x2d,0xd8,0x7a,0x89,0x54,0xff,0x00, +0x5a,0x78,0xd4,0x6d,0x49,0xe2,0xe6,0x03,0xf4,0x90,0x7f,0x8d,0x7e,0x71,0x7d,0x9e, +0xed,0x7f,0xe5,0x9c,0xa3,0xf0,0x34,0xb9,0xbb,0x43,0xff,0x00,0x2d,0x47,0xe7,0x47, +0xfa,0xc7,0x2f,0xf9,0xf5,0xf8,0xff,0x00,0xc0,0x0f,0xf5,0x8a,0x56,0xd6,0x8b,0xfb, +0xff,0x00,0xe0,0x1f,0xa4,0x0b,0x75,0x13,0x8c,0xac,0xa8,0xc3,0xd4,0x30,0x34,0xf1, +0x20,0x3d,0xc1,0xfc,0x6b,0xf3,0x78,0x5e,0x5e,0xa7,0x49,0x66,0x51,0xec,0xcd,0x53, +0x2e,0xb5,0xaa,0xc6,0xc0,0xad,0xf5,0xda,0x9f,0x51,0x33,0x83,0xfc,0xea,0xd7,0x11, +0xf7,0xa5,0xf8,0xff,0x00,0xc0,0x29,0x71,0x1a,0xeb,0x49,0xfd,0xff,0x00,0xf0,0x0f, +0xd1,0xb0,0xc3,0xd6,0x97,0x75,0x7e,0x74,0x0f,0x13,0x6b,0x4a,0x30,0x35,0x4b,0xe5, +0xfa,0x5c,0x3f,0xf8,0xd2,0x8f,0x16,0x6b,0x8a,0x72,0x35,0x7d,0x40,0x1f,0xfa,0xfa, +0x93,0xfc,0x6a,0xff,0x00,0xd6,0x38,0xff,0x00,0xcf,0xbf,0xc7,0xfe,0x00,0xff,0x00, +0xd6,0x48,0x75,0xa4,0xfe,0xf3,0xf4,0x58,0x36,0x69,0x6b,0xf3,0xb1,0x7c,0x6b,0xe2, +0x04,0x04,0x0d,0x6b,0x51,0x1f,0xf6,0xf5,0x27,0xf8,0xd5,0x88,0xfe,0x23,0x78,0xa2, +0x10,0x36,0x78,0x83,0x54,0x5c,0x70,0x31,0x79,0x27,0xf8,0xd3,0x5c,0x45,0x0e,0xb4, +0xdf,0xde,0x52,0xe2,0x4a,0x5d,0x69,0xb3,0xf4,0x32,0x8a,0xfc,0xf9,0x5f,0x8a,0x5e, +0x2e,0x41,0x81,0xe2,0x4d,0x54,0x0f,0xfa,0xfb,0x73,0xfd,0x6a,0xc2,0x7c,0x62,0xf1, +0xaa,0x63,0x1e,0x26,0xd4,0xb8,0xe9,0xfb,0xf2,0x6a,0xd7,0x11,0x52,0xeb,0x4d,0xfe, +0x05,0x7f,0xac,0x94,0x3a,0xc1,0xfe,0x07,0xdf,0xd4,0x57,0xc0,0xa3,0xe3,0x57,0x8d, +0xd7,0xfe,0x66,0x6d,0x43,0xf1,0x97,0xff,0x00,0xad,0x4f,0x4f,0x8d,0xfe,0x38,0x5c, +0x7f,0xc5,0x4b,0x7c,0x71,0xea,0xe0,0xff,0x00,0x4a,0xaf,0xf5,0x8a,0x87,0xf2,0x3f, +0xc0,0xaf,0xf5,0x8f,0x0d,0xfc,0x8f,0xf0,0x3e,0xf7,0xa2,0xbe,0x0c,0x5f,0x8e,0xde, +0x3a,0x5e,0x9e,0x24,0xbc,0xfc,0x76,0x9f,0xe9,0x56,0x53,0xf6,0x84,0xf1,0xea,0x63, +0xfe,0x2a,0x19,0x8e,0x3d,0x61,0x8c,0xff,0x00,0xec,0xb4,0xd7,0x11,0x61,0xdf,0xd8, +0x97,0xe1,0xfe,0x65,0x2e,0x22,0xc2,0xf5,0x8c,0xbf,0x0f,0xf3,0x3e,0xea,0xa2,0xbe, +0x1c,0x8b,0xf6,0x8e,0xf1,0xf4,0x44,0x9f,0xed,0xc2,0xd9,0xfe,0xf5,0xbc,0x47,0xff, +0x00,0x65,0xab,0xf6,0x3f,0xb5,0x17,0x8e,0xed,0x26,0x57,0x96,0xee,0xd2,0xed,0x07, +0x54,0x9a,0xd5,0x40,0x3f,0xf7,0xce,0x0d,0x68,0xb8,0x83,0x0a,0xf7,0x4f,0xf0,0xff, +0x00,0x32,0xd7,0x10,0xe0,0xde,0xe9,0xaf,0x97,0xfc,0x13,0xed,0x4a,0x2b,0xe6,0x2f, +0x0c,0xfe,0xd8,0x52,0x06,0x58,0xfc,0x41,0xa1,0x86,0x5e,0xf3,0xe9,0xcf,0x83,0xed, +0xf2,0x39,0xff,0x00,0xd9,0xab,0xda,0xbc,0x15,0xf1,0x6f,0xc2,0xfe,0x3f,0x5d,0xba, +0x46,0xa9,0x1c,0x97,0x40,0x65,0xad,0x26,0xfd,0xdc,0xcb,0xff,0x00,0x01,0x3d,0x7e, +0xa3,0x22,0xbd,0x6c,0x3e,0x63,0x86,0xc4,0xe9,0x4e,0x7a,0xf6,0xd9,0x9e,0xa6,0x1f, +0x32,0xc2,0xe2,0x9d,0xa9,0xcd,0x5f,0xb6,0xcc,0xec,0xe8,0xa6,0xa9,0xcd,0x3a,0xbd, +0x13,0xd3,0x0a,0x28,0xa2,0x80,0x0a,0x28,0xa2,0x80,0x0a,0x28,0xa2,0x80,0x0a,0x42, +0x69,0x6a,0xbd,0xe5,0xd4,0x56,0x56,0xd3,0x5c,0x4f,0x22,0xc5,0x04,0x48,0x5d,0xdd, +0xce,0x02,0xa8,0x19,0x24,0x9a,0x4f,0x45,0x71,0x37,0x65,0x76,0x78,0x6f,0xed,0x35, +0xf1,0x65,0xfc,0x33,0xa6,0x2f,0x86,0xb4,0xb9,0xb6,0x6a,0x57,0xd1,0xee,0xb8,0x95, +0x1b,0x0d,0x0c,0x3d,0x30,0x3d,0x0b,0x72,0x3e,0x80,0xfa,0x8a,0xe4,0xbf,0x64,0xbf, +0x08,0xfd,0xa7,0x55,0xbe,0xd7,0x66,0x43,0xb6,0xdd,0x7c,0xa8,0x8f,0x6d,0xc7,0xad, +0x78,0x9f,0x8c,0xbc,0x4d,0x71,0xe3,0x9f,0x17,0xea,0x3a,0xbc,0xdb,0x8b,0xde,0x4e, +0x5a,0x34,0x3d,0x51,0x33,0x84,0x5f,0xc0,0x00,0x2b,0xed,0x7f,0x82,0x9e,0x13,0x1e, +0x11,0xf8,0x7d,0xa6,0xdb,0x15,0xdb,0x3c,0xa9,0xe7,0xcb,0x91,0x83,0xb9,0xb9,0xaf, +0x89,0xc3,0x4e,0x59,0x96,0x64,0xea,0xbf,0x86,0x1b,0x7e,0x9f,0xe6,0x7c,0x56,0x0a, +0xa4,0xb3,0x3c,0xc1,0xd7,0x97,0xc3,0x0d,0xbf,0x4f,0xf3,0x3b,0xb0,0x31,0x4b,0x45, +0x15,0xf6,0xe7,0xdb,0x09,0x4b,0x45,0x14,0x00,0x53,0x43,0x83,0xd2,0x9d,0x5e,0x0f, +0xf1,0xcb,0xf6,0xdc,0xf8,0x3b,0xfb,0x3e,0x5c,0xc9,0x61,0xe2,0xaf,0x16,0xc2,0xfa, +0xda,0x02,0x7f,0xb1,0xf4,0xc4,0x6b,0xbb,0xa0,0x47,0x66,0x54,0xc8,0x8c,0x9e,0xde, +0x61,0x5c,0xd0,0x07,0xba,0x89,0x01,0x6d,0xbc,0xe7,0xdc,0x1a,0x7d,0x7e,0x71,0xeb, +0xdf,0xf0,0x5a,0xdf,0x00,0x5b,0xb3,0x0d,0x1b,0xe1,0xf7,0x89,0x2f,0x80,0xe8,0xd7, +0xd3,0xdb,0xdb,0xe7,0xf0,0x56,0x92,0xbe,0x9f,0xfd,0x94,0x7f,0x6a,0xb8,0xbf,0x69, +0x8f,0x85,0xfa,0xaf,0x8f,0x2e,0x7c,0x36,0xfe,0x0b,0xd0,0xac,0xae,0x64,0xb7,0x59, +0xef,0xef,0x92,0x44,0x91,0x63,0x40,0xd2,0xca,0x5b,0x6a,0x85,0x45,0xce,0x32,0x7d, +0x1b,0xa6,0x28,0x11,0xef,0xb4,0x57,0x17,0x6d,0xf1,0xb3,0xe1,0xe5,0xeb,0x2a,0xdb, +0xf8,0xf3,0xc3,0x33,0xb3,0x1c,0x05,0x8b,0x58,0xb7,0x62,0x4f,0xe0,0xf5,0xd9,0x83, +0x9e,0x94,0x0c,0x5a,0x2b,0x33,0x5f,0xf1,0x1e,0x9f,0xe1,0x7d,0x3d,0xaf,0xb5,0x3b, +0x91,0x6b,0x6a,0xac,0x14,0xb9,0x52,0xdc,0x93,0x80,0x30,0x01,0x35,0x81,0x17,0xc5, +0xff,0x00,0x07,0xcd,0xd3,0x5d,0x80,0x7f,0xbe,0xae,0xbf,0xcc,0x57,0x34,0xf1,0x34, +0x69,0x4b,0x96,0xa4,0xd2,0x7e,0x6d,0x22,0x1c,0xe1,0x17,0x66,0xd2,0x3b,0x1a,0x31, +0x5c,0xcc,0x7f,0x12,0xfc,0x2b,0x26,0x31,0xe2,0x0b,0x01,0x9f,0xef,0x4e,0xa3,0xf9, +0xd4,0xc3,0xe2,0x0f,0x86,0x0f,0x4f,0x10,0xe9,0x9f,0xf8,0x16,0x9f,0xe3,0x49,0x62, +0xb0,0xef,0x6a,0x8b,0xef,0x42,0xf6,0x90,0xfe,0x64,0x74,0x34,0x56,0x12,0xf8,0xe7, +0xc3,0x8e,0x78,0xd7,0xf4,0xc3,0xff,0x00,0x6f,0x91,0xff,0x00,0x8d,0x58,0x8b,0xc5, +0x3a,0x34,0xe3,0xf7,0x7a,0xb5,0x8c,0x9f,0xee,0xdc,0x21,0xfe,0xb5,0xa2,0xad,0x4d, +0xed,0x25,0xf7,0x8f,0x9a,0x2f,0x66,0x6a,0xd1,0x55,0x13,0x55,0xb2,0x97,0x95,0xbb, +0x81,0xbf,0xdd,0x95,0x4f,0xf5,0xa9,0x96,0x78,0xa4,0xfb,0xb2,0x2b,0x7d,0x1a,0xaf, +0x9e,0x2f,0x66,0x55,0xd1,0x2d,0x14,0xdd,0xdd,0xc1,0xa5,0x07,0x35,0x43,0x16,0x8a, +0x28,0xa6,0x01,0x45,0x21,0xe9,0x49,0x9a,0x00,0x75,0x26,0x29,0x32,0x3d,0x69,0x73, +0x48,0x05,0xa4,0xc5,0x18,0xf7,0xa5,0xa6,0x02,0x62,0x96,0x8a,0x28,0x00,0xa2,0x8a, +0x28,0x01,0x29,0x68,0xa2,0x80,0x12,0x8c,0x52,0xd1,0x40,0x05,0x14,0x51,0x40,0x05, +0x26,0x29,0x68,0xa0,0x04,0xc5,0x18,0x1e,0x94,0xb4,0x50,0x02,0x6d,0x1e,0x82,0x93, +0xcb,0x53,0xfc,0x23,0xf2,0xa0,0x92,0x3f,0x87,0x3f,0x8d,0x28,0xcf,0x71,0x8a,0x00, +0x69,0x82,0x33,0xd6,0x35,0x3f,0x80,0xa6,0x9b,0x58,0x5b,0xac,0x48,0x7f,0xe0,0x22, +0xa5,0xa2,0x95,0x97,0x61,0x59,0x10,0x1b,0x1b,0x73,0xd6,0x08,0xff,0x00,0xef,0x91, +0x4d,0x3a,0x6d,0xa3,0x75,0xb6,0x84,0xfd,0x50,0x55,0x9a,0x29,0x72,0xc7,0xb0,0x59, +0x14,0x9b,0x46,0xb0,0x6e,0xb6,0x56,0xe7,0xfe,0xd9,0x8f,0xf0,0xa8,0xdb,0xc3,0xba, +0x5b,0x75,0xd3,0xed,0x8f,0xfd,0xb2,0x5f,0xf0,0xad,0x1a,0x29,0x7b,0x38,0x76,0x17, +0x2a,0xec,0x64,0xb7,0x85,0x74,0x76,0xeb,0xa6,0x5a,0x9f,0xfb,0x64,0xbf,0xe1,0x51, +0xb7,0x83,0x74,0x36,0xeb,0xa4,0xda,0x1f,0xac,0x23,0xfc,0x2b,0x6a,0x8a,0x9f,0x65, +0x4f,0xf9,0x57,0xdc,0x2e,0x48,0x76,0x30,0x1f,0xc0,0x9e,0x1e,0x93,0xef,0x68,0xd6, +0x67,0xfe,0xd8,0x8a,0x89,0xbe,0x1c,0xf8,0x65,0xba,0xe8,0x96,0x7f,0xf7,0xec,0x57, +0x49,0x45,0x4b,0xc3,0xd2,0x7b,0xc1,0x7d,0xc4,0xfb,0x28,0x3f,0xb2,0x8e,0x55,0xbe, +0x17,0xf8,0x55,0xfa,0xe8,0x96,0x9f,0xf7,0xc5,0x42,0xdf,0x09,0x3c,0x22,0xdd,0x74, +0x3b,0x5f,0xfb,0xe6,0xba,0xfa,0x5a,0x8f,0xaa,0xd0,0xfe,0x45,0xf7,0x21,0x7b,0x1a, +0x5f,0xca,0xbe,0xe3,0x89,0x7f,0x83,0x7e,0x0e,0x7e,0xba,0x1d,0xb7,0xe5,0x50,0x3f, +0xc0,0xff,0x00,0x05,0x3f,0xfc,0xc0,0xe0,0x1f,0x4c,0xd7,0x7b,0x45,0x4b,0xc1,0xe1, +0xdf,0xfc,0xbb,0x5f,0x72,0x27,0xea,0xf4,0x7f,0x91,0x7d,0xc7,0x9e,0x3f,0xc0,0x5f, +0x04,0xbf,0xfc,0xc1,0xa3,0x1f,0x46,0x35,0x0b,0xfe,0xcf,0x7e,0x09,0x7f,0xf9,0x85, +0x63,0xe8,0xe6,0xbd,0x23,0x34,0x64,0x7a,0xd4,0x7d,0x47,0x0b,0xff,0x00,0x3e,0xd7, +0xdc,0x88,0xfa,0xa5,0x0f,0xe4,0x5f,0x71,0xe6,0x0f,0xfb,0x39,0x78,0x25,0xff,0x00, +0xe6,0x1c,0xc3,0xe8,0xf5,0x0b,0xfe,0xcd,0x5e,0x09,0x7f,0xf9,0x72,0x90,0x7d,0x24, +0xaf,0x55,0xa2,0xa7,0xfb,0x3f,0x08,0xff,0x00,0xe5,0xda,0xfb,0x89,0xfa,0x96,0x19, +0xef,0x4d,0x7d,0xc7,0x92,0x3f,0xec,0xc5,0xe0,0xb6,0xe9,0x05,0xc2,0xff,0x00,0xdb, +0x4a,0x81,0xff,0x00,0x65,0xcf,0x07,0xb7,0x41,0x72,0xbf,0xf6,0xd2,0xbd,0x8e,0x8a, +0x9f,0xec,0xcc,0x1b,0xff,0x00,0x97,0x4b,0xee,0x27,0xea,0x18,0x57,0xff,0x00,0x2e, +0xd7,0xdc,0x78,0xb3,0xfe,0xca,0xbe,0x12,0x6e,0x92,0x5d,0x2f,0xfc,0x08,0x54,0x2f, +0xfb,0x27,0xf8,0x5d,0xba,0x5c,0xdd,0x0f,0xc4,0x57,0xb7,0xd1,0x51,0xfd,0x95,0x82, +0xff,0x00,0x9f,0x48,0x97,0x97,0x61,0x1f,0xfc,0xbb,0x47,0x84,0xbf,0xec,0x95,0xe1, +0xb6,0xe9,0x7d,0x76,0x3f,0x2a,0xa5,0x77,0xfb,0x24,0x69,0xd0,0x95,0x9f,0x4e,0xd6, +0x6e,0xed,0xae,0xe3,0x21,0xe2,0x90,0x60,0x15,0x61,0xd0,0x82,0x39,0x06,0xbe,0x83, +0xa4,0x3d,0x29,0x7f,0x64,0xe0,0xf7,0x54,0xed,0xf7,0x99,0xbc,0xaf,0x07,0x2f,0xf9, +0x76,0x8f,0x01,0xf0,0x97,0xc6,0x3d,0x4f,0xe1,0xff,0x00,0x89,0xd3,0xc2,0x5e,0x3e, +0xb9,0x59,0xa1,0x77,0x10,0xda,0x6b,0xa4,0x6d,0xcb,0x67,0x01,0x66,0xed,0xcf,0x1f, +0x3f,0xe7,0xeb,0x5e,0xfa,0x8c,0x18,0x70,0x72,0x3d,0x6b,0xe3,0x1f,0xda,0x88,0xa5, +0xee,0xbb,0x24,0x4c,0x01,0x05,0x88,0xc7,0xad,0x77,0x1f,0xb1,0xff,0x00,0xc6,0x49, +0xbc,0x47,0x65,0x79,0xe0,0x6d,0x66,0xe9,0xa6,0xd5,0xf4,0xa8,0x84,0xd6,0x53,0x4a, +0xd9,0x79,0xed,0x72,0x06,0x09,0xee,0x63,0x25,0x47,0xd1,0x97,0xd2,0xb9,0x70,0x18, +0xde,0x6a,0xd3,0xc3,0x4d,0xdf,0x95,0xe8,0xcf,0x23,0x07,0x98,0xfb,0x2c,0x6b,0xcb, +0xea,0xbb,0xaf,0xb2,0xdf,0xe4,0xff,0x00,0x43,0xe9,0x8a,0x29,0x9b,0xbd,0xff,0x00, +0x5a,0x2b,0xe8,0x8f,0xaa,0xe6,0x43,0xe8,0xa2,0x8a,0x45,0x05,0x14,0x51,0x40,0x05, +0x79,0x0f,0xed,0x3d,0xe2,0xdf,0xf8,0x46,0xfe,0x1a,0xdc,0x5a,0x45,0x26,0xcb,0xad, +0x55,0xc5,0xa2,0x60,0xf3,0xb3,0xac,0x9f,0xf8,0xe8,0x23,0xfe,0x05,0x5e,0xb8,0x49, +0xed,0x5f,0x1b,0x7e,0xd4,0xbe,0x30,0x3a,0xff,0x00,0xc4,0x4f,0xec,0xb8,0xdf,0x75, +0xae,0x93,0x10,0x8b,0x00,0x82,0x0c,0xad,0x86,0x73,0xf8,0x0d,0xa3,0xea,0x0d,0x78, +0xf9,0xb6,0x23,0xea,0xf8,0x59,0x35,0xbb,0xd1,0x7c,0xcf,0x13,0x38,0xc4,0xfd,0x5b, +0x07,0x26,0xb7,0x96,0x8b,0xe6,0x72,0x5f,0x06,0x7c,0x26,0x7c,0x5d,0xe3,0xed,0x32, +0xd3,0x6e,0xe8,0x52,0x41,0x2c,0xb9,0xfe,0xe8,0xe6,0xbe,0xf6,0x8d,0x04,0x68,0xa8, +0xa3,0x0a,0xa3,0x00,0x0f,0x4a,0xf9,0xd3,0xf6,0x49,0xf0,0x8f,0xd9,0xf4,0xfb,0xfd, +0x7a,0x68,0xfe,0x79,0x4f,0x93,0x13,0x1f,0x4e,0xf5,0xf4,0x60,0xae,0x3c,0x8b,0x0f, +0xec,0xb0,0xde,0xd1,0xef,0x2d,0x7e,0x5d,0x0c,0x32,0x2c,0x37,0xb0,0xc2,0x29,0x3d, +0xe5,0xa8,0xb4,0x51,0x45,0x7d,0x21,0xf4,0x41,0x48,0x4e,0x29,0x6b,0x95,0xf8,0xad, +0xe3,0x88,0x3e,0x19,0xfc,0x32,0xf1,0x5f,0x8b,0x6e,0x81,0x68,0x34,0x4d,0x2e,0xe7, +0x50,0x65,0x03,0x39,0xf2,0xa3,0x67,0xc7,0xe3,0x8a,0x00,0xfc,0xfb,0xff,0x00,0x82, +0x96,0x7f,0xc1,0x41,0x75,0x2f,0x01,0x6a,0xd7,0xbf,0x09,0xbe,0x1b,0x6a,0x06,0xcf, +0x59,0x8e,0x30,0x35,0xcd,0x72,0x03,0x87,0xb6,0xdc,0x33,0xf6,0x68,0x5b,0xb3,0xed, +0x20,0xb3,0x8f,0xbb,0xb8,0x01,0xce,0xec,0x7c,0x27,0xf0,0x53,0xf6,0x29,0xf8,0xcd, +0xfb,0x4a,0x59,0xcb,0xaf,0x78,0x6b,0xc3,0xb2,0x4d,0xa4,0xc9,0x21,0x27,0x5a,0xd5, +0xee,0x45,0xbc,0x33,0xbe,0x4e,0xe2,0xae,0xe7,0x32,0x1c,0x83,0x92,0xa0,0xe0,0xf5, +0x35,0xe5,0x9a,0x76,0xab,0x1f,0x8f,0xbe,0x29,0xda,0x6a,0x3e,0x2e,0xbf,0x2b,0x0e, +0xb3,0xac,0xa4,0xfa,0xb5,0xfb,0xb6,0xd2,0xa9,0x2c,0xe0,0xcf,0x21,0x3d,0xb0,0x19, +0x8f,0xb5,0x7f,0x40,0x9f,0x1c,0x3e,0x24,0xe8,0x3f,0xb3,0x97,0xec,0xbf,0xae,0xf8, +0x9b,0x43,0x5b,0x5b,0x7d,0x2b,0x46,0xd1,0x44,0x7a,0x34,0x36,0xa5,0x44,0x4c,0xcc, +0xa2,0x3b,0x61,0x1e,0x38,0x20,0xb3,0x27,0x4e,0xdc,0xd3,0x25,0x6a,0x7f,0x3e,0x1e, +0x2f,0xf0,0x4e,0xa1,0xe0,0xef,0x1d,0x6a,0xbe,0x13,0x9d,0xa1,0xbe,0xd5,0x74,0xeb, +0xe7,0xd3,0xa4,0xfb,0x03,0x99,0x63,0x92,0x64,0x7d,0x85,0x50,0xe0,0x6e,0xf9,0x81, +0x03,0x8e,0x71,0x5f,0xbd,0xbe,0x1c,0xf8,0x6b,0xa7,0x7e,0xce,0x7f,0xb0,0xcd,0xef, +0x86,0x2e,0x84,0x51,0xc7,0xa3,0x78,0x42,0xed,0xf5,0x07,0xc6,0x16,0x4b,0x86,0xb7, +0x91,0xe7,0x27,0xeb,0x23,0x30,0xfc,0xab,0xf2,0x6b,0xfe,0x09,0xd5,0xf0,0x92,0x7f, +0x8e,0x9f,0xb5,0xbf,0x87,0xae,0x75,0x24,0x6b,0xed,0x3f,0x45,0x95,0xfc,0x45,0xa9, +0xcb,0x29,0xfb,0xcd,0x11,0x06,0x32,0x4f,0x72,0xd3,0xb4,0x59,0xf5,0x19,0xaf,0xb2, +0xff,0x00,0xe0,0xac,0x1f,0xb6,0x06,0x8d,0xa5,0x78,0x12,0xe7,0xe0,0xdf,0x85,0xb5, +0x38,0x6f,0xf5,0xfd,0x52,0x44,0xfe,0xde,0x6b,0x67,0x0e,0xb6,0x56,0xc8,0x43,0x08, +0x19,0x81,0xe2,0x47,0x60,0x99,0x5e,0x48,0x50,0x72,0x06,0xe1,0x40,0x2d,0x35,0x3f, +0x2c,0xfe,0x17,0x78,0x72,0xe3,0xc6,0x1f,0x12,0xfc,0x27,0xa0,0xd9,0x0c,0xdd,0xea, +0x7a,0xb5,0xa5,0x9c,0x5c,0xe3,0xe6,0x92,0x64,0x51,0xfc,0xeb,0xfa,0x6e,0x8d,0x3c, +0xb4,0x55,0xeb,0x80,0x06,0x6b,0xf1,0x1f,0xfe,0x09,0x3f,0xf0,0x0e,0xe3,0xe2,0x67, +0xed,0x0b,0x17,0x8c,0xaf,0x2d,0x0b,0xf8,0x7b,0xc1,0xa9,0xf6,0xb6,0x92,0x45,0x3b, +0x1e,0xf1,0x81,0x10,0x20,0x3e,0xaa,0x73,0x27,0xb6,0xc1,0xeb,0x5f,0xb7,0x2c,0xc1, +0x14,0x92,0x70,0x00,0xcd,0x0c,0x16,0xc7,0x81,0xfe,0xd2,0x7e,0x22,0x12,0xdd,0x69, +0x9a,0x24,0x6d,0x91,0x18,0x37,0x52,0x8f,0x73,0x95,0x4f,0xd3,0x77,0xe6,0x2b,0xc4, +0xab,0x7b,0xc7,0x5e,0x20,0x3e,0x28,0xf1,0x6e,0xa7,0xa9,0x64,0x98,0xe5,0x98,0x88, +0xb3,0xd9,0x07,0x0b,0xfa,0x01,0x58,0x35,0xf8,0x96,0x67,0x89,0xfa,0xde,0x2e,0x75, +0x56,0xd7,0xb2,0xf4,0x5a,0x1f,0x29,0x88,0xa9,0xed,0x6a,0xb9,0x06,0x68,0xa2,0x8c, +0xd7,0x98,0x73,0x85,0x14,0x51,0x48,0x00,0x71,0x4e,0x49,0x5e,0x33,0x95,0x76,0x52, +0x3b,0x83,0x8a,0x6d,0x14,0xd3,0x6b,0x60,0xb9,0xb5,0xa6,0xf8,0xd7,0x5f,0xd2,0x0a, +0xfd,0x93,0x58,0xbd,0x84,0x2f,0x45,0x13,0x31,0x5f,0xc8,0xf1,0x5e,0x89,0xe1,0x6f, +0xda,0x2b,0x56,0xb0,0x91,0x22,0xd6,0xed,0xd3,0x51,0xb7,0xef,0x2c,0x2a,0x12,0x51, +0xf8,0x7d,0xd3,0xfa,0x7d,0x6b,0xc8,0x68,0xaf,0x43,0x0f,0x98,0xe2,0xb0,0xb2,0xbd, +0x2a,0x8f,0xf4,0xfb,0x8d,0xe1,0x5e,0xa5,0x37,0x78,0xc8,0xfb,0x57,0xc3,0x5e,0x28, +0xd3,0xbc,0x59,0xa6,0xa5,0xf6,0x9b,0x72,0xb7,0x10,0x31,0xc1,0xec,0xc8,0xdd,0xd5, +0x87,0x63,0x5a,0xd5,0xf2,0x47,0xc2,0x6f,0x18,0x4f,0xe1,0x2f,0x17,0xda,0x10,0xe7, +0xec,0x57,0x6e,0xb0,0x5c,0xc7,0x9e,0x08,0x27,0x01,0xbe,0xaa,0x4e,0x7f,0x3f,0x5a, +0xfa,0xd9,0x4e,0x46,0x6b,0xf5,0x3c,0xa7,0x31,0x59,0x8d,0x0e,0x76,0xad,0x25,0xa3, +0x3e,0x8b,0x0d,0x5f,0xdb,0xc2,0xfd,0x50,0x37,0x00,0xd7,0xcd,0x1f,0x15,0x3e,0x26, +0xeb,0x51,0x78,0xeb,0x51,0xb7,0xd2,0xf5,0x5b,0x9b,0x5b,0x4b,0x56,0x10,0x04,0x89, +0xf0,0xa5,0x94,0x7c,0xc7,0x1f,0xef,0x64,0x7e,0x15,0xf4,0x4e,0xbb,0xaa,0xc7,0xa1, +0xe8,0xd7,0xda,0x84,0xdc,0xc5,0x6b,0x0b,0xcc,0xc0,0x75,0x21,0x41,0x38,0xfd,0x2b, +0xe2,0x8b,0xbb,0xa9,0x2f,0x6e,0xa6,0xb8,0x95,0xb7,0xcb,0x33,0xb4,0x8e,0xc7,0xbb, +0x13,0x92,0x6b,0xc6,0xe2,0x5c,0x64,0xe8,0xd3,0xa7,0x4a,0x9c,0xac,0xdb,0xbe,0x9d, +0x8e,0x6c,0x7d,0x57,0x08,0xa8,0xc5,0xd8,0xea,0x13,0xe2,0xc7,0x8b,0xa3,0xe9,0xae, +0xdd,0x7e,0x3b,0x4f,0xf3,0x15,0x32,0x7c,0x64,0xf1,0x94,0x7d,0x35,0xb9,0x0f,0xfb, +0xd1,0x46,0x7f,0xf6,0x5a,0xe3,0x28,0xaf,0x82,0x58,0xec,0x52,0xda,0xac,0xbe,0xf6, +0x78,0x9e,0xda,0xa7,0xf3,0x3f,0xbc,0xef,0x13,0xe3,0x8f,0x8c,0xd3,0xfe,0x62,0xc1, +0xbf,0xde,0xb7,0x8b,0xff,0x00,0x89,0xab,0x09,0xf1,0xef,0xc6,0x0b,0xd6,0xf6,0x06, +0xfa,0xdb,0xaf,0xf8,0x57,0x9d,0xd1,0x5a,0x2c,0xcb,0x1a,0xb6,0xad,0x2f,0xbd,0x97, +0xf5,0x8a,0xbf,0xcc,0xcf,0x4a,0x5f,0xda,0x0b,0xc5,0xca,0x79,0x96,0xd1,0xff,0x00, +0xde,0xb7,0xff,0x00,0x03,0x53,0xa7,0xed,0x17,0xe2,0xa4,0xeb,0x16,0x9c,0xff,0x00, +0x58,0x1b,0xff,0x00,0x8b,0xaf,0x2e,0xa2,0xb4,0x59,0xb6,0x39,0x6d,0x59,0xfd,0xe3, +0x58,0x9a,0xcb,0xed,0x33,0xd6,0x23,0xfd,0xa4,0xbc,0x48,0xbf,0x7a,0xcb,0x4e,0x6f, +0xfb,0x66,0xe3,0xff,0x00,0x67,0xab,0x09,0xfb,0x4b,0x6b,0x60,0x7c,0xda,0x5d,0x8b, +0x1f,0x6d,0xe3,0xfa,0xd7,0x8f,0xd1,0x56,0xb3,0x9c,0x7a,0xff,0x00,0x97,0xac,0x7f, +0x5a,0xaf,0xfc,0xc7,0xb3,0x27,0xed,0x33,0xaa,0x0f,0xbd,0xa2,0xda,0xb7,0xd2,0x56, +0x1f,0xd2,0xa7,0x5f,0xda,0x6e,0xef,0xf8,0xb4,0x08,0x7f,0x0b,0xa3,0xff,0x00,0xc4, +0xd7,0x89,0x51,0xfa,0xd6,0xab,0x3c,0xcc,0x3a,0x55,0xfc,0x17,0xf9,0x14,0xb1,0x95, +0xff,0x00,0x98,0xfb,0x1b,0xe1,0xef,0x8b,0x26,0xf1,0xb7,0x86,0x61,0xd5,0xa5,0xb3, +0x16,0x42,0x67,0x75,0x48,0xc3,0xee,0xc8,0x52,0x57,0x39,0xc0,0xee,0x0d,0x74,0xb5, +0x89,0xe0,0xad,0x23,0xfb,0x03,0xc2,0x9a,0x56,0x9e,0x7e,0xf4,0x16,0xe8,0xaf,0xee, +0xd8,0xcb,0x1f,0xcf,0x35,0xb4,0x6b,0xf5,0xac,0x3f,0x3f,0xb1,0x87,0xb5,0x77,0x95, +0x95,0xfd,0x4f,0xa5,0x85,0xf9,0x17,0x36,0xe2,0xd2,0x13,0x8a,0xaf,0x7b,0x7f,0x6f, +0xa7,0x5a,0x49,0x73,0x75,0x3c,0x76,0xf6,0xf1,0x8d,0xcf,0x2c,0xac,0x15,0x54,0x7a, +0x92,0x6b,0xc7,0x3c,0x65,0xfb,0x45,0xdb,0xda,0xb3,0xdb,0x78,0x7a,0xdf,0xed,0x72, +0x0e,0x3e,0xd9,0x70,0x08,0x8f,0xea,0xab,0xd4,0xfe,0x38,0xfc,0x6b,0x0c,0x5e,0x3b, +0x0f,0x82,0x8f,0x35,0x69,0x5b,0xcb,0xaf,0xdc,0x4d,0x5a,0xd0,0xa4,0xaf,0x36,0x7b, +0x51,0x70,0xa3,0x24,0xe0,0x7a,0x9a,0xe5,0xf5,0x8f,0x8a,0x3e,0x16,0xd0,0xb7,0x0b, +0x9d,0x6a,0xd8,0xba,0x9c,0x18,0xe0,0x6f,0x39,0x81,0xf7,0x09,0x92,0x2b,0xe5,0xbf, +0x10,0xf8,0xe3,0x5d,0xf1,0x4c,0x8c,0xda,0x96,0xa5,0x34,0xe8,0x4e,0x7c,0xa0,0xdb, +0x63,0x1f,0x45,0x18,0x15,0x85,0xd2,0xbe,0x33,0x11,0xc5,0x2f,0x6c,0x3d,0x3f,0x9b, +0xff,0x00,0x25,0xfe,0x67,0x95,0x3c,0xc7,0xf9,0x23,0xf7,0x9f,0x4b,0xdf,0xfe,0xd1, +0x7e,0x19,0xb6,0x72,0xb0,0x45,0x7d,0x79,0xe8,0xd1,0xc4,0x15,0x7f,0xf1,0xe6,0x07, +0xf4,0xac,0xb9,0xbf,0x69,0x9d,0x31,0x4f,0xee,0x74,0x6b,0xb7,0x1f,0xed,0xc8,0xab, +0xfc,0xb3,0x5f,0x3e,0x51,0x5e,0x44,0xb8,0x8f,0x1f,0x2d,0x9a,0x5f,0x2f,0xf3,0x39, +0x5e,0x3a,0xb3,0xea,0x7b,0xfa,0xfe,0xd3,0x76,0x64,0xfc,0xda,0x14,0xe0,0x7b,0x4e, +0xa7,0xfa,0x55,0xb8,0xbf,0x69,0x6d,0x10,0xe3,0xcc,0xd2,0xf5,0x04,0xf5,0xda,0x23, +0x6f,0xfd,0x98,0x57,0xce,0xb4,0x54,0xae,0x21,0xcc,0x17,0xda,0x4f,0xe4,0x84,0xb1, +0xd5,0xfb,0x9f,0x53,0x58,0x7c,0x7b,0xf0,0x85,0xe8,0x4f,0x32,0xf2,0x6b,0x36,0x6f, +0xe1,0x9e,0xdd,0xb8,0xfa,0x95,0x04,0x7e,0xb5,0xd8,0xe9,0x3e,0x25,0xd2,0xb5,0xe0, +0x4e,0x9d,0xa9,0x5a,0xde,0xe0,0x64,0x88,0x25,0x56,0x23,0xea,0x07,0x4a,0xf8,0xa2, +0x9d,0x14,0xaf,0x04,0x8a,0xf1,0xbb,0x46,0xeb,0xca,0xb2,0x1c,0x11,0xf4,0x22,0xbd, +0x0a,0x3c,0x51,0x88,0x8b,0xfd,0xf4,0x13,0x5e,0x5a,0x3f,0xd4,0xde,0x19,0x8c,0xd7, +0xc4,0xae,0x7d,0xcf,0x9c,0x9e,0xb4,0xb5,0xf2,0xcf,0x84,0xfe,0x39,0x78,0x8b,0xc3, +0xae,0x91,0xdd,0x4d,0xfd,0xaf,0x68,0x3a,0xc7,0x72,0x7e,0x70,0x3d,0x9f,0xaf,0xe7, +0x9a,0xf7,0xbf,0x04,0x7c,0x49,0xd1,0xfc,0x75,0x6e,0x4d,0x94,0xde,0x55,0xda,0x0c, +0xc9,0x69,0x36,0x04,0x8b,0xee,0x3d,0x47,0xb8,0xaf,0xaf,0xc0,0xe7,0x18,0x5c,0x73, +0xe5,0x83,0xb4,0xbb,0x3f,0xd0,0xf4,0xe8,0xe2,0xa9,0xd6,0xd1,0x3b,0x33,0xac,0xa2, +0x90,0x1c,0x8a,0x5a,0xf7,0x0e,0xc0,0xa2,0x8a,0x28,0x00,0xa2,0x90,0x9c,0x57,0x3b, +0xe2,0x9f,0x88,0x1a,0x1f,0x83,0x93,0x3a,0x9d,0xfc,0x71,0x4a,0x46,0x44,0x09,0xf3, +0xc8,0xdf,0xf0,0x11,0xce,0x3d,0xcf,0x15,0x95,0x4a,0xb0,0xa5,0x1e,0x6a,0x92,0xb2, +0xf3,0x26,0x52,0x51,0x57,0x93,0x3a,0x3a,0x4c,0xd7,0x84,0x6b,0xdf,0xb4,0xb3,0x1d, +0xc9,0xa3,0xe9,0x20,0x0e,0xd2,0xde,0x3f,0x3f,0xf7,0xc2,0xff,0x00,0xf1,0x55,0xc3, +0xea,0x7f,0x1b,0x7c,0x5f,0xa9,0x13,0xff,0x00,0x13,0x31,0x68,0xa7,0xf8,0x6d,0xa2, +0x55,0xc7,0xe3,0x82,0x7f,0x5a,0xf9,0xca,0xfc,0x45,0x81,0xa5,0xa4,0x5b,0x97,0xa2, +0xff,0x00,0x33,0x82,0x78,0xea,0x31,0xd1,0x6a,0x7d,0x5d,0x9f,0xca,0x8d,0xc3,0xd6, +0xbe,0x30,0xba,0xf1,0xaf,0x88,0x2f,0x73,0xe7,0xeb,0x7a,0x84,0x80,0xf5,0x06,0xe5, +0xf1,0xf9,0x66,0xb3,0x1e,0xfa,0xe6,0x43,0x96,0xb8,0x95,0x89,0xee,0xce,0x4d,0x79, +0x92,0xe2,0xaa,0x6b,0xe1,0xa4,0xfe,0xff,0x00,0xf8,0x07,0x3b,0xcc,0xa3,0xd2,0x27, +0xdc,0x04,0x2b,0x1f,0x9b,0x69,0xfa,0xd3,0x86,0xd0,0x30,0x00,0xfc,0x2b,0xe1,0xbf, +0xb5,0xcf,0xff,0x00,0x3d,0xa4,0xff,0x00,0xbe,0x8d,0x58,0xb6,0xd7,0x35,0x2b,0x33, +0x9b,0x7d,0x42,0xea,0x03,0xeb,0x1c,0xcc,0xbf,0xc8,0xd4,0xae,0x2a,0x87,0x5a,0x3f, +0x8f,0xfc,0x01,0x7f,0x69,0x2e,0xb1,0xfc,0x4f,0xb6,0xb6,0xa9,0x3d,0x06,0x69,0xd9, +0xe3,0x8a,0xf8,0xe6,0xd3,0xe2,0x37,0x8a,0x2c,0xbf,0xd5,0x6b,0xd7,0xff,0x00,0x47, +0x9d,0x9c,0x7f,0xe3,0xd9,0xae,0x82,0xc3,0xe3,0xcf,0x8b,0xec,0x48,0xdf,0x75,0x05, +0xea,0x8e,0xd3,0xc0,0xbf,0xcd,0x71,0x5d,0x74,0xf8,0x9f,0x0b,0x2f,0x8e,0x2d,0x7d, +0xcc,0xda,0x39,0x85,0x37,0xba,0x68,0xfa,0xa2,0x90,0xf1,0x5e,0x27,0xe1,0x2f,0xda, +0x22,0x6d,0x5f,0x53,0xb3,0xd3,0xef,0xb4,0x61,0xe6,0xdc,0xca,0x90,0xac,0x96,0xb2, +0x7f,0x13,0x10,0x07,0xca,0xdf,0x5f,0x5a,0xf6,0xc1,0xc8,0x15,0xf4,0x78,0x4c,0x75, +0x0c,0x74,0x5c,0xa8,0x4a,0xf6,0x3b,0xa9,0x56,0x85,0x65,0x78,0x30,0x56,0x0e,0xa0, +0x8e,0x86,0x96,0x9a,0xab,0xb4,0x60,0x74,0xa7,0x57,0x79,0xb0,0x53,0x5c,0xe1,0x49, +0xf4,0x14,0xea,0x8a,0xe9,0xfc,0xbb,0x69,0x5b,0xd1,0x09,0xfd,0x29,0x3d,0x80,0xf8, +0x93,0xf6,0x80,0xb9,0xfb,0x47,0x8a,0xe4,0x5c,0xe7,0x04,0xd7,0x87,0xe8,0xfe,0x3c, +0x97,0xe1,0x5f,0xc5,0x4f,0x09,0x78,0xaa,0x10,0x0a,0x5a,0x5f,0x24,0x57,0x0a,0x4e, +0x03,0x41,0x27,0xee,0xe4,0x07,0xfe,0x02,0xc4,0x8f,0x70,0x3d,0x2b,0xd6,0xbe,0x33, +0x5c,0x79,0xde,0x2d,0xb8,0x39,0xce,0x33,0x5f,0x2e,0x7c,0x77,0xba,0x30,0xe8,0x72, +0xed,0x38,0x60,0xa4,0x8c,0x7a,0xd7,0xe7,0x18,0x29,0x37,0x8e,0x94,0x97,0x76,0x7e, +0x39,0x8f,0xa9,0x25,0x9a,0x53,0x9c,0x77,0xe7,0x47,0xec,0x77,0xdb,0x61,0xff,0x00, +0x9e,0xc9,0xf9,0xd1,0x5e,0x03,0xfd,0x91,0x7b,0xff,0x00,0x3f,0x72,0xff,0x00,0xdf, +0x46,0x8a,0xfd,0x0f,0x9d,0x9f,0xaf,0x73,0x79,0x1f,0x44,0xd1,0x45,0x15,0xa9,0xa8, +0x51,0x45,0x14,0x01,0x93,0xe2,0x9d,0x7a,0x1f,0x0b,0xf8,0x77,0x53,0xd5,0xae,0x48, +0xf2,0x6c,0xed,0xde,0x76,0x1e,0xbb,0x41,0x38,0xfc,0x4f,0x15,0xf9,0xe8,0xf3,0x5d, +0x78,0x97,0x5b,0x92,0x79,0x4b,0x4d,0x79,0x7d,0x39,0x76,0x3d,0x49,0x66,0x6c,0xff, +0x00,0x5a,0xfa,0x97,0xf6,0xb9,0xf1,0x6b,0x69,0x9e,0x11,0xb1,0xd0,0xa0,0x90,0x2c, +0xba,0x9c,0xdb,0xe5,0x51,0x8c,0xf9,0x51,0xf3,0xfa,0xb1,0x5f,0xc8,0xd7,0x8e,0x7e, +0xce,0xde,0x11,0xff,0x00,0x84,0xa3,0xe2,0x15,0xa3,0xc8,0xbb,0xad,0xac,0xff,0x00, +0x7e,0xfc,0x71,0xc7,0x41,0xf9,0xd7,0xc3,0xe7,0x33,0x78,0xac,0x54,0x30,0x90,0xfe, +0x9b,0xff,0x00,0x80,0x7c,0x26,0x6f,0x27,0x8c,0xc7,0x53,0xc2,0x47,0x65,0xbf,0xab, +0xff,0x00,0x80,0x7d,0x75,0xf0,0xeb,0xc3,0x51,0xf8,0x4f,0xc1,0xba,0x5e,0x9a,0x8b, +0xb5,0xa2,0x84,0x17,0xf7,0x62,0x32,0x6b,0xa4,0x03,0x14,0x2f,0x02,0x96,0xbe,0xd2, +0x9c,0x15,0x38,0x28,0x47,0x64,0x7d,0xc4,0x22,0xa1,0x15,0x15,0xb2,0x0a,0x28,0xa2, +0xb4,0x2c,0x2b,0x88,0xf8,0xe1,0xe0,0x17,0xf8,0xa9,0xf0,0x77,0xc6,0xbe,0x0f,0x8e, +0x5f,0x22,0x5d,0x73,0x48,0xba,0xb0,0x8e,0x53,0xfc,0x0f,0x24,0x4c,0xaa,0x7f,0x02, +0x45,0x76,0xf4,0x84,0x66,0x80,0x3f,0x97,0xbf,0x12,0xf8,0x6f,0x53,0xf0,0x77,0x88, +0x75,0x2d,0x0f,0x59,0xb3,0x97,0x4f,0xd5,0x74,0xeb,0x87,0xb5,0xba,0xb5,0x9d,0x70, +0xf1,0x48,0xa4,0x86,0x52,0x3e,0xa2,0xb4,0xa7,0xf8,0x99,0xe2,0xdb,0x9f,0x06,0x0f, +0x08,0x4d,0xe2,0x5d,0x56,0x6f,0x0b,0x09,0x56,0x71,0xa3,0x49,0x79,0x23,0x5a,0xac, +0x8b,0x9d,0xac,0x23,0x27,0x68,0x23,0x27,0xa0,0xef,0x5f,0xbd,0xff,0x00,0xb4,0x67, +0xec,0x2b,0xf0,0x9f,0xf6,0x99,0xb8,0x6d,0x4b,0xc4,0xba,0x3c,0xba,0x77,0x88,0xf6, +0x04,0x1a,0xee,0x8f,0x20,0x82,0xe9,0x80,0x18,0x01,0xf8,0x29,0x26,0x07,0x03,0x7a, +0x92,0x07,0x00,0x81,0x5f,0x2a,0x6a,0xbf,0xf0,0x44,0xcf,0x0c,0x49,0x76,0x0e,0x99, +0xf1,0x3b,0x56,0xb6,0xb5,0xef,0x1d,0xde,0x9b,0x14,0xcf,0x8f,0xf7,0x95,0x90,0x7e, +0x95,0x57,0x22,0xcf,0xa1,0xf9,0x77,0xe0,0xff,0x00,0x89,0x7e,0x2c,0xf8,0x7d,0x0e, +0xa7,0x17,0x86,0x3c,0x45,0xa9,0x78,0x7d,0x75,0x38,0x84,0x17,0x9f,0xd9,0xb7,0x2f, +0x03,0x4f,0x18,0x24,0x84,0x62,0xa4,0x12,0x32,0x4f,0x15,0xdb,0xfe,0xcf,0x3f,0xb3, +0x4f,0x8e,0xff,0x00,0x6a,0x2f,0x1c,0x47,0xa3,0x78,0x5a,0xc6,0x49,0x63,0xf3,0x03, +0x6a,0x1a,0xcd,0xc8,0x3f,0x66,0xb3,0x42,0x79,0x79,0x1f,0xb9,0xeb,0x85,0x19,0x66, +0x3d,0x2b,0xf5,0x27,0xe1,0xef,0xfc,0x11,0xd7,0xe0,0xf7,0x86,0x2f,0xe1,0xbb,0xf1, +0x1e,0xad,0xe2,0x0f,0x18,0x98,0xf9,0x36,0x97,0x17,0x0b,0x6b,0x6e,0xc7,0xdc,0x44, +0xa1,0xff,0x00,0x0d,0xf5,0xf6,0xa7,0x82,0x3c,0x03,0xe1,0xcf,0x86,0xbe,0x1e,0xb6, +0xd0,0x7c,0x2b,0xa2,0x58,0xf8,0x7f,0x47,0xb7,0x1f,0xbb,0xb3,0xd3,0xe0,0x58,0xa3, +0x07,0xb9,0x20,0x0e,0x58,0xf7,0x63,0xc9,0xee,0x69,0x5c,0x12,0xee,0x71,0xdf,0xb3, +0x97,0xec,0xfd,0xe1,0xbf,0xd9,0xab,0xe1,0x7e,0x9d,0xe0,0xcf,0x0d,0xc6,0x5a,0x38, +0x7f,0x7b,0x77,0x7d,0x22,0x81,0x35,0xed,0xc3,0x01,0xbe,0x67,0x3e,0xa7,0x00,0x01, +0xd8,0x00,0x07,0x02,0xb6,0x7e,0x30,0xf8,0x8c,0x78,0x6f,0xc0,0x7a,0x8c,0x8a,0xc1, +0x6e,0x2e,0x57,0xec,0xb0,0xf3,0x83,0xb9,0xf8,0x24,0x7b,0x85,0xdc,0x7f,0x0a,0xed, +0xeb,0xe7,0x8f,0xda,0x43,0xc4,0x5f,0x6b,0xd6,0x6c,0x34,0x68,0xdf,0x29,0x6b,0x19, +0x9e,0x50,0x3a,0x6f,0x6e,0x07,0xe4,0x07,0xfe,0x3d,0x5e,0x2e,0x6f,0x89,0xfa,0xae, +0x0e,0x73,0x5b,0xbd,0x17,0xab,0xd0,0xe7,0xc5,0x54,0xf6,0x74,0x9b,0x3c,0x6e,0x8a, +0x28,0xaf,0xc6,0x0f,0x95,0x0a,0xf6,0xff,0x00,0xd9,0xcf,0xc2,0x90,0x5e,0xc5,0xaa, +0xea,0xf7,0x76,0xf1,0x4e,0x99,0x16,0xd1,0x09,0x50,0x30,0xc8,0xf9,0x98,0xe0,0xfd, +0x57,0xf5,0xaf,0x10,0xaf,0xb0,0xbe,0x1a,0x78,0x74,0xf8,0x63,0xc1,0x1a,0x4d,0x8b, +0xa9,0x59,0xc4,0x5e,0x64,0xc0,0x8c,0x10,0xee,0x77,0x30,0xfc,0x09,0xc7,0xe1,0x5f, +0x57,0xc3,0xb8,0x5f,0x6f,0x8b,0xf6,0x92,0x5a,0x45,0x7e,0x2f,0x44,0x7a,0x58,0x0a, +0x7c,0xf5,0x79,0x9f,0x43,0x4e,0x4f,0x09,0xe8,0x93,0x0f,0xde,0x69,0x16,0x2f,0xf5, +0xb6,0x43,0xfd,0x2b,0x36,0xf3,0xe1,0x87,0x85,0x2f,0x91,0x96,0x4d,0x02,0xc5,0x41, +0xea,0x62,0x84,0x46,0x7f,0x35,0xc1,0xae,0x9c,0x0c,0x51,0x5f,0xa6,0xcb,0x0f,0x46, +0x5f,0x14,0x13,0xf9,0x23,0xe8,0x1d,0x38,0x3d,0xd2,0x3c,0x33,0xe2,0x17,0xc0,0x1b, +0x3b,0x6d,0x3a,0xe3,0x50,0xf0,0xf3,0xcb,0x1c,0x90,0xa1,0x76,0xb3,0x95,0xb7,0x87, +0x03,0x93,0xb5,0x8f,0x39,0xfa,0x93,0x9f,0x6a,0xf0,0x8a,0xfb,0x2b,0xc7,0x7e,0x21, +0x83,0xc3,0x3e,0x14,0xd4,0x6f,0xe6,0x20,0x6c,0x89,0x95,0x14,0xff,0x00,0x1b,0x91, +0x85,0x1f,0x99,0xaf,0x8d,0x40,0xc0,0x02,0xbf,0x34,0xe2,0x2c,0x2e,0x1b,0x0d,0x5a, +0x1e,0xc1,0x59,0xb5,0xaa,0x5f,0x81,0xe0,0x63,0xa9,0xc2,0x9c,0xd7,0x26,0x81,0x45, +0x14,0x57,0xc9,0x1e,0x61,0x6f,0x49,0xb5,0x7b,0xed,0x56,0xce,0xde,0x21,0x99,0x25, +0x99,0x23,0x5c,0x7a,0x96,0x00,0x7f,0x3a,0xfb,0x79,0x38,0x50,0x2b,0xe5,0xdf,0x81, +0x3e,0x13,0x6f,0x10,0x78,0xce,0x2b,0xc9,0x13,0x75,0xa6,0x9a,0x3c,0xf7,0x24,0x70, +0x64,0xe8,0x83,0xeb,0x9f,0x9b,0xfe,0x03,0x5f,0x51,0x81,0x5f,0xa5,0xf0,0xc5,0x09, +0x53,0xc3,0xce,0xab,0xfb,0x4f,0x4f,0x91,0xef,0xe5,0xd0,0x71,0x83,0x93,0xea,0x61, +0x78,0xdb,0xc3,0x4f,0xe2,0xff,0x00,0x0e,0x5d,0xe9,0x2b,0x78,0xf6,0x22,0xe3,0x68, +0x69,0x91,0x37,0x10,0x03,0x02,0x46,0x32,0x3a,0xe3,0x15,0xe4,0xf2,0x7e,0xcc,0x63, +0xf8,0x3c,0x40,0x7f,0xe0,0x56,0x9f,0xfd,0x9d,0x7b,0xb5,0x26,0x2b,0xe8,0x71,0x59, +0x6e,0x17,0x19,0x25,0x3a,0xf0,0xbb,0xf5,0x67,0x75,0x4c,0x3d,0x3a,0xae,0xf3,0x57, +0x3c,0x09,0xff,0x00,0x66,0x4b,0xaf,0xe0,0xd7,0xa1,0x3f,0xef,0x5b,0x11,0xff,0x00, +0xb3,0x55,0x77,0xfd,0x99,0xf5,0x31,0xf7,0x35,0xab,0x46,0xfa,0xc4,0xc2,0xbe,0x85, +0xc5,0x52,0xd6,0x35,0x38,0xb4,0x7d,0x2a,0xf2,0xfa,0x63,0x88,0xad,0xa2,0x79,0x58, +0xfb,0x28,0x26,0xbc,0xe9,0xe4,0x39,0x72,0x4d,0xb8,0x5b,0xe6,0xff,0x00,0xcc,0xc1, +0xe0,0xa8,0x2d,0x6c,0x7c,0x65,0xe2,0x0d,0x20,0xe8,0x1a,0xdd,0xee,0x9a,0xd7,0x11, +0xdc,0xbd,0xac,0x86,0x26,0x92,0x20,0x42,0x96,0x1d,0x40,0xcf,0xa1,0xc8,0xfc,0x2b, +0x3e,0xa6,0xbc,0xba,0x96,0xfe,0xee,0x6b,0x99,0xdb,0x7c,0xf3,0x3b,0x49,0x23,0x7a, +0xb1,0x39,0x27,0xf3,0x35,0x0d,0x7e,0x51,0x53,0x95,0xcd,0xb8,0x2d,0x2f,0xa1,0xf3, +0x4e,0xd7,0x76,0x0a,0x28,0xad,0x2f,0x0d,0xe9,0x2d,0xaf,0x78,0x83,0x4d,0xd3,0xd4, +0x13,0xf6,0x9b,0x84,0x8c,0xe3,0xb2,0x93,0xc9,0xfc,0xb3,0x4a,0x10,0x75,0x24,0xa0, +0xb7,0x6e,0xc1,0x15,0x76,0x91,0xd2,0xda,0xfc,0x17,0xf1,0x7d,0xe5,0xa4,0x37,0x30, +0xe9,0x41,0xe2,0x99,0x04,0x88,0x7c,0xf8,0xc1,0xc1,0x19,0x19,0x05,0xb8,0xa4,0x93, +0xe0,0xb7,0x8c,0xe3,0xeb,0xa2,0x39,0xff,0x00,0x76,0x68,0x8f,0xfe,0xcd,0x5f,0x59, +0x43,0x1a,0xc5,0x12,0x22,0x8d,0xaa,0xa0,0x00,0x07,0x61,0x4e,0xc7,0xbd,0x7e,0x99, +0xfe,0xac,0x61,0x1a,0x5e,0xf4,0xaf,0xea,0xbf,0xc8,0xf7,0xff,0x00,0xb3,0xa9,0xf7, +0x67,0xc8,0x12,0x7c,0x2a,0xf1,0x6c,0x47,0xe6,0xd0,0x6e,0xcf,0xfb,0xaa,0x0f,0xf2, +0x35,0xa1,0xe1,0x2f,0x86,0x1e,0x20,0x9b,0xc5,0x3a,0x52,0x5e,0xe8,0xb7,0x50,0x5a, +0x7d,0xa5,0x1a,0x67,0x9a,0x22,0x10,0x20,0x39,0x6c,0x9f,0x70,0x31,0x5f,0x57,0x8a, +0x31,0x44,0x38,0x67,0x0d,0x09,0xa9,0x29,0xbd,0x3d,0x06,0xb2,0xfa,0x69,0xde,0xec, +0x07,0x02,0xb1,0x7c,0x59,0xe2,0xed,0x3f,0xc1,0xba,0x3c,0x9a,0x86,0xa1,0x2e,0xc8, +0xc7,0xca,0x91,0xaf,0xdf,0x95,0xbb,0x2a,0x8e,0xe7,0xf9,0x75,0x35,0x7f,0x56,0xd5, +0x6d,0xb4,0x4d,0x36,0xe6,0xfa,0xf2,0x51,0x0d,0xb4,0x08,0x64,0x91,0xcf,0x60,0x3f, +0xcf,0x4a,0xf9,0x1b,0xe2,0x07,0x8e,0x6e,0xfc,0x77,0xae,0xbd,0xe4,0xe5,0xa3,0xb6, +0x8c,0x95,0xb6,0xb7,0xcf,0x11,0x27,0xf8,0x9e,0xe7,0xfa,0x62,0xbd,0x1c,0xdb,0x34, +0x8e,0x5d,0x4a,0xd1,0xd6,0x6f,0x65,0xfa,0xb3,0x7c,0x4e,0x21,0x50,0x8e,0x9b,0xb2, +0x6f,0x1e,0x7c,0x48,0xd5,0x3c,0x79,0x78,0x5a,0xe5,0xcd,0xbd,0x8a,0x1c,0xc5,0x67, +0x1b,0x1d,0x8b,0xe8,0x4f,0xf7,0x9b,0xdc,0xfe,0x18,0xae,0x4e,0x8a,0x2b,0xf2,0x5a, +0xd5,0xaa,0x62,0x26,0xea,0x55,0x77,0x6c,0xf9,0x99,0x4e,0x53,0x7c,0xd2,0x7a,0x85, +0x14,0x57,0x5d,0xe0,0x0f,0x86,0x9a,0xa7,0x8f,0xae,0x8f,0xd9,0x80,0xb7,0xb1,0x8d, +0xb1,0x2d,0xe4,0x83,0xe5,0x1f,0xec,0x81,0xfc,0x4d,0xed,0xf9,0xd3,0xa3,0x46,0xa6, +0x22,0x6a,0x9d,0x25,0x76,0xc7,0x08,0x4a,0xa4,0xb9,0x62,0xae,0xce,0x46,0xa7,0xb7, +0xb1,0xb9,0xbc,0xff,0x00,0x51,0x6f,0x2c,0xf8,0xeb,0xe5,0xa1,0x6f,0xe5,0x5f,0x55, +0xf8,0x5f,0xe0,0xe7,0x86,0x7c,0x35,0x12,0x11,0x60,0x97,0xf7,0x23,0x19,0x9e,0xf0, +0x09,0x0e,0x7d,0x40,0x3f,0x28,0xfc,0x05,0x76,0xc9,0x0a,0x46,0x00,0x55,0x0a,0x07, +0x18,0x03,0x02,0xbe,0xce,0x87,0x0b,0x54,0x94,0x6f,0x5a,0xa2,0x4f,0xb2,0x57,0xfc, +0x74,0x3d,0x58,0x65,0xd2,0x7f,0x1c,0xac,0x7c,0x3f,0x71,0xa7,0x5d,0xda,0x0c,0xcf, +0x6b,0x34,0x23,0xd6,0x48,0xca,0xff,0x00,0x31,0x55,0xeb,0xee,0x96,0x8d,0x5d,0x48, +0x60,0x08,0x3d,0x8d,0x71,0xde,0x29,0xf8,0x4d,0xe1,0xcf,0x15,0x42,0xfe,0x6d,0x8a, +0x59,0xdd,0x31,0x2c,0x2e,0xad,0x00,0x8d,0xf7,0x7a,0x9c,0x70,0xdf,0x88,0x34,0xeb, +0xf0,0xb5,0x48,0xc6,0xf4,0x6a,0x5d,0xf6,0x6a,0xc1,0x3c,0xb9,0xa5,0xee,0x4a,0xe7, +0xc8,0xf4,0x57,0x4b,0xe3,0xbf,0x02,0x5f,0xf8,0x0f,0x56,0xfb,0x25,0xd8,0xf3,0x61, +0x93,0x2d,0x05,0xca,0x8c,0x2c,0x8b,0xfd,0x08,0xee,0x3d,0xeb,0x9a,0xaf,0x89,0xab, +0x4a,0x74,0x26,0xe9,0xd4,0x56,0x68,0xf2,0x65,0x17,0x07,0xcb,0x2d,0xc2,0xac,0x69, +0xfa,0x85,0xce,0x95,0x7b,0x0d,0xdd,0x9c,0xef,0x6d,0x73,0x0b,0x6e,0x8e,0x58,0xdb, +0x05,0x4d,0x57,0xa2,0xb3,0x4d,0xc5,0xa7,0x1d,0x1a,0x25,0x3b,0x6a,0x8f,0xaa,0xfe, +0x13,0xfc,0x4d,0x8f,0xc7,0x9a,0x61,0x86,0xe3,0x6c,0x5a,0xb5,0xb2,0x8f,0x3a,0x31, +0xc0,0x91,0x7f,0xbe,0xbe,0xde,0xa3,0xb1,0xfa,0x8a,0xef,0xc5,0x7c,0x59,0xe1,0x3f, +0x12,0xdc,0x78,0x47,0xc4,0x16,0x7a,0xad,0xb1,0x25,0xe0,0x6f,0x99,0x33,0xfe,0xb1, +0x0f,0xde,0x53,0xf5,0x19,0xaf,0xb2,0xf4,0xeb,0xd8,0x75,0x2b,0x0b,0x7b,0xbb,0x77, +0x12,0x41,0x3c,0x6b,0x24,0x6c,0x3a,0x15,0x23,0x20,0xd7,0xeb,0x39,0x16,0x64,0xf1, +0xd4,0x5c,0x2a,0x3f,0x7e,0x3b,0xf9,0xae,0x8c,0xfa,0x5c,0x1d,0x77,0x5a,0x16,0x96, +0xe8,0xb3,0x48,0x4e,0xd1,0x93,0x41,0xaf,0x29,0xf8,0xf9,0xe3,0x99,0x3c,0x3f,0xa2, +0x45,0xa4,0xd9,0xc8,0x52,0xf3,0x50,0x07,0x7b,0x29,0xe5,0x22,0x1d,0x7f,0x3e,0x9f, +0x4c,0xd7,0xb5,0x8b,0xc4,0xc3,0x07,0x46,0x55,0xa7,0xb2,0x3a,0xea,0xd4,0x54,0xa0, +0xe6,0xfa,0x1c,0xff,0x00,0xc5,0x1f,0x8e,0xb2,0x2c,0xb3,0x69,0x5e,0x1b,0x94,0x2e, +0xdc,0xa4,0xba,0x82,0xf3,0xcf,0x71,0x1f,0xff,0x00,0x15,0xf9,0x7a,0xd7,0x87,0x4f, +0x3c,0xb7,0x33,0x3c,0xb3,0x48,0xf2,0xca,0xec,0x59,0x9d,0xd8,0xb3,0x31,0x3d,0x49, +0x26,0x99,0x45,0x7e,0x39,0x8d,0xc7,0xd7,0xc7,0xd4,0xe7,0xaa,0xfd,0x17,0x44,0x7c, +0xb5,0x5a,0xd3,0xac,0xef,0x20,0xa2,0x8a,0x2b,0xce,0x30,0x0a,0x2b,0xba,0xf0,0xbf, +0xc1,0x8f,0x13,0x78,0xa2,0x14,0xb8,0x4b,0x64,0xb0,0xb5,0x7e,0x56,0x5b,0xc6,0x29, +0xb8,0x7a,0x85,0x00,0x9f,0xd2,0xbb,0x28,0x3f,0x66,0x5b,0xb6,0x51,0xe7,0xeb,0xd1, +0x21,0xee,0x23,0xb6,0x2d,0xfa,0x96,0x15,0xeb,0xd1,0xca,0x31,0xd5,0xd7,0x34,0x29, +0xbb,0x79,0xe9,0xf9,0x9d,0x31,0xc3,0x56,0x9a,0xba,0x89,0xe2,0x74,0x57,0xb9,0x37, +0xec,0xc6,0xf8,0xf9,0x7c,0x42,0x3f,0x1b,0x4f,0xfe,0xce,0xaa,0x5c,0x7e,0xcc,0xfa, +0x8a,0xa9,0xf2,0x35,0xab,0x59,0x0f,0x61,0x24,0x2c,0x9f,0xc8,0x9a,0xdd,0xe4,0x59, +0x82,0xff,0x00,0x97,0x7f,0x8a,0xff,0x00,0x32,0xfe,0xa7,0x5d,0x7d,0x93,0xc6,0x28, +0xaf,0x47,0xd4,0xbe,0x01,0x78,0xb2,0xc4,0x33,0x43,0x05,0xb5,0xf2,0x8f,0xf9,0xe1, +0x38,0xcf,0xe4,0xc0,0x57,0x15,0xac,0x78,0x6b,0x56,0xf0,0xfb,0xed,0xd4,0xb4,0xdb, +0x9b,0x2e,0x70,0x1a,0x68,0xc8,0x53,0xf4,0x3d,0x0d,0x79,0xd5,0xb0,0x58,0x9c,0x3e, +0xb5,0x69,0xb5,0xf2,0x30,0x95,0x2a,0x90,0xf8,0xa3,0x63,0xac,0xf8,0x1d,0xa4,0x0d, +0x57,0xe2,0x25,0x83,0x32,0x6e,0x8e,0xd5,0x5e,0xe1,0xbd,0xb0,0x30,0xa7,0xfe,0xfa, +0x65,0xaf,0xab,0x07,0x4a,0xf0,0x8f,0xd9,0x9f,0x48,0x05,0xb5,0x9d,0x51,0x97,0xfb, +0x96,0xc8,0x7f,0xf1,0xe6,0xff,0x00,0xd9,0x6b,0xde,0x2b,0xf4,0xce,0x1d,0xa3,0xec, +0xb0,0x2a,0x5f,0xcc,0xdb,0xfd,0x3f,0x43,0xe8,0x30,0x30,0xe5,0xa3,0x7e,0xe1,0x45, +0x14,0x57,0xd3,0x9e,0x80,0x55,0x2d,0x66,0x4f,0x2b,0x4a,0xbb,0x6f,0x48,0xcd,0x5d, +0xac,0x7f,0x16,0xcb,0xe4,0x78,0x7a,0xf9,0xff,0x00,0xe9,0x99,0xac,0xea,0x3b,0x41, +0xb2,0x64,0xed,0x16,0xcf,0x83,0x7e,0x27,0xcf,0xe7,0x78,0xa6,0xf4,0x83,0x9c,0x12, +0x3f,0x5a,0xf9,0xc3,0xe2,0xbc,0x5f,0xda,0x1a,0xa6,0x95,0x65,0xb7,0x79,0xb8,0xbd, +0x82,0x1d,0x9d,0x77,0x6e,0x91,0x57,0x1f,0xad,0x7d,0x01,0xe3,0xa9,0xbc,0xdd,0x7a, +0xf5,0xb3,0x9f,0x9c,0x8a,0xf1,0x3b,0xa8,0x3f,0xb4,0xfe,0x36,0xfc,0x3b,0xb2,0xed, +0x37,0x88,0xf4,0xe4,0xfa,0x8f,0xb4,0xc7,0xfe,0x15,0xf9,0xde,0x54,0xb9,0xb1,0x2d, +0xf9,0xfe,0xa7,0xe3,0x33,0x5e,0xd7,0x36,0xa4,0xbf,0xbc,0x7e,0xb6,0xff,0x00,0x61, +0x5a,0xff,0x00,0xcf,0xba,0xfe,0x54,0x56,0xad,0x15,0xfa,0x2f,0x2a,0x3f,0x66,0xb2, +0x1f,0x45,0x14,0x55,0x94,0x14,0xd2,0x69,0xd5,0xc8,0xfc,0x55,0xf1,0x6f,0xfc,0x21, +0x1e,0x01,0xd6,0xb5,0x75,0x60,0xb3,0xc3,0x09,0x48,0x33,0x8f,0xf5,0xad,0xf2,0xa7, +0x07,0xaf,0x24,0x1c,0x7b,0x56,0x75,0x26,0xa9,0xc1,0xce,0x5b,0x23,0x3a,0x93,0x54, +0xa0,0xe7,0x2d,0x96,0xa7,0xc8,0x5f,0x1f,0xbc,0x5f,0xff,0x00,0x09,0x8f,0xc4,0xfd, +0x4e,0x48,0xa4,0x2f,0x69,0x64,0x45,0x94,0x18,0x24,0x8c,0x26,0x77,0x11,0xf5,0x62, +0xdf,0xa5,0x7b,0xc7,0xec,0xaf,0xe1,0x1f,0xec,0x7f,0x08,0x4d,0xab,0x4a,0x98,0x9a, +0xf9,0xfe,0x52,0x47,0x3b,0x05,0x7c,0xa9,0xa0,0x69,0x73,0xf8,0x83,0x5d,0xb5,0xb3, +0x8c,0x19,0x66,0xb9,0x98,0x2f,0xa9,0x24,0x9e,0x4d,0x7e,0x85,0x78,0x67,0x45,0x8b, +0xc3,0xfa,0x0d,0x8e,0x9f,0x12,0x85,0x4b,0x78,0x95,0x30,0x3d,0x40,0xe6,0xbe,0x27, +0x28,0x83,0xc5,0xe3,0x27,0x8a,0x9f,0x4f,0xcd,0xff,0x00,0xc0,0x3e,0x27,0x23,0x84, +0xb1,0x58,0x9a,0x98,0xc9,0xff,0x00,0x57,0x34,0xc5,0x2d,0x14,0x57,0xdd,0x1f,0x74, +0x14,0x51,0x45,0x00,0x32,0x49,0x16,0x18,0xd9,0xdd,0x82,0x22,0x82,0x59,0x98,0xe0, +0x01,0xea,0x6b,0xe0,0x7f,0xda,0x6b,0xfe,0x0a,0xd3,0xe0,0xaf,0x85,0x9a,0x95,0xe7, +0x87,0xbe,0x1e,0x69,0xc9,0xe3,0xcd,0x72,0xdd,0x8c,0x73,0x5f,0xb4,0xa6,0x3d,0x36, +0x17,0x07,0x95,0x0e,0x3e,0x69,0x88,0xff,0x00,0x67,0x0b,0xfe,0xd7,0x5a,0xe2,0xbf, +0xe0,0xad,0x3f,0xb5,0xed,0xe7,0x84,0xed,0x62,0xf8,0x37,0xe1,0x3b,0xf6,0xb6,0xbe, +0xd4,0x2d,0xc5,0xc7,0x88,0x6e,0xa0,0x7c,0x3c,0x76,0xef,0xfe,0xae,0xd8,0x10,0x78, +0x2e,0x3e,0x66,0xff,0x00,0x64,0xa8,0xe8,0xc6,0xbe,0x5a,0xfd,0x8a,0x7f,0xe0,0x9d, +0x9a,0xff,0x00,0xed,0x53,0xa7,0xc9,0xe2,0x9d,0x5f,0x55,0x3e,0x15,0xf0,0x3c,0x53, +0x18,0x12,0xed,0x21,0xf3,0x2e,0x6f,0x5d,0x71,0xb9,0x61,0x52,0x40,0x0a,0xbd,0x0b, +0xb6,0x46,0x78,0x00,0xe0,0xe1,0x92,0xfc,0x8c,0xef,0x1a,0xff,0x00,0xc1,0x51,0x7f, +0x68,0x5f,0x17,0xcd,0x37,0x91,0xe2,0xeb,0x7f,0x0e,0xdb,0x3b,0x16,0x5b,0x7d,0x1b, +0x4f,0x86,0x30,0x83,0xb0,0x0e,0xea,0xcf,0xf9,0xb5,0x7d,0x1d,0xff,0x00,0x04,0xc4, +0xf8,0xc5,0xf1,0xb7,0xf6,0x81,0xf8,0xe3,0x7d,0x71,0xe2,0x9f,0x88,0x1a,0xe6,0xad, +0xe0,0xff,0x00,0x0f,0xd8,0xbd,0xd5,0xe5,0xb5,0xc3,0x29,0x86,0x79,0xe4,0xcc,0x70, +0xc4,0xc7,0x6e,0x47,0x57,0x93,0x03,0xfe,0x79,0x57,0xc9,0xbf,0xb7,0x6f,0xc0,0x4f, +0x01,0xfe,0xcd,0x7f,0x18,0x6d,0xbc,0x0b,0xe0,0x8d,0x57,0x58,0xd5,0xde,0xd7,0x4f, +0x8e,0xe3,0x53,0x9f,0x57,0x9e,0x29,0x19,0x27,0x90,0x96,0x58,0xc0,0x8e,0x34,0x0b, +0x88,0xf6,0x31,0xce,0x7f,0xd6,0x0e,0x98,0xaf,0xd3,0xef,0xf8,0x25,0x5f,0xc1,0x81, +0xf0,0xbf,0xf6,0x5f,0xb1,0xd7,0x2e,0xad,0xfc,0xad,0x5f,0xc5,0xf3,0x9d,0x56,0x56, +0x3f,0x7b,0xec,0xff,0x00,0x72,0xdd,0x7d,0x86,0xd0,0x5b,0xfe,0xda,0x50,0x08,0x8f, +0xe3,0x97,0xfc,0x15,0x17,0xc0,0x9f,0x00,0x7e,0x2c,0xeb,0xfe,0x01,0xd7,0xfc,0x21, +0xe2,0x5b,0xbd,0x43,0x48,0x92,0x34,0x92,0xea,0xc4,0x5b,0xb4,0x32,0x07,0x89,0x24, +0x56,0x5d,0xd2,0x29,0xe8,0xe3,0xb7,0x50,0x6b,0xe8,0x3f,0xd9,0xdb,0xe3,0xe6,0x87, +0xfb,0x4a,0xfc,0x30,0xb3,0xf1,0xc7,0x87,0x6c,0xef,0xac,0x34,0xcb,0x99,0xe5,0xb7, +0x58,0x35,0x15,0x45,0x98,0x34,0x6d,0xb5,0xb2,0x15,0x98,0x63,0x3d,0x39,0xaf,0xc2, +0xdf,0xdb,0xb3,0xc7,0x76,0x9f,0x11,0xbf,0x6b,0x6f,0x89,0x5a,0xcd,0x84,0xbe,0x75, +0x90,0xd4,0xbe,0xc5,0x13,0x8e,0x84,0x5b,0xc6,0x90,0x12,0x3d,0x8b,0x46,0xc7,0xf1, +0xaf,0xd8,0xaf,0xf8,0x27,0x2f,0x81,0x67,0xf0,0x0f,0xec,0x75,0xf0,0xfa,0xd2,0xe5, +0x59,0x2e,0x2f,0xed,0xa4,0xd5,0x59,0x58,0x60,0x81,0x71,0x2b,0x4a,0x9f,0xf8,0xe3, +0x2d,0x03,0x4f,0x53,0xe9,0x19,0xa7,0x5b,0x78,0x9e,0x49,0x18,0x24,0x68,0xa5,0x99, +0x98,0xe0,0x00,0x3b,0xd7,0xc5,0xfe,0x2d,0xd7,0x5f,0xc4,0xde,0x25,0xd4,0x75,0x37, +0x27,0xfd,0x22,0x66,0x65,0x07,0xb2,0x74,0x51,0xf8,0x00,0x05,0x7d,0x29,0xf1,0xbf, +0xc4,0x5f,0xd8,0x1e,0x01,0xbc,0x54,0x70,0xb7,0x17,0xc4,0x5a,0x46,0x3d,0x43,0x7d, +0xff,0x00,0xfc,0x74,0x37,0xe9,0x5f,0x2a,0x57,0xe7,0x1c,0x51,0x8a,0xe6,0x9c,0x30, +0xeb,0xa6,0xaf,0xe7,0xb1,0xe1,0xe6,0x15,0x2f,0x25,0x4f,0xe6,0x14,0x51,0x45,0x7c, +0x29,0xe3,0x9a,0x5e,0x1a,0x92,0xc6,0x2d,0x7f,0x4f,0x93,0x52,0x25,0x6c,0x23,0x99, +0x5e,0x6d,0xab,0xb8,0x95,0x07,0x24,0x60,0x7a,0xe3,0x1f,0x8d,0x7d,0x2b,0x1f,0xc7, +0x9f,0x06,0xb0,0x03,0xed,0xf2,0xaf,0xd6,0xda,0x4f,0xf0,0xaf,0x96,0x28,0xaf,0x6b, +0x01,0x9b,0x56,0xcb,0xa3,0x28,0xd2,0x49,0xdf,0xbf,0xfc,0x39,0xd7,0x47,0x13,0x3a, +0x09,0xa8,0xad,0xcf,0xaa,0xcf,0xc7,0x5f,0x06,0x81,0x9f,0xed,0x37,0xff,0x00,0xc0, +0x69,0x3f,0xf8,0x9a,0xc7,0xd6,0x3f,0x68,0xcf,0x0e,0xda,0x44,0xc2,0xc6,0xde,0xef, +0x50,0x97,0xb0,0xd9,0xe5,0xaf,0xe2,0x4f,0x3f,0xa5,0x7c,0xd9,0x45,0x7a,0x53,0xe2, +0x6c,0x6c,0x95,0x92,0x8a,0xf9,0x7f,0xc1,0x37,0x79,0x85,0x67,0xb5,0x8e,0xa7,0xc7, +0x5f,0x11,0x35,0x5f,0x1e,0xdd,0xab,0xde,0x32,0xc3,0x69,0x19,0x26,0x1b,0x48,0xbe, +0xe2,0x7b,0x9f,0x53,0xee,0x7f,0x0c,0x57,0x2d,0x45,0x6b,0xe9,0x1e,0x12,0xd6,0xb5, +0xed,0xa7,0x4f,0xd2,0xee,0xae,0x91,0xba,0x3c,0x71,0x1d,0x9f,0xf7,0xd7,0x4f,0xd6, +0xbe,0x72,0x73,0xad,0x8b,0xa8,0xe5,0x2b,0xca,0x4f,0xe6,0x70,0xc9,0xce,0xac,0xae, +0xf5,0x66,0x45,0x69,0x78,0x7b,0xc3,0xb7,0xfe,0x29,0xd5,0x21,0xd3,0xf4,0xe8,0x0c, +0xd7,0x12,0x1f,0xf8,0x0a,0x0e,0xec,0xc7,0xb0,0x15,0xe9,0x5e,0x18,0xfd,0x9d,0x75, +0x7d,0x45,0xd2,0x4d,0x66,0xe2,0x3d,0x36,0x0e,0x09,0x8a,0x32,0x24,0x94,0x8f,0x4e, +0x38,0x1f,0x99,0xfa,0x57,0xb9,0x78,0x4f,0xc1,0x7a,0x57,0x82,0xec,0x3e,0xcb,0xa6, +0x5b,0x08,0xb3,0x83,0x24,0xad,0xcc,0x92,0x1f,0x56,0x6e,0xff,0x00,0x4e,0x83,0xb0, +0x15,0xf4,0x79,0x7f,0x0f,0xe2,0x31,0x12,0x52,0xc4,0x2e,0x48,0xfe,0x2f,0xfa,0xf3, +0x3b,0xa8,0x60,0xa7,0x37,0x79,0xe8,0x8a,0xfe,0x01,0xf0,0x5d,0xaf,0x81,0xbc,0x3f, +0x0e,0x9f,0x6e,0x7c,0xc9,0x4f,0xcf,0x3c,0xf8,0xc1,0x95,0xcf,0x53,0xf4,0xec,0x3d, +0x85,0x74,0xb4,0x94,0xb5,0xfa,0x7d,0x2a,0x51,0xa3,0x05,0x4e,0x0a,0xc9,0x1f,0x43, +0x18,0xa8,0xa5,0x15,0xb0,0x51,0x45,0x15,0xa9,0x41,0x5e,0x6f,0xf1,0xeb,0x5c,0xfe, +0xc9,0xf0,0x05,0xc4,0x0a,0xdb,0x65,0xbe,0x91,0x6d,0xd7,0x1e,0x99,0xdc,0xdf,0xa0, +0x23,0xf1,0xaf,0x47,0x3d,0x2b,0xe7,0x8f,0xda,0x4f,0x5b,0xfb,0x4e,0xbd,0xa6,0x69, +0x68,0xdf,0x25,0xac,0x26,0x67,0x03,0xfb,0xce,0x70,0x3f,0x20,0xbf,0xad,0x78,0x79, +0xd5,0x7f,0xab,0xe0,0x6a,0x49,0x6e,0xf4,0xfb,0xce,0x4c,0x5c,0xf9,0x28,0xc9,0x9e, +0x39,0x45,0x14,0x57,0xe3,0x67,0xca,0x85,0x7a,0x67,0xec,0xfb,0xa2,0xff,0x00,0x69, +0x78,0xec,0x5d,0xba,0x93,0x1d,0x84,0x0d,0x2e,0x7b,0x07,0x6f,0x95,0x41,0xfc,0x0b, +0x1f,0xc2,0xbc,0xce,0xbe,0x89,0xfd,0x9b,0x74,0x41,0x6b,0xe1,0xdd,0x47,0x54,0x65, +0x22,0x4b,0xc9,0xc4,0x4a,0x4f,0x42,0x91,0x8e,0x08,0xfc,0x59,0x87,0xe1,0x5e,0xf6, +0x47,0x43,0xdb,0xe3,0xe0,0x9e,0xcb,0x5f,0xbb,0xfe,0x09,0xd9,0x84,0x87,0x3d,0x68, +0xf9,0x6a,0x7b,0x08,0xe9,0x4b,0x45,0x15,0xfb,0x11,0xf5,0x21,0x48,0x4e,0x29,0x6a, +0x9e,0xad,0xa8,0xc5,0xa4,0xe9,0xb7,0x57,0xb3,0x9c,0x43,0x6f,0x13,0x4a,0xe7,0xd9, +0x41,0x27,0xf9,0x54,0xc9,0xa8,0xa6,0xde,0xc2,0x6e,0xda,0xb3,0xc3,0x3f,0x68,0x9f, +0x1b,0xb5,0xc5,0xdc,0x3e,0x1b,0xb5,0x90,0x88,0xa2,0x02,0x6b,0xbd,0xa7,0xef,0x31, +0xe5,0x50,0xfd,0x07,0xcd,0x8f,0x71,0xe9,0x5e,0x27,0x57,0x35,0x9d,0x52,0x7d,0x6f, +0x55,0xbb,0xd4,0x2e,0x4e,0x67,0xb9,0x95,0xa5,0x7f,0xa9,0x39,0xc7,0xd0,0x74,0xfc, +0x2a,0x9d,0x7e,0x25,0x98,0x62,0xe5,0x8d,0xc4,0xca,0xb3,0xdb,0xa7,0xa7,0x43,0xe4, +0xab,0xd5,0x75,0xaa,0x39,0x30,0xa2,0x8a,0x2b,0xce,0x30,0x3a,0x5f,0x87,0xde,0x0a, +0x9f,0xc7,0x5e,0x22,0x86,0xc2,0x32,0x63,0xb7,0x5f,0xde,0x5c,0x4c,0x07,0xdc,0x8f, +0xbf,0xe2,0x7a,0x0f,0xfe,0xb5,0x7d,0x71,0xa3,0x69,0x16,0x9a,0x16,0x9b,0x05,0x8d, +0x8c,0x2b,0x6f,0x6b,0x02,0xed,0x48,0xd0,0x71,0xf5,0x3e,0xa4,0xf5,0x27,0xa9,0xae, +0x13,0xe0,0x4f,0x84,0xd7,0xc3,0xde,0x0d,0x8a,0xf2,0x44,0x02,0xf3,0x52,0xc5,0xc3, +0x92,0x39,0x11,0xff,0x00,0xcb,0x31,0xf9,0x73,0xf5,0x63,0x5e,0x93,0x5f,0xad,0x64, +0x59,0x7c,0x70,0x98,0x75,0x52,0x4b,0xdf,0x9e,0xaf,0xc9,0x74,0x47,0xd2,0xe0,0xe8, +0x2a,0x54,0xd4,0x9e,0xec,0x4a,0x5a,0x28,0xaf,0xa6,0x3d,0x00,0xa2,0x8a,0x28,0x03, +0x8c,0xf8,0xb1,0xe1,0x58,0xbc,0x55,0xe0,0xbb,0xe8,0x76,0x03,0x75,0x6e,0x86,0xe2, +0xdd,0xb1,0xc8,0x75,0x19,0xc0,0xfa,0x8c,0x8f,0xc6,0xbe,0x47,0xaf,0xb9,0xe4,0x50, +0xe8,0x54,0x8c,0x82,0x30,0x6b,0xe2,0x0d,0x46,0x11,0x6f,0xa8,0xdd,0x42,0x3a,0x47, +0x2b,0xa0,0xfc,0x09,0x15,0xf9,0xd7,0x14,0xd0,0x8c,0x67,0x4e,0xb2,0xdd,0xdd,0x3f, +0x91,0xe1,0x66,0x30,0x49,0xc6,0x5d,0xca,0xf4,0x51,0x45,0x7c,0x21,0xe3,0x85,0x7d, +0x49,0xf0,0x17,0x5a,0x6d,0x57,0xe1,0xf5,0xb4,0x4e,0xe5,0xe4,0xb2,0x95,0xed,0xc9, +0x3e,0x83,0xe6,0x51,0xf8,0x2b,0x01,0xf8,0x57,0xcb,0x75,0xf4,0x27,0xec,0xcf,0x29, +0x3a,0x0e,0xb3,0x1f,0x65,0xba,0x56,0xfc,0xd3,0x1f,0xd2,0xbe,0xa7,0x86,0xea,0x38, +0x63,0x94,0x57,0x54,0xff,0x00,0xcc,0xf4,0x70,0x12,0x6a,0xb5,0xbb,0x9e,0xcc,0x6b, +0xe5,0x2f,0x8e,0x1a,0x9b,0xea,0x3f,0x11,0xb5,0x14,0x66,0x2d,0x1d,0xa8,0x48,0x23, +0x1e,0x80,0x28,0x27,0xff,0x00,0x1e,0x66,0xaf,0xab,0x3b,0x57,0xc8,0xdf,0x17,0x6d, +0x5a,0xd3,0xe2,0x3e,0xb8,0xad,0xd5,0xa6,0x12,0x0f,0xa3,0x28,0x23,0xf9,0xd7,0xd3, +0x71,0x3c,0xa4,0xb0,0x91,0x4b,0x67,0x2f,0xd1,0x9d,0xf9,0x83,0xfd,0xd2,0xf5,0x38, +0xfa,0x28,0xa2,0xbf,0x30,0x3e,0x7c,0x2b,0xb7,0xf8,0x35,0xa3,0xd9,0xeb,0x5e,0x3f, +0xb0,0x8a,0xf7,0x6b,0x45,0x18,0x69,0x96,0x37,0xe4,0x48,0xca,0x32,0xa3,0xf3,0xe7, +0xf0,0xae,0x22,0xac,0xe9,0xba,0x8d,0xce,0x91,0x7f,0x05,0xed,0xa4,0xcd,0x05,0xcc, +0x0e,0x1e,0x39,0x13,0xaa,0x91,0x5d,0x38,0x6a,0x91,0xa3,0x5e,0x15,0x26,0xae,0x93, +0x4e,0xc5,0xd3,0x92,0x8c,0xd4,0x9e,0xc7,0xdb,0xea,0x38,0xc5,0x3b,0x15,0xe2,0xbe, +0x10,0xfd,0xa3,0x2c,0xe7,0x8d,0x21,0xf1,0x0d,0xb3,0xda,0xcc,0x38,0x37,0x56,0xeb, +0xba,0x33,0xee,0x57,0xa8,0xfc,0x33,0x5e,0xa7,0xa3,0x78,0xbb,0x46,0xf1,0x0a,0x06, +0xd3,0xb5,0x2b,0x6b,0xbf,0x55,0x8e,0x41,0xb8,0x7d,0x57,0xa8,0xaf,0xd9,0x70,0xb9, +0x86,0x17,0x16,0x93,0xa5,0x35,0xe9,0xd7,0xee,0x3e,0xae,0x9d,0x7a,0x75,0x7e,0x16, +0x6b,0xe2,0x82,0x29,0x37,0x52,0xe6,0xbd,0x23,0x70,0xc7,0xe3,0x4c,0x9e,0xde,0x3b, +0x98,0xda,0x39,0x51,0x64,0x8d,0x86,0x19,0x1d,0x72,0x08,0xf4,0x22,0xa4,0xa2,0x95, +0x93,0xdc,0x2c,0x50,0xd2,0x74,0x2b,0x0d,0x06,0x29,0x62,0xd3,0xed,0x21,0xb3,0x8a, +0x49,0x0c,0xad,0x1c,0x08,0x15,0x4b,0x10,0x01,0x38,0x1f,0x41,0x57,0xe8,0xa2,0x94, +0x62,0xa2,0xad,0x15,0x64,0x24,0x92,0xd1,0x05,0x14,0x51,0x54,0x30,0xae,0x67,0xe2, +0x24,0xfe,0x47,0x85,0x2f,0x5b,0xa1,0xdb,0x8a,0xe9,0xab,0x88,0xf8,0xbd,0x71,0xf6, +0x7f,0x07,0xdc,0x1c,0xe3,0x3f,0xe1,0x5c,0xb8,0xa9,0x72,0xd0,0x9b,0xf2,0x66,0x35, +0x9d,0xa9,0xc9,0x9f,0x08,0x78,0xa6,0x5d,0xfa,0x9d,0xe3,0x67,0xf8,0xcd,0x79,0xb7, +0xc3,0x9b,0x15,0xd7,0x3f,0x6a,0xdf,0x86,0x16,0x6f,0xc8,0x1a,0xd4,0x73,0xe3,0xde, +0x25,0x69,0x47,0xea,0x95,0xdf,0x6b,0xaf,0xba,0x7b,0x86,0xf5,0x63,0x5c,0x9f,0xec, +0xe3,0x0b,0xea,0x3f,0xb6,0xaf,0xc3,0xb4,0x0b,0xb9,0x21,0x96,0xf6,0x66,0xf6,0x0b, +0x67,0x3e,0x0f,0xe6,0x45,0x7c,0x36,0x48,0xaf,0x56,0xe7,0xe4,0x38,0x15,0xed,0x33, +0x9a,0x5e,0xad,0x9f,0xab,0x7b,0x68,0xa5,0xcd,0x15,0xfa,0x21,0xfb,0x08,0xb4,0x51, +0x45,0x22,0xc4,0xcd,0x7c,0xcb,0xfb,0x60,0xf8,0xbc,0xee,0xd1,0xfc,0x33,0x0b,0xe0, +0x1c,0xdf,0x5c,0x80,0x4f,0xba,0xc6,0x3e,0x9f,0x7c,0xfe,0x02,0xbe,0x97,0x95,0xc4, +0x68,0xce,0xc4,0x2a,0xa8,0x24,0x92,0x70,0x00,0xaf,0xcf,0xaf,0x89,0xbe,0x2c,0x93, +0xc6,0xfe,0x3c,0xd6,0x35,0x56,0x72,0xf1,0x4b,0x39,0x8e,0x01,0x9c,0x85,0x89,0x7e, +0x54,0xc7,0xe0,0x33,0xf8,0xd7,0xce,0x67,0x98,0x8f,0x63,0x86,0xf6,0x6b,0x79,0x69, +0xf2,0xea,0x7c,0xc7,0x10,0x62,0x7d,0x96,0x17,0xd9,0x47,0x79,0xbb,0x7c,0xba,0x9e, +0x89,0xfb,0x2d,0x78,0x47,0xfb,0x6b,0xc6,0x8d,0xa9,0xcb,0x1e,0xe8,0x2c,0x17,0x70, +0x27,0xa6,0xf3,0xd2,0xbe,0xc4,0x1d,0x2b,0xca,0x3f,0x67,0x0f,0x08,0xff,0x00,0xc2, +0x37,0xf0,0xfe,0x09,0xe4,0x4d,0xb7,0x17,0xc7,0xce,0x62,0x47,0x38,0xed,0x5e,0xaf, +0x5d,0x19,0x3e,0x1f,0xd8,0x61,0x63,0x7d,0xe5,0xab,0xf9,0xff,0x00,0xc0,0x3d,0x0c, +0xab,0x0d,0xf5,0x6c,0x24,0x62,0xf7,0x7a,0xb1,0x68,0xa2,0x8a,0xf6,0xcf,0x5c,0x29, +0x09,0xa5,0xa4,0xc5,0x00,0x7f,0x37,0xdf,0xb5,0x6f,0x8c,0xaf,0x3c,0x7d,0xfb,0x4a, +0x7c,0x4c,0xd6,0xef,0x9c,0xc9,0x34,0xda,0xfd,0xe4,0x28,0x4f,0x55,0x8a,0x29,0x4c, +0x51,0x2f,0xe1,0x1c,0x68,0x3f,0x0a,0xfd,0x53,0xfd,0x82,0x7f,0x6c,0xcf,0x83,0xf6, +0x1f,0xb3,0x47,0x85,0xfc,0x31,0xa9,0xf8,0xa7,0x4c,0xf0,0xae,0xbb,0xe1,0xbb,0x13, +0x6f,0x77,0xa7,0x6a,0x93,0xad,0xb1,0x99,0x94,0xb3,0x19,0x62,0x67,0x20,0x49,0xbf, +0x24,0xe0,0x1c,0xe4,0x90,0x47,0x4a,0xf8,0x47,0xfe,0x0a,0x39,0xfb,0x2b,0x78,0x83, +0xe0,0x87,0xc7,0x0f,0x10,0xf8,0xa2,0x1d,0x3e,0x69,0xfc,0x11,0xe2,0x7b,0xf9,0x75, +0x1b,0x2d,0x4a,0x35,0xdd,0x1c,0x32,0xca,0xdb,0xe5,0x82,0x4c,0x0f,0x91,0x83,0xb3, +0x6d,0xcf,0x55,0x23,0x07,0x39,0x03,0xe4,0x43,0xc7,0x19,0xaa,0x22,0xf6,0x67,0xaf, +0x6b,0x7a,0xcd,0xcf,0xed,0x4b,0xfb,0x51,0x5c,0xea,0x1a,0x95,0xf2,0x58,0x0f,0x17, +0x78,0x83,0x32,0x5d,0x5d,0xca,0xa8,0xb6,0x76,0xaf,0x20,0x03,0x73,0x36,0x00,0x11, +0xc2,0x00,0xe7,0xfb,0x95,0xfa,0x69,0xfb,0x5b,0xff,0x00,0xc1,0x44,0x3e,0x1f,0x7c, +0x15,0xf8,0x50,0xfe,0x01,0xf8,0x43,0xac,0xda,0x78,0x83,0xc4,0xc7,0x4f,0x5d,0x32, +0xd2,0xe7,0x49,0x71,0x2d,0xa6,0x95,0x08,0x4f,0x2c,0x48,0x65,0x19,0x57,0x90,0x28, +0xf9,0x55,0x49,0xc1,0xc1,0x38,0xc6,0x0f,0xe3,0x6f,0x5a,0xf5,0x3f,0x80,0xff,0x00, +0xb3,0x47,0xc4,0x3f,0xda,0x3b,0xc4,0x91,0x69,0x3e,0x0b,0xd0,0x66,0xbc,0x8b,0x78, +0x17,0x3a,0x9c,0xe0,0xc7,0x65,0x6a,0x33,0xcb,0x4b,0x2e,0x30,0x31,0x9f,0xba,0x32, +0xc7,0xb0,0x34,0x09,0x17,0x3f,0x65,0xcf,0x80,0x7a,0xc7,0xed,0x37,0xf1,0xb7,0x43, +0xf0,0x8d,0x92,0xcc,0x6d,0x27,0x9b,0xed,0x3a,0xb5,0xf8,0xc9,0xfb,0x35,0xa2,0x90, +0x65,0x90,0x9e,0x79,0x3f,0x75,0x73,0xd5,0x99,0x6b,0xfa,0x2e,0xd2,0xb4,0xcb,0x6d, +0x13,0x4b,0xb4,0xd3,0xec,0xa2,0x58,0x2c,0xed,0x21,0x48,0x21,0x89,0x06,0x02,0x22, +0xa8,0x55,0x03,0xe8,0x00,0xaf,0x0f,0xfd,0x90,0xff,0x00,0x64,0x5f,0x0d,0x7e,0xc9, +0xbe,0x00,0x1a,0x4e,0x98,0xcb,0xaa,0x78,0x86,0xfb,0x6c,0x9a,0xb6,0xb6,0xf1,0xed, +0x7b,0x99,0x00,0xe1,0x50,0x73,0xb2,0x35,0xe7,0x6a,0xe4,0xf5,0x24,0x92,0x6b,0xdd, +0x2f,0x6f,0x22,0xb0,0xb4,0x9e,0xe6,0x76,0xd9,0x0c,0x31,0xb4,0x8e,0xc7,0xb2,0x81, +0x92,0x7f,0x2a,0x87,0x24,0x95,0xd9,0x5b,0x23,0xe7,0x6f,0xda,0x2f,0xc4,0x7f,0xda, +0x1e,0x26,0xb5,0xd2,0xa3,0x6c,0xc7,0x61,0x16,0xe7,0x19,0xe3,0xcc,0x7c,0x1f,0xd1, +0x42,0xfe,0x75,0xe4,0x95,0xa1,0xe2,0x0d,0x62,0x4f,0x10,0x6b,0x97,0xfa,0x94,0xbf, +0x7e,0xea,0x66,0x97,0x1e,0x80,0x9e,0x07,0xe0,0x30,0x3f,0x0a,0xcf,0xaf,0xc4,0x31, +0xf8,0x87,0x8a,0xc5,0x4e,0xb7,0x77,0xf8,0x74,0x3e,0x4a,0xb5,0x4f,0x6b,0x51,0xcc, +0x28,0xa2,0xba,0x5f,0x87,0x1e,0x1f,0xff,0x00,0x84,0x9f,0xc6,0xba,0x5d,0x8b,0x2e, +0xe8,0x4c,0xa2,0x49,0x81,0xe9,0xb1,0x7e,0x66,0x07,0xeb,0x8c,0x7e,0x35,0xcb,0x46, +0x94,0xab,0x54,0x8d,0x28,0xef,0x27,0x6f,0xbc,0xce,0x31,0x73,0x92,0x8a,0xea,0x61, +0x49,0xa7,0xdd,0x43,0xfe,0xb2,0xda,0x64,0xff,0x00,0x7a,0x32,0x2a,0xb9,0x18,0x35, +0xf7,0x40,0x41,0x80,0x36,0x8c,0x56,0x37,0x88,0x3c,0x17,0xa3,0x78,0x9e,0xd9,0xe1, +0xd4,0x34,0xe8,0x27,0xdc,0x31,0xe6,0x6c,0x02,0x45,0xf7,0x0c,0x39,0x15,0xf7,0x15, +0x38,0x56,0x49,0x5e,0x9d,0x5b,0xbf,0x35,0xff,0x00,0x04,0xf5,0xe5,0x97,0x3b,0x7b, +0xb2,0x3e,0x30,0xa2,0xba,0x4f,0x88,0x3e,0x0e,0x97,0xc0,0xfe,0x26,0xb8,0xd3,0x5d, +0x8c,0x90,0xe0,0x4b,0x04,0xad,0xd5,0xe3,0x3d,0x09,0xf7,0x18,0x20,0xfb,0x8a,0xe6, +0xeb,0xe1,0xaa,0xd2,0x9d,0x1a,0x8e,0x9c,0xd5,0x9a,0xd0,0xf2,0x25,0x17,0x06,0xe2, +0xfa,0x05,0x74,0x7e,0x0d,0xf1,0xde,0xab,0xe0,0x9d,0x4a,0x3b,0x8b,0x2b,0x87,0x36, +0xfb,0x81,0x96,0xd5,0x98,0xf9,0x72,0xaf,0x70,0x47,0x63,0xef,0xd4,0x57,0x39,0x45, +0x14,0xaa,0xce,0x8c,0xd5,0x4a,0x6e,0xcd,0x04,0x64,0xe0,0xf9,0xa3,0xb9,0xf7,0x06, +0x95,0xa8,0xc3,0xab,0xe9,0xb6,0xd7,0xb6,0xed,0xba,0x0b,0x88,0xd6,0x54,0x3e,0xc4, +0x64,0x7f,0x3a,0xb7,0x5c,0x27,0xc1,0x2b,0xef,0xb7,0x7c,0x37,0xd2,0x49,0x39,0x68, +0x83,0xc2,0x7f,0xe0,0x2e,0x40,0xfd,0x31,0x5d,0xdd,0x7e,0xe5,0x86,0xab,0xed,0xe8, +0x42,0xaf,0x74,0x9f,0xde,0x8f,0xaf,0xa7,0x2e,0x78,0x29,0x77,0x0a,0x28,0xa2,0xba, +0x4d,0x02,0x8a,0x28,0xa0,0x04,0x27,0x00,0xd7,0xc7,0x1f,0x11,0x35,0xcf,0xf8,0x48, +0xbc,0x6d,0xac,0x5f,0x2b,0x07,0x8d,0xa7,0x64,0x8c,0x8e,0x85,0x17,0xe5,0x53,0xf8, +0x80,0x0f,0xe3,0x5f,0x54,0x78,0xf7,0x5d,0xff,0x00,0x84,0x73,0xc1,0xfa,0xb6,0xa0, +0xae,0x12,0x48,0xad,0xdb,0xcb,0x2d,0xd3,0x79,0x18,0x4f,0xfc,0x78,0x8a,0xf8,0xcc, +0x0c,0x0c,0x57,0xc0,0x71,0x4d,0x7d,0x29,0xd0,0x5e,0xaf,0xf2,0x5f,0xa9,0xe2,0xe6, +0x33,0xf8,0x60,0x2d,0x14,0x51,0x5f,0x9f,0x1e,0x20,0x57,0xd8,0xdf,0x0e,0xb4,0x4f, +0xec,0x0f,0x04,0xe8,0xf6,0x44,0x61,0xd6,0xdd,0x5d,0xc7,0xfb,0x4d,0xf3,0x37,0xea, +0xc6,0xbe,0x53,0xf0,0x5e,0x91,0xfd,0xbf,0xe2,0xcd,0x27,0x4f,0xc6,0x56,0x7b,0x94, +0x0e,0x3f,0xd9,0x07,0x2d,0xfa,0x03,0x5f,0x68,0x28,0x01,0x40,0x1c,0x01,0x5f,0x7f, +0xc2,0xd4,0x3f,0x89,0x5d,0xfa,0x7e,0xaf,0xf4,0x3d,0xac,0xba,0x1f,0x14,0xfe,0x41, +0x4b,0x45,0x15,0xfa,0x09,0xed,0x85,0x79,0xb7,0xc7,0xed,0x63,0xfb,0x2f,0xe1,0xfc, +0xf0,0xa9,0x2b,0x25,0xf4,0xc9,0x6e,0xa4,0x7a,0x67,0x73,0x7e,0x88,0x47,0xe3,0x5e, +0x93,0x5e,0x17,0xfb,0x4e,0x6a,0x0e,0xb1,0xe8,0x36,0x4a,0x7e,0x46,0x32,0xcc,0xc3, +0xdc,0x6d,0x03,0xf9,0xb5,0x78,0xd9,0xc5,0x57,0x47,0x01,0x56,0x4b,0xb5,0xbe,0xfd, +0x0e,0x5c,0x54,0xb9,0x28,0xc9,0x9e,0x11,0x45,0x14,0x57,0xe3,0x07,0xca,0x05,0x5e, +0xd0,0xb4,0xc6,0xd6,0xb5,0xab,0x0d,0x3d,0x0e,0x1a,0xea,0x74,0x87,0x3e,0x9b,0x88, +0x19,0xaa,0x35,0xda,0x7c,0x1b,0xb4,0x5b,0xdf,0x89,0x3a,0x2a,0x3f,0xdd,0x57,0x79, +0x3f,0x15,0x8d,0x88,0xfd,0x40,0xae,0xac,0x2d,0x3f,0x6d,0x5e,0x14,0xdf,0x56,0x97, +0xe2,0x69,0x4e,0x3c,0xd3,0x8c,0x7c,0xcf,0xac,0xad,0xa0,0x8e,0xd6,0xde,0x28,0x62, +0x50,0x91,0x46,0xa1,0x11,0x47,0x40,0x00,0xc0,0x02,0xa5,0xa4,0x14,0xb5,0xfb,0xaa, +0x49,0x2b,0x23,0xec,0x42,0x8a,0x28,0xa6,0x01,0x45,0x14,0x50,0x04,0x73,0x38,0x86, +0x27,0x76,0x38,0x55,0x04,0x93,0xf8,0x57,0xc3,0xd7,0x93,0x7d,0xa6,0xf2,0x79,0xbf, +0xe7,0xa4,0x8c,0xff,0x00,0x99,0xcd,0x7d,0x79,0xf1,0x37,0x5a,0x5d,0x07,0xc0,0xba, +0xc5,0xd1,0x38,0x73,0x01,0x8a,0x3c,0x1e,0x77,0x3f,0xca,0x3f,0x9e,0x7f,0x0a,0xf8, +0xf6,0xbf,0x3a,0xe2,0x9a,0xa9,0xce,0x95,0x25,0xd1,0x36,0x78,0x59,0x8c,0xb5,0x8c, +0x42,0x8a,0x28,0xaf,0x84,0x3c,0x70,0xaf,0xa1,0xff,0x00,0x66,0x98,0x36,0xf8,0x6b, +0x56,0x97,0x04,0x6f,0xbb,0x0b,0x9f,0xa2,0x0f,0xf1,0xaf,0x9e,0x3a,0xd7,0xd5,0x5f, +0x02,0xf4,0xa6,0xd3,0x3e,0x1d,0x58,0x3b,0xae,0xd9,0x2e,0x9d,0xee,0x08,0xf6,0x27, +0x0b,0xff,0x00,0x8e,0x81,0x5f,0x55,0xc3,0x74,0xdc,0xf1,0xdc,0xdd,0x93,0xff,0x00, +0x23,0xd1,0xc0,0x46,0xf5,0xaf,0xd9,0x1e,0x81,0x8e,0x2b,0xc3,0xbf,0x68,0x6f,0x02, +0xcd,0x71,0xe4,0xf8,0x8e,0xce,0x33,0x20,0x89,0x04,0x57,0x61,0x47,0x21,0x73,0xf2, +0xbf,0xe1,0x9c,0x1f,0xc3,0xde,0xbd,0xc4,0x53,0x66,0x85,0x27,0x8d,0xa3,0x91,0x16, +0x44,0x71,0xb5,0x95,0x86,0x41,0x1e,0x86,0xbf,0x46,0xc7,0x60,0xe1,0x8e,0xa1,0x2a, +0x33,0xeb,0xf8,0x33,0xdd,0xad,0x49,0x56,0x83,0x83,0x3e,0x17,0xa2,0xbd,0xc7,0xe2, +0x1f,0xec,0xff,0x00,0x20,0x96,0x5b,0xff,0x00,0x0d,0x60,0xa3,0x65,0x9b,0x4f,0x76, +0xc1,0x53,0xff,0x00,0x4c,0xd8,0xff,0x00,0x23,0xef,0xcf,0x41,0x5e,0x2d,0x7f,0xa7, +0x5d,0x69,0x57,0x2f,0x6f,0x79,0x6f,0x2d,0xac,0xe9,0xf7,0xa3,0x95,0x0a,0xb0,0xfc, +0x0d,0x7e,0x43,0x8c,0xcb,0xf1,0x18,0x19,0xb8,0xd5,0x8e,0x9d,0xfa,0x33,0xe6,0x2a, +0xd0,0x9d,0x17,0x69,0x22,0xbd,0x14,0x51,0x5e,0x69,0x80,0x52,0xab,0x14,0x60,0xca, +0x4a,0xb0,0x39,0x04,0x1c,0x11,0x49,0x45,0x34,0xed,0xaa,0x03,0xab,0xd1,0xbe,0x29, +0xf8,0xa7,0x41,0xda,0xb6,0xba,0xcd,0xc3,0x46,0x08,0xfd,0xdd,0xc1,0xf3,0x94,0x8f, +0x4f,0x9b,0x24,0x0f,0xa6,0x2b,0xd1,0x34,0x0f,0xda,0x56,0x65,0x65,0x4d,0x6b,0x4a, +0x57,0x52,0x79,0x9a,0xc9,0x88,0x20,0x7f,0xb8,0xc7,0x9f,0xfb,0xe8,0x57,0x88,0x51, +0x5e,0xae,0x1f,0x35,0xc6,0x61,0xbf,0x87,0x51,0xdb,0xb3,0xd5,0x7e,0x27,0x4c,0x31, +0x35,0x69,0xfc,0x32,0x3e,0xc3,0xf0,0xc7,0xc4,0x9f,0x0f,0xf8,0xb8,0x2a,0xe9,0xf7, +0xe8,0x6e,0x08,0xcf,0xd9,0xa5,0xf9,0x25,0x1f,0xf0,0x13,0xd7,0xf0,0xcd,0x74,0xf9, +0xaf,0x85,0x91,0xda,0x37,0x57,0x46,0x2a,0xca,0x72,0x18,0x1c,0x10,0x6b,0xd6,0x7e, +0x1c,0xfc,0x75,0xbe,0xd1,0x25,0x8a,0xc7,0x5e,0x77,0xbf,0xd3,0xce,0x14,0x5c,0x9e, +0x66,0x8b,0xeb,0xfd,0xe1,0xf5,0xe7,0xeb,0xd2,0xbe,0xcb,0x01,0xc4,0xb0,0xaa,0xd5, +0x3c,0x52,0xe5,0x7d,0xd6,0xdf,0x3e,0xc7,0xab,0x47,0x1e,0xa4,0xf9,0x6a,0x2b,0x1f, +0x48,0xd1,0x50,0x59,0x5e,0xc1,0xa8,0x5a,0xc5,0x73,0x6d,0x2a,0xcf,0x6f,0x2a,0x87, +0x8e,0x44,0x39,0x56,0x53,0xd0,0x83,0x53,0xd7,0xdb,0xa6,0x9a,0xba,0x3d,0x7d,0xc2, +0x8a,0x28,0xa6,0x01,0x5e,0x5f,0xf1,0xfa,0xf4,0xda,0xf8,0x48,0xa8,0xfe,0x2c,0xd7, +0xa8,0x57,0x8a,0xfe,0xd2,0xd7,0x5e,0x57,0x87,0xe3,0x4c,0xff,0x00,0x09,0x38,0xaf, +0x2f,0x33,0x97,0x2e,0x12,0xa3,0xf2,0x38,0xb1,0xb2,0xe5,0xc3,0xcd,0xf9,0x1f,0x18, +0x6b,0x32,0x65,0x65,0x6e,0xe4,0x93,0x55,0xff,0x00,0x62,0x7b,0x51,0xaa,0x7e,0xd9, +0x36,0xcf,0x8c,0x8b,0x2d,0x16,0xfa,0xe7,0xe8,0x49,0x8a,0x3c,0xff,0x00,0xe4,0x43, +0xf9,0xd1,0xad,0xbe,0xdb,0x69,0x0f,0xb1,0xad,0x6f,0xf8,0x27,0x95,0x9f,0xdb,0x3f, +0x6a,0x3f,0x15,0x5e,0xe3,0x22,0xd7,0xc3,0x72,0xc5,0xbb,0xd0,0xc9,0x73,0x01,0xff, +0x00,0xda,0x66,0xbe,0x63,0x21,0x8f,0xbd,0x73,0xf2,0xcc,0x8d,0x73,0xe7,0x09,0xf6, +0x4c,0xfd,0x29,0xdb,0x45,0x1c,0xd1,0x5f,0x79,0x73,0xf5,0xeb,0x21,0xd4,0x51,0x49, +0x48,0xa3,0xcd,0x3f,0x68,0x5f,0x18,0x9f,0x07,0xfc,0x31,0xd4,0xa4,0x85,0xf6,0x5d, +0xdf,0x62,0xc6,0x03,0xe8,0x5f,0x3b,0x8f,0xe0,0x81,0x8f,0xd4,0x0a,0xf8,0xeb,0xc0, +0x3e,0x1d,0x93,0xc5,0x3e,0x2c,0xd3,0x74,0xd8,0xd7,0x3e,0x6c,0xca,0x1b,0xd8,0x67, +0x9a,0xf5,0x7f,0xda,0xdb,0xc6,0x1f,0xda,0xbe,0x30,0xb2,0xd0,0x61,0x7c,0xc1,0xa6, +0xc3,0xe6,0x4a,0x01,0xe0,0xca,0xfe,0xbe,0xe1,0x40,0xff,0x00,0xbe,0xab,0x43,0xf6, +0x4b,0xf0,0x7f,0xda,0xb5,0x7b,0xdd,0x76,0x64,0xca,0x5b,0x2f,0x97,0x11,0x3f,0xde, +0x3d,0x6b,0xe0,0xb1,0xcd,0xe6,0x19,0x8c,0x68,0x2d,0x96,0x9f,0xe6,0x7c,0x06,0x2d, +0xbc,0xc7,0x35,0x54,0x57,0xc3,0x1d,0x3e,0xed,0x59,0xf5,0x0e,0x9f,0x65,0x1e,0x9d, +0x63,0x6f,0x6d,0x12,0x85,0x8e,0x14,0x08,0xa0,0x7a,0x01,0x8a,0xb3,0x48,0x3a,0x52, +0xd7,0xde,0x24,0x92,0xb2,0x3e,0xf9,0x2b,0x2b,0x20,0xa2,0x8a,0x29,0x8c,0x2b,0xf2, +0xdf,0xf6,0xd7,0xff,0x00,0x82,0x9b,0x78,0xf3,0xe1,0x1f,0xed,0x0d,0xa9,0xf8,0x43, +0xe1,0xcc,0x9a,0x4b,0xe8,0xfa,0x0c,0x49,0x69,0x7d,0xfd,0xa1,0x69,0xf6,0x81,0x3d, +0xe6,0x37,0x49,0x82,0x19,0x59,0x42,0x6e,0x09,0x80,0x7a,0xab,0x57,0xea,0x2c,0xb2, +0xa4,0x31,0xb3,0xc8,0xea,0x88,0xa0,0x96,0x66,0x38,0x00,0x7a,0x93,0x5f,0x84,0x3f, +0xf0,0x51,0x9f,0xd9,0xb7,0xc4,0x9f,0x0a,0xbe,0x3b,0xf8,0xa7,0xc5,0xe2,0xde,0x4d, +0x4b,0xc1,0xbe,0x27,0xd4,0x65,0xd4,0xad,0x75,0x8b,0x71,0xbe,0x28,0xe5,0x99,0x8b, +0xc9,0x04,0x84,0x67,0x63,0x2b,0xb3,0x63,0x38,0xdc,0xb8,0x23,0xb8,0x0d,0x09,0x9f, +0x6d,0x7e,0xc1,0xff,0x00,0xb5,0xcf,0xc4,0xef,0xdb,0x5b,0xc4,0xde,0x24,0xd0,0xbc, +0x73,0xe1,0x9f,0x07,0xcf,0xe0,0x9d,0x2e,0xc5,0x5f,0x51,0x78,0x74,0xf9,0x77,0x4d, +0x2c,0x84,0x88,0x62,0xdb,0x24,0xce,0x9c,0xec,0x91,0x89,0xdb,0xc0,0x4c,0x63,0x90, +0x47,0xb1,0xf8,0xbf,0xfe,0x09,0x9f,0xfb,0x3c,0xf8,0xc2,0xe9,0xae,0x64,0xf0,0x2a, +0xe9,0x13,0x39,0x25,0x8e,0x91,0x79,0x35,0xb2,0x1c,0xff,0x00,0xb0,0x1b,0x68,0xfc, +0x00,0xaf,0x84,0xbf,0xe0,0x93,0xbf,0xb5,0x1f,0x82,0x3e,0x09,0xea,0xfe,0x2e,0xf0, +0x97,0x8d,0xb5,0x2b,0x7f,0x0f,0x45,0xe2,0x09,0x2d,0xee,0x2c,0xb5,0x6b,0xaf,0x92, +0x01,0x24,0x61,0xd5,0xa2,0x96,0x4e,0x88,0x08,0x60,0x54,0x9e,0x33,0xbf,0x24,0x64, +0x67,0xf5,0xef,0x4a,0xf1,0x66,0x89,0xad,0xdb,0x47,0x71,0xa7,0xeb,0x36,0x17,0xf0, +0x48,0x01,0x49,0x6d,0xae,0x92,0x45,0x61,0xec,0x54,0x90,0x68,0x04,0x7c,0xe9,0xe1, +0x0f,0xf8,0x26,0x9f,0xec,0xf1,0xe0,0xeb,0x85,0xb8,0x8f,0xc0,0x51,0xea,0xf3,0x29, +0x05,0x5b,0x58,0xbc,0x9a,0xe5,0x47,0xfc,0x01,0x9f,0x69,0xfc,0x41,0xaf,0xa4,0x34, +0x2f,0x0f,0x69,0x7e,0x18,0xd2,0xe0,0xd3,0x74,0x7d,0x3a,0xd7,0x4a,0xd3,0xe0,0x1b, +0x62,0xb4,0xb2,0x85,0x61,0x89,0x07,0xa0,0x55,0x00,0x0a,0xd0,0x0c,0x18,0x02,0x08, +0x20,0xf7,0x14,0x64,0x1a,0x43,0x16,0xbc,0xdb,0xe3,0xcf,0x88,0xff,0x00,0xb1,0x3c, +0x0d,0x35,0xb4,0x6d,0x89,0xf5,0x17,0x16,0xeb,0x83,0xc8,0x5e,0xae,0x7e,0x98,0x18, +0xff,0x00,0x81,0x0a,0xf4,0x83,0xc0,0xaf,0x99,0x7f,0x68,0x4f,0x10,0x9d,0x5f,0xc6, +0x69,0xa7,0xa3,0x66,0x1d,0x3a,0x30,0x84,0x7f,0xd3,0x46,0xc3,0x37,0xe9,0xb4,0x7e, +0x15,0xe0,0xe7,0x78,0x9f,0xaa,0xe0,0xa6,0xd6,0xf2,0xd1,0x7c,0xff,0x00,0xe0,0x1c, +0x58,0xba,0x9e,0xce,0x93,0xf3,0x3c,0xbe,0x8a,0x28,0xaf,0xc7,0x4f,0x97,0x0a,0xf7, +0x2f,0xd9,0xaf,0xc3,0xd9,0x93,0x55,0xd6,0xa4,0x5c,0xe3,0x16,0xb1,0x1f,0xfc,0x79, +0xff,0x00,0xf6,0x5a,0xf0,0xda,0xfa,0xff,0x00,0xe1,0x77,0x87,0x8f,0x86,0x7c,0x0f, +0xa5,0x5a,0x32,0x14,0x99,0xa2,0x13,0x4c,0x0f,0x50,0xef,0xf3,0x10,0x7e,0x99,0xc7, +0xe1,0x5f,0x55,0xc3,0x98,0x6f,0x6d,0x8c,0xf6,0x8f,0x68,0x2b,0xfc,0xf6,0x47,0xa3, +0x80,0xa7,0xcf,0x57,0x9b,0xb1,0xd6,0x51,0x49,0x4b,0x5f,0xab,0x1f,0x48,0x78,0x4f, +0xed,0x35,0xa7,0x28,0x3a,0x1d,0xfa,0xaf,0xcc,0x7c,0xd8,0x5d,0xbd,0x7e,0xe9,0x5f, +0xfd,0x9b,0xf3,0xaf,0x0a,0xaf,0xa3,0xff,0x00,0x69,0x38,0x03,0xf8,0x3a,0xc2,0x5c, +0x72,0x97,0xca,0x33,0xec,0x63,0x7f,0xf0,0x15,0xf3,0x85,0x7e,0x47,0xc4,0x30,0x50, +0xcc,0x26,0xd7,0x54,0x9f,0xe0,0x7c,0xce,0x39,0x5a,0xbb,0x0a,0x28,0xa2,0xbe,0x6c, +0xe0,0x3e,0x92,0xfd,0x9b,0xef,0x84,0xfe,0x0c,0xbc,0xb6,0xce,0x5a,0x0b,0xc6,0xe3, +0xd1,0x59,0x54,0x8f,0xd7,0x35,0xeb,0x35,0xe1,0x1f,0xb3,0x1d,0xd0,0x0d,0xe2,0x0b, +0x62,0xdc,0x91,0x0c,0x8a,0xbf,0xf7,0xd8,0x27,0xf9,0x57,0xbb,0x66,0xbf,0x64,0xc9, +0x6a,0x7b,0x4c,0x05,0x27,0xd9,0x5b,0xee,0x76,0x3e,0xa7,0x09,0x2e,0x6a,0x11,0x16, +0x8a,0x28,0xaf,0x70,0xec,0x0a,0x28,0xa4,0x3d,0x28,0x03,0xc8,0x3f,0x69,0x0d,0x6f, +0xec,0x9e,0x19,0xb1,0xd3,0x11,0x80,0x7b,0xd9,0xf7,0xb0,0xf5,0x44,0xe7,0xff,0x00, +0x42,0x2b,0xf9,0x57,0xce,0x95,0xe9,0x7f,0xb4,0x06,0xb8,0x75,0x4f,0x1e,0x3d,0xa0, +0x20,0xc5,0x61,0x0a,0xc2,0x30,0x73,0xf3,0x1f,0x99,0xbf,0xf4,0x20,0x3f,0x0a,0xf3, +0x4a,0xfc,0x77,0x3b,0xaf,0xf5,0x8c,0x74,0xda,0xd9,0x69,0xf7,0x7f,0xc1,0x3e,0x5b, +0x19,0x3e,0x7a,0xcf,0xcb,0x40,0xa2,0x8a,0x2b,0xc1,0x38,0xcf,0x55,0xfd,0x9d,0x74, +0x53,0x7f,0xe3,0x2b,0x8b,0xf6,0x40,0x62,0xb1,0xb7,0x24,0x37,0xa3,0xb9,0xda,0x3f, +0x40,0xf5,0xf4,0xb5,0x79,0x2f,0xec,0xe7,0xa2,0x7d,0x87,0xc1,0xf7,0x3a,0x83,0xc6, +0x04,0x97,0xd7,0x07,0x6b,0xf7,0x31,0xa7,0xca,0x07,0xfd,0xf5,0xbf,0xf3,0xaf,0x5a, +0xaf,0xd8,0x32,0x2a,0x1e,0xc3,0x01,0x0b,0xef,0x2d,0x7e,0xff,0x00,0xf8,0x16,0x3e, +0xa3,0x07,0x0e,0x4a,0x2b,0xcf,0x50,0xa2,0x8a,0x2b,0xe8,0x0e,0xd0,0xaf,0x00,0xfd, +0xa6,0xc6,0x35,0x3d,0x04,0xf6,0x30,0xcb,0xfc,0xd6,0xbd,0xfe,0xbc,0x67,0xf6,0x97, +0xd2,0xbc,0xed,0x0f,0x49,0xd4,0x42,0x92,0x6d,0xe7,0x68,0x4e,0x07,0x00,0x3a,0xe7, +0x27,0xf1,0x41,0xf9,0xd7,0x81,0x9e,0xc1,0xcf,0x2f,0xa8,0x97,0x93,0xfc,0x4e,0x2c, +0x62,0xbd,0x09,0x1f,0x3d,0x51,0x45,0x15,0xf8,0xf1,0xf2,0xe1,0x5d,0xa7,0xc1,0xcb, +0xc4,0xb1,0xf8,0x93,0xa2,0xbb,0x9c,0x2b,0xc8,0xf1,0x7e,0x2c,0x8c,0xa3,0xf5,0x22, +0xb8,0xba,0xb1,0xa7,0xdf,0x4d,0xa5,0xdf,0xdb,0x5e,0x5b,0xb6,0xd9,0xed,0xe4,0x59, +0x50,0xfa,0x32,0x9c,0x8f,0xe5,0x5d,0x38,0x6a,0xbe,0xc2,0xbc,0x2a,0xbf,0xb2,0xd3, +0xfb,0x99,0x74,0xe5,0xc9,0x35,0x2e,0xcc,0xfb,0x88,0x52,0xd6,0x4f,0x86,0x3c,0x43, +0x6d,0xe2,0x9d,0x0e,0xcf,0x53,0xb4,0x6c,0xc5,0x70,0x81,0xb6,0xe7,0x25,0x1b,0xba, +0x9f,0x70,0x72,0x3f,0x0a,0xd6,0xaf,0xdd,0x21,0x38,0xce,0x2a,0x71,0x77,0x4c,0xfb, +0x14,0xd3,0x57,0x41,0x45,0x14,0x55,0x8c,0x28,0xa4,0xc8,0xae,0x4f,0xe2,0x2f,0x8f, +0xed,0x3c,0x07,0xa2,0xb5,0xcc,0x84,0x4b,0x7b,0x28,0x2b,0x6d,0x6d,0x9e,0x5d,0xbd, +0x4f,0xfb,0x23,0xb9,0xff,0x00,0x1a,0xc6,0xb5,0x68,0x50,0xa6,0xea,0xd4,0x76,0x48, +0x89,0x49,0x41,0x39,0x4b,0x63,0xcb,0x7f,0x68,0xdf,0x17,0x2d,0xc5,0xcd,0x9f,0x87, +0xad,0xdf,0x3e,0x41,0x17,0x37,0x38,0xec,0xc4,0x10,0x8b,0xf9,0x12,0x7f,0x11,0x5e, +0x27,0x56,0x75,0x2d,0x46,0xe3,0x56,0xbf,0x9e,0xf6,0xee,0x53,0x35,0xcc,0xee,0x64, +0x91,0xcf,0x72,0x6a,0xb5,0x7e,0x2d,0x98,0x62,0xde,0x3b,0x13,0x2a,0xcf,0xae,0xde, +0x9d,0x0f,0x94,0xaf,0x55,0xd6,0x9b,0x98,0x51,0x45,0x15,0xe7,0x18,0x16,0x74,0xcd, +0x3e,0x6d,0x5b,0x51,0xb5,0xb2,0xb6,0x5d,0xf7,0x17,0x32,0x2c,0x51,0xa9,0xe8,0x59, +0x8e,0x07,0xf3,0xaf,0xb5,0xb4,0x7d,0x3a,0x2d,0x1f,0x4a,0xb4,0xb1,0x80,0x62,0x1b, +0x68,0x96,0x14,0x1e,0xca,0x00,0x1f,0xca,0xbc,0x03,0xf6,0x78,0xf0,0x69,0xd4,0x75, +0xa9,0xb5,0xfb,0x84,0xff,0x00,0x47,0xb2,0x06,0x38,0x32,0x3e,0xf4,0xa4,0x72,0x7f, +0x05,0x3f,0x99,0xf6,0xaf,0xa2,0x87,0x4a,0xfd,0x3b,0x86,0xb0,0x8e,0x8d,0x09,0x62, +0x24,0xb5,0x9e,0xde,0x88,0xfa,0x0c,0xbe,0x97,0x2c,0x1c,0xdf,0x51,0x68,0xa4,0xcd, +0x2d,0x7d,0x91,0xea,0x88,0x46,0x6b,0x33,0x5b,0xf0,0xd6,0x97,0xe2,0x2b,0x63,0x06, +0xa5,0x61,0x05,0xec,0x7d,0x84,0xa8,0x09,0x1f,0x43,0xd4,0x7e,0x15,0xa9,0x45,0x4c, +0xa1,0x19,0xae,0x59,0x2b,0xa1,0x34,0x9a,0xb3,0x3c,0x7b,0x5f,0xfd,0x9b,0xf4,0x8b, +0xd6,0x32,0x69,0x57,0xd3,0xe9,0xac,0x4e,0x7c,0xb9,0x07,0x9d,0x18,0x1e,0x83,0x90, +0x47,0xe6,0x6b,0xce,0x35,0xdf,0x81,0x3e,0x2a,0xd1,0x81,0x78,0xad,0xa2,0xd4,0xe2, +0x19,0xf9,0xad,0x1f,0x2d,0x8e,0xdf,0x29,0xc1,0xfc,0xb3,0x5f,0x54,0x52,0x11,0x5f, +0x3d,0x88,0xc8,0x30,0x35,0xf5,0x51,0xe5,0x7e,0x5f,0xe5,0xb1,0xc3,0x3c,0x15,0x19, +0xf4,0xb7,0xa1,0xf0,0xe5,0xed,0x85,0xd6,0x9b,0x39,0x86,0xee,0xda,0x5b,0x59,0x87, +0x58,0xe6,0x42,0x8d,0xf9,0x1a,0x82,0xbe,0xdb,0xd5,0xf4,0x1d,0x3f,0x5d,0xb6,0x36, +0xfa,0x85,0x9c,0x37,0xb0,0x9f,0xe1,0x99,0x03,0x63,0xdc,0x7a,0x57,0x8b,0xfc,0x45, +0xf8,0x03,0x1d,0xbd,0xb4,0xda,0x8f,0x86,0xb7,0xe5,0x32,0xef,0x60,0xe7,0x76,0x47, +0x7d,0x84,0xf3,0x9f,0x63,0x9c,0xfa,0xf6,0xaf,0x91,0xc6,0xf0,0xe5,0x7a,0x11,0x75, +0x28,0x4b,0x9d,0x2e,0x9b,0x3f,0xf8,0x27,0x9b,0x57,0x01,0x38,0x2e,0x68,0x3b,0xa3, +0xc3,0x28,0xa0,0x8c,0x1c,0x74,0xa2,0xbe,0x40,0xf2,0xc2,0x8a,0x28,0xa0,0x0f,0x6f, +0xfd,0x9d,0xbc,0x6b,0x22,0xdc,0xcf,0xe1,0xcb,0x99,0x0b,0x46,0xca,0x67,0xb5,0xdc, +0x7e,0xe9,0x1f,0x79,0x07,0xb1,0xeb,0xf8,0x1a,0xf7,0xba,0xf8,0xf7,0xe1,0x7d,0xe3, +0xd8,0xfc,0x41,0xd0,0x64,0x8c,0xe0,0xb5,0xd2,0xc6,0x7e,0x8d,0xf2,0x9f,0xd1,0x8d, +0x7d,0x84,0x2b,0xf5,0x6e,0x1c,0xc4,0x4a,0xb6,0x13,0x92,0x6f,0xe1,0x76,0xf9,0x1f, +0x47,0x80,0xa8,0xe7,0x4a,0xcf,0xa0,0xb4,0x51,0x45,0x7d,0x51,0xe9,0x08,0x78,0xaf, +0x9f,0xbf,0x6a,0x3b,0xbd,0x96,0x51,0xc7,0x9e,0x89,0xd2,0xbe,0x81,0x35,0xf3,0x27, +0xed,0x4f,0x77,0xfe,0x90,0x23,0x07,0xf8,0x45,0x78,0x59,0xd4,0xb9,0x70,0x53,0x3c, +0xac,0xce,0x5c,0xb8,0x59,0xb3,0xe5,0x3f,0x11,0x3e,0xdb,0x19,0x4f,0xfb,0x26,0xbb, +0xef,0xf8,0x26,0x55,0x81,0xb9,0xf8,0x97,0xf1,0x53,0x53,0xed,0x0d,0xa5,0x8d,0xb0, +0x3f,0xef,0xbc,0xcd,0xff,0x00,0xb2,0x0a,0xf3,0x8f,0x16,0xc9,0xe5,0xe9,0xb3,0x9f, +0x45,0xaf,0x63,0xff,0x00,0x82,0x5b,0xdb,0x16,0xb7,0xf8,0xab,0x7d,0xb7,0x89,0x35, +0x1b,0x38,0x43,0x7a,0xec,0x8a,0x42,0x7f,0xf4,0x3a,0xf2,0xb2,0x28,0xe8,0xd9,0xf9, +0xdf,0x0d,0x47,0x9b,0x33,0x9c,0xbb,0x44,0xfb,0xb3,0x9a,0x29,0xd4,0x57,0xd9,0x1f, +0xac,0x85,0x52,0xd5,0xb5,0x28,0x74,0x9d,0x36,0xee,0xfa,0xe0,0xed,0x82,0xda,0x26, +0x99,0xcf,0xfb,0x2a,0x32,0x6a,0xed,0x78,0xaf,0xed,0x53,0xe3,0x0f,0xec,0x0f,0x87, +0xab,0xa5,0xc3,0x26,0xdb,0xad,0x5e,0x61,0x09,0x00,0xe0,0xf9,0x4b,0xf3,0x48,0x7e, +0x9f,0x75,0x7f,0xe0,0x55,0xcd,0x89,0xac,0xb0,0xf4,0x65,0x55,0xf4,0x47,0x26,0x2e, +0xba,0xc2,0xd0,0x9d,0x67,0xd1,0x1f,0x26,0x78,0x83,0x5a,0xb8,0xf1,0x6f,0x89,0x2f, +0xf5,0x4b,0x8c,0xb5,0xc5,0xf5,0xc3,0x4a,0x47,0xa6,0x4f,0x03,0xf0,0x18,0x1f,0x85, +0x7d,0xbd,0xf0,0x4b,0xc2,0x63,0xc2,0x3f,0x0f,0xf4,0xeb,0x76,0x4d,0xb3,0xcc,0x82, +0x69,0x78,0xc7,0x26,0xbe,0x43,0xf8,0x3b,0xe1,0x46,0xf1,0x77,0x8f,0x74,0xcb,0x3d, +0xbb,0xa1,0x59,0x04,0x92,0x9f,0x45,0x1c,0xd7,0xde,0xf0,0xc4,0xb0,0xc2,0x91,0xa0, +0xda,0xaa,0x00,0x03,0xda,0xbe,0x4f,0x21,0xa2,0xea,0x54,0xa9,0x89,0x9f,0xa7,0xdf, +0xab,0x3e,0x57,0x87,0xa8,0x39,0x73,0xe2,0xa7,0xbb,0xfe,0x99,0x25,0x14,0x56,0x47, +0x8b,0xfc,0x53,0xa7,0x78,0x1f,0xc2,0x9a,0xcf,0x88,0xb5,0x79,0xbe,0xcf,0xa5,0xe9, +0x36,0x73,0x5f,0x5d,0x4b,0x8c,0xec,0x8a,0x34,0x2e,0xe7,0x1d,0xf8,0x53,0x5f,0x6a, +0x7d,0xa9,0xaf,0x45,0x7e,0x2d,0xcd,0xff,0x00,0x05,0x91,0xf8,0xd2,0x35,0x2b,0x86, +0xb6,0xd1,0x7c,0x20,0xd6,0x2d,0x2b,0x18,0x22,0x9e,0xc2,0x7f,0x31,0x63,0x2c,0x76, +0xab,0x30,0x9c,0x02,0x40,0xc0,0xce,0x2b,0xf5,0x5f,0xf6,0x6a,0xf1,0xbf,0x8a,0xfe, +0x25,0x7c,0x0e,0xf0,0x8f,0x8a,0xfc,0x6b,0x65,0x63,0xa6,0xf8,0x83,0x5a,0xb3,0x5b, +0xf9,0x2d,0x34,0xe4,0x74,0x8a,0x38,0xa4,0x25,0xa1,0xe1,0xd9,0x8e,0x4c,0x65,0x09, +0xc9,0xea,0x48,0xa0,0x49,0xdc,0xf9,0xef,0xfe,0x0a,0xb9,0xf1,0xa3,0xfe,0x15,0x97, +0xec,0xc9,0x73,0xe1,0xfb,0x39,0x8c,0x7a,0xb7,0x8c,0x6e,0x06,0x96,0x81,0x7a,0x8b, +0x60,0x37,0xdc,0x1f,0xa1,0x50,0x13,0xfe,0xda,0x57,0xe2,0x00,0xd4,0x6e,0xc5,0xab, +0xdb,0x0b,0xa9,0x85,0xb3,0xfd,0xe8,0x44,0x87,0x63,0x73,0x9e,0x47,0x4e,0xa2,0xbf, +0xa2,0x9f,0x8f,0x5f,0xb2,0x2f,0xc3,0x3f,0xda,0x5e,0xfb,0x4b,0xbc,0xf1,0xf6,0x95, +0x77,0xaa,0xcd,0xa6,0x44,0xf0,0xda,0x79,0x3a,0x8c,0xd6,0xeb,0x12,0xb1,0xcb,0x7c, +0xa8,0xc0,0x12,0x48,0x19,0x24,0x67,0x81,0xe9,0x5e,0x33,0x7d,0xff,0x00,0x04,0x93, +0xfd,0x9e,0xae,0xff,0x00,0xd5,0x69,0x5a,0xed,0x97,0xfd,0x70,0xd6,0x24,0x3f,0xfa, +0x1e,0xea,0x62,0x6a,0xe7,0xe1,0xa7,0x34,0xf8,0x66,0x92,0xde,0x41,0x24,0x4e,0xd1, +0x48,0x3a,0x32,0x1c,0x11,0xf8,0xd7,0xed,0x36,0xa9,0xff,0x00,0x04,0x70,0xf8,0x23, +0x78,0xa7,0xec,0x9a,0xb7,0x8b,0xb4,0xf2,0x7b,0xa5,0xfc,0x2f,0x8f,0xfb,0xea,0x13, +0x5c,0x9d,0xff,0x00,0xfc,0x11,0x47,0xe1,0xf4,0xad,0xfe,0x85,0xf1,0x0f,0xc4,0xd6, +0xe3,0xd2,0xe2,0xde,0xde,0x5f,0xe4,0xab,0x4e,0xe2,0xb3,0x3f,0x28,0xad,0x3e,0x21, +0xf8,0xaa,0xc3,0x02,0xd7,0xc4,0xda,0xc5,0xb6,0x3a,0x08,0x6f,0xe5,0x4c,0x7e,0x4d, +0x5f,0xb1,0x9f,0xf0,0x49,0x2f,0x0c,0x78,0x9e,0x4f,0x82,0x3a,0xbf,0x8e,0x7c,0x53, +0xae,0xea,0xda,0xcc,0xbe,0x20,0xbe,0xf2,0x74,0xf4,0xd4,0xef,0x25,0x9c,0x43,0x6d, +0x06,0x54,0xb2,0x07,0x63,0x8d,0xf2,0x17,0xe9,0xd7,0x60,0xaf,0x36,0xbe,0xff,0x00, +0x82,0x23,0xe8,0x0e,0xa7,0xec,0x9f,0x15,0xb5,0x28,0x4f,0xfd,0x36,0xd1,0xa3,0x93, +0xf9,0x4c,0xb5,0xfa,0x0f,0xf0,0x97,0xe1,0xbe,0x9f,0xf0,0x87,0xe1,0x9f,0x86,0x7c, +0x19,0xa5,0xb6,0xfb,0x1d,0x12,0xc2,0x2b,0x28,0xe5,0x2b,0xb4,0xc9,0xb5,0x70,0xce, +0x47,0x38,0x2c,0xd9,0x63,0xcf,0x52,0x69,0x31,0xa4,0xce,0x8f,0x55,0xd4,0x62,0xd2, +0x74,0xdb,0xab,0xd9,0xdb,0x6c,0x36,0xf1,0x34,0xae,0x7d,0x94,0x64,0xd7,0xc5,0x5a, +0xb6,0xa5,0x2e,0xb1,0xaa,0x5d,0xdf,0x4e,0x73,0x35,0xcc,0xad,0x2b,0x7d,0x49,0xcd, +0x7d,0x6b,0xf1,0x2b,0xc3,0xba,0x97,0x8a,0xfc,0x29,0x73,0xa5,0x69,0x93,0x41,0x04, +0xd7,0x0c,0xa1,0xde,0x76,0x65,0x1b,0x01,0xc9,0x03,0x00,0xf2,0x70,0x07,0xd0,0x9a, +0xf1,0x39,0x7f,0x67,0x2f,0x13,0xa2,0x92,0xb7,0x3a,0x6c,0x87,0xd1,0x66,0x70,0x7f, +0x54,0xaf,0x85,0xe2,0x1a,0x18,0xbc,0x5c,0xe1,0x0a,0x34,0xdb,0x8a,0xd7,0x4e,0xe7, +0x93,0x8e,0x85,0x5a,0x8d,0x46,0x11,0xba,0x47,0x95,0xd1,0x5e,0x87,0x3f,0xc0,0x5f, +0x18,0xc2,0x7e,0x5b,0x18,0x26,0xf7,0x4b,0x84,0xfe,0xa4,0x55,0x39,0x3e,0x0a,0x78, +0xd2,0x3c,0x9f,0xec,0x46,0x61,0xfe,0xcd,0xc4,0x47,0xff,0x00,0x66,0xaf,0x89,0x79, +0x6e,0x36,0x3b,0xd2,0x97,0xdc,0xcf,0x25,0xd0,0xaa,0xbe,0xcb,0x32,0xfe,0x1d,0xf8, +0x7b,0xfe,0x12,0x8f,0x19,0xe9,0x76,0x0c,0x81,0xe1,0x69,0x44,0x92,0x83,0xd3,0xcb, +0x5f,0x99,0x87,0xe2,0x06,0x3f,0x1a,0xfb,0x1c,0x70,0x05,0x78,0xcf,0xc0,0xaf,0x87, +0x5a,0x9f,0x86,0x75,0x2d,0x47,0x51,0xd6,0x2c,0x9a,0xd2,0x7d,0x82,0x08,0x55,0xc8, +0x24,0x82,0x72,0xc7,0x82,0x7d,0x14,0x7e,0x75,0xec,0xd5,0xfa,0x37,0x0f,0x61,0x25, +0x86,0xc2,0xb9,0x54,0x56,0x94,0x9f,0xe5,0xa2,0x3d,0xdc,0x0d,0x27,0x4e,0x9d,0xda, +0xd5,0x8b,0x45,0x14,0x57,0xd4,0x9e,0x89,0xe6,0x1f,0xb4,0x3c,0x7e,0x67,0xc3,0xfc, +0xff,0x00,0x72,0xee,0x36,0xfd,0x18,0x7f,0x5a,0xf9,0x8e,0xbe,0xa7,0xf8,0xf7,0x1e, +0xff,0x00,0x86,0xb7,0xed,0xfd,0xc9,0x61,0x6f,0xfc,0x88,0x07,0xf5,0xaf,0x96,0x33, +0x5f,0x96,0x71,0x32,0xb6,0x35,0x3f,0xee,0xaf,0xcd,0x9f,0x3b,0x98,0x2f,0xde,0xdf, +0xc8,0x28,0xa2,0x8a,0xf9,0x23,0xcc,0x3d,0x5f,0xf6,0x6f,0xb9,0x31,0xf8,0xd6,0xf2, +0x1c,0xe1,0x64,0xb1,0x63,0x8f,0x52,0x1d,0x3f,0xc4,0xd7,0xd2,0x63,0xad,0x7c,0xa1, +0xf0,0x42,0xf1,0xad,0x3e,0x25,0x69,0x4a,0xa7,0x0b,0x30,0x96,0x26,0xfa,0x79,0x6c, +0x7f,0x98,0x15,0xf5,0x78,0xaf,0xd5,0x38,0x6a,0x7c,0xd8,0x2e,0x5e,0xcd,0xff,0x00, +0x99,0xf4,0x78,0x07,0x7a,0x36,0xec,0xc5,0xa2,0x8a,0x2b,0xeb,0x0f,0x48,0x2a,0x3b, +0x89,0xd2,0xda,0x09,0x25,0x91,0x82,0x47,0x1a,0x96,0x66,0x27,0x80,0x00,0xe4,0xd3, +0xcd,0x70,0xff,0x00,0x19,0xb5,0xcf,0xec,0x4f,0x87,0xba,0xa1,0x5c,0x79,0xb7,0x4a, +0x2d,0x14,0x1e,0xfb,0xf8,0x6f,0xfc,0x77,0x71,0xfc,0x2b,0x9f,0x11,0x59,0x50,0xa3, +0x3a,0xaf,0xa2,0x6c,0x89,0xcb,0x92,0x2e,0x5d,0x8f,0x96,0xb5,0xbd,0x56,0x4d,0x73, +0x59,0xbe,0xd4,0x65,0x1b,0x64,0xba,0x9d,0xe6,0x2b,0xfd,0xdd,0xc4,0x9c,0x7e,0x15, +0x4a,0x8a,0x2b,0xf0,0x99,0xc9,0xce,0x4e,0x4f,0x76,0x7c,0x73,0x77,0x77,0x61,0x40, +0x04,0x90,0x07,0x24,0xd1,0x5d,0x17,0xc3,0xcd,0x1b,0xfb,0x7f,0xc6,0xda,0x3d,0x91, +0x5d,0xc8,0xf7,0x0a,0xee,0x3d,0x51,0x7e,0x66,0xfd,0x14,0xd5,0xd1,0xa6,0xeb,0x54, +0x8d,0x35,0xbb,0x69,0x0e,0x31,0x72,0x92,0x8a,0xea,0x7d,0x59,0xe0,0x9d,0x10,0x78, +0x77,0xc2,0x7a,0x56,0x9e,0x17,0x6b,0x43,0x6e,0x81,0xc7,0xfb,0x64,0x65,0xbf,0x52, +0x6b,0x76,0x90,0x74,0x18,0xe9,0x4b,0x5f,0xbb,0xd3,0x82,0xa7,0x05,0x05,0xb2,0x56, +0x3e,0xc6,0x2b,0x95,0x24,0x82,0x8a,0x28,0xad,0x0a,0x0a,0xc0,0xf1,0xcf,0x86,0x93, +0xc5,0xde,0x16,0xd4,0x34,0xb6,0x21,0x5a,0x78,0xff,0x00,0x76,0xc7,0xa2,0xc8,0x0e, +0x54,0x9f,0x6c,0x81,0x5b,0xf4,0x86,0xb3,0xa9,0x08,0xd5,0x83,0x84,0xb6,0x7a,0x0a, +0x49,0x49,0x38,0xbe,0xa7,0xc3,0x57,0x56,0xb2,0xd9,0x5c,0xcb,0x6f,0x3c,0x6d,0x14, +0xd1,0x39,0x8d,0xd1,0x86,0x0a,0xb0,0x38,0x20,0xd4,0x55,0xf4,0x07,0xc6,0xef,0x85, +0x32,0xea,0x8c,0xfe,0x20,0xd1,0xe1,0x32,0x5d,0x01,0x9b,0xab,0x64,0x1c,0xc8,0x07, +0xf1,0xa8,0xee,0x40,0xea,0x3b,0x8f,0x7e,0xbf,0x3f,0xd7,0xe2,0xd9,0x86,0x06,0xa6, +0x02,0xb3,0xa7,0x3d,0xba,0x3e,0xeb,0xfa,0xdc,0xf9,0x3a,0xf4,0x65,0x46,0x7c,0xac, +0x28,0xa2,0x8a,0xf3,0x0e,0x73,0xb3,0xf8,0x73,0xf1,0x3a,0xfb,0xe1,0xf5,0xe3,0x04, +0x43,0x77,0xa7,0x4a,0x73,0x35,0xab,0x1c,0x73,0xfd,0xe5,0x3d,0x8f,0xf3,0xfc,0xb1, +0xf4,0x3f,0x86,0xbe,0x2b,0xf8,0x67,0xc4,0xd1,0x21,0x87,0x52,0x8a,0xd6,0x72,0x39, +0xb7,0xbb,0x61,0x13,0x83,0xe9,0xc9,0xc1,0xfc,0x09,0xaf,0x91,0x68,0xaf,0xa1,0xcb, +0xf3,0xbc,0x46,0x02,0x3e,0xcd,0x7b,0xd1,0xec,0xfa,0x7a,0x33,0xba,0x8e,0x2e,0xa5, +0x15,0xcb,0xba,0x3e,0xe7,0x8e,0xe2,0x29,0x90,0x3c,0x72,0x23,0xa1,0xe8,0xca,0xc0, +0x83,0x54,0xf5,0x0d,0x7f,0x4c,0xd2,0x50,0xb5,0xee,0xa1,0x6b,0x68,0xa3,0xbc,0xd3, +0x2a,0xff,0x00,0x33,0x5f,0x13,0x2c,0x8e,0x83,0x0a,0xcc,0xa3,0xd8,0xe2,0x9a,0x79, +0x39,0x27,0x27,0xde,0xbd,0xd7,0xc5,0x52,0xb7,0xbb,0x47,0x5f,0x5f,0xf8,0x07,0x67, +0xf6,0x93,0xe9,0x1f,0xc7,0xfe,0x01,0xf4,0x6f,0x8c,0x7f,0x68,0x5d,0x2b,0x4c,0x89, +0xe1,0xd0,0xe3,0x3a,0xa5,0xd9,0xc8,0x13,0x30,0x29,0x0a,0x7e,0x7c,0xb7,0xe1,0xc1, +0xf5,0xaf,0x03,0xd7,0xbc,0x41,0x7f,0xe2,0x6d,0x4a,0x5b,0xfd,0x46,0xe1,0xae,0x6e, +0x64,0xea,0xcd,0xd0,0x0e,0xc0,0x0e,0xc0,0x7a,0x0a,0xce,0xa2,0xbe,0x5f,0x1d,0x9a, +0x62,0x71,0xef,0xf7,0xaf,0x4e,0xcb,0x63,0xce,0xad,0x88,0xa9,0x5b,0xe2,0xd8,0x28, +0xa2,0x8a,0xf2,0x4e,0x60,0xad,0x8f,0x09,0xf8,0x5e,0xf7,0xc6,0x1a,0xe5,0xbe,0x9b, +0x62,0x84,0xc9,0x21,0xcb,0xc8,0x47,0xcb,0x1a,0x7f,0x13,0x1f,0x61,0xfa,0x9c,0x0e, +0xf4,0x78,0x5f,0xc2,0x9a,0x97,0x8c,0x35,0x44,0xb1,0xd3,0x60,0x32,0xc8,0x7e,0xfb, +0x9c,0x84,0x89,0x7f,0xbc,0xc7,0xb0,0xfd,0x7d,0x33,0x5f,0x54,0x7c,0x3e,0xf8,0x7f, +0x63,0xe0,0x2d,0x24,0x41,0x6e,0x04,0xd7,0x72,0x00,0x6e,0x2e,0x98,0x61,0xa4,0x3f, +0xd0,0x0e,0xc2,0xbe,0x8b,0x29,0xca,0x67,0x8f,0xa8,0xa7,0x35,0x6a,0x6b,0x77,0xdf, +0xc9,0x1d,0xb8,0x6c,0x34,0xab,0xca,0xef,0xe1,0x35,0xbc,0x35,0xe1,0xeb,0x5f,0x0b, +0x68,0xb6,0xba,0x65,0x92,0x95,0x82,0x04,0xda,0x09,0xea,0xc7,0xbb,0x1f,0x72,0x72, +0x7f,0x1a,0xd4,0x14,0x52,0xd7,0xeb,0x70,0x84,0x69,0xc5,0x46,0x2a,0xc9,0x1f,0x4e, +0x92,0x4a,0xc8,0xc7,0xf1,0x4f,0x8a,0x6c,0x7c,0x21,0xa5,0x9d,0x43,0x51,0x76,0x4b, +0x60,0xe9,0x19,0x28,0xbb,0x8e,0x58,0xe3,0xa7,0xb7,0x5e,0x39,0xc0,0xa9,0x74,0x3f, +0x12,0x69,0x9e,0x23,0xb5,0x17,0x1a,0x6d,0xf4,0x37,0x91,0x11,0x92,0x62,0x6c,0x95, +0xfa,0x8e,0xa0,0xfb,0x1a,0xf1,0xdf,0xda,0x5f,0x5d,0xf9,0x74,0x8d,0x1d,0x1b,0xae, +0xeb,0xa9,0x00,0x3f,0xf0,0x15,0xff,0x00,0xd9,0xab,0xc4,0x2c,0xaf,0xee,0x74,0xeb, +0x85,0x9e,0xd2,0xe2,0x5b,0x69,0xd7,0xee,0xc9,0x0b,0x94,0x61,0xf8,0x8a,0xf8,0xec, +0x77,0x10,0x3c,0x16,0x32,0x54,0x79,0x79,0xa2,0xad,0xeb,0x73,0xcb,0xad,0x8d,0xf6, +0x55,0x5c,0x6d,0x74,0x7d,0xc7,0x9a,0x5a,0xf9,0x63,0x44,0xf8,0xf1,0xe2,0xbd,0x1c, +0x2a,0x4d,0x71,0x16,0xa7,0x10,0xfe,0x1b,0xa8,0xf2,0xd8,0xff,0x00,0x79,0x70,0x7f, +0x3c,0xd7,0x6f,0xa6,0x7e,0xd3,0x36,0xcc,0x48,0xd4,0x34,0x39,0xa2,0x03,0xf8,0xad, +0xa6,0x0f,0x93,0xf4,0x60,0xbf,0xce,0xbb,0xe8,0xf1,0x0e,0x06,0xaa,0xf7,0xa4,0xe2, +0xfc,0xd7,0xf9,0x5c,0xda,0x18,0xea,0x32,0xdd,0xd8,0xf6,0xfc,0xd1,0x9a,0xf3,0x1b, +0x0f,0xda,0x1f,0xc2,0xb7,0x6a,0x0c,0xdf,0x6d,0xb1,0x3e,0x93,0x41,0x9f,0xfd,0x00, +0xb5,0x5f,0x5f,0x8e,0xbe,0x0b,0x23,0xfe,0x42,0xce,0x3e,0xb6,0xb2,0xff,0x00,0xf1, +0x35,0xe9,0x47,0x33,0xc1,0x4b,0x6a,0xb1,0xfb,0xcd,0xd6,0x22,0x93,0xda,0x48,0xef, +0xe9,0x1d,0x82,0xa1,0x24,0x80,0x31,0xce,0x6b,0xcd,0xaf,0xff,0x00,0x68,0x1f,0x09, +0x5a,0xc2,0xcd,0x0c,0xd7,0x37,0xcc,0x3f,0x82,0x1b,0x76,0x52,0x7f,0xef,0xbd,0xa3, +0xf5,0xaf,0x35,0xf1,0xe7,0xc7,0xab,0xef,0x12,0x5a,0x4d,0xa7,0xe9,0x36,0xe7,0x4c, +0xb2,0x94,0x15,0x92,0x56,0x6c,0xcc,0xeb,0xe9,0xc7,0x0b,0xef,0x8c,0xfd,0x6b,0x93, +0x13,0x9d,0xe0,0xa8,0x41,0xb5,0x35,0x27,0xd9,0x6a,0x67,0x53,0x17,0x4a,0x0a,0xf7, +0xb9,0xe7,0xbe,0x28,0x96,0x0b,0x8f,0x12,0xea,0xd2,0xda,0xe3,0xec,0xcf,0x77,0x2b, +0x45,0xb7,0xa6,0xd2,0xe4,0x8c,0x7e,0x15,0x97,0x45,0x15,0xf9,0x04,0xe5,0xcf,0x37, +0x2e,0xee,0xe7,0xcb,0xb7,0x77,0x70,0xa2,0x8a,0x2a,0x04,0x75,0xff,0x00,0x08,0xf4, +0xf6,0xd4,0xbe,0x22,0xe8,0x88,0x01,0xc4,0x73,0x79,0xc4,0x8e,0xc1,0x14,0xb7,0xf4, +0xaf,0xae,0xc7,0x4a,0xf0,0x7f,0xd9,0xbf,0xc2,0xac,0x64,0xbe,0xf1,0x04,0xc9,0x85, +0xdb,0xf6,0x6b,0x72,0x47,0x5e,0xee,0x7f,0x40,0x3f,0x3a,0xf7,0x81,0xd2,0xbf,0x57, +0xe1,0xcc,0x3b,0xa3,0x82,0xe7,0x97,0xda,0x77,0xf9,0x74,0x3e,0x93,0x03,0x07,0x1a, +0x57,0x7d,0x45,0xa2,0x8a,0x2b,0xea,0x4f,0x44,0x69,0xaf,0x92,0xff,0x00,0x69,0xfb, +0xbf,0x33,0x5a,0x74,0xce,0x70,0xd5,0xf5,0xab,0x74,0xaf,0x8c,0x7f,0x68,0xdb,0xbf, +0x3b,0xc4,0xb2,0x8c,0xff,0x00,0x19,0xaf,0x99,0xcf,0xdd,0xb0,0xb6,0xee,0xd1,0xe0, +0x67,0x72,0xe5,0xc2,0x48,0xf9,0xcb,0xc7,0x32,0xec,0xd2,0x67,0x3d,0x3e,0x5a,0xfa, +0x47,0xfe,0x09,0x79,0xa6,0x88,0x7e,0x0f,0xf8,0xbb,0x50,0xc7,0xcd,0x77,0xe2,0x39, +0x57,0x38,0xec,0x90,0x42,0x07,0xea,0x4d,0x7c,0xc3,0xf1,0x1e,0x5f,0x2f,0x46,0x9c, +0xe7,0xb1,0xfe,0x55,0xf5,0xff,0x00,0xfc,0x13,0x53,0x4f,0x36,0x9f,0xb3,0x2c,0x17, +0x24,0x63,0xed,0xda,0xcd,0xf5,0xc0,0x3e,0xb8,0x93,0xcb,0xff,0x00,0xda,0x75,0x9e, +0x47,0x1b,0x53,0xb9,0xf1,0xbc,0x27,0x1b,0xe2,0xeb,0xcf,0xc9,0x1f,0x55,0x51,0x45, +0x15,0xf5,0x47,0xea,0x21,0x5f,0x13,0x7e,0xd3,0x3e,0x2f,0x3e,0x27,0xf8,0x9b,0x71, +0x68,0x8e,0x4d,0xa6,0x92,0x9f,0x64,0x41,0xdb,0x7f,0x59,0x0f,0xe7,0x81,0xff,0x00, +0x01,0xaf,0xae,0xbc,0x73,0xe2,0x68,0x7c,0x1d,0xe1,0x2d,0x57,0x59,0x9b,0x1b,0x6c, +0xe0,0x69,0x14,0x1f,0xe2,0x7c,0x61,0x57,0xf1,0x62,0x07,0xe3,0x5f,0x9f,0x28,0x2e, +0x75,0xcd,0x57,0x74,0x8c,0xd3,0x5d,0x5d,0xcc,0x59,0x98,0xf2,0x59,0xd9,0xb2,0x4f, +0xe6,0x6b,0xe4,0xb8,0x83,0x11,0xcb,0x4e,0x34,0x23,0xbb,0xd7,0xfa,0xf9,0x9f,0x1b, +0xc4,0x58,0x87,0xc9,0x0c,0x34,0x77,0x93,0xbb,0xf4,0xff,0x00,0x87,0x3e,0x96,0xfd, +0x92,0x7c,0x1f,0xe4,0xd9,0xdf,0x6b,0xf2,0xa6,0x0c,0x87,0xc9,0x88,0x91,0xdb,0xb9, +0xaf,0xa3,0xeb,0x97,0xf8,0x6f,0xe1,0xa4,0xf0,0x97,0x83,0x74,0xcd,0x39,0x54,0x2b, +0x47,0x10,0x2f,0x8e,0xec,0x7a,0xd7,0x51,0x5e,0xde,0x5d,0x87,0xfa,0xb6,0x1a,0x14, +0xfa,0xf5,0xf5,0x3e,0x8f,0x03,0x87,0x58,0x5c,0x3c,0x29,0x76,0x41,0x5f,0x0c,0x7f, +0xc1,0x5c,0xbe,0x35,0x9f,0x87,0x7f,0xb3,0xbc,0x3e,0x0f,0xb2,0x9b,0xcb,0xd5,0x3c, +0x65,0x75,0xf6,0x56,0xda,0xd8,0x65,0xb4,0x88,0xac,0x93,0x1f,0x70,0xc7,0xcb,0x42, +0x3b,0x87,0x6f,0x4a,0xfb,0x9e,0xbf,0x23,0xff,0x00,0xe0,0xb6,0x56,0x5a,0x90,0xf8, +0x89,0xf0,0xd6,0xf2,0x48,0xdc,0xe9,0x07,0x4a,0xb9,0x8a,0x17,0xc7,0xc8,0x26,0x13, +0x29,0x90,0x7d,0x76,0x98,0xff,0x00,0x2a,0xf4,0xd1,0xdc,0xcf,0x86,0xbf,0x67,0xbf, +0x04,0xe9,0xbf,0x12,0x7e,0x39,0x78,0x17,0xc3,0x3a,0xcd,0xe4,0x76,0x1a,0x56,0xa9, +0xac,0x5b,0xdb,0x5d,0x4f,0x2b,0x05,0x51,0x19,0x71,0xb8,0x64,0xf7,0x61,0xf2,0x8f, +0x72,0x2b,0xfa,0x16,0xf8,0xcd,0xf1,0x1b,0x4e,0xf8,0x1d,0xf0,0x6f,0xc5,0x1e,0x2e, +0x9e,0x38,0xe3,0xb4,0xd0,0x34,0xc9,0x27,0x86,0xd9,0x70,0x81,0xdd,0x53,0x11,0x44, +0xbd,0x86,0xe6,0xda,0xa0,0x7b,0xd7,0xf3,0x4e,0xac,0x51,0x83,0x29,0x2a,0xc0,0xe4, +0x11,0xd4,0x57,0x5f,0xaa,0xfc,0x62,0xf1,0xde,0xbb,0xe1,0x97,0xf0,0xee,0xa7,0xe3, +0x2d,0x7b,0x51,0xd0,0x5f,0x6e,0xed,0x32,0xeb,0x52,0x9a,0x5b,0x73,0xb4,0x86,0x5c, +0xc6,0xcc,0x47,0x04,0x02,0x38,0xe3,0x14,0xc8,0x4e,0xc7,0x77,0xe1,0x9f,0xda,0x7f, +0xe3,0xb6,0xb5,0xe2,0xab,0x6b,0x5d,0x23,0xe2,0x6f,0x8b,0x5b,0x55,0xd5,0x2f,0x16, +0x28,0xa1,0x4d,0x5a,0x72,0xad,0x2c,0x8f,0x85,0x01,0x4b,0x60,0x0c,0xb7,0x40,0x31, +0x5f,0xd0,0x5f,0xc3,0xcd,0x07,0x50,0xf0,0xbf,0x81,0x74,0x0d,0x27,0x55,0xd4,0xae, +0x35,0x9d,0x52,0xce,0xc6,0x18,0x6f,0x35,0x0b,0xa9,0x0c,0x92,0x5c,0xcc,0x10,0x79, +0x92,0x33,0x1e,0x4e,0x5b,0x26,0xbf,0x99,0xff,0x00,0x09,0xf8,0xaf,0x55,0xf0,0x37, +0x89,0x34,0xed,0x7f,0x43,0xbc,0x6d,0x3f,0x58,0xd3,0xa7,0x5b,0x9b,0x5b,0xa4,0x55, +0x66,0x8a,0x45,0x39,0x56,0x01,0x81,0x19,0x1e,0xe2,0xbe,0x84,0xd3,0x3f,0xe0,0xa5, +0x1f,0xb4,0x76,0x95,0xf7,0x3e,0x24,0x5c,0x4e,0x3d,0x2e,0xb4,0xfb,0x49,0x7f,0xf4, +0x28,0x8d,0x0c,0x69,0x9f,0xbf,0xd4,0x57,0xe1,0x66,0x99,0xff,0x00,0x05,0x62,0xfd, +0xa1,0xec,0x17,0x12,0xeb,0xda,0x46,0xa1,0xef,0x73,0xa4,0x42,0x3f,0xf4,0x00,0xb5, +0xbf,0x63,0xff,0x00,0x05,0x87,0xf8,0xed,0x6b,0x81,0x35,0x9f,0x84,0xaf,0x3f,0xeb, +0xae,0x99,0x2a,0x9f,0xfc,0x76,0x61,0x4a,0xc5,0x5d,0x1f,0xb6,0x94,0x57,0x86,0xfe, +0xc6,0x7f,0x16,0x3c,0x69,0xf1,0xc7,0xe0,0x3e,0x8b,0xe3,0x8f,0x1c,0x58,0xe9,0xba, +0x6e,0xa3,0xac,0x49,0x2c,0xd6,0xb6,0xfa,0x64,0x4f,0x1c,0x7f,0x66,0x0d,0xb5,0x18, +0x87,0x76,0x39,0x62,0xac,0x7a,0xe3,0x05,0x7f,0x1f,0x4a,0xf8,0xa1,0xe3,0xfd,0x3f, +0xe1,0x67,0xc3,0xbf,0x12,0x78,0xbf,0x54,0x60,0x2c,0x34,0x4b,0x09,0xaf,0xa5,0x05, +0xb1,0xbf,0x62,0x92,0x14,0x7b,0xb1,0xc2,0x8f,0x72,0x29,0x0c,0xea,0x28,0xaf,0xcb, +0xad,0x3b,0xfe,0x0b,0x77,0x64,0x42,0x8b,0xef,0x84,0xd3,0xab,0x77,0xfb,0x3e,0xb8, +0x0f,0xf3,0x80,0x57,0x61,0xa5,0x7f,0xc1,0x6a,0xfe,0x1b,0xcb,0x1e,0x75,0x2f,0x00, +0x78,0xa6,0xd2,0x4f,0xee,0xda,0xbd,0xb4,0xe3,0xf3,0x69,0x13,0xf9,0x53,0xb0,0xae, +0x8f,0xd1,0x5a,0x2b,0xe0,0x5b,0x4f,0xf8,0x2c,0xef,0xc1,0x89,0xb1,0xe7,0x78,0x6b, +0xc6,0xb6,0xe7,0xd3,0xec,0x56,0xad,0xfc,0xae,0x2b,0xab,0xd1,0xbf,0xe0,0xad,0xdf, +0xb3,0xe6,0xa6,0xa0,0xdd,0x6a,0x9a,0xee,0x90,0x7d,0x2f,0x34,0x89,0x1b,0x1f,0xf7, +0xe8,0xbd,0x01,0x74,0x7d,0x9f,0x45,0x7c,0xa7,0x69,0xff,0x00,0x05,0x44,0xfd,0x9b, +0x6e,0x80,0x27,0xe2,0x04,0x90,0x67,0xfe,0x7a,0xe8,0xb7,0xe3,0xf9,0x42,0x6b,0xa6, +0xd2,0xff,0x00,0xe0,0xa0,0xbf,0xb3,0xce,0xae,0x14,0xc3,0xf1,0x4f,0x46,0x8b,0x77, +0x41,0x74,0xb3,0x40,0x7f,0xf1,0xf4,0x14,0x87,0x73,0xe8,0x6a,0x2b,0xc9,0xf4,0xff, +0x00,0xda,0xcb,0xe0,0xb6,0xa8,0xa1,0xad,0xfe,0x2b,0xf8,0x35,0x81,0xec,0xfa,0xe5, +0xba,0x1f,0xc9,0x9c,0x56,0xfd,0x97,0xc7,0x5f,0x86,0xda,0x96,0x3e,0xc9,0xf1,0x07, +0xc2,0xd7,0x39,0xe9,0xe5,0x6b,0x56,0xcd,0x9f,0xc9,0xe8,0x03,0xb4,0x9a,0x08,0xe7, +0x52,0x92,0x22,0xc8,0x87,0xaa,0xb0,0xc8,0x3f,0x85,0x50,0x9f,0xc3,0x3a,0x3d,0xcf, +0xfa,0xed,0x2e,0xce,0x5f,0xf7,0xed,0xd0,0xff,0x00,0x4a,0x76,0x9f,0xe2,0x4d,0x27, +0x56,0x8c,0x49,0x63,0xa9,0xd9,0x5e,0xc6,0x79,0x0d,0x6f,0x70,0x92,0x03,0xf9,0x13, +0x5a,0x0a,0xe1,0x86,0x41,0x04,0x7a,0x83,0x51,0x28,0x46,0x5f,0x12,0xb8,0x9a,0x4f, +0x74,0x73,0xf3,0x7c,0x3c,0xf0,0xc5,0xc7,0x32,0x78,0x7f,0x4e,0x3f,0xf6,0xea,0x83, +0xfa,0x55,0x49,0x7e,0x15,0x78,0x46,0x51,0xce,0x81,0x66,0xbf,0xee,0x47,0xb7,0xf9, +0x57,0x59,0x9a,0x5a,0xc2,0x58,0x5a,0x12,0xde,0x0b,0xee,0x44,0x3a,0x70,0x7b,0xc5, +0x1c,0x8e,0x9d,0xf0,0xaf,0xc2,0xfa,0x4e,0xa5,0x6f,0x7f,0x65,0xa5,0xad,0xbd,0xd4, +0x0d,0xba,0x37,0x49,0x5f,0x83,0xd3,0xa6,0x71,0x5d,0x68,0xeb,0x4b,0x45,0x69,0x4e, +0x8d,0x3a,0x2a,0xd4,0xe2,0x92,0xf2,0x2a,0x31,0x8c,0x34,0x8a,0xb0,0x51,0x45,0x15, +0xb1,0x42,0x1a,0xe2,0x7e,0x28,0x7c,0x3c,0x9b,0xe2,0x1d,0x85,0x9d,0xaa,0x6a,0x22, +0xc2,0x3b,0x79,0x0c,0xa5,0x4c,0x3e,0x66,0xf6,0xc6,0x07,0xf1,0x0c,0x63,0x27,0xd7, +0xad,0x76,0xf4,0x56,0x15,0xe8,0x43,0x13,0x4d,0xd2,0xa8,0xaf,0x17,0xb9,0x13,0x82, +0xa9,0x17,0x19,0x6c,0x7c,0xf5,0x37,0xec,0xcd,0xaa,0x2e,0x7c,0x9d,0x66,0xd1,0xff, +0x00,0xdf,0x8d,0x97,0xfc,0x6a,0x93,0xfe,0xcd,0xbe,0x23,0x19,0xd9,0x7d,0xa6,0xb7, +0xd6,0x49,0x07,0xfe,0xc9,0x5f,0x49,0x51,0x5e,0x0b,0xe1,0xdc,0xbd,0xfd,0x97,0xf7, +0xb3,0x8d,0xe0,0x68,0xbe,0x9f,0x89,0xf3,0x1c,0xff,0x00,0xb3,0xbf,0x8a,0xa2,0x52, +0x55,0xf4,0xf9,0x88,0xfe,0x14,0x9c,0x8f,0xe6,0xa2,0xbb,0x0f,0x83,0x7f,0x0a,0xb5, +0x8f,0x0a,0x78,0x9a,0x7d,0x4b,0x57,0x82,0x38,0x55,0x20,0x31,0xc3,0xb6,0x45,0x7d, +0xcc,0xc4,0x64,0xf0,0x78,0xc0,0x18,0xfc,0x6b,0xdb,0x28,0xaa,0xa1,0x90,0xe1,0x30, +0xd5,0x63,0x5a,0x17,0xbc,0x7c,0xc2,0x18,0x2a,0x54,0xe4,0xa4,0xaf,0xa0,0x51,0x45, +0x15,0xf4,0x67,0x78,0x51,0x45,0x14,0x00,0x51,0x45,0x14,0x00,0x87,0x9a,0xf2,0xef, +0x88,0x7f,0x03,0xac,0x3c,0x55,0x24,0x97,0xda,0x63,0xa6,0x9b,0xa9,0xb6,0x59,0xb8, +0xfd,0xd4,0xc7,0xd5,0x80,0xe8,0x7d,0xc7,0xe4,0x6b,0xd4,0xa8,0xae,0x4c,0x4e,0x16, +0x8e,0x2e,0x1e,0xce,0xb4,0x6e,0x8c,0xea,0x53,0x8d,0x55,0xcb,0x35,0x73,0xe3,0x1f, +0x13,0x78,0x1f,0x5b,0xf0,0x84,0xc5,0x35,0x4b,0x09,0x20,0x8f,0x38,0x13,0xaf,0xcd, +0x13,0x7d,0x18,0x71,0xf8,0x75,0xf6,0xac,0x2a,0xfb,0x9e,0x68,0x52,0x78,0xca,0x48, +0xaa,0xe8,0x78,0x2a,0xc3,0x20,0xd7,0x15,0xae,0x7c,0x18,0xf0,0x9e,0xb8,0x59,0xdf, +0x4d,0x5b,0x49,0x4f,0xfc,0xb4,0xb3,0x6f,0x2b,0xf4,0x1f,0x2f,0xe9,0x5f,0x0f,0x8a, +0xe1,0x79,0x5e,0xf8,0x69,0xfc,0x9f,0xf9,0xa3,0xc7,0xa9,0x97,0x3d,0xe9,0xbf,0xbc, +0xf9,0x36,0x8a,0xf7,0xed,0x43,0xf6,0x65,0xb2,0x91,0x89,0xb0,0xd6,0xe7,0x85,0x7b, +0x2d,0xc4,0x2b,0x27,0xea,0x0a,0xd6,0x0d,0xcf,0xec,0xd5,0xad,0x23,0x91,0x06,0xa9, +0x63,0x2a,0xf6,0x32,0x07,0x43,0xfa,0x03,0x5e,0x0c,0xf2,0x2c,0xc2,0x0f,0xf8,0x77, +0xf4,0x68,0xe3,0x78,0x3a,0xeb,0xec,0x9e,0x3f,0x45,0x7a,0xb1,0xfd,0x9b,0xfc,0x4b, +0xda,0xf7,0x4b,0x3f,0xf6,0xd6,0x4f,0xfe,0x22,0x9e,0x9f,0xb3,0x6f,0x88,0xc9,0xf9, +0xef,0xb4,0xd5,0x1e,0xd2,0x48,0x7f,0xf6,0x4a,0xc1,0x64,0xf8,0xf7,0xff,0x00,0x2e, +0x99,0x1f,0x55,0xad,0xfc,0xac,0xf2,0x6a,0x2b,0xdb,0x74,0xff,0x00,0xd9,0x9a,0xe9, +0xb9,0xbd,0xd7,0x22,0x8f,0xd5,0x60,0xb7,0x2f,0xfa,0x92,0x3f,0x95,0x75,0x9a,0x3f, +0xec,0xf3,0xe1,0x9b,0x0c,0x35,0xdb,0x5d,0x6a,0x4c,0x3b,0x4b,0x26,0xc4,0xfc,0x97, +0x07,0xf5,0xae,0xda,0x5c,0x3d,0x8f,0xa8,0xf5,0x8a,0x8f,0xab,0xff,0x00,0x2b,0x9a, +0xc7,0x03,0x5a,0x5b,0xab,0x1f,0x36,0x59,0xd9,0x5c,0x6a,0x17,0x09,0x05,0xac,0x12, +0xdc,0xcc,0xe7,0x0b,0x1c,0x28,0x59,0x8f,0xd0,0x0a,0xf5,0x5f,0x05,0xfe,0xcf,0x9a, +0x9e,0xaa,0xd1,0xdc,0xeb,0xb2,0x7f,0x66,0x5a,0x13,0x9f,0x21,0x08,0x69,0xd8,0x7e, +0xa1,0x7f,0x1c,0x9f,0x6a,0xf7,0xdd,0x1f,0xc3,0xba,0x6f,0x87,0xe1,0x31,0x69,0xd6, +0x36,0xf6,0x51,0x9e,0xa2,0x18,0xc2,0xe7,0xeb,0xeb,0x5a,0x75,0xf4,0xd8,0x3e,0x19, +0xa3,0x49,0xa9,0xe2,0x25,0xcc,0xfb,0x6c,0xbf,0xcd,0x9e,0x85,0x2c,0xbe,0x31,0xd6, +0xa3,0xb9,0x93,0xe1,0xdf,0x0c,0xe9,0xbe,0x15,0xd3,0xd6,0xcf,0x4c,0xb5,0x4b,0x58, +0x47,0x5d,0xbf,0x79,0xcf,0xab,0x1e,0xa4,0xfd,0x6b,0x54,0x74,0xa5,0xa2,0xbe,0xca, +0x10,0x8d,0x38,0xa8,0xc1,0x59,0x23,0xd5,0x49,0x45,0x59,0x05,0x35,0xba,0x73,0x4e, +0xa8,0x2f,0x56,0x66,0xb5,0x98,0x40,0x50,0x4f,0xb0,0xf9,0x65,0xfe,0xee,0xec,0x71, +0x9f,0x6c,0xd5,0x3d,0x15,0xc6,0x7c,0x99,0xf1,0x6f,0x5d,0xfe,0xdf,0xf1,0xfe,0xab, +0x32,0xb6,0xe8,0xa1,0x93,0xec,0xd1,0xf3,0x9e,0x13,0x83,0x8f,0xab,0x6e,0x3f,0x8d, +0x71,0xd5,0xdd,0x6b,0xff,0x00,0x06,0x7c,0x5b,0xa3,0xb4,0x92,0x35,0x81,0xd4,0x50, +0x1c,0x99,0xac,0xdb,0xcc,0x2d,0xef,0xb7,0xef,0x7e,0x95,0xc5,0xde,0xd9,0x5c,0x69, +0xb3,0x18,0x6e,0xed,0xe5,0xb5,0x98,0x75,0x8e,0x64,0x28,0xdf,0x91,0xe6,0xbf,0x11, +0xc6,0xd2,0xc4,0x2a,0xd3,0xa9,0x5e,0x0d,0x36,0xdb,0xd5,0x1f,0x23,0x5a,0x33,0xe7, +0x72,0x92,0xdc,0x86,0x8a,0x28,0xaf,0x38,0xc0,0x28,0xa2,0x8a,0x00,0x28,0xa2,0x8a, +0x00,0x28,0xa2,0xae,0xe9,0x5a,0x26,0xa1,0xae,0xcf,0xe4,0xe9,0xd6,0x53,0xde,0xcb, +0xdd,0x60,0x42,0xd8,0xf7,0x38,0xe9,0xf8,0xd5,0x46,0x32,0x9b,0xe5,0x8a,0xbb,0x1a, +0x4d,0xe8,0x8a,0x55,0xd4,0x78,0x03,0xc0,0x17,0xfe,0x3d,0xd5,0xd6,0xde,0xdd,0x5a, +0x2b,0x38,0xc8,0x37,0x17,0x44,0x7c,0xb1,0xaf,0xa0,0xf5,0x63,0xd8,0x7f,0x4a,0xef, +0xbc,0x1b,0xfb,0x3b,0xde,0xdd,0xba,0x5c,0x78,0x86,0x71,0x67,0x00,0xe4,0xda,0x40, +0xc1,0xa4,0x6f,0x62,0xc3,0x81,0xf8,0x67,0xf0,0xaf,0x76,0xd1,0x74,0x5b,0x1f,0x0f, +0xd8,0x47,0x65,0xa7,0xdb,0x25,0xad,0xb4,0x63,0xe5,0x44,0x1f,0xa9,0xf5,0x3e,0xe6, +0xbe,0xc3,0x2c,0xe1,0xfa,0xb5,0xa4,0xaa,0x62,0x97,0x2c,0x7b,0x75,0x7f,0xe4,0x7a, +0x98,0x7c,0x14,0xa4,0xd4,0xaa,0x68,0x83,0x45,0xd1,0xad,0x74,0x0d,0x32,0xdb,0x4f, +0xb2,0x8c,0x45,0x6d,0x02,0x04,0x45,0xf6,0xf5,0x3e,0xa4,0xfa,0xd5,0xe1,0x4b,0x45, +0x7e,0x99,0x18,0xa8,0x25,0x18,0xec,0x8f,0x7d,0x24,0x95,0x90,0x51,0x45,0x15,0x43, +0x1b,0x21,0xdb,0x1b,0x1f,0x40,0x4d,0x7c,0x35,0xf1,0xd6,0xeb,0xcf,0xf1,0x4c,0xbc, +0xe7,0xe6,0x26,0xbe,0xe0,0xbe,0x7f,0x2e,0xce,0x76,0x3d,0x90,0x9f,0xd2,0xbe,0x0b, +0xf8,0xbb,0x38,0x9f,0xc5,0x13,0xfd,0x4f,0xf3,0xaf,0x91,0xe2,0x19,0x5a,0x9d,0x38, +0xf7,0x67,0xcb,0x71,0x0c,0xad,0x86,0xb1,0xe0,0x5f,0x15,0xe7,0xf2,0xb4,0x59,0xb9, +0xec,0x7f,0x95,0x7d,0xeb,0xfb,0x03,0x69,0xbf,0xd9,0xdf,0xb2,0x7f,0x81,0x7d,0x6e, +0x23,0xb8,0xb9,0x38,0xff,0x00,0x6e,0xe2,0x53,0x5f,0x9f,0x7f,0x19,0x26,0x11,0xe8, +0x92,0xf3,0x8f,0x94,0xff,0x00,0x2a,0xfd,0x29,0xfd,0x90,0xec,0x06,0x9b,0xfb,0x31, +0x7c,0x33,0x84,0x2e,0xdc,0xe8,0x76,0xd2,0x90,0x7d,0x5d,0x77,0x9f,0xd5,0xab,0xb3, +0x26,0x56,0xa2,0x78,0x1c,0x1f,0x1b,0xfb,0x79,0xf9,0xa3,0xd7,0xa8,0xa2,0x8a,0xfa, +0x23,0xf4,0x83,0xe7,0x5f,0xda,0xf7,0xc6,0x0d,0x69,0xa2,0xe9,0x5e,0x1c,0x81,0xf0, +0x6f,0x64,0x37,0x37,0x00,0x7f,0x71,0x3e,0xe8,0x3f,0x56,0x39,0xff,0x00,0x80,0xd7, +0x94,0x7e,0xcf,0x3e,0x12,0xff,0x00,0x84,0xa3,0xe2,0x15,0xa3,0x3a,0x6e,0xb7,0xb3, +0xfd,0xfb,0xfa,0x71,0xd2,0xb2,0x7e,0x36,0xf8,0xb1,0xbc,0x65,0xf1,0x33,0x5a,0xbb, +0x0f,0xbe,0xda,0xde,0x53,0x67,0x6f,0xce,0x40,0x48,0xf2,0x38,0xfa,0xb6,0xe3,0xf8, +0xd7,0xd0,0x7f,0xb2,0xb7,0x84,0x46,0x93,0xe1,0x29,0xf5,0x79,0x53,0x13,0xde,0xbe, +0x14,0x91,0xfc,0x03,0xff,0x00,0xaf,0x5f,0x01,0xff,0x00,0x23,0x1c,0xd3,0xfb,0xa9, +0xfe,0x0b,0xfc,0xd9,0xf9,0xfd,0x2f,0xf8,0x52,0xcd,0x5c,0xf7,0x8c,0x7f,0x25,0xff, +0x00,0x04,0xf7,0x30,0x30,0x00,0xe9,0x4b,0x48,0x29,0x6b,0xef,0xcf,0xd0,0x02,0xbc, +0xff,0x00,0xe3,0x67,0xc0,0x9f,0x05,0xfe,0xd0,0x9e,0x0c,0x97,0xc3,0x1e,0x37,0xd1, +0xe3,0xd5,0xb4,0xd2,0xe2,0x58,0x9b,0x71,0x49,0xad,0xe5,0x00,0x81,0x24,0x4e,0x39, +0x46,0xc1,0x23,0x8e,0xa0,0x90,0x72,0x09,0x15,0xe8,0x14,0x50,0x07,0xe6,0x47,0x8d, +0x3f,0xe0,0x89,0xda,0x1d,0xc5,0xc3,0x4b,0xe1,0x5f,0x89,0xb7,0xfa,0x7c,0x1c,0x9f, +0x23,0x57,0xd3,0x92,0xe5,0x87,0xfd,0xb4,0x47,0x8f,0xff,0x00,0x41,0xaf,0xcb,0x8f, +0x1b,0x68,0x56,0x5e,0x17,0xf1,0x86,0xb5,0xa3,0xe9,0xda,0xb4,0x7a,0xf5,0x8e,0x9f, +0x79,0x2d,0xac,0x3a,0x9c,0x31,0x98,0xe3,0xba,0x54,0x72,0xa2,0x55,0x52,0x49,0x0a, +0xd8,0xc8,0xe7,0xa1,0xaf,0xe9,0x9b,0xc6,0x1a,0x1d,0xc7,0x89,0x7c,0x2b,0xac,0x69, +0x16,0x9a,0x94,0xba,0x35,0xcd,0xfd,0x9c,0xb6,0xb1,0xea,0x10,0x20,0x69,0x2d,0x99, +0xd0,0xa8,0x91,0x01,0xe0,0xb2,0xe7,0x23,0x3c,0x64,0x0a,0xfc,0xdd,0xd4,0x3f,0xe0, +0x89,0x1a,0x41,0x95,0x5a,0xc7,0xe2,0x9d,0xea,0xc6,0x18,0x12,0x97,0x3a,0x42,0x31, +0x23,0xb8,0xca,0xca,0x3f,0x95,0x3b,0x92,0xd1,0xf2,0x97,0xc2,0x7f,0xf8,0x26,0x5f, +0xc6,0x3f,0x8c,0xbf,0x0d,0x34,0x4f,0x1b,0xe8,0x03,0x41,0x87,0x4b,0xd5,0xe2,0x69, +0xad,0xed,0xf5,0x0b,0xd7,0x86,0xe3,0x60,0x76,0x50,0xc5,0x7c,0xb2,0x30,0xdb,0x77, +0x0e,0x79,0x04,0x1a,0xd3,0xbc,0xff,0x00,0x82,0x4e,0x7e,0xd1,0x16,0xa4,0x88,0xf4, +0x0d,0x1e,0xe8,0x0e,0xf0,0xeb,0x30,0x8c,0xff,0x00,0xdf,0x44,0x57,0xed,0xff,0x00, +0x85,0x7c,0x35,0x63,0xe0,0xdf,0x0c,0xe9,0x3a,0x06,0x99,0x17,0x91,0xa6,0xe9,0x76, +0x91,0x59,0x5a,0xc5,0x9c,0xec,0x8a,0x34,0x08,0x83,0xf2,0x51,0x5a,0xb4,0x5c,0x2c, +0x8f,0xc0,0x4d,0x47,0xfe,0x09,0xa7,0xfb,0x47,0x69,0xcc,0xc0,0xfc,0x38,0x9a,0xe5, +0x57,0xf8,0xad,0xb5,0x1b,0x47,0x07,0xe9,0xfb,0xdc,0x9a,0xc6,0xd1,0xbf,0x60,0x7f, +0x8e,0xf7,0xde,0x25,0xd3,0x34,0xbb,0xcf,0x86,0x7e,0x20,0xb0,0x86,0xea,0xee,0x2b, +0x79,0x6f,0x5e,0xd7,0x74,0x50,0x2b,0x38,0x53,0x23,0x32,0x92,0x02,0xa8,0x39,0x27, +0x3d,0x05,0x7f,0x42,0x78,0xa0,0x80,0x7b,0x51,0x70,0xe5,0x46,0x2f,0x82,0xfc,0x29, +0x63,0xe0,0x5f,0x07,0x68,0x9e,0x1c,0xd3,0x23,0x58,0xb4,0xfd,0x26,0xce,0x1b,0x28, +0x11,0x46,0x00,0x48,0xd0,0x28,0xfd,0x05,0x7c,0x4f,0xff,0x00,0x05,0x7d,0xf8,0xb1, +0x73,0xe1,0x4f,0x80,0x9a,0x6f,0x82,0x34,0xd5,0xb8,0x6b,0xef,0x15,0xde,0xff,0x00, +0xa4,0x98,0x63,0x2c,0xa2,0xce,0xdf,0x6b,0xb8,0x62,0x3a,0x66,0x46,0x84,0x0f,0x50, +0x1b,0xd2,0xbe,0xf3,0xa6,0xb2,0x2b,0x75,0x00,0xfd,0x45,0x22,0x8f,0xe5,0xad,0xa3, +0x64,0x24,0x32,0xb2,0xe3,0xfb,0xc3,0x14,0xd1,0xcf,0x4e,0x6b,0xfa,0x8b,0xbc,0xd1, +0x74,0xfd,0x42,0x33,0x1d,0xd5,0x85,0xb5,0xca,0x1e,0xab,0x34,0x2a,0xe0,0xfe,0x04, +0x57,0x2d,0xab,0xfc,0x11,0xf8,0x77,0xaf,0xa9,0x5d,0x4b,0xc0,0x7e,0x19,0xbf,0x53, +0xd4,0x5c,0xe9,0x16,0xf2,0x67,0xf3,0x4a,0x77,0x23,0x94,0xfe,0x67,0x71,0x9a,0x2b, +0xfa,0x3a,0xba,0xfd,0x90,0x3e,0x07,0x5e,0xe7,0xcd,0xf8,0x43,0xe0,0x9c,0x9e,0xa5, +0x34,0x1b,0x64,0x3f,0x98,0x41,0x5c,0xbe,0xad,0xff,0x00,0x04,0xfb,0xfd,0x9e,0xb5, +0x9c,0xf9,0xdf,0x0b,0x74,0x58,0x73,0xff,0x00,0x3e,0x7e,0x6d,0xbf,0xfe,0x8b,0x75, +0xc5,0x3b,0x87,0x29,0xfc,0xf6,0xd1,0x5f,0xbd,0x17,0x5f,0xf0,0x4b,0x8f,0xd9,0xb2, +0xe9,0xcb,0x0f,0x01,0xcd,0x01,0x3f,0xf3,0xcb,0x5b,0xbe,0x03,0xf2,0xf3,0xab,0x9f, +0xd5,0x3f,0xe0,0x92,0x1f,0xb3,0xed,0xfe,0xef,0xb3,0xe9,0xba,0xf6,0x9b,0x9e,0x9f, +0x66,0xd5,0xdd,0xb1,0xff,0x00,0x7f,0x03,0x51,0x70,0xe5,0x3f,0x0d,0xe8,0xaf,0xd9, +0xab,0xef,0xf8,0x23,0x0f,0xc1,0xdb,0x87,0x63,0x6d,0xe2,0x8f,0x19,0x5a,0x03,0xd1, +0x7e,0xd5,0x6c,0xe0,0x7e,0x70,0x56,0x05,0xff,0x00,0xfc,0x11,0x43,0xc0,0x32,0x03, +0xf6,0x2f,0x88,0x9e,0x24,0xb7,0x3d,0xbe,0xd1,0x6f,0x6f,0x2e,0x3f,0x25,0x5a,0x2e, +0x1c,0xac,0xfc,0x89,0x8a,0xee,0x68,0x71,0xe5,0xcd,0x24,0x78,0xfe,0xeb,0x11,0x5a, +0xf6,0x3e,0x3b,0xf1,0x2e,0x98,0x41,0xb3,0xf1,0x0e,0xab,0x69,0x8e,0x9e,0x45,0xec, +0xa9,0xfc,0x9a,0xbf,0x4c,0x35,0x5f,0xf8,0x22,0x28,0x24,0xff,0x00,0x66,0x7c,0x59, +0xd8,0x3b,0x0b,0xbd,0x13,0x71,0xff,0x00,0xc7,0x67,0x15,0xcd,0xde,0xff,0x00,0xc1, +0x12,0xbc,0x5d,0x19,0x3f,0x64,0xf8,0x9d,0xa2,0x4e,0x3b,0x79,0xda,0x6c,0xd1,0xff, +0x00,0x27,0x6a,0x05,0x66,0x7c,0x2f,0xa6,0xfe,0xd0,0x9f,0x14,0x34,0x62,0x0d,0x8f, +0xc4,0x5f,0x15,0x5a,0xe3,0xa7,0x95,0xac,0xdc,0x2f,0xfe,0xcf,0x5d,0x56,0x9f,0xfb, +0x6a,0xfc,0x77,0xd2,0xc0,0x16,0xff,0x00,0x15,0xfc,0x53,0x81,0xda,0x5d,0x45,0xe4, +0xff,0x00,0xd0,0xb3,0x5f,0x4c,0x6a,0xdf,0xf0,0x46,0x1f,0x8b,0x96,0xc7,0xfe,0x25, +0xfe,0x2c,0xf0,0x85,0xf0,0xff,0x00,0xa6,0xb3,0x5c,0xc2,0x7f,0xf4,0x4b,0x57,0x29, +0x7d,0xff,0x00,0x04,0x87,0xf8,0xfd,0x68,0x48,0x8a,0x1f,0x0d,0x5e,0x81,0xde,0x1d, +0x57,0x19,0xff,0x00,0xbe,0xd1,0x68,0x1d,0x99,0xe6,0x56,0x1f,0xf0,0x50,0xcf,0xda, +0x23,0x4f,0x60,0x53,0xe2,0x86,0xab,0x28,0x1d,0xae,0x22,0x82,0x5f,0xfd,0x0a,0x33, +0x5d,0x4e,0x9b,0xff,0x00,0x05,0x4c,0xfd,0xa3,0x34,0xec,0x67,0xc6,0x36,0x97,0x80, +0x76,0xb9,0xd2,0x2d,0x9b,0x3f,0x92,0x03,0x4b,0xa9,0xff,0x00,0xc1,0x2c,0x7f,0x68, +0xdd,0x3c,0x9d,0x9e,0x0d,0xb4,0xbd,0x03,0xbd,0xb6,0xb1,0x68,0x73,0xf8,0x34,0x8a, +0x6b,0x8d,0xbf,0xff,0x00,0x82,0x7f,0xfe,0xd0,0xba,0x73,0xb2,0xc9,0xf0,0xb3,0x5a, +0x93,0x6f,0x7b,0x7f,0x2a,0x50,0x7e,0x9b,0x5c,0xe6,0x8d,0x03,0x53,0xd5,0xac,0x7f, +0xe0,0xaf,0x7f,0x1f,0x6d,0x14,0x09,0x64,0xf0,0xcd,0xe7,0xfb,0x53,0x69,0x44,0x1f, +0xfc,0x72,0x45,0xae,0x9f,0x4b,0xff,0x00,0x82,0xce,0xfc,0x5e,0xb4,0x50,0x2f,0x7c, +0x2f,0xe1,0x1b,0xff,0x00,0x53,0xf6,0x7b,0x88,0xcf,0xe9,0x35,0x7c,0xc5,0x7b,0xfb, +0x1b,0xfc,0x73,0xd3,0xf7,0x79,0xff,0x00,0x09,0xbc,0x5c,0x02,0x8c,0x92,0x9a,0x4c, +0xce,0x07,0xe2,0xaa,0x6b,0x90,0xd4,0x7e,0x0a,0xfc,0x42,0xd1,0xd9,0x96,0xfb,0xc0, +0x9e,0x25,0xb4,0x2b,0xf7,0xbc,0xed,0x22,0xe1,0x71,0xf9,0xa5,0x1a,0x05,0xd9,0xf7, +0xa6,0x9f,0xff,0x00,0x05,0xb3,0xf1,0x7c,0x48,0x3e,0xdd,0xf0,0xcb,0x44,0xb8,0x7f, +0x5b,0x7d,0x46,0x68,0x87,0xe4,0x55,0xab,0x7f,0x4f,0xff,0x00,0x82,0xdd,0xce,0x31, +0xf6,0xef,0x84,0x91,0xb7,0xa9,0xb7,0xd7,0x88,0xfd,0x0c,0x06,0xbf,0x32,0xee,0x7c, +0x31,0xac,0x59,0x92,0x27,0xd2,0xaf,0x61,0x23,0xaf,0x99,0x6c,0xeb,0x8f,0xcc,0x56, +0x73,0xa1,0x8d,0xb6,0xb0,0x2a,0xde,0x87,0x8a,0x34,0x0b,0xb3,0xf5,0xc7,0x4a,0xff, +0x00,0x82,0xd8,0xf8,0x36,0x54,0xce,0xa5,0xf0,0xd7,0x5d,0xb6,0x6e,0xe2,0xd2,0xfa, +0x19,0x87,0xfe,0x3c,0x12,0xba,0x0b,0x2f,0xf8,0x2d,0x17,0xc2,0x59,0x71,0xf6,0x9f, +0x06,0xf8,0xc6,0xdc,0xfa,0xa4,0x36,0xae,0x3f,0xf4,0x78,0xaf,0xc6,0xdc,0xe7,0xbd, +0x18,0x34,0x58,0x2e,0xcf,0xdb,0xbd,0x37,0xfe,0x0a,0xfd,0xf0,0x16,0xf5,0x03,0x5c, +0x7f,0xc2,0x4d,0x60,0x4f,0x69,0xb4,0xb0,0xf8,0xff,0x00,0xbe,0x24,0x6a,0xe9,0xec, +0xbf,0xe0,0xaa,0x5f,0xb3,0x75,0xdc,0x41,0xe4,0xf1,0xb5,0xdd,0xa3,0x1f,0xe0,0x9b, +0x44,0xbd,0x24,0x7e,0x2b,0x11,0x1f,0xad,0x7e,0x0e,0xe2,0x8a,0x2c,0x1c,0xc7,0xf4, +0x01,0x63,0xff,0x00,0x05,0x23,0xfd,0x9c,0x6f,0xc0,0xd9,0xf1,0x32,0xce,0x2c,0xf6, +0x9e,0xc6,0xee,0x3f,0xfd,0x0a,0x21,0x5d,0x6e,0x99,0xfb,0x6a,0xfc,0x06,0xd5,0xe3, +0x0f,0x07,0xc5,0xcf,0x08,0xc6,0x0f,0x6b,0xad,0x56,0x2b,0x73,0xf9,0x48,0x54,0xd7, +0xf3,0xa5,0x9a,0x29,0x58,0x39,0x8f,0xe9,0x32,0xcf,0xf6,0x9c,0xf8,0x3f,0xa8,0x15, +0x16,0xdf,0x15,0x3c,0x17,0x39,0x6e,0x82,0x3f,0x10,0x5a,0x1c,0xff,0x00,0xe4,0x4a, +0xeb,0xb4,0xdf,0x1f,0x78,0x63,0x59,0x50,0xd6,0x1e,0x22,0xd2,0x6f,0x94,0xf2,0x0d, +0xb5,0xf4,0x52,0x03,0xf9,0x31,0xaf,0xe6,0x16,0x9c,0xb2,0x32,0x10,0x55,0x8a,0x91, +0xdc,0x1a,0x2c,0x1c,0xc7,0xf5,0x25,0x14,0xf1,0xcc,0x9b,0xe3,0x75,0x75,0xf5,0x52, +0x08,0xa7,0xe6,0xbf,0x97,0x8b,0x7f,0x10,0xea,0xb6,0x98,0xf2,0x35,0x3b,0xc8,0x71, +0xd3,0xcb,0xb8,0x75,0xc7,0xe4,0x6b,0x7b,0x4f,0xf8,0xc3,0xe3,0xcd,0x2b,0x1f,0x62, +0xf1,0xb7,0x88,0xad,0x31,0xd3,0xc9,0xd5,0x67,0x4c,0x7e,0x4f,0x45,0x87,0xcc,0x7f, +0x4d,0x39,0xa5,0xaf,0xe7,0x07,0x4e,0xfd,0xae,0x3e,0x35,0xe9,0x48,0xa9,0x69,0xf1, +0x5b,0xc5,0xf0,0xa2,0xf0,0x17,0xfb,0x66,0x72,0x3f,0x22,0xd5,0xd1,0xe9,0xff,0x00, +0xb7,0xbf,0xed,0x07,0xa6,0xe3,0xca,0xf8,0xab,0xaf,0xc9,0x8e,0xd7,0x12,0x24,0xdf, +0xfa,0x1a,0x9a,0x2c,0x1c,0xc8,0xfe,0x86,0xe8,0xaf,0xc0,0xed,0x33,0xfe,0x0a,0x75, +0xfb,0x46,0xe9,0x7d,0x3c,0x7c,0x2e,0x87,0xa5,0xd6,0x99,0x69,0x27,0xf3,0x8f,0x35, +0xd2,0xd9,0x7f,0xc1,0x5b,0x3f,0x68,0x4b,0x5c,0x79,0xba,0xae,0x85,0x79,0xff,0x00, +0x5d,0xb4,0x88,0xc6,0x7f,0xef,0x82,0xb4,0x58,0x77,0x47,0xee,0x65,0x15,0xf8,0xa9, +0xa6,0xff,0x00,0xc1,0x63,0xbe,0x37,0x5a,0x11,0xf6,0xad,0x2f,0xc2,0x77,0xc3,0xbe, +0xeb,0x09,0x90,0xff,0x00,0xe3,0xb3,0x0a,0xea,0xf4,0xff,0x00,0xf8,0x2d,0x67,0xc4, +0x28,0x71,0xf6,0xdf,0x87,0xfe,0x1b,0xb9,0xff,0x00,0xae,0x33,0xdc,0x45,0xfc,0xd9, +0xa8,0xb0,0x5d,0x1f,0xb0,0x14,0x57,0xe4,0xf5,0x8f,0xfc,0x16,0xe7,0x5b,0x56,0x1f, +0x6c,0xf8,0x51,0x60,0xeb,0xdc,0xc1,0xad,0x3a,0x9f,0xd6,0x13,0x5d,0x66,0x99,0xff, +0x00,0x05,0xb7,0xd0,0x5d,0x07,0xf6,0x8f,0xc2,0xdd,0x4a,0x27,0xef,0xf6,0x5d,0x56, +0x37,0x1f,0xf8,0xf4,0x62,0x8b,0x05,0xd1,0xfa,0x6b,0x45,0x7e,0x77,0xd8,0xff,0x00, +0xc1,0x6a,0x7e,0x18,0xc8,0x83,0xed,0x7e,0x06,0xf1,0x6c,0x12,0x1e,0xa2,0x1f,0xb2, +0xc8,0x07,0xe2,0x65,0x5f,0xe5,0x5d,0x16,0x9b,0xff,0x00,0x05,0x8e,0xf8,0x23,0x76, +0x07,0xda,0x74,0xaf,0x17,0x58,0x9e,0xfb,0xec,0x21,0x7c,0x7f,0xdf,0x33,0x1a,0x56, +0x0b,0xa3,0xee,0xea,0x2b,0xe3,0xdd,0x33,0xfe,0x0a,0xbd,0xfb,0x3a,0xdf,0x45,0xbe, +0x7f,0x12,0x6a,0xba,0x71,0xfe,0xe5,0xce,0x8d,0x72,0xc7,0xff,0x00,0x21,0xab,0x0a, +0xdd,0xb2,0xff,0x00,0x82,0x9c,0x7e,0xcd,0xd7,0xcc,0x14,0x7c,0x43,0x10,0x93,0xff, +0x00,0x3d,0xb4,0xab,0xd4,0xfe,0x70,0xd0,0x3b,0x9f,0x52,0xd1,0x5e,0x13,0xa6,0xfe, +0xdd,0x5f,0x00,0x35,0x58,0x95,0xe2,0xf8,0xb1,0xe1,0xa8,0x81,0xed,0x75,0x77,0xe4, +0x1f,0xc9,0xc0,0x35,0xbd,0x6b,0xfb,0x59,0x7c,0x14,0xbd,0x0a,0x61,0xf8,0xb5,0xe0, +0xa6,0xdd,0xd0,0x1d,0x7e,0xd4,0x13,0xf8,0x17,0xa0,0x0f,0x58,0xa2,0xb8,0xed,0x33, +0xe3,0x27,0x80,0xb5,0xa4,0x56,0xd3,0xfc,0x6d,0xe1,0xdb,0xd5,0x6e,0x86,0xdf,0x55, +0x81,0xf3,0xf9,0x3d,0x74,0xd6,0x9a,0xb5,0x8d,0xfc,0x61,0xed,0xaf,0x2d,0xee,0x10, +0xf4,0x68,0xa5,0x56,0x07,0xf1,0x06,0x80,0x2d,0xd4,0x17,0x56,0x70,0x5e,0x46,0x63, +0x9e,0x08,0xe7,0x8c,0xf5,0x59,0x14,0x30,0x3f,0x81,0xa9,0x43,0x82,0x32,0x0e,0x7e, +0x94,0xb9,0xa4,0xd2,0x6a,0xcc,0x37,0x39,0x4b,0xff,0x00,0x85,0x9e,0x14,0xd4,0x41, +0x12,0xe8,0x56,0x6a,0x4f,0x56,0x85,0x3c,0xa3,0xf9,0xae,0x2b,0x02,0xf3,0xf6,0x7d, +0xf0,0x95,0xc6,0x7c,0xb8,0x6e,0xad,0x73,0xff,0x00,0x3c,0xae,0x09,0xff,0x00,0xd0, +0xb3,0x5e,0x95,0x9a,0x2b,0x86,0xa6,0x5f,0x84,0xab,0xf1,0xd2,0x8b,0xf9,0x23,0x07, +0x42,0x9c,0xb7,0x8a,0x3c,0x7e,0x6f,0xd9,0xa7,0x44,0x63,0xfb,0xad,0x57,0x50,0x4f, +0xf7,0xbc,0xb6,0xff,0x00,0xd9,0x45,0x56,0x6f,0xd9,0x9b,0x4f,0xcf,0xcb,0xad,0x5c, +0x8f,0xac,0x4a,0x7f,0xad,0x7b,0x55,0x26,0x2b,0x8d,0xe4,0xb9,0x7b,0xff,0x00,0x97, +0x4b,0xf1,0xff,0x00,0x33,0x3f,0xaa,0x50,0xfe,0x53,0xc6,0x13,0xf6,0x66,0xd3,0x54, +0xfc,0xda,0xcd,0xd1,0xff,0x00,0x76,0x35,0x15,0x7e,0xd3,0xf6,0x70,0xf0,0xdc,0x0c, +0x0c,0xd7,0x7a,0x85,0xcf,0xb3,0x48,0x8a,0x3f,0x45,0xaf,0x58,0xc5,0x2d,0x38,0xe4, +0xd8,0x08,0xed,0x49,0x02,0xc2,0xd1,0x5f,0x64,0xe2,0x74,0xcf,0x83,0x7e,0x11,0xd2, +0x88,0x29,0xa3,0xc5,0x3b,0x7a,0xdc,0xb3,0x4b,0xfa,0x31,0x22,0xba,0xfb,0x4b,0x2b, +0x7b,0x08,0x56,0x1b,0x68,0x23,0x82,0x25,0xe0,0x24,0x48,0x14,0x0f,0xc0,0x54,0xf4, +0x57,0xa5,0x4b,0x0f,0x46,0x82,0xb5,0x28,0x25,0xe8,0x8e,0x88,0xc2,0x30,0xf8,0x55, +0x82,0x8a,0x28,0xae,0x82,0xc2,0x8a,0x28,0xa0,0x02,0x8a,0x28,0xa0,0x0c,0xef,0x10, +0xcb,0xe4,0xe8,0x97,0xaf,0xe9,0x13,0x7f,0x2a,0xf8,0x0b,0xe2,0x14,0xe6,0x7f,0x11, +0x5d,0x31,0xe7,0xe6,0x35,0xf7,0x7f,0x8e,0x66,0xf2,0x3c,0x2d,0xa8,0x36,0x71,0xfb, +0xb2,0x2b,0xe0,0x2f,0x18,0x4b,0xe6,0xeb,0x37,0x6d,0xfe,0xd1,0xaf,0x88,0xe2,0x29, +0x7b,0xf4,0xa3,0xea,0x7c,0x67,0x12,0x4a,0xd4,0xa2,0x8f,0x00,0xf8,0xed,0x75,0xe5, +0x68,0x93,0x8c,0xf4,0x42,0x7f,0x4a,0xfd,0x6a,0xf8,0x37,0xa6,0xff,0x00,0x63,0x7c, +0x24,0xf0,0x55,0x81,0x50,0x86,0xdb,0x45,0xb3,0x88,0xa8,0x18,0xc1,0x10,0xa0,0xaf, +0xc8,0x7f,0x8e,0xbf,0xe9,0x36,0x82,0xd8,0x13,0x99,0x59,0x63,0xe3,0xfd,0xa3,0x8f, +0xeb,0x5f,0xb3,0x7a,0x25,0xa8,0xb1,0xd1,0xec,0x6d,0x87,0x48,0x60,0x8e,0x31,0xf8, +0x28,0x1f,0xd2,0xbd,0xcc,0xa9,0x5a,0x82,0x38,0xf8,0x3e,0x3f,0xec,0xd5,0x27,0xde, +0x45,0xea,0x28,0xa2,0xbd,0xb3,0xef,0xcf,0xcd,0xfd,0x0b,0x4e,0x93,0xc4,0x1e,0x25, +0x8e,0xce,0x20,0x5a,0x4b,0x8b,0x92,0xbf,0x9b,0x1a,0xfd,0x0a,0xf0,0xbe,0x8b,0x17, +0x87,0xb4,0x1b,0x1d,0x3a,0x15,0xc2,0x41,0x12,0xa7,0xe3,0x8e,0x6b,0xe1,0x7f,0x80, +0x9a,0xce,0x9f,0xa2,0x7c,0x4f,0x67,0xd6,0x07,0x96,0x6c,0xae,0x65,0x88,0xa3,0x8e, +0x56,0x40,0xe4,0x73,0x9f,0xa5,0x7d,0xb5,0x6f,0xf1,0x0b,0x40,0xb8,0x50,0x57,0x51, +0x8b,0xf1,0x35,0xf2,0x19,0x34,0x29,0xd1,0x9d,0x59,0xce,0x49,0x4a,0xf6,0xf9,0x1f, +0x11,0xc3,0x2a,0x9a,0xc3,0xca,0xa4,0x9f,0xbc,0xdd,0xbe,0xe3,0xa4,0xa2,0xb1,0xe3, +0xf1,0x6e,0x91,0x2f,0xdd,0xbf,0x84,0xff,0x00,0xc0,0xaa,0xd2,0x6b,0x76,0x12,0x7d, +0xdb,0xc8,0x4f,0xfc,0x0c,0x57,0xd5,0xaa,0x90,0x7b,0x34,0x7d,0xaa,0x94,0x5f,0x52, +0xf5,0x23,0x67,0x1c,0x75,0xf7,0xa8,0x12,0xf6,0xde,0x5f,0xb9,0x3c,0x6d,0xf4,0x61, +0x52,0x89,0x50,0xf4,0x70,0x7f,0x1a,0xbb,0xa6,0x3b,0x8e,0x19,0xc0,0xc8,0xe6,0x8a, +0x40,0xd9,0x1d,0x69,0x73,0x4c,0x62,0xd1,0x49,0x45,0x00,0x2d,0x14,0x51,0x40,0x05, +0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x09,0x8a,0x5a,0x28,0xa0, +0x02,0x8a,0x28,0xa0,0x02,0x92,0x96,0x8a,0x00,0x4c,0x0f,0x4a,0x31,0x4b,0x45,0x00, +0x25,0x2d,0x14,0x50,0x01,0x45,0x14,0x50,0x03,0x1e,0x24,0x91,0x4a,0xba,0x2b,0x29, +0xea,0x08,0xc8,0xac,0x4d,0x5b,0xc0,0x5e,0x19,0xd7,0xa2,0x31,0xea,0x7e,0x1d,0xd2, +0x75,0x18,0xcf,0x54,0xba,0xb1,0x8a,0x50,0x7f,0x06,0x53,0x5b,0xd4,0x50,0x07,0x98, +0xdf,0x7e,0xcb,0xdf,0x07,0x35,0x26,0x66,0xba,0xf8,0x51,0xe0,0xa9,0xd9,0xba,0xb3, +0xf8,0x7e,0xd0,0x93,0xf8,0xf9,0x75,0x85,0xa9,0xfe,0xc5,0x1f,0x01,0xb5,0x58,0xca, +0x4d,0xf0,0x8f,0xc2,0x31,0x8f,0x5b,0x6d,0x2a,0x28,0x0f,0xe7,0x18,0x53,0x5e,0xd7, +0x45,0x00,0x7c,0xcb,0xa9,0x7f,0xc1,0x35,0xff,0x00,0x67,0x0d,0x53,0x3e,0x67,0xc3, +0x4b,0x58,0x49,0xef,0x6d,0xa8,0x5d,0xc3,0xff,0x00,0xa0,0xca,0x2b,0x9e,0xbe,0xff, +0x00,0x82,0x54,0x7e,0xce,0x37,0x6b,0x88,0xbc,0x21,0x7f,0x64,0x7f,0xbd,0x06,0xb7, +0x78,0x4f,0xfe,0x3f,0x23,0x57,0xd7,0x74,0x50,0x16,0x3e,0x1b,0xd6,0x3f,0xe0,0x8f, +0x5f,0x02,0xb5,0x01,0xfe,0x89,0x71,0xe2,0x9d,0x2c,0xff,0x00,0xd3,0xbe,0xa4,0x8f, +0xff,0x00,0xa3,0x23,0x6a,0xe5,0xae,0xbf,0xe0,0x8a,0xff,0x00,0x0b,0x1c,0x9f,0xb3, +0xf8,0xe3,0xc6,0x10,0xe7,0xa7,0x98,0xd6,0xaf,0x8f,0xca,0x11,0x5f,0xa1,0xb4,0x50, +0x2b,0x23,0xf3,0x37,0x55,0xff,0x00,0x82,0x25,0x78,0x72,0x40,0xdf,0xd9,0x9f,0x14, +0x35,0x4b,0x73,0xdb,0xed,0x7a,0x5c,0x72,0xe3,0xfe,0xf9,0x75,0xae,0x4e,0xef,0xfe, +0x08,0x8b,0xab,0xab,0x1f,0xb2,0xfc,0x59,0xb1,0x91,0x7b,0x09,0xb4,0x37,0x53,0xf8, +0xe2,0x73,0x5f,0xab,0xd4,0x50,0x16,0x47,0xe4,0x0e,0xa5,0xff,0x00,0x04,0x51,0xf8, +0x81,0x10,0x3f,0x60,0xf8,0x85,0xe1,0xbb,0xa3,0xdb,0xcf,0xb7,0x9e,0x1c,0xfe,0x41, +0xab,0x8f,0xd4,0xff,0x00,0xe0,0x8e,0x7f,0x1c,0x2d,0x1b,0x16,0xba,0x97,0x84,0xaf, +0xc7,0xaa,0xea,0x12,0xa7,0xe8,0xd0,0xd7,0xed,0x6d,0x18,0xa7,0x70,0xb2,0x3f,0x0c, +0x35,0x0f,0xf8,0x24,0xc7,0xed,0x0d,0x65,0x9f,0x2b,0x45,0xd1,0x6f,0xb1,0xff,0x00, +0x3e,0xfa,0xc4,0x43,0x3f,0xf7,0xde,0xda,0xe5,0x35,0x6f,0xf8,0x26,0x9f,0xed,0x1d, +0xa4,0xb1,0x07,0xe1,0xcc,0xd7,0x60,0x75,0x6b,0x5d,0x42,0xd2,0x41,0xff,0x00,0xa3, +0x6b,0xf7,0xeb,0x14,0x62,0x8b,0x85,0x91,0xfc,0xf0,0x5e,0xfe,0xc2,0x3f,0xb4,0x05, +0x81,0x22,0x5f,0x85,0x1e,0x22,0x6c,0x7f,0xcf,0x1b,0x71,0x2f,0xfe,0x80,0x4d,0x72, +0xfa,0xa7,0xec,0xb7,0xf1,0x8b,0x46,0x62,0xb7,0x9f,0x0b,0x7c,0x5f,0x16,0x3a,0x91, +0xa2,0x5c,0x38,0x1f,0x8a,0xa1,0x15,0xfd,0x23,0xd1,0x8a,0x2e,0x2b,0x1f,0xcc,0x7d, +0xff,0x00,0xc2,0xef,0x19,0xe9,0x4c,0x56,0xf7,0xc2,0x5a,0xed,0x99,0x1d,0x44,0xfa, +0x6c,0xc9,0x8f,0xcd,0x6b,0x02,0xe7,0x4e,0xbb,0xb3,0x62,0xb3,0xda,0xcd,0x03,0x0e, +0xa2,0x48,0xca,0x91,0xf9,0x8a,0xfe,0xa3,0xf0,0x2a,0xbd,0xc6,0x99,0x67,0x76,0x8c, +0x93,0xda,0xc1,0x32,0xb7,0x05,0x64,0x8c,0x30,0x3f,0x98,0xa2,0xe1,0xca,0x7f,0x2e, +0x18,0xa2,0xbf,0xa6,0x6d,0x43,0xe0,0xc7,0xc3,0xed,0x58,0xb1,0xbe,0xf0,0x2f,0x86, +0xaf,0x0b,0x72,0xc6,0x7d,0x22,0xdd,0xc9,0xfa,0xe5,0x2b,0x9e,0xbd,0xfd,0x95,0xbe, +0x0c,0xea,0x0a,0xcb,0x3f,0xc2,0x8f,0x06,0x3e,0xee,0xa4,0x68,0x36,0xca,0x7f,0x30, +0x80,0xd1,0x71,0x72,0x9f,0xcd,0xd5,0x18,0x3d,0x6b,0xfa,0x1a,0xd5,0x7f,0x60,0x8f, +0xd9,0xf7,0x58,0x56,0x13,0xfc,0x29,0xd0,0x23,0xdd,0xd4,0xda,0xc4,0xd0,0x1f,0xcd, +0x18,0x57,0x23,0x77,0xff,0x00,0x04,0xbb,0xfd,0x9b,0x2e,0xd9,0x9b,0xfe,0x15,0xfc, +0x90,0x33,0x73,0x98,0x75,0xbb,0xf1,0xfa,0x79,0xf8,0x1f,0x95,0x3b,0x87,0x29,0xf8, +0x27,0x45,0x7e,0xe5,0xeb,0x3f,0xf0,0x49,0x4f,0xd9,0xef,0x53,0x8c,0xad,0xae,0x91, +0xad,0xe9,0x07,0xb3,0x5a,0x6b,0x12,0xb9,0x1f,0xf7,0xf7,0x7d,0x71,0xd7,0xbf,0xf0, +0x46,0x0f,0x83,0x73,0xb9,0x6b,0x7f,0x14,0xf8,0xd6,0xdb,0x3f,0xc3,0xf6,0xcb,0x47, +0x03,0xf3,0xb6,0xcf,0xeb,0x45,0xc3,0x94,0xfc,0x65,0xa2,0xbf,0x5f,0xb5,0x5f,0xf8, +0x22,0x97,0xc3,0xc9,0x50,0x0d,0x37,0xe2,0x0f,0x89,0xed,0x5f,0xd6,0xea,0x1b,0x79, +0xc7,0xe4,0xa8,0x95,0xc8,0xea,0x7f,0xf0,0x44,0x58,0x49,0x3f,0xd9,0xdf,0x16,0x9d, +0x7d,0x05,0xd6,0x85,0x9f,0xd5,0x67,0x14,0x5c,0x56,0x67,0xe5,0x7d,0x48,0x97,0x33, +0x45,0xf7,0x25,0x74,0xff,0x00,0x75,0x88,0xaf,0xd2,0x8b,0xef,0xf8,0x22,0x57,0x8a, +0x63,0xcf,0xd8,0xfe,0x28,0xe9,0x13,0xfa,0x79,0xfa,0x54,0xb1,0x67,0xf2,0x91,0xab, +0x95,0xd4,0xff,0x00,0xe0,0x8c,0x1f,0x16,0xad,0xc9,0xfb,0x0f,0x8b,0x3c,0x27,0x7a, +0x07,0x4f,0x32,0x6b,0x88,0x89,0xff,0x00,0xc8,0x46,0x80,0xb3,0x3e,0x19,0xd3,0xfc, +0x77,0xe2,0x5d,0x25,0x95,0xac,0x7c,0x43,0xaa,0xd9,0x95,0xe4,0x1b,0x7b,0xd9,0x13, +0x1f,0x93,0x57,0x63,0xa7,0x7e,0xd3,0xbf,0x17,0xf4,0x95,0x55,0xb3,0xf8,0xa1,0xe2, +0xfb,0x74,0x5e,0x8a,0x9a,0xdd,0xc8,0x03,0xf0,0xdf,0x5f,0x47,0x5e,0x7f,0xc1,0x20, +0x7e,0x3e,0x5b,0x13,0xe5,0x8f,0x0b,0xdd,0x81,0xd3,0xc9,0xd5,0x58,0x67,0xfe,0xfa, +0x8c,0x57,0x35,0xa9,0xff,0x00,0xc1,0x2b,0xff,0x00,0x68,0xcd,0x3c,0x31,0x8f,0xc2, +0x16,0x77,0xd8,0xff,0x00,0x9f,0x5d,0x5e,0xd8,0xe7,0xe9,0xb9,0xd6,0x80,0xd4,0xf3, +0x8b,0x4f,0xdb,0x7b,0xe3,0xdd,0x96,0x3c,0xaf,0x8b,0x3e,0x29,0x38,0xe9,0xe6,0xdf, +0xb4,0x9f,0xfa,0x16,0x6b,0xa5,0xd3,0x7f,0xe0,0xa3,0xbf,0xb4,0x5e,0x99,0x81,0x1f, +0xc4,0xbb,0xd9,0x80,0xed,0x73,0x69,0x6d,0x2e,0x7f,0xef,0xa8,0xcd,0x56,0xbf,0xff, +0x00,0x82,0x78,0x7e,0xd1,0x3a,0x71,0x3e,0x67,0xc2,0xed,0x52,0x4c,0x7f,0xcf,0x09, +0xed,0xe5,0xff,0x00,0xd0,0x64,0x35,0xcd,0x6a,0x5f,0xb1,0x97,0xc7,0x4d,0x28,0x91, +0x71,0xf0,0x9f,0xc5,0x9c,0x75,0x30,0xe9,0x92,0x4a,0x3f,0x34,0x06,0x80,0xd4,0xf5, +0x8b,0x2f,0xf8,0x2a,0xd7,0xed,0x17,0x68,0xa0,0x3f,0x8a,0x34,0xdb,0xac,0x77,0x9f, +0x46,0xb7,0xe7,0xfe,0xf9,0x51,0x5b,0xf6,0x1f,0xf0,0x57,0xff,0x00,0x8f,0x56,0xa4, +0x79,0xeb,0xe1,0x8b,0xc0,0x3a,0xf9,0xba,0x5b,0x29,0x3f,0xf7,0xcc,0x82,0xbe,0x5b, +0xd4,0xfe,0x04,0xfc,0x49,0xd1,0x5c,0xa5,0xf7,0xc3,0xff,0x00,0x14,0x5a,0x30,0xea, +0x25,0xd1,0xee,0x17,0xff,0x00,0x64,0xae,0x7e,0xf3,0xc1,0x5e,0x21,0xd3,0xce,0x2e, +0xb4,0x1d,0x4e,0xd8,0xff,0x00,0xd3,0x6b,0x39,0x13,0xf9,0xad,0x03,0xd4,0xfb,0xcb, +0x4d,0xff,0x00,0x82,0xd2,0xfc,0x51,0xb7,0x50,0x2f,0x7c,0x15,0xe1,0x5b,0xcf,0x52, +0x82,0xe2,0x23,0xff,0x00,0xa3,0x0d,0x74,0x56,0x5f,0xf0,0x5b,0x5f,0x14,0x2e,0x05, +0xdf,0xc3,0x0d,0x22,0x5f,0x53,0x06,0xa7,0x2a,0x7f,0x34,0x35,0xf9,0xab,0x34,0x12, +0xdb,0xb6,0xd9,0x63,0x78,0x9b,0xd1,0xd4,0x83,0x4c,0xa3,0x40,0xbb,0x3f,0x54,0x74, +0xbf,0xf8,0x2d,0xcd,0xbe,0x40,0xd4,0x7e,0x14,0x4a,0x07,0x73,0x6b,0xad,0x03,0xfa, +0x34,0x35,0xd4,0x58,0xff,0x00,0xc1,0x6b,0xfc,0x07,0x20,0x1f,0x6c,0xf8,0x77,0xe2, +0x38,0x0f,0xfd,0x30,0xb9,0xb7,0x93,0xf9,0x95,0xaf,0xc8,0x6c,0x51,0x45,0x85,0xcc, +0xcf,0xd9,0x9d,0x3b,0xfe,0x0b,0x39,0xf0,0x82,0xe4,0x81,0x77,0xe1,0x8f,0x17,0xd9, +0x67,0xf8,0xbe,0xcd,0x6f,0x20,0x1f,0x94,0xd5,0xd7,0x69,0xdf,0xf0,0x56,0xff,0x00, +0xd9,0xf6,0xf2,0x20,0xd7,0x1a,0x96,0xbd,0xa7,0xb1,0xfe,0x19,0xf4,0x99,0x18,0x8f, +0xfb,0xe0,0xb0,0xaf,0xc3,0x8a,0xb5,0xa4,0xd8,0xbe,0xa7,0xaa,0xd9,0xd9,0xc4,0xbb, +0xa5,0xb8,0x99,0x21,0x50,0x3b,0x96,0x60,0x07,0xf3,0xa2,0xc3,0xb9,0xfd,0x3f,0xe8, +0x3a,0xd5,0xb7,0x88,0xf4,0x4d,0x3f,0x56,0xb3,0x2e,0x6c,0xef,0xed,0xe3,0xba,0x84, +0xc8,0xa5,0x58,0xa3,0xa8,0x65,0xca,0x9e,0x41,0xc1,0x1c,0x1a,0xbf,0x55,0x34,0xab, +0x18,0xf4,0xcd,0x32,0xd2,0xce,0x14,0x11,0xc5,0x6f,0x0a,0x44,0x88,0x3a,0x28,0x55, +0x00,0x0f,0xd2,0xad,0xd4,0x96,0x14,0x51,0x45,0x00,0x72,0x3f,0x14,0xe7,0xfb,0x3f, +0x83,0x6f,0x4f,0xa8,0xc5,0x7c,0x0d,0xe2,0x29,0x37,0xdf,0xdd,0x37,0xab,0x9a,0xfb, +0x9b,0xe3,0x65,0xcf,0x91,0xe0,0xc9,0x87,0xf7,0x8e,0x3f,0x4a,0xf8,0x43,0x5a,0x7d, +0xd3,0x4e,0xde,0xac,0x6b,0xe0,0x33,0xe7,0x7c,0x54,0x23,0xd9,0x1f,0x01,0xc4,0xf3, +0xb2,0x48,0xf1,0x4f,0x1a,0x42,0x35,0x2f,0x88,0x9e,0x12,0xb1,0x64,0xf3,0x16,0xe7, +0x5a,0xb2,0x84,0xa6,0x33,0xb8,0x34,0xe8,0x08,0xfc,0x8d,0x7e,0xcc,0xa0,0x0a,0xa1, +0x40,0xc0,0x1c,0x57,0xe3,0xef,0x87,0xac,0x9f,0x5c,0xfd,0xa4,0xfe,0x19,0x59,0x2f, +0x3b,0xbc,0x47,0x67,0x26,0x3d,0x92,0x40,0xe7,0xff,0x00,0x40,0xaf,0xd8,0x31,0x5f, +0x57,0x97,0x46,0xd4,0x11,0xd7,0xc2,0x71,0xe5,0xcb,0xef,0xdd,0xb1,0x68,0xa2,0x8a, +0xf5,0x0f,0xb4,0x3f,0x3c,0xbf,0x6b,0x4f,0x07,0xde,0xfc,0x28,0xf8,0xc1,0x3e,0xbf, +0x6f,0x19,0x5d,0x0b,0xc4,0x4d,0xf6,0x95,0x78,0xc6,0x04,0x73,0x80,0x04,0xaa,0x7d, +0xc9,0xf9,0xff,0x00,0xe0,0x47,0xd2,0xb9,0x0d,0x2b,0xc6,0x12,0x5d,0xc4,0xaf,0x15, +0xeb,0xe0,0x8e,0xcf,0x5f,0xa1,0xbf,0x13,0xfe,0x1a,0x68,0xdf,0x15,0xfc,0x21,0x77, +0xe1,0xfd,0x6e,0x0f,0x36,0xda,0x61,0xba,0x39,0x57,0x1b,0xe0,0x90,0x0f,0x96,0x44, +0x3d,0x88,0xcf,0xe3,0xc8,0x3c,0x1a,0xfc,0xed,0xf8,0x9f,0xfb,0x2e,0xf8,0xe3,0xe1, +0x16,0xa9,0x33,0xdb,0xac,0x97,0xda,0x46,0xec,0xc3,0x7f,0x6e,0xa4,0xc6,0xc3,0x3c, +0x06,0x1f,0xc2,0x7d,0x8f,0xe1,0x9a,0xf9,0x3c,0xcb,0x2d,0x84,0xe4,0xea,0x6c,0x7e, +0x4f,0x9d,0xe5,0x78,0x9c,0x16,0x22,0x58,0xac,0x22,0x6e,0x13,0x77,0x69,0x74,0x66, +0xfc,0x3e,0x28,0xd4,0x23,0xe6,0x3b,0xf9,0x47,0xfc,0x0e,0xaf,0x43,0xe3,0x9d,0x6e, +0x1f,0xbb,0xa9,0x4b,0xf8,0xb5,0x78,0xb9,0xb9,0xf1,0x3e,0x9f,0xf2,0x4d,0x68,0x5c, +0x8e,0xf8,0xe4,0xd2,0x8f,0x15,0xeb,0x11,0x7d,0xfb,0x09,0x3f,0x23,0x5f,0x35,0xf5, +0x19,0xaf,0x86,0x4b,0xef,0x3c,0x48,0xe2,0x71,0xd1,0x5f,0x0c,0xbe,0xf3,0xdd,0x21, +0xf8,0x9f,0xe2,0x38,0x0f,0xcb,0xa8,0xb9,0xad,0x1b,0x7f,0x8c,0xfe,0x26,0xb7,0xe9, +0x7a,0xcd,0xf5,0xaf,0x9f,0x57,0xc7,0x97,0x91,0xfd,0xfb,0x49,0x57,0xf0,0x35,0x22, +0x7c,0x46,0x2b,0xf7,0xe2,0x90,0x1f,0x71,0x4d,0x61,0x71,0x31,0xf8,0x64,0xfe,0xf3, +0x55,0x99,0x63,0x61,0xba,0x91,0xf4,0x94,0x1f,0xb4,0x1f,0x8a,0x21,0xc7,0xef,0xf3, +0xf8,0xd6,0xa5,0xbf,0xed,0x33,0xe2,0x38,0xb1,0xbc,0x96,0xc7,0xbd,0x7c,0xc2,0x9f, +0x12,0x60,0xfe,0x2d,0xc3,0xf0,0xab,0x31,0xfc,0x44,0xb4,0x60,0x32,0xff,0x00,0xa5, +0x5a,0x58,0xf8,0xed,0x37,0xf7,0x9b,0x47,0x3c,0xc5,0x43,0x79,0x4b,0xee,0x3e,0xa8, +0xb5,0xfd,0xaa,0x75,0x98,0x88,0xf3,0x22,0xdc,0x3f,0x3a,0xd5,0xb7,0xfd,0xac,0xae, +0x86,0x3c,0xcb,0x6c,0xfa,0xfc,0xa2,0xbe,0x4c,0x8f,0xc7,0x96,0x4d,0xff,0x00,0x2d, +0x16,0xac,0xa7,0x8c,0xac,0x9f,0x1f,0xbd,0x43,0xf8,0xd5,0xac,0x46,0x63,0x0f,0xb4, +0xcd,0xe3,0xc4,0x98,0x88,0xef,0x3f,0xc0,0xfa,0xfe,0xd7,0xf6,0xb2,0x84,0xe3,0xce, +0xb6,0xff,0x00,0xc7,0x6b,0x52,0xdb,0xf6,0xab,0xd2,0xe4,0x23,0xcc,0x80,0x0f,0xc0, +0xd7,0xc6,0x69,0xe2,0x8b,0x37,0xe9,0x2a,0xfe,0x06,0xa7,0x4d,0x7a,0xd5,0xfa,0x38, +0x3f,0x8d,0x52,0xcc,0x73,0x18,0x6e,0xff,0x00,0x03,0xaa,0x3c,0x51,0x5b,0xf9,0x91, +0xf6,0xdd,0xbf,0xed,0x3b,0xe1,0xe9,0x00,0xde,0x30,0x4f,0xfb,0x55,0xa9,0x6d,0xfb, +0x43,0xf8,0x66,0x7c,0x66,0x5d,0xbf,0xf0,0x21,0x5f,0x0a,0xae,0xad,0x6e,0xdd,0x1c, +0x54,0x83,0x50,0x84,0xf4,0x93,0xf5,0xad,0x16,0x73,0x8f,0x8e,0xf6,0xfb,0x8e,0xb8, +0x71,0x45,0x4e,0xb6,0x3e,0xf8,0xb7,0xf8,0xdf,0xe1,0x99,0xc8,0xc5,0xd0,0x1f,0x88, +0xad,0x28,0x3e,0x2a,0xf8,0x72,0x71,0x91,0x7e,0xa3,0xf2,0xaf,0xcf,0xa5,0xbf,0x51, +0xf7,0x66,0x23,0xe8,0x6a,0x64,0xd4,0xe4,0x5f,0xbb,0x70,0xc3,0xfe,0x05,0x5a,0xac, +0xfb,0x14,0xbe,0x28,0x2f,0xc4,0xeb,0x8f,0x13,0xcb,0xac,0x51,0xfa,0x19,0x17,0x8f, +0xb4,0x29,0xbe,0xee,0xa1,0x1f,0xe7,0x57,0x23,0xf1,0x4e,0x95,0x2f,0xdd,0xbe,0x84, +0xff,0x00,0xc0,0xab,0xf3,0xbe,0x3d,0x6e,0xf1,0x3e,0xe5,0xe4,0xa3,0xe8,0xf5,0x66, +0x3f,0x15,0xea,0xb1,0x11,0xb7,0x50,0x9b,0xfe,0xfb,0x35,0xb2,0xe2,0x1a,0x8b,0xe2, +0xa7,0xf8,0x9d,0x51,0xe2,0x58,0x3d,0xe0,0x7e,0x88,0xa6,0xb1,0x63,0x27,0xdd,0xbb, +0x88,0xff,0x00,0xc0,0xc5,0x4a,0xb7,0x90,0x3f,0xdd,0x99,0x0f,0xd1,0x85,0x7e,0x7b, +0x43,0xe3,0xfd,0x7a,0x2f,0xbb,0xa8,0xcb,0xf9,0xd5,0xf8,0x3e,0x2b,0x78,0x8e,0x0c, +0x62,0xf9,0xcf,0xd4,0xd6,0xeb,0x88,0xa3,0xf6,0xa9,0xbf,0xbc,0xe8,0x8f,0x11,0xd0, +0x7b,0xc5,0x9f,0x7f,0x09,0x14,0xff,0x00,0x10,0xfc,0xe9,0x73,0xef,0x5f,0x08,0xc1, +0xf1,0xbf,0xc4,0xd0,0x7f,0xcb,0xd1,0x6f,0xc4,0xd6,0x9d,0xb7,0xed,0x11,0xe2,0x58, +0x3a,0xcb,0x9f,0xf8,0x11,0xad,0xe3,0xc4,0x34,0x1e,0xf0,0x67,0x44,0x78,0x83,0x0a, +0xf7,0xb9,0xf6,0xe0,0x34,0x66,0xbe,0x37,0xb6,0xfd,0xa7,0x35,0xf8,0x71,0xbf,0x2d, +0xf8,0xd6,0xad,0xbf,0xed,0x57,0xaa,0x2f,0xfa,0xc8,0x49,0x1f,0x85,0x6d,0x1c,0xfb, +0x08,0xf7,0xbf,0xdc,0x6f,0x1c,0xf3,0x06,0xfe,0xd1,0xf5,0x9e,0x68,0x07,0x35,0xf3, +0x0d,0xbf,0xed,0x65,0x28,0xff,0x00,0x59,0x6f,0x9f,0xf8,0x0e,0x6b,0x52,0xdb,0xf6, +0xb1,0xb5,0x38,0xf3,0x6d,0xc0,0xfc,0x2b,0xa2,0x39,0xd6,0x09,0xfd,0xaf,0xc0,0xe9, +0x8e,0x6d,0x83,0x97,0xdb,0x3e,0x8b,0xa2,0xbc,0x26,0x0f,0xda,0xa3,0x47,0x7c,0x07, +0x88,0x03,0xdf,0xad,0x6a,0x5b,0x7e,0xd2,0xde,0x1e,0x98,0x0d,0xe4,0x2f,0xfc,0x0a, +0xb7,0x8e,0x6b,0x83,0x97,0xfc,0xbc,0x46,0xf1,0xc7,0xe1,0xa5,0xb4,0xd1,0xec,0x54, +0x57,0x98,0xdb,0xfe,0xd0,0x3e,0x19,0x9f,0xfe,0x5b,0x05,0xff,0x00,0x81,0x56,0x9c, +0x1f,0x19,0xfc,0x35,0x36,0x3f,0xd3,0x00,0xfc,0x45,0x74,0x47,0x1d,0x86,0x96,0xd5, +0x17,0xde,0x6e,0xb1,0x34,0x65,0xb4,0xd1,0xdd,0xd1,0x5c,0xa4,0x1f,0x13,0xfc,0x3d, +0x38,0x18,0xbe,0x41,0xf5,0x35,0x76,0x2f,0x1c,0xe8,0x93,0x7d,0xdb,0xf8,0x8f,0xe3, +0x5b,0x2c,0x45,0x29,0x6d,0x25,0xf7,0x9a,0x2a,0xb4,0xde,0xd2,0x46,0xf5,0x15,0x97, +0x1f,0x89,0x74,0xc9,0x47,0xcb,0x7d,0x09,0xff,0x00,0x81,0x55,0x94,0xd5,0xac,0xe4, +0xfb,0xb7,0x51,0x1f,0xf8,0x10,0xad,0x54,0xe2,0xf6,0x65,0xa9,0x27,0xb3,0x2d,0xd1, +0x51,0x0b,0xa8,0x5b,0xa4,0xa8,0x7f,0xe0,0x42,0x9e,0x1d,0x58,0x64,0x10,0x7e,0x86, +0xaa,0xe8,0xab,0x8e,0xa2,0x93,0x34,0x66,0x98,0x0b,0x45,0x26,0x45,0x19,0xa0,0x05, +0xa2,0x93,0x34,0xb4,0x00,0x51,0x45,0x14,0x00,0x51,0x45,0x14,0x00,0x51,0x45,0x14, +0x00,0x51,0x45,0x14,0x00,0x51,0x45,0x14,0x00,0x51,0x45,0x14,0x00,0x51,0x45,0x14, +0x00,0x51,0x45,0x14,0x00,0x94,0x6d,0x06,0x96,0x8a,0x00,0x4c,0x51,0x8a,0x5a,0x28, +0x01,0x31,0x4d,0x31,0xa1,0x04,0x15,0x04,0x1e,0xb9,0x14,0xfa,0x28,0x03,0x1e,0xfb, +0xc1,0xba,0x06,0xa9,0x9f,0xb6,0x68,0x7a,0x6d,0xde,0x7a,0xf9,0xf6,0x91,0xbe,0x7f, +0x31,0x5c,0xe5,0xf7,0xc0,0x6f,0x86,0x7a,0x9e,0xef,0xb5,0xfc,0x3c,0xf0,0xad,0xc9, +0x6e,0xa6,0x5d,0x16,0xd9,0x89,0xfc,0x4a,0x57,0x77,0x45,0x00,0x78,0xd6,0xa9,0xfb, +0x1a,0x7c,0x0b,0xd6,0x15,0xc5,0xcf,0xc2,0x6f,0x09,0x12,0xfd,0x5a,0x2d,0x2a,0x28, +0x9b,0xfe,0xfa,0x40,0x08,0xae,0x2e,0xfb,0xfe,0x09,0xb1,0xfb,0x37,0x5f,0xbb,0xb4, +0x9f,0x0c,0xad,0x23,0x2d,0xd7,0xc8,0xd4,0x6f,0x22,0x03,0xe8,0x16,0x60,0x05,0x7d, +0x33,0x45,0x00,0x7c,0x97,0x7f,0xff,0x00,0x04,0xb0,0xfd,0x9b,0xaf,0x22,0x65,0x8f, +0xc1,0x17,0x56,0x6c,0x7f,0x8e,0x0d,0x6e,0xf4,0x91,0xff,0x00,0x7d,0x4a,0xc3,0xf4, +0xac,0x5d,0x0f,0xfe,0x09,0x3f,0xf0,0x43,0xc3,0x5e,0x2b,0xd2,0x3c,0x41,0xa7,0x37, +0x89,0x21,0xba,0xd2,0xef,0x61,0xbe,0x86,0x17,0xd4,0x52,0x48,0x59,0xe3,0x70,0xe1, +0x58,0x34,0x44,0x95,0x25,0x40,0x23,0x3d,0x3b,0xd7,0xd9,0xd4,0x50,0x2b,0x05,0x14, +0x51,0x40,0xc2,0x8a,0x28,0xa0,0x0f,0x29,0xfd,0xa1,0x2e,0x7c,0x9f,0x0a,0x05,0xce, +0x32,0x58,0xfe,0x95,0xf0,0xf6,0xaa,0xfc,0x48,0x7d,0xcd,0x7d,0x97,0xfb,0x4b,0xdc, +0xf9,0x7a,0x24,0x29,0x9f,0xe1,0x3c,0x57,0xc5,0xda,0xb3,0xe2,0x27,0x3f,0x5a,0xfc, +0xeb,0x38,0x7c,0xd8,0xfb,0x76,0x48,0xfc,0xd3,0x8a,0x27,0xef,0xdb,0xc8,0xe4,0x3e, +0x04,0xda,0x0d,0x63,0xf6,0xc8,0xf8,0x6d,0x01,0xc9,0xf2,0xaf,0xe6,0xb9,0xe3,0xfe, +0x99,0xdb,0xca,0xc3,0xf9,0x57,0xeb,0x58,0xaf,0xcb,0x1f,0xd8,0xe7,0x4f,0x6d,0x5f, +0xf6,0xce,0xd0,0xa5,0x03,0x29,0x61,0xa7,0xdf,0x5d,0x37,0xb0,0xf2,0xbc,0xb1,0xfa, +0xc8,0x2b,0xf5,0x38,0x77,0xaf,0xb7,0xc1,0xab,0x51,0x47,0xd1,0xf0,0xd4,0x39,0x32, +0xca,0x7e,0x62,0xd1,0x45,0x15,0xdc,0x7d,0x40,0x98,0xa6,0xc9,0x0a,0x4a,0xa5,0x5d, +0x43,0xa1,0xe0,0xab,0x0c,0x83,0x4f,0xa2,0x80,0x38,0xad,0x6b,0xe0,0xcf,0x83,0x35, +0xf9,0x1a,0x4b,0xbd,0x02,0xd7,0xcc,0x61,0x82,0xd0,0x83,0x17,0xe8,0xa4,0x0a,0xe5, +0xaf,0x7f,0x65,0x8f,0x01,0x5d,0x9c,0xad,0x95,0xc5,0xbf,0xb4,0x53,0x7f,0xf1,0x40, +0xd7,0xaf,0x51,0x5c,0xd2,0xc3,0x51,0x96,0xf0,0x47,0x24,0xb0,0x98,0x79,0xbb,0xca, +0x9a,0xfb,0x8f,0x09,0xba,0xfd,0x8f,0x3c,0x13,0x36,0x4a,0x4d,0xa8,0x46,0x7d,0xdd, +0x08,0xff,0x00,0xd0,0x2b,0x02,0xff,0x00,0xf6,0x26,0xd0,0x27,0xcf,0xd9,0xf5,0x69, +0x22,0x3f,0xf4,0xd2,0xdc,0x3f,0xf2,0x61,0x5f,0x4a,0x51,0xf8,0xd6,0x4f,0x03,0x87, +0x7f,0x60,0xe7,0x79,0x6e,0x16,0x5f,0x63,0xf3,0x3e,0x50,0xbc,0xfd,0x84,0xec,0x64, +0xe6,0x2d,0x6a,0x17,0x3f,0xed,0xda,0x95,0xff,0x00,0xd9,0x8d,0x73,0xd7,0xdf,0xb0, +0x65,0xd9,0x62,0x20,0xbb,0xd3,0x5c,0x76,0x2c,0x59,0x4f,0xfe,0x81,0x5f,0x68,0x62, +0x8c,0x56,0x4f,0x2e,0xa0,0xfa,0x3f,0xbd,0x98,0xbc,0xa7,0x0a,0xfe,0xcb,0xfb,0xd9, +0xf0,0x8d,0xe7,0xec,0x1d,0xae,0x2a,0xb1,0x8d,0x6c,0x65,0x3d,0x82,0x4d,0x8c,0xfe, +0x78,0xae,0x7a,0xfb,0xf6,0x20,0xf1,0x54,0x07,0xe4,0xd3,0x0b,0x0f,0xfa,0x67,0x70, +0x87,0xff,0x00,0x66,0xaf,0xd0,0xfc,0x51,0x8a,0x87,0x96,0xd3,0xe9,0x27,0xf7,0x9c, +0xf2,0xc8,0xf0,0xb2,0xef,0xf8,0x7f,0x91,0xf9,0xa7,0x7b,0xfb,0x1f,0x78,0xc6,0xd4, +0x90,0xba,0x46,0xa0,0x4f,0xfb,0x1f,0x30,0xfd,0x2b,0x0a,0xef,0xf6,0x69,0xf1,0x85, +0x91,0x3b,0xb4,0xed,0x4e,0x3c,0x7a,0xdb,0xb7,0xf8,0x57,0xea,0x4e,0x29,0x0a,0xe6, +0xa1,0xe5,0xab,0xa4,0xdf,0xe0,0x72,0xcb,0x87,0x70,0xd2,0xeb,0xf8,0x23,0xf2,0x7a, +0xef,0xe0,0xd7,0x8a,0x6c,0x72,0x59,0x6e,0xa3,0x03,0xfb,0xf1,0x11,0x59,0xef,0xe0, +0x3f,0x13,0xdb,0x74,0x91,0xce,0x3d,0x54,0xd7,0xeb,0x83,0x44,0xae,0x30,0xc0,0x11, +0xe8,0x45,0x55,0x9f,0x45,0xb0,0xba,0xff,0x00,0x5d,0x65,0x6f,0x30,0xff,0x00,0x6e, +0x25,0x3f,0xd2,0xb2,0x79,0x6c,0xba,0x4f,0xf0,0x38,0xe5,0xc2,0xf8,0x79,0x76,0xfb, +0xbf,0xe0,0x9f,0x92,0x6d,0xa0,0x78,0xaa,0xdf,0xdf,0xeb,0x9a,0x88,0xa7,0x8a,0x2d, +0xfe,0xf4,0x3b,0xbe,0x86,0xbf,0x57,0xee,0x3c,0x03,0xe1,0xbb,0xa0,0x7c,0xdd,0x07, +0x4d,0x7c,0xf7,0x36,0xa9,0xfe,0x15,0x97,0x73,0xf0,0x6f,0xc1,0x77,0x79,0xf3,0x3c, +0x3b,0x67,0xff,0x00,0x00,0x52,0x9f,0xc8,0x8a,0xc9,0xe5,0xb5,0x3b,0xa6,0x72,0x4b, +0x84,0xe9,0x74,0xb7,0xe2,0x8f,0xcb,0x31,0xaa,0xf8,0x8a,0x0f,0xbf,0x68,0xc6,0x94, +0x78,0xab,0x58,0x8b,0xef,0xd8,0xcb,0xc7,0xfb,0x26,0xbf,0x4d,0xae,0x7f,0x67,0x8f, +0x00,0xdd,0x67,0x3a,0x12,0x46,0x4f,0x74,0x99,0xff,0x00,0xf8,0xaa,0xc5,0xbb,0xfd, +0x94,0xfc,0x09,0x75,0x9d,0xb6,0xf7,0x70,0x67,0xfe,0x79,0xca,0xbf,0xd5,0x4d,0x63, +0x2c,0xb2,0xa7,0xf2,0xc5,0x9c,0xb2,0xe1,0x37,0xd3,0xff,0x00,0x4a,0x67,0xe7,0x32, +0xf8,0xee,0xf6,0x3f,0xbf,0x6b,0x28,0xfc,0x0d,0x4c,0x9f,0x11,0x4a,0x9f,0x9e,0x17, +0x1f,0x85,0x7d,0xf7,0x79,0xfb,0x1c,0x78,0x36,0x7f,0xf5,0x37,0x57,0xd1,0x1f,0xf6, +0x8a,0x37,0xfe,0xca,0x2b,0x02,0xf3,0xf6,0x22,0xd1,0x26,0x72,0x62,0xd6,0x9d,0x17, +0xd1,0xed,0x43,0x1f,0xcf,0x78,0xac,0x1e,0x59,0x3e,0xb4,0x97,0xde,0x73,0x4b,0x85, +0xab,0xaf,0x86,0xff,0x00,0x7a,0x3e,0x2b,0x4f,0x89,0x10,0xff,0x00,0x10,0x65,0xfa, +0x8a,0xb1,0x1f,0xc4,0x4b,0x46,0xea,0xf8,0xaf,0xac,0x2f,0x7f,0x61,0x2b,0x49,0x01, +0xf2,0x35,0x88,0x1d,0xbb,0x09,0x2d,0x8a,0xff,0x00,0x53,0x5c,0xf5,0xe7,0xec,0x19, +0xa8,0x1f,0xf5,0x77,0x5a,0x63,0x8f,0xf7,0x98,0x7f,0xec,0xb5,0x83,0xcb,0x5f,0x5a, +0x4c,0xe7,0x97,0x0e,0xe2,0xe3,0xb3,0x97,0xe0,0xcf,0x9e,0xa3,0xf1,0xed,0x9b,0xff, +0x00,0xcb,0x45,0x15,0x66,0x3f,0x19,0xd9,0x3f,0xfc,0xb5,0x4f,0xce,0xbd,0x7a,0xfb, +0xf6,0x11,0xd7,0xe3,0x62,0x23,0x86,0xce,0x61,0xeb,0x1c,0xc0,0x67,0xf3,0xc5,0x73, +0xf7,0x9f,0xb1,0x27,0x8b,0x21,0xdd,0xb3,0x4a,0x76,0x03,0xfe,0x79,0xdc,0x21,0xff, +0x00,0xd9,0xab,0x09,0x65,0xb1,0x5b,0xd3,0x92,0xf9,0x1c,0xd2,0xc9,0x31,0xd1,0xea, +0xff,0x00,0xf0,0x13,0x89,0x4f,0x14,0xd9,0xbf,0xfc,0xb5,0x4f,0xfb,0xea,0xa7,0x4d, +0x7e,0xd5,0xff,0x00,0x8d,0x4f,0xe2,0x2b,0x4a,0xf7,0xf6,0x43,0xf1,0x8d,0xa0,0x2d, +0xfd,0x8f,0xa8,0x81,0xe9,0x1a,0x16,0xfe,0x42,0xb0,0xef,0x7f,0x66,0xdf,0x17,0x58, +0xf2,0xda,0x76,0xa7,0x17,0xfb,0xf6,0xed,0xfe,0x15,0xcf,0x2c,0xbe,0x9a,0xee,0xbe, +0x47,0x3c,0xb2,0xdc,0x74,0x3a,0xfe,0x0c,0xbe,0xba,0xb5,0xbb,0x7f,0x18,0xa9,0x17, +0x51,0x80,0xff,0x00,0x18,0xae,0x46,0xe7,0xe1,0x07,0x89,0xac,0x8e,0x1b,0xed,0x28, +0x47,0x67,0x88,0xd5,0x17,0xf0,0x2f,0x89,0xad,0x8f,0x12,0x3f,0x1e,0xaa,0x6b,0x17, +0x81,0xa5,0xd2,0x46,0x2f,0x0d,0x8d,0x8f,0x63,0xd0,0x16,0xfa,0x23,0xd2,0x4f,0xd6, +0xa5,0x5b,0xdc,0x7d,0xd9,0x88,0xfc,0x6b,0xcc,0xdb,0x42,0xf1,0x4d,0xbe,0x79,0x27, +0xeb,0x9a,0x66,0xcf,0x13,0x41,0xf7,0xa2,0x2d,0x8f,0x43,0x51,0xfd,0x9f,0x17,0xb4, +0x85,0xc9,0x8d,0x8f,0xd8,0xfc,0x4f,0x55,0x4d,0x52,0x74,0xfb,0xb7,0x4e,0x3e,0x8d, +0x56,0x23,0xd7,0xef,0xe3,0xfb,0x97,0xb2,0x8f,0xa3,0x1a,0xf2,0x1f,0xed,0x5f,0x10, +0xc2,0x3e,0x6b,0x47,0x3f,0x4a,0x51,0xe2,0x9d,0x62,0x3f,0xbf,0x67,0x27,0xfd,0xf3, +0x51,0xfd,0x9d,0x2e,0x92,0x41,0xed,0x31,0xb0,0xde,0x9b,0xfb,0xcf,0x67,0x8f,0xc6, +0x1a,0xc4,0x5f,0x77,0x50,0x97,0xfe,0xfa,0xab,0xb0,0x7c,0x44,0xd7,0xe0,0xfb,0xba, +0x84,0x9f,0x8d,0x78,0x7a,0xf8,0xea,0xf2,0x3f,0xf5,0x96,0xb2,0x8f,0xf8,0x09,0xa9, +0x53,0xe2,0x29,0x5f,0xbf,0x14,0x8b,0xf5,0x14,0x96,0x06,0xbc,0x7e,0x17,0xf8,0x94, +0xb1,0xd8,0xb8,0x6f,0x19,0x23,0xde,0x60,0xf8,0xb7,0xe2,0x48,0x3f,0xe5,0xf4,0x9f, +0xad,0x69,0x43,0xf1,0xd7,0xc4,0xd0,0x81,0x8b,0x8c,0xe3,0xdc,0xd7,0xcf,0x91,0xfc, +0x48,0x87,0xb8,0x65,0xfc,0x2a,0xcc,0x7f,0x11,0x2d,0x5b,0xab,0xe3,0xea,0x2a,0x95, +0x0c,0x5c,0x7e,0x19,0x3f,0xbc,0xd5,0x67,0x18,0x98,0x6e,0xe4,0xbe,0x47,0xd1,0xb6, +0xbf,0xb4,0x67,0x88,0xe0,0x00,0x17,0xcf,0xd0,0xd6,0xa5,0xbf,0xed,0x3f,0xae,0x46, +0x7e,0x70,0xc7,0xf1,0xaf,0x99,0xe3,0xf1,0xed,0x9b,0x7f,0xcb,0x41,0xf8,0xd5,0x98, +0xfc,0x69,0x66,0xf8,0xfd,0xea,0x7e,0x75,0x4a,0x58,0xf8,0x6d,0x26,0x6f,0x1e,0x20, +0xaf,0x1f,0xb6,0xfe,0xe3,0xea,0x5b,0x7f,0xda,0xb3,0x50,0x4c,0x6f,0x84,0x93,0xf4, +0x15,0xa9,0x6b,0xfb,0x58,0x37,0x1e,0x6c,0x39,0xff,0x00,0x80,0xd7,0xc9,0xd1,0xf8, +0xae,0xd1,0xff,0x00,0xe5,0xa2,0x7e,0x75,0x3a,0x78,0x86,0xd5,0xfa,0x3a,0xfe,0x75, +0x6b,0x19,0x98,0xc3,0xed,0x33,0xa6,0x3c,0x4d,0x59,0x7f,0xcb,0xc4,0x7d,0x7f,0x6f, +0xfb,0x56,0xd9,0x39,0xc3,0xc2,0x07,0xd4,0x56,0xad,0xb7,0xed,0x45,0xa2,0xc9,0x8f, +0x31,0x00,0xfc,0x6b,0xe3,0x15,0xd6,0x2d,0xdb,0xf8,0x87,0xe7,0x52,0x2e,0xa5,0x03, +0x7f,0x1e,0x2b,0x45,0x9a,0xe6,0x11,0xdd,0xfe,0x07,0x5c,0x38,0x9a,0xb7,0xf3,0x26, +0x7d,0xbb,0x6d,0xfb,0x48,0x78,0x7a,0x7c,0x6e,0x60,0xbf,0xf0,0x2a,0xd4,0x83,0xe3, +0xdf,0x86,0x66,0xc7,0xef,0xc0,0xff,0x00,0x81,0x0a,0xf8,0x48,0x5f,0x44,0x7a,0x3f, +0xeb,0x4f,0x5b,0xc5,0xea,0x25,0xc7,0xe3,0x5a,0x2c,0xef,0x1b,0x1d,0xd2,0xfb,0x8e, +0xc8,0xf1,0x35,0x5e,0xa9,0x33,0xef,0xd8,0x3e,0x30,0xf8,0x6e,0x7c,0x62,0xec,0x0f, +0xc4,0x55,0xe8,0x7e,0x25,0x78,0x7e,0x7c,0x6d,0xbe,0x4f,0xc6,0xbf,0x3e,0x56,0xf9, +0x86,0x31,0x3b,0x7f,0xdf,0x55,0x3a,0x6a,0xd7,0x51,0xfd,0xcb,0xb9,0x07,0xd1,0xab, +0x65,0xc4,0x18,0x85,0xbc,0x11,0xd5,0x1e,0x25,0x7d,0x60,0x7e,0x86,0x47,0xe3,0x4d, +0x16,0x5c,0x62,0xfe,0x2f,0xc4,0xd5,0xa8,0xfc,0x45,0xa6,0xcb,0xf7,0x6f,0x61,0x3f, +0xf0,0x2a,0xfc,0xf1,0x8f,0xc4,0x7a,0x8c,0x7f,0x76,0xf6,0x51,0xff,0x00,0x02,0xab, +0x91,0x78,0xdf,0x5a,0x87,0xee,0xea,0x12,0x7e,0x75,0xb2,0xe2,0x29,0xaf,0x8a,0x9f, +0xe2,0x74,0x47,0x89,0x21,0xd6,0x07,0xe8,0x52,0xea,0x96,0x8f,0xf7,0x6e,0x62,0x3f, +0x46,0x15,0x2a,0xdc,0x44,0xdd,0x24,0x43,0xf4,0x22,0xbf,0x3f,0x20,0xf8,0x97,0xe2, +0x08,0x08,0xdb,0x7c,0xe7,0xeb,0x57,0xe1,0xf8,0xc5,0xe2,0x48,0x7f,0xe5,0xec,0x9a, +0xde,0x3c,0x45,0x0f,0xb5,0x4d,0x9d,0x31,0xe2,0x2c,0x3b,0xde,0x2c,0xfb,0xdc,0x3a, +0x9e,0x8c,0x0f,0xe3,0x4b,0x9a,0xf8,0x66,0xdf,0xe3,0xdf,0x89,0x2d,0xff,0x00,0xe5, +0xb6,0x7f,0x13,0x5a,0x96,0xdf,0xb4,0x87,0x88,0x21,0xc6,0xe6,0x2d,0xf8,0x9a,0xdd, +0x71,0x0e,0x1d,0xef,0x16,0x8d,0xe3,0x9f,0xe1,0x1e,0xec,0xfb,0x4b,0x38,0xa3,0x22, +0xbe,0x42,0xb7,0xfd,0xa8,0xb5,0x98,0xf1,0xb9,0x0f,0xe7,0x9a,0xd4,0xb5,0xfd,0xab, +0x2e,0xd7,0x1e,0x64,0x44,0xfe,0x15,0xba,0xcf,0xb0,0x8f,0x7b,0xfd,0xc7,0x44,0x73, +0xac,0x1c,0xbe,0xd1,0xf5,0x4e,0x45,0x15,0xf3,0x55,0xb7,0xed,0x5c,0xac,0x47,0x99, +0x00,0x03,0xfd,0xda,0xd5,0xb7,0xfd,0xaa,0x74,0xe6,0xc6,0xf8,0x97,0xf2,0x35,0xbc, +0x73,0x9c,0x14,0xbe,0xd9,0xd1,0x1c,0xd3,0x09,0x2d,0xa6,0x8f,0xa0,0x33,0x4b,0x5e, +0x25,0x6b,0xfb,0x4e,0x68,0xb2,0xfd,0xf0,0x8b,0xf8,0x9a,0xd5,0xb7,0xfd,0xa2,0xfc, +0x3b,0x36,0x01,0x60,0x0f,0xfb,0xd5,0xd1,0x1c,0xcf,0x07,0x2d,0xaa,0x23,0x75,0x8e, +0xc3,0xcb,0x69,0xa3,0xd6,0x28,0xaf,0x3a,0x83,0xe3,0x9f,0x86,0xe6,0xc7,0xfa,0x40, +0x5c,0xff,0x00,0xb4,0x2b,0x46,0xdf,0xe2,0xdf,0x87,0x6e,0x31,0x8b,0xb5,0x1f,0x52, +0x2b,0x75,0x8d,0xc3,0x4b,0x6a,0x8b,0xef,0x36,0x58,0x8a,0x2f,0x69,0x23,0xb4,0xa2, +0xb9,0xa8,0xfe,0x22,0xe8,0x12,0xfd,0xdb,0xf4,0xcd,0x5b,0x8b,0xc6,0x1a,0x44,0xdf, +0x76,0xfa,0x2f,0xc4,0xd6,0xca,0xbd,0x29,0x6d,0x25,0xf7,0x9a,0x2a,0x90,0x7b,0x33, +0x6a,0x8a,0xce,0x4f,0x10,0x69,0xd2,0x7d,0xdb,0xc8,0x5b,0xfe,0x05,0x56,0x13,0x51, +0xb6,0x7e,0x97,0x11,0x1f,0xf8,0x18,0xad,0x14,0xe2,0xf6,0x65,0x73,0x2e,0xe5,0x9a, +0x2a,0x35,0xb8,0x89,0xfe,0xec,0x88,0x7e,0x8d,0x4f,0xdc,0x3d,0x45,0x55,0xca,0x16, +0x8a,0x29,0x33,0x4c,0x05,0xa2,0x93,0x34,0x66,0x80,0x16,0x8a,0x4a,0x33,0x40,0x0b, +0x45,0x14,0x94,0x01,0xf3,0xdf,0xed,0x45,0x77,0xb6,0xde,0x38,0xf3,0xd2,0x3c,0x57, +0xc7,0x5e,0x24,0xbc,0x5b,0x7b,0x39,0x58,0x9c,0x61,0x4d,0x7d,0x53,0xfb,0x54,0x5f, +0x88,0xee,0x4a,0x93,0x8c,0x28,0x02,0xbe,0x1a,0xf8,0x97,0xe2,0x95,0xb6,0xb3,0x78, +0x95,0xf2,0xc4,0x73,0xcd,0x7e,0x79,0x88,0xa6,0xeb,0xe6,0x53,0xf2,0xb1,0xf9,0x1f, +0x13,0xd4,0x73,0xc4,0xaa,0x31,0xdd,0x9e,0xad,0xff,0x00,0x04,0xe8,0xd3,0xe6,0xd6, +0x3f,0x69,0x8f,0x14,0xea,0xe1,0x37,0xda,0x69,0xfe,0x1f,0x92,0x06,0x7c,0xfd,0xd9, +0x25,0xb8,0x8b,0x60,0xfc,0x44,0x4f,0xf9,0x57,0xe9,0x78,0xaf,0x87,0x7f,0xe0,0x96, +0xbe,0x07,0x96,0xcb,0xc1,0x1e,0x34,0xf1,0xa4,0xe0,0x8f,0xed,0xcd,0x42,0x3b,0x3b, +0x70,0xc3,0xac,0x56,0xca,0xd9,0x61,0xf5,0x69,0x98,0x7f,0xc0,0x2b,0xee,0x3a,0xfb, +0xba,0x11,0xe5,0xa6,0x91,0xfa,0x46,0x59,0x43,0xea,0xf8,0x3a,0x74,0xfb,0x20,0xa2, +0x8a,0x2b,0xa0,0xf5,0x02,0x8a,0x28,0xa0,0x02,0x8a,0x28,0xa0,0x02,0x8a,0x28,0xa0, +0x02,0x8a,0x28,0xa0,0x02,0x8a,0x28,0xa0,0x02,0x8a,0x28,0xa0,0x02,0x8a,0x28,0xa0, +0x02,0x8a,0x28,0xa0,0x02,0x8a,0x28,0xa0,0x02,0x93,0x14,0xb4,0x50,0x02,0x62,0x8c, +0x52,0xd1,0x40,0x0d,0x23,0xd2,0x94,0x0a,0x5a,0x28,0x01,0x31,0x46,0xd1,0x4b,0x45, +0x00,0x46,0xd0,0xa3,0x82,0x19,0x15,0x81,0xec,0x45,0x54,0x9b,0x40,0xd3,0x6e,0x46, +0x26,0xd3,0xed,0x65,0x1f,0xed,0xc2,0xa7,0xfa,0x55,0xfa,0x2a,0x5c,0x53,0xdd,0x12, +0xe2,0x9e,0xe8,0xe7,0x6e,0x7e,0x1e,0x78,0x62,0xf3,0xfd,0x76,0x81,0xa7,0x3f,0xfd, +0xbb,0x20,0xfe,0x42,0xb2,0xee,0x7e,0x0b,0xf8,0x26,0xef,0x3e,0x67,0x87,0x2c,0xc6, +0x7f,0xb8,0xa5,0x3f,0x91,0x15,0xdb,0x51,0x59,0xba,0x34,0x9e,0xf1,0x5f,0x71,0x93, +0xa1,0x4a,0x5b,0xc1,0x7d,0xc8,0xf3,0x2b,0xbf,0xd9,0xc7,0xc0,0x37,0x60,0x8f,0xec, +0x51,0x1f,0xba,0x4c,0xff,0x00,0xd4,0x9a,0xc7,0xba,0xfd,0x93,0xfc,0x09,0x70,0x72, +0xb0,0xdd,0xc3,0xec,0x92,0xaf,0xf5,0x53,0x5e,0xcb,0x45,0x64,0xf0,0x94,0x1f,0xd8, +0x46,0x0f,0x03,0x86,0x7b,0xd3,0x5f,0x71,0xe0,0x37,0xbf,0xb1,0xaf,0x84,0x27,0xcf, +0x91,0x77,0x79,0x11,0x3f,0xdf,0xd8,0xf8,0xfd,0x05,0x61,0x5d,0x7e,0xc3,0xba,0x2c, +0xb9,0xf2,0xf5,0xc6,0x5f,0x4d,0xd6,0x80,0xff,0x00,0xec,0xf5,0xf4,0xdd,0x15,0x9b, +0xc0,0xe1,0xdf,0xd9,0xfc,0xcc,0x9e,0x5b,0x84,0x7f,0x63,0xf3,0x3e,0x46,0xd4,0x3f, +0x61,0x38,0x98,0x9f,0xb3,0x6a,0xd6,0x92,0x0f,0xfa,0x69,0x01,0x4f,0xe5,0x9a,0xe7, +0xef,0x3f,0x60,0xcd,0x49,0x89,0xf2,0xee,0xb4,0xb7,0x1d,0xbe,0x77,0x07,0xff,0x00, +0x40,0xaf,0xb6,0x31,0x46,0x2b,0x37,0x97,0x50,0xe9,0x75,0xf3,0x31,0x79,0x46,0x15, +0xf4,0x7f,0x79,0xf0,0x45,0xff,0x00,0xec,0x29,0xe2,0x18,0x81,0x31,0x5b,0x5a,0x4d, +0x8e,0xd1,0xdc,0x00,0x4f,0xe7,0x8a,0xc0,0xba,0xfd,0x89,0xbc,0x5d,0x10,0x24,0x69, +0x12,0x71,0xfd,0xcb,0x84,0x3f,0xc9,0xab,0xf4,0x5b,0x14,0x98,0x35,0x1f,0xd9,0xb4, +0xfa,0x49,0x9c,0xf2,0xc8,0xf0,0xd2,0xea,0xff,0x00,0x0f,0xf2,0x3f,0x33,0x2f,0xbf, +0x64,0xaf,0x18,0x59,0x96,0x1f,0xd8,0xda,0x96,0x47,0xfc,0xf3,0x8d,0x98,0x7e,0x60, +0x56,0x15,0xdf,0xec,0xe7,0xe2,0xcb,0x30,0x49,0xd3,0xf5,0x38,0xc0,0xea,0x5a,0xdd, +0xb1,0xfc,0xab,0xf5,0x47,0x14,0x9b,0x73,0xd6,0xb3,0x79,0x6f,0x6a,0x8c,0xe5,0x97, +0x0e,0xe1,0xe5,0xd7,0xf0,0x47,0xe4,0xbd,0xcf,0xc2,0x3f,0x11,0xd9,0x83,0x93,0x70, +0x9f,0xef,0x46,0x45,0x51,0x93,0xc0,0xfe,0x25,0xb7,0xe9,0x23,0xf1,0xea,0xa6,0xbf, +0x5c,0xde,0xde,0x39,0x06,0x19,0x15,0x87,0xa3,0x0c,0xd5,0x3b,0x8f,0x0f,0x69,0x77, +0x9f,0xeb,0xf4,0xeb,0x49,0xbf,0xdf,0x81,0x5b,0xf9,0x8a,0xcd,0xe5,0xd3,0xe9,0x3f, +0xc0,0xe3,0x9f,0x0b,0xd0,0x97,0x6f,0xbb,0xfe,0x09,0xf9,0x24,0xda,0x1f,0x8a,0x2d, +0xfb,0x96,0xc7,0xd6,0xa3,0x2b,0xe2,0x58,0x3a,0xc5,0xbb,0xe8,0x6b,0xf5,0x7a,0xe3, +0xe1,0xb7,0x85,0x6e,0xb3,0xe6,0xf8,0x7b,0x4d,0x6c,0xf5,0x3f,0x66,0x40,0x7f,0x41, +0x59,0x57,0x5f,0x04,0x7c,0x0f,0x77,0xf7,0xfc,0x3b,0x68,0x3d,0x76,0xee,0x5f,0xe4, +0x6b,0x27,0x96,0xd5,0xee,0x99,0xc7,0x2e,0x14,0xa6,0xf6,0xb7,0xe2,0x7e,0x5a,0xff, +0x00,0x6a,0xf8,0x86,0x1f,0xbd,0x6a,0xc7,0x1e,0x94,0xe1,0xe2,0x9d,0x62,0x2f,0xbf, +0x67,0x27,0xfd,0xf3,0x5f,0xa6,0x37,0x7f,0xb3,0x5f,0x80,0x2e,0xff,0x00,0xe6,0x0c, +0x61,0xff,0x00,0xae,0x73,0x3f,0xf5,0x26,0xb1,0xee,0xbf,0x64,0xbf,0x01,0xdc,0x92, +0x56,0x1b,0xd8,0x7d,0x92,0x65,0xfe,0xaa,0x6b,0x17,0x96,0xd5,0xfe,0x58,0x9c,0xb2, +0xe1,0x3e,0xcb,0xf1,0x7f,0xe4,0x7e,0x74,0x8f,0x1c,0xde,0xc6,0x7e,0x7b,0x59,0x07, +0xe0,0x6a,0x54,0xf8,0x88,0xeb,0xf7,0xe2,0x71,0xf9,0xd7,0xde,0xd7,0xbf,0xb1,0x87, +0x85,0x27,0xcf,0x91,0x7f,0x79,0x0f,0xfb,0xea,0xaf,0xfe,0x15,0x89,0x75,0xfb,0x0e, +0x68,0xf2,0x92,0x63,0xd7,0x18,0x7b,0x35,0xa0,0x3f,0xfb,0x3d,0x61,0x2c,0xb6,0xa7, +0x5a,0x6b,0xef,0x39,0xa5,0xc2,0xd5,0x97,0xc3,0x7f,0xbd,0x1f,0x16,0xc7,0xf1,0x1e, +0x2e,0xe0,0x8a,0xb3,0x1f,0xc4,0x4b,0x66,0xea,0xf5,0xf5,0x5e,0xa1,0xfb,0x08,0x29, +0xcf,0xd9,0xb5,0x6b,0x39,0x07,0x6f,0x36,0x16,0x5f,0xe5,0x9a,0xe7,0xee,0xff,0x00, +0x60,0xbd,0x4c,0x82,0x52,0xe7,0x4a,0x7f,0x6d,0xce,0x3f,0xf6,0x4a,0xc2,0x59,0x6b, +0xeb,0x49,0x9c,0xd2,0xe1,0xcc,0x5c,0x76,0x72,0xfc,0x19,0xf3,0xec,0x7e,0x3d,0xb4, +0x7c,0x66,0x40,0x3e,0xb5,0x66,0x3f,0x1a,0xd9,0xbe,0x3f,0x7a,0xb5,0xea,0xfa,0x87, +0xec,0x2f,0xe2,0x58,0x58,0x88,0xac,0x6d,0xe7,0x03,0xbc,0x57,0x0a,0x07,0xea,0x45, +0x61,0x5e,0x7e,0xc5,0x3e,0x2f,0x81,0x49,0x1a,0x3c,0xa7,0x1f,0xf3,0xce,0x74,0x6f, +0xe4,0xd5,0x83,0xcb,0xa3,0xd6,0x9c,0x97,0xc8,0xe7,0x96,0x49,0x8e,0x8e,0xd2,0x7f, +0xf8,0x09,0xc6,0xc7,0xe2,0xcb,0x47,0xc7,0xef,0x53,0xf3,0xa9,0xd3,0xc4,0x76,0xaf, +0xd2,0x45,0x3f,0x8d,0x5d,0xbc,0xfd,0x93,0x7c,0x61,0x66,0x0b,0x7f,0x62,0xea,0x60, +0x7f,0xb1,0x13,0x37,0xf2,0x15,0x87,0x79,0xfb,0x3b,0xf8,0xb2,0xc7,0xef,0xe9,0xfa, +0x9c,0x5f,0xef,0xdb,0xb0,0xfe,0x95,0xce,0xf0,0x14,0x97,0x46,0xbe,0x47,0x3c,0xb2, +0xec,0x74,0x3e,0xd7,0xe0,0xcd,0x55,0xd6,0xad,0xdb,0xf8,0x87,0xe7,0x52,0x0d,0x4e, +0x06,0xfe,0x31,0x5c,0x6d,0xc7,0xc2,0x9f,0x10,0xda,0x31,0x52,0xd3,0xa1,0x07,0x18, +0x68,0xc8,0xaa,0x72,0x78,0x23,0xc4,0x96,0xfd,0x24,0x63,0x8f,0xf6,0x4d,0x66,0xf0, +0x34,0xba,0x48,0xc1,0xe1,0x71,0xb1,0xec,0xcf,0x41,0x17,0xf0,0xff,0x00,0x7a,0x9e, +0xb7,0x91,0xf6,0x7f,0xd6,0xbc,0xd1,0xb4,0x4f,0x13,0x41,0xdc,0x9f,0x6e,0x69,0xa4, +0x78,0x96,0x0e,0xb1,0x16,0xfc,0x6b,0x37,0x97,0xc5,0xed,0x22,0x7d,0x9e,0x35,0x7d, +0x84,0xfe,0x67,0xa8,0xad,0xe0,0x1d,0x25,0x23,0xf1,0xa9,0x93,0x50,0x95,0x7e,0xed, +0xc3,0x8f,0xa3,0x57,0x93,0xff,0x00,0x6a,0xf8,0x82,0x1f,0xbd,0x6a,0xc7,0x1e,0x94, +0xa3,0xc5,0x3a,0xbc,0x5f,0x7e,0xd2,0x4f,0xfb,0xe6,0xa1,0xe5,0xcf,0xa4,0x90,0x73, +0x62,0xe3,0xbd,0x37,0xf7,0x9e,0xbd,0x1e,0xb5,0x7b,0x11,0xf9,0x2e,0xe4,0x1f,0x47, +0x35,0x65,0x3c,0x55,0xaa,0xc7,0xf7,0x6f,0xa5,0xff,0x00,0xbe,0x8d,0x78,0xe0,0xf1, +0xcd,0xe4,0x7f,0x7e,0xda,0x41,0xff,0x00,0x01,0x35,0x2a,0x7c,0x44,0x61,0xf7,0xa2, +0x71,0x51,0xfd,0x9f,0x55,0x6c,0xff,0x00,0x11,0xac,0x5e,0x26,0x3b,0xc2,0x47,0xb4, +0xc3,0xe3,0xcd,0x72,0x0f,0xbb,0x7d,0x27,0xe2,0x6a,0xec,0x3f,0x14,0x7c,0x43,0x0e, +0x31,0x7a,0xe7,0xea,0x6b,0xc4,0x13,0xe2,0x3c,0x47,0x19,0xdd,0x56,0xa3,0xf8,0x89, +0x6c,0x71,0x97,0x22,0x8f,0xa9,0xe2,0x63,0xb5,0xfe,0xf3,0x45,0x9a,0x57,0x86,0xfc, +0xcb,0xef,0x3d,0xda,0xdf,0xe3,0x4f,0x89,0x20,0xc6,0x2e,0x4f,0xe6,0x6b,0x46,0xdb, +0xe3,0xff,0x00,0x88,0xa0,0xc6,0x64,0x2c,0x7d,0x77,0x57,0x81,0x47,0xe3,0xdb,0x46, +0xff,0x00,0x96,0x95,0x66,0x3f,0x1a,0xda,0x37,0xfc,0xb5,0x5a,0x7c,0x98,0xc8,0x6d, +0x27,0xf7,0x9b,0x47,0x3c,0xad,0x1f,0xb6,0xfe,0xe3,0xe8,0x8b,0x7f,0xda,0x53,0x5f, +0x8b,0x86,0x27,0x1e,0xcd,0x5a,0x96,0xdf,0xb5,0x26,0xab,0x10,0x1b,0xe3,0x63,0xf5, +0x35,0xf3,0x5c,0x7e,0x2d,0xb4,0x7e,0x92,0xaf,0xe7,0x53,0xaf,0x88,0xed,0x5f,0xa3, +0xaf,0xe7,0x56,0xab,0xe3,0xe1,0xb4,0xd9,0xd3,0x1e,0x22,0xac,0xbf,0xe5,0xe1,0xf5, +0x0d,0xb7,0xed,0x59,0x73,0x91,0xe6,0xa1,0xff,0x00,0xbe,0x45,0x6b,0x5b,0x7e,0xd5, +0xb0,0xb6,0x03,0xc2,0x3e,0xa4,0x57,0xc9,0xc9,0xad,0xdb,0xbf,0xf1,0x8f,0xce,0xa5, +0x5d,0x52,0x06,0xfe,0x2a,0xb5,0x98,0x66,0x10,0xfb,0x6f,0xee,0x3a,0xe1,0xc4,0x95, +0x97,0xdb,0x47,0xd8,0x16,0xbf,0xb5,0x26,0x9a,0xc3,0xf7,0xa8,0xbf,0x91,0xad,0x4b, +0x6f,0xda,0x5b,0x44,0x9b,0x19,0x0a,0x3f,0x1a,0xf8,0xb4,0x6a,0x30,0x9e,0x77,0x0a, +0x6b,0xea,0xb0,0x20,0x3f,0x3f,0xeb,0x5b,0x47,0x36,0xc7,0xad,0x2f,0x7f,0x91,0xd4, +0xb8,0x9e,0xac,0x77,0x68,0xfb,0xa2,0xdf,0xf6,0x84,0xf0,0xec,0xa0,0x66,0x50,0x0f, +0xb3,0x0a,0xb7,0x37,0xc7,0x8f,0x0d,0x43,0x6e,0x65,0x7b,0x8c,0x01,0xdb,0x70,0xcd, +0x7e,0x7b,0xdf,0xf8,0xce,0xd6,0xc9,0x09,0x33,0x85,0xc7,0xfb,0x55,0xc0,0x78,0x93, +0xe2,0xcc,0x80,0x34,0x76,0x92,0xb1,0x27,0xbe,0x6b,0xd5,0xa1,0x8f,0xcc,0x2a,0xbd, +0x52,0x17,0xfa,0xd9,0x56,0x4f,0x96,0x9d,0x3e,0x66,0x7b,0xb7,0xed,0x37,0xf1,0xc6, +0xcf,0x5f,0xd5,0xee,0xe4,0xb5,0x93,0x31,0x74,0x8c,0x1e,0xb5,0xf2,0xd7,0x87,0x3c, +0x2b,0xaf,0xfc,0x6d,0xf1,0xe6,0x9f,0xe1,0x8d,0x0a,0x16,0xb8,0xd4,0x35,0x09,0x76, +0x6e,0xfe,0x08,0x63,0xcf,0xcd,0x23,0x9e,0xca,0xa3,0x24,0x9f,0x6f,0x5a,0x93,0xc2, +0xbe,0x13,0xf1,0x57,0xc6,0x6f,0x16,0x41,0xa3,0x68,0x36,0x13,0x6a,0xba,0x95,0xc3, +0x70,0x89,0xf7,0x51,0x7b,0xbb,0xb1,0xe1,0x54,0x77,0x27,0xfa,0x8a,0xfd,0x46,0xfd, +0x97,0x3f,0x65,0xdd,0x1b,0xf6,0x79,0xf0,0xdb,0x39,0x31,0xea,0x5e,0x2b,0xbe,0x41, +0xfd,0xa1,0xa9,0xe3,0x8c,0x75,0xf2,0xa2,0xcf,0x21,0x01,0xfc,0x58,0xf2,0x7b,0x01, +0xe9,0x61,0x70,0xaf,0x99,0xce,0x5b,0xbd,0x5b,0x34,0xcb,0x30,0x15,0x73,0x1c,0x53, +0xc6,0x62,0x3f,0xe0,0x7a,0x23,0xd2,0xfe,0x17,0x7c,0x3e,0xd3,0x7e,0x15,0xf8,0x03, +0x44,0xf0,0xa6,0x92,0x81,0x6c,0x74,0xbb,0x65,0x81,0x5b,0x1c,0xbb,0x75,0x67,0x3e, +0xec,0xc4,0x93,0xf5,0xae,0xaa,0x90,0x0c,0x52,0xd7,0xd0,0x25,0x6d,0x0f,0xd2,0xd2, +0xb2,0xb2,0x0a,0x28,0xa2,0x81,0x85,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14, +0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14, +0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14, +0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14, +0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14, +0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14, +0x51,0x40,0x05,0x14,0x51,0x40,0x09,0x46,0x29,0x68,0xa0,0x04,0xc5,0x18,0xa5,0xa2, +0x80,0x13,0x6d,0x26,0xda,0x75,0x14,0x01,0x13,0xda,0xc3,0x26,0x77,0xc4,0x8d,0x9e, +0xb9,0x50,0x6a,0x8d,0xc7,0x86,0xb4,0x9b,0xa0,0x44,0xda,0x5d,0x9c,0xca,0x7a,0x89, +0x20,0x43,0xfd,0x2b,0x4e,0x8a,0x97,0x18,0xbd,0xd1,0x2e,0x31,0x7b,0xa3,0x98,0xb9, +0xf8,0x65,0xe1,0x3b,0xb1,0xfb,0xdf,0x0e,0xe9,0xa7,0xe9,0x6c,0x8b,0xfc,0x85,0x65, +0xdd,0x7c,0x0e,0xf0,0x35,0xd9,0x26,0x4f,0x0e,0x5a,0x0f,0xf7,0x37,0x27,0xf2,0x22, +0xbb,0xba,0x2b,0x37,0x42,0x93,0xde,0x2b,0xee,0x31,0x78,0x7a,0x32,0xde,0x0b,0xee, +0x47,0x96,0x5d,0xfe,0xcc,0xfe,0x00,0xbb,0x24,0xff,0x00,0x64,0x34,0x24,0xff,0x00, +0xcf,0x39,0x9b,0x8f,0xcc,0x9a,0xc7,0xba,0xfd,0x91,0xfc,0x0b,0x71,0xf7,0x12,0xf6, +0x13,0xfe,0xcc,0xaa,0x7f,0x9a,0xd7,0xb5,0xd1,0x59,0x3c,0x25,0x07,0xf6,0x11,0x8b, +0xc0,0xe1,0x9f,0xfc,0xbb,0x47,0xcf,0x37,0xbf,0xb1,0x77,0x85,0x67,0x27,0xc8,0xd4, +0x2e,0xe1,0x1e,0x8e,0x88,0xff,0x00,0xcb,0x15,0x8b,0x75,0xfb,0x0d,0x69,0x12,0xe7, +0xcb,0xd7,0x58,0x7a,0x6f,0xb4,0x07,0xff,0x00,0x66,0xaf,0xa8,0x28,0xac,0xde,0x07, +0x0e,0xfe,0xcf,0xe6,0x64,0xf2,0xcc,0x2b,0xfb,0x1f,0x8b,0x3e,0x3e,0xbf,0xfd,0x84, +0x1c,0x93,0xf6,0x7d,0x56,0xc6,0x40,0x7f,0xe7,0xac,0x4c,0xbf,0xc8,0x1a,0xc1,0xbd, +0xfd,0x83,0x35,0x65,0xc9,0x8e,0xe7,0x4b,0x97,0xe8,0xee,0x0f,0xea,0xa2,0xbe,0xdf, +0xa4,0x6e,0x95,0x93,0xcb,0xa8,0x74,0xbf,0xde,0x60,0xf2,0x8c,0x2b,0xe8,0xfe,0xf3, +0xe0,0x0b,0xef,0xd8,0x67,0xc4,0xd1,0x93,0xe5,0xe9,0xf0,0x4c,0x3f,0xe9,0x95,0xc2, +0x0f,0xe6,0x45,0x61,0x5e,0x7e,0xc5,0x7e,0x30,0xb7,0x04,0x8d,0x16,0x63,0xff,0x00, +0x5c,0xe7,0x46,0xfe,0x4c,0x6b,0xf4,0x6c,0x75,0xa0,0x75,0xac,0xde,0x5d,0x4f,0xa4, +0x99,0xcf,0x2c,0x8f,0x0c,0xfa,0xbf,0xc3,0xfc,0x8f,0xcc,0x3b,0xcf,0xd9,0x53,0xc5, +0xd6,0x8c,0x41,0xd1,0x35,0x51,0x8f,0xee,0xc0,0xec,0x3f,0x30,0x2b,0x16,0xfb,0xf6, +0x7b,0xf1,0x56,0x9e,0xa5,0xa4,0xb1,0xd4,0xa1,0x03,0xbb,0xc0,0xc3,0xfa,0x57,0xea, +0xb8,0xe9,0x4d,0x3c,0xd4,0x3c,0xbb,0xb4,0xd9,0xcb,0x2e,0x1d,0xc3,0xbe,0xbf,0x82, +0x3f,0x24,0x67,0xf8,0x59,0xaf,0xda,0x9c,0x16,0x99,0x7f,0xde,0x42,0x2a,0xa3,0xf8, +0x2b,0xc4,0x50,0x1e,0x25,0x6f,0xc4,0x1a,0xfd,0x75,0x96,0xd6,0x19,0x57,0xe7,0x89, +0x1f,0xfd,0xe5,0x06,0xb3,0x2f,0x3c,0x37,0xa4,0x5d,0xff,0x00,0xaf,0xd2,0xec,0xa6, +0xff,0x00,0xae,0x96,0xe8,0xdf,0xcc,0x57,0x34,0xf0,0x72,0x8f,0xdb,0xfc,0x3f,0xe0, +0x9e,0x65,0x5e,0x1d,0xc3,0xc7,0xb7,0xdd,0xff,0x00,0x04,0xfc,0x94,0x9b,0x44,0xf1, +0x2c,0x2b,0xc3,0x13,0xf4,0xcd,0x64,0x5d,0xe8,0x9e,0x28,0x94,0x13,0x99,0x31,0xec, +0x09,0xaf,0xd4,0x6f,0x14,0x78,0x37,0x40,0x44,0x98,0xae,0x87,0xa6,0x83,0x8e,0xa2, +0xd2,0x3f,0xf0,0xac,0x0f,0x06,0xf8,0x4b,0x43,0x9e,0xf1,0xd6,0x5d,0x1b,0x4f,0x91, +0x72,0x38,0x7b,0x54,0x23,0xf9,0x57,0x1c,0x63,0x25,0x2b,0x2b,0x7d,0xc7,0x8f,0x2c, +0x97,0x0c,0xa5,0xca,0x92,0xfb,0x8f,0xcc,0x9b,0x2f,0x86,0x9e,0x2d,0xf1,0x2d,0xd8, +0xb7,0xb3,0xd3,0xef,0x75,0x19,0xd8,0xf1,0x15,0xbc,0x4c,0xed,0xcf,0xb0,0x15,0xf4, +0x27,0xc2,0x4f,0xf8,0x27,0x6f,0x8a,0x7c,0x4d,0x3c,0x37,0x7e,0x31,0xb9,0x5f,0x0d, +0xe9,0x99,0x05,0xa0,0x52,0x24,0xba,0x71,0xd7,0x85,0x1f,0x2a,0xfd,0x58,0xe4,0x7f, +0x76,0xbf,0x46,0x74,0xed,0x2e,0xcf,0x4c,0xb7,0x58,0xac,0xed,0x20,0xb4,0x8c,0x0e, +0x12,0x08,0xd5,0x00,0xfc,0x00,0xab,0x8b,0x5e,0xfd,0x1c,0x3d,0xd2,0x94,0xdd,0xcf, +0xa2,0xc0,0xf0,0xed,0x18,0x5a,0x75,0x26,0xe4,0xbb,0x5a,0xc8,0xe2,0x7e,0x16,0xfc, +0x1b,0xf0,0xa7,0xc1,0xcd,0x0c,0x69,0x9e,0x18,0xd2,0xe3,0xb3,0x46,0x03,0xce,0xb8, +0x6f,0x9a,0x79,0xc8,0xef,0x23,0xf5,0x3f,0x4e,0x83,0xb0,0x15,0xdb,0x8e,0x28,0x1d, +0x29,0x6b,0xd0,0x49,0x25,0x64,0x7d,0x8c,0x29,0xc6,0x9c,0x54,0x20,0xac,0x90,0x51, +0x45,0x14,0xcd,0x02,0x8a,0x28,0xa0,0x0f,0xff,0xd9,}; + +static const unsigned int dummy_align__runtime_shtml = 3; +static const unsigned char data__runtime_shtml[] = { +/* /runtime.shtml (15 chars) */ +0x2f,0x72,0x75,0x6e,0x74,0x69,0x6d,0x65,0x2e,0x73,0x68,0x74,0x6d,0x6c,0x00,0x00, + +/* HTTP header */ +/* "HTTP/1.0 200 OK +" (17 bytes) */ +0x48,0x54,0x54,0x50,0x2f,0x31,0x2e,0x30,0x20,0x32,0x30,0x30,0x20,0x4f,0x4b,0x0d, +0x0a, +/* "Server: lwIP/1.3.1 (http://savannah.nongnu.org/projects/lwip) +" (63 bytes) */ +0x53,0x65,0x72,0x76,0x65,0x72,0x3a,0x20,0x6c,0x77,0x49,0x50,0x2f,0x31,0x2e,0x33, +0x2e,0x31,0x20,0x28,0x68,0x74,0x74,0x70,0x3a,0x2f,0x2f,0x73,0x61,0x76,0x61,0x6e, +0x6e,0x61,0x68,0x2e,0x6e,0x6f,0x6e,0x67,0x6e,0x75,0x2e,0x6f,0x72,0x67,0x2f,0x70, +0x72,0x6f,0x6a,0x65,0x63,0x74,0x73,0x2f,0x6c,0x77,0x69,0x70,0x29,0x0d,0x0a, +/* "Content-type: text/html +Expires: Fri, 10 Apr 2008 14:00:00 GMT +Pragma: no-cache + +" (85 bytes) */ +0x43,0x6f,0x6e,0x74,0x65,0x6e,0x74,0x2d,0x74,0x79,0x70,0x65,0x3a,0x20,0x74,0x65, +0x78,0x74,0x2f,0x68,0x74,0x6d,0x6c,0x0d,0x0a,0x45,0x78,0x70,0x69,0x72,0x65,0x73, +0x3a,0x20,0x46,0x72,0x69,0x2c,0x20,0x31,0x30,0x20,0x41,0x70,0x72,0x20,0x32,0x30, +0x30,0x38,0x20,0x31,0x34,0x3a,0x30,0x30,0x3a,0x30,0x30,0x20,0x47,0x4d,0x54,0x0d, +0x0a,0x50,0x72,0x61,0x67,0x6d,0x61,0x3a,0x20,0x6e,0x6f,0x2d,0x63,0x61,0x63,0x68, +0x65,0x0d,0x0a,0x0d,0x0a, +/* raw file data (758 bytes) */ +0x3c,0x21,0x44,0x4f,0x43,0x54,0x59,0x50,0x45,0x20,0x48,0x54,0x4d,0x4c,0x20,0x50, +0x55,0x42,0x4c,0x49,0x43,0x20,0x22,0x2d,0x2f,0x2f,0x57,0x33,0x43,0x2f,0x2f,0x44, +0x54,0x44,0x20,0x48,0x54,0x4d,0x4c,0x20,0x34,0x2e,0x30,0x31,0x20,0x54,0x72,0x61, +0x6e,0x73,0x69,0x74,0x69,0x6f,0x6e,0x61,0x6c,0x2f,0x2f,0x45,0x4e,0x22,0x20,0x22, +0x68,0x74,0x74,0x70,0x3a,0x2f,0x2f,0x77,0x77,0x77,0x2e,0x77,0x33,0x2e,0x6f,0x72, +0x67,0x2f,0x54,0x52,0x2f,0x68,0x74,0x6d,0x6c,0x34,0x2f,0x6c,0x6f,0x6f,0x73,0x65, +0x2e,0x64,0x74,0x64,0x22,0x3e,0x0d,0x0a,0x3c,0x68,0x74,0x6d,0x6c,0x3e,0x0d,0x0a, +0x20,0x20,0x3c,0x68,0x65,0x61,0x64,0x3e,0x0d,0x0a,0x20,0x20,0x20,0x20,0x3c,0x74, +0x69,0x74,0x6c,0x65,0x3e,0x46,0x72,0x65,0x65,0x52,0x54,0x4f,0x53,0x2e,0x6f,0x72, +0x67,0x20,0x6c,0x77,0x49,0x50,0x20,0x57,0x45,0x42,0x20,0x73,0x65,0x72,0x76,0x65, +0x72,0x20,0x64,0x65,0x6d,0x6f,0x3c,0x2f,0x74,0x69,0x74,0x6c,0x65,0x3e,0x0d,0x0a, +0x20,0x20,0x3c,0x2f,0x68,0x65,0x61,0x64,0x3e,0x0d,0x0a,0x20,0x20,0x3c,0x42,0x4f, +0x44,0x59,0x20,0x6f,0x6e,0x4c,0x6f,0x61,0x64,0x3d,0x22,0x77,0x69,0x6e,0x64,0x6f, +0x77,0x2e,0x73,0x65,0x74,0x54,0x69,0x6d,0x65,0x6f,0x75,0x74,0x28,0x26,0x71,0x75, +0x6f,0x74,0x3b,0x6c,0x6f,0x63,0x61,0x74,0x69,0x6f,0x6e,0x2e,0x68,0x72,0x65,0x66, +0x3d,0x27,0x72,0x75,0x6e,0x74,0x69,0x6d,0x65,0x2e,0x73,0x68,0x74,0x6d,0x6c,0x27, +0x26,0x71,0x75,0x6f,0x74,0x3b,0x2c,0x32,0x30,0x30,0x30,0x29,0x22,0x3e,0x0d,0x0a, +0x3c,0x66,0x6f,0x6e,0x74,0x20,0x66,0x61,0x63,0x65,0x3d,0x22,0x61,0x72,0x69,0x61, +0x6c,0x22,0x3e,0x0d,0x0a,0x3c,0x61,0x20,0x68,0x72,0x65,0x66,0x3d,0x22,0x69,0x6e, +0x64,0x65,0x78,0x2e,0x73,0x68,0x74,0x6d,0x6c,0x22,0x3e,0x54,0x61,0x73,0x6b,0x20, +0x53,0x74,0x61,0x74,0x73,0x3c,0x2f,0x61,0x3e,0x20,0x3c,0x62,0x3e,0x7c,0x3c,0x2f, +0x62,0x3e,0x20,0x3c,0x61,0x20,0x68,0x72,0x65,0x66,0x3d,0x22,0x72,0x75,0x6e,0x74, +0x69,0x6d,0x65,0x2e,0x73,0x68,0x74,0x6d,0x6c,0x22,0x3e,0x52,0x75,0x6e,0x20,0x54, +0x69,0x6d,0x65,0x20,0x53,0x74,0x61,0x74,0x73,0x3c,0x2f,0x61,0x3e,0x20,0x3c,0x62, +0x3e,0x7c,0x3c,0x2f,0x62,0x3e,0x20,0x3c,0x61,0x20,0x68,0x72,0x65,0x66,0x3d,0x22, +0x68,0x74,0x74,0x70,0x3a,0x2f,0x2f,0x77,0x77,0x77,0x2e,0x66,0x72,0x65,0x65,0x72, +0x74,0x6f,0x73,0x2e,0x6f,0x72,0x67,0x2f,0x22,0x3e,0x46,0x72,0x65,0x65,0x52,0x54, +0x4f,0x53,0x20,0x48,0x6f,0x6d,0x65,0x70,0x61,0x67,0x65,0x3c,0x2f,0x61,0x3e,0x20, +0x3c,0x62,0x3e,0x7c,0x3c,0x2f,0x62,0x3e,0x20,0x3c,0x61,0x20,0x68,0x72,0x65,0x66, +0x3d,0x22,0x6c,0x6f,0x67,0x6f,0x2e,0x6a,0x70,0x67,0x22,0x3e,0x33,0x37,0x4b,0x20, +0x6a,0x70,0x67,0x3c,0x2f,0x61,0x3e,0x0d,0x0a,0x3c,0x62,0x72,0x3e,0x3c,0x70,0x3e, +0x0d,0x0a,0x3c,0x68,0x72,0x3e,0x0d,0x0a,0x3c,0x62,0x72,0x3e,0x3c,0x70,0x3e,0x0d, +0x0a,0x3c,0x68,0x32,0x3e,0x52,0x75,0x6e,0x2d,0x74,0x69,0x6d,0x65,0x20,0x73,0x74, +0x61,0x74,0x69,0x73,0x74,0x69,0x63,0x73,0x3c,0x2f,0x68,0x32,0x3e,0x0d,0x0a,0x50, +0x61,0x67,0x65,0x20,0x77,0x69,0x6c,0x6c,0x20,0x72,0x65,0x66,0x72,0x65,0x73,0x68, +0x20,0x65,0x76,0x65,0x72,0x79,0x20,0x32,0x20,0x73,0x65,0x63,0x6f,0x6e,0x64,0x73, +0x2e,0x3c,0x70,0x3e,0x0d,0x0a,0x3c,0x66,0x6f,0x6e,0x74,0x20,0x66,0x61,0x63,0x65, +0x3d,0x22,0x63,0x6f,0x75,0x72,0x69,0x65,0x72,0x22,0x3e,0x3c,0x70,0x72,0x65,0x3e, +0x54,0x61,0x73,0x6b,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20, +0x41,0x62,0x73,0x20,0x54,0x69,0x6d,0x65,0x20,0x20,0x20,0x20,0x20,0x20,0x25,0x20, +0x54,0x69,0x6d,0x65,0x3c,0x62,0x72,0x3e,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a, +0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a, +0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a, +0x3c,0x62,0x72,0x3e,0x0d,0x0a,0x3c,0x21,0x2d,0x2d,0x23,0x72,0x75,0x6e,0x5f,0x73, +0x74,0x61,0x74,0x73,0x2d,0x2d,0x3e,0x0d,0x0d,0x0a,0x3c,0x2f,0x70,0x72,0x65,0x3e, +0x3c,0x2f,0x66,0x6f,0x6e,0x74,0x3e,0x0d,0x0a,0x3c,0x2f,0x66,0x6f,0x6e,0x74,0x3e, +0x0d,0x0a,0x3c,0x2f,0x62,0x6f,0x64,0x79,0x3e,0x0d,0x0a,0x3c,0x2f,0x68,0x74,0x6d, +0x6c,0x3e,0x0d,0x0a,0x0d,0x0a,}; + + + +const struct fsdata_file file__404_html[] = { { +file_NULL, +data__404_html, +data__404_html + 12, +sizeof(data__404_html) - 12, +1, +}}; + +const struct fsdata_file file__index_shtml[] = { { +file__404_html, +data__index_shtml, +data__index_shtml + 16, +sizeof(data__index_shtml) - 16, +1, +}}; + +const struct fsdata_file file__logo_jpg[] = { { +file__index_shtml, +data__logo_jpg, +data__logo_jpg + 12, +sizeof(data__logo_jpg) - 12, +1, +}}; + +const struct fsdata_file file__runtime_shtml[] = { { +file__logo_jpg, +data__runtime_shtml, +data__runtime_shtml + 16, +sizeof(data__runtime_shtml) - 16, +1, +}}; + +#define FS_ROOT file__runtime_shtml +#define FS_NUMFILES 4 + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/fsdata.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/fsdata.h new file mode 100644 index 000000000..6f6c557f3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/fsdata.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __FSDATA_H__ +#define __FSDATA_H__ + +#include "lwip/opt.h" +#include "fs.h" + +struct fsdata_file { + const struct fsdata_file *next; + const unsigned char *name; + const unsigned char *data; + int len; + u8_t http_header_included; +#if HTTPD_PRECALCULATED_CHECKSUM + u16_t chksum_count; + const struct fsdata_chksum *chksum; +#endif /* HTTPD_PRECALCULATED_CHECKSUM */ +}; + +#endif /* __FSDATA_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/httpd.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/httpd.c new file mode 100644 index 000000000..6f1132caf --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/httpd.c @@ -0,0 +1,2184 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +/* This httpd supports for a + * rudimentary server-side-include facility which will replace tags of the form + * in any file whose extension is .shtml, .shtm or .ssi with + * strings provided by an include handler whose pointer is provided to the + * module via function http_set_ssi_handler(). + * Additionally, a simple common + * gateway interface (CGI) handling mechanism has been added to allow clients + * to hook functions to particular request URIs. + * + * To enable SSI support, define label LWIP_HTTPD_SSI in lwipopts.h. + * To enable CGI support, define label LWIP_HTTPD_CGI in lwipopts.h. + * + * By default, the server assumes that HTTP headers are already present in + * each file stored in the file system. By defining LWIP_HTTPD_DYNAMIC_HEADERS in + * lwipopts.h, this behavior can be changed such that the server inserts the + * headers automatically based on the extension of the file being served. If + * this mode is used, be careful to ensure that the file system image used + * does not already contain the header information. + * + * File system images without headers can be created using the makefsfile + * tool with the -h command line option. + * + * + * Notes about valid SSI tags + * -------------------------- + * + * The following assumptions are made about tags used in SSI markers: + * + * 1. No tag may contain '-' or whitespace characters within the tag name. + * 2. Whitespace is allowed between the tag leadin "". + * 3. The maximum tag name length is LWIP_HTTPD_MAX_TAG_NAME_LEN, currently 8 characters. + * + * Notes on CGI usage + * ------------------ + * + * The simple CGI support offered here works with GET method requests only + * and can handle up to 16 parameters encoded into the URI. The handler + * function may not write directly to the HTTP output but must return a + * filename that the HTTP server will send to the browser as a response to + * the incoming CGI request. + * + * @todo: + * - don't use mem_malloc() (for SSI/dynamic headers) + * - split too long functions into multiple smaller functions? + * - support more file types? + */ +#include "lwip/debug.h" +#include "lwip/stats.h" +#include "httpd.h" +#include "httpd_structs.h" +#include "lwip/tcp.h" +#include "fs.h" + +#include +#include + +#if LWIP_TCP + +#ifndef HTTPD_DEBUG +#define HTTPD_DEBUG LWIP_DBG_OFF +#endif + +/** Set this to 1 and add the next line to lwippools.h to use a memp pool + * for allocating struct http_state instead of the heap: + * + * LWIP_MEMPOOL(HTTPD_STATE, 20, 100, "HTTPD_STATE") + */ +#ifndef HTTPD_USE_MEM_POOL +#define HTTPD_USE_MEM_POOL 0 +#endif + +/** The server port for HTTPD to use */ +#ifndef HTTPD_SERVER_PORT +#define HTTPD_SERVER_PORT 80 +#endif + +/** Maximum retries before the connection is aborted/closed. + * - number of times pcb->poll is called -> default is 4*500ms = 2s; + * - reset when pcb->sent is called + */ +#ifndef HTTPD_MAX_RETRIES +#define HTTPD_MAX_RETRIES 4 +#endif + +/** The poll delay is X*500ms */ +#ifndef HTTPD_POLL_INTERVAL +#define HTTPD_POLL_INTERVAL 4 +#endif + +/** Priority for tcp pcbs created by HTTPD (very low by default). + * Lower priorities get killed first when running out of memroy. + */ +#ifndef HTTPD_TCP_PRIO +#define HTTPD_TCP_PRIO TCP_PRIO_MIN +#endif + +/** Set this to 1 to enabled timing each file sent */ +#ifndef LWIP_HTTPD_TIMING +#define LWIP_HTTPD_TIMING 0 +#endif +#ifndef HTTPD_DEBUG_TIMING +#define HTTPD_DEBUG_TIMING LWIP_DBG_OFF +#endif + +/** Set this to 1 on platforms where strnstr is not available */ +#ifndef LWIP_HTTPD_STRNSTR_PRIVATE +#define LWIP_HTTPD_STRNSTR_PRIVATE 1 +#endif + +/** Set this to one to show error pages when parsing a request fails instead + of simply closing the connection. */ +#ifndef LWIP_HTTPD_SUPPORT_EXTSTATUS +#define LWIP_HTTPD_SUPPORT_EXTSTATUS 0 +#endif + +/** Set this to 0 to drop support for HTTP/0.9 clients (to save some bytes) */ +#ifndef LWIP_HTTPD_SUPPORT_V09 +#define LWIP_HTTPD_SUPPORT_V09 1 +#endif + +/** Set this to 1 to support HTTP request coming in in multiple packets/pbufs */ +#ifndef LWIP_HTTPD_SUPPORT_REQUESTLIST +#define LWIP_HTTPD_SUPPORT_REQUESTLIST 0 +#endif + +#if LWIP_HTTPD_SUPPORT_REQUESTLIST +/** Number of rx pbufs to enqueue to parse an incoming request (up to the first + newline) */ +#ifndef LWIP_HTTPD_REQ_QUEUELEN +#define LWIP_HTTPD_REQ_QUEUELEN 10 +#endif + +/** Number of (TCP payload-) bytes (in pbufs) to enqueue to parse and incoming + request (up to the first double-newline) */ +#ifndef LWIP_HTTPD_REQ_BUFSIZE +#define LWIP_HTTPD_REQ_BUFSIZE LWIP_HTTPD_MAX_REQ_LENGTH +#endif + +/** Defines the maximum length of a HTTP request line (up to the first CRLF, + copied from pbuf into this a global buffer when pbuf- or packet-queues + are received - otherwise the input pbuf is used directly) */ +#ifndef LWIP_HTTPD_MAX_REQ_LENGTH +#define LWIP_HTTPD_MAX_REQ_LENGTH 1023 +#endif +#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */ + +/** Maximum length of the filename to send as response to a POST request, + * filled in by the application when a POST is finished. + */ +#ifndef LWIP_HTTPD_POST_MAX_RESPONSE_URI_LEN +#define LWIP_HTTPD_POST_MAX_RESPONSE_URI_LEN 63 +#endif + +/** Set this to 0 to not send the SSI tag (default is on, so the tag will + * be sent in the HTML page */ +#ifndef LWIP_HTTPD_SSI_INCLUDE_TAG +#define LWIP_HTTPD_SSI_INCLUDE_TAG 1 +#endif + +/** Set this to 1 to call tcp_abort when tcp_close fails with memory error. + * This can be used to prevent consuming all memory in situations where the + * HTTP server has low priority compared to other communication. */ +#ifndef LWIP_HTTPD_ABORT_ON_CLOSE_MEM_ERROR +#define LWIP_HTTPD_ABORT_ON_CLOSE_MEM_ERROR 0 +#endif + +#ifndef true +#define true ((u8_t)1) +#endif + +#ifndef false +#define false ((u8_t)0) +#endif + +/** Minimum length for a valid HTTP/0.9 request: "GET /\r\n" -> 7 bytes */ +#define MIN_REQ_LEN 7 + +#define CRLF "\r\n" + +/** These defines check whether tcp_write has to copy data or not */ + +/** This was TI's check whether to let TCP copy data or not +#define HTTP_IS_DATA_VOLATILE(hs) ((hs->file < (char *)0x20000000) ? 0 : TCP_WRITE_FLAG_COPY)*/ +#ifndef HTTP_IS_DATA_VOLATILE +#if LWIP_HTTPD_SSI +/* Copy for SSI files, no copy for non-SSI files */ +#define HTTP_IS_DATA_VOLATILE(hs) ((hs)->tag_check ? TCP_WRITE_FLAG_COPY : 0) +#else /* LWIP_HTTPD_SSI */ +/** Default: don't copy if the data is sent from file-system directly */ +#define HTTP_IS_DATA_VOLATILE(hs) (((hs->file != NULL) && (hs->handle != NULL) && (hs->file == \ + (char*)hs->handle->data + hs->handle->len - hs->left)) \ + ? 0 : TCP_WRITE_FLAG_COPY) +#endif /* LWIP_HTTPD_SSI */ +#endif + +/** Default: headers are sent from ROM */ +#ifndef HTTP_IS_HDR_VOLATILE +#define HTTP_IS_HDR_VOLATILE(hs, ptr) 0 +#endif + +#if LWIP_HTTPD_SSI +/** Default: Tags are sent from struct http_state and are therefore volatile */ +#ifndef HTTP_IS_TAG_VOLATILE +#define HTTP_IS_TAG_VOLATILE(ptr) TCP_WRITE_FLAG_COPY +#endif +#endif /* LWIP_HTTPD_SSI */ + +typedef struct +{ + const char *name; + u8_t shtml; +} default_filename; + +const default_filename g_psDefaultFilenames[] = { + {"/index.shtml", true }, + {"/index.ssi", true }, + {"/index.shtm", true }, + {"/index.html", false }, + {"/index.htm", false } +}; + +#define NUM_DEFAULT_FILENAMES (sizeof(g_psDefaultFilenames) / \ + sizeof(default_filename)) + +#if LWIP_HTTPD_SUPPORT_REQUESTLIST +/** HTTP request is copied here from pbufs for simple parsing */ +static char httpd_req_buf[LWIP_HTTPD_MAX_REQ_LENGTH+1]; +#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */ + +#if LWIP_HTTPD_SUPPORT_POST +/** Filename for response file to send when POST is finished */ +static char http_post_response_filename[LWIP_HTTPD_POST_MAX_RESPONSE_URI_LEN+1]; +#endif /* LWIP_HTTPD_SUPPORT_POST */ + +#if LWIP_HTTPD_DYNAMIC_HEADERS +/* The number of individual strings that comprise the headers sent before each + * requested file. + */ +#define NUM_FILE_HDR_STRINGS 3 +#endif /* LWIP_HTTPD_DYNAMIC_HEADERS */ + +#if LWIP_HTTPD_SSI + +#define HTTPD_LAST_TAG_PART 0xFFFF + +const char * const g_pcSSIExtensions[] = { + ".shtml", ".shtm", ".ssi", ".xml" +}; + +#define NUM_SHTML_EXTENSIONS (sizeof(g_pcSSIExtensions) / sizeof(const char *)) + +enum tag_check_state { + TAG_NONE, /* Not processing an SSI tag */ + TAG_LEADIN, /* Tag lead in "" being processed */ + TAG_SENDING /* Sending tag replacement string */ +}; +#endif /* LWIP_HTTPD_SSI */ + +struct http_state { + struct fs_file *handle; + char *file; /* Pointer to first unsent byte in buf. */ + +#if LWIP_HTTPD_SUPPORT_REQUESTLIST + struct pbuf *req; +#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */ + +#if LWIP_HTTPD_SSI || LWIP_HTTPD_DYNAMIC_HEADERS + char *buf; /* File read buffer. */ + int buf_len; /* Size of file read buffer, buf. */ +#endif /* LWIP_HTTPD_SSI || LWIP_HTTPD_DYNAMIC_HEADERS */ + u32_t left; /* Number of unsent bytes in buf. */ + u8_t retries; +#if LWIP_HTTPD_SSI + const char *parsed; /* Pointer to the first unparsed byte in buf. */ +#if !LWIP_HTTPD_SSI_INCLUDE_TAG + const char *tag_started;/* Poitner to the first opening '<' of the tag. */ +#endif /* !LWIP_HTTPD_SSI_INCLUDE_TAG */ + const char *tag_end; /* Pointer to char after the closing '>' of the tag. */ + u32_t parse_left; /* Number of unparsed bytes in buf. */ + u16_t tag_index; /* Counter used by tag parsing state machine */ + u16_t tag_insert_len; /* Length of insert in string tag_insert */ +#if LWIP_HTTPD_SSI_MULTIPART + u16_t tag_part; /* Counter passed to and changed by tag insertion function to insert multiple times */ +#endif /* LWIP_HTTPD_SSI_MULTIPART */ + u8_t tag_check; /* true if we are processing a .shtml file else false */ + u8_t tag_name_len; /* Length of the tag name in string tag_name */ + char tag_name[LWIP_HTTPD_MAX_TAG_NAME_LEN + 1]; /* Last tag name extracted */ + char tag_insert[LWIP_HTTPD_MAX_TAG_INSERT_LEN + 1]; /* Insert string for tag_name */ + enum tag_check_state tag_state; /* State of the tag processor */ +#endif /* LWIP_HTTPD_SSI */ +#if LWIP_HTTPD_CGI + char *params[LWIP_HTTPD_MAX_CGI_PARAMETERS]; /* Params extracted from the request URI */ + char *param_vals[LWIP_HTTPD_MAX_CGI_PARAMETERS]; /* Values for each extracted param */ +#endif /* LWIP_HTTPD_CGI */ +#if LWIP_HTTPD_DYNAMIC_HEADERS + const char *hdrs[NUM_FILE_HDR_STRINGS]; /* HTTP headers to be sent. */ + u16_t hdr_pos; /* The position of the first unsent header byte in the + current string */ + u16_t hdr_index; /* The index of the hdr string currently being sent. */ +#endif /* LWIP_HTTPD_DYNAMIC_HEADERS */ +#if LWIP_HTTPD_TIMING + u32_t time_started; +#endif /* LWIP_HTTPD_TIMING */ +#if LWIP_HTTPD_SUPPORT_POST + u32_t post_content_len_left; +#if LWIP_HTTPD_POST_MANUAL_WND + u32_t unrecved_bytes; + struct tcp_pcb *pcb; + u8_t no_auto_wnd; +#endif /* LWIP_HTTPD_POST_MANUAL_WND */ +#endif /* LWIP_HTTPD_SUPPORT_POST*/ +}; + +static err_t http_find_file(struct http_state *hs, const char *uri, int is_09); +static err_t http_init_file(struct http_state *hs, struct fs_file *file, int is_09, const char *uri); +static err_t http_poll(void *arg, struct tcp_pcb *pcb); + +#if LWIP_HTTPD_SSI +/* SSI insert handler function pointer. */ +tSSIHandler g_pfnSSIHandler = NULL; +int g_iNumTags = 0; +const char **g_ppcTags = NULL; + +#define LEN_TAG_LEAD_IN 5 +const char * const g_pcTagLeadIn = ""; +#endif /* LWIP_HTTPD_SSI */ + +#if LWIP_HTTPD_CGI +/* CGI handler information */ +const tCGI *g_pCGIs; +int g_iNumCGIs; +#endif /* LWIP_HTTPD_CGI */ + +#if LWIP_HTTPD_STRNSTR_PRIVATE +/** Like strstr but does not need 'buffer' to be NULL-terminated */ +static char* +strnstr(const char* buffer, const char* token, size_t n) +{ + const char* p; + int tokenlen = (int)strlen(token); + if (tokenlen == 0) { + return (char *)buffer; + } + for (p = buffer; *p && (p + tokenlen <= buffer + n); p++) { + if ((*p == *token) && (strncmp(p, token, tokenlen) == 0)) { + return (char *)p; + } + } + return NULL; +} +#endif /* LWIP_HTTPD_STRNSTR_PRIVATE */ + +/** Allocate a struct http_state. */ +static struct http_state* +http_state_alloc(void) +{ + struct http_state *ret; +#if HTTPD_USE_MEM_POOL + ret = (struct http_state *)memp_malloc(MEMP_HTTPD_STATE); +#else /* HTTPD_USE_MEM_POOL */ + ret = (struct http_state *)mem_malloc(sizeof(struct http_state)); +#endif /* HTTPD_USE_MEM_POOL */ + if (ret != NULL) { + /* Initialize the structure. */ + memset(ret, 0, sizeof(struct http_state)); +#if LWIP_HTTPD_DYNAMIC_HEADERS + /* Indicate that the headers are not yet valid */ + ret->hdr_index = NUM_FILE_HDR_STRINGS; +#endif /* LWIP_HTTPD_DYNAMIC_HEADERS */ + } + return ret; +} + +/** Free a struct http_state. + * Also frees the file data if dynamic. + */ +static void +http_state_free(struct http_state *hs) +{ + if (hs != NULL) { + if(hs->handle) { +#if LWIP_HTTPD_TIMING + u32_t ms_needed = sys_now() - hs->time_started; + u32_t needed = LWIP_MAX(1, (ms_needed/100)); + LWIP_DEBUGF(HTTPD_DEBUG_TIMING, ("httpd: needed %"U32_F" ms to send file of %d bytes -> %"U32_F" bytes/sec\n", + ms_needed, hs->handle->len, ((((u32_t)hs->handle->len) * 10) / needed))); +#endif /* LWIP_HTTPD_TIMING */ + fs_close(hs->handle); + hs->handle = NULL; + } +#if LWIP_HTTPD_SSI || LWIP_HTTPD_DYNAMIC_HEADERS + if (hs->buf != NULL) { + mem_free(hs->buf); + hs->buf = NULL; + } +#endif /* LWIP_HTTPD_SSI || LWIP_HTTPD_DYNAMIC_HEADERS */ +#if HTTPD_USE_MEM_POOL + memp_free(MEMP_HTTPD_STATE, hs); +#else /* HTTPD_USE_MEM_POOL */ + mem_free(hs); +#endif /* HTTPD_USE_MEM_POOL */ + } +} + +/** Call tcp_write() in a loop trying smaller and smaller length + * + * @param pcb tcp_pcb to send + * @param ptr Data to send + * @param length Length of data to send (in/out: on return, contains the + * amount of data sent) + * @param apiflags directly passed to tcp_write + * @return the return value of tcp_write + */ +static err_t +http_write(struct tcp_pcb *pcb, const void* ptr, u16_t *length, u8_t apiflags) +{ + u16_t len; + err_t err; + LWIP_ASSERT("length != NULL", length != NULL); + len = *length; + do { + LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("Trying go send %d bytes\n", len)); + err = tcp_write(pcb, ptr, len, apiflags); + if (err == ERR_MEM) { + if ((tcp_sndbuf(pcb) == 0) || + (tcp_sndqueuelen(pcb) >= TCP_SND_QUEUELEN)) { + /* no need to try smaller sizes */ + len = 1; + } else { + len /= 2; + } + LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, + ("Send failed, trying less (%d bytes)\n", len)); + } + } while ((err == ERR_MEM) && (len > 1)); + + if (err == ERR_OK) { + LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("Sent %d bytes\n", len)); + } else { + LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("Send failed with err %d (\"%s\")\n", err, lwip_strerr(err))); + } + + *length = len; + return err; +} + +/** + * The connection shall be actively closed. + * Reset the sent- and recv-callbacks. + * + * @param pcb the tcp pcb to reset callbacks + * @param hs connection state to free + */ +static err_t +http_close_conn(struct tcp_pcb *pcb, struct http_state *hs) +{ + err_t err; + LWIP_DEBUGF(HTTPD_DEBUG, ("Closing connection %p\n", (void*)pcb)); + +#if LWIP_HTTPD_SUPPORT_POST + if (hs != NULL) { + if ((hs->post_content_len_left != 0) +#if LWIP_HTTPD_POST_MANUAL_WND + || ((hs->no_auto_wnd != 0) && (hs->unrecved_bytes != 0)) +#endif /* LWIP_HTTPD_POST_MANUAL_WND */ + ) { + /* make sure the post code knows that the connection is closed */ + http_post_response_filename[0] = 0; + httpd_post_finished(hs, http_post_response_filename, LWIP_HTTPD_POST_MAX_RESPONSE_URI_LEN); + } + } +#endif /* LWIP_HTTPD_SUPPORT_POST*/ + + + tcp_arg(pcb, NULL); + tcp_recv(pcb, NULL); + tcp_err(pcb, NULL); + tcp_poll(pcb, NULL, 0); + tcp_sent(pcb, NULL); + if(hs != NULL) { + http_state_free(hs); + } + + err = tcp_close(pcb); + if (err != ERR_OK) { + LWIP_DEBUGF(HTTPD_DEBUG, ("Error %d closing %p\n", err, (void*)pcb)); + /* error closing, try again later in poll */ + tcp_poll(pcb, http_poll, HTTPD_POLL_INTERVAL); + } + return err; +} +#if LWIP_HTTPD_CGI +/** + * Extract URI parameters from the parameter-part of an URI in the form + * "test.cgi?x=y" @todo: better explanation! + * Pointers to the parameters are stored in hs->param_vals. + * + * @param hs http connection state + * @param params pointer to the NULL-terminated parameter string from the URI + * @return number of parameters extracted + */ +static int +extract_uri_parameters(struct http_state *hs, char *params) +{ + char *pair; + char *equals; + int loop; + + /* If we have no parameters at all, return immediately. */ + if(!params || (params[0] == '\0')) { + return(0); + } + + /* Get a pointer to our first parameter */ + pair = params; + + /* Parse up to LWIP_HTTPD_MAX_CGI_PARAMETERS from the passed string and ignore the + * remainder (if any) */ + for(loop = 0; (loop < LWIP_HTTPD_MAX_CGI_PARAMETERS) && pair; loop++) { + + /* Save the name of the parameter */ + hs->params[loop] = pair; + + /* Remember the start of this name=value pair */ + equals = pair; + + /* Find the start of the next name=value pair and replace the delimiter + * with a 0 to terminate the previous pair string. */ + pair = strchr(pair, '&'); + if(pair) { + *pair = '\0'; + pair++; + } else { + /* We didn't find a new parameter so find the end of the URI and + * replace the space with a '\0' */ + pair = strchr(equals, ' '); + if(pair) { + *pair = '\0'; + } + + /* Revert to NULL so that we exit the loop as expected. */ + pair = NULL; + } + + /* Now find the '=' in the previous pair, replace it with '\0' and save + * the parameter value string. */ + equals = strchr(equals, '='); + if(equals) { + *equals = '\0'; + hs->param_vals[loop] = equals + 1; + } else { + hs->param_vals[loop] = NULL; + } + } + + return loop; +} +#endif /* LWIP_HTTPD_CGI */ + +#if LWIP_HTTPD_SSI +/** + * Insert a tag (found in an shtml in the form of "" into the file. + * The tag's name is stored in hs->tag_name (NULL-terminated), the replacement + * should be written to hs->tag_insert (up to a length of LWIP_HTTPD_MAX_TAG_INSERT_LEN). + * The amount of data written is stored to hs->tag_insert_len. + * + * @todo: return tag_insert_len - maybe it can be removed from struct http_state? + * + * @param hs http connection state + */ +static void +get_tag_insert(struct http_state *hs) +{ + int loop; + size_t len; +#if LWIP_HTTPD_SSI_MULTIPART + u16_t current_tag_part = hs->tag_part; + hs->tag_part = HTTPD_LAST_TAG_PART; +#endif /* LWIP_HTTPD_SSI_MULTIPART */ + + if(g_pfnSSIHandler && g_ppcTags && g_iNumTags) { + + /* Find this tag in the list we have been provided. */ + for(loop = 0; loop < g_iNumTags; loop++) { + if(strcmp(hs->tag_name, g_ppcTags[loop]) == 0) { + hs->tag_insert_len = g_pfnSSIHandler(loop, hs->tag_insert, + LWIP_HTTPD_MAX_TAG_INSERT_LEN +#if LWIP_HTTPD_SSI_MULTIPART + , current_tag_part, &hs->tag_part +#endif /* LWIP_HTTPD_SSI_MULTIPART */ +#if LWIP_HTTPD_FILE_STATE + , hs->handle->state +#endif /* LWIP_HTTPD_FILE_STATE */ + ); + return; + } + } + } + + /* If we drop out, we were asked to serve a page which contains tags that + * we don't have a handler for. Merely echo back the tags with an error + * marker. */ +#define UNKNOWN_TAG1_TEXT "***UNKNOWN TAG " +#define UNKNOWN_TAG1_LEN 18 +#define UNKNOWN_TAG2_TEXT "***" +#define UNKNOWN_TAG2_LEN 7 + len = LWIP_MIN(strlen(hs->tag_name), + LWIP_HTTPD_MAX_TAG_INSERT_LEN - (UNKNOWN_TAG1_LEN + UNKNOWN_TAG2_LEN)); + MEMCPY(hs->tag_insert, UNKNOWN_TAG1_TEXT, UNKNOWN_TAG1_LEN); + MEMCPY(&hs->tag_insert[UNKNOWN_TAG1_LEN], hs->tag_name, len); + MEMCPY(&hs->tag_insert[UNKNOWN_TAG1_LEN + len], UNKNOWN_TAG2_TEXT, UNKNOWN_TAG2_LEN); + hs->tag_insert[UNKNOWN_TAG1_LEN + len + UNKNOWN_TAG2_LEN] = 0; + + len = strlen(hs->tag_insert); + LWIP_ASSERT("len <= 0xffff", len <= 0xffff); + hs->tag_insert_len = (u16_t)len; +} +#endif /* LWIP_HTTPD_SSI */ + +#if LWIP_HTTPD_DYNAMIC_HEADERS +/** + * Generate the relevant HTTP headers for the given filename and write + * them into the supplied buffer. + */ +static void +get_http_headers(struct http_state *pState, char *pszURI) +{ + unsigned int iLoop; + char *pszWork; + char *pszExt; + char *pszVars; + + /* Ensure that we initialize the loop counter. */ + iLoop = 0; + + /* In all cases, the second header we send is the server identification + so set it here. */ + pState->hdrs[1] = g_psHTTPHeaderStrings[HTTP_HDR_SERVER]; + + /* Is this a normal file or the special case we use to send back the + default "404: Page not found" response? */ + if (pszURI == NULL) { + pState->hdrs[0] = g_psHTTPHeaderStrings[HTTP_HDR_NOT_FOUND]; + pState->hdrs[2] = g_psHTTPHeaderStrings[DEFAULT_404_HTML]; + + /* Set up to send the first header string. */ + pState->hdr_index = 0; + pState->hdr_pos = 0; + return; + } else { + /* We are dealing with a particular filename. Look for one other + special case. We assume that any filename with "404" in it must be + indicative of a 404 server error whereas all other files require + the 200 OK header. */ + if (strstr(pszURI, "404")) { + pState->hdrs[0] = g_psHTTPHeaderStrings[HTTP_HDR_NOT_FOUND]; + } else if (strstr(pszURI, "400")) { + pState->hdrs[0] = g_psHTTPHeaderStrings[HTTP_HDR_BAD_REQUEST]; + } else if (strstr(pszURI, "501")) { + pState->hdrs[0] = g_psHTTPHeaderStrings[HTTP_HDR_NOT_IMPL]; + } else { + pState->hdrs[0] = g_psHTTPHeaderStrings[HTTP_HDR_OK]; + } + + /* Determine if the URI has any variables and, if so, temporarily remove + them. */ + pszVars = strchr(pszURI, '?'); + if(pszVars) { + *pszVars = '\0'; + } + + /* Get a pointer to the file extension. We find this by looking for the + last occurrence of "." in the filename passed. */ + pszExt = NULL; + pszWork = strchr(pszURI, '.'); + while(pszWork) { + pszExt = pszWork + 1; + pszWork = strchr(pszExt, '.'); + } + + /* Now determine the content type and add the relevant header for that. */ + for(iLoop = 0; (iLoop < NUM_HTTP_HEADERS) && pszExt; iLoop++) { + /* Have we found a matching extension? */ + if(!strcmp(g_psHTTPHeaders[iLoop].extension, pszExt)) { + pState->hdrs[2] = + g_psHTTPHeaderStrings[g_psHTTPHeaders[iLoop].headerIndex]; + break; + } + } + + /* Reinstate the parameter marker if there was one in the original URI. */ + if(pszVars) { + *pszVars = '?'; + } + } + + /* Does the URL passed have any file extension? If not, we assume it + is a special-case URL used for control state notification and we do + not send any HTTP headers with the response. */ + if(!pszExt) { + /* Force the header index to a value indicating that all headers + have already been sent. */ + pState->hdr_index = NUM_FILE_HDR_STRINGS; + } else { + /* Did we find a matching extension? */ + if(iLoop == NUM_HTTP_HEADERS) { + /* No - use the default, plain text file type. */ + pState->hdrs[2] = g_psHTTPHeaderStrings[HTTP_HDR_DEFAULT_TYPE]; + } + + /* Set up to send the first header string. */ + pState->hdr_index = 0; + pState->hdr_pos = 0; + } +} +#endif /* LWIP_HTTPD_DYNAMIC_HEADERS */ + +/** + * Try to send more data on this pcb. + * + * @param pcb the pcb to send data + * @param hs connection state + */ +static u8_t +http_send_data(struct tcp_pcb *pcb, struct http_state *hs) +{ + err_t err; + u16_t len; + u16_t mss; + u8_t data_to_send = false; +#if LWIP_HTTPD_DYNAMIC_HEADERS + u16_t hdrlen, sendlen; +#endif /* LWIP_HTTPD_DYNAMIC_HEADERS */ + + LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("http_send_data: pcb=%p hs=%p left=%d\n", (void*)pcb, + (void*)hs, hs != NULL ? hs->left : 0)); + +#if LWIP_HTTPD_SUPPORT_POST && LWIP_HTTPD_POST_MANUAL_WND + if (hs->unrecved_bytes != 0) { + return 0; + } +#endif /* LWIP_HTTPD_SUPPORT_POST && LWIP_HTTPD_POST_MANUAL_WND */ + +#if LWIP_HTTPD_DYNAMIC_HEADERS + /* If we were passed a NULL state structure pointer, ignore the call. */ + if (hs == NULL) { + return 0; + } + + /* Assume no error until we find otherwise */ + err = ERR_OK; + + /* Do we have any more header data to send for this file? */ + if(hs->hdr_index < NUM_FILE_HDR_STRINGS) { + /* How much data can we send? */ + len = tcp_sndbuf(pcb); + sendlen = len; + + while(len && (hs->hdr_index < NUM_FILE_HDR_STRINGS) && sendlen) { + const void *ptr; + u16_t old_sendlen; + /* How much do we have to send from the current header? */ + hdrlen = (u16_t)strlen(hs->hdrs[hs->hdr_index]); + + /* How much of this can we send? */ + sendlen = (len < (hdrlen - hs->hdr_pos)) ? len : (hdrlen - hs->hdr_pos); + + /* Send this amount of data or as much as we can given memory + * constraints. */ + ptr = (const void *)(hs->hdrs[hs->hdr_index] + hs->hdr_pos); + old_sendlen = sendlen; + err = http_write(pcb, ptr, &sendlen, HTTP_IS_HDR_VOLATILE(hs, ptr)); + if ((err == ERR_OK) && (old_sendlen != sendlen)) { + /* Remember that we added some more data to be transmitted. */ + data_to_send = true; + } else if (err != ERR_OK) { + /* special case: http_write does not try to send 1 byte */ + sendlen = 0; + } + + /* Fix up the header position for the next time round. */ + hs->hdr_pos += sendlen; + len -= sendlen; + + /* Have we finished sending this string? */ + if(hs->hdr_pos == hdrlen) { + /* Yes - move on to the next one */ + hs->hdr_index++; + hs->hdr_pos = 0; + } + } + + /* If we get here and there are still header bytes to send, we send + * the header information we just wrote immediately. If there are no + * more headers to send, but we do have file data to send, drop through + * to try to send some file data too. */ + if((hs->hdr_index < NUM_FILE_HDR_STRINGS) || !hs->file) { + LWIP_DEBUGF(HTTPD_DEBUG, ("tcp_output\n")); + return 1; + } + } +#else /* LWIP_HTTPD_DYNAMIC_HEADERS */ + /* Assume no error until we find otherwise */ + err = ERR_OK; +#endif /* LWIP_HTTPD_DYNAMIC_HEADERS */ + + /* Have we run out of file data to send? If so, we need to read the next + * block from the file. */ + if (hs->left == 0) { +#if LWIP_HTTPD_SSI || LWIP_HTTPD_DYNAMIC_HEADERS + int count; +#endif /* LWIP_HTTPD_SSI || LWIP_HTTPD_DYNAMIC_HEADERS */ + + /* Do we have a valid file handle? */ + if (hs->handle == NULL) { + /* No - close the connection. */ + http_close_conn(pcb, hs); + return 0; + } + if (fs_bytes_left(hs->handle) <= 0) { + /* We reached the end of the file so this request is done. + * @todo: don't close here for HTTP/1.1? */ + LWIP_DEBUGF(HTTPD_DEBUG, ("End of file.\n")); + http_close_conn(pcb, hs); + return 0; + } +#if LWIP_HTTPD_SSI || LWIP_HTTPD_DYNAMIC_HEADERS + /* Do we already have a send buffer allocated? */ + if(hs->buf) { + /* Yes - get the length of the buffer */ + count = hs->buf_len; + } else { + /* We don't have a send buffer so allocate one up to 2mss bytes long. */ + count = 2 * tcp_mss(pcb); + do { + hs->buf = (char*)mem_malloc((mem_size_t)count); + if (hs->buf != NULL) { + hs->buf_len = count; + break; + } + count = count / 2; + } while (count > 100); + + /* Did we get a send buffer? If not, return immediately. */ + if (hs->buf == NULL) { + LWIP_DEBUGF(HTTPD_DEBUG, ("No buff\n")); + return 0; + } + } + + /* Read a block of data from the file. */ + LWIP_DEBUGF(HTTPD_DEBUG, ("Trying to read %d bytes.\n", count)); + + count = fs_read(hs->handle, hs->buf, count); + if(count < 0) { + /* We reached the end of the file so this request is done. + * @todo: don't close here for HTTP/1.1? */ + LWIP_DEBUGF(HTTPD_DEBUG, ("End of file.\n")); + http_close_conn(pcb, hs); + return 1; + } + + /* Set up to send the block of data we just read */ + LWIP_DEBUGF(HTTPD_DEBUG, ("Read %d bytes.\n", count)); + hs->left = count; + hs->file = hs->buf; +#if LWIP_HTTPD_SSI + hs->parse_left = count; + hs->parsed = hs->buf; +#endif /* LWIP_HTTPD_SSI */ +#else /* LWIP_HTTPD_SSI || LWIP_HTTPD_DYNAMIC_HEADERS */ + LWIP_ASSERT("SSI and DYNAMIC_HEADERS turned off but eof not reached", 0); +#endif /* LWIP_HTTPD_SSI || LWIP_HTTPD_DYNAMIC_HEADERS */ + } + +#if LWIP_HTTPD_SSI + if(!hs->tag_check) { +#endif /* LWIP_HTTPD_SSI */ + /* We are not processing an SHTML file so no tag checking is necessary. + * Just send the data as we received it from the file. */ + + /* We cannot send more data than space available in the send + buffer. */ + if (tcp_sndbuf(pcb) < hs->left) { + len = tcp_sndbuf(pcb); + } else { + len = (u16_t)hs->left; + LWIP_ASSERT("hs->left did not fit into u16_t!", (len == hs->left)); + } + mss = tcp_mss(pcb); + if(len > (2 * mss)) { + len = 2 * mss; + } + + err = http_write(pcb, hs->file, &len, HTTP_IS_DATA_VOLATILE(hs)); + if (err == ERR_OK) { + data_to_send = true; + hs->file += len; + hs->left -= len; + } +#if LWIP_HTTPD_SSI + } else { + /* We are processing an SHTML file so need to scan for tags and replace + * them with insert strings. We need to be careful here since a tag may + * straddle the boundary of two blocks read from the file and we may also + * have to split the insert string between two tcp_write operations. */ + + /* How much data could we send? */ + len = tcp_sndbuf(pcb); + + /* Do we have remaining data to send before parsing more? */ + if(hs->parsed > hs->file) { + /* We cannot send more data than space available in the send + buffer. */ + if (tcp_sndbuf(pcb) < (hs->parsed - hs->file)) { + len = tcp_sndbuf(pcb); + } else { + LWIP_ASSERT("Data size does not fit into u16_t!", + (hs->parsed - hs->file) <= 0xffff); + len = (u16_t)(hs->parsed - hs->file); + } + mss = tcp_mss(pcb); + if(len > (2 * mss)) { + len = 2 * mss; + } + + err = http_write(pcb, hs->file, &len, HTTP_IS_DATA_VOLATILE(hs)); + if (err == ERR_OK) { + data_to_send = true; + hs->file += len; + hs->left -= len; + } + + /* If the send buffer is full, return now. */ + if(tcp_sndbuf(pcb) == 0) { + return data_to_send; + } + } + + LWIP_DEBUGF(HTTPD_DEBUG, ("State %d, %d left\n", hs->tag_state, hs->parse_left)); + + /* We have sent all the data that was already parsed so continue parsing + * the buffer contents looking for SSI tags. */ + while((hs->parse_left) && (err == ERR_OK)) { + /* @todo: somewhere in this loop, 'len' should grow again... */ + if (len == 0) { + return data_to_send; + } + switch(hs->tag_state) { + case TAG_NONE: + /* We are not currently processing an SSI tag so scan for the + * start of the lead-in marker. */ + if(*hs->parsed == g_pcTagLeadIn[0]) { + /* We found what could be the lead-in for a new tag so change + * state appropriately. */ + hs->tag_state = TAG_LEADIN; + hs->tag_index = 1; +#if !LWIP_HTTPD_SSI_INCLUDE_TAG + hs->tag_started = hs->parsed; +#endif /* !LWIP_HTTPD_SSI_INCLUDE_TAG */ + } + + /* Move on to the next character in the buffer */ + hs->parse_left--; + hs->parsed++; + break; + + case TAG_LEADIN: + /* We are processing the lead-in marker, looking for the start of + * the tag name. */ + + /* Have we reached the end of the leadin? */ + if(hs->tag_index == LEN_TAG_LEAD_IN) { + hs->tag_index = 0; + hs->tag_state = TAG_FOUND; + } else { + /* Have we found the next character we expect for the tag leadin? */ + if(*hs->parsed == g_pcTagLeadIn[hs->tag_index]) { + /* Yes - move to the next one unless we have found the complete + * leadin, in which case we start looking for the tag itself */ + hs->tag_index++; + } else { + /* We found an unexpected character so this is not a tag. Move + * back to idle state. */ + hs->tag_state = TAG_NONE; + } + + /* Move on to the next character in the buffer */ + hs->parse_left--; + hs->parsed++; + } + break; + + case TAG_FOUND: + /* We are reading the tag name, looking for the start of the + * lead-out marker and removing any whitespace found. */ + + /* Remove leading whitespace between the tag leading and the first + * tag name character. */ + if((hs->tag_index == 0) && ((*hs->parsed == ' ') || + (*hs->parsed == '\t') || (*hs->parsed == '\n') || + (*hs->parsed == '\r'))) { + /* Move on to the next character in the buffer */ + hs->parse_left--; + hs->parsed++; + break; + } + + /* Have we found the end of the tag name? This is signalled by + * us finding the first leadout character or whitespace */ + if((*hs->parsed == g_pcTagLeadOut[0]) || + (*hs->parsed == ' ') || (*hs->parsed == '\t') || + (*hs->parsed == '\n') || (*hs->parsed == '\r')) { + + if(hs->tag_index == 0) { + /* We read a zero length tag so ignore it. */ + hs->tag_state = TAG_NONE; + } else { + /* We read a non-empty tag so go ahead and look for the + * leadout string. */ + hs->tag_state = TAG_LEADOUT; + LWIP_ASSERT("hs->tag_index <= 0xff", hs->tag_index <= 0xff); + hs->tag_name_len = (u8_t)hs->tag_index; + hs->tag_name[hs->tag_index] = '\0'; + if(*hs->parsed == g_pcTagLeadOut[0]) { + hs->tag_index = 1; + } else { + hs->tag_index = 0; + } + } + } else { + /* This character is part of the tag name so save it */ + if(hs->tag_index < LWIP_HTTPD_MAX_TAG_NAME_LEN) { + hs->tag_name[hs->tag_index++] = *hs->parsed; + } else { + /* The tag was too long so ignore it. */ + hs->tag_state = TAG_NONE; + } + } + + /* Move on to the next character in the buffer */ + hs->parse_left--; + hs->parsed++; + + break; + + /* We are looking for the end of the lead-out marker. */ + case TAG_LEADOUT: + /* Remove leading whitespace between the tag leading and the first + * tag leadout character. */ + if((hs->tag_index == 0) && ((*hs->parsed == ' ') || + (*hs->parsed == '\t') || (*hs->parsed == '\n') || + (*hs->parsed == '\r'))) { + /* Move on to the next character in the buffer */ + hs->parse_left--; + hs->parsed++; + break; + } + + /* Have we found the next character we expect for the tag leadout? */ + if(*hs->parsed == g_pcTagLeadOut[hs->tag_index]) { + /* Yes - move to the next one unless we have found the complete + * leadout, in which case we need to call the client to process + * the tag. */ + + /* Move on to the next character in the buffer */ + hs->parse_left--; + hs->parsed++; + + if(hs->tag_index == (LEN_TAG_LEAD_OUT - 1)) { + /* Call the client to ask for the insert string for the + * tag we just found. */ +#if LWIP_HTTPD_SSI_MULTIPART + hs->tag_part = 0; /* start with tag part 0 */ +#endif /* LWIP_HTTPD_SSI_MULTIPART */ + get_tag_insert(hs); + + /* Next time through, we are going to be sending data + * immediately, either the end of the block we start + * sending here or the insert string. */ + hs->tag_index = 0; + hs->tag_state = TAG_SENDING; + hs->tag_end = hs->parsed; +#if !LWIP_HTTPD_SSI_INCLUDE_TAG + hs->parsed = hs->tag_started; +#endif /* !LWIP_HTTPD_SSI_INCLUDE_TAG*/ + + /* If there is any unsent data in the buffer prior to the + * tag, we need to send it now. */ + if (hs->tag_end > hs->file) { + /* How much of the data can we send? */ +#if LWIP_HTTPD_SSI_INCLUDE_TAG + if(len > hs->tag_end - hs->file) { + len = (u16_t)(hs->tag_end - hs->file); + } +#else /* LWIP_HTTPD_SSI_INCLUDE_TAG*/ + if(len > hs->tag_started - hs->file) { + /* we would include the tag in sending */ + len = (u16_t)(hs->tag_started - hs->file); + } +#endif /* LWIP_HTTPD_SSI_INCLUDE_TAG*/ + + err = http_write(pcb, hs->file, &len, HTTP_IS_DATA_VOLATILE(hs)); + if (err == ERR_OK) { + data_to_send = true; +#if !LWIP_HTTPD_SSI_INCLUDE_TAG + if(hs->tag_started <= hs->file) { + /* pretend to have sent the tag, too */ + len += hs->tag_end - hs->tag_started; + } +#endif /* !LWIP_HTTPD_SSI_INCLUDE_TAG*/ + hs->file += len; + hs->left -= len; + } + } + } else { + hs->tag_index++; + } + } else { + /* We found an unexpected character so this is not a tag. Move + * back to idle state. */ + hs->parse_left--; + hs->parsed++; + hs->tag_state = TAG_NONE; + } + break; + + /* + * We have found a valid tag and are in the process of sending + * data as a result of that discovery. We send either remaining data + * from the file prior to the insert point or the insert string itself. + */ + case TAG_SENDING: + /* Do we have any remaining file data to send from the buffer prior + * to the tag? */ + if(hs->tag_end > hs->file) { + /* How much of the data can we send? */ +#if LWIP_HTTPD_SSI_INCLUDE_TAG + if(len > hs->tag_end - hs->file) { + len = (u16_t)(hs->tag_end - hs->file); + } +#else /* LWIP_HTTPD_SSI_INCLUDE_TAG*/ + LWIP_ASSERT("hs->started >= hs->file", hs->tag_started >= hs->file); + if (len > hs->tag_started - hs->file) { + /* we would include the tag in sending */ + len = (u16_t)(hs->tag_started - hs->file); + } +#endif /* LWIP_HTTPD_SSI_INCLUDE_TAG*/ + if (len != 0) { + err = http_write(pcb, hs->file, &len, HTTP_IS_DATA_VOLATILE(hs)); + } else { + err = ERR_OK; + } + if (err == ERR_OK) { + data_to_send = true; +#if !LWIP_HTTPD_SSI_INCLUDE_TAG + if(hs->tag_started <= hs->file) { + /* pretend to have sent the tag, too */ + len += hs->tag_end - hs->tag_started; + } +#endif /* !LWIP_HTTPD_SSI_INCLUDE_TAG*/ + hs->file += len; + hs->left -= len; + } + } else { +#if LWIP_HTTPD_SSI_MULTIPART + if(hs->tag_index >= hs->tag_insert_len) { + /* Did the last SSIHandler have more to send? */ + if (hs->tag_part != HTTPD_LAST_TAG_PART) { + /* If so, call it again */ + hs->tag_index = 0; + get_tag_insert(hs); + } + } +#endif /* LWIP_HTTPD_SSI_MULTIPART */ + + /* Do we still have insert data left to send? */ + if(hs->tag_index < hs->tag_insert_len) { + /* We are sending the insert string itself. How much of the + * insert can we send? */ + if(len > (hs->tag_insert_len - hs->tag_index)) { + len = (hs->tag_insert_len - hs->tag_index); + } + + /* Note that we set the copy flag here since we only have a + * single tag insert buffer per connection. If we don't do + * this, insert corruption can occur if more than one insert + * is processed before we call tcp_output. */ + err = http_write(pcb, &(hs->tag_insert[hs->tag_index]), &len, + HTTP_IS_TAG_VOLATILE(hs)); + if (err == ERR_OK) { + data_to_send = true; + hs->tag_index += len; + /* Don't return here: keep on sending data */ + } + } else { + /* We have sent all the insert data so go back to looking for + * a new tag. */ + LWIP_DEBUGF(HTTPD_DEBUG, ("Everything sent.\n")); + hs->tag_index = 0; + hs->tag_state = TAG_NONE; +#if !LWIP_HTTPD_SSI_INCLUDE_TAG + hs->parsed = hs->tag_end; +#endif /* !LWIP_HTTPD_SSI_INCLUDE_TAG*/ + } + break; + } + } + } + + /* If we drop out of the end of the for loop, this implies we must have + * file data to send so send it now. In TAG_SENDING state, we've already + * handled this so skip the send if that's the case. */ + if((hs->tag_state != TAG_SENDING) && (hs->parsed > hs->file)) { + /* We cannot send more data than space available in the send + buffer. */ + if (tcp_sndbuf(pcb) < (hs->parsed - hs->file)) { + len = tcp_sndbuf(pcb); + } else { + LWIP_ASSERT("Data size does not fit into u16_t!", + (hs->parsed - hs->file) <= 0xffff); + len = (u16_t)(hs->parsed - hs->file); + } + if(len > (2 * tcp_mss(pcb))) { + len = 2 * tcp_mss(pcb); + } + + err = http_write(pcb, hs->file, &len, HTTP_IS_DATA_VOLATILE(hs)); + if (err == ERR_OK) { + data_to_send = true; + hs->file += len; + hs->left -= len; + } + } + } +#endif /* LWIP_HTTPD_SSI */ + + if((hs->left == 0) && (fs_bytes_left(hs->handle) <= 0)) { + /* We reached the end of the file so this request is done. + * This adds the FIN flag right into the last data segment. + * @todo: don't close here for HTTP/1.1? */ + LWIP_DEBUGF(HTTPD_DEBUG, ("End of file.\n")); + http_close_conn(pcb, hs); + return 0; + } + LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("send_data end.\n")); + return data_to_send; +} + +#if LWIP_HTTPD_SUPPORT_EXTSTATUS +/** Initialize a http connection with a file to send for an error message + * + * @param hs http connection state + * @param error_nr HTTP error number + * @return ERR_OK if file was found and hs has been initialized correctly + * another err_t otherwise + */ +static err_t +http_find_error_file(struct http_state *hs, u16_t error_nr) +{ + const char *uri1, *uri2, *uri3; + struct fs_file *file; + + if (error_nr == 501) { + uri1 = "/501.html"; + uri2 = "/501.htm"; + uri3 = "/501.shtml"; + } else { + /* 400 (bad request is the default) */ + uri1 = "/400.html"; + uri2 = "/400.htm"; + uri3 = "/400.shtml"; + } + file = fs_open(uri1); + if (file == NULL) { + file = fs_open(uri2); + if (file == NULL) { + file = fs_open(uri3); + if (file == NULL) { + LWIP_DEBUGF(HTTPD_DEBUG, ("Error page for error %"U16_F" not found\n", + error_nr)); + return ERR_ARG; + } + } + } + return http_init_file(hs, file, 0, NULL); +} +#else /* LWIP_HTTPD_SUPPORT_EXTSTATUS */ +#define http_find_error_file(hs, error_nr) ERR_ARG +#endif /* LWIP_HTTPD_SUPPORT_EXTSTATUS */ + +/** + * Get the file struct for a 404 error page. + * Tries some file names and returns NULL if none found. + * + * @param uri pointer that receives the actual file name URI + * @return file struct for the error page or NULL no matching file was found + */ +static struct fs_file * +http_get_404_file(const char **uri) +{ + struct fs_file *file; + + *uri = "/404.html"; + file = fs_open(*uri); + if(file == NULL) { + /* 404.html doesn't exist. Try 404.htm instead. */ + *uri = "/404.htm"; + file = fs_open(*uri); + if(file == NULL) { + /* 404.htm doesn't exist either. Try 404.shtml instead. */ + *uri = "/404.shtml"; + file = fs_open(*uri); + if(file == NULL) { + /* 404.htm doesn't exist either. Indicate to the caller that it should + * send back a default 404 page. + */ + *uri = NULL; + } + } + } + + return file; +} + +#if LWIP_HTTPD_SUPPORT_POST +static err_t +http_handle_post_finished(struct http_state *hs) +{ + /* application error or POST finished */ + /* NULL-terminate the buffer */ + http_post_response_filename[0] = 0; + httpd_post_finished(hs, http_post_response_filename, LWIP_HTTPD_POST_MAX_RESPONSE_URI_LEN); + return http_find_file(hs, http_post_response_filename, 0); +} + +/** Pass received POST body data to the application and correctly handle + * returning a response document or closing the connection. + * ATTENTION: The application is responsible for the pbuf now, so don't free it! + * + * @param hs http connection state + * @param p pbuf to pass to the application + * @return ERR_OK if passed successfully, another err_t if the response file + * hasn't been found (after POST finished) + */ +static err_t +http_post_rxpbuf(struct http_state *hs, struct pbuf *p) +{ + err_t err; + + /* adjust remaining Content-Length */ + if (hs->post_content_len_left < p->tot_len) { + hs->post_content_len_left = 0; + } else { + hs->post_content_len_left -= p->tot_len; + } + err = httpd_post_receive_data(hs, p); + if ((err != ERR_OK) || (hs->post_content_len_left == 0)) { +#if LWIP_HTTPD_SUPPORT_POST && LWIP_HTTPD_POST_MANUAL_WND + if (hs->unrecved_bytes != 0) { + return ERR_OK; + } +#endif /* LWIP_HTTPD_SUPPORT_POST && LWIP_HTTPD_POST_MANUAL_WND */ + /* application error or POST finished */ + return http_handle_post_finished(hs); + } + + return ERR_OK; +} + +/** Handle a post request. Called from http_parse_request when method 'POST' + * is found. + * + * @param pcb The tcp_pcb which received this packet. + * @param p The input pbuf (containing the POST header and body). + * @param hs The http connection state. + * @param data HTTP request (header and part of body) from input pbuf(s). + * @param data_len Size of 'data'. + * @param uri The HTTP URI parsed from input pbuf(s). + * @param uri_end Pointer to the end of 'uri' (here, the rest of the HTTP + * header starts). + * @return ERR_OK: POST correctly parsed and accepted by the application. + * ERR_INPROGRESS: POST not completely parsed (no error yet) + * another err_t: Error parsing POST or denied by the application + */ +static err_t +http_post_request(struct tcp_pcb *pcb, struct pbuf **inp, struct http_state *hs, + char *data, u16_t data_len, char *uri, char *uri_end) +{ + err_t err; + /* search for end-of-header (first double-CRLF) */ + char* crlfcrlf = strnstr(uri_end + 1, CRLF CRLF, data_len - (uri_end + 1 - data)); + +#if LWIP_HTTPD_POST_MANUAL_WND + hs->pcb = pcb; +#else /* LWIP_HTTPD_POST_MANUAL_WND */ + LWIP_UNUSED_ARG(pcb); /* only used for LWIP_HTTPD_POST_MANUAL_WND */ +#endif /* LWIP_HTTPD_POST_MANUAL_WND */ + + if (crlfcrlf != NULL) { + /* search for "Content-Length: " */ +#define HTTP_HDR_CONTENT_LEN "Content-Length: " +#define HTTP_HDR_CONTENT_LEN_LEN 16 +#define HTTP_HDR_CONTENT_LEN_DIGIT_MAX_LEN 10 + char *scontent_len = strnstr(uri_end + 1, HTTP_HDR_CONTENT_LEN, crlfcrlf - (uri_end + 1)); + if (scontent_len != NULL) { + char *scontent_len_end = strnstr(scontent_len + HTTP_HDR_CONTENT_LEN_LEN, CRLF, HTTP_HDR_CONTENT_LEN_DIGIT_MAX_LEN); + if (scontent_len_end != NULL) { + int content_len; + char *conten_len_num = scontent_len + HTTP_HDR_CONTENT_LEN_LEN; + *scontent_len_end = 0; + content_len = atoi(conten_len_num); + if (content_len > 0) { + /* adjust length of HTTP header passed to application */ + const char *hdr_start_after_uri = uri_end + 1; + u16_t hdr_len = LWIP_MIN(data_len, crlfcrlf + 4 - data); + u16_t hdr_data_len = LWIP_MIN(data_len, crlfcrlf + 4 - hdr_start_after_uri); + u8_t post_auto_wnd = 1; + http_post_response_filename[0] = 0; + err = httpd_post_begin(hs, uri, hdr_start_after_uri, hdr_data_len, content_len, + http_post_response_filename, LWIP_HTTPD_POST_MAX_RESPONSE_URI_LEN, &post_auto_wnd); + if (err == ERR_OK) { + /* try to pass in data of the first pbuf(s) */ + struct pbuf *q = *inp; + u16_t start_offset = hdr_len; +#if LWIP_HTTPD_POST_MANUAL_WND + hs->no_auto_wnd = !post_auto_wnd; +#endif /* LWIP_HTTPD_POST_MANUAL_WND */ + /* set the Content-Length to be received for this POST */ + hs->post_content_len_left = (u32_t)content_len; + + /* get to the pbuf where the body starts */ + while((q != NULL) && (q->len <= start_offset)) { + struct pbuf *head = q; + start_offset -= q->len; + q = q->next; + /* free the head pbuf */ + head->next = NULL; + pbuf_free(head); + } + *inp = NULL; + if (q != NULL) { + /* hide the remaining HTTP header */ + pbuf_header(q, -(s16_t)start_offset); +#if LWIP_HTTPD_POST_MANUAL_WND + if (!post_auto_wnd) { + /* already tcp_recved() this data... */ + hs->unrecved_bytes = q->tot_len; + } +#endif /* LWIP_HTTPD_POST_MANUAL_WND */ + return http_post_rxpbuf(hs, q); + } else { + return ERR_OK; + } + } else { + /* return file passed from application */ + return http_find_file(hs, http_post_response_filename, 0); + } + } else { + LWIP_DEBUGF(HTTPD_DEBUG, ("POST received invalid Content-Length: %s\n", + conten_len_num)); + return ERR_ARG; + } + } + } + } + /* if we come here, the POST is incomplete */ +#if LWIP_HTTPD_SUPPORT_REQUESTLIST + return ERR_INPROGRESS; +#else /* LWIP_HTTPD_SUPPORT_REQUESTLIST */ + return ERR_ARG; +#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */ +} + +#if LWIP_HTTPD_POST_MANUAL_WND +/** A POST implementation can call this function to update the TCP window. + * This can be used to throttle data reception (e.g. when received data is + * programmed to flash and data is received faster than programmed). + * + * @param connection A connection handle passed to httpd_post_begin for which + * httpd_post_finished has *NOT* been called yet! + * @param recved_len Length of data received (for window update) + */ +void httpd_post_data_recved(void *connection, u16_t recved_len) +{ + struct http_state *hs = (struct http_state*)connection; + if (hs != NULL) { + if (hs->no_auto_wnd) { + u16_t len = recved_len; + if (hs->unrecved_bytes >= recved_len) { + hs->unrecved_bytes -= recved_len; + } else { + LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_LEVEL_WARNING, ("httpd_post_data_recved: recved_len too big\n")); + len = (u16_t)hs->unrecved_bytes; + hs->unrecved_bytes = 0; + } + if (hs->pcb != NULL) { + if (len != 0) { + tcp_recved(hs->pcb, len); + } + if ((hs->post_content_len_left == 0) && (hs->unrecved_bytes == 0)) { + /* finished handling POST */ + http_handle_post_finished(hs); + http_send_data(hs->pcb, hs); + } + } + } + } +} +#endif /* LWIP_HTTPD_POST_MANUAL_WND */ + +#endif /* LWIP_HTTPD_SUPPORT_POST */ + +/** + * When data has been received in the correct state, try to parse it + * as a HTTP request. + * + * @param p the received pbuf + * @param hs the connection state + * @param pcb the tcp_pcb which received this packet + * @return ERR_OK if request was OK and hs has been initialized correctly + * ERR_INPROGRESS if request was OK so far but not fully received + * another err_t otherwise + */ +static err_t +http_parse_request(struct pbuf **inp, struct http_state *hs, struct tcp_pcb *pcb) +{ + char *data; + char *crlf; + u16_t data_len; + struct pbuf *p = *inp; +#if LWIP_HTTPD_SUPPORT_REQUESTLIST + u16_t clen; +#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */ +#if LWIP_HTTPD_SUPPORT_POST + err_t err; +#endif /* LWIP_HTTPD_SUPPORT_POST */ + + LWIP_UNUSED_ARG(pcb); /* only used for post */ + LWIP_ASSERT("p != NULL", p != NULL); + LWIP_ASSERT("hs != NULL", hs != NULL); + + if ((hs->handle != NULL) || (hs->file != NULL)) { + LWIP_DEBUGF(HTTPD_DEBUG, ("Received data while sending a file\n")); + /* already sending a file */ + /* @todo: abort? */ + return ERR_USE; + } + +#if LWIP_HTTPD_SUPPORT_REQUESTLIST + + LWIP_DEBUGF(HTTPD_DEBUG, ("Received %"U16_F" bytes\n", p->tot_len)); + + /* first check allowed characters in this pbuf? */ + + /* enqueue the pbuf */ + if (hs->req == NULL) { + LWIP_DEBUGF(HTTPD_DEBUG, ("First pbuf\n")); + hs->req = p; + } else { + LWIP_DEBUGF(HTTPD_DEBUG, ("pbuf enqueued\n")); + pbuf_cat(hs->req, p); + } + + if (hs->req->next != NULL) { + data_len = LWIP_MIN(hs->req->tot_len, LWIP_HTTPD_MAX_REQ_LENGTH); + pbuf_copy_partial(hs->req, httpd_req_buf, data_len, 0); + data = httpd_req_buf; + } else +#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */ + { + data = (char *)p->payload; + data_len = p->len; + if (p->len != p->tot_len) { + LWIP_DEBUGF(HTTPD_DEBUG, ("Warning: incomplete header due to chained pbufs\n")); + } + } + + /* received enough data for minimal request? */ + if (data_len >= MIN_REQ_LEN) { + /* wait for CRLF before parsing anything */ + crlf = strnstr(data, CRLF, data_len); + if (crlf != NULL) { +#if LWIP_HTTPD_SUPPORT_POST + int is_post = 0; +#endif /* LWIP_HTTPD_SUPPORT_POST */ + int is_09 = 0; + char *sp1, *sp2; + u16_t left_len, uri_len; + LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("CRLF received, parsing request\n")); + /* parse method */ + if (!strncmp(data, "GET ", 4)) { + sp1 = data + 3; + /* received GET request */ + LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("Received GET request\"\n")); +#if LWIP_HTTPD_SUPPORT_POST + } else if (!strncmp(data, "POST ", 5)) { + /* store request type */ + is_post = 1; + sp1 = data + 4; + /* received GET request */ + LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("Received POST request\n")); +#endif /* LWIP_HTTPD_SUPPORT_POST */ + } else { + /* null-terminate the METHOD (pbuf is freed anyway wen returning) */ + data[4] = 0; + /* unsupported method! */ + LWIP_DEBUGF(HTTPD_DEBUG, ("Unsupported request method (not implemented): \"%s\"\n", + data)); + return http_find_error_file(hs, 501); + } + /* if we come here, method is OK, parse URI */ + left_len = data_len - ((sp1 +1) - data); + sp2 = strnstr(sp1 + 1, " ", left_len); +#if LWIP_HTTPD_SUPPORT_V09 + if (sp2 == NULL) { + /* HTTP 0.9: respond with correct protocol version */ + sp2 = strnstr(sp1 + 1, CRLF, left_len); + is_09 = 1; +#if LWIP_HTTPD_SUPPORT_POST + if (is_post) { + /* HTTP/0.9 does not support POST */ + goto badrequest; + } +#endif /* LWIP_HTTPD_SUPPORT_POST */ + } +#endif /* LWIP_HTTPD_SUPPORT_V09 */ + uri_len = sp2 - (sp1 + 1); + if ((sp2 != 0) && (sp2 > sp1)) { + char *uri = sp1 + 1; + /* null-terminate the METHOD (pbuf is freed anyway wen returning) */ + *sp1 = 0; + uri[uri_len] = 0; + LWIP_DEBUGF(HTTPD_DEBUG, ("Received \"%s\" request for URI: \"%s\"\n", + data, uri)); +#if LWIP_HTTPD_SUPPORT_POST + if (is_post) { +#if LWIP_HTTPD_SUPPORT_REQUESTLIST + struct pbuf **q = &hs->req; +#else /* LWIP_HTTPD_SUPPORT_REQUESTLIST */ + struct pbuf **q = inp; +#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */ + err = http_post_request(pcb, q, hs, data, data_len, uri, sp2); + if (err != ERR_OK) { + /* restore header for next try */ + *sp1 = ' '; + *sp2 = ' '; + uri[uri_len] = ' '; + } + if (err == ERR_ARG) { + goto badrequest; + } + return err; + } else +#endif /* LWIP_HTTPD_SUPPORT_POST */ + { + return http_find_file(hs, uri, is_09); + } + } else { + LWIP_DEBUGF(HTTPD_DEBUG, ("invalid URI\n")); + } + } + } + +#if LWIP_HTTPD_SUPPORT_REQUESTLIST + clen = pbuf_clen(hs->req); + if ((hs->req->tot_len <= LWIP_HTTPD_REQ_BUFSIZE) && + (clen <= LWIP_HTTPD_REQ_QUEUELEN)) { + /* request not fully received (too short or CRLF is missing) */ + return ERR_INPROGRESS; + } else +#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */ + { +#if LWIP_HTTPD_SUPPORT_POST +badrequest: +#endif /* LWIP_HTTPD_SUPPORT_POST */ + LWIP_DEBUGF(HTTPD_DEBUG, ("bad request\n")); + /* could not parse request */ + return http_find_error_file(hs, 400); + } +} + +/** Try to find the file specified by uri and, if found, initialize hs + * accordingly. + * + * @param hs the connection state + * @param uri the HTTP header URI + * @param is_09 1 if the request is HTTP/0.9 (no HTTP headers in response) + * @return ERR_OK if file was found and hs has been initialized correctly + * another err_t otherwise + */ +static err_t +http_find_file(struct http_state *hs, const char *uri, int is_09) +{ + size_t loop; + struct fs_file *file = NULL; + char *params; +#if LWIP_HTTPD_CGI + int i; + int count; +#endif /* LWIP_HTTPD_CGI */ + +#if LWIP_HTTPD_SSI + /* + * By default, assume we will not be processing server-side-includes + * tags + */ + hs->tag_check = false; +#endif /* LWIP_HTTPD_SSI */ + + /* Have we been asked for the default root file? */ + if((uri[0] == '/') && (uri[1] == 0)) { + /* Try each of the configured default filenames until we find one + that exists. */ + for (loop = 0; loop < NUM_DEFAULT_FILENAMES; loop++) { + LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("Looking for %s...\n", g_psDefaultFilenames[loop].name)); + file = fs_open((char *)g_psDefaultFilenames[loop].name); + uri = (char *)g_psDefaultFilenames[loop].name; + if(file != NULL) { + LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("Opened.\n")); +#if LWIP_HTTPD_SSI + hs->tag_check = g_psDefaultFilenames[loop].shtml; +#endif /* LWIP_HTTPD_SSI */ + break; + } + } + if (file == NULL) { + /* None of the default filenames exist so send back a 404 page */ + file = http_get_404_file(&uri); +#if LWIP_HTTPD_SSI + hs->tag_check = false; +#endif /* LWIP_HTTPD_SSI */ + } + } else { + /* No - we've been asked for a specific file. */ + /* First, isolate the base URI (without any parameters) */ + params = (char *)strchr(uri, '?'); + if (params != NULL) { + /* URI contains parameters. NULL-terminate the base URI */ + *params = '\0'; + params++; + } + +#if LWIP_HTTPD_CGI + /* Does the base URI we have isolated correspond to a CGI handler? */ + if (g_iNumCGIs && g_pCGIs) { + for (i = 0; i < g_iNumCGIs; i++) { + if (strcmp(uri, g_pCGIs[i].pcCGIName) == 0) { + /* + * We found a CGI that handles this URI so extract the + * parameters and call the handler. + */ + count = extract_uri_parameters(hs, params); + uri = g_pCGIs[i].pfnCGIHandler(i, count, hs->params, + hs->param_vals); + break; + } + } + } +#endif /* LWIP_HTTPD_CGI */ + + LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("Opening %s\n", uri)); + + file = fs_open(uri); + if (file == NULL) { + file = http_get_404_file(&uri); + } +#if LWIP_HTTPD_SSI + if (file != NULL) { + /* + * See if we have been asked for an shtml file and, if so, + * enable tag checking. + */ + hs->tag_check = false; + for (loop = 0; loop < NUM_SHTML_EXTENSIONS; loop++) { + if (strstr(uri, g_pcSSIExtensions[loop])) { + hs->tag_check = true; + break; + } + } + } +#endif /* LWIP_HTTPD_SSI */ + } + return http_init_file(hs, file, is_09, uri); +} + +/** Initialize a http connection with a file to send (if found). + * Called by http_find_file and http_find_error_file. + * + * @param hs http connection state + * @param file file structure to send (or NULL if not found) + * @param is_09 1 if the request is HTTP/0.9 (no HTTP headers in response) + * @param uri the HTTP header URI + * @return ERR_OK if file was found and hs has been initialized correctly + * another err_t otherwise + */ +static err_t +http_init_file(struct http_state *hs, struct fs_file *file, int is_09, const char *uri) +{ + if (file != NULL) { + /* file opened, initialise struct http_state */ +#if LWIP_HTTPD_SSI + hs->tag_index = 0; + hs->tag_state = TAG_NONE; + hs->parsed = file->data; + hs->parse_left = file->len; + hs->tag_end = file->data; +#endif /* LWIP_HTTPD_SSI */ + hs->handle = file; + hs->file = (char*)file->data; + LWIP_ASSERT("File length must be positive!", (file->len >= 0)); + hs->left = file->len; + hs->retries = 0; +#if LWIP_HTTPD_TIMING + hs->time_started = sys_now(); +#endif /* LWIP_HTTPD_TIMING */ +#if !LWIP_HTTPD_DYNAMIC_HEADERS + LWIP_ASSERT("HTTP headers not included in file system", hs->handle->http_header_included); +#endif /* !LWIP_HTTPD_DYNAMIC_HEADERS */ +#if LWIP_HTTPD_SUPPORT_V09 + if (hs->handle->http_header_included && is_09) { + /* HTTP/0.9 responses are sent without HTTP header, + search for the end of the header. */ + char *file_start = strnstr(hs->file, CRLF CRLF, hs->left); + if (file_start != NULL) { + size_t diff = file_start + 4 - hs->file; + hs->file += diff; + hs->left -= (u32_t)diff; + } + } +#endif /* LWIP_HTTPD_SUPPORT_V09*/ + } else { + hs->handle = NULL; + hs->file = NULL; + hs->left = 0; + hs->retries = 0; + } +#if LWIP_HTTPD_DYNAMIC_HEADERS + /* Determine the HTTP headers to send based on the file extension of + * the requested URI. */ + if ((hs->handle == NULL) || !hs->handle->http_header_included) { + get_http_headers(hs, (char*)uri); + } +#else /* LWIP_HTTPD_DYNAMIC_HEADERS */ + LWIP_UNUSED_ARG(uri); +#endif /* LWIP_HTTPD_DYNAMIC_HEADERS */ + return ERR_OK; +} + +/** + * The pcb had an error and is already deallocated. + * The argument might still be valid (if != NULL). + */ +static void +http_err(void *arg, err_t err) +{ + struct http_state *hs = (struct http_state *)arg; + LWIP_UNUSED_ARG(err); + + LWIP_DEBUGF(HTTPD_DEBUG, ("http_err: %s", lwip_strerr(err))); + + if (hs != NULL) { + http_state_free(hs); + } +} + +/** + * Data has been sent and acknowledged by the remote host. + * This means that more data can be sent. + */ +static err_t +http_sent(void *arg, struct tcp_pcb *pcb, u16_t len) +{ + struct http_state *hs = (struct http_state *)arg; + + LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("http_sent %p\n", (void*)pcb)); + + LWIP_UNUSED_ARG(len); + + if (hs == NULL) { + return ERR_OK; + } + + hs->retries = 0; + + http_send_data(pcb, hs); + + return ERR_OK; +} + +/** + * The poll function is called every 2nd second. + * If there has been no data sent (which resets the retries) in 8 seconds, close. + * If the last portion of a file has not been sent in 2 seconds, close. + * + * This could be increased, but we don't want to waste resources for bad connections. + */ +static err_t +http_poll(void *arg, struct tcp_pcb *pcb) +{ + struct http_state *hs = (struct http_state *)arg; + LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("http_poll: pcb=%p hs=%p pcb_state=%s\n", + (void*)pcb, (void*)hs, tcp_debug_state_str(pcb->state))); + + if (hs == NULL) { + err_t closed; + /* arg is null, close. */ + LWIP_DEBUGF(HTTPD_DEBUG, ("http_poll: arg is NULL, close\n")); + closed = http_close_conn(pcb, hs); + LWIP_UNUSED_ARG(closed); +#if LWIP_HTTPD_ABORT_ON_CLOSE_MEM_ERROR + if (closed == ERR_MEM) { + tcp_abort(pcb); + return ERR_ABRT; + } +#endif /* LWIP_HTTPD_ABORT_ON_CLOSE_MEM_ERROR */ + return ERR_OK; + } else { + hs->retries++; + if (hs->retries == HTTPD_MAX_RETRIES) { + LWIP_DEBUGF(HTTPD_DEBUG, ("http_poll: too many retries, close\n")); + http_close_conn(pcb, hs); + return ERR_OK; + } + + /* If this connection has a file open, try to send some more data. If + * it has not yet received a GET request, don't do this since it will + * cause the connection to close immediately. */ + if(hs && (hs->handle)) { + LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("http_poll: try to send more data\n")); + if(http_send_data(pcb, hs)) { + /* If we wrote anything to be sent, go ahead and send it now. */ + LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("tcp_output\n")); + tcp_output(pcb); + } + } + } + + return ERR_OK; +} + +/** + * Data has been received on this pcb. + * For HTTP 1.0, this should normally only happen once (if the request fits in one packet). + */ +static err_t +http_recv(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err) +{ + err_t parsed = ERR_ABRT; + struct http_state *hs = (struct http_state *)arg; + LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("http_recv: pcb=%p pbuf=%p err=%s\n", (void*)pcb, + (void*)p, lwip_strerr(err))); + + if ((err != ERR_OK) || (p == NULL) || (hs == NULL)) { + /* error or closed by other side? */ + if (p != NULL) { + /* Inform TCP that we have taken the data. */ + tcp_recved(pcb, p->tot_len); + pbuf_free(p); + } + if (hs == NULL) { + /* this should not happen, only to be robust */ + LWIP_DEBUGF(HTTPD_DEBUG, ("Error, http_recv: hs is NULL, close\n")); + } + http_close_conn(pcb, hs); + return ERR_OK; + } + +#if LWIP_HTTPD_SUPPORT_POST && LWIP_HTTPD_POST_MANUAL_WND + if (hs->no_auto_wnd) { + hs->unrecved_bytes += p->tot_len; + } else +#endif /* LWIP_HTTPD_SUPPORT_POST && LWIP_HTTPD_POST_MANUAL_WND */ + { + /* Inform TCP that we have taken the data. */ + tcp_recved(pcb, p->tot_len); + } + +#if LWIP_HTTPD_SUPPORT_POST + if (hs->post_content_len_left > 0) { + /* reset idle counter when POST data is received */ + hs->retries = 0; + /* this is data for a POST, pass the complete pbuf to the application */ + http_post_rxpbuf(hs, p); + /* pbuf is passed to the application, don't free it! */ + if (hs->post_content_len_left == 0) { + /* all data received, send response or close connection */ + http_send_data(pcb, hs); + } + return ERR_OK; + } else +#endif /* LWIP_HTTPD_SUPPORT_POST */ + { + if (hs->handle == NULL) { + parsed = http_parse_request(&p, hs, pcb); + LWIP_ASSERT("http_parse_request: unexpected return value", parsed == ERR_OK + || parsed == ERR_INPROGRESS ||parsed == ERR_ARG || parsed == ERR_USE); + } else { + LWIP_DEBUGF(HTTPD_DEBUG, ("http_recv: already sending data\n")); + } +#if LWIP_HTTPD_SUPPORT_REQUESTLIST + if (parsed != ERR_INPROGRESS) { + /* request fully parsed or error */ + if (hs->req != NULL) { + pbuf_free(hs->req); + hs->req = NULL; + } + } +#else /* LWIP_HTTPD_SUPPORT_REQUESTLIST */ + if (p != NULL) { + /* pbuf not passed to application, free it now */ + pbuf_free(p); + } +#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */ + if (parsed == ERR_OK) { +#if LWIP_HTTPD_SUPPORT_POST + if (hs->post_content_len_left == 0) +#endif /* LWIP_HTTPD_SUPPORT_POST */ + { + LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("http_recv: data %p len %"S32_F"\n", hs->file, hs->left)); + http_send_data(pcb, hs); + } + } else if (parsed == ERR_ARG) { + /* @todo: close on ERR_USE? */ + http_close_conn(pcb, hs); + } + } + return ERR_OK; +} + +/** + * A new incoming connection has been accepted. + */ +static err_t +http_accept(void *arg, struct tcp_pcb *pcb, err_t err) +{ + struct http_state *hs; + struct tcp_pcb_listen *lpcb = (struct tcp_pcb_listen*)arg; + LWIP_UNUSED_ARG(err); + LWIP_DEBUGF(HTTPD_DEBUG, ("http_accept %p / %p\n", (void*)pcb, arg)); + + /* Decrease the listen backlog counter */ + tcp_accepted(lpcb); + /* Set priority */ + tcp_setprio(pcb, HTTPD_TCP_PRIO); + + /* Allocate memory for the structure that holds the state of the + connection - initialized by that function. */ + hs = http_state_alloc(); + if (hs == NULL) { + LWIP_DEBUGF(HTTPD_DEBUG, ("http_accept: Out of memory, RST\n")); + return ERR_MEM; + } + + /* Tell TCP that this is the structure we wish to be passed for our + callbacks. */ + tcp_arg(pcb, hs); + + /* Set up the various callback functions */ + tcp_recv(pcb, http_recv); + tcp_err(pcb, http_err); + tcp_poll(pcb, http_poll, HTTPD_POLL_INTERVAL); + tcp_sent(pcb, http_sent); + + return ERR_OK; +} + +/** + * Initialize the httpd with the specified local address. + */ +static void +httpd_init_addr(ip_addr_t *local_addr) +{ + struct tcp_pcb *pcb; + err_t err; + + pcb = tcp_new(); + LWIP_ASSERT("httpd_init: tcp_new failed", pcb != NULL); + tcp_setprio(pcb, HTTPD_TCP_PRIO); + /* set SOF_REUSEADDR here to explicitly bind httpd to multiple interfaces */ + err = tcp_bind(pcb, local_addr, HTTPD_SERVER_PORT); + LWIP_ASSERT("httpd_init: tcp_bind failed", err == ERR_OK); + pcb = tcp_listen(pcb); + LWIP_ASSERT("httpd_init: tcp_listen failed", pcb != NULL); + /* initialize callback arg and accept callback */ + tcp_arg(pcb, pcb); + tcp_accept(pcb, http_accept); +} + +/** + * Initialize the httpd: set up a listening PCB and bind it to the defined port + */ +void +httpd_init(void) +{ +#if HTTPD_USE_MEM_POOL + LWIP_ASSERT("memp_sizes[MEMP_HTTPD_STATE] >= sizeof(http_state)", + memp_sizes[MEMP_HTTPD_STATE] >= sizeof(http_state)); +#endif + LWIP_DEBUGF(HTTPD_DEBUG, ("httpd_init\n")); + + httpd_init_addr(IP_ADDR_ANY); +} + +#if LWIP_HTTPD_SSI +/** + * Set the SSI handler function. + * + * @param ssi_handler the SSI handler function + * @param tags an array of SSI tag strings to search for in SSI-enabled files + * @param num_tags number of tags in the 'tags' array + */ +void +http_set_ssi_handler(tSSIHandler ssi_handler, const char **tags, int num_tags) +{ + LWIP_DEBUGF(HTTPD_DEBUG, ("http_set_ssi_handler\n")); + + LWIP_ASSERT("no ssi_handler given", ssi_handler != NULL); + LWIP_ASSERT("no tags given", tags != NULL); + LWIP_ASSERT("invalid number of tags", num_tags > 0); + + g_pfnSSIHandler = ssi_handler; + g_ppcTags = tags; + g_iNumTags = num_tags; +} +#endif /* LWIP_HTTPD_SSI */ + +#if LWIP_HTTPD_CGI +/** + * Set an array of CGI filenames/handler functions + * + * @param cgis an array of CGI filenames/handler functions + * @param num_handlers number of elements in the 'cgis' array + */ +void +http_set_cgi_handlers(const tCGI *cgis, int num_handlers) +{ + LWIP_ASSERT("no cgis given", cgis != NULL); + LWIP_ASSERT("invalid number of handlers", num_handlers > 0); + + g_pCGIs = cgis; + g_iNumCGIs = num_handlers; +} +#endif /* LWIP_HTTPD_CGI */ + +#endif /* LWIP_TCP */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/httpd.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/httpd.h new file mode 100644 index 000000000..8c3c03d47 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/httpd.h @@ -0,0 +1,236 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * This version of the file has been modified by Texas Instruments to offer + * simple server-side-include (SSI) and Common Gateway Interface (CGI) + * capability. + */ + +#ifndef __HTTPD_H__ +#define __HTTPD_H__ + +#include "lwip/opt.h" +#include "lwip/err.h" +#include "lwip/pbuf.h" + + +/** Set this to 1 to support CGI */ +#ifndef LWIP_HTTPD_CGI +#define LWIP_HTTPD_CGI 0 +#endif + +/** Set this to 1 to support SSI (Server-Side-Includes) */ +#ifndef LWIP_HTTPD_SSI +#define LWIP_HTTPD_SSI 1 +#endif + +/** Set this to 1 to support HTTP POST */ +#ifndef LWIP_HTTPD_SUPPORT_POST +#define LWIP_HTTPD_SUPPORT_POST 0 +#endif + + +#if LWIP_HTTPD_CGI + +/* + * Function pointer for a CGI script handler. + * + * This function is called each time the HTTPD server is asked for a file + * whose name was previously registered as a CGI function using a call to + * http_set_cgi_handler. The iIndex parameter provides the index of the + * CGI within the ppcURLs array passed to http_set_cgi_handler. Parameters + * pcParam and pcValue provide access to the parameters provided along with + * the URI. iNumParams provides a count of the entries in the pcParam and + * pcValue arrays. Each entry in the pcParam array contains the name of a + * parameter with the corresponding entry in the pcValue array containing the + * value for that parameter. Note that pcParam may contain multiple elements + * with the same name if, for example, a multi-selection list control is used + * in the form generating the data. + * + * The function should return a pointer to a character string which is the + * path and filename of the response that is to be sent to the connected + * browser, for example "/thanks.htm" or "/response/error.ssi". + * + * The maximum number of parameters that will be passed to this function via + * iNumParams is defined by LWIP_HTTPD_MAX_CGI_PARAMETERS. Any parameters in the incoming + * HTTP request above this number will be discarded. + * + * Requests intended for use by this CGI mechanism must be sent using the GET + * method (which encodes all parameters within the URI rather than in a block + * later in the request). Attempts to use the POST method will result in the + * request being ignored. + * + */ +typedef const char *(*tCGIHandler)(int iIndex, int iNumParams, char *pcParam[], + char *pcValue[]); + +/* + * Structure defining the base filename (URL) of a CGI and the associated + * function which is to be called when that URL is requested. + */ +typedef struct +{ + const char *pcCGIName; + tCGIHandler pfnCGIHandler; +} tCGI; + +void http_set_cgi_handlers(const tCGI *pCGIs, int iNumHandlers); + + +/* The maximum number of parameters that the CGI handler can be sent. */ +#ifndef LWIP_HTTPD_MAX_CGI_PARAMETERS +#define LWIP_HTTPD_MAX_CGI_PARAMETERS 16 +#endif + +#endif /* LWIP_HTTPD_CGI */ + +#if LWIP_HTTPD_SSI + +/** LWIP_HTTPD_SSI_MULTIPART==1: SSI handler function is called with 2 more + * arguments indicating a counter for insert string that are too long to be + * inserted at once: the SSI handler function must then set 'next_tag_part' + * which will be passed back to it in the next call. */ +#ifndef LWIP_HTTPD_SSI_MULTIPART +#define LWIP_HTTPD_SSI_MULTIPART 0 +#endif + +/* + * Function pointer for the SSI tag handler callback. + * + * This function will be called each time the HTTPD server detects a tag of the + * form in a .shtml, .ssi or .shtm file where "name" appears as + * one of the tags supplied to http_set_ssi_handler in the ppcTags array. The + * returned insert string, which will be appended after the the string + * "" in file sent back to the client,should be written to pointer + * pcInsert. iInsertLen contains the size of the buffer pointed to by + * pcInsert. The iIndex parameter provides the zero-based index of the tag as + * found in the ppcTags array and identifies the tag that is to be processed. + * + * The handler returns the number of characters written to pcInsert excluding + * any terminating NULL or a negative number to indicate a failure (tag not + * recognized, for example). + * + * Note that the behavior of this SSI mechanism is somewhat different from the + * "normal" SSI processing as found in, for example, the Apache web server. In + * this case, the inserted text is appended following the SSI tag rather than + * replacing the tag entirely. This allows for an implementation that does not + * require significant additional buffering of output data yet which will still + * offer usable SSI functionality. One downside to this approach is when + * attempting to use SSI within JavaScript. The SSI tag is structured to + * resemble an HTML comment but this syntax does not constitute a comment + * within JavaScript and, hence, leaving the tag in place will result in + * problems in these cases. To work around this, any SSI tag which needs to + * output JavaScript code must do so in an encapsulated way, sending the whole + * HTML section as a single include. + */ +typedef u16_t (*tSSIHandler)(int iIndex, char *pcInsert, int iInsertLen +#if LWIP_HTTPD_SSI_MULTIPART + , u16_t current_tag_part, u16_t *next_tag_part +#endif /* LWIP_HTTPD_SSI_MULTIPART */ +#if LWIP_HTTPD_FILE_STATE + , void *connection_state +#endif /* LWIP_HTTPD_FILE_STATE */ + ); + +void http_set_ssi_handler(tSSIHandler pfnSSIHandler, + const char **ppcTags, int iNumTags); + +/* The maximum length of the string comprising the tag name */ +#ifndef LWIP_HTTPD_MAX_TAG_NAME_LEN +#define LWIP_HTTPD_MAX_TAG_NAME_LEN 8 +#endif + +/* The maximum length of string that can be returned to replace any given tag */ +#ifndef LWIP_HTTPD_MAX_TAG_INSERT_LEN +#define LWIP_HTTPD_MAX_TAG_INSERT_LEN 192 +#endif + +#endif /* LWIP_HTTPD_SSI */ + +#if LWIP_HTTPD_SUPPORT_POST + +/* These functions must be implemented by the application */ + +/** Called when a POST request has been received. The application can decide + * whether to accept it or not. + * + * @param connection Unique connection identifier, valid until httpd_post_end + * is called. + * @param uri The HTTP header URI receiving the POST request. + * @param http_request The raw HTTP request (the first packet, normally). + * @param http_request_len Size of 'http_request'. + * @param content_len Content-Length from HTTP header. + * @param response_uri Filename of response file, to be filled when denying the + * request + * @param response_uri_len Size of the 'response_uri' buffer. + * @param post_auto_wnd Set this to 0 to let the callback code handle window + * updates by calling 'httpd_post_data_recved' (to throttle rx speed) + * default is 1 (httpd handles window updates automatically) + * @return ERR_OK: Accept the POST request, data may be passed in + * another err_t: Deny the POST request, send back 'bad request'. + */ +err_t httpd_post_begin(void *connection, const char *uri, const char *http_request, + u16_t http_request_len, int content_len, char *response_uri, + u16_t response_uri_len, u8_t *post_auto_wnd); + +/** Called for each pbuf of data that has been received for a POST. + * ATTENTION: The application is responsible for freeing the pbufs passed in! + * + * @param connection Unique connection identifier. + * @param p Received data. + * @return ERR_OK: Data accepted. + * another err_t: Data denied, http_post_get_response_uri will be called. + */ +err_t httpd_post_receive_data(void *connection, struct pbuf *p); + +/** Called when all data is received or when the connection is closed. + * The application must return the filename/URI of a file to send in response + * to this POST request. If the response_uri buffer is untouched, a 404 + * response is returned. + * + * @param connection Unique connection identifier. + * @param response_uri Filename of response file, to be filled when denying the request + * @param response_uri_len Size of the 'response_uri' buffer. + */ +void httpd_post_finished(void *connection, char *response_uri, u16_t response_uri_len); + +#ifndef LWIP_HTTPD_POST_MANUAL_WND +#define LWIP_HTTPD_POST_MANUAL_WND 0 +#endif + +#if LWIP_HTTPD_POST_MANUAL_WND +void httpd_post_data_recved(void *connection, u16_t recved_len); +#endif /* LWIP_HTTPD_POST_MANUAL_WND */ + +#endif /* LWIP_HTTPD_SUPPORT_POST */ + +void httpd_init(void); + +#endif /* __HTTPD_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/httpd_structs.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/httpd_structs.h new file mode 100644 index 000000000..1080a5597 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/httpd_structs.h @@ -0,0 +1,115 @@ +#ifndef __HTTPD_STRUCTS_H__ +#define __HTTPD_STRUCTS_H__ + +#include "httpd.h" + +/** This string is passed in the HTTP header as "Server: " */ +#ifndef HTTPD_SERVER_AGENT +#define HTTPD_SERVER_AGENT "lwIP/1.3.1 (http://savannah.nongnu.org/projects/lwip)" +#endif + +/** Set this to 1 if you want to include code that creates HTTP headers + * at runtime. Default is off: HTTP headers are then created statically + * by the makefsdata tool. Static headers mean smaller code size, but + * the (readonly) fsdata will grow a bit as every file includes the HTTP + * header. */ +#ifndef LWIP_HTTPD_DYNAMIC_HEADERS +#define LWIP_HTTPD_DYNAMIC_HEADERS 0 +#endif + + +#if LWIP_HTTPD_DYNAMIC_HEADERS +/** This struct is used for a list of HTTP header strings for various + * filename extensions. */ +typedef struct +{ + const char *extension; + int headerIndex; +} tHTTPHeader; + +/** A list of strings used in HTTP headers */ +static const char * const g_psHTTPHeaderStrings[] = +{ + "Content-type: text/html\r\n\r\n", + "Content-type: text/html\r\nExpires: Fri, 10 Apr 2008 14:00:00 GMT\r\nPragma: no-cache\r\n\r\n", + "Content-type: image/gif\r\n\r\n", + "Content-type: image/png\r\n\r\n", + "Content-type: image/jpeg\r\n\r\n", + "Content-type: image/bmp\r\n\r\n", + "Content-type: image/x-icon\r\n\r\n", + "Content-type: application/octet-stream\r\n\r\n", + "Content-type: application/x-javascript\r\n\r\n", + "Content-type: application/x-javascript\r\n\r\n", + "Content-type: text/css\r\n\r\n", + "Content-type: application/x-shockwave-flash\r\n\r\n", + "Content-type: text/xml\r\n\r\n", + "Content-type: text/plain\r\n\r\n", + "HTTP/1.0 200 OK\r\n", + "HTTP/1.0 404 File not found\r\n", + "HTTP/1.0 400 Bad Request\r\n", + "HTTP/1.0 501 Not Implemented\r\n", + "HTTP/1.1 200 OK\r\n", + "HTTP/1.1 404 File not found\r\n", + "HTTP/1.1 400 Bad Request\r\n", + "HTTP/1.1 501 Not Implemented\r\n", + "Content-Length: ", + "Connection: Close\r\n", + "Server: "HTTPD_SERVER_AGENT"\r\n", + "\r\n

404: The requested file cannot be found.

\r\n" +}; + +/* Indexes into the g_psHTTPHeaderStrings array */ +#define HTTP_HDR_HTML 0 /* text/html */ +#define HTTP_HDR_SSI 1 /* text/html Expires... */ +#define HTTP_HDR_GIF 2 /* image/gif */ +#define HTTP_HDR_PNG 3 /* image/png */ +#define HTTP_HDR_JPG 4 /* image/jpeg */ +#define HTTP_HDR_BMP 5 /* image/bmp */ +#define HTTP_HDR_ICO 6 /* image/x-icon */ +#define HTTP_HDR_APP 7 /* application/octet-stream */ +#define HTTP_HDR_JS 8 /* application/x-javascript */ +#define HTTP_HDR_RA 9 /* application/x-javascript */ +#define HTTP_HDR_CSS 10 /* text/css */ +#define HTTP_HDR_SWF 11 /* application/x-shockwave-flash */ +#define HTTP_HDR_XML 12 /* text/xml */ +#define HTTP_HDR_DEFAULT_TYPE 13 /* text/plain */ +#define HTTP_HDR_OK 14 /* 200 OK */ +#define HTTP_HDR_NOT_FOUND 15 /* 404 File not found */ +#define HTTP_HDR_BAD_REQUEST 16 /* 400 Bad request */ +#define HTTP_HDR_NOT_IMPL 17 /* 501 Not Implemented */ +#define HTTP_HDR_OK_11 18 /* 200 OK */ +#define HTTP_HDR_NOT_FOUND_11 19 /* 404 File not found */ +#define HTTP_HDR_BAD_REQUEST_11 20 /* 400 Bad request */ +#define HTTP_HDR_NOT_IMPL_11 21 /* 501 Not Implemented */ +#define HTTP_HDR_CONTENT_LENGTH 22 /* Content-Length: (HTTP 1.1)*/ +#define HTTP_HDR_CONN_CLOSE 23 /* Connection: Close (HTTP 1.1) */ +#define HTTP_HDR_SERVER 24 /* Server: HTTPD_SERVER_AGENT */ +#define DEFAULT_404_HTML 25 /* default 404 body */ + +/** A list of extension-to-HTTP header strings */ +const static tHTTPHeader g_psHTTPHeaders[] = +{ + { "html", HTTP_HDR_HTML}, + { "htm", HTTP_HDR_HTML}, + { "shtml",HTTP_HDR_SSI}, + { "shtm", HTTP_HDR_SSI}, + { "ssi", HTTP_HDR_SSI}, + { "gif", HTTP_HDR_GIF}, + { "png", HTTP_HDR_PNG}, + { "jpg", HTTP_HDR_JPG}, + { "bmp", HTTP_HDR_BMP}, + { "ico", HTTP_HDR_ICO}, + { "class",HTTP_HDR_APP}, + { "cls", HTTP_HDR_APP}, + { "js", HTTP_HDR_JS}, + { "ram", HTTP_HDR_RA}, + { "css", HTTP_HDR_CSS}, + { "swf", HTTP_HDR_SWF}, + { "xml", HTTP_HDR_XML} +}; + +#define NUM_HTTP_HEADERS (sizeof(g_psHTTPHeaders) / sizeof(tHTTPHeader)) + +#endif /* LWIP_HTTPD_DYNAMIC_HEADERS */ + +#endif /* __HTTPD_STRUCTS_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/MakeFSData_proj.sln b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/MakeFSData_proj.sln new file mode 100644 index 000000000..df961bb8d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/MakeFSData_proj.sln @@ -0,0 +1,20 @@ + +Microsoft Visual Studio Solution File, Format Version 11.00 +# Visual C++ Express 2010 +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "MakeFSData_proj", "MakeFSData_proj.vcxproj", "{31A9131E-BD1E-4F2D-8E1F-BC8E679E0368}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|Win32 = Debug|Win32 + Release|Win32 = Release|Win32 + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {31A9131E-BD1E-4F2D-8E1F-BC8E679E0368}.Debug|Win32.ActiveCfg = Debug|Win32 + {31A9131E-BD1E-4F2D-8E1F-BC8E679E0368}.Debug|Win32.Build.0 = Debug|Win32 + {31A9131E-BD1E-4F2D-8E1F-BC8E679E0368}.Release|Win32.ActiveCfg = Release|Win32 + {31A9131E-BD1E-4F2D-8E1F-BC8E679E0368}.Release|Win32.Build.0 = Release|Win32 + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection +EndGlobal diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/MakeFSData_proj.suo b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/MakeFSData_proj.suo new file mode 100644 index 0000000000000000000000000000000000000000..3b44ee3bfe3a05655a2381dadd8c56495d4aaac3 GIT binary patch literal 11264 zcmeHNTWlOx89vUXP1-_}20{oWT|$6ByxZAbUuq`~*=rLT*IRpIBN!2lcW3R1C%dbe zSvw}SgoMNkQl-8lRPuuQLe(c;Kp^pe5S7}82o+x1z93$ZP$gbKjrqPabL{ncFJo^~ z8tA|J=bSln=KSaU=f9rWx8FMY-p}4R`Mzj@i(P$A9u7>48h)OLh@7aRbi^ulGCUj?2RC(|a?%YV>AxTQAou3LessF@S-)oi6l>y! zxB}`G)NrL)`RLzFx81`VK(3rQa(hKHlv9@GZC+4+eWw@k9zqBx$^4$TXfSh)sh2-WNNl;mbiN) zd4MdEhUYNN%@JM*j4k#GY7_f;|F3vCBgTae@1w&Cm|_`a9$vu2ZyI_%C1%i4M2iJ~ zVWXach4yf_j2=7to_Yi~PImc$c1+ zvzQkR%xpo9F(-SM#3Jr``92O9f&ZcW(*Cmyh;%Ku-}DuPR{Cko%9OLOV|L`3*L5Ce z;r|)0k~TpO+T+4F_Jg2LD}BZv^u2Y^wJ?KfSL#B173-%a(+Y;A&)7rx|5o~Wx#lvY zpoU#>dd2~yPr4j0EPci+#{rojTTm}ajTiW2D4!O3l7D}88tl(J$ za?Y5mf!(%oH-okYq?KHcz^`i}2Gpg-+?1M9g;&?1D_N^zCqr#LO*RBEA0E7!g_S?XQfiD=`je0xT1Dm| zbAc|@VADF;qCv<%V^+qbVd*noW~@eNrQhEEG|$9;PhE#VpD{0OT3Grg&{yd{?Tv>u zJFqm=1M0txdl$aL&x}mSwI{WJwvf3&vqc==1OGn{`hNow0yE&>?BQCHev>}X*LfX! z==)7-1hrj9x#c$vxfz@c3sD^qe;mk;YxvzxCGxq^p z!>f+r%32P7Hw{VfYeU$B1n#2ZIXsEuj!!f4ZUh!*46Pd88$ruDY*ZQ2N!ztWcS?GX zW~w|f+1^LZ&EH-2Jp^AO#QmJxd6{)}A2EwPDuG)!1IcQZ^n%Z2KpS2K0Pe`X8S`wYh(S&+cQ4nNrZ)Xi2j$}#g7Aa z(q;?nkEBc5g!a9*w|)V)?*;3hf{nca30?p#pZ1oH&qBg_!D+0YvdtVkEd8&buksJO zmG)`K3GEY4O-!*C*l5PCF>oy{`Nilljb3HY+0r~_-rZ$!w{zLD-Mg8`keo*fGtNVk zM`01D<e<%R#EBZ}i$*j0#WP$o5sxL(l3lIE1WFM1|4dx_ySVE=I zDhs&*>0vx~E67T2fUn9kahE&iW9aqRsbjCjPyISN_3|^ndU@fe`xo)Dg!jFBcQU_x z`{*xDidX;eSk7eu$#of2&?X&*w{K;SsY0F)ijhWchRxgC% zy8zC=1^pS%d&BylX8)_=AjZLUDNp3E6GTh&h24SY?>tv#OdFOyaTiMWVw zuRedd&USvzy|`8y*G;`_F6$M?G##(z>Igv$TQ_jN?p0ii1y3UIqokVerU9}mp zm9Tq^KY8L*h2&jDjaFTGY0~Zld&&RLVK9|{Z`U`Tur?rp9!`1u?}3h#%g!-4@{hjs zk7uos7On5J)^_dq{y0F*U``*_{zTE&2?m>zxrYraP?fmQWcjjaQT>AMI||xA(p9jd zLz{+Y(I!8$pbQtZGKMY37T4BpXEh|_!+hdZ^!B^lTf)7NIy#H_rR2W0%AWS?a)Y}aB8PY(q>y6GQd66O6m4M_dt zdHy57u=I22dznT9FpCuyv10msp0?hC{?qd>L-)h{2Y~rMPnQ%AQ*VyhU?P=f~dfKK1-}iickroqYA@-+d?k?;kQ+Rr6J4k12P2TuLUQ&y|caP72G3 z=vY!q;G}RkIW(+ESkL}XnV(iRoDlr@6#SJ24^RA-vF+AWwHudmzlukI^t r|Fqxuw_pDCvVV#8)81^|i~SwP+yB}eq5q275tjXrw)+ttX8QjDH|eFb literal 0 HcmV?d00001 diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/MakeFSData_proj.vcxproj b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/MakeFSData_proj.vcxproj new file mode 100644 index 000000000..06914a791 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/MakeFSData_proj.vcxproj @@ -0,0 +1,91 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + + {31A9131E-BD1E-4F2D-8E1F-BC8E679E0368} + Win32Proj + MakeFSData_proj + + + + Application + true + Unicode + + + Application + false + true + Unicode + + + + + + + + + + + + + true + + + false + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) + $(LWIP_DIR)\src\include;$(LWIP_DIR)\..\contrib-1.4.0\ports\win32\include;$(LWIP_DIR)\src\include\ipv4 + + + Console + true + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + + + Console + true + true + true + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/MakeFSData_proj.vcxproj.filters b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/MakeFSData_proj.vcxproj.filters new file mode 100644 index 000000000..c88c739e6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/MakeFSData_proj.vcxproj.filters @@ -0,0 +1,36 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + + + + + + Header Files + + + Header Files + + + + + Source Files + + + Source Files + + + \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/MakeFSData_proj.vcxproj.user b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/MakeFSData_proj.vcxproj.user new file mode 100644 index 000000000..695b5c78b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/MakeFSData_proj.vcxproj.user @@ -0,0 +1,3 @@ + + + \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/fs/404.html b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/fs/404.html new file mode 100644 index 000000000..40b343a91 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/fs/404.html @@ -0,0 +1,21 @@ + +lwIP - A Lightweight TCP/IP Stack + + + + +
+ SICS logo + +

lwIP - A Lightweight TCP/IP Stack

+

404 - Page not found

+

+ Sorry, the page you are requesting was not found on this + server. +

+ 		+   +
+ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/fs/index.shtml b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/fs/index.shtml new file mode 100644 index 000000000..90358d158 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/fs/index.shtml @@ -0,0 +1,20 @@ + + + + FreeRTOS.org lwIP WEB server demo + + + +Task Stats | Run Time Stats | FreeRTOS Homepage | 37K jpg +

+

+

+

Task statistics

+Page will refresh every 2 seconds.

+

Task          State  Priority  Stack	#
************************************************

+
+
+ + + + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/fs/logo.jpg b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/fs/logo.jpg new file mode 100644 index 0000000000000000000000000000000000000000..d3670e4f0c726e023b83ad4b1a3e6bb6b2c2446a GIT binary patch literal 28602 zcmbTdc|25q{69LPgplkhQ&C7LOLkMqTA5^-5L1yg$v$LeLiR0$D5k8*GFgT!&14<2 zWu1_1WM9WRX2#4tpYQM9-+espU-#Z)#$#rjc{{Ij-tX7zxx5bR4{I89($vtz5X8m? z0;i18RuC9C&ZBJqvw{B4jqM0*pU3hzJS}e-jZI6&(|slKL(!J>z|5 zR&HK?L1EFC;;)re)wr74?{)RfEv;?s#E#Bi1A{}uBcwm0V>9I0e{=H-i%ZLtt?ixN zy?yEd?Z3F#K}j-J1E?9@$j&L`f2 z7nDPf3*AcoT+zfOrSf1?_^D4nw}`ar%tgw7q5V%}|L+0|`~MZ${|@Z`j%y5bf}IVx zc7s-%tIT+1KrvH^Ib*)f-{x{ za)U^?S82Ivq4yMOH$%D7;cf37w}f{l!>1=?TK1mucxZG&RJzVhZm9=2>!f(xSQ0TR z`v~4&g=I%K&t8+KHpW%L%X)PTB?P0b6C4cw5iF(?pzTbRVX+TAaO=0JAI0-|4*2BN z{8^xr#EW7HneCm>YPU*65_7BAB6O2}S^C3Lf^8M|LCFU0~qk5F2@3uiDHZHF&kK$>+dl{P(^u%w$f zut9!hh|gFpnRu9#VD}VE4vEEp8&Tol&E!YOyWW_?^g?j8dJ>V*eTsS2fCXxW4P!U; zo6Ptb#-G5ZF?e?B`E3^HlyM}ItLQN8eOU?W3Z$}1xaR!f>VX^D6$?%}NYbQ@w*lWA zilG}L4vs^{ZHQ&nMl8@XY$0Y3xv7%q=Px;vaEk@1!i0WAcPL~mozJ7IsM=YxK%MUi zRVr#YbQ?yKNWVv=h;lxN=qs@;M5jH3j(s4SB<*~-PAvPnO(Wq6tHaZgog&KE0sZ@s z)wb!vB`+-&XxtP&dQdrrW!`O}L$2Gw7&c@cIt(!poUMtkA=1=z(H{J#!<4h0ut2rW zED(8RbbQZt(~;=k{Sk!CbMBmnDLSgYadh0y(w*hHUvzXd z(n8bDiUHM)+rv|o7rFQABYYqB?b|l_&Ox#!}{lcR7fxq@A-62bU z`gzxXA@x7{$YGd@-i$HE{Z}WJkc5tT&b64Y`wsauS8XMv7hhxiv`M<&qJugPe4EQdhnkj2V#2=(h`&0%K9^B-5p5EFy{ zmVisb5V}Jb+TW(Mc4ipeMPQ`GtsK;|KpF5ThTx(x!EJ-BV_IV6OB3@F?m7RjGNm<{ z&BIX0xFWuN1kSvK_wX7e5xEfqoy5G@P!`B#<4iFN^j0-$@h1ypiyq7T7+AmprF>%! z^jPnpk0EbCTrp8SKoUBVR8~F3Fwj8##_;z+1%T!GdMoKL1#jgQs;92s8>2pB4rzj( zma*qsNOJem=oZ-_Y}s(`l{?jbrb4#$D#2g|=no4Nn<$BVn)=@i8l1(x{_BKD8A9qO zEy2MAV3~-0TDVoeaF`W=7oyf_Ee4|ZfhbFTfZ*<|KV|+QmMx-A&~^2cspo$ZW2%|R zXKlt9(GZ~nV$4pj?h7GU>&E6_n>psg?H}O1jv?M@{!=pclAGvpDWko0IWH5G6mz^? zVG-r>*O5#Jhe8FH&{Pr3>;t9N4X*3nWP7C~+AAmp8zIr;aL%FL>NjxV40FA>J={ol z>wy9L4+$|VCa4R{iMIa+ne3!+HgCO#wQAXL7SWv0v(|#`wj7v1+rbZ#8754%1KQ-7 zVNyB92eOv@r8lNn=Gd=kq@yb7Yrz0Zj1` z4Hl@6KxBe|m&X42%}R0hlFgi@i6LWk=>^@kHGx@hs44HA&#f)SrwQ<}<|$&Aagg z{%yVGT>P21y+q2+ZOmHpD08>*ztUB*2f>LZu3dtquMezoT4oL3fb943x_%Gm-iL0o zK+2?()00cs42IyEsr*K>?)T`~*a8_g*MD>sv~i+kWT-K&d*#XVX-1P8fgb6@}O z=Pft)A9F+2)`O3r7uq?r$Ba9yb?3}F-or&NrU6#3!By{c+BBDwEK60TT%oK zo1_?WoyqgN6v#+68yhLNlO1mi{IYY8Fz8iAN)*ZpY*fQUJtCc7-AT_MKzUv`Gb8Fepndw#WF9umhFRXhPz#wqk{^0<3G-h9GI{!K z!#!@}*4|sDlb@>fDe6K?B7(Hj!UB0E1GVyDT$`5a?0zsV9<%=UJQJ5&c5m(Ceo~f_ zvwOdlpjBl?T0HaXYa*Qeqi^xrrtWPao5B{|nm9BpEf@2c+~@stcp z?XqAli6oCVrQzNh7x z=U?;Y@V-@+oDcDvjnD_fZ!c=B7nq|-n_tFT>h1go*OCq^;hSZrAucC3lRq)Ro$a+UA zbTk0&O$_d|47_SWw$f!Gm5Ek(QK}VfF&(qtc58}D=fZ@aHk>|RPqR(>`kQI6fBw~J z_%Hly3_2XehpInYJ9i%f)V`w-#?NW+UD7LqJ54iFj0U)m%<>L88A;56{DgB57)^O# zLp2^|ABqco5aGBu|3gaEDR>BJ#KQvVk^V;03i$uQz32Jqnuv=m(EOQ}#a$j|j{~r? z&s(H4)+)D%4gpTh+!#HEmM*?=4@pe<4}{h%9c}&(gaVcLSs!QZO&`MEz>maO%xbs9 z|5QDhWic3#;YoiHRm@-bQ!i5Nl^Dk@mFO~5`}#){{H?Ise)Ge$Fct`7oRRSa%xExr zLs(6lsaZk>KrR;q(xu&gr(w)SUaXbRo+rP3Ed1nmnC3Bjc)qS2+G%>oz3UKlVcwFo?R|%&TD;O$ij*PEne)UkFLiocr3bLy+Qge z+tFxZSs=KA1!^~GG2dQu@M9sDLhNVPlm}ldKDc?Mj=4CG-%H?d{gTI>2jVw9 z7~C`2Od8#x9|pTJgP^H`V6)ww$K^V4{Hxz4`!^I&_9v9DsDEpg)1CWLZEk=(zjM>r zOwJ>XS~eT4C(cl&z~f$ox~kq&T)6*?U2`kXg*Y1vVgSW8EFIl+(_e|rokZZmOSm8F zvq`+F*5kt-Rr6P6&(*GK?Oat-!*{mc)exCYi#<7N58c$J3ybh*sl1opd0xhLc-^2; z1#d&{tAuju2Yov`q`YDO?O@gG1-I{Z=W0KZ)HqiqWA=COqB~koQfbrd^Yq49cf4Ts zXZ*0=%EDkiojubr#R(a4fBMBiD0`we{0Fe!Jc>}g=x;q6k&183iFt@yYrCB7B6lKd zlNV%Gq^>ebwmg_z!<#ASL=27)RqikCu?8_nV;B^7$0o@{=h(~*1vSVOrYOQ^wjF$m zA@gbU#KdwiuHfUN+4&SFbH)noMS@PX)ynH*9uzQ>3$n>KOLke~5sk+x@K9eh74Oxg z7-&mULQkI4`|2xG)3gGwz0xF<@)Fc@LWCH~96((-HQ|;e?U^j5{vgRW4LTS&FW*}7 zis*1oPnPncsMzWK-23RNQBEEj+e0;Kx=RdgQqkX|&l? z94~yl`S89vh|~iX*1NP~j#x3T9oV(|V0Xv*BuC6vFABe>)pn^=ClVV3Q#{(qkDL|e~boZIU$9UR)1*P}1K$EpB z5W7XunkYGcMdTv@h=FVwhgHn2wyDwdv^ku8nANqWG9q=D-)Kw-?lSYDI|FdprG$%q z$K!Fxn0*}BbCyO*>bI`?7!0J@QnW3WL9CKlQ~ApOBX_KJz#2SI1Rr~`L9ITH=E(z+ z3@OH(Hd3O~t!2d!JrJr$V}ah&C1y6_E>UVDp9~jNiQIDWH*Q()cmUJ95@f4abZYSkXQr4UF(6fQ6=?GRcJaUgn~JRlg0eTDWavNiGb*9q98 zB=lV=6}Ajc@gV9vqZ^EmRgEKpr`CM<^hRGEPg*V+VrnovPB>`uhb5`G*>z$6-n0Fk zkG=lN{AHf>ba2+(Zc?nC$nRR7Z1+F)AH}A@8bW+9)( z9l-`-!Vv>_6@fOT=em#&EYL-!OPUVxKx!XzXNuX660h<3W`GP@>~9rDQ|38$O6v%2 z+1H@!ejc^pwT==-6F)6RZ_psh-%kuNxqGQm1Zz_iA7>kD?uQnqVp~_nx*S%(PCce|sI8eAhOL`Xv zaMNbl#kP~vPSF>wrItBOskzxgSdLgqgW<}r$}<8x7k+T-m`BGQ?g%>ALWU;A<4LXM z$i9y`)wr#`H%v`LTuXWK#JxkTs}|7*^->puUC7!eaDITT~okeo-NWZp9Y3|!Iv9|ksKmSM3eESimO~yo@28X9=Wiz}@ z4R3R8cT8;x^y>BrryNE+-EDB=mUO`%y7GN{I@{?lH{> z^?FxY?pun3%#7051y8s|)!;_;lli~D-j=3Uq6JTK{+fc@?lpA??;!5_pYVJ1#dJ@* z*gE1F;;J>@r^Lwgtdi=-enqgLZx)YcOm>8pW0x2WZg%}#hjO~Fsi}Lf>*z+Y{~j%H zkfIiuIvF$YHYgY3>q%}~xHOF0jQys}`ae$Qk=CS_y7D7}$fhOvkI z*%+*E5cqb#fpGB`a|0o^RC0DOn1>o@FwMhOD3LZ(QNdLPy)O~`fskZm{Xxm^$uBaxZF3Q z`%jfU^4W!yj-=xUJ_>8d8aW|bFMJjjt^{aa^%ePO>ddq#wRkhI9nYT#zhLicT>mZ6 zg269+_bd8{LBP%%=hu)7!YQhk#b#i%zXHEaRR$EO^ijBaT=q+faem|jz1->|Y9@Ic zbBzD^J+i&E7Y~=Ucb-X*lx=BTcBzz%tCY;A4LE?-s$Ev)H!*ve-#zcN*6Y*`vIc-FLzyfG?AxZC!)gI6L`4s4r1kzvQjVNZcR*4-dCjI7V{wZas@Hn#%QUwL1X?LYFMtKO^ zb`!^KcK6dg9T4ZLTR}nKx|IlVXI=SSnVAiS0BL$ZQfa1vB3VY}7khtjJwueo;|1~W z?awR_@9thvm=60)UnE|#=68sE?n5fts21E%H8}k+kF)L^-@|>!&ULp(r`Elv0MK+e zLl`ZYL1j<(@wVG)pkD~VmWwGu2Y214N>F;ZP>(KUfc|U++mMPNDb^mI|!Tae$*e>=Y_8a~*!jJ0MboyRg zu}!Ok)6e*m>w#ApT*MhTtmQl0D{e2v)&Qk+JNO}Y$Zilu-wevNn94utCZe=kqkkxW zeS0PLxOphNV6%DKbPhEb37;k}+ zSs*_9C3(c&g;`g(Wc8EmM+}v z_}|slD&L0baIrwncd*l>&yWo}U};ua1s-PZUfWkIF{HIN<0IN0jHqc;BQI~!9HYx} zgC5dlFEuXx)AYIb-EN)*>Ta6;qVPQA8JYLo;^~R?ERw+AAEl9(QqJ8E8chMI2Cf4^4w_t_lrLI zSN<)v&ofGqlIK3OX+3aQti5lGEI93wb>ZYW&F7ex*Wj?&YqvFAc)5z@e&`;nq`6J5 zavrG&u_3QPn(B43B0np35Pv0Or_vfOCoUZLtD&ujJ*)3spQmk^^Hv{sO743M=`%f$ zAaf?ZU<8)`_&1kV6Q5R7+b1AH%~_y5{c&boHPPO*f5ht#3v|tDWj#H?-uUrx-30GRIqJQcKH*zT&sdv@YgZJ@ zKneT7A74&ItFCO~jN5nI?f2Z9bm|J$O&21M+fPyzj{b_j5_fof zU3Vo58&hKHcWG(J+I8!hC})>KbEz9GqBrdo@5ILqPhXxFi4Vt*-h<^<-D@j4d-|fb zd(u~?Amd&VG3!a>>~mXOWs=slpUG%Eelo9u7Q4|FVlx9d^%r5(DiT~)adFx!Q-xW< zKWXtF4cl4y<1f$isv+>yO&t&E=UT#2=SVA>B2JW{N0%We?St}o+M~09wj$|^RmNuh zsW-85)Pvbf9Z0T0{%FU8?faas6b03(Rne(3-uks_ll`aany$&EOaqi=0+B= zdOHMXJ6O7LE;m-b_bRu1{U)IaFp_hHzTa{BhC^A~waa}EjsRf>8e}2Pb~WY;EB)u! zrD_yt>B1}hzpf3FROK3imJYJ7wOD7>$B_MCb?U3_)Ps;)5D6%=_v<56H!Ze!ORdC) z|B3V!Oh?wlKbtUs1)yUAS(aI3k4$Zs#TpIa*$|bjD*8upTS*5q8h!tM!h}l^9@d-m zwV~?q4~j2OyLMRY=<)^)e|z{*59fy4x|(+REj7=vlzKLw7e>AquKXf#*kR_!x2r`= z+B0kkrzs#UV2qFAvduH-=^X&72C}`!r2J0r*}T&@Gyf3`EQ1`khXBwZL zTQtBCd6*?{^&&7!E2oDH|q6W-LZ5IePYep}JY-n;I}gB#pGcxnt0py``y#wdfgZD(6sLtd@2Kt2=5$lrF%vHQo9 zW-}PVqCYVp)Rh$`8;NnAZ1+RoI7KyOxz(;(nKMS(+I~Q8aklop$0B5Oe0DyHZpye? zMIlB#-zZh>%ABixs3vUiUeyyB{Hy+(w1GJrMWwa;VVj4KL%roqG1OTFcBsXYc#$0<$3#rp zwIK8TG)SA&##A7|TPH6L`K!wuUT}WKS?Om^1sz4oQ3$Q@Kay;XmM?2XTWt+>^^q(P z!%uw)ei^oK#yocZ_WxNys*+m=sYl2LgZ$%98RaSE1;pN4=z5J%5?B7`JTop z{Wy3QoPd-E6EVlWv9E1mN5-I=*mPN}2iphht~}WRlPLm2lVl{Q#r37E?`t0sek>HT zrVh+WHwZP0I0A9);~Tr(+&;N+KjYiz9F`1)6oiZ#1Y3}wKTk`EJwP|92SvEx5{rm% z0X4YfM9HLbi<|f*31d9@6~aI#jAgQI+G9f-A$*t@A)U}Z9coirpT*9qZiHX;I~)yp**x#48FwdGU+hbP z@HcaSN!@htqO3e(c5WVRB<8j8EQv2`%&oTI(4!1k_$V% z_a)>Up$ri;j4qjWH+iu`@4frzK(;eS6Ud0OF25pzT~_G;S$0FL+SjL^eZ#Bxiqk9Y zCW8mu+}MkcIsD*v(_?1B$nx2RJDshj&|Arg#~C(JGY)%3`s1_HIbHAuCfDejC|%bB z_gBZ40NaT!uzMbmaNTptzO>~p)xxSi>U#;AE{xukIk4>fQaIWCVyvnKaKI&SZGZJ7 zaBrh?k9hnj+PF4%|B$mM$$QB`2Bwz%0O@7bFr;YaQkPbMF4iRe_G4VmMqPaWbS|Ow zSJik?k^aAuVgIk1SO2G;X~Cl=xiLhC3z5yrjX7yn6% zPin^-Ve9_gU$l%5yXryaH5BmrGI2}GNd6OpOZb2!^gG_gta4%kl04&l)ui42*AB2& z&d)|5O*TbsJz+Du)n;@5D$~|F^}^@Psq$=8SeO5f%xa&U7GD+kS-mx55Ile{id@!k zdF%AEr`&N3Io%#}N{OdGEJFlvLe2_jzZgqNzLu2%S|^;bCEBo#DN#?`L9*WW zvf;v0{CToc2c$u7o&0afcU+YEvk$@#2X-}Rvblt-dLi<)RJFX(6$i+-*nJNJF}HN} zf5yL*^R^c@%P*8J)hF~OqmQoT_Z;o!lhhRanryG(o}A|(e5pLutZgtQekg}HzO2!v zElkFrJj}bYkZ_*DTQ%0Lp>DlWud)vN!ccK2%0o05Qn-%|;^aLDR*5&iBVk{#qc7_s zMMY8z)Rsu=dga-{{wNU-a+sX@1Hcn{Nu0f#GpYT4Ow-&cAyWLT&+(lL`MGJSf3Msh z@RR2~Ciir3?R-_N$%(Qv$A#~lWYYlOge~U2dzxD&>?EDi511d8SIb?<(oCZWCA-h# zu}dY<)F0k^XwJW9W+5|=z8Cxa{;=h&mR;P5IgTi_r)AH&PP* zhkR!zFS;2mr%ica>t99gIzGaz&hjinYOpQUJay;O_nh~5T=e+o4MMIPW33ndX$Y^W zWI2>!N?y4Z^a#_=(~kq*#)a0NkS_XTYU6r8LxpGh%+#aT(E4^gObGJ`J|nHwwYT;1 z7imC5$M#`k@K;jXnK~nC);^Rwnu%;5BVtgN#Ay{Osn_Lwl4InaN08gratQI{Q)Ig6 zs8LWuNPSKWT>)W4_h?Tj?vh-*BKlIMaC-pXdRG1y#DyPl$(q$SnOy(w)rt~(pBibb zIbiL@^}v6gI3njt00{I`_e2Tr?sMs<`@t2ixv_hFkL0)t^4maY^(mZJJXQxuHx0Qv zvhlG~b?oq;EYvDi?ykAg%o$e*_o2mM82Wi%_#U{*D1vdVm|Apqv%F!ZLC`C($UU{J zBJ*99_*0j2CIso}GymQinNp3I+?sTGMEGe}R#Kdr?EmzM;$JW9xnMnld-~Sy(9It$pHAC)$S;ZrSGKqR^`#~Ndyd`r zI!K@yv_MazxzX(aG;muF93o7;&t#+OmyRLATZvG6<$(ngZ-v6N9A(sf7i>NQNgGVz-#mnh^} z-|JxFnmVOce={Ma+f(Mlnih`QNmt8#`|NE_5X9eiIMaisI8fc?DR`%Pa5eYgm9_K6 z=VOi?x$wn`eG!D^KYRT0i!3b0ro&;XbSprlyustoz#NYm{KcxO!5+LAn!TxiO7QZYZfOlgL;^E%jVX@qa*?P z@CMUfZy%?)csJK1bg2U6%()VeQtL8&S7MnUyCLJ%*n7=4C3g9VNzsHpvvSOd1qxQa zTqmZsf8*xs>+#m=(K@1eh@8=xA=O2hzt`rUA2HZJp((sCtYK~9kZng$1F+ZbT!!|m zO1-PO_0VWNzKoyDOWz0W`NoZjUgCNy}tIw51YQ|;c%Kh$gA5wmiDEkWT}Q! zvsTX&Jz}ZX>V(#+eI(N)zfl{aK47Bh8s3baR=ja|&3*zk7g@5lcnj-?nM}eKDI(+o z0lBaK-jP_@PaHBJ5)mw*)<-pN^elzTb0!oy#V1CH&RI}j^UuO95&QPQ3G;2D)qE;H zWn4Dir7##I24x^(sof_|zL5xtbLXpAyl#pzRPJv1 z>&bqALyWe;jM%L2;P8ihk1XqevM=yo+2{Oq)Zuq^`v|UtSC{YfvR{Q{u>^?9=(1iE-mt=WF*0m_;@Dq z^JSG4s>(!}iFJ6mo@nk5A{h+8`E%(&cHw=T_v`~SpveMgEdB%hpN+no4hrZZdpDSp zSCE%N>C%2)8uvE_FG@eYiy|ieeK;|jrZRu|cebe8g&#uZ4sNd>ln6ckW%^B%Yie!`WxbY7Vk?H9`u+0K{^E<{eWL{j7r~o?q|F|` z18hX{m^#ex@-H8;GbcSpP-hta`2LHrM2A4aV6V`l9Ot-|!vMgTkE&4!#WS< zkRwxi#1bRP`~!D+uyOx=8;7PZwr#$im;1afMQ3-o;M%);C^v3!rXL>UySs9J$lSy@uLt4^7sGHet_|f!?AcE}ZD(JE zYbQ;ICJk{@SAOc9O>NV=GU)e*r1$)n#2=TeUG&&^J9rF#wet6qkfy?xc~iFOUrhYW z4Z!m$(cinXi5|nfnh0?EWv7%O0GZVFn6BuV7ms&UNC*0_jwv(})huBxXZ6->cKI;R zB(oj8JWoX=3LXCx%obZ^to492DV^4TfGZUC0kJ&;UgIsM>d$m% z-C3laFmXd3es&CcU z>!kGWM&B6>XWw+TVjJ8X;dc;t@5-C#r{mJSA6JuO#(&;*d}~xeB`~=#bRBB*Qn}OS zFQdqx&^T4LCNk19R zO*e}^{@5}{g&^(Zvb$kQagHe)H}Wo8xh}eC%x2DR_iPc+a2=9{s(Fae)wS<%Z&w`aW@Tis#fzO zpNwBBtB&YR;q3^NQR~(F-Iqv~nCXySP1^>bT;ZQj>!loi*m%P{(OA=K%hNvFZ)2H6 zQd?1*0au;<%}eHa`ZxJREMfnT%mJ*ync&pv{_5^gnNhp-0KFnEMRx(9ferg|m0LDn zSC+j4;>PQ>nj>B@DDe8#=>E6e+Y2nvE%^gjZ`u;N`q+1WsHE~6f@*r?k+x=GJYTraq<>juEbnl$>X4zv9%(6jP!dpDj|)Jm)8)r~=J z?C#)#lvWpVkx@2mB{?P84lU^cq!WehZ~@tX|YO7UE9HRA+nEyz#+_b)W3sZZ%k zMk>SX%F`cQU|oPOQz=_B_C-xytrgVN+=h?x9Te1+_`KZ<-|H)irtTF?jXT)YjIRB& zxldF6m^26Q8GLi&WkTg3J=1TlQ%$j(9{peh8mXi2NzUf$v#5UF_A<0);i5!6=A{pW zdjvaiUZeN2ci>&R&>-w4AnC=+=694s$x2CUI-I$*@o&_^Med)VA4 z(?jjZZ;1(9Po;4=lhL#j_>3!Orp#UQdlZn#%h84&Dt4PA8Dx3KV+Bu+t|H%j;R5Rq zp@fSK?tT_8w~_y>npLIq3Yg0~aU;rZu)(ELvyeK@Y%$63w?^|Gy=s6hb-6zjQIE6kB{6W z{N;lCi&_E)aaOEQPw&@L_h*o^e;7A^JH=1q2HH^xTbTX?={N$5A-HS*NH-_u#0=m=)wX5Upn=S{Qk+x+gw0UhOADRS-bdeU zs^%a9dgJ0y`lW^q>LshtI%)>R!eWiLAmJNiqY;o|E4jCmL^|h|sxSsvN1$HVjf>P$ zOOUlOY7!dy!K<;i&^uaNm9mSY2UEO8A5=az+@@D$$qm6q!KD!ohH9?I{Ry#(Q6ziLR zXS?)+FCoHhzf-(oly>jLaW zd&ZCwnB>=`+wj?jBL!n{hBUd^`mH(n)7V!K`xqX2K6lx&I0jQRRiX!r`l9JeE^1(A zUKFx6iep$5A;8U9ebKled|$!Rbzivso%q#QRmFv~R13H}vKVWCQUFfL(PZj?ntWtU zf5^EJ1$nUxInC&6j#mOou6{gn<7cn@E_~0OLWpHv4B^{Mie-2_b1bBW+g8~fD5(DP zi`B@#_<3eD@$NIO&Sm3ICVvk$nA~-gJf?8QYNziET{AwoHvYx2^w8kA$LfE8+GQI5VjMrOH$Tuc(YQmF+p=0LyGNZCsZ{Mu7^dvh#ED}H3< zR7F?Fm!GGM#idFA`PKQE1wrKqakR2kukgcuAE)6s=~}##L{y-#RioK%Sh0 z|0^*gS3zXU^v+Yiwj3d~j6(B9%HZLfvF|6$XB$A5yr_v53l#Q3CtUL%bwqmF$K+^*&KCRq(V9q=1386AIqouXQfeCI@Jv#lvm ztoUj_W#+5aT_%q-=|Or>kWY&>KAPcH9giiMEu7_yihK-mnttZxQAFQQY?Lh~(qF;IeB?^j05a^jRflw#4>1fWgz{e>*3lv$qcG&sE zixJJai%nO7r+X{cs6p1TJs9oxN|RF^vbnJbQr)`nJ+HcJ)RC<-GfowbNe|9KT1f+r zWg(w8Z&AwhF1nc(@mx*6L<@S3elNU>zz%D;hx}1=0G2`K4uUiI`f3|cAXoT}FKfpP zjB#B|4l_EP?kw{f^lz}|B?}~u>sy6J)qj2zRBNgrBuS@wF#^3A@)!Y|`*~W}+~+Y} zDT?+<>9`-(_k3;eL(e3f>a*wN4<}kbqJ&Lj`N^8A#`84UUSlKde?w^#t$ket;ks;NZ^R@`UfhXp6@L6J> zhuZB#Ruvx~4u4Y<%xz+#fiG%-Syzre>hjX@6zbPZ=#S+7rg3h_YKOCZBSLvOo_Vf+ zM%kY2Ly6Ow4o=FK^&89DNhkt@L>`SiR(PbUNVi^Zh4%MAYv-9^NGWjoxA}alsJ;{} z`poVuhkjs@sjphe8Q;S>-K1?s#SSDAFHd!8?LQy&Aa=w@v$o-hVE9sJ6N3wz?27%| zwcTiVM6c&n|0*q5r9M%yK)9=3Zy}K^_g2S8>ht2SpW&9fyy&|F_i^i=JzVn|2QLE+ zX>h?SiQ(Mcd4I@RL7Fl$lRrpp4{95X;BYFZ%UagE_dJg~L>6^~;T^&YUr_qAoC$x`zI|z7lRz|$q?TW$2${i^B z$2T$PM&h?aqzc?JM30JgoK}#&`GSMw1A3wO{z*RMH(xV8PVSdW(w8DNcaOlS&a>a2 ztCsxQm{Ds~n^}SLxYpD^OGyjk7~@(dHh_J6(5Hul9*|aEzHw_ayxa*kOEK*rQlPQV zL(Ugu>zfDMdAuYp+mQHhwy4%Y^JlRiE6i)QC=Z<=^K+4nSX|%*o^wX57F}VGK zU&2|5@|9u`WK;ORdw5!}VAuUtB60@Ec5bBgPM&v9sIk=5z>_*6%9cSvxn(Q9U1bS- zR*yXWki;z81IOD`3i-#G%lEuRicT^mzH9-cJ?JG`hvZd=8ob_ZJfy0b%T6sT3F3>_zEw^jmzjyN{6Z{l0cdjGVG z&s?+dK^IYZb-+be&z5Gyh94Iym{z+$ zNfWeyUdL2j5tVja8|&HqsrNm#3*h$tIYtr|b(BUK3Gzx`C)f%=xw}To=i!2=K|Lis z8R`db*Tj2;DHx}l<7gZHg;3xYE^K+DFWEKZ?2H1;=7YrZX*VI@#_A_9%2Uo+I7U{{ zzX#?QKWJ~?ZS#K1X0#GI@A2<@xImYgs#F7sc7Ty+eHhhwLNze8VTT2Z(n~)~2?75b zo$}Z!JQ39yojhKL&0EQ!dd=i-W`z6oXj;k}om5I(4JMg8Oxj1$YEBE$c6arX*rOgk z(vb_e2|s~udW2WQM4_u1_4q44bPek~^WU=``}3?ix-=F1lGt@iJIc$Ho!+S$0b3zx5$9^EYRhh{=a>Z1Q!Cw65$j|6Cv87)$=dlv~_W* z-MBqe{;0XQ_jjlLCtFEA@-z`@4@JU^dUn&RO;YjyXzjbAnh4u&QB)K}q*sZ8NC`z0 z1O8UZNshK%}=sRCWj^(n%QLXdLB_Gz@QiIO1ifCB+bGD8*16wrFr7GGLftOahuO9dJIYYQAsFrwh|?{ zMOhdP$?-^h(=~rnB8>_;rt|D<)g5_wFTAOnNuP`h_GA?|8Y~5ics;FrZi*}gXX7oq z&iln*7k+GU1(ynnK>)^xtQ4U@Lf)@+fte2EftLAfBfCiTo5sh2`GpDf9|mAEIS{OO z;=bBt%g486u@o)jjzr8^M>KBGWY!M+ijyyB-`03JR>w5HZFpqggY7U>;y`+QG7KO& z2P>jKU|_4IsZwaF_jBzQE69&eCZY6JB#)}&X4{Nf6cHt4x?Js=RjegF{NwPYo)FTG zwURH)`{s*cf8t3bL>u@NSPeVto>EDo$0mrzTgMSY+-V!C1>_v@rn+WN;JIfV#8$o^8@G0z~hdSIR- zcw7%?>8@|Z2`4_<)BTsKhzIwabNj)C^A%UoQ_9t}sizU;bJw%t4svscE6iib3EBZJ z;<3(|ANk)(=ukj0c?R7lk0jD|hZ0Ow+{_hPW zG~gUR)AT$&wgXkkEp69)k&j_}EAJ1Dv=H3B8U{VVcDQxTssj_VH1kGNbB-yN^#`|J z2eb&qej#HT4IPY>m9*gR2Xfu599DJI9UsTsk{Tq$Z%N5VD?}dEz02+i z5D*f9s_BFaAzuoeL>g86&gMK)v)gNB+B|C`K2qYnW6ZsDpHsI#AH(~L^IZWi|Es`V zrM2!t*}yM$eV`*bCYkD#K<};>X3~&Z*5>BpVZU2Y|K}1hj;9KLC-V8(H54rwGobFELJtToIGZen_lq4>?duoZRqV% zP}`jIV1DVN$2_sJ!aZ2m=oP~lqfSK+B81ZyVnP1UqNsD`B1)MP)6E&g=MH%76-!Yv z9G>|8d04pQE7f#ygu675kDT$-Y+BbsOOJ}JaD(nZI0 z$2~!iPFwy}HzI->dR8TO7!OPIN`tL!&!(SM9Jg|Mq@r`BnVQVBTRLWW8<&JSNCoK16n>Y0;S|L1&+a{g~K(IG8$vy+O|9*^_ojO{8@?&#}% zKd_~*ueqaN4c+E$4NTp1v!YLL(u=PBSo)T**0-I(`5sl|3X5?cnsolha4OIu3mdN( zJg6^}T0Gt*vr)ByNNkxJwREiDb0y7Jrg+7^l$efNz_GXXH%ko^ShL<3AA*RQUtfF^ zKM@LQa>@-Lb7T1LR=R9{ns&n$$y}$d)%fOJvwe3-wLXvxk-0g)fq&1H6!P{waZ6*@J}+@74QCJXx=e>y<~V zyBt5Ez6aVT4u@uS)DfwC`C@!)sG!S)TtkLdn-7NABM-NH%J+s4EZ_|3m4@7s5}gWZK?GjQ(3Ev(tEHDqGYDuvMzH#%L8 z3=VP?{rOAzAA>8w5ROLjUtwR0-$s1`;gBXt`?z*0ogyE2{e$epl6U{dAS)mAP*KGd z<4j*6h#M&F>~2kD46W_Qb~yc>8`c}GrkG-0*rh@;MF+( zr-R^@YgGk}a_HV)j<^Ao)!J@eH?Lu{vv{b(fEuzF(u>Q#niorjXn8~EPiwf`81 z_6_Kh^xllK$xXsaeZ(PbKfyHJU8`iCA^7s+n;O4GW50fUbB23~OP^^$GX^#jF?OM) zNoN)wQFRz7gcda!h@TImVKq_z817;^QGyP}*1Vgcm08PUSpVHvw4Y4ztSG5>8}{DxUhZxy)E77++723;_psujCwpMR9CoWJNOliHgfcWkD7QB?IMGj(zh z{565QiRNvDFDtEl9Lcxt$&3E{^9Pow65qF#+=v9Oz*}L_I93Hc!6nAKVLC$u#}d*m z%Sb5knYVsRVENT?pL2dE1O~vPeD@g9$CDkt!z#RVj=Xvm&!D_>`u&!HIo47d)u0Pf#ypCqV^;%JIc?qqD5(_GWLl<7q_y_p zo*`rRr^E&nYVe_mi{C?6)}elG)+3(!P-R2WYw^ePZ;IbOiM;3g^)1-9HLoG}jw)$0 z17~u`5E>9Q#nP_y2uiSPFg)y)pq&iV1MxHnDD#-rdzoUn?h4nz;J#kDU*rYWqBC_pVVZoZ+D5GS8O%wziMxC%V0R8uaj1HSMDsll5XZaDV1= zMvj8uOIXTX%lZ;s93JvOV2>t4NaE)V?Z*3#}8v&!i*Me0HSQa$HQz~ z2q=DY#y-T*s~N;=0UWrd2V5s~W-?(^N3ed(+0 z=6h-?o3bf)D>ly+ImTwFuN6?!aE}z>fQZCpP+$o(`>VoI$Lao$q0OGV8yvph9JN;b zu$RD>%*QHzW3NEG6?Zym7burY??rPdykJE&!@13gd5Ogna&)|vF`D8;_33Zm0o}_~ z!{9M1^|^lxy%q3BPSa!!NK{fAU5qYG4gpggaw{wwkvlpjl1Cz17(jD)7ztsu4xYMT z!VlKv`W!B#E*L||`uH(Xy=R7m&?1Qor6TX(H0JA8kHHS0laFXw3TyVQHX!^wY#n3Wk1_`jKq1mO1_v%)B)zxVqr8J$VV>X?fRxflq+2e; zFd7aOBWEy3hzr-5m*nn6ilO5J2=$G6DOv~oNDtK-t1lNQH!Jv$!Ei4i9KWm>*b+by zq$}Mw`Mr$~aa9FXBjL2Or*PNS1Lcd&;>G(h&qXn* zuU1iA#vb2detegj3X4==sn~7P20!!{xbd_nhdg5S!m<)~(n17vs`&D{6U zr-0Up!|WTSupM7a>%?LmpMt3@e!NbJ&P*fo>@r#+8+D)QIby#9;4oiyT3*A=6v8XK zChpE{R!(L?X23w0%Lphtqy%w}5GgIxwsY)=e~Z#SyETk%Uh9$G%V=GP(U>n;xu$|s zeQJov#?*p8-OA=%Vhr^-c=&W=J10%j^d@Tg8h-CH0L$m*ndVmIz3KW6cHSJMU~}55 z*lCEbjhX(iut>k#r!CgXohOV3@|Xpl&*j(78%4%V2!Ox3E5^0il}_~X+I@05ZvmGa zg*?CVBV|ibrQLm?^QRX`t^)LcCSo@f@?x_pyhMJWW61syLQg%c3#ofE2eZiZm{zK$ zxcsodanquOoJr=T*u8;?4D~I8(Ns7RQ!eojP=x7-9pShqN_s)4d$Im4-r;@c?2{!!#_3z&nBrC)Vv2srOn*zi{5#yhO3kLJ29H&BoZE<2lg zC3E(@61hg7rux-0pc9B#!Mp-ebwI|xS;Bp9I*cy(>mNhu^$B(AX#RIA$agN2xm^^M zXVJnK@(M6`wmR{<Kvlg~Ona!tNp10sJu71+2(a@a>SW)cvpT{DlsJAn zA^6(glMtsiUvUU$Ldx5j2)6KfE1sjXA{G$!W*YOv@S0{&)-DAir>_ebvt+HWK#7y! zq191tO{>=GM4?Z`%GbTqltdjT=X3GjYpGtK--x=s{- zTbXSE7q6NL7T}Xx;-GN{NZS-hM6U(jQefb{kFC!*`Zg zqKdVVB>_fPpfPj50*-jp1!-iq9afxXw{iL+-%{6p{+ z4{Aa0W1Wr1thzb z{NjS*J~GyBOI0TShC3KiG9$;Qv#_enbpRrwpjU)`rBV)K?@j>nb+z-87cR3C+S{u{{^fb)w>N=>jxna(xtU z7*_DYE$+s<9C^f8=UL?2v>tS3pq~9OQ_`za+wiPd<2!R6=$xQRw@sEiKlM!vqBa$` z_!T7kzL@oBY406C*qfx%n*L;?YbWc8*_ma;P1iWNNgPZlNs$bX*tEg;90oBNF8yQbT>6Z{m*cdnp^_`7+lzHA8m#$8 zGUZng7y7;U@K3ADBK47{3@rxrnNp?^ozqN;SL~_*gPDTS>IwkSn*bbmg%r?RAjc|A z|LBrYjq)f97byw0MLt985p{;Z&I06bMX*7F)lkj8Nyk)c!zJIU=^w+_KhTV$g3MDy zkCJnE?Iq+(WZkJMUp+cZ)C8nFJZgf&uo)Emc;zvAggfDj^go7y`fQLDW{En@m*Qr? zo*Nb+bOk_cJ-?WjGK@j}VTXUi>O)1hm5jh|74v;_XL=OPrKsaEPV%>WL!=*gl|J5} zpN=Xjf|OIu%HjgfV3iC3f(N{4P@hM0?pzLtyaqt)_775)FB6yRa(||+ ziDX(A>(x^HUCNtNssog5r%?uB&onTYy;16M;!mmN)~b5lQF_ek-o**x?EAc-Kg1H{!4 z^Q$njmfq-wVRT7pT*)$1g}F1wFUbCWkoyRZtikr)D}Ka<`y z=kSPs4DA|kE7bT0s6GTMvBcuQ`-P*4bAkb*oR9<)n>@q-j&~=~r~>##pmB%D`{tRgzyvV;)>~?~eCAaBH#JQ8vEuX!vF2`%b6i&Sz+>Me0q((@*4qsuB z3gg8-XpO2x`hkJP9)xW2j{#+z?YBA`)o|;e+Cmbx-}SEEVvv4eLnD7dOw zJ&oaH3pkhT$>}Cm5xC*0JSn7t;z5xD$M}y?8{hQ4!S|1{?$p4Zdg1_??)p1}2rg|V z59bobLj}b_Q*gYTsZ19^?Drukv(c{ps!BLW#I(OMP!H+CkA49a$eZMMbHP5dDBe+f zpuXGfBIMK1h~qTb7=*IDt&1Z9Np*Q;bpD-GJ``oJRNXrdj#6e=_d=781Z2DHQSTbYJW5;bL!b zV}1~ROTvhOt-oY23GDP?cmv~Fq`=<0>E*WsvJxbfrYDt((kSUfTYTJ1N7#NWOdGgw z9yIWHs@Qqv`eNWy(NV~;=I!!_n|cEG6v4X?j z$23Ki0Di0C-1x0nnsxUQeOpg>yggAE)Nuf=Z_WN+tk6~tt7Z)M>P##i{td@T7jT&7 zre5-yrMa@*7<*oQ(?oFQBU{pg+u?X(yQ%<{1fVIh0CAS5;QDxR@|eb26Vf%iwMq39 zq%jCJn|7euDf3}&!g35s=^&I9t@rx^@ra%X% z^!@c~Qw_bP>tGoR%=M$VSJ{IoXJDdmMX+}?RA)o=A;G;5eztyl@)Cdsr@S-&SBW4p zntr8f*}r=igEnbPj-yeuOvs8Nff~?#!bga^?sIo};3a+ADAne9b==M;2o@4~scmB$ z7|y|wt`n5YYLnXP0vpjB&*(Bu|y4?eILim_1Dz~Ufo zZxTmRnO$a>x~fMpDsZ9P2kZjvtZ?K@aOTny*GZwL@AW_IBLuiwS5cgu z#RiA`yeO<>{rWe^qKW9{<3zd1`XeGyv|WGObyIDAE^BGm4#vGw#$KhLPNyiA69l3N zdB7I~g6ZuUM0jqQjre2@Xew-I(XRRkn@nZv3qb_jC(``oYVtb|h5$9FZ|vC@2l&C^ z)$pvn0$lA9ioG|W1&utz1x6lImpwM%r+1E?~}*XqB3i*u#IJD1~P>+PM0`Y zAo{0-Q&{KZsLWNd&hL|{wHljkvpLwlwWlU22KSTJbiZ@^b3{-Vb z%?qJPL%dV2WeT>~zR5nzYzQaywlZJ+-Cad*IiaP5pm6|2w2)SpbP?N6lfq8*YwU6- zLn1soG&_Sp>K$zKX{dOPQe^-E&X+tT?AaEGSIG1ku;g20=ObtCWn3_Qc^(m3xKtFI znV?{o!lHgfo&W1e@ICfF;`#p;(f@C+pIlBIF*XB`z#Wsu0sh%Vao67 zQw8WB4*o7v{s((;^+1`rO?lmQIy~{SoGNvQJInUK{pY`C7x#|gRX-FE*S|T{C8S9 zM#L8No7eaiGM3eKC+;6Zkap8fu@&1ZPaXf$bYQY-is^*> zUDR`d@AdTNFiJkpo3>K=zExXx*bd!Q_Q6#BE;7*UBM;uZ_6PBzPn~-r=uS#*2eWpL z)%|ZXMQ7jZWxiD|ah}1yS3D5VsXIQ>_55A$d)}pN=6MX#7In<(b4g+g4r_?qyfcC^ zu{wwit|?Zev31sNw^7-=jKM6wuVHUYV(-sos>~>%;MUGQmL|-SGKp`=|%WZXes00rXPI{2|#^842e_0k{+x2 zk5>UED~~0a7rxCGWlzt%=?r__zY2(M`ESgOM80}s=9L$!`=DTZIDIU@t!oful~F0S$CLw0@4ZBY9u$hFG%opAFSR`PTaLtyTw9s#PozjuE#=Bo@1l^?t; zz(c?HeFJGX&1-Czd;e2AAU7g2)ZfC(2m^9JYiYsj(2plo`14n_O*hI1??f=0us&Ryg8Hg)U$ z#8=bo@SJz|Gi6Zs4QOayY)D58>MvE#NcV{+rRuR-jIrp*29c6nj>;0)f{@_n8`YdO zVcG_SFE3y?dvV&f0qu)y{9Tg#_o;LW-X7H|&2rq3@z~zdY@I?&d2c5WLfgG#Qf8_QdVTZfGnPRFW{OaaW z@ui~=Cw@bWf7Px6u7NMs*qV)&5MsWFK$m*G zR-BsgL8!b6a@y#Y(})4B^A}TJk!>?yNG;L!a*a+)ViW5dEPwJyj2X_M~fE^P3`5Ye;3YZM*jERp(qRkZxdl+9mki)n+E zv?AFN;g=8S+|~H+r~q2q1CL^%`o7)A>fGB#RV2$|%~S?P+89Xu3OyHEf#fa4T940M z^`m`417~D%QD3j?Sc^GR9y^rN$WcHV_-~n1l^e&Nu~CNlgz!uxmSCtARAZVj9p)+@RS9_l^@?fI0V8>Dm`2JuiefW=<lbg@O(C63n%fMcKdqrx|FtJ$L);TN8}x?s3fb^zfV^k^=WpUgO_&nyir z48t5zTr0CmV~%u4{HZ|NsMyb_XVeE^ite&6CJZ@~RL_*u`CC|FGkXR_>b|F<^17+m z_|NF`UB?t;19bfsrJ8*{H||iw?EVUH%aZ~&0YSg+9!Y!u&nK<`Ljwlj?lVfbGRy~Ye4LLTJ8b$d zKs))|3ei+8{cCHt6|OrBUNzTtcP6>h8)m0Rsa+WsACMr#YYf7kE2p3ji#{mAOzmq`-%g5@pDbz}P` z81xn+8>(p$wN~dZJ947VT0pb4$nN=pWmp3d z&C;9f2F4>CTpoi&%21NphO?j`?{BGDa^CeP&Q^uERxAJky03O&c6X3>%}n4Y0@-}_ zsVWY)z1QJ$&f-Z!>#1$BT)BHy1cW&l)&_(^>YUnyKh1)eAom|kfafY9E8uTs!F1%a z&%wfh2WrlcXdDG2mxotwxxgeOX9sudAn#x&#f6bN74 zC%7MsOpV~m!a~3)MEbE&Rxot#2rtSxhpl*<5xxM$ui*0=o=gA8Gk4y&nbSCw+=Q%y z@U(3T%g#hrfCz85vb$^jjdEHNKU(R0lgaG{4;-A#^?wY{>K?s&vZ#%8>4EKOH<~%G zYJKjX?XvWKL*?IIL)^v&+TBsBw1WwZ*2DZOR}RD07P**w}%|A z?ZfJE-km_ZI%fMOoh##^Ix8i&kVJwq6oWp{?ej}!E{KV479{8=B1lcBEEBM5;sm_= z?<{7u+^U5m`t>Lvv&3hA^msw6Q`*m{6Rr$kKaib+Xe!#O8WpzfyMgL!eT?tSX7?Nt zF$M~y#}uUkA3WdBbO%|4(W`$9?8VksR2nt0V3q3)TTPHS!D$T!R%p)2`!B9IH**qH zHTfrvvw(Zc#m$iyy<`K8>4LlrmXA8v8_aBUnYS|_o9VO$q zO;k^g)ss_nsmc_)^AxxBTeHoH$>W-Td2p3i(wg@3ad9O&Zetb?()pQT0sz+OYK9N9 z^UC*&FxaYvCipNKIb_`6&x~Rp2TJDj-Uss9S37;S3g#-MHWcf9SKEN-W8<&85dqUc z&v3_?>mh9vqXypuLf2ab@AxwDdgq~Us4l6xC%lKF#(GI#)a(MPzy|+TJbY+q34<#2=3 zsXDRgb;Q0wKuy`~Qy=leNSX#M8D={vxaUV6zbU_B4XwXR`&K}V_S(wCUphuL-3mCi z{QNa0wa22)LZS02w}+5n>kHV7zi2<5H&AT=!3{7zAm_#hzw)fH4Ym-f@v>K2YfjiL zE&O=)$w;r53tNAG`B7+PFc_Kqf0Q0cj=S$+QFA8`@PM|>Qa%vaYZD<6=R@(Zw?RVkxPpIgpbeicOxv7H3_ za}-Cf=$$iX+gB3b5~-<%D&0$%g09Q^`d4d^y_sQ~`L-%Lk!9idSi zmBoFZV~>;GRftR*sq8aT6=T|Ck7}4jgHi2x5RH67?8Vy$WoLzBLCvOd3L! zIb!PXh6RDe4wElYJjHa5j$e4W)di(MqSVxIv=2fFdqKvncaV$4k8te*zw2o46>U3W z7j=@C*4efQ0#F@*~)CVk4OTadgQ-T&+40 z!(;Q0!E#Z9{>XXfmDg9V;wdY=>{Pro>g*w|iHhn{!H*iY3`gJXQ#3%WH>|;~LU|~A z0h`7dIoV}{-xzBenhs4?elF{(4yx8*M>}ONG}YtY!7keaW|*2bczcL4tOehU?OBA289N-p`??~=KP7Lpt{oKLNjDGW&T!yVYOcTe>b^nACd52+L3sp z9w6=(8K|qOgpmIQXI)M``Sr==YWI;4h!o9q4(W~4@FdCNA61zalP+ST&vBd{VxTe< zMOo8?Zufth#Ah~;NqpvBSLSNW+X)CBsvtSGy^!olnS literal 0 HcmV?d00001 diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/fs/runtime.shtml b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/fs/runtime.shtml new file mode 100644 index 000000000..e66202b9d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/fs/runtime.shtml @@ -0,0 +1,20 @@ + + + + FreeRTOS.org lwIP WEB server demo + + + +Task Stats | Run Time Stats | FreeRTOS Homepage | 37K jpg +

+

+

+

Run-time statistics

+Page will refresh every 2 seconds.

+

Task            Abs Time      % Time
****************************************

+

+
+ + + + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/fsdata.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/fsdata.c new file mode 100644 index 000000000..f2ddfd935 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/fsdata.c @@ -0,0 +1,2068 @@ +#include "fs.h" +#include "lwip/def.h" +#include "fsdata.h" + + +#define file_NULL (struct fsdata_file *) NULL + + +static const unsigned int dummy_align__404_html = 0; +static const unsigned char data__404_html[] = { +/* /404.html (10 chars) */ +0x2f,0x34,0x30,0x34,0x2e,0x68,0x74,0x6d,0x6c,0x00,0x00,0x00, + +/* HTTP header */ +/* "HTTP/1.0 404 File not found +" (29 bytes) */ +0x48,0x54,0x54,0x50,0x2f,0x31,0x2e,0x30,0x20,0x34,0x30,0x34,0x20,0x46,0x69,0x6c, +0x65,0x20,0x6e,0x6f,0x74,0x20,0x66,0x6f,0x75,0x6e,0x64,0x0d,0x0a, +/* "Server: lwIP/1.3.1 (http://savannah.nongnu.org/projects/lwip) +" (63 bytes) */ +0x53,0x65,0x72,0x76,0x65,0x72,0x3a,0x20,0x6c,0x77,0x49,0x50,0x2f,0x31,0x2e,0x33, +0x2e,0x31,0x20,0x28,0x68,0x74,0x74,0x70,0x3a,0x2f,0x2f,0x73,0x61,0x76,0x61,0x6e, +0x6e,0x61,0x68,0x2e,0x6e,0x6f,0x6e,0x67,0x6e,0x75,0x2e,0x6f,0x72,0x67,0x2f,0x70, +0x72,0x6f,0x6a,0x65,0x63,0x74,0x73,0x2f,0x6c,0x77,0x69,0x70,0x29,0x0d,0x0a, +/* "Content-type: text/html + +" (27 bytes) */ +0x43,0x6f,0x6e,0x74,0x65,0x6e,0x74,0x2d,0x74,0x79,0x70,0x65,0x3a,0x20,0x74,0x65, +0x78,0x74,0x2f,0x68,0x74,0x6d,0x6c,0x0d,0x0a,0x0d,0x0a, +/* raw file data (544 bytes) */ +0x3c,0x68,0x74,0x6d,0x6c,0x3e,0x0a,0x3c,0x68,0x65,0x61,0x64,0x3e,0x3c,0x74,0x69, +0x74,0x6c,0x65,0x3e,0x6c,0x77,0x49,0x50,0x20,0x2d,0x20,0x41,0x20,0x4c,0x69,0x67, +0x68,0x74,0x77,0x65,0x69,0x67,0x68,0x74,0x20,0x54,0x43,0x50,0x2f,0x49,0x50,0x20, +0x53,0x74,0x61,0x63,0x6b,0x3c,0x2f,0x74,0x69,0x74,0x6c,0x65,0x3e,0x3c,0x2f,0x68, +0x65,0x61,0x64,0x3e,0x0a,0x3c,0x62,0x6f,0x64,0x79,0x20,0x62,0x67,0x63,0x6f,0x6c, +0x6f,0x72,0x3d,0x22,0x77,0x68,0x69,0x74,0x65,0x22,0x20,0x74,0x65,0x78,0x74,0x3d, +0x22,0x62,0x6c,0x61,0x63,0x6b,0x22,0x3e,0x0a,0x0a,0x20,0x20,0x20,0x20,0x3c,0x74, +0x61,0x62,0x6c,0x65,0x20,0x77,0x69,0x64,0x74,0x68,0x3d,0x22,0x31,0x30,0x30,0x25, +0x22,0x3e,0x0a,0x20,0x20,0x20,0x20,0x20,0x20,0x3c,0x74,0x72,0x20,0x76,0x61,0x6c, +0x69,0x67,0x6e,0x3d,0x22,0x74,0x6f,0x70,0x22,0x3e,0x3c,0x74,0x64,0x20,0x77,0x69, +0x64,0x74,0x68,0x3d,0x22,0x38,0x30,0x22,0x3e,0x09,0x20,0x20,0x0a,0x09,0x20,0x20, +0x3c,0x61,0x20,0x68,0x72,0x65,0x66,0x3d,0x22,0x68,0x74,0x74,0x70,0x3a,0x2f,0x2f, +0x77,0x77,0x77,0x2e,0x73,0x69,0x63,0x73,0x2e,0x73,0x65,0x2f,0x22,0x3e,0x3c,0x69, +0x6d,0x67,0x20,0x73,0x72,0x63,0x3d,0x22,0x2f,0x69,0x6d,0x67,0x2f,0x73,0x69,0x63, +0x73,0x2e,0x67,0x69,0x66,0x22,0x0a,0x09,0x20,0x20,0x62,0x6f,0x72,0x64,0x65,0x72, +0x3d,0x22,0x30,0x22,0x20,0x61,0x6c,0x74,0x3d,0x22,0x53,0x49,0x43,0x53,0x20,0x6c, +0x6f,0x67,0x6f,0x22,0x20,0x74,0x69,0x74,0x6c,0x65,0x3d,0x22,0x53,0x49,0x43,0x53, +0x20,0x6c,0x6f,0x67,0x6f,0x22,0x3e,0x3c,0x2f,0x61,0x3e,0x0a,0x09,0x3c,0x2f,0x74, +0x64,0x3e,0x3c,0x74,0x64,0x20,0x77,0x69,0x64,0x74,0x68,0x3d,0x22,0x35,0x30,0x30, +0x22,0x3e,0x09,0x20,0x20,0x0a,0x09,0x20,0x20,0x3c,0x68,0x31,0x3e,0x6c,0x77,0x49, +0x50,0x20,0x2d,0x20,0x41,0x20,0x4c,0x69,0x67,0x68,0x74,0x77,0x65,0x69,0x67,0x68, +0x74,0x20,0x54,0x43,0x50,0x2f,0x49,0x50,0x20,0x53,0x74,0x61,0x63,0x6b,0x3c,0x2f, +0x68,0x31,0x3e,0x0a,0x09,0x20,0x20,0x3c,0x68,0x32,0x3e,0x34,0x30,0x34,0x20,0x2d, +0x20,0x50,0x61,0x67,0x65,0x20,0x6e,0x6f,0x74,0x20,0x66,0x6f,0x75,0x6e,0x64,0x3c, +0x2f,0x68,0x32,0x3e,0x0a,0x09,0x20,0x20,0x3c,0x70,0x3e,0x0a,0x09,0x20,0x20,0x20, +0x20,0x53,0x6f,0x72,0x72,0x79,0x2c,0x20,0x74,0x68,0x65,0x20,0x70,0x61,0x67,0x65, +0x20,0x79,0x6f,0x75,0x20,0x61,0x72,0x65,0x20,0x72,0x65,0x71,0x75,0x65,0x73,0x74, +0x69,0x6e,0x67,0x20,0x77,0x61,0x73,0x20,0x6e,0x6f,0x74,0x20,0x66,0x6f,0x75,0x6e, +0x64,0x20,0x6f,0x6e,0x20,0x74,0x68,0x69,0x73,0x0a,0x09,0x20,0x20,0x20,0x20,0x73, +0x65,0x72,0x76,0x65,0x72,0x2e,0x20,0x0a,0x09,0x20,0x20,0x3c,0x2f,0x70,0x3e,0x0a, +0x09,0x3c,0x2f,0x74,0x64,0x3e,0x3c,0x74,0x64,0x3e,0x0a,0x09,0x20,0x20,0x26,0x6e, +0x62,0x73,0x70,0x3b,0x0a,0x09,0x3c,0x2f,0x74,0x64,0x3e,0x3c,0x2f,0x74,0x72,0x3e, +0x0a,0x20,0x20,0x20,0x20,0x20,0x20,0x3c,0x2f,0x74,0x61,0x62,0x6c,0x65,0x3e,0x0a, +0x3c,0x2f,0x62,0x6f,0x64,0x79,0x3e,0x0a,0x3c,0x2f,0x68,0x74,0x6d,0x6c,0x3e,0x0a, +}; + +static const unsigned int dummy_align__index_shtml = 1; +static const unsigned char data__index_shtml[] = { +/* /index.shtml (13 chars) */ +0x2f,0x69,0x6e,0x64,0x65,0x78,0x2e,0x73,0x68,0x74,0x6d,0x6c,0x00,0x00,0x00,0x00, + +/* HTTP header */ +/* "HTTP/1.0 200 OK +" (17 bytes) */ +0x48,0x54,0x54,0x50,0x2f,0x31,0x2e,0x30,0x20,0x32,0x30,0x30,0x20,0x4f,0x4b,0x0d, +0x0a, +/* "Server: lwIP/1.3.1 (http://savannah.nongnu.org/projects/lwip) +" (63 bytes) */ +0x53,0x65,0x72,0x76,0x65,0x72,0x3a,0x20,0x6c,0x77,0x49,0x50,0x2f,0x31,0x2e,0x33, +0x2e,0x31,0x20,0x28,0x68,0x74,0x74,0x70,0x3a,0x2f,0x2f,0x73,0x61,0x76,0x61,0x6e, +0x6e,0x61,0x68,0x2e,0x6e,0x6f,0x6e,0x67,0x6e,0x75,0x2e,0x6f,0x72,0x67,0x2f,0x70, +0x72,0x6f,0x6a,0x65,0x63,0x74,0x73,0x2f,0x6c,0x77,0x69,0x70,0x29,0x0d,0x0a, +/* "Content-type: text/html +Expires: Fri, 10 Apr 2008 14:00:00 GMT +Pragma: no-cache + +" (85 bytes) */ +0x43,0x6f,0x6e,0x74,0x65,0x6e,0x74,0x2d,0x74,0x79,0x70,0x65,0x3a,0x20,0x74,0x65, +0x78,0x74,0x2f,0x68,0x74,0x6d,0x6c,0x0d,0x0a,0x45,0x78,0x70,0x69,0x72,0x65,0x73, +0x3a,0x20,0x46,0x72,0x69,0x2c,0x20,0x31,0x30,0x20,0x41,0x70,0x72,0x20,0x32,0x30, +0x30,0x38,0x20,0x31,0x34,0x3a,0x30,0x30,0x3a,0x30,0x30,0x20,0x47,0x4d,0x54,0x0d, +0x0a,0x50,0x72,0x61,0x67,0x6d,0x61,0x3a,0x20,0x6e,0x6f,0x2d,0x63,0x61,0x63,0x68, +0x65,0x0d,0x0a,0x0d,0x0a, +/* raw file data (762 bytes) */ +0x3c,0x21,0x44,0x4f,0x43,0x54,0x59,0x50,0x45,0x20,0x48,0x54,0x4d,0x4c,0x20,0x50, +0x55,0x42,0x4c,0x49,0x43,0x20,0x22,0x2d,0x2f,0x2f,0x57,0x33,0x43,0x2f,0x2f,0x44, +0x54,0x44,0x20,0x48,0x54,0x4d,0x4c,0x20,0x34,0x2e,0x30,0x31,0x20,0x54,0x72,0x61, +0x6e,0x73,0x69,0x74,0x69,0x6f,0x6e,0x61,0x6c,0x2f,0x2f,0x45,0x4e,0x22,0x20,0x22, +0x68,0x74,0x74,0x70,0x3a,0x2f,0x2f,0x77,0x77,0x77,0x2e,0x77,0x33,0x2e,0x6f,0x72, +0x67,0x2f,0x54,0x52,0x2f,0x68,0x74,0x6d,0x6c,0x34,0x2f,0x6c,0x6f,0x6f,0x73,0x65, +0x2e,0x64,0x74,0x64,0x22,0x3e,0x0d,0x0a,0x3c,0x68,0x74,0x6d,0x6c,0x3e,0x0d,0x0a, +0x20,0x20,0x3c,0x68,0x65,0x61,0x64,0x3e,0x0d,0x0a,0x20,0x20,0x20,0x20,0x3c,0x74, +0x69,0x74,0x6c,0x65,0x3e,0x46,0x72,0x65,0x65,0x52,0x54,0x4f,0x53,0x2e,0x6f,0x72, +0x67,0x20,0x6c,0x77,0x49,0x50,0x20,0x57,0x45,0x42,0x20,0x73,0x65,0x72,0x76,0x65, +0x72,0x20,0x64,0x65,0x6d,0x6f,0x3c,0x2f,0x74,0x69,0x74,0x6c,0x65,0x3e,0x0d,0x0a, +0x20,0x20,0x3c,0x2f,0x68,0x65,0x61,0x64,0x3e,0x0d,0x0a,0x20,0x20,0x3c,0x42,0x4f, +0x44,0x59,0x20,0x6f,0x6e,0x4c,0x6f,0x61,0x64,0x3d,0x22,0x77,0x69,0x6e,0x64,0x6f, +0x77,0x2e,0x73,0x65,0x74,0x54,0x69,0x6d,0x65,0x6f,0x75,0x74,0x28,0x26,0x71,0x75, +0x6f,0x74,0x3b,0x6c,0x6f,0x63,0x61,0x74,0x69,0x6f,0x6e,0x2e,0x68,0x72,0x65,0x66, +0x3d,0x27,0x69,0x6e,0x64,0x65,0x78,0x2e,0x73,0x68,0x74,0x6d,0x6c,0x27,0x26,0x71, +0x75,0x6f,0x74,0x3b,0x2c,0x32,0x30,0x30,0x30,0x29,0x22,0x3e,0x0d,0x0a,0x3c,0x66, +0x6f,0x6e,0x74,0x20,0x66,0x61,0x63,0x65,0x3d,0x22,0x61,0x72,0x69,0x61,0x6c,0x22, +0x3e,0x0d,0x0a,0x3c,0x61,0x20,0x68,0x72,0x65,0x66,0x3d,0x22,0x69,0x6e,0x64,0x65, +0x78,0x2e,0x73,0x68,0x74,0x6d,0x6c,0x22,0x3e,0x54,0x61,0x73,0x6b,0x20,0x53,0x74, +0x61,0x74,0x73,0x3c,0x2f,0x61,0x3e,0x20,0x3c,0x62,0x3e,0x7c,0x3c,0x2f,0x62,0x3e, +0x20,0x3c,0x61,0x20,0x68,0x72,0x65,0x66,0x3d,0x22,0x72,0x75,0x6e,0x74,0x69,0x6d, +0x65,0x2e,0x73,0x68,0x74,0x6d,0x6c,0x22,0x3e,0x52,0x75,0x6e,0x20,0x54,0x69,0x6d, +0x65,0x20,0x53,0x74,0x61,0x74,0x73,0x3c,0x2f,0x61,0x3e,0x20,0x3c,0x62,0x3e,0x7c, +0x3c,0x2f,0x62,0x3e,0x20,0x3c,0x61,0x20,0x68,0x72,0x65,0x66,0x3d,0x22,0x68,0x74, +0x74,0x70,0x3a,0x2f,0x2f,0x77,0x77,0x77,0x2e,0x66,0x72,0x65,0x65,0x72,0x74,0x6f, +0x73,0x2e,0x6f,0x72,0x67,0x2f,0x22,0x3e,0x46,0x72,0x65,0x65,0x52,0x54,0x4f,0x53, +0x20,0x48,0x6f,0x6d,0x65,0x70,0x61,0x67,0x65,0x3c,0x2f,0x61,0x3e,0x20,0x3c,0x62, +0x3e,0x7c,0x3c,0x2f,0x62,0x3e,0x20,0x3c,0x61,0x20,0x68,0x72,0x65,0x66,0x3d,0x22, +0x6c,0x6f,0x67,0x6f,0x2e,0x6a,0x70,0x67,0x22,0x3e,0x33,0x37,0x4b,0x20,0x6a,0x70, +0x67,0x3c,0x2f,0x61,0x3e,0x0d,0x0a,0x3c,0x62,0x72,0x3e,0x3c,0x70,0x3e,0x0d,0x0a, +0x3c,0x68,0x72,0x3e,0x0d,0x0a,0x3c,0x62,0x72,0x3e,0x3c,0x70,0x3e,0x0d,0x0a,0x3c, +0x68,0x32,0x3e,0x54,0x61,0x73,0x6b,0x20,0x73,0x74,0x61,0x74,0x69,0x73,0x74,0x69, +0x63,0x73,0x3c,0x2f,0x68,0x32,0x3e,0x0d,0x0a,0x50,0x61,0x67,0x65,0x20,0x77,0x69, +0x6c,0x6c,0x20,0x72,0x65,0x66,0x72,0x65,0x73,0x68,0x20,0x65,0x76,0x65,0x72,0x79, +0x20,0x32,0x20,0x73,0x65,0x63,0x6f,0x6e,0x64,0x73,0x2e,0x3c,0x70,0x3e,0x0d,0x0a, +0x3c,0x66,0x6f,0x6e,0x74,0x20,0x66,0x61,0x63,0x65,0x3d,0x22,0x63,0x6f,0x75,0x72, +0x69,0x65,0x72,0x22,0x3e,0x3c,0x70,0x72,0x65,0x3e,0x54,0x61,0x73,0x6b,0x20,0x20, +0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x53,0x74,0x61,0x74,0x65,0x20,0x20,0x50, +0x72,0x69,0x6f,0x72,0x69,0x74,0x79,0x20,0x20,0x53,0x74,0x61,0x63,0x6b,0x09,0x23, +0x3c,0x62,0x72,0x3e,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a, +0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a, +0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a, +0x2a,0x2a,0x2a,0x2a,0x3c,0x62,0x72,0x3e,0x0d,0x0a,0x3c,0x21,0x2d,0x2d,0x23,0x72, +0x74,0x6f,0x73,0x5f,0x73,0x74,0x61,0x74,0x73,0x2d,0x2d,0x3e,0x0d,0x0a,0x3c,0x2f, +0x70,0x72,0x65,0x3e,0x3c,0x2f,0x66,0x6f,0x6e,0x74,0x3e,0x0d,0x0a,0x3c,0x2f,0x66, +0x6f,0x6e,0x74,0x3e,0x0d,0x0a,0x3c,0x2f,0x62,0x6f,0x64,0x79,0x3e,0x0d,0x0a,0x3c, +0x2f,0x68,0x74,0x6d,0x6c,0x3e,0x0d,0x0a,0x0d,0x0a,}; + +static const unsigned int dummy_align__logo_jpg = 2; +static const unsigned char data__logo_jpg[] = { +/* /logo.jpg (10 chars) */ +0x2f,0x6c,0x6f,0x67,0x6f,0x2e,0x6a,0x70,0x67,0x00,0x00,0x00, + +/* HTTP header */ +/* "HTTP/1.0 200 OK +" (17 bytes) */ +0x48,0x54,0x54,0x50,0x2f,0x31,0x2e,0x30,0x20,0x32,0x30,0x30,0x20,0x4f,0x4b,0x0d, +0x0a, +/* "Server: lwIP/1.3.1 (http://savannah.nongnu.org/projects/lwip) +" (63 bytes) */ +0x53,0x65,0x72,0x76,0x65,0x72,0x3a,0x20,0x6c,0x77,0x49,0x50,0x2f,0x31,0x2e,0x33, +0x2e,0x31,0x20,0x28,0x68,0x74,0x74,0x70,0x3a,0x2f,0x2f,0x73,0x61,0x76,0x61,0x6e, +0x6e,0x61,0x68,0x2e,0x6e,0x6f,0x6e,0x67,0x6e,0x75,0x2e,0x6f,0x72,0x67,0x2f,0x70, +0x72,0x6f,0x6a,0x65,0x63,0x74,0x73,0x2f,0x6c,0x77,0x69,0x70,0x29,0x0d,0x0a, +/* "Content-type: image/jpeg + +" (28 bytes) */ +0x43,0x6f,0x6e,0x74,0x65,0x6e,0x74,0x2d,0x74,0x79,0x70,0x65,0x3a,0x20,0x69,0x6d, +0x61,0x67,0x65,0x2f,0x6a,0x70,0x65,0x67,0x0d,0x0a,0x0d,0x0a, +/* raw file data (28602 bytes) */ +0xff,0xd8,0xff,0xe0,0x00,0x10,0x4a,0x46,0x49,0x46,0x00,0x01,0x01,0x00,0x00,0x01, +0x00,0x01,0x00,0x00,0xff,0xdb,0x00,0x43,0x00,0x03,0x02,0x02,0x03,0x02,0x02,0x03, +0x03,0x03,0x03,0x04,0x03,0x03,0x04,0x05,0x08,0x05,0x05,0x04,0x04,0x05,0x0a,0x07, +0x07,0x06,0x08,0x0c,0x0a,0x0c,0x0c,0x0b,0x0a,0x0b,0x0b,0x0d,0x0e,0x12,0x10,0x0d, +0x0e,0x11,0x0e,0x0b,0x0b,0x10,0x16,0x10,0x11,0x13,0x14,0x15,0x15,0x15,0x0c,0x0f, +0x17,0x18,0x16,0x14,0x18,0x12,0x14,0x15,0x14,0xff,0xdb,0x00,0x43,0x01,0x03,0x04, +0x04,0x05,0x04,0x05,0x09,0x05,0x05,0x09,0x14,0x0d,0x0b,0x0d,0x14,0x14,0x14,0x14, +0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14, +0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14, +0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0x14,0xff,0xc0, +0x00,0x11,0x08,0x00,0xea,0x02,0x71,0x03,0x01,0x22,0x00,0x02,0x11,0x01,0x03,0x11, +0x01,0xff,0xc4,0x00,0x1f,0x00,0x00,0x01,0x05,0x01,0x01,0x01,0x01,0x01,0x01,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09, +0x0a,0x0b,0xff,0xc4,0x00,0xb5,0x10,0x00,0x02,0x01,0x03,0x03,0x02,0x04,0x03,0x05, +0x05,0x04,0x04,0x00,0x00,0x01,0x7d,0x01,0x02,0x03,0x00,0x04,0x11,0x05,0x12,0x21, +0x31,0x41,0x06,0x13,0x51,0x61,0x07,0x22,0x71,0x14,0x32,0x81,0x91,0xa1,0x08,0x23, +0x42,0xb1,0xc1,0x15,0x52,0xd1,0xf0,0x24,0x33,0x62,0x72,0x82,0x09,0x0a,0x16,0x17, +0x18,0x19,0x1a,0x25,0x26,0x27,0x28,0x29,0x2a,0x34,0x35,0x36,0x37,0x38,0x39,0x3a, +0x43,0x44,0x45,0x46,0x47,0x48,0x49,0x4a,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5a, +0x63,0x64,0x65,0x66,0x67,0x68,0x69,0x6a,0x73,0x74,0x75,0x76,0x77,0x78,0x79,0x7a, +0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8a,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99, +0x9a,0xa2,0xa3,0xa4,0xa5,0xa6,0xa7,0xa8,0xa9,0xaa,0xb2,0xb3,0xb4,0xb5,0xb6,0xb7, +0xb8,0xb9,0xba,0xc2,0xc3,0xc4,0xc5,0xc6,0xc7,0xc8,0xc9,0xca,0xd2,0xd3,0xd4,0xd5, +0xd6,0xd7,0xd8,0xd9,0xda,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,0xea,0xf1, +0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xff,0xc4,0x00,0x1f,0x01,0x00,0x03, +0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01, +0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0xff,0xc4,0x00,0xb5,0x11,0x00, +0x02,0x01,0x02,0x04,0x04,0x03,0x04,0x07,0x05,0x04,0x04,0x00,0x01,0x02,0x77,0x00, +0x01,0x02,0x03,0x11,0x04,0x05,0x21,0x31,0x06,0x12,0x41,0x51,0x07,0x61,0x71,0x13, +0x22,0x32,0x81,0x08,0x14,0x42,0x91,0xa1,0xb1,0xc1,0x09,0x23,0x33,0x52,0xf0,0x15, +0x62,0x72,0xd1,0x0a,0x16,0x24,0x34,0xe1,0x25,0xf1,0x17,0x18,0x19,0x1a,0x26,0x27, +0x28,0x29,0x2a,0x35,0x36,0x37,0x38,0x39,0x3a,0x43,0x44,0x45,0x46,0x47,0x48,0x49, +0x4a,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5a,0x63,0x64,0x65,0x66,0x67,0x68,0x69, +0x6a,0x73,0x74,0x75,0x76,0x77,0x78,0x79,0x7a,0x82,0x83,0x84,0x85,0x86,0x87,0x88, +0x89,0x8a,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9a,0xa2,0xa3,0xa4,0xa5,0xa6, +0xa7,0xa8,0xa9,0xaa,0xb2,0xb3,0xb4,0xb5,0xb6,0xb7,0xb8,0xb9,0xba,0xc2,0xc3,0xc4, +0xc5,0xc6,0xc7,0xc8,0xc9,0xca,0xd2,0xd3,0xd4,0xd5,0xd6,0xd7,0xd8,0xd9,0xda,0xe2, +0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,0xe9,0xea,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9, +0xfa,0xff,0xda,0x00,0x0c,0x03,0x01,0x00,0x02,0x11,0x03,0x11,0x00,0x3f,0x00,0xfd, +0x53,0xa2,0x8a,0x28,0x00,0xa2,0x8a,0x28,0x00,0xa2,0x8a,0x28,0x00,0xa4,0x34,0x8e, +0x70,0x09,0xaf,0x0b,0xf1,0xbf,0xc6,0x4b,0x8f,0x13,0x78,0xc2,0xdb,0xc1,0x7e,0x0f, +0xb8,0x2b,0x24,0x93,0x08,0xae,0xf5,0x48,0x88,0x3b,0x47,0xf1,0x2c,0x7f,0x4e,0x72, +0xdf,0x97,0xad,0x72,0x62,0x71,0x54,0xf0,0xb1,0xe6,0x9e,0xef,0x44,0xba,0xb6,0x73, +0x57,0xc4,0x43,0x0e,0x93,0x9e,0xef,0x44,0xba,0xb6,0x77,0xbe,0x3b,0xf8,0xb9,0xa1, +0xf8,0x16,0x39,0x23,0x9d,0xe4,0xd4,0x35,0x05,0x1c,0x58,0x59,0x2e,0xf9,0x3d,0xb7, +0x76,0x51,0xf5,0xfc,0x8d,0x78,0x07,0x8a,0xff,0x00,0x69,0x3f,0x1b,0x6a,0xb3,0x3a, +0x69,0x3a,0x7f,0xf6,0x2d,0xb7,0xf0,0x81,0x09,0x96,0x5f,0xc5,0x98,0x63,0xf2,0x15, +0xf4,0xde,0x83,0xe0,0xdd,0x27,0xc3,0xf6,0x62,0x0b,0x6b,0x38,0xc9,0x3f,0x33,0xcb, +0x20,0xde,0xf2,0x37,0x76,0x66,0x3c,0x92,0x6b,0x40,0xe9,0x16,0x47,0xad,0x9c,0x1f, +0xf7,0xec,0x57,0x9d,0x88,0xc2,0xe3,0x31,0x2b,0xf8,0xbc,0x8b,0xb2,0x5f,0xad,0xce, +0x3c,0x46,0x1b,0x13,0x88,0x56,0x8d,0x5e,0x45,0xe4,0xbf,0x53,0xe0,0x8d,0x4f,0xc6, +0xfe,0x33,0xd5,0x18,0x9b,0xcd,0x5f,0x56,0x90,0x93,0x9c,0x19,0xa4,0x0b,0xf9,0x0e, +0x2b,0x35,0x75,0xff,0x00,0x10,0xc7,0x9c,0x6a,0x3a,0x82,0xfa,0xfe,0xfa,0x41,0xfd, +0x6b,0xf4,0x19,0xb4,0x2d,0x39,0xba,0xd8,0x5b,0x7f,0xdf,0xa1,0xfe,0x15,0x19,0xf0, +0xce,0x94,0xff,0x00,0x7b,0x4d,0xb5,0x3f,0xf6,0xc5,0x7f,0xc2,0xbc,0x79,0x64,0x15, +0xa4,0xef,0xed,0xaf,0xf2,0x7f,0xe6,0x78,0x72,0xc8,0x6a,0x49,0xdd,0xd7,0x7f,0xd7, +0xcc,0xf8,0x0d,0x3c,0x5f,0xe2,0x68,0x94,0x05,0xd6,0x35,0x45,0x03,0xa0,0x17,0x32, +0x0f,0xeb,0x53,0x27,0x8f,0xbc,0x59,0x11,0x25,0x75,0xfd,0x59,0x33,0xe9,0x77,0x28, +0xfe,0xb5,0xf7,0x8b,0x78,0x3b,0x44,0x7e,0xba,0x4d,0x99,0xff,0x00,0xb6,0x2b,0x51, +0x37,0x81,0x7c,0x3c,0xf9,0xce,0x8d,0x66,0x73,0xff,0x00,0x4c,0x56,0xa5,0x64,0x58, +0x85,0xb5,0x6f,0xcc,0x9f,0xec,0x2a,0xeb,0x6a,0xef,0xf1,0xff,0x00,0x33,0xe1,0x6f, +0xf8,0x59,0x3e,0x2f,0x5f,0xf9,0x98,0xb5,0x7f,0xfc,0x0c,0x93,0xfc,0x69,0xeb,0xf1, +0x4f,0xc6,0x51,0x9c,0xaf,0x89,0x35,0x5c,0xfb,0xdd,0x3f,0xf8,0xd7,0xdc,0x0d,0xf0, +0xf3,0xc3,0x6f,0xd7,0x44,0xb2,0x3f,0xf6,0xc8,0x54,0x4f,0xf0,0xcb,0xc2,0xaf,0xf7, +0xb4,0x2b,0x23,0xff,0x00,0x6c,0x85,0x2f,0xec,0x4c,0x5f,0xfc,0xfe,0xfc,0xc5,0xfd, +0x89,0x8a,0x5b,0x57,0x7f,0x89,0xf1,0x54,0x7f,0x17,0xfc,0x6b,0x1f,0xfc,0xcc,0x9a, +0x99,0xfa,0xdc,0x35,0x58,0x8b,0xe3,0x87,0x8e,0xe1,0x6c,0xaf,0x89,0x2f,0x73,0xd3, +0xe6,0x21,0x87,0xe4,0x45,0x7d,0x8e,0xff,0x00,0x09,0x7c,0x20,0xfd,0x74,0x0b,0x3f, +0xc2,0x3c,0x54,0x2f,0xf0,0x6b,0xc1,0xaf,0xd7,0x41,0xb5,0x1f,0x45,0xa4,0xb2,0x7c, +0x72,0xda,0xb7,0xe2,0xc7,0xfd,0x8f,0x8d,0x5b,0x62,0x1f,0xe2,0x7c,0x8a,0x9f,0x1f, +0xbc,0x7e,0x83,0x1f,0xf0,0x91,0x5c,0x7d,0x4c,0x71,0x9f,0xfd,0x96,0xa6,0x1f,0xb4, +0x37,0x8f,0xc7,0xfc,0xcc,0x12,0xfe,0x30,0x45,0xff,0x00,0xc4,0x57,0xd5,0xaf,0xf0, +0x43,0xc1,0x4e,0x0f,0xfc,0x48,0xa0,0x1f,0x4a,0x89,0xbe,0x03,0xf8,0x21,0xf3,0xff, +0x00,0x12,0x48,0x86,0x7d,0x09,0xa7,0xfd,0x95,0x98,0xad,0xab,0x7e,0x2c,0x3f,0xb2, +0xb3,0x15,0xb6,0x21,0xfd,0xec,0xf9,0x69,0x7f,0x68,0xaf,0x1f,0x8f,0xf9,0x8f,0x39, +0xfa,0xdb,0xc5,0xff,0x00,0xc4,0xd4,0x89,0xfb,0x48,0x78,0xf9,0x08,0x3f,0xdb,0x59, +0xc7,0xad,0xb4,0x47,0xff,0x00,0x65,0xaf,0xa6,0x9f,0xf6,0x7d,0xf0,0x33,0x8e,0x74, +0x75,0x1e,0xe1,0x8d,0x42,0xff,0x00,0xb3,0x9f,0x81,0x9c,0x7f,0xc8,0x2d,0x97,0xe9, +0x21,0xa3,0xfb,0x33,0x34,0x5b,0x56,0xff,0x00,0xc9,0x98,0xbf,0xb3,0x33,0x35,0xb5, +0x7f,0xc5,0x9f,0x39,0xc7,0xfb,0x4d,0xf8,0xf1,0x17,0x07,0x52,0x85,0xcf,0xab,0x5a, +0xa6,0x7f,0x95,0x58,0x4f,0xda,0x9b,0xc7,0x49,0x8f,0xf4,0x9b,0x36,0xc7,0xad,0xaa, +0xf3,0xfa,0xd7,0xbe,0xbf,0xec,0xd5,0xe0,0x86,0xc9,0x16,0x32,0xaf,0xd2,0x43,0x50, +0x3f,0xec,0xc5,0xe0,0xa6,0xe9,0x6f,0x3a,0xff,0x00,0xdb,0x4a,0x5f,0xd9,0xf9,0xb2, +0xda,0xaf,0xfe,0x4c,0xc3,0xfb,0x3f,0x36,0x5b,0x57,0xfc,0x59,0xe2,0x0b,0xfb,0x57, +0x78,0xdd,0x7a,0x9d,0x39,0xbe,0xb6,0xc7,0xfa,0x35,0x3d,0x7f,0x6b,0x0f,0x1a,0x82, +0x32,0x9a,0x61,0xff,0x00,0xb7,0x66,0xff,0x00,0xe2,0xeb,0xd9,0xdb,0xf6,0x5a,0xf0, +0x63,0x0e,0x12,0xe5,0x7f,0xed,0xa5,0x42,0xff,0x00,0xb2,0xa7,0x83,0xcf,0x47,0xbb, +0x5f,0xfb,0x69,0x43,0xc1,0xe7,0x0b,0x6a,0x9f,0xf9,0x30,0x7d,0x4b,0x37,0x5b,0x56, +0xfc,0x4f,0x23,0x5f,0xda,0xd7,0xc6,0x43,0xad,0xbe,0x96,0xdf,0xf6,0xc1,0xff,0x00, +0xf8,0xba,0x91,0x3f,0x6b,0x8f,0x16,0x82,0x37,0x59,0x69,0x6d,0xeb,0xfb,0xa7,0xff, +0x00,0xe2,0xeb,0xd4,0x24,0xfd,0x93,0xbc,0x2a,0xd8,0xdb,0x75,0x78,0xbf,0xf0,0x20, +0x6a,0x07,0xfd,0x92,0x3c,0x34,0x73,0x8b,0xfb,0xb5,0xf4,0xe9,0x4b,0xea,0xb9,0xca, +0xfb,0x7f,0x88,0x7d,0x53,0x39,0x5b,0x55,0xfc,0x4f,0x3d,0x8b,0xf6,0xbe,0xf1,0x32, +0xe7,0xcc,0xd2,0xb4,0xc7,0xf4,0xc2,0xc8,0x3f,0xf6,0x6a,0xb0,0x9f,0xb6,0x16,0xbc, +0x31,0xbb,0x43,0xd3,0x5b,0xd7,0x0d,0x20,0xfe,0xb5,0xda,0xc9,0xfb,0x22,0xe8,0x19, +0xf9,0x75,0x3b,0xa0,0x3d,0xd4,0x54,0x0f,0xfb,0x21,0x68,0xe4,0x7c,0xba,0xbd,0xcf, +0xe2,0x82,0x9f,0xb1,0xce,0x97,0xda,0xfc,0x50,0x7b,0x0c,0xe9,0x7d,0xbf,0xc8,0xe6, +0x07,0xed,0x89,0xaa,0xf7,0xf0,0xf5,0x99,0xfa,0x4e,0xdf,0xe1,0x4f,0x5f,0xdb,0x1b, +0x50,0x1f,0x7b,0xc3,0x96,0xa7,0xe9,0x72,0xdf,0xfc,0x4d,0x6f,0x3f,0xec,0x7f,0xa6, +0x1c,0xed,0xd6,0xe7,0x5f,0xac,0x60,0xd4,0x12,0x7e,0xc7,0xb6,0x99,0x1b,0x35,0xd9, +0x31,0xef,0x17,0xff,0x00,0x5e,0x8e,0x4c,0xed,0x75,0xfc,0x85,0xec,0xf3,0xb5,0xf6, +0xbf,0x23,0x35,0x7f,0x6c,0x7b,0xc3,0xf7,0xbc,0x35,0x01,0x1e,0xd7,0x67,0xff,0x00, +0x89,0xa9,0x93,0xf6,0xc8,0x70,0x06,0xef,0x0b,0xa9,0x3d,0xf1,0x7b,0xff,0x00,0xd8, +0x54,0xaf,0xfb,0x1e,0xa0,0x5f,0x97,0x5d,0xe7,0xde,0x2a,0x85,0xbf,0x63,0xe9,0x32, +0x76,0xeb,0xa9,0xed,0x98,0x8d,0x2f,0xf8,0x5b,0x5d,0xff,0x00,0xf2,0x50,0xb6,0x76, +0xba,0xfe,0x44,0xeb,0xfb,0x64,0xc4,0x7e,0xf7,0x85,0xdf,0x1e,0xd7,0xa3,0xff,0x00, +0x8d,0xd4,0xcb,0xfb,0x63,0xda,0x63,0xe6,0xf0,0xcc,0xc0,0xfb,0x5e,0x03,0xff,0x00, +0xb2,0x56,0x63,0xfe,0xc7,0xd7,0x7d,0xb5,0xc8,0x4f,0xd5,0x0d,0x40,0xff,0x00,0xb2, +0x06,0xa6,0x01,0xdb,0xad,0x5b,0x13,0xee,0x84,0x53,0xf6,0x99,0xda,0xe8,0xfe,0xe8, +0x87,0x3e,0x78,0xbf,0xa4,0x6f,0x27,0xed,0x8b,0xa7,0x13,0xcf,0x87,0x2e,0x40,0xff, +0x00,0xaf,0x95,0x3f,0xfb,0x2d,0x48,0x3f,0x6c,0x3d,0x27,0x1f,0x37,0x87,0xaf,0x01, +0xf6,0x9d,0x0f,0xf4,0xae,0x59,0xbf,0x64,0x2d,0x68,0x1e,0x35,0x6b,0x53,0xef,0x83, +0x50,0x37,0xec,0x8d,0xe2,0x11,0xf7,0x75,0x0b,0x46,0xfc,0x4d,0x4f,0xb7,0xce,0x97, +0xd9,0x7f,0x72,0x17,0xb5,0xce,0xd7,0xd9,0xfc,0x11,0xdd,0x45,0xfb,0x5f,0xf8,0x74, +0xb7,0xcf,0xa3,0x6a,0x4a,0x3d,0x54,0xc6,0x7f,0xf6,0x6a,0xb3,0x1f,0xed,0x75,0xe1, +0x36,0x5c,0xbe,0x9b,0xab,0x2b,0x7a,0x08,0xe3,0x3f,0xfb,0x3d,0x79,0xb4,0x9f,0xb2, +0x67,0x89,0x54,0x1c,0x5e,0x5a,0x13,0xfe,0xf1,0xa8,0x1b,0xf6,0x50,0xf1,0x5f,0x69, +0xad,0x1b,0xfe,0x07,0x42,0xc5,0x67,0x0b,0xec,0x3f,0xb9,0x0f,0xeb,0x39,0xd2,0xfb, +0x1f,0x82,0x3d,0x54,0x7e,0xd6,0xfe,0x0e,0xce,0x0d,0x96,0xae,0x07,0xaf,0x93,0x1f, +0xff,0x00,0x17,0x4f,0x1f,0xb5,0xaf,0x83,0x31,0xff,0x00,0x1e,0xba,0xb7,0xfd,0xf8, +0x4f,0xfe,0x2e,0xbc,0x85,0xbf,0x65,0x4f,0x18,0x0f,0xbb,0xf6,0x46,0xff,0x00,0xb6, +0xb5,0x03,0xfe,0xcb,0xbe,0x34,0x4c,0xe2,0x0b,0x76,0x03,0xd2,0x51,0x43,0xc7,0x66, +0xeb,0x7a,0x7f,0xf9,0x28,0x7d,0x73,0x39,0x5f,0xf2,0xeb,0xf0,0x3d,0xa9,0x7f,0x6a, +0xff,0x00,0x05,0x36,0x3f,0x75,0xa9,0xaf,0xd6,0xdd,0x7f,0xf8,0xaa,0x91,0x7f,0x6a, +0xaf,0x04,0x11,0xc9,0xd4,0x53,0xeb,0x6c,0x3f,0xf8,0xaa,0xf0,0xb6,0xfd,0x99,0x7c, +0x6c,0xbd,0x2c,0xe2,0x3f,0x49,0x45,0x42,0xff,0x00,0xb3,0x67,0x8d,0xd4,0x7f,0xc8, +0x3d,0x4f,0xd1,0xc5,0x2f,0xed,0x1c,0xd5,0x7f,0xcb,0xbf,0xfc,0x95,0x8b,0xeb,0xf9, +0xba,0xff,0x00,0x97,0x5f,0x87,0xfc,0x13,0xe8,0x48,0xbf,0x69,0xef,0x01,0xc8,0xe0, +0x1b,0xeb,0xa8,0xc1,0xfe,0x26,0xb5,0x6c,0x0f,0xca,0xad,0x2f,0xed,0x27,0xf0,0xfd, +0x81,0x3f,0xdb,0x2e,0xbe,0xc6,0xd6,0x5f,0xfe,0x26,0xbe,0x6b,0x6f,0xd9,0xd7,0xc7, +0x0a,0x78,0xd2,0xc9,0xc7,0xa3,0x8a,0x81,0xff,0x00,0x67,0xef,0x1c,0xa9,0xff,0x00, +0x90,0x34,0x87,0xe8,0xc0,0xff,0x00,0x5a,0x7f,0xda,0x99,0x9c,0x77,0xa5,0xff,0x00, +0x92,0xb0,0xfe,0xd2,0xcd,0x56,0xf4,0x7f,0x06,0x7d,0x42,0x3f,0x68,0x9f,0x87,0xcd, +0xff,0x00,0x33,0x02,0x8f,0xad,0xb4,0xdf,0xfc,0x45,0x38,0x7e,0xd0,0x9f,0x0f,0xcf, +0x4f,0x11,0x47,0xff,0x00,0x80,0xf2,0x8f,0xfd,0x92,0xbe,0x55,0x6f,0x81,0x3e,0x37, +0x43,0xce,0x89,0x37,0xe1,0x51,0x3f,0xc1,0x4f,0x1a,0x27,0x5d,0x0e,0xe7,0x8f,0x6a, +0x6f,0x38,0xcc,0x16,0xf4,0xbf,0xf2,0x59,0x07,0xf6,0xae,0x64,0xb7,0xa1,0xf8,0x3f, +0xf3,0x3e,0xb2,0x1f,0x1f,0xfc,0x00,0xd8,0xff,0x00,0x8a,0x8e,0x1e,0x7d,0x62,0x93, +0xff,0x00,0x89,0xa9,0xd3,0xe3,0xaf,0x80,0xdc,0x64,0x78,0x92,0xd4,0x7d,0x43,0x8f, +0xe9,0x5f,0x1f,0xbf,0xc1,0xff,0x00,0x18,0xa0,0xe7,0x42,0xba,0xe7,0xfd,0x9a,0x85, +0xbe,0x14,0xf8,0xb9,0x3a,0xe8,0x77,0x7f,0xf7,0xc5,0x2f,0xed,0xac,0x72,0xff,0x00, +0x97,0x4b,0xee,0x62,0xfe,0xd8,0xc7,0xad,0xe8,0x7e,0x0c,0xfb,0x3d,0x3e,0x32,0xf8, +0x21,0xc0,0xc7,0x89,0xb4,0xfe,0x7d,0x65,0xc5,0x48,0x9f,0x17,0x7c,0x14,0xf9,0xc7, +0x89,0xf4,0xce,0x3d,0x6e,0x14,0x57,0xc4,0xef,0xf0,0xd3,0xc5,0x51,0x9f,0x9b,0x44, +0xbd,0x1f,0xf6,0xc8,0xd4,0x0d,0xe0,0x0f,0x12,0x27,0x5d,0x1e,0xf0,0x7f,0xdb,0x23, +0x47,0xf6,0xee,0x29,0x6f,0x49,0x7e,0x23,0xfe,0xdb,0xc6,0x2d,0xe8,0x7e,0x67,0xdc, +0x63,0xe2,0xbf,0x83,0x4f,0x4f,0x13,0xe9,0x7f,0xf8,0x16,0x9f,0xe3,0x52,0x2f,0xc4, +0xef,0x09,0x36,0x71,0xe2,0x5d,0x2f,0x8f,0xfa,0x7b,0x4f,0xf1,0xaf,0x85,0x1b,0xc1, +0x5e,0x20,0x5e,0xba,0x55,0xd0,0xff,0x00,0xb6,0x46,0xa2,0x6f,0x0a,0x6b,0x69,0xd7, +0x4c,0xba,0x1f,0xf6,0xc8,0xd1,0xfd,0xbf,0x89,0xeb,0x49,0x7e,0x22,0xfe,0xdd,0xc5, +0x2d,0xe8,0x7e,0x67,0xde,0xc9,0xf1,0x07,0xc2,0xf2,0x80,0x57,0xc4,0x3a,0x59,0x07, +0xa7,0xfa,0x64,0x7f,0xe3,0x56,0x13,0xc6,0x5a,0x04,0x9f,0x77,0x5a,0xd3,0x9b,0x1e, +0x97,0x49,0xfe,0x35,0xf9,0xfa,0xde,0x1c,0xd5,0xd7,0xae,0x9f,0x72,0x3f,0xed,0x91, +0xa8,0xce,0x89,0xa9,0x27,0x06,0xca,0xe0,0x7d,0x63,0x34,0xd7,0x10,0xd6,0x5b,0xd3, +0x5f,0x8f,0xf9,0x0f,0xfb,0x7e,0xbf,0x5a,0x1f,0x99,0xfa,0x1a,0x9e,0x23,0xd2,0x64, +0x50,0x57,0x54,0xb3,0x60,0x7a,0x62,0xe1,0x3f,0xc6,0x9f,0xfd,0xbb,0xa6,0x9e,0x9a, +0x8d,0xa9,0xff,0x00,0xb6,0xeb,0xfe,0x35,0xf9,0xd8,0x74,0xbb,0xe1,0xd6,0xd6,0x61, +0xff,0x00,0x00,0x34,0xc3,0x61,0x78,0xbd,0x60,0x90,0x7d,0x54,0xd3,0xff,0x00,0x58, +0xe7,0xd6,0x97,0xe3,0xff,0x00,0x00,0x7f,0xeb,0x0d,0x45,0xff,0x00,0x2e,0x7f,0x1f, +0xf8,0x07,0xe8,0xca,0x6a,0xf6,0x2e,0x32,0x2f,0x2d,0xd8,0x7a,0x89,0x54,0xff,0x00, +0x5a,0x78,0xd4,0x6d,0x49,0xe2,0xe6,0x03,0xf4,0x90,0x7f,0x8d,0x7e,0x71,0x7d,0x9e, +0xed,0x7f,0xe5,0x9c,0xa3,0xf0,0x34,0xb9,0xbb,0x43,0xff,0x00,0x2d,0x47,0xe7,0x47, +0xfa,0xc7,0x2f,0xf9,0xf5,0xf8,0xff,0x00,0xc0,0x0f,0xf5,0x8a,0x56,0xd6,0x8b,0xfb, +0xff,0x00,0xe0,0x1f,0xa4,0x0b,0x75,0x13,0x8c,0xac,0xa8,0xc3,0xd4,0x30,0x34,0xf1, +0x20,0x3d,0xc1,0xfc,0x6b,0xf3,0x78,0x5e,0x5e,0xa7,0x49,0x66,0x51,0xec,0xcd,0x53, +0x2e,0xb5,0xaa,0xc6,0xc0,0xad,0xf5,0xda,0x9f,0x51,0x33,0x83,0xfc,0xea,0xd7,0x11, +0xf7,0xa5,0xf8,0xff,0x00,0xc0,0x29,0x71,0x1a,0xeb,0x49,0xfd,0xff,0x00,0xf0,0x0f, +0xd1,0xb0,0xc3,0xd6,0x97,0x75,0x7e,0x74,0x0f,0x13,0x6b,0x4a,0x30,0x35,0x4b,0xe5, +0xfa,0x5c,0x3f,0xf8,0xd2,0x8f,0x16,0x6b,0x8a,0x72,0x35,0x7d,0x40,0x1f,0xfa,0xfa, +0x93,0xfc,0x6a,0xff,0x00,0xd6,0x38,0xff,0x00,0xcf,0xbf,0xc7,0xfe,0x00,0xff,0x00, +0xd6,0x48,0x75,0xa4,0xfe,0xf3,0xf4,0x58,0x36,0x69,0x6b,0xf3,0xb1,0x7c,0x6b,0xe2, +0x04,0x04,0x0d,0x6b,0x51,0x1f,0xf6,0xf5,0x27,0xf8,0xd5,0x88,0xfe,0x23,0x78,0xa2, +0x10,0x36,0x78,0x83,0x54,0x5c,0x70,0x31,0x79,0x27,0xf8,0xd3,0x5c,0x45,0x0e,0xb4, +0xdf,0xde,0x52,0xe2,0x4a,0x5d,0x69,0xb3,0xf4,0x32,0x8a,0xfc,0xf9,0x5f,0x8a,0x5e, +0x2e,0x41,0x81,0xe2,0x4d,0x54,0x0f,0xfa,0xfb,0x73,0xfd,0x6a,0xc2,0x7c,0x62,0xf1, +0xaa,0x63,0x1e,0x26,0xd4,0xb8,0xe9,0xfb,0xf2,0x6a,0xd7,0x11,0x52,0xeb,0x4d,0xfe, +0x05,0x7f,0xac,0x94,0x3a,0xc1,0xfe,0x07,0xdf,0xd4,0x57,0xc0,0xa3,0xe3,0x57,0x8d, +0xd7,0xfe,0x66,0x6d,0x43,0xf1,0x97,0xff,0x00,0xad,0x4f,0x4f,0x8d,0xfe,0x38,0x5c, +0x7f,0xc5,0x4b,0x7c,0x71,0xea,0xe0,0xff,0x00,0x4a,0xaf,0xf5,0x8a,0x87,0xf2,0x3f, +0xc0,0xaf,0xf5,0x8f,0x0d,0xfc,0x8f,0xf0,0x3e,0xf7,0xa2,0xbe,0x0c,0x5f,0x8e,0xde, +0x3a,0x5e,0x9e,0x24,0xbc,0xfc,0x76,0x9f,0xe9,0x56,0x53,0xf6,0x84,0xf1,0xea,0x63, +0xfe,0x2a,0x19,0x8e,0x3d,0x61,0x8c,0xff,0x00,0xec,0xb4,0xd7,0x11,0x61,0xdf,0xd8, +0x97,0xe1,0xfe,0x65,0x2e,0x22,0xc2,0xf5,0x8c,0xbf,0x0f,0xf3,0x3e,0xea,0xa2,0xbe, +0x1c,0x8b,0xf6,0x8e,0xf1,0xf4,0x44,0x9f,0xed,0xc2,0xd9,0xfe,0xf5,0xbc,0x47,0xff, +0x00,0x65,0xab,0xf6,0x3f,0xb5,0x17,0x8e,0xed,0x26,0x57,0x96,0xee,0xd2,0xed,0x07, +0x54,0x9a,0xd5,0x40,0x3f,0xf7,0xce,0x0d,0x68,0xb8,0x83,0x0a,0xf7,0x4f,0xf0,0xff, +0x00,0x32,0xd7,0x10,0xe0,0xde,0xe9,0xaf,0x97,0xfc,0x13,0xed,0x4a,0x2b,0xe6,0x2f, +0x0c,0xfe,0xd8,0x52,0x06,0x58,0xfc,0x41,0xa1,0x86,0x5e,0xf3,0xe9,0xcf,0x83,0xed, +0xf2,0x39,0xff,0x00,0xd9,0xab,0xda,0xbc,0x15,0xf1,0x6f,0xc2,0xfe,0x3f,0x5d,0xba, +0x46,0xa9,0x1c,0x97,0x40,0x65,0xad,0x26,0xfd,0xdc,0xcb,0xff,0x00,0x01,0x3d,0x7e, +0xa3,0x22,0xbd,0x6c,0x3e,0x63,0x86,0xc4,0xe9,0x4e,0x7a,0xf6,0xd9,0x9e,0xa6,0x1f, +0x32,0xc2,0xe2,0x9d,0xa9,0xcd,0x5f,0xb6,0xcc,0xec,0xe8,0xa6,0xa9,0xcd,0x3a,0xbd, +0x13,0xd3,0x0a,0x28,0xa2,0x80,0x0a,0x28,0xa2,0x80,0x0a,0x28,0xa2,0x80,0x0a,0x42, +0x69,0x6a,0xbd,0xe5,0xd4,0x56,0x56,0xd3,0x5c,0x4f,0x22,0xc5,0x04,0x48,0x5d,0xdd, +0xce,0x02,0xa8,0x19,0x24,0x9a,0x4f,0x45,0x71,0x37,0x65,0x76,0x78,0x6f,0xed,0x35, +0xf1,0x65,0xfc,0x33,0xa6,0x2f,0x86,0xb4,0xb9,0xb6,0x6a,0x57,0xd1,0xee,0xb8,0x95, +0x1b,0x0d,0x0c,0x3d,0x30,0x3d,0x0b,0x72,0x3e,0x80,0xfa,0x8a,0xe4,0xbf,0x64,0xbf, +0x08,0xfd,0xa7,0x55,0xbe,0xd7,0x66,0x43,0xb6,0xdd,0x7c,0xa8,0x8f,0x6d,0xc7,0xad, +0x78,0x9f,0x8c,0xbc,0x4d,0x71,0xe3,0x9f,0x17,0xea,0x3a,0xbc,0xdb,0x8b,0xde,0x4e, +0x5a,0x34,0x3d,0x51,0x33,0x84,0x5f,0xc0,0x00,0x2b,0xed,0x7f,0x82,0x9e,0x13,0x1e, +0x11,0xf8,0x7d,0xa6,0xdb,0x15,0xdb,0x3c,0xa9,0xe7,0xcb,0x91,0x83,0xb9,0xb9,0xaf, +0x89,0xc3,0x4e,0x59,0x96,0x64,0xea,0xbf,0x86,0x1b,0x7e,0x9f,0xe6,0x7c,0x56,0x0a, +0xa4,0xb3,0x3c,0xc1,0xd7,0x97,0xc3,0x0d,0xbf,0x4f,0xf3,0x3b,0xb0,0x31,0x4b,0x45, +0x15,0xf6,0xe7,0xdb,0x09,0x4b,0x45,0x14,0x00,0x53,0x43,0x83,0xd2,0x9d,0x5e,0x0f, +0xf1,0xcb,0xf6,0xdc,0xf8,0x3b,0xfb,0x3e,0x5c,0xc9,0x61,0xe2,0xaf,0x16,0xc2,0xfa, +0xda,0x02,0x7f,0xb1,0xf4,0xc4,0x6b,0xbb,0xa0,0x47,0x66,0x54,0xc8,0x8c,0x9e,0xde, +0x61,0x5c,0xd0,0x07,0xba,0x89,0x01,0x6d,0xbc,0xe7,0xdc,0x1a,0x7d,0x7e,0x71,0xeb, +0xdf,0xf0,0x5a,0xdf,0x00,0x5b,0xb3,0x0d,0x1b,0xe1,0xf7,0x89,0x2f,0x80,0xe8,0xd7, +0xd3,0xdb,0xdb,0xe7,0xf0,0x56,0x92,0xbe,0x9f,0xfd,0x94,0x7f,0x6a,0xb8,0xbf,0x69, +0x8f,0x85,0xfa,0xaf,0x8f,0x2e,0x7c,0x36,0xfe,0x0b,0xd0,0xac,0xae,0x64,0xb7,0x59, +0xef,0xef,0x92,0x44,0x91,0x63,0x40,0xd2,0xca,0x5b,0x6a,0x85,0x45,0xce,0x32,0x7d, +0x1b,0xa6,0x28,0x11,0xef,0xb4,0x57,0x17,0x6d,0xf1,0xb3,0xe1,0xe5,0xeb,0x2a,0xdb, +0xf8,0xf3,0xc3,0x33,0xb3,0x1c,0x05,0x8b,0x58,0xb7,0x62,0x4f,0xe0,0xf5,0xd9,0x83, +0x9e,0x94,0x0c,0x5a,0x2b,0x33,0x5f,0xf1,0x1e,0x9f,0xe1,0x7d,0x3d,0xaf,0xb5,0x3b, +0x91,0x6b,0x6a,0xac,0x14,0xb9,0x52,0xdc,0x93,0x80,0x30,0x01,0x35,0x81,0x17,0xc5, +0xff,0x00,0x07,0xcd,0xd3,0x5d,0x80,0x7f,0xbe,0xae,0xbf,0xcc,0x57,0x34,0xf1,0x34, +0x69,0x4b,0x96,0xa4,0xd2,0x7e,0x6d,0x22,0x1c,0xe1,0x17,0x66,0xd2,0x3b,0x1a,0x31, +0x5c,0xcc,0x7f,0x12,0xfc,0x2b,0x26,0x31,0xe2,0x0b,0x01,0x9f,0xef,0x4e,0xa3,0xf9, +0xd4,0xc3,0xe2,0x0f,0x86,0x0f,0x4f,0x10,0xe9,0x9f,0xf8,0x16,0x9f,0xe3,0x49,0x62, +0xb0,0xef,0x6a,0x8b,0xef,0x42,0xf6,0x90,0xfe,0x64,0x74,0x34,0x56,0x12,0xf8,0xe7, +0xc3,0x8e,0x78,0xd7,0xf4,0xc3,0xff,0x00,0x6f,0x91,0xff,0x00,0x8d,0x58,0x8b,0xc5, +0x3a,0x34,0xe3,0xf7,0x7a,0xb5,0x8c,0x9f,0xee,0xdc,0x21,0xfe,0xb5,0xa2,0xad,0x4d, +0xed,0x25,0xf7,0x8f,0x9a,0x2f,0x66,0x6a,0xd1,0x55,0x13,0x55,0xb2,0x97,0x95,0xbb, +0x81,0xbf,0xdd,0x95,0x4f,0xf5,0xa9,0x96,0x78,0xa4,0xfb,0xb2,0x2b,0x7d,0x1a,0xaf, +0x9e,0x2f,0x66,0x55,0xd1,0x2d,0x14,0xdd,0xdd,0xc1,0xa5,0x07,0x35,0x43,0x16,0x8a, +0x28,0xa6,0x01,0x45,0x21,0xe9,0x49,0x9a,0x00,0x75,0x26,0x29,0x32,0x3d,0x69,0x73, +0x48,0x05,0xa4,0xc5,0x18,0xf7,0xa5,0xa6,0x02,0x62,0x96,0x8a,0x28,0x00,0xa2,0x8a, +0x28,0x01,0x29,0x68,0xa2,0x80,0x12,0x8c,0x52,0xd1,0x40,0x05,0x14,0x51,0x40,0x05, +0x26,0x29,0x68,0xa0,0x04,0xc5,0x18,0x1e,0x94,0xb4,0x50,0x02,0x6d,0x1e,0x82,0x93, +0xcb,0x53,0xfc,0x23,0xf2,0xa0,0x92,0x3f,0x87,0x3f,0x8d,0x28,0xcf,0x71,0x8a,0x00, +0x69,0x82,0x33,0xd6,0x35,0x3f,0x80,0xa6,0x9b,0x58,0x5b,0xac,0x48,0x7f,0xe0,0x22, +0xa5,0xa2,0x95,0x97,0x61,0x59,0x10,0x1b,0x1b,0x73,0xd6,0x08,0xff,0x00,0xef,0x91, +0x4d,0x3a,0x6d,0xa3,0x75,0xb6,0x84,0xfd,0x50,0x55,0x9a,0x29,0x72,0xc7,0xb0,0x59, +0x14,0x9b,0x46,0xb0,0x6e,0xb6,0x56,0xe7,0xfe,0xd9,0x8f,0xf0,0xa8,0xdb,0xc3,0xba, +0x5b,0x75,0xd3,0xed,0x8f,0xfd,0xb2,0x5f,0xf0,0xad,0x1a,0x29,0x7b,0x38,0x76,0x17, +0x2a,0xec,0x64,0xb7,0x85,0x74,0x76,0xeb,0xa6,0x5a,0x9f,0xfb,0x64,0xbf,0xe1,0x51, +0xb7,0x83,0x74,0x36,0xeb,0xa4,0xda,0x1f,0xac,0x23,0xfc,0x2b,0x6a,0x8a,0x9f,0x65, +0x4f,0xf9,0x57,0xdc,0x2e,0x48,0x76,0x30,0x1f,0xc0,0x9e,0x1e,0x93,0xef,0x68,0xd6, +0x67,0xfe,0xd8,0x8a,0x89,0xbe,0x1c,0xf8,0x65,0xba,0xe8,0x96,0x7f,0xf7,0xec,0x57, +0x49,0x45,0x4b,0xc3,0xd2,0x7b,0xc1,0x7d,0xc4,0xfb,0x28,0x3f,0xb2,0x8e,0x55,0xbe, +0x17,0xf8,0x55,0xfa,0xe8,0x96,0x9f,0xf7,0xc5,0x42,0xdf,0x09,0x3c,0x22,0xdd,0x74, +0x3b,0x5f,0xfb,0xe6,0xba,0xfa,0x5a,0x8f,0xaa,0xd0,0xfe,0x45,0xf7,0x21,0x7b,0x1a, +0x5f,0xca,0xbe,0xe3,0x89,0x7f,0x83,0x7e,0x0e,0x7e,0xba,0x1d,0xb7,0xe5,0x50,0x3f, +0xc0,0xff,0x00,0x05,0x3f,0xfc,0xc0,0xe0,0x1f,0x4c,0xd7,0x7b,0x45,0x4b,0xc1,0xe1, +0xdf,0xfc,0xbb,0x5f,0x72,0x27,0xea,0xf4,0x7f,0x91,0x7d,0xc7,0x9e,0x3f,0xc0,0x5f, +0x04,0xbf,0xfc,0xc1,0xa3,0x1f,0x46,0x35,0x0b,0xfe,0xcf,0x7e,0x09,0x7f,0xf9,0x85, +0x63,0xe8,0xe6,0xbd,0x23,0x34,0x64,0x7a,0xd4,0x7d,0x47,0x0b,0xff,0x00,0x3e,0xd7, +0xdc,0x88,0xfa,0xa5,0x0f,0xe4,0x5f,0x71,0xe6,0x0f,0xfb,0x39,0x78,0x25,0xff,0x00, +0xe6,0x1c,0xc3,0xe8,0xf5,0x0b,0xfe,0xcd,0x5e,0x09,0x7f,0xf9,0x72,0x90,0x7d,0x24, +0xaf,0x55,0xa2,0xa7,0xfb,0x3f,0x08,0xff,0x00,0xe5,0xda,0xfb,0x89,0xfa,0x96,0x19, +0xef,0x4d,0x7d,0xc7,0x92,0x3f,0xec,0xc5,0xe0,0xb6,0xe9,0x05,0xc2,0xff,0x00,0xdb, +0x4a,0x81,0xff,0x00,0x65,0xcf,0x07,0xb7,0x41,0x72,0xbf,0xf6,0xd2,0xbd,0x8e,0x8a, +0x9f,0xec,0xcc,0x1b,0xff,0x00,0x97,0x4b,0xee,0x27,0xea,0x18,0x57,0xff,0x00,0x2e, +0xd7,0xdc,0x78,0xb3,0xfe,0xca,0xbe,0x12,0x6e,0x92,0x5d,0x2f,0xfc,0x08,0x54,0x2f, +0xfb,0x27,0xf8,0x5d,0xba,0x5c,0xdd,0x0f,0xc4,0x57,0xb7,0xd1,0x51,0xfd,0x95,0x82, +0xff,0x00,0x9f,0x48,0x97,0x97,0x61,0x1f,0xfc,0xbb,0x47,0x84,0xbf,0xec,0x95,0xe1, +0xb6,0xe9,0x7d,0x76,0x3f,0x2a,0xa5,0x77,0xfb,0x24,0x69,0xd0,0x95,0x9f,0x4e,0xd6, +0x6e,0xed,0xae,0xe3,0x21,0xe2,0x90,0x60,0x15,0x61,0xd0,0x82,0x39,0x06,0xbe,0x83, +0xa4,0x3d,0x29,0x7f,0x64,0xe0,0xf7,0x54,0xed,0xf7,0x99,0xbc,0xaf,0x07,0x2f,0xf9, +0x76,0x8f,0x01,0xf0,0x97,0xc6,0x3d,0x4f,0xe1,0xff,0x00,0x89,0xd3,0xc2,0x5e,0x3e, +0xb9,0x59,0xa1,0x77,0x10,0xda,0x6b,0xa4,0x6d,0xcb,0x67,0x01,0x66,0xed,0xcf,0x1f, +0x3f,0xe7,0xeb,0x5e,0xfa,0x8c,0x18,0x70,0x72,0x3d,0x6b,0xe3,0x1f,0xda,0x88,0xa5, +0xee,0xbb,0x24,0x4c,0x01,0x05,0x88,0xc7,0xad,0x77,0x1f,0xb1,0xff,0x00,0xc6,0x49, +0xbc,0x47,0x65,0x79,0xe0,0x6d,0x66,0xe9,0xa6,0xd5,0xf4,0xa8,0x84,0xd6,0x53,0x4a, +0xd9,0x79,0xed,0x72,0x06,0x09,0xee,0x63,0x25,0x47,0xd1,0x97,0xd2,0xb9,0x70,0x18, +0xde,0x6a,0xd3,0xc3,0x4d,0xdf,0x95,0xe8,0xcf,0x23,0x07,0x98,0xfb,0x2c,0x6b,0xcb, +0xea,0xbb,0xaf,0xb2,0xdf,0xe4,0xff,0x00,0x43,0xe9,0x8a,0x29,0x9b,0xbd,0xff,0x00, +0x5a,0x2b,0xe8,0x8f,0xaa,0xe6,0x43,0xe8,0xa2,0x8a,0x45,0x05,0x14,0x51,0x40,0x05, +0x79,0x0f,0xed,0x3d,0xe2,0xdf,0xf8,0x46,0xfe,0x1a,0xdc,0x5a,0x45,0x26,0xcb,0xad, +0x55,0xc5,0xa2,0x60,0xf3,0xb3,0xac,0x9f,0xf8,0xe8,0x23,0xfe,0x05,0x5e,0xb8,0x49, +0xed,0x5f,0x1b,0x7e,0xd4,0xbe,0x30,0x3a,0xff,0x00,0xc4,0x4f,0xec,0xb8,0xdf,0x75, +0xae,0x93,0x10,0x8b,0x00,0x82,0x0c,0xad,0x86,0x73,0xf8,0x0d,0xa3,0xea,0x0d,0x78, +0xf9,0xb6,0x23,0xea,0xf8,0x59,0x35,0xbb,0xd1,0x7c,0xcf,0x13,0x38,0xc4,0xfd,0x5b, +0x07,0x26,0xb7,0x96,0x8b,0xe6,0x72,0x5f,0x06,0x7c,0x26,0x7c,0x5d,0xe3,0xed,0x32, +0xd3,0x6e,0xe8,0x52,0x41,0x2c,0xb9,0xfe,0xe8,0xe6,0xbe,0xf6,0x8d,0x04,0x68,0xa8, +0xa3,0x0a,0xa3,0x00,0x0f,0x4a,0xf9,0xd3,0xf6,0x49,0xf0,0x8f,0xd9,0xf4,0xfb,0xfd, +0x7a,0x68,0xfe,0x79,0x4f,0x93,0x13,0x1f,0x4e,0xf5,0xf4,0x60,0xae,0x3c,0x8b,0x0f, +0xec,0xb0,0xde,0xd1,0xef,0x2d,0x7e,0x5d,0x0c,0x32,0x2c,0x37,0xb0,0xc2,0x29,0x3d, +0xe5,0xa8,0xb4,0x51,0x45,0x7d,0x21,0xf4,0x41,0x48,0x4e,0x29,0x6b,0x95,0xf8,0xad, +0xe3,0x88,0x3e,0x19,0xfc,0x32,0xf1,0x5f,0x8b,0x6e,0x81,0x68,0x34,0x4d,0x2e,0xe7, +0x50,0x65,0x03,0x39,0xf2,0xa3,0x67,0xc7,0xe3,0x8a,0x00,0xfc,0xfb,0xff,0x00,0x82, +0x96,0x7f,0xc1,0x41,0x75,0x2f,0x01,0x6a,0xd7,0xbf,0x09,0xbe,0x1b,0x6a,0x06,0xcf, +0x59,0x8e,0x30,0x35,0xcd,0x72,0x03,0x87,0xb6,0xdc,0x33,0xf6,0x68,0x5b,0xb3,0xed, +0x20,0xb3,0x8f,0xbb,0xb8,0x01,0xce,0xec,0x7c,0x27,0xf0,0x53,0xf6,0x29,0xf8,0xcd, +0xfb,0x4a,0x59,0xcb,0xaf,0x78,0x6b,0xc3,0xb2,0x4d,0xa4,0xc9,0x21,0x27,0x5a,0xd5, +0xee,0x45,0xbc,0x33,0xbe,0x4e,0xe2,0xae,0xe7,0x32,0x1c,0x83,0x92,0xa0,0xe0,0xf5, +0x35,0xe5,0x9a,0x76,0xab,0x1f,0x8f,0xbe,0x29,0xda,0x6a,0x3e,0x2e,0xbf,0x2b,0x0e, +0xb3,0xac,0xa4,0xfa,0xb5,0xfb,0xb6,0xd2,0xa9,0x2c,0xe0,0xcf,0x21,0x3d,0xb0,0x19, +0x8f,0xb5,0x7f,0x40,0x9f,0x1c,0x3e,0x24,0xe8,0x3f,0xb3,0x97,0xec,0xbf,0xae,0xf8, +0x9b,0x43,0x5b,0x5b,0x7d,0x2b,0x46,0xd1,0x44,0x7a,0x34,0x36,0xa5,0x44,0x4c,0xcc, +0xa2,0x3b,0x61,0x1e,0x38,0x20,0xb3,0x27,0x4e,0xdc,0xd3,0x25,0x6a,0x7f,0x3e,0x1e, +0x2f,0xf0,0x4e,0xa1,0xe0,0xef,0x1d,0x6a,0xbe,0x13,0x9d,0xa1,0xbe,0xd5,0x74,0xeb, +0xe7,0xd3,0xa4,0xfb,0x03,0x99,0x63,0x92,0x64,0x7d,0x85,0x50,0xe0,0x6e,0xf9,0x81, +0x03,0x8e,0x71,0x5f,0xbd,0xbe,0x1c,0xf8,0x6b,0xa7,0x7e,0xce,0x7f,0xb0,0xcd,0xef, +0x86,0x2e,0x84,0x51,0xc7,0xa3,0x78,0x42,0xed,0xf5,0x07,0xc6,0x16,0x4b,0x86,0xb7, +0x91,0xe7,0x27,0xeb,0x23,0x30,0xfc,0xab,0xf2,0x6b,0xfe,0x09,0xd5,0xf0,0x92,0x7f, +0x8e,0x9f,0xb5,0xbf,0x87,0xae,0x75,0x24,0x6b,0xed,0x3f,0x45,0x95,0xfc,0x45,0xa9, +0xcb,0x29,0xfb,0xcd,0x11,0x06,0x32,0x4f,0x72,0xd3,0xb4,0x59,0xf5,0x19,0xaf,0xb2, +0xff,0x00,0xe0,0xac,0x1f,0xb6,0x06,0x8d,0xa5,0x78,0x12,0xe7,0xe0,0xdf,0x85,0xb5, +0x38,0x6f,0xf5,0xfd,0x52,0x44,0xfe,0xde,0x6b,0x67,0x0e,0xb6,0x56,0xc8,0x43,0x08, +0x19,0x81,0xe2,0x47,0x60,0x99,0x5e,0x48,0x50,0x72,0x06,0xe1,0x40,0x2d,0x35,0x3f, +0x2c,0xfe,0x17,0x78,0x72,0xe3,0xc6,0x1f,0x12,0xfc,0x27,0xa0,0xd9,0x0c,0xdd,0xea, +0x7a,0xb5,0xa5,0x9c,0x5c,0xe3,0xe6,0x92,0x64,0x51,0xfc,0xeb,0xfa,0x6e,0x8d,0x3c, +0xb4,0x55,0xeb,0x80,0x06,0x6b,0xf1,0x1f,0xfe,0x09,0x3f,0xf0,0x0e,0xe3,0xe2,0x67, +0xed,0x0b,0x17,0x8c,0xaf,0x2d,0x0b,0xf8,0x7b,0xc1,0xa9,0xf6,0xb6,0x92,0x45,0x3b, +0x1e,0xf1,0x81,0x10,0x20,0x3e,0xaa,0x73,0x27,0xb6,0xc1,0xeb,0x5f,0xb7,0x2c,0xc1, +0x14,0x92,0x70,0x00,0xcd,0x0c,0x16,0xc7,0x81,0xfe,0xd2,0x7e,0x22,0x12,0xdd,0x69, +0x9a,0x24,0x6d,0x91,0x18,0x37,0x52,0x8f,0x73,0x95,0x4f,0xd3,0x77,0xe6,0x2b,0xc4, +0xab,0x7b,0xc7,0x5e,0x20,0x3e,0x28,0xf1,0x6e,0xa7,0xa9,0x64,0x98,0xe5,0x98,0x88, +0xb3,0xd9,0x07,0x0b,0xfa,0x01,0x58,0x35,0xf8,0x96,0x67,0x89,0xfa,0xde,0x2e,0x75, +0x56,0xd7,0xb2,0xf4,0x5a,0x1f,0x29,0x88,0xa9,0xed,0x6a,0xb9,0x06,0x68,0xa2,0x8c, +0xd7,0x98,0x73,0x85,0x14,0x51,0x48,0x00,0x71,0x4e,0x49,0x5e,0x33,0x95,0x76,0x52, +0x3b,0x83,0x8a,0x6d,0x14,0xd3,0x6b,0x60,0xb9,0xb5,0xa6,0xf8,0xd7,0x5f,0xd2,0x0a, +0xfd,0x93,0x58,0xbd,0x84,0x2f,0x45,0x13,0x31,0x5f,0xc8,0xf1,0x5e,0x89,0xe1,0x6f, +0xda,0x2b,0x56,0xb0,0x91,0x22,0xd6,0xed,0xd3,0x51,0xb7,0xef,0x2c,0x2a,0x12,0x51, +0xf8,0x7d,0xd3,0xfa,0x7d,0x6b,0xc8,0x68,0xaf,0x43,0x0f,0x98,0xe2,0xb0,0xb2,0xbd, +0x2a,0x8f,0xf4,0xfb,0x8d,0xe1,0x5e,0xa5,0x37,0x78,0xc8,0xfb,0x57,0xc3,0x5e,0x28, +0xd3,0xbc,0x59,0xa6,0xa5,0xf6,0x9b,0x72,0xb7,0x10,0x31,0xc1,0xec,0xc8,0xdd,0xd5, +0x87,0x63,0x5a,0xd5,0xf2,0x47,0xc2,0x6f,0x18,0x4f,0xe1,0x2f,0x17,0xda,0x10,0xe7, +0xec,0x57,0x6e,0xb0,0x5c,0xc7,0x9e,0x08,0x27,0x01,0xbe,0xaa,0x4e,0x7f,0x3f,0x5a, +0xfa,0xd9,0x4e,0x46,0x6b,0xf5,0x3c,0xa7,0x31,0x59,0x8d,0x0e,0x76,0xad,0x25,0xa3, +0x3e,0x8b,0x0d,0x5f,0xdb,0xc2,0xfd,0x50,0x37,0x00,0xd7,0xcd,0x1f,0x15,0x3e,0x26, +0xeb,0x51,0x78,0xeb,0x51,0xb7,0xd2,0xf5,0x5b,0x9b,0x5b,0x4b,0x56,0x10,0x04,0x89, +0xf0,0xa5,0x94,0x7c,0xc7,0x1f,0xef,0x64,0x7e,0x15,0xf4,0x4e,0xbb,0xaa,0xc7,0xa1, +0xe8,0xd7,0xda,0x84,0xdc,0xc5,0x6b,0x0b,0xcc,0xc0,0x75,0x21,0x41,0x38,0xfd,0x2b, +0xe2,0x8b,0xbb,0xa9,0x2f,0x6e,0xa6,0xb8,0x95,0xb7,0xcb,0x33,0xb4,0x8e,0xc7,0xbb, +0x13,0x92,0x6b,0xc6,0xe2,0x5c,0x64,0xe8,0xd3,0xa7,0x4a,0x9c,0xac,0xdb,0xbe,0x9d, +0x8e,0x6c,0x7d,0x57,0x08,0xa8,0xc5,0xd8,0xea,0x13,0xe2,0xc7,0x8b,0xa3,0xe9,0xae, +0xdd,0x7e,0x3b,0x4f,0xf3,0x15,0x32,0x7c,0x64,0xf1,0x94,0x7d,0x35,0xb9,0x0f,0xfb, +0xd1,0x46,0x7f,0xf6,0x5a,0xe3,0x28,0xaf,0x82,0x58,0xec,0x52,0xda,0xac,0xbe,0xf6, +0x78,0x9e,0xda,0xa7,0xf3,0x3f,0xbc,0xef,0x13,0xe3,0x8f,0x8c,0xd3,0xfe,0x62,0xc1, +0xbf,0xde,0xb7,0x8b,0xff,0x00,0x89,0xab,0x09,0xf1,0xef,0xc6,0x0b,0xd6,0xf6,0x06, +0xfa,0xdb,0xaf,0xf8,0x57,0x9d,0xd1,0x5a,0x2c,0xcb,0x1a,0xb6,0xad,0x2f,0xbd,0x97, +0xf5,0x8a,0xbf,0xcc,0xcf,0x4a,0x5f,0xda,0x0b,0xc5,0xca,0x79,0x96,0xd1,0xff,0x00, +0xde,0xb7,0xff,0x00,0x03,0x53,0xa7,0xed,0x17,0xe2,0xa4,0xeb,0x16,0x9c,0xff,0x00, +0x58,0x1b,0xff,0x00,0x8b,0xaf,0x2e,0xa2,0xb4,0x59,0xb6,0x39,0x6d,0x59,0xfd,0xe3, +0x58,0x9a,0xcb,0xed,0x33,0xd6,0x23,0xfd,0xa4,0xbc,0x48,0xbf,0x7a,0xcb,0x4e,0x6f, +0xfb,0x66,0xe3,0xff,0x00,0x67,0xab,0x09,0xfb,0x4b,0x6b,0x60,0x7c,0xda,0x5d,0x8b, +0x1f,0x6d,0xe3,0xfa,0xd7,0x8f,0xd1,0x56,0xb3,0x9c,0x7a,0xff,0x00,0x97,0xac,0x7f, +0x5a,0xaf,0xfc,0xc7,0xb3,0x27,0xed,0x33,0xaa,0x0f,0xbd,0xa2,0xda,0xb7,0xd2,0x56, +0x1f,0xd2,0xa7,0x5f,0xda,0x6e,0xef,0xf8,0xb4,0x08,0x7f,0x0b,0xa3,0xff,0x00,0xc4, +0xd7,0x89,0x51,0xfa,0xd6,0xab,0x3c,0xcc,0x3a,0x55,0xfc,0x17,0xf9,0x14,0xb1,0x95, +0xff,0x00,0x98,0xfb,0x1b,0xe1,0xef,0x8b,0x26,0xf1,0xb7,0x86,0x61,0xd5,0xa5,0xb3, +0x16,0x42,0x67,0x75,0x48,0xc3,0xee,0xc8,0x52,0x57,0x39,0xc0,0xee,0x0d,0x74,0xb5, +0x89,0xe0,0xad,0x23,0xfb,0x03,0xc2,0x9a,0x56,0x9e,0x7e,0xf4,0x16,0xe8,0xaf,0xee, +0xd8,0xcb,0x1f,0xcf,0x35,0xb4,0x6b,0xf5,0xac,0x3f,0x3f,0xb1,0x87,0xb5,0x77,0x95, +0x95,0xfd,0x4f,0xa5,0x85,0xf9,0x17,0x36,0xe2,0xd2,0x13,0x8a,0xaf,0x7b,0x7f,0x6f, +0xa7,0x5a,0x49,0x73,0x75,0x3c,0x76,0xf6,0xf1,0x8d,0xcf,0x2c,0xac,0x15,0x54,0x7a, +0x92,0x6b,0xc7,0x3c,0x65,0xfb,0x45,0xdb,0xda,0xb3,0xdb,0x78,0x7a,0xdf,0xed,0x72, +0x0e,0x3e,0xd9,0x70,0x08,0x8f,0xea,0xab,0xd4,0xfe,0x38,0xfc,0x6b,0x0c,0x5e,0x3b, +0x0f,0x82,0x8f,0x35,0x69,0x5b,0xcb,0xaf,0xdc,0x4d,0x5a,0xd0,0xa4,0xaf,0x36,0x7b, +0x51,0x70,0xa3,0x24,0xe0,0x7a,0x9a,0xe5,0xf5,0x8f,0x8a,0x3e,0x16,0xd0,0xb7,0x0b, +0x9d,0x6a,0xd8,0xba,0x9c,0x18,0xe0,0x6f,0x39,0x81,0xf7,0x09,0x92,0x2b,0xe5,0xbf, +0x10,0xf8,0xe3,0x5d,0xf1,0x4c,0x8c,0xda,0x96,0xa5,0x34,0xe8,0x4e,0x7c,0xa0,0xdb, +0x63,0x1f,0x45,0x18,0x15,0x85,0xd2,0xbe,0x33,0x11,0xc5,0x2f,0x6c,0x3d,0x3f,0x9b, +0xff,0x00,0x25,0xfe,0x67,0x95,0x3c,0xc7,0xf9,0x23,0xf7,0x9f,0x4b,0xdf,0xfe,0xd1, +0x7e,0x19,0xb6,0x72,0xb0,0x45,0x7d,0x79,0xe8,0xd1,0xc4,0x15,0x7f,0xf1,0xe6,0x07, +0xf4,0xac,0xb9,0xbf,0x69,0x9d,0x31,0x4f,0xee,0x74,0x6b,0xb7,0x1f,0xed,0xc8,0xab, +0xfc,0xb3,0x5f,0x3e,0x51,0x5e,0x44,0xb8,0x8f,0x1f,0x2d,0x9a,0x5f,0x2f,0xf3,0x39, +0x5e,0x3a,0xb3,0xea,0x7b,0xfa,0xfe,0xd3,0x76,0x64,0xfc,0xda,0x14,0xe0,0x7b,0x4e, +0xa7,0xfa,0x55,0xb8,0xbf,0x69,0x6d,0x10,0xe3,0xcc,0xd2,0xf5,0x04,0xf5,0xda,0x23, +0x6f,0xfd,0x98,0x57,0xce,0xb4,0x54,0xae,0x21,0xcc,0x17,0xda,0x4f,0xe4,0x84,0xb1, +0xd5,0xfb,0x9f,0x53,0x58,0x7c,0x7b,0xf0,0x85,0xe8,0x4f,0x32,0xf2,0x6b,0x36,0x6f, +0xe1,0x9e,0xdd,0xb8,0xfa,0x95,0x04,0x7e,0xb5,0xd8,0xe9,0x3e,0x25,0xd2,0xb5,0xe0, +0x4e,0x9d,0xa9,0x5a,0xde,0xe0,0x64,0x88,0x25,0x56,0x23,0xea,0x07,0x4a,0xf8,0xa2, +0x9d,0x14,0xaf,0x04,0x8a,0xf1,0xbb,0x46,0xeb,0xca,0xb2,0x1c,0x11,0xf4,0x22,0xbd, +0x0a,0x3c,0x51,0x88,0x8b,0xfd,0xf4,0x13,0x5e,0x5a,0x3f,0xd4,0xde,0x19,0x8c,0xd7, +0xc4,0xae,0x7d,0xcf,0x9c,0x9e,0xb4,0xb5,0xf2,0xcf,0x84,0xfe,0x39,0x78,0x8b,0xc3, +0xae,0x91,0xdd,0x4d,0xfd,0xaf,0x68,0x3a,0xc7,0x72,0x7e,0x70,0x3d,0x9f,0xaf,0xe7, +0x9a,0xf7,0xbf,0x04,0x7c,0x49,0xd1,0xfc,0x75,0x6e,0x4d,0x94,0xde,0x55,0xda,0x0c, +0xc9,0x69,0x36,0x04,0x8b,0xee,0x3d,0x47,0xb8,0xaf,0xaf,0xc0,0xe7,0x18,0x5c,0x73, +0xe5,0x83,0xb4,0xbb,0x3f,0xd0,0xf4,0xe8,0xe2,0xa9,0xd6,0xd1,0x3b,0x33,0xac,0xa2, +0x90,0x1c,0x8a,0x5a,0xf7,0x0e,0xc0,0xa2,0x8a,0x28,0x00,0xa2,0x90,0x9c,0x57,0x3b, +0xe2,0x9f,0x88,0x1a,0x1f,0x83,0x93,0x3a,0x9d,0xfc,0x71,0x4a,0x46,0x44,0x09,0xf3, +0xc8,0xdf,0xf0,0x11,0xce,0x3d,0xcf,0x15,0x95,0x4a,0xb0,0xa5,0x1e,0x6a,0x92,0xb2, +0xf3,0x26,0x52,0x51,0x57,0x93,0x3a,0x3a,0x4c,0xd7,0x84,0x6b,0xdf,0xb4,0xb3,0x1d, +0xc9,0xa3,0xe9,0x20,0x0e,0xd2,0xde,0x3f,0x3f,0xf7,0xc2,0xff,0x00,0xf1,0x55,0xc3, +0xea,0x7f,0x1b,0x7c,0x5f,0xa9,0x13,0xff,0x00,0x13,0x31,0x68,0xa7,0xf8,0x6d,0xa2, +0x55,0xc7,0xe3,0x82,0x7f,0x5a,0xf9,0xca,0xfc,0x45,0x81,0xa5,0xa4,0x5b,0x97,0xa2, +0xff,0x00,0x33,0x82,0x78,0xea,0x31,0xd1,0x6a,0x7d,0x5d,0x9f,0xca,0x8d,0xc3,0xd6, +0xbe,0x30,0xba,0xf1,0xaf,0x88,0x2f,0x73,0xe7,0xeb,0x7a,0x84,0x80,0xf5,0x06,0xe5, +0xf1,0xf9,0x66,0xb3,0x1e,0xfa,0xe6,0x43,0x96,0xb8,0x95,0x89,0xee,0xce,0x4d,0x79, +0x92,0xe2,0xaa,0x6b,0xe1,0xa4,0xfe,0xff,0x00,0xf8,0x07,0x3b,0xcc,0xa3,0xd2,0x27, +0xdc,0x04,0x2b,0x1f,0x9b,0x69,0xfa,0xd3,0x86,0xd0,0x30,0x00,0xfc,0x2b,0xe1,0xbf, +0xb5,0xcf,0xff,0x00,0x3d,0xa4,0xff,0x00,0xbe,0x8d,0x58,0xb6,0xd7,0x35,0x2b,0x33, +0x9b,0x7d,0x42,0xea,0x03,0xeb,0x1c,0xcc,0xbf,0xc8,0xd4,0xae,0x2a,0x87,0x5a,0x3f, +0x8f,0xfc,0x01,0x7f,0x69,0x2e,0xb1,0xfc,0x4f,0xb6,0xb6,0xa9,0x3d,0x06,0x69,0xd9, +0xe3,0x8a,0xf8,0xe6,0xd3,0xe2,0x37,0x8a,0x2c,0xbf,0xd5,0x6b,0xd7,0xff,0x00,0x47, +0x9d,0x9c,0x7f,0xe3,0xd9,0xae,0x82,0xc3,0xe3,0xcf,0x8b,0xec,0x48,0xdf,0x75,0x05, +0xea,0x8e,0xd3,0xc0,0xbf,0xcd,0x71,0x5d,0x74,0xf8,0x9f,0x0b,0x2f,0x8e,0x2d,0x7d, +0xcc,0xda,0x39,0x85,0x37,0xba,0x68,0xfa,0xa2,0x90,0xf1,0x5e,0x27,0xe1,0x2f,0xda, +0x22,0x6d,0x5f,0x53,0xb3,0xd3,0xef,0xb4,0x61,0xe6,0xdc,0xca,0x90,0xac,0x96,0xb2, +0x7f,0x13,0x10,0x07,0xca,0xdf,0x5f,0x5a,0xf6,0xc1,0xc8,0x15,0xf4,0x78,0x4c,0x75, +0x0c,0x74,0x5c,0xa8,0x4a,0xf6,0x3b,0xa9,0x56,0x85,0x65,0x78,0x30,0x56,0x0e,0xa0, +0x8e,0x86,0x96,0x9a,0xab,0xb4,0x60,0x74,0xa7,0x57,0x79,0xb0,0x53,0x5c,0xe1,0x49, +0xf4,0x14,0xea,0x8a,0xe9,0xfc,0xbb,0x69,0x5b,0xd1,0x09,0xfd,0x29,0x3d,0x80,0xf8, +0x93,0xf6,0x80,0xb9,0xfb,0x47,0x8a,0xe4,0x5c,0xe7,0x04,0xd7,0x87,0xe8,0xfe,0x3c, +0x97,0xe1,0x5f,0xc5,0x4f,0x09,0x78,0xaa,0x10,0x0a,0x5a,0x5f,0x24,0x57,0x0a,0x4e, +0x03,0x41,0x27,0xee,0xe4,0x07,0xfe,0x02,0xc4,0x8f,0x70,0x3d,0x2b,0xd6,0xbe,0x33, +0x5c,0x79,0xde,0x2d,0xb8,0x39,0xce,0x33,0x5f,0x2e,0x7c,0x77,0xba,0x30,0xe8,0x72, +0xed,0x38,0x60,0xa4,0x8c,0x7a,0xd7,0xe7,0x18,0x29,0x37,0x8e,0x94,0x97,0x76,0x7e, +0x39,0x8f,0xa9,0x25,0x9a,0x53,0x9c,0x77,0xe7,0x47,0xec,0x77,0xdb,0x61,0xff,0x00, +0x9e,0xc9,0xf9,0xd1,0x5e,0x03,0xfd,0x91,0x7b,0xff,0x00,0x3f,0x72,0xff,0x00,0xdf, +0x46,0x8a,0xfd,0x0f,0x9d,0x9f,0xaf,0x73,0x79,0x1f,0x44,0xd1,0x45,0x15,0xa9,0xa8, +0x51,0x45,0x14,0x01,0x93,0xe2,0x9d,0x7a,0x1f,0x0b,0xf8,0x77,0x53,0xd5,0xae,0x48, +0xf2,0x6c,0xed,0xde,0x76,0x1e,0xbb,0x41,0x38,0xfc,0x4f,0x15,0xf9,0xe8,0xf3,0x5d, +0x78,0x97,0x5b,0x92,0x79,0x4b,0x4d,0x79,0x7d,0x39,0x76,0x3d,0x49,0x66,0x6c,0xff, +0x00,0x5a,0xfa,0x97,0xf6,0xb9,0xf1,0x6b,0x69,0x9e,0x11,0xb1,0xd0,0xa0,0x90,0x2c, +0xba,0x9c,0xdb,0xe5,0x51,0x8c,0xf9,0x51,0xf3,0xfa,0xb1,0x5f,0xc8,0xd7,0x8e,0x7e, +0xce,0xde,0x11,0xff,0x00,0x84,0xa3,0xe2,0x15,0xa3,0xc8,0xbb,0xad,0xac,0xff,0x00, +0x7e,0xfc,0x71,0xc7,0x41,0xf9,0xd7,0xc3,0xe7,0x33,0x78,0xac,0x54,0x30,0x90,0xfe, +0x9b,0xff,0x00,0x80,0x7c,0x26,0x6f,0x27,0x8c,0xc7,0x53,0xc2,0x47,0x65,0xbf,0xab, +0xff,0x00,0x80,0x7d,0x75,0xf0,0xeb,0xc3,0x51,0xf8,0x4f,0xc1,0xba,0x5e,0x9a,0x8b, +0xb5,0xa2,0x84,0x17,0xf7,0x62,0x32,0x6b,0xa4,0x03,0x14,0x2f,0x02,0x96,0xbe,0xd2, +0x9c,0x15,0x38,0x28,0x47,0x64,0x7d,0xc4,0x22,0xa1,0x15,0x15,0xb2,0x0a,0x28,0xa2, +0xb4,0x2c,0x2b,0x88,0xf8,0xe1,0xe0,0x17,0xf8,0xa9,0xf0,0x77,0xc6,0xbe,0x0f,0x8e, +0x5f,0x22,0x5d,0x73,0x48,0xba,0xb0,0x8e,0x53,0xfc,0x0f,0x24,0x4c,0xaa,0x7f,0x02, +0x45,0x76,0xf4,0x84,0x66,0x80,0x3f,0x97,0xbf,0x12,0xf8,0x6f,0x53,0xf0,0x77,0x88, +0x75,0x2d,0x0f,0x59,0xb3,0x97,0x4f,0xd5,0x74,0xeb,0x87,0xb5,0xba,0xb5,0x9d,0x70, +0xf1,0x48,0xa4,0x86,0x52,0x3e,0xa2,0xb4,0xa7,0xf8,0x99,0xe2,0xdb,0x9f,0x06,0x0f, +0x08,0x4d,0xe2,0x5d,0x56,0x6f,0x0b,0x09,0x56,0x71,0xa3,0x49,0x79,0x23,0x5a,0xac, +0x8b,0x9d,0xac,0x23,0x27,0x68,0x23,0x27,0xa0,0xef,0x5f,0xbd,0xff,0x00,0xb4,0x67, +0xec,0x2b,0xf0,0x9f,0xf6,0x99,0xb8,0x6d,0x4b,0xc4,0xba,0x3c,0xba,0x77,0x88,0xf6, +0x04,0x1a,0xee,0x8f,0x20,0x82,0xe9,0x80,0x18,0x01,0xf8,0x29,0x26,0x07,0x03,0x7a, +0x92,0x07,0x00,0x81,0x5f,0x2a,0x6a,0xbf,0xf0,0x44,0xcf,0x0c,0x49,0x76,0x0e,0x99, +0xf1,0x3b,0x56,0xb6,0xb5,0xef,0x1d,0xde,0x9b,0x14,0xcf,0x8f,0xf7,0x95,0x90,0x7e, +0x95,0x57,0x22,0xcf,0xa1,0xf9,0x77,0xe0,0xff,0x00,0x89,0x7e,0x2c,0xf8,0x7d,0x0e, +0xa7,0x17,0x86,0x3c,0x45,0xa9,0x78,0x7d,0x75,0x38,0x84,0x17,0x9f,0xd9,0xb7,0x2f, +0x03,0x4f,0x18,0x24,0x84,0x62,0xa4,0x12,0x32,0x4f,0x15,0xdb,0xfe,0xcf,0x3f,0xb3, +0x4f,0x8e,0xff,0x00,0x6a,0x2f,0x1c,0x47,0xa3,0x78,0x5a,0xc6,0x49,0x63,0xf3,0x03, +0x6a,0x1a,0xcd,0xc8,0x3f,0x66,0xb3,0x42,0x79,0x79,0x1f,0xb9,0xeb,0x85,0x19,0x66, +0x3d,0x2b,0xf5,0x27,0xe1,0xef,0xfc,0x11,0xd7,0xe0,0xf7,0x86,0x2f,0xe1,0xbb,0xf1, +0x1e,0xad,0xe2,0x0f,0x18,0x98,0xf9,0x36,0x97,0x17,0x0b,0x6b,0x6e,0xc7,0xdc,0x44, +0xa1,0xff,0x00,0x0d,0xf5,0xf6,0xa7,0x82,0x3c,0x03,0xe1,0xcf,0x86,0xbe,0x1e,0xb6, +0xd0,0x7c,0x2b,0xa2,0x58,0xf8,0x7f,0x47,0xb7,0x1f,0xbb,0xb3,0xd3,0xe0,0x58,0xa3, +0x07,0xb9,0x20,0x0e,0x58,0xf7,0x63,0xc9,0xee,0x69,0x5c,0x12,0xee,0x71,0xdf,0xb3, +0x97,0xec,0xfd,0xe1,0xbf,0xd9,0xab,0xe1,0x7e,0x9d,0xe0,0xcf,0x0d,0xc6,0x5a,0x38, +0x7f,0x7b,0x77,0x7d,0x22,0x81,0x35,0xed,0xc3,0x01,0xbe,0x67,0x3e,0xa7,0x00,0x01, +0xd8,0x00,0x07,0x02,0xb6,0x7e,0x30,0xf8,0x8c,0x78,0x6f,0xc0,0x7a,0x8c,0x8a,0xc1, +0x6e,0x2e,0x57,0xec,0xb0,0xf3,0x83,0xb9,0xf8,0x24,0x7b,0x85,0xdc,0x7f,0x0a,0xed, +0xeb,0xe7,0x8f,0xda,0x43,0xc4,0x5f,0x6b,0xd6,0x6c,0x34,0x68,0xdf,0x29,0x6b,0x19, +0x9e,0x50,0x3a,0x6f,0x6e,0x07,0xe4,0x07,0xfe,0x3d,0x5e,0x2e,0x6f,0x89,0xfa,0xae, +0x0e,0x73,0x5b,0xbd,0x17,0xab,0xd0,0xe7,0xc5,0x54,0xf6,0x74,0x9b,0x3c,0x6e,0x8a, +0x28,0xaf,0xc6,0x0f,0x95,0x0a,0xf6,0xff,0x00,0xd9,0xcf,0xc2,0x90,0x5e,0xc5,0xaa, +0xea,0xf7,0x76,0xf1,0x4e,0x99,0x16,0xd1,0x09,0x50,0x30,0xc8,0xf9,0x98,0xe0,0xfd, +0x57,0xf5,0xaf,0x10,0xaf,0xb0,0xbe,0x1a,0x78,0x74,0xf8,0x63,0xc1,0x1a,0x4d,0x8b, +0xa9,0x59,0xc4,0x5e,0x64,0xc0,0x8c,0x10,0xee,0x77,0x30,0xfc,0x09,0xc7,0xe1,0x5f, +0x57,0xc3,0xb8,0x5f,0x6f,0x8b,0xf6,0x92,0x5a,0x45,0x7e,0x2f,0x44,0x7a,0x58,0x0a, +0x7c,0xf5,0x79,0x9f,0x43,0x4e,0x4f,0x09,0xe8,0x93,0x0f,0xde,0x69,0x16,0x2f,0xf5, +0xb6,0x43,0xfd,0x2b,0x36,0xf3,0xe1,0x87,0x85,0x2f,0x91,0x96,0x4d,0x02,0xc5,0x41, +0xea,0x62,0x84,0x46,0x7f,0x35,0xc1,0xae,0x9c,0x0c,0x51,0x5f,0xa6,0xcb,0x0f,0x46, +0x5f,0x14,0x13,0xf9,0x23,0xe8,0x1d,0x38,0x3d,0xd2,0x3c,0x33,0xe2,0x17,0xc0,0x1b, +0x3b,0x6d,0x3a,0xe3,0x50,0xf0,0xf3,0xcb,0x1c,0x90,0xa1,0x76,0xb3,0x95,0xb7,0x87, +0x03,0x93,0xb5,0x8f,0x39,0xfa,0x93,0x9f,0x6a,0xf0,0x8a,0xfb,0x2b,0xc7,0x7e,0x21, +0x83,0xc3,0x3e,0x14,0xd4,0x6f,0xe6,0x20,0x6c,0x89,0x95,0x14,0xff,0x00,0x1b,0x91, +0x85,0x1f,0x99,0xaf,0x8d,0x40,0xc0,0x02,0xbf,0x34,0xe2,0x2c,0x2e,0x1b,0x0d,0x5a, +0x1e,0xc1,0x59,0xb5,0xaa,0x5f,0x81,0xe0,0x63,0xa9,0xc2,0x9c,0xd7,0x26,0x81,0x45, +0x14,0x57,0xc9,0x1e,0x61,0x6f,0x49,0xb5,0x7b,0xed,0x56,0xce,0xde,0x21,0x99,0x25, +0x99,0x23,0x5c,0x7a,0x96,0x00,0x7f,0x3a,0xfb,0x79,0x38,0x50,0x2b,0xe5,0xdf,0x81, +0x3e,0x13,0x6f,0x10,0x78,0xce,0x2b,0xc9,0x13,0x75,0xa6,0x9a,0x3c,0xf7,0x24,0x70, +0x64,0xe8,0x83,0xeb,0x9f,0x9b,0xfe,0x03,0x5f,0x51,0x81,0x5f,0xa5,0xf0,0xc5,0x09, +0x53,0xc3,0xce,0xab,0xfb,0x4f,0x4f,0x91,0xef,0xe5,0xd0,0x71,0x83,0x93,0xea,0x61, +0x78,0xdb,0xc3,0x4f,0xe2,0xff,0x00,0x0e,0x5d,0xe9,0x2b,0x78,0xf6,0x22,0xe3,0x68, +0x69,0x91,0x37,0x10,0x03,0x02,0x46,0x32,0x3a,0xe3,0x15,0xe4,0xf2,0x7e,0xcc,0x63, +0xf8,0x3c,0x40,0x7f,0xe0,0x56,0x9f,0xfd,0x9d,0x7b,0xb5,0x26,0x2b,0xe8,0x71,0x59, +0x6e,0x17,0x19,0x25,0x3a,0xf0,0xbb,0xf5,0x67,0x75,0x4c,0x3d,0x3a,0xae,0xf3,0x57, +0x3c,0x09,0xff,0x00,0x66,0x4b,0xaf,0xe0,0xd7,0xa1,0x3f,0xef,0x5b,0x11,0xff,0x00, +0xb3,0x55,0x77,0xfd,0x99,0xf5,0x31,0xf7,0x35,0xab,0x46,0xfa,0xc4,0xc2,0xbe,0x85, +0xc5,0x52,0xd6,0x35,0x38,0xb4,0x7d,0x2a,0xf2,0xfa,0x63,0x88,0xad,0xa2,0x79,0x58, +0xfb,0x28,0x26,0xbc,0xe9,0xe4,0x39,0x72,0x4d,0xb8,0x5b,0xe6,0xff,0x00,0xcc,0xc1, +0xe0,0xa8,0x2d,0x6c,0x7c,0x65,0xe2,0x0d,0x20,0xe8,0x1a,0xdd,0xee,0x9a,0xd7,0x11, +0xdc,0xbd,0xac,0x86,0x26,0x92,0x20,0x42,0x96,0x1d,0x40,0xcf,0xa1,0xc8,0xfc,0x2b, +0x3e,0xa6,0xbc,0xba,0x96,0xfe,0xee,0x6b,0x99,0xdb,0x7c,0xf3,0x3b,0x49,0x23,0x7a, +0xb1,0x39,0x27,0xf3,0x35,0x0d,0x7e,0x51,0x53,0x95,0xcd,0xb8,0x2d,0x2f,0xa1,0xf3, +0x4e,0xd7,0x76,0x0a,0x28,0xad,0x2f,0x0d,0xe9,0x2d,0xaf,0x78,0x83,0x4d,0xd3,0xd4, +0x13,0xf6,0x9b,0x84,0x8c,0xe3,0xb2,0x93,0xc9,0xfc,0xb3,0x4a,0x10,0x75,0x24,0xa0, +0xb7,0x6e,0xc1,0x15,0x76,0x91,0xd2,0xda,0xfc,0x17,0xf1,0x7d,0xe5,0xa4,0x37,0x30, +0xe9,0x41,0xe2,0x99,0x04,0x88,0x7c,0xf8,0xc1,0xc1,0x19,0x19,0x05,0xb8,0xa4,0x93, +0xe0,0xb7,0x8c,0xe3,0xeb,0xa2,0x39,0xff,0x00,0x76,0x68,0x8f,0xfe,0xcd,0x5f,0x59, +0x43,0x1a,0xc5,0x12,0x22,0x8d,0xaa,0xa0,0x00,0x07,0x61,0x4e,0xc7,0xbd,0x7e,0x99, +0xfe,0xac,0x61,0x1a,0x5e,0xf4,0xaf,0xea,0xbf,0xc8,0xf7,0xff,0x00,0xb3,0xa9,0xf7, +0x67,0xc8,0x12,0x7c,0x2a,0xf1,0x6c,0x47,0xe6,0xd0,0x6e,0xcf,0xfb,0xaa,0x0f,0xf2, +0x35,0xa1,0xe1,0x2f,0x86,0x1e,0x20,0x9b,0xc5,0x3a,0x52,0x5e,0xe8,0xb7,0x50,0x5a, +0x7d,0xa5,0x1a,0x67,0x9a,0x22,0x10,0x20,0x39,0x6c,0x9f,0x70,0x31,0x5f,0x57,0x8a, +0x31,0x44,0x38,0x67,0x0d,0x09,0xa9,0x29,0xbd,0x3d,0x06,0xb2,0xfa,0x69,0xde,0xec, +0x07,0x02,0xb1,0x7c,0x59,0xe2,0xed,0x3f,0xc1,0xba,0x3c,0x9a,0x86,0xa1,0x2e,0xc8, +0xc7,0xca,0x91,0xaf,0xdf,0x95,0xbb,0x2a,0x8e,0xe7,0xf9,0x75,0x35,0x7f,0x56,0xd5, +0x6d,0xb4,0x4d,0x36,0xe6,0xfa,0xf2,0x51,0x0d,0xb4,0x08,0x64,0x91,0xcf,0x60,0x3f, +0xcf,0x4a,0xf9,0x1b,0xe2,0x07,0x8e,0x6e,0xfc,0x77,0xae,0xbd,0xe4,0xe5,0xa3,0xb6, +0x8c,0x95,0xb6,0xb7,0xcf,0x11,0x27,0xf8,0x9e,0xe7,0xfa,0x62,0xbd,0x1c,0xdb,0x34, +0x8e,0x5d,0x4a,0xd1,0xd6,0x6f,0x65,0xfa,0xb3,0x7c,0x4e,0x21,0x50,0x8e,0x9b,0xb2, +0x6f,0x1e,0x7c,0x48,0xd5,0x3c,0x79,0x78,0x5a,0xe5,0xcd,0xbd,0x8a,0x1c,0xc5,0x67, +0x1b,0x1d,0x8b,0xe8,0x4f,0xf7,0x9b,0xdc,0xfe,0x18,0xae,0x4e,0x8a,0x2b,0xf2,0x5a, +0xd5,0xaa,0x62,0x26,0xea,0x55,0x77,0x6c,0xf9,0x99,0x4e,0x53,0x7c,0xd2,0x7a,0x85, +0x14,0x57,0x5d,0xe0,0x0f,0x86,0x9a,0xa7,0x8f,0xae,0x8f,0xd9,0x80,0xb7,0xb1,0x8d, +0xb1,0x2d,0xe4,0x83,0xe5,0x1f,0xec,0x81,0xfc,0x4d,0xed,0xf9,0xd3,0xa3,0x46,0xa6, +0x22,0x6a,0x9d,0x25,0x76,0xc7,0x08,0x4a,0xa4,0xb9,0x62,0xae,0xce,0x46,0xa7,0xb7, +0xb1,0xb9,0xbc,0xff,0x00,0x51,0x6f,0x2c,0xf8,0xeb,0xe5,0xa1,0x6f,0xe5,0x5f,0x55, +0xf8,0x5f,0xe0,0xe7,0x86,0x7c,0x35,0x12,0x11,0x60,0x97,0xf7,0x23,0x19,0x9e,0xf0, +0x09,0x0e,0x7d,0x40,0x3f,0x28,0xfc,0x05,0x76,0xc9,0x0a,0x46,0x00,0x55,0x0a,0x07, +0x18,0x03,0x02,0xbe,0xce,0x87,0x0b,0x54,0x94,0x6f,0x5a,0xa2,0x4f,0xb2,0x57,0xfc, +0x74,0x3d,0x58,0x65,0xd2,0x7f,0x1c,0xac,0x7c,0x3f,0x71,0xa7,0x5d,0xda,0x0c,0xcf, +0x6b,0x34,0x23,0xd6,0x48,0xca,0xff,0x00,0x31,0x55,0xeb,0xee,0x96,0x8d,0x5d,0x48, +0x60,0x08,0x3d,0x8d,0x71,0xde,0x29,0xf8,0x4d,0xe1,0xcf,0x15,0x42,0xfe,0x6d,0x8a, +0x59,0xdd,0x31,0x2c,0x2e,0xad,0x00,0x8d,0xf7,0x7a,0x9c,0x70,0xdf,0x88,0x34,0xeb, +0xf0,0xb5,0x48,0xc6,0xf4,0x6a,0x5d,0xf6,0x6a,0xc1,0x3c,0xb9,0xa5,0xee,0x4a,0xe7, +0xc8,0xf4,0x57,0x4b,0xe3,0xbf,0x02,0x5f,0xf8,0x0f,0x56,0xfb,0x25,0xd8,0xf3,0x61, +0x93,0x2d,0x05,0xca,0x8c,0x2c,0x8b,0xfd,0x08,0xee,0x3d,0xeb,0x9a,0xaf,0x89,0xab, +0x4a,0x74,0x26,0xe9,0xd4,0x56,0x68,0xf2,0x65,0x17,0x07,0xcb,0x2d,0xc2,0xac,0x69, +0xfa,0x85,0xce,0x95,0x7b,0x0d,0xdd,0x9c,0xef,0x6d,0x73,0x0b,0x6e,0x8e,0x58,0xdb, +0x05,0x4d,0x57,0xa2,0xb3,0x4d,0xc5,0xa7,0x1d,0x1a,0x25,0x3b,0x6a,0x8f,0xaa,0xfe, +0x13,0xfc,0x4d,0x8f,0xc7,0x9a,0x61,0x86,0xe3,0x6c,0x5a,0xb5,0xb2,0x8f,0x3a,0x31, +0xc0,0x91,0x7f,0xbe,0xbe,0xde,0xa3,0xb1,0xfa,0x8a,0xef,0xc5,0x7c,0x59,0xe1,0x3f, +0x12,0xdc,0x78,0x47,0xc4,0x16,0x7a,0xad,0xb1,0x25,0xe0,0x6f,0x99,0x33,0xfe,0xb1, +0x0f,0xde,0x53,0xf5,0x19,0xaf,0xb2,0xf4,0xeb,0xd8,0x75,0x2b,0x0b,0x7b,0xbb,0x77, +0x12,0x41,0x3c,0x6b,0x24,0x6c,0x3a,0x15,0x23,0x20,0xd7,0xeb,0x39,0x16,0x64,0xf1, +0xd4,0x5c,0x2a,0x3f,0x7e,0x3b,0xf9,0xae,0x8c,0xfa,0x5c,0x1d,0x77,0x5a,0x16,0x96, +0xe8,0xb3,0x48,0x4e,0xd1,0x93,0x41,0xaf,0x29,0xf8,0xf9,0xe3,0x99,0x3c,0x3f,0xa2, +0x45,0xa4,0xd9,0xc8,0x52,0xf3,0x50,0x07,0x7b,0x29,0xe5,0x22,0x1d,0x7f,0x3e,0x9f, +0x4c,0xd7,0xb5,0x8b,0xc4,0xc3,0x07,0x46,0x55,0xa7,0xb2,0x3a,0xea,0xd4,0x54,0xa0, +0xe6,0xfa,0x1c,0xff,0x00,0xc5,0x1f,0x8e,0xb2,0x2c,0xb3,0x69,0x5e,0x1b,0x94,0x2e, +0xdc,0xa4,0xba,0x82,0xf3,0xcf,0x71,0x1f,0xff,0x00,0x15,0xf9,0x7a,0xd7,0x87,0x4f, +0x3c,0xb7,0x33,0x3c,0xb3,0x48,0xf2,0xca,0xec,0x59,0x9d,0xd8,0xb3,0x31,0x3d,0x49, +0x26,0x99,0x45,0x7e,0x39,0x8d,0xc7,0xd7,0xc7,0xd4,0xe7,0xaa,0xfd,0x17,0x44,0x7c, +0xb5,0x5a,0xd3,0xac,0xef,0x20,0xa2,0x8a,0x2b,0xce,0x30,0x0a,0x2b,0xba,0xf0,0xbf, +0xc1,0x8f,0x13,0x78,0xa2,0x14,0xb8,0x4b,0x64,0xb0,0xb5,0x7e,0x56,0x5b,0xc6,0x29, +0xb8,0x7a,0x85,0x00,0x9f,0xd2,0xbb,0x28,0x3f,0x66,0x5b,0xb6,0x51,0xe7,0xeb,0xd1, +0x21,0xee,0x23,0xb6,0x2d,0xfa,0x96,0x15,0xeb,0xd1,0xca,0x31,0xd5,0xd7,0x34,0x29, +0xbb,0x79,0xe9,0xf9,0x9d,0x31,0xc3,0x56,0x9a,0xba,0x89,0xe2,0x74,0x57,0xb9,0x37, +0xec,0xc6,0xf8,0xf9,0x7c,0x42,0x3f,0x1b,0x4f,0xfe,0xce,0xaa,0x5c,0x7e,0xcc,0xfa, +0x8a,0xa9,0xf2,0x35,0xab,0x59,0x0f,0x61,0x24,0x2c,0x9f,0xc8,0x9a,0xdd,0xe4,0x59, +0x82,0xff,0x00,0x97,0x7f,0x8a,0xff,0x00,0x32,0xfe,0xa7,0x5d,0x7d,0x93,0xc6,0x28, +0xaf,0x47,0xd4,0xbe,0x01,0x78,0xb2,0xc4,0x33,0x43,0x05,0xb5,0xf2,0x8f,0xf9,0xe1, +0x38,0xcf,0xe4,0xc0,0x57,0x15,0xac,0x78,0x6b,0x56,0xf0,0xfb,0xed,0xd4,0xb4,0xdb, +0x9b,0x2e,0x70,0x1a,0x68,0xc8,0x53,0xf4,0x3d,0x0d,0x79,0xd5,0xb0,0x58,0x9c,0x3e, +0xb5,0x69,0xb5,0xf2,0x30,0x95,0x2a,0x90,0xf8,0xa3,0x63,0xac,0xf8,0x1d,0xa4,0x0d, +0x57,0xe2,0x25,0x83,0x32,0x6e,0x8e,0xd5,0x5e,0xe1,0xbd,0xb0,0x30,0xa7,0xfe,0xfa, +0x65,0xaf,0xab,0x07,0x4a,0xf0,0x8f,0xd9,0x9f,0x48,0x05,0xb5,0x9d,0x51,0x97,0xfb, +0x96,0xc8,0x7f,0xf1,0xe6,0xff,0x00,0xd9,0x6b,0xde,0x2b,0xf4,0xce,0x1d,0xa3,0xec, +0xb0,0x2a,0x5f,0xcc,0xdb,0xfd,0x3f,0x43,0xe8,0x30,0x30,0xe5,0xa3,0x7e,0xe1,0x45, +0x14,0x57,0xd3,0x9e,0x80,0x55,0x2d,0x66,0x4f,0x2b,0x4a,0xbb,0x6f,0x48,0xcd,0x5d, +0xac,0x7f,0x16,0xcb,0xe4,0x78,0x7a,0xf9,0xff,0x00,0xe9,0x99,0xac,0xea,0x3b,0x41, +0xb2,0x64,0xed,0x16,0xcf,0x83,0x7e,0x27,0xcf,0xe7,0x78,0xa6,0xf4,0x83,0x9c,0x12, +0x3f,0x5a,0xf9,0xc3,0xe2,0xbc,0x5f,0xda,0x1a,0xa6,0x95,0x65,0xb7,0x79,0xb8,0xbd, +0x82,0x1d,0x9d,0x77,0x6e,0x91,0x57,0x1f,0xad,0x7d,0x01,0xe3,0xa9,0xbc,0xdd,0x7a, +0xf5,0xb3,0x9f,0x9c,0x8a,0xf1,0x3b,0xa8,0x3f,0xb4,0xfe,0x36,0xfc,0x3b,0xb2,0xed, +0x37,0x88,0xf4,0xe4,0xfa,0x8f,0xb4,0xc7,0xfe,0x15,0xf9,0xde,0x54,0xb9,0xb1,0x2d, +0xf9,0xfe,0xa7,0xe3,0x33,0x5e,0xd7,0x36,0xa4,0xbf,0xbc,0x7e,0xb6,0xff,0x00,0x61, +0x5a,0xff,0x00,0xcf,0xba,0xfe,0x54,0x56,0xad,0x15,0xfa,0x2f,0x2a,0x3f,0x66,0xb2, +0x1f,0x45,0x14,0x55,0x94,0x14,0xd2,0x69,0xd5,0xc8,0xfc,0x55,0xf1,0x6f,0xfc,0x21, +0x1e,0x01,0xd6,0xb5,0x75,0x60,0xb3,0xc3,0x09,0x48,0x33,0x8f,0xf5,0xad,0xf2,0xa7, +0x07,0xaf,0x24,0x1c,0x7b,0x56,0x75,0x26,0xa9,0xc1,0xce,0x5b,0x23,0x3a,0x93,0x54, +0xa0,0xe7,0x2d,0x96,0xa7,0xc8,0x5f,0x1f,0xbc,0x5f,0xff,0x00,0x09,0x8f,0xc4,0xfd, +0x4e,0x48,0xa4,0x2f,0x69,0x64,0x45,0x94,0x18,0x24,0x8c,0x26,0x77,0x11,0xf5,0x62, +0xdf,0xa5,0x7b,0xc7,0xec,0xaf,0xe1,0x1f,0xec,0x7f,0x08,0x4d,0xab,0x4a,0x98,0x9a, +0xf9,0xfe,0x52,0x47,0x3b,0x05,0x7c,0xa9,0xa0,0x69,0x73,0xf8,0x83,0x5d,0xb5,0xb3, +0x8c,0x19,0x66,0xb9,0x98,0x2f,0xa9,0x24,0x9e,0x4d,0x7e,0x85,0x78,0x67,0x45,0x8b, +0xc3,0xfa,0x0d,0x8e,0x9f,0x12,0x85,0x4b,0x78,0x95,0x30,0x3d,0x40,0xe6,0xbe,0x27, +0x28,0x83,0xc5,0xe3,0x27,0x8a,0x9f,0x4f,0xcd,0xff,0x00,0xc0,0x3e,0x27,0x23,0x84, +0xb1,0x58,0x9a,0x98,0xc9,0xff,0x00,0x57,0x34,0xc5,0x2d,0x14,0x57,0xdd,0x1f,0x74, +0x14,0x51,0x45,0x00,0x32,0x49,0x16,0x18,0xd9,0xdd,0x82,0x22,0x82,0x59,0x98,0xe0, +0x01,0xea,0x6b,0xe0,0x7f,0xda,0x6b,0xfe,0x0a,0xd3,0xe0,0xaf,0x85,0x9a,0x95,0xe7, +0x87,0xbe,0x1e,0x69,0xc9,0xe3,0xcd,0x72,0xdd,0x8c,0x73,0x5f,0xb4,0xa6,0x3d,0x36, +0x17,0x07,0x95,0x0e,0x3e,0x69,0x88,0xff,0x00,0x67,0x0b,0xfe,0xd7,0x5a,0xe2,0xbf, +0xe0,0xad,0x3f,0xb5,0xed,0xe7,0x84,0xed,0x62,0xf8,0x37,0xe1,0x3b,0xf6,0xb6,0xbe, +0xd4,0x2d,0xc5,0xc7,0x88,0x6e,0xa0,0x7c,0x3c,0x76,0xef,0xfe,0xae,0xd8,0x10,0x78, +0x2e,0x3e,0x66,0xff,0x00,0x64,0xa8,0xe8,0xc6,0xbe,0x5a,0xfd,0x8a,0x7f,0xe0,0x9d, +0x9a,0xff,0x00,0xed,0x53,0xa7,0xc9,0xe2,0x9d,0x5f,0x55,0x3e,0x15,0xf0,0x3c,0x53, +0x18,0x12,0xed,0x21,0xf3,0x2e,0x6f,0x5d,0x71,0xb9,0x61,0x52,0x40,0x0a,0xbd,0x0b, +0xb6,0x46,0x78,0x00,0xe0,0xe1,0x92,0xfc,0x8c,0xef,0x1a,0xff,0x00,0xc1,0x51,0x7f, +0x68,0x5f,0x17,0xcd,0x37,0x91,0xe2,0xeb,0x7f,0x0e,0xdb,0x3b,0x16,0x5b,0x7d,0x1b, +0x4f,0x86,0x30,0x83,0xb0,0x0e,0xea,0xcf,0xf9,0xb5,0x7d,0x1d,0xff,0x00,0x04,0xc4, +0xf8,0xc5,0xf1,0xb7,0xf6,0x81,0xf8,0xe3,0x7d,0x71,0xe2,0x9f,0x88,0x1a,0xe6,0xad, +0xe0,0xff,0x00,0x0f,0xd8,0xbd,0xd5,0xe5,0xb5,0xc3,0x29,0x86,0x79,0xe4,0xcc,0x70, +0xc4,0xc7,0x6e,0x47,0x57,0x93,0x03,0xfe,0x79,0x57,0xc9,0xbf,0xb7,0x6f,0xc0,0x4f, +0x01,0xfe,0xcd,0x7f,0x18,0x6d,0xbc,0x0b,0xe0,0x8d,0x57,0x58,0xd5,0xde,0xd7,0x4f, +0x8e,0xe3,0x53,0x9f,0x57,0x9e,0x29,0x19,0x27,0x90,0x96,0x58,0xc0,0x8e,0x34,0x0b, +0x88,0xf6,0x31,0xce,0x7f,0xd6,0x0e,0x98,0xaf,0xd3,0xef,0xf8,0x25,0x5f,0xc1,0x81, +0xf0,0xbf,0xf6,0x5f,0xb1,0xd7,0x2e,0xad,0xfc,0xad,0x5f,0xc5,0xf3,0x9d,0x56,0x56, +0x3f,0x7b,0xec,0xff,0x00,0x72,0xdd,0x7d,0x86,0xd0,0x5b,0xfe,0xda,0x50,0x08,0x8f, +0xe3,0x97,0xfc,0x15,0x17,0xc0,0x9f,0x00,0x7e,0x2c,0xeb,0xfe,0x01,0xd7,0xfc,0x21, +0xe2,0x5b,0xbd,0x43,0x48,0x92,0x34,0x92,0xea,0xc4,0x5b,0xb4,0x32,0x07,0x89,0x24, +0x56,0x5d,0xd2,0x29,0xe8,0xe3,0xb7,0x50,0x6b,0xe8,0x3f,0xd9,0xdb,0xe3,0xe6,0x87, +0xfb,0x4a,0xfc,0x30,0xb3,0xf1,0xc7,0x87,0x6c,0xef,0xac,0x34,0xcb,0x99,0xe5,0xb7, +0x58,0x35,0x15,0x45,0x98,0x34,0x6d,0xb5,0xb2,0x15,0x98,0x63,0x3d,0x39,0xaf,0xc2, +0xdf,0xdb,0xb3,0xc7,0x76,0x9f,0x11,0xbf,0x6b,0x6f,0x89,0x5a,0xcd,0x84,0xbe,0x75, +0x90,0xd4,0xbe,0xc5,0x13,0x8e,0x84,0x5b,0xc6,0x90,0x12,0x3d,0x8b,0x46,0xc7,0xf1, +0xaf,0xd8,0xaf,0xf8,0x27,0x2f,0x81,0x67,0xf0,0x0f,0xec,0x75,0xf0,0xfa,0xd2,0xe5, +0x59,0x2e,0x2f,0xed,0xa4,0xd5,0x59,0x58,0x60,0x81,0x71,0x2b,0x4a,0x9f,0xf8,0xe3, +0x2d,0x03,0x4f,0x53,0xe9,0x19,0xa7,0x5b,0x78,0x9e,0x49,0x18,0x24,0x68,0xa5,0x99, +0x98,0xe0,0x00,0x3b,0xd7,0xc5,0xfe,0x2d,0xd7,0x5f,0xc4,0xde,0x25,0xd4,0x75,0x37, +0x27,0xfd,0x22,0x66,0x65,0x07,0xb2,0x74,0x51,0xf8,0x00,0x05,0x7d,0x29,0xf1,0xbf, +0xc4,0x5f,0xd8,0x1e,0x01,0xbc,0x54,0x70,0xb7,0x17,0xc4,0x5a,0x46,0x3d,0x43,0x7d, +0xff,0x00,0xfc,0x74,0x37,0xe9,0x5f,0x2a,0x57,0xe7,0x1c,0x51,0x8a,0xe6,0x9c,0x30, +0xeb,0xa6,0xaf,0xe7,0xb1,0xe1,0xe6,0x15,0x2f,0x25,0x4f,0xe6,0x14,0x51,0x45,0x7c, +0x29,0xe3,0x9a,0x5e,0x1a,0x92,0xc6,0x2d,0x7f,0x4f,0x93,0x52,0x25,0x6c,0x23,0x99, +0x5e,0x6d,0xab,0xb8,0x95,0x07,0x24,0x60,0x7a,0xe3,0x1f,0x8d,0x7d,0x2b,0x1f,0xc7, +0x9f,0x06,0xb0,0x03,0xed,0xf2,0xaf,0xd6,0xda,0x4f,0xf0,0xaf,0x96,0x28,0xaf,0x6b, +0x01,0x9b,0x56,0xcb,0xa3,0x28,0xd2,0x49,0xdf,0xbf,0xfc,0x39,0xd7,0x47,0x13,0x3a, +0x09,0xa8,0xad,0xcf,0xaa,0xcf,0xc7,0x5f,0x06,0x81,0x9f,0xed,0x37,0xff,0x00,0xc0, +0x69,0x3f,0xf8,0x9a,0xc7,0xd6,0x3f,0x68,0xcf,0x0e,0xda,0x44,0xc2,0xc6,0xde,0xef, +0x50,0x97,0xb0,0xd9,0xe5,0xaf,0xe2,0x4f,0x3f,0xa5,0x7c,0xd9,0x45,0x7a,0x53,0xe2, +0x6c,0x6c,0x95,0x92,0x8a,0xf9,0x7f,0xc1,0x37,0x79,0x85,0x67,0xb5,0x8e,0xa7,0xc7, +0x5f,0x11,0x35,0x5f,0x1e,0xdd,0xab,0xde,0x32,0xc3,0x69,0x19,0x26,0x1b,0x48,0xbe, +0xe2,0x7b,0x9f,0x53,0xee,0x7f,0x0c,0x57,0x2d,0x45,0x6b,0xe9,0x1e,0x12,0xd6,0xb5, +0xed,0xa7,0x4f,0xd2,0xee,0xae,0x91,0xba,0x3c,0x71,0x1d,0x9f,0xf7,0xd7,0x4f,0xd6, +0xbe,0x72,0x73,0xad,0x8b,0xa8,0xe5,0x2b,0xca,0x4f,0xe6,0x70,0xc9,0xce,0xac,0xae, +0xf5,0x66,0x45,0x69,0x78,0x7b,0xc3,0xb7,0xfe,0x29,0xd5,0x21,0xd3,0xf4,0xe8,0x0c, +0xd7,0x12,0x1f,0xf8,0x0a,0x0e,0xec,0xc7,0xb0,0x15,0xe9,0x5e,0x18,0xfd,0x9d,0x75, +0x7d,0x45,0xd2,0x4d,0x66,0xe2,0x3d,0x36,0x0e,0x09,0x8a,0x32,0x24,0x94,0x8f,0x4e, +0x38,0x1f,0x99,0xfa,0x57,0xb9,0x78,0x4f,0xc1,0x7a,0x57,0x82,0xec,0x3e,0xcb,0xa6, +0x5b,0x08,0xb3,0x83,0x24,0xad,0xcc,0x92,0x1f,0x56,0x6e,0xff,0x00,0x4e,0x83,0xb0, +0x15,0xf4,0x79,0x7f,0x0f,0xe2,0x31,0x12,0x52,0xc4,0x2e,0x48,0xfe,0x2f,0xfa,0xf3, +0x3b,0xa8,0x60,0xa7,0x37,0x79,0xe8,0x8a,0xfe,0x01,0xf0,0x5d,0xaf,0x81,0xbc,0x3f, +0x0e,0x9f,0x6e,0x7c,0xc9,0x4f,0xcf,0x3c,0xf8,0xc1,0x95,0xcf,0x53,0xf4,0xec,0x3d, +0x85,0x74,0xb4,0x94,0xb5,0xfa,0x7d,0x2a,0x51,0xa3,0x05,0x4e,0x0a,0xc9,0x1f,0x43, +0x18,0xa8,0xa5,0x15,0xb0,0x51,0x45,0x15,0xa9,0x41,0x5e,0x6f,0xf1,0xeb,0x5c,0xfe, +0xc9,0xf0,0x05,0xc4,0x0a,0xdb,0x65,0xbe,0x91,0x6d,0xd7,0x1e,0x99,0xdc,0xdf,0xa0, +0x23,0xf1,0xaf,0x47,0x3d,0x2b,0xe7,0x8f,0xda,0x4f,0x5b,0xfb,0x4e,0xbd,0xa6,0x69, +0x68,0xdf,0x25,0xac,0x26,0x67,0x03,0xfb,0xce,0x70,0x3f,0x20,0xbf,0xad,0x78,0x79, +0xd5,0x7f,0xab,0xe0,0x6a,0x49,0x6e,0xf4,0xfb,0xce,0x4c,0x5c,0xf9,0x28,0xc9,0x9e, +0x39,0x45,0x14,0x57,0xe3,0x67,0xca,0x85,0x7a,0x67,0xec,0xfb,0xa2,0xff,0x00,0x69, +0x78,0xec,0x5d,0xba,0x93,0x1d,0x84,0x0d,0x2e,0x7b,0x07,0x6f,0x95,0x41,0xfc,0x0b, +0x1f,0xc2,0xbc,0xce,0xbe,0x89,0xfd,0x9b,0x74,0x41,0x6b,0xe1,0xdd,0x47,0x54,0x65, +0x22,0x4b,0xc9,0xc4,0x4a,0x4f,0x42,0x91,0x8e,0x08,0xfc,0x59,0x87,0xe1,0x5e,0xf6, +0x47,0x43,0xdb,0xe3,0xe0,0x9e,0xcb,0x5f,0xbb,0xfe,0x09,0xd9,0x84,0x87,0x3d,0x68, +0xf9,0x6a,0x7b,0x08,0xe9,0x4b,0x45,0x15,0xfb,0x11,0xf5,0x21,0x48,0x4e,0x29,0x6a, +0x9e,0xad,0xa8,0xc5,0xa4,0xe9,0xb7,0x57,0xb3,0x9c,0x43,0x6f,0x13,0x4a,0xe7,0xd9, +0x41,0x27,0xf9,0x54,0xc9,0xa8,0xa6,0xde,0xc2,0x6e,0xda,0xb3,0xc3,0x3f,0x68,0x9f, +0x1b,0xb5,0xc5,0xdc,0x3e,0x1b,0xb5,0x90,0x88,0xa2,0x02,0x6b,0xbd,0xa7,0xef,0x31, +0xe5,0x50,0xfd,0x07,0xcd,0x8f,0x71,0xe9,0x5e,0x27,0x57,0x35,0x9d,0x52,0x7d,0x6f, +0x55,0xbb,0xd4,0x2e,0x4e,0x67,0xb9,0x95,0xa5,0x7f,0xa9,0x39,0xc7,0xd0,0x74,0xfc, +0x2a,0x9d,0x7e,0x25,0x98,0x62,0xe5,0x8d,0xc4,0xca,0xb3,0xdb,0xa7,0xa7,0x43,0xe4, +0xab,0xd5,0x75,0xaa,0x39,0x30,0xa2,0x8a,0x2b,0xce,0x30,0x3a,0x5f,0x87,0xde,0x0a, +0x9f,0xc7,0x5e,0x22,0x86,0xc2,0x32,0x63,0xb7,0x5f,0xde,0x5c,0x4c,0x07,0xdc,0x8f, +0xbf,0xe2,0x7a,0x0f,0xfe,0xb5,0x7d,0x71,0xa3,0x69,0x16,0x9a,0x16,0x9b,0x05,0x8d, +0x8c,0x2b,0x6f,0x6b,0x02,0xed,0x48,0xd0,0x71,0xf5,0x3e,0xa4,0xf5,0x27,0xa9,0xae, +0x13,0xe0,0x4f,0x84,0xd7,0xc3,0xde,0x0d,0x8a,0xf2,0x44,0x02,0xf3,0x52,0xc5,0xc3, +0x92,0x39,0x11,0xff,0x00,0xcb,0x31,0xf9,0x73,0xf5,0x63,0x5e,0x93,0x5f,0xad,0x64, +0x59,0x7c,0x70,0x98,0x75,0x52,0x4b,0xdf,0x9e,0xaf,0xc9,0x74,0x47,0xd2,0xe0,0xe8, +0x2a,0x54,0xd4,0x9e,0xec,0x4a,0x5a,0x28,0xaf,0xa6,0x3d,0x00,0xa2,0x8a,0x28,0x03, +0x8c,0xf8,0xb1,0xe1,0x58,0xbc,0x55,0xe0,0xbb,0xe8,0x76,0x03,0x75,0x6e,0x86,0xe2, +0xdd,0xb1,0xc8,0x75,0x19,0xc0,0xfa,0x8c,0x8f,0xc6,0xbe,0x47,0xaf,0xb9,0xe4,0x50, +0xe8,0x54,0x8c,0x82,0x30,0x6b,0xe2,0x0d,0x46,0x11,0x6f,0xa8,0xdd,0x42,0x3a,0x47, +0x2b,0xa0,0xfc,0x09,0x15,0xf9,0xd7,0x14,0xd0,0x8c,0x67,0x4e,0xb2,0xdd,0xdd,0x3f, +0x91,0xe1,0x66,0x30,0x49,0xc6,0x5d,0xca,0xf4,0x51,0x45,0x7c,0x21,0xe3,0x85,0x7d, +0x49,0xf0,0x17,0x5a,0x6d,0x57,0xe1,0xf5,0xb4,0x4e,0xe5,0xe4,0xb2,0x95,0xed,0xc9, +0x3e,0x83,0xe6,0x51,0xf8,0x2b,0x01,0xf8,0x57,0xcb,0x75,0xf4,0x27,0xec,0xcf,0x29, +0x3a,0x0e,0xb3,0x1f,0x65,0xba,0x56,0xfc,0xd3,0x1f,0xd2,0xbe,0xa7,0x86,0xea,0x38, +0x63,0x94,0x57,0x54,0xff,0x00,0xcc,0xf4,0x70,0x12,0x6a,0xb5,0xbb,0x9e,0xcc,0x6b, +0xe5,0x2f,0x8e,0x1a,0x9b,0xea,0x3f,0x11,0xb5,0x14,0x66,0x2d,0x1d,0xa8,0x48,0x23, +0x1e,0x80,0x28,0x27,0xff,0x00,0x1e,0x66,0xaf,0xab,0x3b,0x57,0xc8,0xdf,0x17,0x6d, +0x5a,0xd3,0xe2,0x3e,0xb8,0xad,0xd5,0xa6,0x12,0x0f,0xa3,0x28,0x23,0xf9,0xd7,0xd3, +0x71,0x3c,0xa4,0xb0,0x91,0x4b,0x67,0x2f,0xd1,0x9d,0xf9,0x83,0xfd,0xd2,0xf5,0x38, +0xfa,0x28,0xa2,0xbf,0x30,0x3e,0x7c,0x2b,0xb7,0xf8,0x35,0xa3,0xd9,0xeb,0x5e,0x3f, +0xb0,0x8a,0xf7,0x6b,0x45,0x18,0x69,0x96,0x37,0xe4,0x48,0xca,0x32,0xa3,0xf3,0xe7, +0xf0,0xae,0x22,0xac,0xe9,0xba,0x8d,0xce,0x91,0x7f,0x05,0xed,0xa4,0xcd,0x05,0xcc, +0x0e,0x1e,0x39,0x13,0xaa,0x91,0x5d,0x38,0x6a,0x91,0xa3,0x5e,0x15,0x26,0xae,0x93, +0x4e,0xc5,0xd3,0x92,0x8c,0xd4,0x9e,0xc7,0xdb,0xea,0x38,0xc5,0x3b,0x15,0xe2,0xbe, +0x10,0xfd,0xa3,0x2c,0xe7,0x8d,0x21,0xf1,0x0d,0xb3,0xda,0xcc,0x38,0x37,0x56,0xeb, +0xba,0x33,0xee,0x57,0xa8,0xfc,0x33,0x5e,0xa7,0xa3,0x78,0xbb,0x46,0xf1,0x0a,0x06, +0xd3,0xb5,0x2b,0x6b,0xbf,0x55,0x8e,0x41,0xb8,0x7d,0x57,0xa8,0xaf,0xd9,0x70,0xb9, +0x86,0x17,0x16,0x93,0xa5,0x35,0xe9,0xd7,0xee,0x3e,0xae,0x9d,0x7a,0x75,0x7e,0x16, +0x6b,0xe2,0x82,0x29,0x37,0x52,0xe6,0xbd,0x23,0x70,0xc7,0xe3,0x4c,0x9e,0xde,0x3b, +0x98,0xda,0x39,0x51,0x64,0x8d,0x86,0x19,0x1d,0x72,0x08,0xf4,0x22,0xa4,0xa2,0x95, +0x93,0xdc,0x2c,0x50,0xd2,0x74,0x2b,0x0d,0x06,0x29,0x62,0xd3,0xed,0x21,0xb3,0x8a, +0x49,0x0c,0xad,0x1c,0x08,0x15,0x4b,0x10,0x01,0x38,0x1f,0x41,0x57,0xe8,0xa2,0x94, +0x62,0xa2,0xad,0x15,0x64,0x24,0x92,0xd1,0x05,0x14,0x51,0x54,0x30,0xae,0x67,0xe2, +0x24,0xfe,0x47,0x85,0x2f,0x5b,0xa1,0xdb,0x8a,0xe9,0xab,0x88,0xf8,0xbd,0x71,0xf6, +0x7f,0x07,0xdc,0x1c,0xe3,0x3f,0xe1,0x5c,0xb8,0xa9,0x72,0xd0,0x9b,0xf2,0x66,0x35, +0x9d,0xa9,0xc9,0x9f,0x08,0x78,0xa6,0x5d,0xfa,0x9d,0xe3,0x67,0xf8,0xcd,0x79,0xb7, +0xc3,0x9b,0x15,0xd7,0x3f,0x6a,0xdf,0x86,0x16,0x6f,0xc8,0x1a,0xd4,0x73,0xe3,0xde, +0x25,0x69,0x47,0xea,0x95,0xdf,0x6b,0xaf,0xba,0x7b,0x86,0xf5,0x63,0x5c,0x9f,0xec, +0xe3,0x0b,0xea,0x3f,0xb6,0xaf,0xc3,0xb4,0x0b,0xb9,0x21,0x96,0xf6,0x66,0xf6,0x0b, +0x67,0x3e,0x0f,0xe6,0x45,0x7c,0x36,0x48,0xaf,0x56,0xe7,0xe4,0x38,0x15,0xed,0x33, +0x9a,0x5e,0xad,0x9f,0xab,0x7b,0x68,0xa5,0xcd,0x15,0xfa,0x21,0xfb,0x08,0xb4,0x51, +0x45,0x22,0xc4,0xcd,0x7c,0xcb,0xfb,0x60,0xf8,0xbc,0xee,0xd1,0xfc,0x33,0x0b,0xe0, +0x1c,0xdf,0x5c,0x80,0x4f,0xba,0xc6,0x3e,0x9f,0x7c,0xfe,0x02,0xbe,0x97,0x95,0xc4, +0x68,0xce,0xc4,0x2a,0xa8,0x24,0x92,0x70,0x00,0xaf,0xcf,0xaf,0x89,0xbe,0x2c,0x93, +0xc6,0xfe,0x3c,0xd6,0x35,0x56,0x72,0xf1,0x4b,0x39,0x8e,0x01,0x9c,0x85,0x89,0x7e, +0x54,0xc7,0xe0,0x33,0xf8,0xd7,0xce,0x67,0x98,0x8f,0x63,0x86,0xf6,0x6b,0x79,0x69, +0xf2,0xea,0x7c,0xc7,0x10,0x62,0x7d,0x96,0x17,0xd9,0x47,0x79,0xbb,0x7c,0xba,0x9e, +0x89,0xfb,0x2d,0x78,0x47,0xfb,0x6b,0xc6,0x8d,0xa9,0xcb,0x1e,0xe8,0x2c,0x17,0x70, +0x27,0xa6,0xf3,0xd2,0xbe,0xc4,0x1d,0x2b,0xca,0x3f,0x67,0x0f,0x08,0xff,0x00,0xc2, +0x37,0xf0,0xfe,0x09,0xe4,0x4d,0xb7,0x17,0xc7,0xce,0x62,0x47,0x38,0xed,0x5e,0xaf, +0x5d,0x19,0x3e,0x1f,0xd8,0x61,0x63,0x7d,0xe5,0xab,0xf9,0xff,0x00,0xc0,0x3d,0x0c, +0xab,0x0d,0xf5,0x6c,0x24,0x62,0xf7,0x7a,0xb1,0x68,0xa2,0x8a,0xf6,0xcf,0x5c,0x29, +0x09,0xa5,0xa4,0xc5,0x00,0x7f,0x37,0xdf,0xb5,0x6f,0x8c,0xaf,0x3c,0x7d,0xfb,0x4a, +0x7c,0x4c,0xd6,0xef,0x9c,0xc9,0x34,0xda,0xfd,0xe4,0x28,0x4f,0x55,0x8a,0x29,0x4c, +0x51,0x2f,0xe1,0x1c,0x68,0x3f,0x0a,0xfd,0x53,0xfd,0x82,0x7f,0x6c,0xcf,0x83,0xf6, +0x1f,0xb3,0x47,0x85,0xfc,0x31,0xa9,0xf8,0xa7,0x4c,0xf0,0xae,0xbb,0xe1,0xbb,0x13, +0x6f,0x77,0xa7,0x6a,0x93,0xad,0xb1,0x99,0x94,0xb3,0x19,0x62,0x67,0x20,0x49,0xbf, +0x24,0xe0,0x1c,0xe4,0x90,0x47,0x4a,0xf8,0x47,0xfe,0x0a,0x39,0xfb,0x2b,0x78,0x83, +0xe0,0x87,0xc7,0x0f,0x10,0xf8,0xa2,0x1d,0x3e,0x69,0xfc,0x11,0xe2,0x7b,0xf9,0x75, +0x1b,0x2d,0x4a,0x35,0xdd,0x1c,0x32,0xca,0xdb,0xe5,0x82,0x4c,0x0f,0x91,0x83,0xb3, +0x6d,0xcf,0x55,0x23,0x07,0x39,0x03,0xe4,0x43,0xc7,0x19,0xaa,0x22,0xf6,0x67,0xaf, +0x6b,0x7a,0xcd,0xcf,0xed,0x4b,0xfb,0x51,0x5c,0xea,0x1a,0x95,0xf2,0x58,0x0f,0x17, +0x78,0x83,0x32,0x5d,0x5d,0xca,0xa8,0xb6,0x76,0xaf,0x20,0x03,0x73,0x36,0x00,0x11, +0xc2,0x00,0xe7,0xfb,0x95,0xfa,0x69,0xfb,0x5b,0xff,0x00,0xc1,0x44,0x3e,0x1f,0x7c, +0x15,0xf8,0x50,0xfe,0x01,0xf8,0x43,0xac,0xda,0x78,0x83,0xc4,0xc7,0x4f,0x5d,0x32, +0xd2,0xe7,0x49,0x71,0x2d,0xa6,0x95,0x08,0x4f,0x2c,0x48,0x65,0x19,0x57,0x90,0x28, +0xf9,0x55,0x49,0xc1,0xc1,0x38,0xc6,0x0f,0xe3,0x6f,0x5a,0xf5,0x3f,0x80,0xff,0x00, +0xb3,0x47,0xc4,0x3f,0xda,0x3b,0xc4,0x91,0x69,0x3e,0x0b,0xd0,0x66,0xbc,0x8b,0x78, +0x17,0x3a,0x9c,0xe0,0xc7,0x65,0x6a,0x33,0xcb,0x4b,0x2e,0x30,0x31,0x9f,0xba,0x32, +0xc7,0xb0,0x34,0x09,0x17,0x3f,0x65,0xcf,0x80,0x7a,0xc7,0xed,0x37,0xf1,0xb7,0x43, +0xf0,0x8d,0x92,0xcc,0x6d,0x27,0x9b,0xed,0x3a,0xb5,0xf8,0xc9,0xfb,0x35,0xa2,0x90, +0x65,0x90,0x9e,0x79,0x3f,0x75,0x73,0xd5,0x99,0x6b,0xfa,0x2e,0xd2,0xb4,0xcb,0x6d, +0x13,0x4b,0xb4,0xd3,0xec,0xa2,0x58,0x2c,0xed,0x21,0x48,0x21,0x89,0x06,0x02,0x22, +0xa8,0x55,0x03,0xe8,0x00,0xaf,0x0f,0xfd,0x90,0xff,0x00,0x64,0x5f,0x0d,0x7e,0xc9, +0xbe,0x00,0x1a,0x4e,0x98,0xcb,0xaa,0x78,0x86,0xfb,0x6c,0x9a,0xb6,0xb6,0xf1,0xed, +0x7b,0x99,0x00,0xe1,0x50,0x73,0xb2,0x35,0xe7,0x6a,0xe4,0xf5,0x24,0x92,0x6b,0xdd, +0x2f,0x6f,0x22,0xb0,0xb4,0x9e,0xe6,0x76,0xd9,0x0c,0x31,0xb4,0x8e,0xc7,0xb2,0x81, +0x92,0x7f,0x2a,0x87,0x24,0x95,0xd9,0x5b,0x23,0xe7,0x6f,0xda,0x2f,0xc4,0x7f,0xda, +0x1e,0x26,0xb5,0xd2,0xa3,0x6c,0xc7,0x61,0x16,0xe7,0x19,0xe3,0xcc,0x7c,0x1f,0xd1, +0x42,0xfe,0x75,0xe4,0x95,0xa1,0xe2,0x0d,0x62,0x4f,0x10,0x6b,0x97,0xfa,0x94,0xbf, +0x7e,0xea,0x66,0x97,0x1e,0x80,0x9e,0x07,0xe0,0x30,0x3f,0x0a,0xcf,0xaf,0xc4,0x31, +0xf8,0x87,0x8a,0xc5,0x4e,0xb7,0x77,0xf8,0x74,0x3e,0x4a,0xb5,0x4f,0x6b,0x51,0xcc, +0x28,0xa2,0xba,0x5f,0x87,0x1e,0x1f,0xff,0x00,0x84,0x9f,0xc6,0xba,0x5d,0x8b,0x2e, +0xe8,0x4c,0xa2,0x49,0x81,0xe9,0xb1,0x7e,0x66,0x07,0xeb,0x8c,0x7e,0x35,0xcb,0x46, +0x94,0xab,0x54,0x8d,0x28,0xef,0x27,0x6f,0xbc,0xce,0x31,0x73,0x92,0x8a,0xea,0x61, +0x49,0xa7,0xdd,0x43,0xfe,0xb2,0xda,0x64,0xff,0x00,0x7a,0x32,0x2a,0xb9,0x18,0x35, +0xf7,0x40,0x41,0x80,0x36,0x8c,0x56,0x37,0x88,0x3c,0x17,0xa3,0x78,0x9e,0xd9,0xe1, +0xd4,0x34,0xe8,0x27,0xdc,0x31,0xe6,0x6c,0x02,0x45,0xf7,0x0c,0x39,0x15,0xf7,0x15, +0x38,0x56,0x49,0x5e,0x9d,0x5b,0xbf,0x35,0xff,0x00,0x04,0xf5,0xe5,0x97,0x3b,0x7b, +0xb2,0x3e,0x30,0xa2,0xba,0x4f,0x88,0x3e,0x0e,0x97,0xc0,0xfe,0x26,0xb8,0xd3,0x5d, +0x8c,0x90,0xe0,0x4b,0x04,0xad,0xd5,0xe3,0x3d,0x09,0xf7,0x18,0x20,0xfb,0x8a,0xe6, +0xeb,0xe1,0xaa,0xd2,0x9d,0x1a,0x8e,0x9c,0xd5,0x9a,0xd0,0xf2,0x25,0x17,0x06,0xe2, +0xfa,0x05,0x74,0x7e,0x0d,0xf1,0xde,0xab,0xe0,0x9d,0x4a,0x3b,0x8b,0x2b,0x87,0x36, +0xfb,0x81,0x96,0xd5,0x98,0xf9,0x72,0xaf,0x70,0x47,0x63,0xef,0xd4,0x57,0x39,0x45, +0x14,0xaa,0xce,0x8c,0xd5,0x4a,0x6e,0xcd,0x04,0x64,0xe0,0xf9,0xa3,0xb9,0xf7,0x06, +0x95,0xa8,0xc3,0xab,0xe9,0xb6,0xd7,0xb6,0xed,0xba,0x0b,0x88,0xd6,0x54,0x3e,0xc4, +0x64,0x7f,0x3a,0xb7,0x5c,0x27,0xc1,0x2b,0xef,0xb7,0x7c,0x37,0xd2,0x49,0x39,0x68, +0x83,0xc2,0x7f,0xe0,0x2e,0x40,0xfd,0x31,0x5d,0xdd,0x7e,0xe5,0x86,0xab,0xed,0xe8, +0x42,0xaf,0x74,0x9f,0xde,0x8f,0xaf,0xa7,0x2e,0x78,0x29,0x77,0x0a,0x28,0xa2,0xba, +0x4d,0x02,0x8a,0x28,0xa0,0x04,0x27,0x00,0xd7,0xc7,0x1f,0x11,0x35,0xcf,0xf8,0x48, +0xbc,0x6d,0xac,0x5f,0x2b,0x07,0x8d,0xa7,0x64,0x8c,0x8e,0x85,0x17,0xe5,0x53,0xf8, +0x80,0x0f,0xe3,0x5f,0x54,0x78,0xf7,0x5d,0xff,0x00,0x84,0x73,0xc1,0xfa,0xb6,0xa0, +0xae,0x12,0x48,0xad,0xdb,0xcb,0x2d,0xd3,0x79,0x18,0x4f,0xfc,0x78,0x8a,0xf8,0xcc, +0x0c,0x0c,0x57,0xc0,0x71,0x4d,0x7d,0x29,0xd0,0x5e,0xaf,0xf2,0x5f,0xa9,0xe2,0xe6, +0x33,0xf8,0x60,0x2d,0x14,0x51,0x5f,0x9f,0x1e,0x20,0x57,0xd8,0xdf,0x0e,0xb4,0x4f, +0xec,0x0f,0x04,0xe8,0xf6,0x44,0x61,0xd6,0xdd,0x5d,0xc7,0xfb,0x4d,0xf3,0x37,0xea, +0xc6,0xbe,0x53,0xf0,0x5e,0x91,0xfd,0xbf,0xe2,0xcd,0x27,0x4f,0xc6,0x56,0x7b,0x94, +0x0e,0x3f,0xd9,0x07,0x2d,0xfa,0x03,0x5f,0x68,0x28,0x01,0x40,0x1c,0x01,0x5f,0x7f, +0xc2,0xd4,0x3f,0x89,0x5d,0xfa,0x7e,0xaf,0xf4,0x3d,0xac,0xba,0x1f,0x14,0xfe,0x41, +0x4b,0x45,0x15,0xfa,0x09,0xed,0x85,0x79,0xb7,0xc7,0xed,0x63,0xfb,0x2f,0xe1,0xfc, +0xf0,0xa9,0x2b,0x25,0xf4,0xc9,0x6e,0xa4,0x7a,0x67,0x73,0x7e,0x88,0x47,0xe3,0x5e, +0x93,0x5e,0x17,0xfb,0x4e,0x6a,0x0e,0xb1,0xe8,0x36,0x4a,0x7e,0x46,0x32,0xcc,0xc3, +0xdc,0x6d,0x03,0xf9,0xb5,0x78,0xd9,0xc5,0x57,0x47,0x01,0x56,0x4b,0xb5,0xbe,0xfd, +0x0e,0x5c,0x54,0xb9,0x28,0xc9,0x9e,0x11,0x45,0x14,0x57,0xe3,0x07,0xca,0x05,0x5e, +0xd0,0xb4,0xc6,0xd6,0xb5,0xab,0x0d,0x3d,0x0e,0x1a,0xea,0x74,0x87,0x3e,0x9b,0x88, +0x19,0xaa,0x35,0xda,0x7c,0x1b,0xb4,0x5b,0xdf,0x89,0x3a,0x2a,0x3f,0xdd,0x57,0x79, +0x3f,0x15,0x8d,0x88,0xfd,0x40,0xae,0xac,0x2d,0x3f,0x6d,0x5e,0x14,0xdf,0x56,0x97, +0xe2,0x69,0x4e,0x3c,0xd3,0x8c,0x7c,0xcf,0xac,0xad,0xa0,0x8e,0xd6,0xde,0x28,0x62, +0x50,0x91,0x46,0xa1,0x11,0x47,0x40,0x00,0xc0,0x02,0xa5,0xa4,0x14,0xb5,0xfb,0xaa, +0x49,0x2b,0x23,0xec,0x42,0x8a,0x28,0xa6,0x01,0x45,0x14,0x50,0x04,0x73,0x38,0x86, +0x27,0x76,0x38,0x55,0x04,0x93,0xf8,0x57,0xc3,0xd7,0x93,0x7d,0xa6,0xf2,0x79,0xbf, +0xe7,0xa4,0x8c,0xff,0x00,0x99,0xcd,0x7d,0x79,0xf1,0x37,0x5a,0x5d,0x07,0xc0,0xba, +0xc5,0xd1,0x38,0x73,0x01,0x8a,0x3c,0x1e,0x77,0x3f,0xca,0x3f,0x9e,0x7f,0x0a,0xf8, +0xf6,0xbf,0x3a,0xe2,0x9a,0xa9,0xce,0x95,0x25,0xd1,0x36,0x78,0x59,0x8c,0xb5,0x8c, +0x42,0x8a,0x28,0xaf,0x84,0x3c,0x70,0xaf,0xa1,0xff,0x00,0x66,0x98,0x36,0xf8,0x6b, +0x56,0x97,0x04,0x6f,0xbb,0x0b,0x9f,0xa2,0x0f,0xf1,0xaf,0x9e,0x3a,0xd7,0xd5,0x5f, +0x02,0xf4,0xa6,0xd3,0x3e,0x1d,0x58,0x3b,0xae,0xd9,0x2e,0x9d,0xee,0x08,0xf6,0x27, +0x0b,0xff,0x00,0x8e,0x81,0x5f,0x55,0xc3,0x74,0xdc,0xf1,0xdc,0xdd,0x93,0xff,0x00, +0x23,0xd1,0xc0,0x46,0xf5,0xaf,0xd9,0x1e,0x81,0x8e,0x2b,0xc3,0xbf,0x68,0x6f,0x02, +0xcd,0x71,0xe4,0xf8,0x8e,0xce,0x33,0x20,0x89,0x04,0x57,0x61,0x47,0x21,0x73,0xf2, +0xbf,0xe1,0x9c,0x1f,0xc3,0xde,0xbd,0xc4,0x53,0x66,0x85,0x27,0x8d,0xa3,0x91,0x16, +0x44,0x71,0xb5,0x95,0x86,0x41,0x1e,0x86,0xbf,0x46,0xc7,0x60,0xe1,0x8e,0xa1,0x2a, +0x33,0xeb,0xf8,0x33,0xdd,0xad,0x49,0x56,0x83,0x83,0x3e,0x17,0xa2,0xbd,0xc7,0xe2, +0x1f,0xec,0xff,0x00,0x20,0x96,0x5b,0xff,0x00,0x0d,0x60,0xa3,0x65,0x9b,0x4f,0x76, +0xc1,0x53,0xff,0x00,0x4c,0xd8,0xff,0x00,0x23,0xef,0xcf,0x41,0x5e,0x2d,0x7f,0xa7, +0x5d,0x69,0x57,0x2f,0x6f,0x79,0x6f,0x2d,0xac,0xe9,0xf7,0xa3,0x95,0x0a,0xb0,0xfc, +0x0d,0x7e,0x43,0x8c,0xcb,0xf1,0x18,0x19,0xb8,0xd5,0x8e,0x9d,0xfa,0x33,0xe6,0x2a, +0xd0,0x9d,0x17,0x69,0x22,0xbd,0x14,0x51,0x5e,0x69,0x80,0x52,0xab,0x14,0x60,0xca, +0x4a,0xb0,0x39,0x04,0x1c,0x11,0x49,0x45,0x34,0xed,0xaa,0x03,0xab,0xd1,0xbe,0x29, +0xf8,0xa7,0x41,0xda,0xb6,0xba,0xcd,0xc3,0x46,0x08,0xfd,0xdd,0xc1,0xf3,0x94,0x8f, +0x4f,0x9b,0x24,0x0f,0xa6,0x2b,0xd1,0x34,0x0f,0xda,0x56,0x65,0x65,0x4d,0x6b,0x4a, +0x57,0x52,0x79,0x9a,0xc9,0x88,0x20,0x7f,0xb8,0xc7,0x9f,0xfb,0xe8,0x57,0x88,0x51, +0x5e,0xae,0x1f,0x35,0xc6,0x61,0xbf,0x87,0x51,0xdb,0xb3,0xd5,0x7e,0x27,0x4c,0x31, +0x35,0x69,0xfc,0x32,0x3e,0xc3,0xf0,0xc7,0xc4,0x9f,0x0f,0xf8,0xb8,0x2a,0xe9,0xf7, +0xe8,0x6e,0x08,0xcf,0xd9,0xa5,0xf9,0x25,0x1f,0xf0,0x13,0xd7,0xf0,0xcd,0x74,0xf9, +0xaf,0x85,0x91,0xda,0x37,0x57,0x46,0x2a,0xca,0x72,0x18,0x1c,0x10,0x6b,0xd6,0x7e, +0x1c,0xfc,0x75,0xbe,0xd1,0x25,0x8a,0xc7,0x5e,0x77,0xbf,0xd3,0xce,0x14,0x5c,0x9e, +0x66,0x8b,0xeb,0xfd,0xe1,0xf5,0xe7,0xeb,0xd2,0xbe,0xcb,0x01,0xc4,0xb0,0xaa,0xd5, +0x3c,0x52,0xe5,0x7d,0xd6,0xdf,0x3e,0xc7,0xab,0x47,0x1e,0xa4,0xf9,0x6a,0x2b,0x1f, +0x48,0xd1,0x50,0x59,0x5e,0xc1,0xa8,0x5a,0xc5,0x73,0x6d,0x2a,0xcf,0x6f,0x2a,0x87, +0x8e,0x44,0x39,0x56,0x53,0xd0,0x83,0x53,0xd7,0xdb,0xa6,0x9a,0xba,0x3d,0x7d,0xc2, +0x8a,0x28,0xa6,0x01,0x5e,0x5f,0xf1,0xfa,0xf4,0xda,0xf8,0x48,0xa8,0xfe,0x2c,0xd7, +0xa8,0x57,0x8a,0xfe,0xd2,0xd7,0x5e,0x57,0x87,0xe3,0x4c,0xff,0x00,0x09,0x38,0xaf, +0x2f,0x33,0x97,0x2e,0x12,0xa3,0xf2,0x38,0xb1,0xb2,0xe5,0xc3,0xcd,0xf9,0x1f,0x18, +0x6b,0x32,0x65,0x65,0x6e,0xe4,0x93,0x55,0xff,0x00,0x62,0x7b,0x51,0xaa,0x7e,0xd9, +0x36,0xcf,0x8c,0x8b,0x2d,0x16,0xfa,0xe7,0xe8,0x49,0x8a,0x3c,0xff,0x00,0xe4,0x43, +0xf9,0xd1,0xad,0xbe,0xdb,0x69,0x0f,0xb1,0xad,0x6f,0xf8,0x27,0x95,0x9f,0xdb,0x3f, +0x6a,0x3f,0x15,0x5e,0xe3,0x22,0xd7,0xc3,0x72,0xc5,0xbb,0xd0,0xc9,0x73,0x01,0xff, +0x00,0xda,0x66,0xbe,0x63,0x21,0x8f,0xbd,0x73,0xf2,0xcc,0x8d,0x73,0xe7,0x09,0xf6, +0x4c,0xfd,0x29,0xdb,0x45,0x1c,0xd1,0x5f,0x79,0x73,0xf5,0xeb,0x21,0xd4,0x51,0x49, +0x48,0xa3,0xcd,0x3f,0x68,0x5f,0x18,0x9f,0x07,0xfc,0x31,0xd4,0xa4,0x85,0xf6,0x5d, +0xdf,0x62,0xc6,0x03,0xe8,0x5f,0x3b,0x8f,0xe0,0x81,0x8f,0xd4,0x0a,0xf8,0xeb,0xc0, +0x3e,0x1d,0x93,0xc5,0x3e,0x2c,0xd3,0x74,0xd8,0xd7,0x3e,0x6c,0xca,0x1b,0xd8,0x67, +0x9a,0xf5,0x7f,0xda,0xdb,0xc6,0x1f,0xda,0xbe,0x30,0xb2,0xd0,0x61,0x7c,0xc1,0xa6, +0xc3,0xe6,0x4a,0x01,0xe0,0xca,0xfe,0xbe,0xe1,0x40,0xff,0x00,0xbe,0xab,0x43,0xf6, +0x4b,0xf0,0x7f,0xda,0xb5,0x7b,0xdd,0x76,0x64,0xca,0x5b,0x2f,0x97,0x11,0x3f,0xde, +0x3d,0x6b,0xe0,0xb1,0xcd,0xe6,0x19,0x8c,0x68,0x2d,0x96,0x9f,0xe6,0x7c,0x06,0x2d, +0xbc,0xc7,0x35,0x54,0x57,0xc3,0x1d,0x3e,0xed,0x59,0xf5,0x0e,0x9f,0x65,0x1e,0x9d, +0x63,0x6f,0x6d,0x12,0x85,0x8e,0x14,0x08,0xa0,0x7a,0x01,0x8a,0xb3,0x48,0x3a,0x52, +0xd7,0xde,0x24,0x92,0xb2,0x3e,0xf9,0x2b,0x2b,0x20,0xa2,0x8a,0x29,0x8c,0x2b,0xf2, +0xdf,0xf6,0xd7,0xff,0x00,0x82,0x9b,0x78,0xf3,0xe1,0x1f,0xed,0x0d,0xa9,0xf8,0x43, +0xe1,0xcc,0x9a,0x4b,0xe8,0xfa,0x0c,0x49,0x69,0x7d,0xfd,0xa1,0x69,0xf6,0x81,0x3d, +0xe6,0x37,0x49,0x82,0x19,0x59,0x42,0x6e,0x09,0x80,0x7a,0xab,0x57,0xea,0x2c,0xb2, +0xa4,0x31,0xb3,0xc8,0xea,0x88,0xa0,0x96,0x66,0x38,0x00,0x7a,0x93,0x5f,0x84,0x3f, +0xf0,0x51,0x9f,0xd9,0xb7,0xc4,0x9f,0x0a,0xbe,0x3b,0xf8,0xa7,0xc5,0xe2,0xde,0x4d, +0x4b,0xc1,0xbe,0x27,0xd4,0x65,0xd4,0xad,0x75,0x8b,0x71,0xbe,0x28,0xe5,0x99,0x8b, +0xc9,0x04,0x84,0x67,0x63,0x2b,0xb3,0x63,0x38,0xdc,0xb8,0x23,0xb8,0x0d,0x09,0x9f, +0x6d,0x7e,0xc1,0xff,0x00,0xb5,0xcf,0xc4,0xef,0xdb,0x5b,0xc4,0xde,0x24,0xd0,0xbc, +0x73,0xe1,0x9f,0x07,0xcf,0xe0,0x9d,0x2e,0xc5,0x5f,0x51,0x78,0x74,0xf9,0x77,0x4d, +0x2c,0x84,0x88,0x62,0xdb,0x24,0xce,0x9c,0xec,0x91,0x89,0xdb,0xc0,0x4c,0x63,0x90, +0x47,0xb1,0xf8,0xbf,0xfe,0x09,0x9f,0xfb,0x3c,0xf8,0xc2,0xe9,0xae,0x64,0xf0,0x2a, +0xe9,0x13,0x39,0x25,0x8e,0x91,0x79,0x35,0xb2,0x1c,0xff,0x00,0xb0,0x1b,0x68,0xfc, +0x00,0xaf,0x84,0xbf,0xe0,0x93,0xbf,0xb5,0x1f,0x82,0x3e,0x09,0xea,0xfe,0x2e,0xf0, +0x97,0x8d,0xb5,0x2b,0x7f,0x0f,0x45,0xe2,0x09,0x2d,0xee,0x2c,0xb5,0x6b,0xaf,0x92, +0x01,0x24,0x61,0xd5,0xa2,0x96,0x4e,0x88,0x08,0x60,0x54,0x9e,0x33,0xbf,0x24,0x64, +0x67,0xf5,0xef,0x4a,0xf1,0x66,0x89,0xad,0xdb,0x47,0x71,0xa7,0xeb,0x36,0x17,0xf0, +0x48,0x01,0x49,0x6d,0xae,0x92,0x45,0x61,0xec,0x54,0x90,0x68,0x04,0x7c,0xe9,0xe1, +0x0f,0xf8,0x26,0x9f,0xec,0xf1,0xe0,0xeb,0x85,0xb8,0x8f,0xc0,0x51,0xea,0xf3,0x29, +0x05,0x5b,0x58,0xbc,0x9a,0xe5,0x47,0xfc,0x01,0x9f,0x69,0xfc,0x41,0xaf,0xa4,0x34, +0x2f,0x0f,0x69,0x7e,0x18,0xd2,0xe0,0xd3,0x74,0x7d,0x3a,0xd7,0x4a,0xd3,0xe0,0x1b, +0x62,0xb4,0xb2,0x85,0x61,0x89,0x07,0xa0,0x55,0x00,0x0a,0xd0,0x0c,0x18,0x02,0x08, +0x20,0xf7,0x14,0x64,0x1a,0x43,0x16,0xbc,0xdb,0xe3,0xcf,0x88,0xff,0x00,0xb1,0x3c, +0x0d,0x35,0xb4,0x6d,0x89,0xf5,0x17,0x16,0xeb,0x83,0xc8,0x5e,0xae,0x7e,0x98,0x18, +0xff,0x00,0x81,0x0a,0xf4,0x83,0xc0,0xaf,0x99,0x7f,0x68,0x4f,0x10,0x9d,0x5f,0xc6, +0x69,0xa7,0xa3,0x66,0x1d,0x3a,0x30,0x84,0x7f,0xd3,0x46,0xc3,0x37,0xe9,0xb4,0x7e, +0x15,0xe0,0xe7,0x78,0x9f,0xaa,0xe0,0xa6,0xd6,0xf2,0xd1,0x7c,0xff,0x00,0xe0,0x1c, +0x58,0xba,0x9e,0xce,0x93,0xf3,0x3c,0xbe,0x8a,0x28,0xaf,0xc7,0x4f,0x97,0x0a,0xf7, +0x2f,0xd9,0xaf,0xc3,0xd9,0x93,0x55,0xd6,0xa4,0x5c,0xe3,0x16,0xb1,0x1f,0xfc,0x79, +0xff,0x00,0xf6,0x5a,0xf0,0xda,0xfa,0xff,0x00,0xe1,0x77,0x87,0x8f,0x86,0x7c,0x0f, +0xa5,0x5a,0x32,0x14,0x99,0xa2,0x13,0x4c,0x0f,0x50,0xef,0xf3,0x10,0x7e,0x99,0xc7, +0xe1,0x5f,0x55,0xc3,0x98,0x6f,0x6d,0x8c,0xf6,0x8f,0x68,0x2b,0xfc,0xf6,0x47,0xa3, +0x80,0xa7,0xcf,0x57,0x9b,0xb1,0xd6,0x51,0x49,0x4b,0x5f,0xab,0x1f,0x48,0x78,0x4f, +0xed,0x35,0xa7,0x28,0x3a,0x1d,0xfa,0xaf,0xcc,0x7c,0xd8,0x5d,0xbd,0x7e,0xe9,0x5f, +0xfd,0x9b,0xf3,0xaf,0x0a,0xaf,0xa3,0xff,0x00,0x69,0x38,0x03,0xf8,0x3a,0xc2,0x5c, +0x72,0x97,0xca,0x33,0xec,0x63,0x7f,0xf0,0x15,0xf3,0x85,0x7e,0x47,0xc4,0x30,0x50, +0xcc,0x26,0xd7,0x54,0x9f,0xe0,0x7c,0xce,0x39,0x5a,0xbb,0x0a,0x28,0xa2,0xbe,0x6c, +0xe0,0x3e,0x92,0xfd,0x9b,0xef,0x84,0xfe,0x0c,0xbc,0xb6,0xce,0x5a,0x0b,0xc6,0xe3, +0xd1,0x59,0x54,0x8f,0xd7,0x35,0xeb,0x35,0xe1,0x1f,0xb3,0x1d,0xd0,0x0d,0xe2,0x0b, +0x62,0xdc,0x91,0x0c,0x8a,0xbf,0xf7,0xd8,0x27,0xf9,0x57,0xbb,0x66,0xbf,0x64,0xc9, +0x6a,0x7b,0x4c,0x05,0x27,0xd9,0x5b,0xee,0x76,0x3e,0xa7,0x09,0x2e,0x6a,0x11,0x16, +0x8a,0x28,0xaf,0x70,0xec,0x0a,0x28,0xa4,0x3d,0x28,0x03,0xc8,0x3f,0x69,0x0d,0x6f, +0xec,0x9e,0x19,0xb1,0xd3,0x11,0x80,0x7b,0xd9,0xf7,0xb0,0xf5,0x44,0xe7,0xff,0x00, +0x42,0x2b,0xf9,0x57,0xce,0x95,0xe9,0x7f,0xb4,0x06,0xb8,0x75,0x4f,0x1e,0x3d,0xa0, +0x20,0xc5,0x61,0x0a,0xc2,0x30,0x73,0xf3,0x1f,0x99,0xbf,0xf4,0x20,0x3f,0x0a,0xf3, +0x4a,0xfc,0x77,0x3b,0xaf,0xf5,0x8c,0x74,0xda,0xd9,0x69,0xf7,0x7f,0xc1,0x3e,0x5b, +0x19,0x3e,0x7a,0xcf,0xcb,0x40,0xa2,0x8a,0x2b,0xc1,0x38,0xcf,0x55,0xfd,0x9d,0x74, +0x53,0x7f,0xe3,0x2b,0x8b,0xf6,0x40,0x62,0xb1,0xb7,0x24,0x37,0xa3,0xb9,0xda,0x3f, +0x40,0xf5,0xf4,0xb5,0x79,0x2f,0xec,0xe7,0xa2,0x7d,0x87,0xc1,0xf7,0x3a,0x83,0xc6, +0x04,0x97,0xd7,0x07,0x6b,0xf7,0x31,0xa7,0xca,0x07,0xfd,0xf5,0xbf,0xf3,0xaf,0x5a, +0xaf,0xd8,0x32,0x2a,0x1e,0xc3,0x01,0x0b,0xef,0x2d,0x7e,0xff,0x00,0xf8,0x16,0x3e, +0xa3,0x07,0x0e,0x4a,0x2b,0xcf,0x50,0xa2,0x8a,0x2b,0xe8,0x0e,0xd0,0xaf,0x00,0xfd, +0xa6,0xc6,0x35,0x3d,0x04,0xf6,0x30,0xcb,0xfc,0xd6,0xbd,0xfe,0xbc,0x67,0xf6,0x97, +0xd2,0xbc,0xed,0x0f,0x49,0xd4,0x42,0x92,0x6d,0xe7,0x68,0x4e,0x07,0x00,0x3a,0xe7, +0x27,0xf1,0x41,0xf9,0xd7,0x81,0x9e,0xc1,0xcf,0x2f,0xa8,0x97,0x93,0xfc,0x4e,0x2c, +0x62,0xbd,0x09,0x1f,0x3d,0x51,0x45,0x15,0xf8,0xf1,0xf2,0xe1,0x5d,0xa7,0xc1,0xcb, +0xc4,0xb1,0xf8,0x93,0xa2,0xbb,0x9c,0x2b,0xc8,0xf1,0x7e,0x2c,0x8c,0xa3,0xf5,0x22, +0xb8,0xba,0xb1,0xa7,0xdf,0x4d,0xa5,0xdf,0xdb,0x5e,0x5b,0xb6,0xd9,0xed,0xe4,0x59, +0x50,0xfa,0x32,0x9c,0x8f,0xe5,0x5d,0x38,0x6a,0xbe,0xc2,0xbc,0x2a,0xbf,0xb2,0xd3, +0xfb,0x99,0x74,0xe5,0xc9,0x35,0x2e,0xcc,0xfb,0x88,0x52,0xd6,0x4f,0x86,0x3c,0x43, +0x6d,0xe2,0x9d,0x0e,0xcf,0x53,0xb4,0x6c,0xc5,0x70,0x81,0xb6,0xe7,0x25,0x1b,0xba, +0x9f,0x70,0x72,0x3f,0x0a,0xd6,0xaf,0xdd,0x21,0x38,0xce,0x2a,0x71,0x77,0x4c,0xfb, +0x14,0xd3,0x57,0x41,0x45,0x14,0x55,0x8c,0x28,0xa4,0xc8,0xae,0x4f,0xe2,0x2f,0x8f, +0xed,0x3c,0x07,0xa2,0xb5,0xcc,0x84,0x4b,0x7b,0x28,0x2b,0x6d,0x6d,0x9e,0x5d,0xbd, +0x4f,0xfb,0x23,0xb9,0xff,0x00,0x1a,0xc6,0xb5,0x68,0x50,0xa6,0xea,0xd4,0x76,0x48, +0x89,0x49,0x41,0x39,0x4b,0x63,0xcb,0x7f,0x68,0xdf,0x17,0x2d,0xc5,0xcd,0x9f,0x87, +0xad,0xdf,0x3e,0x41,0x17,0x37,0x38,0xec,0xc4,0x10,0x8b,0xf9,0x12,0x7f,0x11,0x5e, +0x27,0x56,0x75,0x2d,0x46,0xe3,0x56,0xbf,0x9e,0xf6,0xee,0x53,0x35,0xcc,0xee,0x64, +0x91,0xcf,0x72,0x6a,0xb5,0x7e,0x2d,0x98,0x62,0xde,0x3b,0x13,0x2a,0xcf,0xae,0xde, +0x9d,0x0f,0x94,0xaf,0x55,0xd6,0x9b,0x98,0x51,0x45,0x15,0xe7,0x18,0x16,0x74,0xcd, +0x3e,0x6d,0x5b,0x51,0xb5,0xb2,0xb6,0x5d,0xf7,0x17,0x32,0x2c,0x51,0xa9,0xe8,0x59, +0x8e,0x07,0xf3,0xaf,0xb5,0xb4,0x7d,0x3a,0x2d,0x1f,0x4a,0xb4,0xb1,0x80,0x62,0x1b, +0x68,0x96,0x14,0x1e,0xca,0x00,0x1f,0xca,0xbc,0x03,0xf6,0x78,0xf0,0x69,0xd4,0x75, +0xa9,0xb5,0xfb,0x84,0xff,0x00,0x47,0xb2,0x06,0x38,0x32,0x3e,0xf4,0xa4,0x72,0x7f, +0x05,0x3f,0x99,0xf6,0xaf,0xa2,0x87,0x4a,0xfd,0x3b,0x86,0xb0,0x8e,0x8d,0x09,0x62, +0x24,0xb5,0x9e,0xde,0x88,0xfa,0x0c,0xbe,0x97,0x2c,0x1c,0xdf,0x51,0x68,0xa4,0xcd, +0x2d,0x7d,0x91,0xea,0x88,0x46,0x6b,0x33,0x5b,0xf0,0xd6,0x97,0xe2,0x2b,0x63,0x06, +0xa5,0x61,0x05,0xec,0x7d,0x84,0xa8,0x09,0x1f,0x43,0xd4,0x7e,0x15,0xa9,0x45,0x4c, +0xa1,0x19,0xae,0x59,0x2b,0xa1,0x34,0x9a,0xb3,0x3c,0x7b,0x5f,0xfd,0x9b,0xf4,0x8b, +0xd6,0x32,0x69,0x57,0xd3,0xe9,0xac,0x4e,0x7c,0xb9,0x07,0x9d,0x18,0x1e,0x83,0x90, +0x47,0xe6,0x6b,0xce,0x35,0xdf,0x81,0x3e,0x2a,0xd1,0x81,0x78,0xad,0xa2,0xd4,0xe2, +0x19,0xf9,0xad,0x1f,0x2d,0x8e,0xdf,0x29,0xc1,0xfc,0xb3,0x5f,0x54,0x52,0x11,0x5f, +0x3d,0x88,0xc8,0x30,0x35,0xf5,0x51,0xe5,0x7e,0x5f,0xe5,0xb1,0xc3,0x3c,0x15,0x19, +0xf4,0xb7,0xa1,0xf0,0xe5,0xed,0x85,0xd6,0x9b,0x39,0x86,0xee,0xda,0x5b,0x59,0x87, +0x58,0xe6,0x42,0x8d,0xf9,0x1a,0x82,0xbe,0xdb,0xd5,0xf4,0x1d,0x3f,0x5d,0xb6,0x36, +0xfa,0x85,0x9c,0x37,0xb0,0x9f,0xe1,0x99,0x03,0x63,0xdc,0x7a,0x57,0x8b,0xfc,0x45, +0xf8,0x03,0x1d,0xbd,0xb4,0xda,0x8f,0x86,0xb7,0xe5,0x32,0xef,0x60,0xe7,0x76,0x47, +0x7d,0x84,0xf3,0x9f,0x63,0x9c,0xfa,0xf6,0xaf,0x91,0xc6,0xf0,0xe5,0x7a,0x11,0x75, +0x28,0x4b,0x9d,0x2e,0x9b,0x3f,0xf8,0x27,0x9b,0x57,0x01,0x38,0x2e,0x68,0x3b,0xa3, +0xc3,0x28,0xa0,0x8c,0x1c,0x74,0xa2,0xbe,0x40,0xf2,0xc2,0x8a,0x28,0xa0,0x0f,0x6f, +0xfd,0x9d,0xbc,0x6b,0x22,0xdc,0xcf,0xe1,0xcb,0x99,0x0b,0x46,0xca,0x67,0xb5,0xdc, +0x7e,0xe9,0x1f,0x79,0x07,0xb1,0xeb,0xf8,0x1a,0xf7,0xba,0xf8,0xf7,0xe1,0x7d,0xe3, +0xd8,0xfc,0x41,0xd0,0x64,0x8c,0xe0,0xb5,0xd2,0xc6,0x7e,0x8d,0xf2,0x9f,0xd1,0x8d, +0x7d,0x84,0x2b,0xf5,0x6e,0x1c,0xc4,0x4a,0xb6,0x13,0x92,0x6f,0xe1,0x76,0xf9,0x1f, +0x47,0x80,0xa8,0xe7,0x4a,0xcf,0xa0,0xb4,0x51,0x45,0x7d,0x51,0xe9,0x08,0x78,0xaf, +0x9f,0xbf,0x6a,0x3b,0xbd,0x96,0x51,0xc7,0x9e,0x89,0xd2,0xbe,0x81,0x35,0xf3,0x27, +0xed,0x4f,0x77,0xfe,0x90,0x23,0x07,0xf8,0x45,0x78,0x59,0xd4,0xb9,0x70,0x53,0x3c, +0xac,0xce,0x5c,0xb8,0x59,0xb3,0xe5,0x3f,0x11,0x3e,0xdb,0x19,0x4f,0xfb,0x26,0xbb, +0xef,0xf8,0x26,0x55,0x81,0xb9,0xf8,0x97,0xf1,0x53,0x53,0xed,0x0d,0xa5,0x8d,0xb0, +0x3f,0xef,0xbc,0xcd,0xff,0x00,0xb2,0x0a,0xf3,0x8f,0x16,0xc9,0xe5,0xe9,0xb3,0x9f, +0x45,0xaf,0x63,0xff,0x00,0x82,0x5b,0xdb,0x16,0xb7,0xf8,0xab,0x7d,0xb7,0x89,0x35, +0x1b,0x38,0x43,0x7a,0xec,0x8a,0x42,0x7f,0xf4,0x3a,0xf2,0xb2,0x28,0xe8,0xd9,0xf9, +0xdf,0x0d,0x47,0x9b,0x33,0x9c,0xbb,0x44,0xfb,0xb3,0x9a,0x29,0xd4,0x57,0xd9,0x1f, +0xac,0x85,0x52,0xd5,0xb5,0x28,0x74,0x9d,0x36,0xee,0xfa,0xe0,0xed,0x82,0xda,0x26, +0x99,0xcf,0xfb,0x2a,0x32,0x6a,0xed,0x78,0xaf,0xed,0x53,0xe3,0x0f,0xec,0x0f,0x87, +0xab,0xa5,0xc3,0x26,0xdb,0xad,0x5e,0x61,0x09,0x00,0xe0,0xf9,0x4b,0xf3,0x48,0x7e, +0x9f,0x75,0x7f,0xe0,0x55,0xcd,0x89,0xac,0xb0,0xf4,0x65,0x55,0xf4,0x47,0x26,0x2e, +0xba,0xc2,0xd0,0x9d,0x67,0xd1,0x1f,0x26,0x78,0x83,0x5a,0xb8,0xf1,0x6f,0x89,0x2f, +0xf5,0x4b,0x8c,0xb5,0xc5,0xf5,0xc3,0x4a,0x47,0xa6,0x4f,0x03,0xf0,0x18,0x1f,0x85, +0x7d,0xbd,0xf0,0x4b,0xc2,0x63,0xc2,0x3f,0x0f,0xf4,0xeb,0x76,0x4d,0xb3,0xcc,0x82, +0x69,0x78,0xc7,0x26,0xbe,0x43,0xf8,0x3b,0xe1,0x46,0xf1,0x77,0x8f,0x74,0xcb,0x3d, +0xbb,0xa1,0x59,0x04,0x92,0x9f,0x45,0x1c,0xd7,0xde,0xf0,0xc4,0xb0,0xc2,0x91,0xa0, +0xda,0xaa,0x00,0x03,0xda,0xbe,0x4f,0x21,0xa2,0xea,0x54,0xa9,0x89,0x9f,0xa7,0xdf, +0xab,0x3e,0x57,0x87,0xa8,0x39,0x73,0xe2,0xa7,0xbb,0xfe,0x99,0x25,0x14,0x56,0x47, +0x8b,0xfc,0x53,0xa7,0x78,0x1f,0xc2,0x9a,0xcf,0x88,0xb5,0x79,0xbe,0xcf,0xa5,0xe9, +0x36,0x73,0x5f,0x5d,0x4b,0x8c,0xec,0x8a,0x34,0x2e,0xe7,0x1d,0xf8,0x53,0x5f,0x6a, +0x7d,0xa9,0xaf,0x45,0x7e,0x2d,0xcd,0xff,0x00,0x05,0x91,0xf8,0xd2,0x35,0x2b,0x86, +0xb6,0xd1,0x7c,0x20,0xd6,0x2d,0x2b,0x18,0x22,0x9e,0xc2,0x7f,0x31,0x63,0x2c,0x76, +0xab,0x30,0x9c,0x02,0x40,0xc0,0xce,0x2b,0xf5,0x5f,0xf6,0x6a,0xf1,0xbf,0x8a,0xfe, +0x25,0x7c,0x0e,0xf0,0x8f,0x8a,0xfc,0x6b,0x65,0x63,0xa6,0xf8,0x83,0x5a,0xb3,0x5b, +0xf9,0x2d,0x34,0xe4,0x74,0x8a,0x38,0xa4,0x25,0xa1,0xe1,0xd9,0x8e,0x4c,0x65,0x09, +0xc9,0xea,0x48,0xa0,0x49,0xdc,0xf9,0xef,0xfe,0x0a,0xb9,0xf1,0xa3,0xfe,0x15,0x97, +0xec,0xc9,0x73,0xe1,0xfb,0x39,0x8c,0x7a,0xb7,0x8c,0x6e,0x06,0x96,0x81,0x7a,0x8b, +0x60,0x37,0xdc,0x1f,0xa1,0x50,0x13,0xfe,0xda,0x57,0xe2,0x00,0xd4,0x6e,0xc5,0xab, +0xdb,0x0b,0xa9,0x85,0xb3,0xfd,0xe8,0x44,0x87,0x63,0x73,0x9e,0x47,0x4e,0xa2,0xbf, +0xa2,0x9f,0x8f,0x5f,0xb2,0x2f,0xc3,0x3f,0xda,0x5e,0xfb,0x4b,0xbc,0xf1,0xf6,0x95, +0x77,0xaa,0xcd,0xa6,0x44,0xf0,0xda,0x79,0x3a,0x8c,0xd6,0xeb,0x12,0xb1,0xcb,0x7c, +0xa8,0xc0,0x12,0x48,0x19,0x24,0x67,0x81,0xe9,0x5e,0x33,0x7d,0xff,0x00,0x04,0x93, +0xfd,0x9e,0xae,0xff,0x00,0xd5,0x69,0x5a,0xed,0x97,0xfd,0x70,0xd6,0x24,0x3f,0xfa, +0x1e,0xea,0x62,0x6a,0xe7,0xe1,0xa7,0x34,0xf8,0x66,0x92,0xde,0x41,0x24,0x4e,0xd1, +0x48,0x3a,0x32,0x1c,0x11,0xf8,0xd7,0xed,0x36,0xa9,0xff,0x00,0x04,0x70,0xf8,0x23, +0x78,0xa7,0xec,0x9a,0xb7,0x8b,0xb4,0xf2,0x7b,0xa5,0xfc,0x2f,0x8f,0xfb,0xea,0x13, +0x5c,0x9d,0xff,0x00,0xfc,0x11,0x47,0xe1,0xf4,0xad,0xfe,0x85,0xf1,0x0f,0xc4,0xd6, +0xe3,0xd2,0xe2,0xde,0xde,0x5f,0xe4,0xab,0x4e,0xe2,0xb3,0x3f,0x28,0xad,0x3e,0x21, +0xf8,0xaa,0xc3,0x02,0xd7,0xc4,0xda,0xc5,0xb6,0x3a,0x08,0x6f,0xe5,0x4c,0x7e,0x4d, +0x5f,0xb1,0x9f,0xf0,0x49,0x2f,0x0c,0x78,0x9e,0x4f,0x82,0x3a,0xbf,0x8e,0x7c,0x53, +0xae,0xea,0xda,0xcc,0xbe,0x20,0xbe,0xf2,0x74,0xf4,0xd4,0xef,0x25,0x9c,0x43,0x6d, +0x06,0x54,0xb2,0x07,0x63,0x8d,0xf2,0x17,0xe9,0xd7,0x60,0xaf,0x36,0xbe,0xff,0x00, +0x82,0x23,0xe8,0x0e,0xa7,0xec,0x9f,0x15,0xb5,0x28,0x4f,0xfd,0x36,0xd1,0xa3,0x93, +0xf9,0x4c,0xb5,0xfa,0x0f,0xf0,0x97,0xe1,0xbe,0x9f,0xf0,0x87,0xe1,0x9f,0x86,0x7c, +0x19,0xa5,0xb6,0xfb,0x1d,0x12,0xc2,0x2b,0x28,0xe5,0x2b,0xb4,0xc9,0xb5,0x70,0xce, +0x47,0x38,0x2c,0xd9,0x63,0xcf,0x52,0x69,0x31,0xa4,0xce,0x8f,0x55,0xd4,0x62,0xd2, +0x74,0xdb,0xab,0xd9,0xdb,0x6c,0x36,0xf1,0x34,0xae,0x7d,0x94,0x64,0xd7,0xc5,0x5a, +0xb6,0xa5,0x2e,0xb1,0xaa,0x5d,0xdf,0x4e,0x73,0x35,0xcc,0xad,0x2b,0x7d,0x49,0xcd, +0x7d,0x6b,0xf1,0x2b,0xc3,0xba,0x97,0x8a,0xfc,0x29,0x73,0xa5,0x69,0x93,0x41,0x04, +0xd7,0x0c,0xa1,0xde,0x76,0x65,0x1b,0x01,0xc9,0x03,0x00,0xf2,0x70,0x07,0xd0,0x9a, +0xf1,0x39,0x7f,0x67,0x2f,0x13,0xa2,0x92,0xb7,0x3a,0x6c,0x87,0xd1,0x66,0x70,0x7f, +0x54,0xaf,0x85,0xe2,0x1a,0x18,0xbc,0x5c,0xe1,0x0a,0x34,0xdb,0x8a,0xd7,0x4e,0xe7, +0x93,0x8e,0x85,0x5a,0x8d,0x46,0x11,0xba,0x47,0x95,0xd1,0x5e,0x87,0x3f,0xc0,0x5f, +0x18,0xc2,0x7e,0x5b,0x18,0x26,0xf7,0x4b,0x84,0xfe,0xa4,0x55,0x39,0x3e,0x0a,0x78, +0xd2,0x3c,0x9f,0xec,0x46,0x61,0xfe,0xcd,0xc4,0x47,0xff,0x00,0x66,0xaf,0x89,0x79, +0x6e,0x36,0x3b,0xd2,0x97,0xdc,0xcf,0x25,0xd0,0xaa,0xbe,0xcb,0x32,0xfe,0x1d,0xf8, +0x7b,0xfe,0x12,0x8f,0x19,0xe9,0x76,0x0c,0x81,0xe1,0x69,0x44,0x92,0x83,0xd3,0xcb, +0x5f,0x99,0x87,0xe2,0x06,0x3f,0x1a,0xfb,0x1c,0x70,0x05,0x78,0xcf,0xc0,0xaf,0x87, +0x5a,0x9f,0x86,0x75,0x2d,0x47,0x51,0xd6,0x2c,0x9a,0xd2,0x7d,0x82,0x08,0x55,0xc8, +0x24,0x82,0x72,0xc7,0x82,0x7d,0x14,0x7e,0x75,0xec,0xd5,0xfa,0x37,0x0f,0x61,0x25, +0x86,0xc2,0xb9,0x54,0x56,0x94,0x9f,0xe5,0xa2,0x3d,0xdc,0x0d,0x27,0x4e,0x9d,0xda, +0xd5,0x8b,0x45,0x14,0x57,0xd4,0x9e,0x89,0xe6,0x1f,0xb4,0x3c,0x7e,0x67,0xc3,0xfc, +0xff,0x00,0x72,0xee,0x36,0xfd,0x18,0x7f,0x5a,0xf9,0x8e,0xbe,0xa7,0xf8,0xf7,0x1e, +0xff,0x00,0x86,0xb7,0xed,0xfd,0xc9,0x61,0x6f,0xfc,0x88,0x07,0xf5,0xaf,0x96,0x33, +0x5f,0x96,0x71,0x32,0xb6,0x35,0x3f,0xee,0xaf,0xcd,0x9f,0x3b,0x98,0x2f,0xde,0xdf, +0xc8,0x28,0xa2,0x8a,0xf9,0x23,0xcc,0x3d,0x5f,0xf6,0x6f,0xb9,0x31,0xf8,0xd6,0xf2, +0x1c,0xe1,0x64,0xb1,0x63,0x8f,0x52,0x1d,0x3f,0xc4,0xd7,0xd2,0x63,0xad,0x7c,0xa1, +0xf0,0x42,0xf1,0xad,0x3e,0x25,0x69,0x4a,0xa7,0x0b,0x30,0x96,0x26,0xfa,0x79,0x6c, +0x7f,0x98,0x15,0xf5,0x78,0xaf,0xd5,0x38,0x6a,0x7c,0xd8,0x2e,0x5e,0xcd,0xff,0x00, +0x99,0xf4,0x78,0x07,0x7a,0x36,0xec,0xc5,0xa2,0x8a,0x2b,0xeb,0x0f,0x48,0x2a,0x3b, +0x89,0xd2,0xda,0x09,0x25,0x91,0x82,0x47,0x1a,0x96,0x66,0x27,0x80,0x00,0xe4,0xd3, +0xcd,0x70,0xff,0x00,0x19,0xb5,0xcf,0xec,0x4f,0x87,0xba,0xa1,0x5c,0x79,0xb7,0x4a, +0x2d,0x14,0x1e,0xfb,0xf8,0x6f,0xfc,0x77,0x71,0xfc,0x2b,0x9f,0x11,0x59,0x50,0xa3, +0x3a,0xaf,0xa2,0x6c,0x89,0xcb,0x92,0x2e,0x5d,0x8f,0x96,0xb5,0xbd,0x56,0x4d,0x73, +0x59,0xbe,0xd4,0x65,0x1b,0x64,0xba,0x9d,0xe6,0x2b,0xfd,0xdd,0xc4,0x9c,0x7e,0x15, +0x4a,0x8a,0x2b,0xf0,0x99,0xc9,0xce,0x4e,0x4f,0x76,0x7c,0x73,0x77,0x77,0x61,0x40, +0x04,0x90,0x07,0x24,0xd1,0x5d,0x17,0xc3,0xcd,0x1b,0xfb,0x7f,0xc6,0xda,0x3d,0x91, +0x5d,0xc8,0xf7,0x0a,0xee,0x3d,0x51,0x7e,0x66,0xfd,0x14,0xd5,0xd1,0xa6,0xeb,0x54, +0x8d,0x35,0xbb,0x69,0x0e,0x31,0x72,0x92,0x8a,0xea,0x7d,0x59,0xe0,0x9d,0x10,0x78, +0x77,0xc2,0x7a,0x56,0x9e,0x17,0x6b,0x43,0x6e,0x81,0xc7,0xfb,0x64,0x65,0xbf,0x52, +0x6b,0x76,0x90,0x74,0x18,0xe9,0x4b,0x5f,0xbb,0xd3,0x82,0xa7,0x05,0x05,0xb2,0x56, +0x3e,0xc6,0x2b,0x95,0x24,0x82,0x8a,0x28,0xad,0x0a,0x0a,0xc0,0xf1,0xcf,0x86,0x93, +0xc5,0xde,0x16,0xd4,0x34,0xb6,0x21,0x5a,0x78,0xff,0x00,0x76,0xc7,0xa2,0xc8,0x0e, +0x54,0x9f,0x6c,0x81,0x5b,0xf4,0x86,0xb3,0xa9,0x08,0xd5,0x83,0x84,0xb6,0x7a,0x0a, +0x49,0x49,0x38,0xbe,0xa7,0xc3,0x57,0x56,0xb2,0xd9,0x5c,0xcb,0x6f,0x3c,0x6d,0x14, +0xd1,0x39,0x8d,0xd1,0x86,0x0a,0xb0,0x38,0x20,0xd4,0x55,0xf4,0x07,0xc6,0xef,0x85, +0x32,0xea,0x8c,0xfe,0x20,0xd1,0xe1,0x32,0x5d,0x01,0x9b,0xab,0x64,0x1c,0xc8,0x07, +0xf1,0xa8,0xee,0x40,0xea,0x3b,0x8f,0x7e,0xbf,0x3f,0xd7,0xe2,0xd9,0x86,0x06,0xa6, +0x02,0xb3,0xa7,0x3d,0xba,0x3e,0xeb,0xfa,0xdc,0xf9,0x3a,0xf4,0x65,0x46,0x7c,0xac, +0x28,0xa2,0x8a,0xf3,0x0e,0x73,0xb3,0xf8,0x73,0xf1,0x3a,0xfb,0xe1,0xf5,0xe3,0x04, +0x43,0x77,0xa7,0x4a,0x73,0x35,0xab,0x1c,0x73,0xfd,0xe5,0x3d,0x8f,0xf3,0xfc,0xb1, +0xf4,0x3f,0x86,0xbe,0x2b,0xf8,0x67,0xc4,0xd1,0x21,0x87,0x52,0x8a,0xd6,0x72,0x39, +0xb7,0xbb,0x61,0x13,0x83,0xe9,0xc9,0xc1,0xfc,0x09,0xaf,0x91,0x68,0xaf,0xa1,0xcb, +0xf3,0xbc,0x46,0x02,0x3e,0xcd,0x7b,0xd1,0xec,0xfa,0x7a,0x33,0xba,0x8e,0x2e,0xa5, +0x15,0xcb,0xba,0x3e,0xe7,0x8e,0xe2,0x29,0x90,0x3c,0x72,0x23,0xa1,0xe8,0xca,0xc0, +0x83,0x54,0xf5,0x0d,0x7f,0x4c,0xd2,0x50,0xb5,0xee,0xa1,0x6b,0x68,0xa3,0xbc,0xd3, +0x2a,0xff,0x00,0x33,0x5f,0x13,0x2c,0x8e,0x83,0x0a,0xcc,0xa3,0xd8,0xe2,0x9a,0x79, +0x39,0x27,0x27,0xde,0xbd,0xd7,0xc5,0x52,0xb7,0xbb,0x47,0x5f,0x5f,0xf8,0x07,0x67, +0xf6,0x93,0xe9,0x1f,0xc7,0xfe,0x01,0xf4,0x6f,0x8c,0x7f,0x68,0x5d,0x2b,0x4c,0x89, +0xe1,0xd0,0xe3,0x3a,0xa5,0xd9,0xc8,0x13,0x30,0x29,0x0a,0x7e,0x7c,0xb7,0xe1,0xc1, +0xf5,0xaf,0x03,0xd7,0xbc,0x41,0x7f,0xe2,0x6d,0x4a,0x5b,0xfd,0x46,0xe1,0xae,0x6e, +0x64,0xea,0xcd,0xd0,0x0e,0xc0,0x0e,0xc0,0x7a,0x0a,0xce,0xa2,0xbe,0x5f,0x1d,0x9a, +0x62,0x71,0xef,0xf7,0xaf,0x4e,0xcb,0x63,0xce,0xad,0x88,0xa9,0x5b,0xe2,0xd8,0x28, +0xa2,0x8a,0xf2,0x4e,0x60,0xad,0x8f,0x09,0xf8,0x5e,0xf7,0xc6,0x1a,0xe5,0xbe,0x9b, +0x62,0x84,0xc9,0x21,0xcb,0xc8,0x47,0xcb,0x1a,0x7f,0x13,0x1f,0x61,0xfa,0x9c,0x0e, +0xf4,0x78,0x5f,0xc2,0x9a,0x97,0x8c,0x35,0x44,0xb1,0xd3,0x60,0x32,0xc8,0x7e,0xfb, +0x9c,0x84,0x89,0x7f,0xbc,0xc7,0xb0,0xfd,0x7d,0x33,0x5f,0x54,0x7c,0x3e,0xf8,0x7f, +0x63,0xe0,0x2d,0x24,0x41,0x6e,0x04,0xd7,0x72,0x00,0x6e,0x2e,0x98,0x61,0xa4,0x3f, +0xd0,0x0e,0xc2,0xbe,0x8b,0x29,0xca,0x67,0x8f,0xa8,0xa7,0x35,0x6a,0x6b,0x77,0xdf, +0xc9,0x1d,0xb8,0x6c,0x34,0xab,0xca,0xef,0xe1,0x35,0xbc,0x35,0xe1,0xeb,0x5f,0x0b, +0x68,0xb6,0xba,0x65,0x92,0x95,0x82,0x04,0xda,0x09,0xea,0xc7,0xbb,0x1f,0x72,0x72, +0x7f,0x1a,0xd4,0x14,0x52,0xd7,0xeb,0x70,0x84,0x69,0xc5,0x46,0x2a,0xc9,0x1f,0x4e, +0x92,0x4a,0xc8,0xc7,0xf1,0x4f,0x8a,0x6c,0x7c,0x21,0xa5,0x9d,0x43,0x51,0x76,0x4b, +0x60,0xe9,0x19,0x28,0xbb,0x8e,0x58,0xe3,0xa7,0xb7,0x5e,0x39,0xc0,0xa9,0x74,0x3f, +0x12,0x69,0x9e,0x23,0xb5,0x17,0x1a,0x6d,0xf4,0x37,0x91,0x11,0x92,0x62,0x6c,0x95, +0xfa,0x8e,0xa0,0xfb,0x1a,0xf1,0xdf,0xda,0x5f,0x5d,0xf9,0x74,0x8d,0x1d,0x1b,0xae, +0xeb,0xa9,0x00,0x3f,0xf0,0x15,0xff,0x00,0xd9,0xab,0xc4,0x2c,0xaf,0xee,0x74,0xeb, +0x85,0x9e,0xd2,0xe2,0x5b,0x69,0xd7,0xee,0xc9,0x0b,0x94,0x61,0xf8,0x8a,0xf8,0xec, +0x77,0x10,0x3c,0x16,0x32,0x54,0x79,0x79,0xa2,0xad,0xeb,0x73,0xcb,0xad,0x8d,0xf6, +0x55,0x5c,0x6d,0x74,0x7d,0xc7,0x9a,0x5a,0xf9,0x63,0x44,0xf8,0xf1,0xe2,0xbd,0x1c, +0x2a,0x4d,0x71,0x16,0xa7,0x10,0xfe,0x1b,0xa8,0xf2,0xd8,0xff,0x00,0x79,0x70,0x7f, +0x3c,0xd7,0x6f,0xa6,0x7e,0xd3,0x36,0xcc,0x48,0xd4,0x34,0x39,0xa2,0x03,0xf8,0xad, +0xa6,0x0f,0x93,0xf4,0x60,0xbf,0xce,0xbb,0xe8,0xf1,0x0e,0x06,0xaa,0xf7,0xa4,0xe2, +0xfc,0xd7,0xf9,0x5c,0xda,0x18,0xea,0x32,0xdd,0xd8,0xf6,0xfc,0xd1,0x9a,0xf3,0x1b, +0x0f,0xda,0x1f,0xc2,0xb7,0x6a,0x0c,0xdf,0x6d,0xb1,0x3e,0x93,0x41,0x9f,0xfd,0x00, +0xb5,0x5f,0x5f,0x8e,0xbe,0x0b,0x23,0xfe,0x42,0xce,0x3e,0xb6,0xb2,0xff,0x00,0xf1, +0x35,0xe9,0x47,0x33,0xc1,0x4b,0x6a,0xb1,0xfb,0xcd,0xd6,0x22,0x93,0xda,0x48,0xef, +0xe9,0x1d,0x82,0xa1,0x24,0x80,0x31,0xce,0x6b,0xcd,0xaf,0xff,0x00,0x68,0x1f,0x09, +0x5a,0xc2,0xcd,0x0c,0xd7,0x37,0xcc,0x3f,0x82,0x1b,0x76,0x52,0x7f,0xef,0xbd,0xa3, +0xf5,0xaf,0x35,0xf1,0xe7,0xc7,0xab,0xef,0x12,0x5a,0x4d,0xa7,0xe9,0x36,0xe7,0x4c, +0xb2,0x94,0x15,0x92,0x56,0x6c,0xcc,0xeb,0xe9,0xc7,0x0b,0xef,0x8c,0xfd,0x6b,0x93, +0x13,0x9d,0xe0,0xa8,0x41,0xb5,0x35,0x27,0xd9,0x6a,0x67,0x53,0x17,0x4a,0x0a,0xf7, +0xb9,0xe7,0xbe,0x28,0x96,0x0b,0x8f,0x12,0xea,0xd2,0xda,0xe3,0xec,0xcf,0x77,0x2b, +0x45,0xb7,0xa6,0xd2,0xe4,0x8c,0x7e,0x15,0x97,0x45,0x15,0xf9,0x04,0xe5,0xcf,0x37, +0x2e,0xee,0xe7,0xcb,0xb7,0x77,0x70,0xa2,0x8a,0x2a,0x04,0x75,0xff,0x00,0x08,0xf4, +0xf6,0xd4,0xbe,0x22,0xe8,0x88,0x01,0xc4,0x73,0x79,0xc4,0x8e,0xc1,0x14,0xb7,0xf4, +0xaf,0xae,0xc7,0x4a,0xf0,0x7f,0xd9,0xbf,0xc2,0xac,0x64,0xbe,0xf1,0x04,0xc9,0x85, +0xdb,0xf6,0x6b,0x72,0x47,0x5e,0xee,0x7f,0x40,0x3f,0x3a,0xf7,0x81,0xd2,0xbf,0x57, +0xe1,0xcc,0x3b,0xa3,0x82,0xe7,0x97,0xda,0x77,0xf9,0x74,0x3e,0x93,0x03,0x07,0x1a, +0x57,0x7d,0x45,0xa2,0x8a,0x2b,0xea,0x4f,0x44,0x69,0xaf,0x92,0xff,0x00,0x69,0xfb, +0xbf,0x33,0x5a,0x74,0xce,0x70,0xd5,0xf5,0xab,0x74,0xaf,0x8c,0x7f,0x68,0xdb,0xbf, +0x3b,0xc4,0xb2,0x8c,0xff,0x00,0x19,0xaf,0x99,0xcf,0xdd,0xb0,0xb6,0xee,0xd1,0xe0, +0x67,0x72,0xe5,0xc2,0x48,0xf9,0xcb,0xc7,0x32,0xec,0xd2,0x67,0x3d,0x3e,0x5a,0xfa, +0x47,0xfe,0x09,0x79,0xa6,0x88,0x7e,0x0f,0xf8,0xbb,0x50,0xc7,0xcd,0x77,0xe2,0x39, +0x57,0x38,0xec,0x90,0x42,0x07,0xea,0x4d,0x7c,0xc3,0xf1,0x1e,0x5f,0x2f,0x46,0x9c, +0xe7,0xb1,0xfe,0x55,0xf5,0xff,0x00,0xfc,0x13,0x53,0x4f,0x36,0x9f,0xb3,0x2c,0x17, +0x24,0x63,0xed,0xda,0xcd,0xf5,0xc0,0x3e,0xb8,0x93,0xcb,0xff,0x00,0xda,0x75,0x9e, +0x47,0x1b,0x53,0xb9,0xf1,0xbc,0x27,0x1b,0xe2,0xeb,0xcf,0xc9,0x1f,0x55,0x51,0x45, +0x15,0xf5,0x47,0xea,0x21,0x5f,0x13,0x7e,0xd3,0x3e,0x2f,0x3e,0x27,0xf8,0x9b,0x71, +0x68,0x8e,0x4d,0xa6,0x92,0x9f,0x64,0x41,0xdb,0x7f,0x59,0x0f,0xe7,0x81,0xff,0x00, +0x01,0xaf,0xae,0xbc,0x73,0xe2,0x68,0x7c,0x1d,0xe1,0x2d,0x57,0x59,0x9b,0x1b,0x6c, +0xe0,0x69,0x14,0x1f,0xe2,0x7c,0x61,0x57,0xf1,0x62,0x07,0xe3,0x5f,0x9f,0x28,0x2e, +0x75,0xcd,0x57,0x74,0x8c,0xd3,0x5d,0x5d,0xcc,0x59,0x98,0xf2,0x59,0xd9,0xb2,0x4f, +0xe6,0x6b,0xe4,0xb8,0x83,0x11,0xcb,0x4e,0x34,0x23,0xbb,0xd7,0xfa,0xf9,0x9f,0x1b, +0xc4,0x58,0x87,0xc9,0x0c,0x34,0x77,0x93,0xbb,0xf4,0xff,0x00,0x87,0x3e,0x96,0xfd, +0x92,0x7c,0x1f,0xe4,0xd9,0xdf,0x6b,0xf2,0xa6,0x0c,0x87,0xc9,0x88,0x91,0xdb,0xb9, +0xaf,0xa3,0xeb,0x97,0xf8,0x6f,0xe1,0xa4,0xf0,0x97,0x83,0x74,0xcd,0x39,0x54,0x2b, +0x47,0x10,0x2f,0x8e,0xec,0x7a,0xd7,0x51,0x5e,0xde,0x5d,0x87,0xfa,0xb6,0x1a,0x14, +0xfa,0xf5,0xf5,0x3e,0x8f,0x03,0x87,0x58,0x5c,0x3c,0x29,0x76,0x41,0x5f,0x0c,0x7f, +0xc1,0x5c,0xbe,0x35,0x9f,0x87,0x7f,0xb3,0xbc,0x3e,0x0f,0xb2,0x9b,0xcb,0xd5,0x3c, +0x65,0x75,0xf6,0x56,0xda,0xd8,0x65,0xb4,0x88,0xac,0x93,0x1f,0x70,0xc7,0xcb,0x42, +0x3b,0x87,0x6f,0x4a,0xfb,0x9e,0xbf,0x23,0xff,0x00,0xe0,0xb6,0x56,0x5a,0x90,0xf8, +0x89,0xf0,0xd6,0xf2,0x48,0xdc,0xe9,0x07,0x4a,0xb9,0x8a,0x17,0xc7,0xc8,0x26,0x13, +0x29,0x90,0x7d,0x76,0x98,0xff,0x00,0x2a,0xf4,0xd1,0xdc,0xcf,0x86,0xbf,0x67,0xbf, +0x04,0xe9,0xbf,0x12,0x7e,0x39,0x78,0x17,0xc3,0x3a,0xcd,0xe4,0x76,0x1a,0x56,0xa9, +0xac,0x5b,0xdb,0x5d,0x4f,0x2b,0x05,0x51,0x19,0x71,0xb8,0x64,0xf7,0x61,0xf2,0x8f, +0x72,0x2b,0xfa,0x16,0xf8,0xcd,0xf1,0x1b,0x4e,0xf8,0x1d,0xf0,0x6f,0xc5,0x1e,0x2e, +0x9e,0x38,0xe3,0xb4,0xd0,0x34,0xc9,0x27,0x86,0xd9,0x70,0x81,0xdd,0x53,0x11,0x44, +0xbd,0x86,0xe6,0xda,0xa0,0x7b,0xd7,0xf3,0x4e,0xac,0x51,0x83,0x29,0x2a,0xc0,0xe4, +0x11,0xd4,0x57,0x5f,0xaa,0xfc,0x62,0xf1,0xde,0xbb,0xe1,0x97,0xf0,0xee,0xa7,0xe3, +0x2d,0x7b,0x51,0xd0,0x5f,0x6e,0xed,0x32,0xeb,0x52,0x9a,0x5b,0x73,0xb4,0x86,0x5c, +0xc6,0xcc,0x47,0x04,0x02,0x38,0xe3,0x14,0xc8,0x4e,0xc7,0x77,0xe1,0x9f,0xda,0x7f, +0xe3,0xb6,0xb5,0xe2,0xab,0x6b,0x5d,0x23,0xe2,0x6f,0x8b,0x5b,0x55,0xd5,0x2f,0x16, +0x28,0xa1,0x4d,0x5a,0x72,0xad,0x2c,0x8f,0x85,0x01,0x4b,0x60,0x0c,0xb7,0x40,0x31, +0x5f,0xd0,0x5f,0xc3,0xcd,0x07,0x50,0xf0,0xbf,0x81,0x74,0x0d,0x27,0x55,0xd4,0xae, +0x35,0x9d,0x52,0xce,0xc6,0x18,0x6f,0x35,0x0b,0xa9,0x0c,0x92,0x5c,0xcc,0x10,0x79, +0x92,0x33,0x1e,0x4e,0x5b,0x26,0xbf,0x99,0xff,0x00,0x09,0xf8,0xaf,0x55,0xf0,0x37, +0x89,0x34,0xed,0x7f,0x43,0xbc,0x6d,0x3f,0x58,0xd3,0xa7,0x5b,0x9b,0x5b,0xa4,0x55, +0x66,0x8a,0x45,0x39,0x56,0x01,0x81,0x19,0x1e,0xe2,0xbe,0x84,0xd3,0x3f,0xe0,0xa5, +0x1f,0xb4,0x76,0x95,0xf7,0x3e,0x24,0x5c,0x4e,0x3d,0x2e,0xb4,0xfb,0x49,0x7f,0xf4, +0x28,0x8d,0x0c,0x69,0x9f,0xbf,0xd4,0x57,0xe1,0x66,0x99,0xff,0x00,0x05,0x62,0xfd, +0xa1,0xec,0x17,0x12,0xeb,0xda,0x46,0xa1,0xef,0x73,0xa4,0x42,0x3f,0xf4,0x00,0xb5, +0xbf,0x63,0xff,0x00,0x05,0x87,0xf8,0xed,0x6b,0x81,0x35,0x9f,0x84,0xaf,0x3f,0xeb, +0xae,0x99,0x2a,0x9f,0xfc,0x76,0x61,0x4a,0xc5,0x5d,0x1f,0xb6,0x94,0x57,0x86,0xfe, +0xc6,0x7f,0x16,0x3c,0x69,0xf1,0xc7,0xe0,0x3e,0x8b,0xe3,0x8f,0x1c,0x58,0xe9,0xba, +0x6e,0xa3,0xac,0x49,0x2c,0xd6,0xb6,0xfa,0x64,0x4f,0x1c,0x7f,0x66,0x0d,0xb5,0x18, +0x87,0x76,0x39,0x62,0xac,0x7a,0xe3,0x05,0x7f,0x1f,0x4a,0xf8,0xa1,0xe3,0xfd,0x3f, +0xe1,0x67,0xc3,0xbf,0x12,0x78,0xbf,0x54,0x60,0x2c,0x34,0x4b,0x09,0xaf,0xa5,0x05, +0xb1,0xbf,0x62,0x92,0x14,0x7b,0xb1,0xc2,0x8f,0x72,0x29,0x0c,0xea,0x28,0xaf,0xcb, +0xad,0x3b,0xfe,0x0b,0x77,0x64,0x42,0x8b,0xef,0x84,0xd3,0xab,0x77,0xfb,0x3e,0xb8, +0x0f,0xf3,0x80,0x57,0x61,0xa5,0x7f,0xc1,0x6a,0xfe,0x1b,0xcb,0x1e,0x75,0x2f,0x00, +0x78,0xa6,0xd2,0x4f,0xee,0xda,0xbd,0xb4,0xe3,0xf3,0x69,0x13,0xf9,0x53,0xb0,0xae, +0x8f,0xd1,0x5a,0x2b,0xe0,0x5b,0x4f,0xf8,0x2c,0xef,0xc1,0x89,0xb1,0xe7,0x78,0x6b, +0xc6,0xb6,0xe7,0xd3,0xec,0x56,0xad,0xfc,0xae,0x2b,0xab,0xd1,0xbf,0xe0,0xad,0xdf, +0xb3,0xe6,0xa6,0xa0,0xdd,0x6a,0x9a,0xee,0x90,0x7d,0x2f,0x34,0x89,0x1b,0x1f,0xf7, +0xe8,0xbd,0x01,0x74,0x7d,0x9f,0x45,0x7c,0xa7,0x69,0xff,0x00,0x05,0x44,0xfd,0x9b, +0x6e,0x80,0x27,0xe2,0x04,0x90,0x67,0xfe,0x7a,0xe8,0xb7,0xe3,0xf9,0x42,0x6b,0xa6, +0xd2,0xff,0x00,0xe0,0xa0,0xbf,0xb3,0xce,0xae,0x14,0xc3,0xf1,0x4f,0x46,0x8b,0x77, +0x41,0x74,0xb3,0x40,0x7f,0xf1,0xf4,0x14,0x87,0x73,0xe8,0x6a,0x2b,0xc9,0xf4,0xff, +0x00,0xda,0xcb,0xe0,0xb6,0xa8,0xa1,0xad,0xfe,0x2b,0xf8,0x35,0x81,0xec,0xfa,0xe5, +0xba,0x1f,0xc9,0x9c,0x56,0xfd,0x97,0xc7,0x5f,0x86,0xda,0x96,0x3e,0xc9,0xf1,0x07, +0xc2,0xd7,0x39,0xe9,0xe5,0x6b,0x56,0xcd,0x9f,0xc9,0xe8,0x03,0xb4,0x9a,0x08,0xe7, +0x52,0x92,0x22,0xc8,0x87,0xaa,0xb0,0xc8,0x3f,0x85,0x50,0x9f,0xc3,0x3a,0x3d,0xcf, +0xfa,0xed,0x2e,0xce,0x5f,0xf7,0xed,0xd0,0xff,0x00,0x4a,0x76,0x9f,0xe2,0x4d,0x27, +0x56,0x8c,0x49,0x63,0xa9,0xd9,0x5e,0xc6,0x79,0x0d,0x6f,0x70,0x92,0x03,0xf9,0x13, +0x5a,0x0a,0xe1,0x86,0x41,0x04,0x7a,0x83,0x51,0x28,0x46,0x5f,0x12,0xb8,0x9a,0x4f, +0x74,0x73,0xf3,0x7c,0x3c,0xf0,0xc5,0xc7,0x32,0x78,0x7f,0x4e,0x3f,0xf6,0xea,0x83, +0xfa,0x55,0x49,0x7e,0x15,0x78,0x46,0x51,0xce,0x81,0x66,0xbf,0xee,0x47,0xb7,0xf9, +0x57,0x59,0x9a,0x5a,0xc2,0x58,0x5a,0x12,0xde,0x0b,0xee,0x44,0x3a,0x70,0x7b,0xc5, +0x1c,0x8e,0x9d,0xf0,0xaf,0xc2,0xfa,0x4e,0xa5,0x6f,0x7f,0x65,0xa5,0xad,0xbd,0xd4, +0x0d,0xba,0x37,0x49,0x5f,0x83,0xd3,0xa6,0x71,0x5d,0x68,0xeb,0x4b,0x45,0x69,0x4e, +0x8d,0x3a,0x2a,0xd4,0xe2,0x92,0xf2,0x2a,0x31,0x8c,0x34,0x8a,0xb0,0x51,0x45,0x15, +0xb1,0x42,0x1a,0xe2,0x7e,0x28,0x7c,0x3c,0x9b,0xe2,0x1d,0x85,0x9d,0xaa,0x6a,0x22, +0xc2,0x3b,0x79,0x0c,0xa5,0x4c,0x3e,0x66,0xf6,0xc6,0x07,0xf1,0x0c,0x63,0x27,0xd7, +0xad,0x76,0xf4,0x56,0x15,0xe8,0x43,0x13,0x4d,0xd2,0xa8,0xaf,0x17,0xb9,0x13,0x82, +0xa9,0x17,0x19,0x6c,0x7c,0xf5,0x37,0xec,0xcd,0xaa,0x2e,0x7c,0x9d,0x66,0xd1,0xff, +0x00,0xdf,0x8d,0x97,0xfc,0x6a,0x93,0xfe,0xcd,0xbe,0x23,0x19,0xd9,0x7d,0xa6,0xb7, +0xd6,0x49,0x07,0xfe,0xc9,0x5f,0x49,0x51,0x5e,0x0b,0xe1,0xdc,0xbd,0xfd,0x97,0xf7, +0xb3,0x8d,0xe0,0x68,0xbe,0x9f,0x89,0xf3,0x1c,0xff,0x00,0xb3,0xbf,0x8a,0xa2,0x52, +0x55,0xf4,0xf9,0x88,0xfe,0x14,0x9c,0x8f,0xe6,0xa2,0xbb,0x0f,0x83,0x7f,0x0a,0xb5, +0x8f,0x0a,0x78,0x9a,0x7d,0x4b,0x57,0x82,0x38,0x55,0x20,0x31,0xc3,0xb6,0x45,0x7d, +0xcc,0xc4,0x64,0xf0,0x78,0xc0,0x18,0xfc,0x6b,0xdb,0x28,0xaa,0xa1,0x90,0xe1,0x30, +0xd5,0x63,0x5a,0x17,0xbc,0x7c,0xc2,0x18,0x2a,0x54,0xe4,0xa4,0xaf,0xa0,0x51,0x45, +0x15,0xf4,0x67,0x78,0x51,0x45,0x14,0x00,0x51,0x45,0x14,0x00,0x87,0x9a,0xf2,0xef, +0x88,0x7f,0x03,0xac,0x3c,0x55,0x24,0x97,0xda,0x63,0xa6,0x9b,0xa9,0xb6,0x59,0xb8, +0xfd,0xd4,0xc7,0xd5,0x80,0xe8,0x7d,0xc7,0xe4,0x6b,0xd4,0xa8,0xae,0x4c,0x4e,0x16, +0x8e,0x2e,0x1e,0xce,0xb4,0x6e,0x8c,0xea,0x53,0x8d,0x55,0xcb,0x35,0x73,0xe3,0x1f, +0x13,0x78,0x1f,0x5b,0xf0,0x84,0xc5,0x35,0x4b,0x09,0x20,0x8f,0x38,0x13,0xaf,0xcd, +0x13,0x7d,0x18,0x71,0xf8,0x75,0xf6,0xac,0x2a,0xfb,0x9e,0x68,0x52,0x78,0xca,0x48, +0xaa,0xe8,0x78,0x2a,0xc3,0x20,0xd7,0x15,0xae,0x7c,0x18,0xf0,0x9e,0xb8,0x59,0xdf, +0x4d,0x5b,0x49,0x4f,0xfc,0xb4,0xb3,0x6f,0x2b,0xf4,0x1f,0x2f,0xe9,0x5f,0x0f,0x8a, +0xe1,0x79,0x5e,0xf8,0x69,0xfc,0x9f,0xf9,0xa3,0xc7,0xa9,0x97,0x3d,0xe9,0xbf,0xbc, +0xf9,0x36,0x8a,0xf7,0xed,0x43,0xf6,0x65,0xb2,0x91,0x89,0xb0,0xd6,0xe7,0x85,0x7b, +0x2d,0xc4,0x2b,0x27,0xea,0x0a,0xd6,0x0d,0xcf,0xec,0xd5,0xad,0x23,0x91,0x06,0xa9, +0x63,0x2a,0xf6,0x32,0x07,0x43,0xfa,0x03,0x5e,0x0c,0xf2,0x2c,0xc2,0x0f,0xf8,0x77, +0xf4,0x68,0xe3,0x78,0x3a,0xeb,0xec,0x9e,0x3f,0x45,0x7a,0xb1,0xfd,0x9b,0xfc,0x4b, +0xda,0xf7,0x4b,0x3f,0xf6,0xd6,0x4f,0xfe,0x22,0x9e,0x9f,0xb3,0x6f,0x88,0xc9,0xf9, +0xef,0xb4,0xd5,0x1e,0xd2,0x48,0x7f,0xf6,0x4a,0xc1,0x64,0xf8,0xf7,0xff,0x00,0x2e, +0x99,0x1f,0x55,0xad,0xfc,0xac,0xf2,0x6a,0x2b,0xdb,0x74,0xff,0x00,0xd9,0x9a,0xe9, +0xb9,0xbd,0xd7,0x22,0x8f,0xd5,0x60,0xb7,0x2f,0xfa,0x92,0x3f,0x95,0x75,0x9a,0x3f, +0xec,0xf3,0xe1,0x9b,0x0c,0x35,0xdb,0x5d,0x6a,0x4c,0x3b,0x4b,0x26,0xc4,0xfc,0x97, +0x07,0xf5,0xae,0xda,0x5c,0x3d,0x8f,0xa8,0xf5,0x8a,0x8f,0xab,0xff,0x00,0x2b,0x9a, +0xc7,0x03,0x5a,0x5b,0xab,0x1f,0x36,0x59,0xd9,0x5c,0x6a,0x17,0x09,0x05,0xac,0x12, +0xdc,0xcc,0xe7,0x0b,0x1c,0x28,0x59,0x8f,0xd0,0x0a,0xf5,0x5f,0x05,0xfe,0xcf,0x9a, +0x9e,0xaa,0xd1,0xdc,0xeb,0xb2,0x7f,0x66,0x5a,0x13,0x9f,0x21,0x08,0x69,0xd8,0x7e, +0xa1,0x7f,0x1c,0x9f,0x6a,0xf7,0xdd,0x1f,0xc3,0xba,0x6f,0x87,0xe1,0x31,0x69,0xd6, +0x36,0xf6,0x51,0x9e,0xa2,0x18,0xc2,0xe7,0xeb,0xeb,0x5a,0x75,0xf4,0xd8,0x3e,0x19, +0xa3,0x49,0xa9,0xe2,0x25,0xcc,0xfb,0x6c,0xbf,0xcd,0x9e,0x85,0x2c,0xbe,0x31,0xd6, +0xa3,0xb9,0x93,0xe1,0xdf,0x0c,0xe9,0xbe,0x15,0xd3,0xd6,0xcf,0x4c,0xb5,0x4b,0x58, +0x47,0x5d,0xbf,0x79,0xcf,0xab,0x1e,0xa4,0xfd,0x6b,0x54,0x74,0xa5,0xa2,0xbe,0xca, +0x10,0x8d,0x38,0xa8,0xc1,0x59,0x23,0xd5,0x49,0x45,0x59,0x05,0x35,0xba,0x73,0x4e, +0xa8,0x2f,0x56,0x66,0xb5,0x98,0x40,0x50,0x4f,0xb0,0xf9,0x65,0xfe,0xee,0xec,0x71, +0x9f,0x6c,0xd5,0x3d,0x15,0xc6,0x7c,0x99,0xf1,0x6f,0x5d,0xfe,0xdf,0xf1,0xfe,0xab, +0x32,0xb6,0xe8,0xa1,0x93,0xec,0xd1,0xf3,0x9e,0x13,0x83,0x8f,0xab,0x6e,0x3f,0x8d, +0x71,0xd5,0xdd,0x6b,0xff,0x00,0x06,0x7c,0x5b,0xa3,0xb4,0x92,0x35,0x81,0xd4,0x50, +0x1c,0x99,0xac,0xdb,0xcc,0x2d,0xef,0xb7,0xef,0x7e,0x95,0xc5,0xde,0xd9,0x5c,0x69, +0xb3,0x18,0x6e,0xed,0xe5,0xb5,0x98,0x75,0x8e,0x64,0x28,0xdf,0x91,0xe6,0xbf,0x11, +0xc6,0xd2,0xc4,0x2a,0xd3,0xa9,0x5e,0x0d,0x36,0xdb,0xd5,0x1f,0x23,0x5a,0x33,0xe7, +0x72,0x92,0xdc,0x86,0x8a,0x28,0xaf,0x38,0xc0,0x28,0xa2,0x8a,0x00,0x28,0xa2,0x8a, +0x00,0x28,0xa2,0xae,0xe9,0x5a,0x26,0xa1,0xae,0xcf,0xe4,0xe9,0xd6,0x53,0xde,0xcb, +0xdd,0x60,0x42,0xd8,0xf7,0x38,0xe9,0xf8,0xd5,0x46,0x32,0x9b,0xe5,0x8a,0xbb,0x1a, +0x4d,0xe8,0x8a,0x55,0xd4,0x78,0x03,0xc0,0x17,0xfe,0x3d,0xd5,0xd6,0xde,0xdd,0x5a, +0x2b,0x38,0xc8,0x37,0x17,0x44,0x7c,0xb1,0xaf,0xa0,0xf5,0x63,0xd8,0x7f,0x4a,0xef, +0xbc,0x1b,0xfb,0x3b,0xde,0xdd,0xba,0x5c,0x78,0x86,0x71,0x67,0x00,0xe4,0xda,0x40, +0xc1,0xa4,0x6f,0x62,0xc3,0x81,0xf8,0x67,0xf0,0xaf,0x76,0xd1,0x74,0x5b,0x1f,0x0f, +0xd8,0x47,0x65,0xa7,0xdb,0x25,0xad,0xb4,0x63,0xe5,0x44,0x1f,0xa9,0xf5,0x3e,0xe6, +0xbe,0xc3,0x2c,0xe1,0xfa,0xb5,0xa4,0xaa,0x62,0x97,0x2c,0x7b,0x75,0x7f,0xe4,0x7a, +0x98,0x7c,0x14,0xa4,0xd4,0xaa,0x68,0x83,0x45,0xd1,0xad,0x74,0x0d,0x32,0xdb,0x4f, +0xb2,0x8c,0x45,0x6d,0x02,0x04,0x45,0xf6,0xf5,0x3e,0xa4,0xfa,0xd5,0xe1,0x4b,0x45, +0x7e,0x99,0x18,0xa8,0x25,0x18,0xec,0x8f,0x7d,0x24,0x95,0x90,0x51,0x45,0x15,0x43, +0x1b,0x21,0xdb,0x1b,0x1f,0x40,0x4d,0x7c,0x35,0xf1,0xd6,0xeb,0xcf,0xf1,0x4c,0xbc, +0xe7,0xe6,0x26,0xbe,0xe0,0xbe,0x7f,0x2e,0xce,0x76,0x3d,0x90,0x9f,0xd2,0xbe,0x0b, +0xf8,0xbb,0x38,0x9f,0xc5,0x13,0xfd,0x4f,0xf3,0xaf,0x91,0xe2,0x19,0x5a,0x9d,0x38, +0xf7,0x67,0xcb,0x71,0x0c,0xad,0x86,0xb1,0xe0,0x5f,0x15,0xe7,0xf2,0xb4,0x59,0xb9, +0xec,0x7f,0x95,0x7d,0xeb,0xfb,0x03,0x69,0xbf,0xd9,0xdf,0xb2,0x7f,0x81,0x7d,0x6e, +0x23,0xb8,0xb9,0x38,0xff,0x00,0x6e,0xe2,0x53,0x5f,0x9f,0x7f,0x19,0x26,0x11,0xe8, +0x92,0xf3,0x8f,0x94,0xff,0x00,0x2a,0xfd,0x29,0xfd,0x90,0xec,0x06,0x9b,0xfb,0x31, +0x7c,0x33,0x84,0x2e,0xdc,0xe8,0x76,0xd2,0x90,0x7d,0x5d,0x77,0x9f,0xd5,0xab,0xb3, +0x26,0x56,0xa2,0x78,0x1c,0x1f,0x1b,0xfb,0x79,0xf9,0xa3,0xd7,0xa8,0xa2,0x8a,0xfa, +0x23,0xf4,0x83,0xe7,0x5f,0xda,0xf7,0xc6,0x0d,0x69,0xa2,0xe9,0x5e,0x1c,0x81,0xf0, +0x6f,0x64,0x37,0x37,0x00,0x7f,0x71,0x3e,0xe8,0x3f,0x56,0x39,0xff,0x00,0x80,0xd7, +0x94,0x7e,0xcf,0x3e,0x12,0xff,0x00,0x84,0xa3,0xe2,0x15,0xa3,0x3a,0x6e,0xb7,0xb3, +0xfd,0xfb,0xfa,0x71,0xd2,0xb2,0x7e,0x36,0xf8,0xb1,0xbc,0x65,0xf1,0x33,0x5a,0xbb, +0x0f,0xbe,0xda,0xde,0x53,0x67,0x6f,0xce,0x40,0x48,0xf2,0x38,0xfa,0xb6,0xe3,0xf8, +0xd7,0xd0,0x7f,0xb2,0xb7,0x84,0x46,0x93,0xe1,0x29,0xf5,0x79,0x53,0x13,0xde,0xbe, +0x14,0x91,0xfc,0x03,0xff,0x00,0xaf,0x5f,0x01,0xff,0x00,0x23,0x1c,0xd3,0xfb,0xa9, +0xfe,0x0b,0xfc,0xd9,0xf9,0xfd,0x2f,0xf8,0x52,0xcd,0x5c,0xf7,0x8c,0x7f,0x25,0xff, +0x00,0x04,0xf7,0x30,0x30,0x00,0xe9,0x4b,0x48,0x29,0x6b,0xef,0xcf,0xd0,0x02,0xbc, +0xff,0x00,0xe3,0x67,0xc0,0x9f,0x05,0xfe,0xd0,0x9e,0x0c,0x97,0xc3,0x1e,0x37,0xd1, +0xe3,0xd5,0xb4,0xd2,0xe2,0x58,0x9b,0x71,0x49,0xad,0xe5,0x00,0x81,0x24,0x4e,0x39, +0x46,0xc1,0x23,0x8e,0xa0,0x90,0x72,0x09,0x15,0xe8,0x14,0x50,0x07,0xe6,0x47,0x8d, +0x3f,0xe0,0x89,0xda,0x1d,0xc5,0xc3,0x4b,0xe1,0x5f,0x89,0xb7,0xfa,0x7c,0x1c,0x9f, +0x23,0x57,0xd3,0x92,0xe5,0x87,0xfd,0xb4,0x47,0x8f,0xff,0x00,0x41,0xaf,0xcb,0x8f, +0x1b,0x68,0x56,0x5e,0x17,0xf1,0x86,0xb5,0xa3,0xe9,0xda,0xb4,0x7a,0xf5,0x8e,0x9f, +0x79,0x2d,0xac,0x3a,0x9c,0x31,0x98,0xe3,0xba,0x54,0x72,0xa2,0x55,0x52,0x49,0x0a, +0xd8,0xc8,0xe7,0xa1,0xaf,0xe9,0x9b,0xc6,0x1a,0x1d,0xc7,0x89,0x7c,0x2b,0xac,0x69, +0x16,0x9a,0x94,0xba,0x35,0xcd,0xfd,0x9c,0xb6,0xb1,0xea,0x10,0x20,0x69,0x2d,0x99, +0xd0,0xa8,0x91,0x01,0xe0,0xb2,0xe7,0x23,0x3c,0x64,0x0a,0xfc,0xdd,0xd4,0x3f,0xe0, +0x89,0x1a,0x41,0x95,0x5a,0xc7,0xe2,0x9d,0xea,0xc6,0x18,0x12,0x97,0x3a,0x42,0x31, +0x23,0xb8,0xca,0xca,0x3f,0x95,0x3b,0x92,0xd1,0xf2,0x97,0xc2,0x7f,0xf8,0x26,0x5f, +0xc6,0x3f,0x8c,0xbf,0x0d,0x34,0x4f,0x1b,0xe8,0x03,0x41,0x87,0x4b,0xd5,0xe2,0x69, +0xad,0xed,0xf5,0x0b,0xd7,0x86,0xe3,0x60,0x76,0x50,0xc5,0x7c,0xb2,0x30,0xdb,0x77, +0x0e,0x79,0x04,0x1a,0xd3,0xbc,0xff,0x00,0x82,0x4e,0x7e,0xd1,0x16,0xa4,0x88,0xf4, +0x0d,0x1e,0xe8,0x0e,0xf0,0xeb,0x30,0x8c,0xff,0x00,0xdf,0x44,0x57,0xed,0xff,0x00, +0x85,0x7c,0x35,0x63,0xe0,0xdf,0x0c,0xe9,0x3a,0x06,0x99,0x17,0x91,0xa6,0xe9,0x76, +0x91,0x59,0x5a,0xc5,0x9c,0xec,0x8a,0x34,0x08,0x83,0xf2,0x51,0x5a,0xb4,0x5c,0x2c, +0x8f,0xc0,0x4d,0x47,0xfe,0x09,0xa7,0xfb,0x47,0x69,0xcc,0xc0,0xfc,0x38,0x9a,0xe5, +0x57,0xf8,0xad,0xb5,0x1b,0x47,0x07,0xe9,0xfb,0xdc,0x9a,0xc6,0xd1,0xbf,0x60,0x7f, +0x8e,0xf7,0xde,0x25,0xd3,0x34,0xbb,0xcf,0x86,0x7e,0x20,0xb0,0x86,0xea,0xee,0x2b, +0x79,0x6f,0x5e,0xd7,0x74,0x50,0x2b,0x38,0x53,0x23,0x32,0x92,0x02,0xa8,0x39,0x27, +0x3d,0x05,0x7f,0x42,0x78,0xa0,0x80,0x7b,0x51,0x70,0xe5,0x46,0x2f,0x82,0xfc,0x29, +0x63,0xe0,0x5f,0x07,0x68,0x9e,0x1c,0xd3,0x23,0x58,0xb4,0xfd,0x26,0xce,0x1b,0x28, +0x11,0x46,0x00,0x48,0xd0,0x28,0xfd,0x05,0x7c,0x4f,0xff,0x00,0x05,0x7d,0xf8,0xb1, +0x73,0xe1,0x4f,0x80,0x9a,0x6f,0x82,0x34,0xd5,0xb8,0x6b,0xef,0x15,0xde,0xff,0x00, +0xa4,0x98,0x63,0x2c,0xa2,0xce,0xdf,0x6b,0xb8,0x62,0x3a,0x66,0x46,0x84,0x0f,0x50, +0x1b,0xd2,0xbe,0xf3,0xa6,0xb2,0x2b,0x75,0x00,0xfd,0x45,0x22,0x8f,0xe5,0xad,0xa3, +0x64,0x24,0x32,0xb2,0xe3,0xfb,0xc3,0x14,0xd1,0xcf,0x4e,0x6b,0xfa,0x8b,0xbc,0xd1, +0x74,0xfd,0x42,0x33,0x1d,0xd5,0x85,0xb5,0xca,0x1e,0xab,0x34,0x2a,0xe0,0xfe,0x04, +0x57,0x2d,0xab,0xfc,0x11,0xf8,0x77,0xaf,0xa9,0x5d,0x4b,0xc0,0x7e,0x19,0xbf,0x53, +0xd4,0x5c,0xe9,0x16,0xf2,0x67,0xf3,0x4a,0x77,0x23,0x94,0xfe,0x67,0x71,0x9a,0x2b, +0xfa,0x3a,0xba,0xfd,0x90,0x3e,0x07,0x5e,0xe7,0xcd,0xf8,0x43,0xe0,0x9c,0x9e,0xa5, +0x34,0x1b,0x64,0x3f,0x98,0x41,0x5c,0xbe,0xad,0xff,0x00,0x04,0xfb,0xfd,0x9e,0xb5, +0x9c,0xf9,0xdf,0x0b,0x74,0x58,0x73,0xff,0x00,0x3e,0x7e,0x6d,0xbf,0xfe,0x8b,0x75, +0xc5,0x3b,0x87,0x29,0xfc,0xf6,0xd1,0x5f,0xbd,0x17,0x5f,0xf0,0x4b,0x8f,0xd9,0xb2, +0xe9,0xcb,0x0f,0x01,0xcd,0x01,0x3f,0xf3,0xcb,0x5b,0xbe,0x03,0xf2,0xf3,0xab,0x9f, +0xd5,0x3f,0xe0,0x92,0x1f,0xb3,0xed,0xfe,0xef,0xb3,0xe9,0xba,0xf6,0x9b,0x9e,0x9f, +0x66,0xd5,0xdd,0xb1,0xff,0x00,0x7f,0x03,0x51,0x70,0xe5,0x3f,0x0d,0xe8,0xaf,0xd9, +0xab,0xef,0xf8,0x23,0x0f,0xc1,0xdb,0x87,0x63,0x6d,0xe2,0x8f,0x19,0x5a,0x03,0xd1, +0x7e,0xd5,0x6c,0xe0,0x7e,0x70,0x56,0x05,0xff,0x00,0xfc,0x11,0x43,0xc0,0x32,0x03, +0xf6,0x2f,0x88,0x9e,0x24,0xb7,0x3d,0xbe,0xd1,0x6f,0x6f,0x2e,0x3f,0x25,0x5a,0x2e, +0x1c,0xac,0xfc,0x89,0x8a,0xee,0x68,0x71,0xe5,0xcd,0x24,0x78,0xfe,0xeb,0x11,0x5a, +0xf6,0x3e,0x3b,0xf1,0x2e,0x98,0x41,0xb3,0xf1,0x0e,0xab,0x69,0x8e,0x9e,0x45,0xec, +0xa9,0xfc,0x9a,0xbf,0x4c,0x35,0x5f,0xf8,0x22,0x28,0x24,0xff,0x00,0x66,0x7c,0x59, +0xd8,0x3b,0x0b,0xbd,0x13,0x71,0xff,0x00,0xc7,0x67,0x15,0xcd,0xde,0xff,0x00,0xc1, +0x12,0xbc,0x5d,0x19,0x3f,0x64,0xf8,0x9d,0xa2,0x4e,0x3b,0x79,0xda,0x6c,0xd1,0xff, +0x00,0x27,0x6a,0x05,0x66,0x7c,0x2f,0xa6,0xfe,0xd0,0x9f,0x14,0x34,0x62,0x0d,0x8f, +0xc4,0x5f,0x15,0x5a,0xe3,0xa7,0x95,0xac,0xdc,0x2f,0xfe,0xcf,0x5d,0x56,0x9f,0xfb, +0x6a,0xfc,0x77,0xd2,0xc0,0x16,0xff,0x00,0x15,0xfc,0x53,0x81,0xda,0x5d,0x45,0xe4, +0xff,0x00,0xd0,0xb3,0x5f,0x4c,0x6a,0xdf,0xf0,0x46,0x1f,0x8b,0x96,0xc7,0xfe,0x25, +0xfe,0x2c,0xf0,0x85,0xf0,0xff,0x00,0xa6,0xb3,0x5c,0xc2,0x7f,0xf4,0x4b,0x57,0x29, +0x7d,0xff,0x00,0x04,0x87,0xf8,0xfd,0x68,0x48,0x8a,0x1f,0x0d,0x5e,0x81,0xde,0x1d, +0x57,0x19,0xff,0x00,0xbe,0xd1,0x68,0x1d,0x99,0xe6,0x56,0x1f,0xf0,0x50,0xcf,0xda, +0x23,0x4f,0x60,0x53,0xe2,0x86,0xab,0x28,0x1d,0xae,0x22,0x82,0x5f,0xfd,0x0a,0x33, +0x5d,0x4e,0x9b,0xff,0x00,0x05,0x4c,0xfd,0xa3,0x34,0xec,0x67,0xc6,0x36,0x97,0x80, +0x76,0xb9,0xd2,0x2d,0x9b,0x3f,0x92,0x03,0x4b,0xa9,0xff,0x00,0xc1,0x2c,0x7f,0x68, +0xdd,0x3c,0x9d,0x9e,0x0d,0xb4,0xbd,0x03,0xbd,0xb6,0xb1,0x68,0x73,0xf8,0x34,0x8a, +0x6b,0x8d,0xbf,0xff,0x00,0x82,0x7f,0xfe,0xd0,0xba,0x73,0xb2,0xc9,0xf0,0xb3,0x5a, +0x93,0x6f,0x7b,0x7f,0x2a,0x50,0x7e,0x9b,0x5c,0xe6,0x8d,0x03,0x53,0xd5,0xac,0x7f, +0xe0,0xaf,0x7f,0x1f,0x6d,0x14,0x09,0x64,0xf0,0xcd,0xe7,0xfb,0x53,0x69,0x44,0x1f, +0xfc,0x72,0x45,0xae,0x9f,0x4b,0xff,0x00,0x82,0xce,0xfc,0x5e,0xb4,0x50,0x2f,0x7c, +0x2f,0xe1,0x1b,0xff,0x00,0x53,0xf6,0x7b,0x88,0xcf,0xe9,0x35,0x7c,0xc5,0x7b,0xfb, +0x1b,0xfc,0x73,0xd3,0xf7,0x79,0xff,0x00,0x09,0xbc,0x5c,0x02,0x8c,0x92,0x9a,0x4c, +0xce,0x07,0xe2,0xaa,0x6b,0x90,0xd4,0x7e,0x0a,0xfc,0x42,0xd1,0xd9,0x96,0xfb,0xc0, +0x9e,0x25,0xb4,0x2b,0xf7,0xbc,0xed,0x22,0xe1,0x71,0xf9,0xa5,0x1a,0x05,0xd9,0xf7, +0xa6,0x9f,0xff,0x00,0x05,0xb3,0xf1,0x7c,0x48,0x3e,0xdd,0xf0,0xcb,0x44,0xb8,0x7f, +0x5b,0x7d,0x46,0x68,0x87,0xe4,0x55,0xab,0x7f,0x4f,0xff,0x00,0x82,0xdd,0xce,0x31, +0xf6,0xef,0x84,0x91,0xb7,0xa9,0xb7,0xd7,0x88,0xfd,0x0c,0x06,0xbf,0x32,0xee,0x7c, +0x31,0xac,0x59,0x92,0x27,0xd2,0xaf,0x61,0x23,0xaf,0x99,0x6c,0xeb,0x8f,0xcc,0x56, +0x73,0xa1,0x8d,0xb6,0xb0,0x2a,0xde,0x87,0x8a,0x34,0x0b,0xb3,0xf5,0xc7,0x4a,0xff, +0x00,0x82,0xd8,0xf8,0x36,0x54,0xce,0xa5,0xf0,0xd7,0x5d,0xb6,0x6e,0xe2,0xd2,0xfa, +0x19,0x87,0xfe,0x3c,0x12,0xba,0x0b,0x2f,0xf8,0x2d,0x17,0xc2,0x59,0x71,0xf6,0x9f, +0x06,0xf8,0xc6,0xdc,0xfa,0xa4,0x36,0xae,0x3f,0xf4,0x78,0xaf,0xc6,0xdc,0xe7,0xbd, +0x18,0x34,0x58,0x2e,0xcf,0xdb,0xbd,0x37,0xfe,0x0a,0xfd,0xf0,0x16,0xf5,0x03,0x5c, +0x7f,0xc2,0x4d,0x60,0x4f,0x69,0xb4,0xb0,0xf8,0xff,0x00,0xbe,0x24,0x6a,0xe9,0xec, +0xbf,0xe0,0xaa,0x5f,0xb3,0x75,0xdc,0x41,0xe4,0xf1,0xb5,0xdd,0xa3,0x1f,0xe0,0x9b, +0x44,0xbd,0x24,0x7e,0x2b,0x11,0x1f,0xad,0x7e,0x0e,0xe2,0x8a,0x2c,0x1c,0xc7,0xf4, +0x01,0x63,0xff,0x00,0x05,0x23,0xfd,0x9c,0x6f,0xc0,0xd9,0xf1,0x32,0xce,0x2c,0xf6, +0x9e,0xc6,0xee,0x3f,0xfd,0x0a,0x21,0x5d,0x6e,0x99,0xfb,0x6a,0xfc,0x06,0xd5,0xe3, +0x0f,0x07,0xc5,0xcf,0x08,0xc6,0x0f,0x6b,0xad,0x56,0x2b,0x73,0xf9,0x48,0x54,0xd7, +0xf3,0xa5,0x9a,0x29,0x58,0x39,0x8f,0xe9,0x32,0xcf,0xf6,0x9c,0xf8,0x3f,0xa8,0x15, +0x16,0xdf,0x15,0x3c,0x17,0x39,0x6e,0x82,0x3f,0x10,0x5a,0x1c,0xff,0x00,0xe4,0x4a, +0xeb,0xb4,0xdf,0x1f,0x78,0x63,0x59,0x50,0xd6,0x1e,0x22,0xd2,0x6f,0x94,0xf2,0x0d, +0xb5,0xf4,0x52,0x03,0xf9,0x31,0xaf,0xe6,0x16,0x9c,0xb2,0x32,0x10,0x55,0x8a,0x91, +0xdc,0x1a,0x2c,0x1c,0xc7,0xf5,0x25,0x14,0xf1,0xcc,0x9b,0xe3,0x75,0x75,0xf5,0x52, +0x08,0xa7,0xe6,0xbf,0x97,0x8b,0x7f,0x10,0xea,0xb6,0x98,0xf2,0x35,0x3b,0xc8,0x71, +0xd3,0xcb,0xb8,0x75,0xc7,0xe4,0x6b,0x7b,0x4f,0xf8,0xc3,0xe3,0xcd,0x2b,0x1f,0x62, +0xf1,0xb7,0x88,0xad,0x31,0xd3,0xc9,0xd5,0x67,0x4c,0x7e,0x4f,0x45,0x87,0xcc,0x7f, +0x4d,0x39,0xa5,0xaf,0xe7,0x07,0x4e,0xfd,0xae,0x3e,0x35,0xe9,0x48,0xa9,0x69,0xf1, +0x5b,0xc5,0xf0,0xa2,0xf0,0x17,0xfb,0x66,0x72,0x3f,0x22,0xd5,0xd1,0xe9,0xff,0x00, +0xb7,0xbf,0xed,0x07,0xa6,0xe3,0xca,0xf8,0xab,0xaf,0xc9,0x8e,0xd7,0x12,0x24,0xdf, +0xfa,0x1a,0x9a,0x2c,0x1c,0xc8,0xfe,0x86,0xe8,0xaf,0xc0,0xed,0x33,0xfe,0x0a,0x75, +0xfb,0x46,0xe9,0x7d,0x3c,0x7c,0x2e,0x87,0xa5,0xd6,0x99,0x69,0x27,0xf3,0x8f,0x35, +0xd2,0xd9,0x7f,0xc1,0x5b,0x3f,0x68,0x4b,0x5c,0x79,0xba,0xae,0x85,0x79,0xff,0x00, +0x5d,0xb4,0x88,0xc6,0x7f,0xef,0x82,0xb4,0x58,0x77,0x47,0xee,0x65,0x15,0xf8,0xa9, +0xa6,0xff,0x00,0xc1,0x63,0xbe,0x37,0x5a,0x11,0xf6,0xad,0x2f,0xc2,0x77,0xc3,0xbe, +0xeb,0x09,0x90,0xff,0x00,0xe3,0xb3,0x0a,0xea,0xf4,0xff,0x00,0xf8,0x2d,0x67,0xc4, +0x28,0x71,0xf6,0xdf,0x87,0xfe,0x1b,0xb9,0xff,0x00,0xae,0x33,0xdc,0x45,0xfc,0xd9, +0xa8,0xb0,0x5d,0x1f,0xb0,0x14,0x57,0xe4,0xf5,0x8f,0xfc,0x16,0xe7,0x5b,0x56,0x1f, +0x6c,0xf8,0x51,0x60,0xeb,0xdc,0xc1,0xad,0x3a,0x9f,0xd6,0x13,0x5d,0x66,0x99,0xff, +0x00,0x05,0xb7,0xd0,0x5d,0x07,0xf6,0x8f,0xc2,0xdd,0x4a,0x27,0xef,0xf6,0x5d,0x56, +0x37,0x1f,0xf8,0xf4,0x62,0x8b,0x05,0xd1,0xfa,0x6b,0x45,0x7e,0x77,0xd8,0xff,0x00, +0xc1,0x6a,0x7e,0x18,0xc8,0x83,0xed,0x7e,0x06,0xf1,0x6c,0x12,0x1e,0xa2,0x1f,0xb2, +0xc8,0x07,0xe2,0x65,0x5f,0xe5,0x5d,0x16,0x9b,0xff,0x00,0x05,0x8e,0xf8,0x23,0x76, +0x07,0xda,0x74,0xaf,0x17,0x58,0x9e,0xfb,0xec,0x21,0x7c,0x7f,0xdf,0x33,0x1a,0x56, +0x0b,0xa3,0xee,0xea,0x2b,0xe3,0xdd,0x33,0xfe,0x0a,0xbd,0xfb,0x3a,0xdf,0x45,0xbe, +0x7f,0x12,0x6a,0xba,0x71,0xfe,0xe5,0xce,0x8d,0x72,0xc7,0xff,0x00,0x21,0xab,0x0a, +0xdd,0xb2,0xff,0x00,0x82,0x9c,0x7e,0xcd,0xd7,0xcc,0x14,0x7c,0x43,0x10,0x93,0xff, +0x00,0x3d,0xb4,0xab,0xd4,0xfe,0x70,0xd0,0x3b,0x9f,0x52,0xd1,0x5e,0x13,0xa6,0xfe, +0xdd,0x5f,0x00,0x35,0x58,0x95,0xe2,0xf8,0xb1,0xe1,0xa8,0x81,0xed,0x75,0x77,0xe4, +0x1f,0xc9,0xc0,0x35,0xbd,0x6b,0xfb,0x59,0x7c,0x14,0xbd,0x0a,0x61,0xf8,0xb5,0xe0, +0xa6,0xdd,0xd0,0x1d,0x7e,0xd4,0x13,0xf8,0x17,0xa0,0x0f,0x58,0xa2,0xb8,0xed,0x33, +0xe3,0x27,0x80,0xb5,0xa4,0x56,0xd3,0xfc,0x6d,0xe1,0xdb,0xd5,0x6e,0x86,0xdf,0x55, +0x81,0xf3,0xf9,0x3d,0x74,0xd6,0x9a,0xb5,0x8d,0xfc,0x61,0xed,0xaf,0x2d,0xee,0x10, +0xf4,0x68,0xa5,0x56,0x07,0xf1,0x06,0x80,0x2d,0xd4,0x17,0x56,0x70,0x5e,0x46,0x63, +0x9e,0x08,0xe7,0x8c,0xf5,0x59,0x14,0x30,0x3f,0x81,0xa9,0x43,0x82,0x32,0x0e,0x7e, +0x94,0xb9,0xa4,0xd2,0x6a,0xcc,0x37,0x39,0x4b,0xff,0x00,0x85,0x9e,0x14,0xd4,0x41, +0x12,0xe8,0x56,0x6a,0x4f,0x56,0x85,0x3c,0xa3,0xf9,0xae,0x2b,0x02,0xf3,0xf6,0x7d, +0xf0,0x95,0xc6,0x7c,0xb8,0x6e,0xad,0x73,0xff,0x00,0x3c,0xae,0x09,0xff,0x00,0xd0, +0xb3,0x5e,0x95,0x9a,0x2b,0x86,0xa6,0x5f,0x84,0xab,0xf1,0xd2,0x8b,0xf9,0x23,0x07, +0x42,0x9c,0xb7,0x8a,0x3c,0x7e,0x6f,0xd9,0xa7,0x44,0x63,0xfb,0xad,0x57,0x50,0x4f, +0xf7,0xbc,0xb6,0xff,0x00,0xd9,0x45,0x56,0x6f,0xd9,0x9b,0x4f,0xcf,0xcb,0xad,0x5c, +0x8f,0xac,0x4a,0x7f,0xad,0x7b,0x55,0x26,0x2b,0x8d,0xe4,0xb9,0x7b,0xff,0x00,0x97, +0x4b,0xf1,0xff,0x00,0x33,0x3f,0xaa,0x50,0xfe,0x53,0xc6,0x13,0xf6,0x66,0xd3,0x54, +0xfc,0xda,0xcd,0xd1,0xff,0x00,0x76,0x35,0x15,0x7e,0xd3,0xf6,0x70,0xf0,0xdc,0x0c, +0x0c,0xd7,0x7a,0x85,0xcf,0xb3,0x48,0x8a,0x3f,0x45,0xaf,0x58,0xc5,0x2d,0x38,0xe4, +0xd8,0x08,0xed,0x49,0x02,0xc2,0xd1,0x5f,0x64,0xe2,0x74,0xcf,0x83,0x7e,0x11,0xd2, +0x88,0x29,0xa3,0xc5,0x3b,0x7a,0xdc,0xb3,0x4b,0xfa,0x31,0x22,0xba,0xfb,0x4b,0x2b, +0x7b,0x08,0x56,0x1b,0x68,0x23,0x82,0x25,0xe0,0x24,0x48,0x14,0x0f,0xc0,0x54,0xf4, +0x57,0xa5,0x4b,0x0f,0x46,0x82,0xb5,0x28,0x25,0xe8,0x8e,0x88,0xc2,0x30,0xf8,0x55, +0x82,0x8a,0x28,0xae,0x82,0xc2,0x8a,0x28,0xa0,0x02,0x8a,0x28,0xa0,0x0c,0xef,0x10, +0xcb,0xe4,0xe8,0x97,0xaf,0xe9,0x13,0x7f,0x2a,0xf8,0x0b,0xe2,0x14,0xe6,0x7f,0x11, +0x5d,0x31,0xe7,0xe6,0x35,0xf7,0x7f,0x8e,0x66,0xf2,0x3c,0x2d,0xa8,0x36,0x71,0xfb, +0xb2,0x2b,0xe0,0x2f,0x18,0x4b,0xe6,0xeb,0x37,0x6d,0xfe,0xd1,0xaf,0x88,0xe2,0x29, +0x7b,0xf4,0xa3,0xea,0x7c,0x67,0x12,0x4a,0xd4,0xa2,0x8f,0x00,0xf8,0xed,0x75,0xe5, +0x68,0x93,0x8c,0xf4,0x42,0x7f,0x4a,0xfd,0x6a,0xf8,0x37,0xa6,0xff,0x00,0x63,0x7c, +0x24,0xf0,0x55,0x81,0x50,0x86,0xdb,0x45,0xb3,0x88,0xa8,0x18,0xc1,0x10,0xa0,0xaf, +0xc8,0x7f,0x8e,0xbf,0xe9,0x36,0x82,0xd8,0x13,0x99,0x59,0x63,0xe3,0xfd,0xa3,0x8f, +0xeb,0x5f,0xb3,0x7a,0x25,0xa8,0xb1,0xd1,0xec,0x6d,0x87,0x48,0x60,0x8e,0x31,0xf8, +0x28,0x1f,0xd2,0xbd,0xcc,0xa9,0x5a,0x82,0x38,0xf8,0x3e,0x3f,0xec,0xd5,0x27,0xde, +0x45,0xea,0x28,0xa2,0xbd,0xb3,0xef,0xcf,0xcd,0xfd,0x0b,0x4e,0x93,0xc4,0x1e,0x25, +0x8e,0xce,0x20,0x5a,0x4b,0x8b,0x92,0xbf,0x9b,0x1a,0xfd,0x0a,0xf0,0xbe,0x8b,0x17, +0x87,0xb4,0x1b,0x1d,0x3a,0x15,0xc2,0x41,0x12,0xa7,0xe3,0x8e,0x6b,0xe1,0x7f,0x80, +0x9a,0xce,0x9f,0xa2,0x7c,0x4f,0x67,0xd6,0x07,0x96,0x6c,0xae,0x65,0x88,0xa3,0x8e, +0x56,0x40,0xe4,0x73,0x9f,0xa5,0x7d,0xb5,0x6f,0xf1,0x0b,0x40,0xb8,0x50,0x57,0x51, +0x8b,0xf1,0x35,0xf2,0x19,0x34,0x29,0xd1,0x9d,0x59,0xce,0x49,0x4a,0xf6,0xf9,0x1f, +0x11,0xc3,0x2a,0x9a,0xc3,0xca,0xa4,0x9f,0xbc,0xdd,0xbe,0xe3,0xa4,0xa2,0xb1,0xe3, +0xf1,0x6e,0x91,0x2f,0xdd,0xbf,0x84,0xff,0x00,0xc0,0xaa,0xd2,0x6b,0x76,0x12,0x7d, +0xdb,0xc8,0x4f,0xfc,0x0c,0x57,0xd5,0xaa,0x90,0x7b,0x34,0x7d,0xaa,0x94,0x5f,0x52, +0xf5,0x23,0x67,0x1c,0x75,0xf7,0xa8,0x12,0xf6,0xde,0x5f,0xb9,0x3c,0x6d,0xf4,0x61, +0x52,0x89,0x50,0xf4,0x70,0x7f,0x1a,0xbb,0xa6,0x3b,0x8e,0x19,0xc0,0xc8,0xe6,0x8a, +0x40,0xd9,0x1d,0x69,0x73,0x4c,0x62,0xd1,0x49,0x45,0x00,0x2d,0x14,0x51,0x40,0x05, +0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x09,0x8a,0x5a,0x28,0xa0, +0x02,0x8a,0x28,0xa0,0x02,0x92,0x96,0x8a,0x00,0x4c,0x0f,0x4a,0x31,0x4b,0x45,0x00, +0x25,0x2d,0x14,0x50,0x01,0x45,0x14,0x50,0x03,0x1e,0x24,0x91,0x4a,0xba,0x2b,0x29, +0xea,0x08,0xc8,0xac,0x4d,0x5b,0xc0,0x5e,0x19,0xd7,0xa2,0x31,0xea,0x7e,0x1d,0xd2, +0x75,0x18,0xcf,0x54,0xba,0xb1,0x8a,0x50,0x7f,0x06,0x53,0x5b,0xd4,0x50,0x07,0x98, +0xdf,0x7e,0xcb,0xdf,0x07,0x35,0x26,0x66,0xba,0xf8,0x51,0xe0,0xa9,0xd9,0xba,0xb3, +0xf8,0x7e,0xd0,0x93,0xf8,0xf9,0x75,0x85,0xa9,0xfe,0xc5,0x1f,0x01,0xb5,0x58,0xca, +0x4d,0xf0,0x8f,0xc2,0x31,0x8f,0x5b,0x6d,0x2a,0x28,0x0f,0xe7,0x18,0x53,0x5e,0xd7, +0x45,0x00,0x7c,0xcb,0xa9,0x7f,0xc1,0x35,0xff,0x00,0x67,0x0d,0x53,0x3e,0x67,0xc3, +0x4b,0x58,0x49,0xef,0x6d,0xa8,0x5d,0xc3,0xff,0x00,0xa0,0xca,0x2b,0x9e,0xbe,0xff, +0x00,0x82,0x54,0x7e,0xce,0x37,0x6b,0x88,0xbc,0x21,0x7f,0x64,0x7f,0xbd,0x06,0xb7, +0x78,0x4f,0xfe,0x3f,0x23,0x57,0xd7,0x74,0x50,0x16,0x3e,0x1b,0xd6,0x3f,0xe0,0x8f, +0x5f,0x02,0xb5,0x01,0xfe,0x89,0x71,0xe2,0x9d,0x2c,0xff,0x00,0xd3,0xbe,0xa4,0x8f, +0xff,0x00,0xa3,0x23,0x6a,0xe5,0xae,0xbf,0xe0,0x8a,0xff,0x00,0x0b,0x1c,0x9f,0xb3, +0xf8,0xe3,0xc6,0x10,0xe7,0xa7,0x98,0xd6,0xaf,0x8f,0xca,0x11,0x5f,0xa1,0xb4,0x50, +0x2b,0x23,0xf3,0x37,0x55,0xff,0x00,0x82,0x25,0x78,0x72,0x40,0xdf,0xd9,0x9f,0x14, +0x35,0x4b,0x73,0xdb,0xed,0x7a,0x5c,0x72,0xe3,0xfe,0xf9,0x75,0xae,0x4e,0xef,0xfe, +0x08,0x8b,0xab,0xab,0x1f,0xb2,0xfc,0x59,0xb1,0x91,0x7b,0x09,0xb4,0x37,0x53,0xf8, +0xe2,0x73,0x5f,0xab,0xd4,0x50,0x16,0x47,0xe4,0x0e,0xa5,0xff,0x00,0x04,0x51,0xf8, +0x81,0x10,0x3f,0x60,0xf8,0x85,0xe1,0xbb,0xa3,0xdb,0xcf,0xb7,0x9e,0x1c,0xfe,0x41, +0xab,0x8f,0xd4,0xff,0x00,0xe0,0x8e,0x7f,0x1c,0x2d,0x1b,0x16,0xba,0x97,0x84,0xaf, +0xc7,0xaa,0xea,0x12,0xa7,0xe8,0xd0,0xd7,0xed,0x6d,0x18,0xa7,0x70,0xb2,0x3f,0x0c, +0x35,0x0f,0xf8,0x24,0xc7,0xed,0x0d,0x65,0x9f,0x2b,0x45,0xd1,0x6f,0xb1,0xff,0x00, +0x3e,0xfa,0xc4,0x43,0x3f,0xf7,0xde,0xda,0xe5,0x35,0x6f,0xf8,0x26,0x9f,0xed,0x1d, +0xa4,0xb1,0x07,0xe1,0xcc,0xd7,0x60,0x75,0x6b,0x5d,0x42,0xd2,0x41,0xff,0x00,0xa3, +0x6b,0xf7,0xeb,0x14,0x62,0x8b,0x85,0x91,0xfc,0xf0,0x5e,0xfe,0xc2,0x3f,0xb4,0x05, +0x81,0x22,0x5f,0x85,0x1e,0x22,0x6c,0x7f,0xcf,0x1b,0x71,0x2f,0xfe,0x80,0x4d,0x72, +0xfa,0xa7,0xec,0xb7,0xf1,0x8b,0x46,0x62,0xb7,0x9f,0x0b,0x7c,0x5f,0x16,0x3a,0x91, +0xa2,0x5c,0x38,0x1f,0x8a,0xa1,0x15,0xfd,0x23,0xd1,0x8a,0x2e,0x2b,0x1f,0xcc,0x7d, +0xff,0x00,0xc2,0xef,0x19,0xe9,0x4c,0x56,0xf7,0xc2,0x5a,0xed,0x99,0x1d,0x44,0xfa, +0x6c,0xc9,0x8f,0xcd,0x6b,0x02,0xe7,0x4e,0xbb,0xb3,0x62,0xb3,0xda,0xcd,0x03,0x0e, +0xa2,0x48,0xca,0x91,0xf9,0x8a,0xfe,0xa3,0xf0,0x2a,0xbd,0xc6,0x99,0x67,0x76,0x8c, +0x93,0xda,0xc1,0x32,0xb7,0x05,0x64,0x8c,0x30,0x3f,0x98,0xa2,0xe1,0xca,0x7f,0x2e, +0x18,0xa2,0xbf,0xa6,0x6d,0x43,0xe0,0xc7,0xc3,0xed,0x58,0xb1,0xbe,0xf0,0x2f,0x86, +0xaf,0x0b,0x72,0xc6,0x7d,0x22,0xdd,0xc9,0xfa,0xe5,0x2b,0x9e,0xbd,0xfd,0x95,0xbe, +0x0c,0xea,0x0a,0xcb,0x3f,0xc2,0x8f,0x06,0x3e,0xee,0xa4,0x68,0x36,0xca,0x7f,0x30, +0x80,0xd1,0x71,0x72,0x9f,0xcd,0xd5,0x18,0x3d,0x6b,0xfa,0x1a,0xd5,0x7f,0x60,0x8f, +0xd9,0xf7,0x58,0x56,0x13,0xfc,0x29,0xd0,0x23,0xdd,0xd4,0xda,0xc4,0xd0,0x1f,0xcd, +0x18,0x57,0x23,0x77,0xff,0x00,0x04,0xbb,0xfd,0x9b,0x2e,0xd9,0x9b,0xfe,0x15,0xfc, +0x90,0x33,0x73,0x98,0x75,0xbb,0xf1,0xfa,0x79,0xf8,0x1f,0x95,0x3b,0x87,0x29,0xf8, +0x27,0x45,0x7e,0xe5,0xeb,0x3f,0xf0,0x49,0x4f,0xd9,0xef,0x53,0x8c,0xad,0xae,0x91, +0xad,0xe9,0x07,0xb3,0x5a,0x6b,0x12,0xb9,0x1f,0xf7,0xf7,0x7d,0x71,0xd7,0xbf,0xf0, +0x46,0x0f,0x83,0x73,0xb9,0x6b,0x7f,0x14,0xf8,0xd6,0xdb,0x3f,0xc3,0xf6,0xcb,0x47, +0x03,0xf3,0xb6,0xcf,0xeb,0x45,0xc3,0x94,0xfc,0x65,0xa2,0xbf,0x5f,0xb5,0x5f,0xf8, +0x22,0x97,0xc3,0xc9,0x50,0x0d,0x37,0xe2,0x0f,0x89,0xed,0x5f,0xd6,0xea,0x1b,0x79, +0xc7,0xe4,0xa8,0x95,0xc8,0xea,0x7f,0xf0,0x44,0x58,0x49,0x3f,0xd9,0xdf,0x16,0x9d, +0x7d,0x05,0xd6,0x85,0x9f,0xd5,0x67,0x14,0x5c,0x56,0x67,0xe5,0x7d,0x48,0x97,0x33, +0x45,0xf7,0x25,0x74,0xff,0x00,0x75,0x88,0xaf,0xd2,0x8b,0xef,0xf8,0x22,0x57,0x8a, +0x63,0xcf,0xd8,0xfe,0x28,0xe9,0x13,0xfa,0x79,0xfa,0x54,0xb1,0x67,0xf2,0x91,0xab, +0x95,0xd4,0xff,0x00,0xe0,0x8c,0x1f,0x16,0xad,0xc9,0xfb,0x0f,0x8b,0x3c,0x27,0x7a, +0x07,0x4f,0x32,0x6b,0x88,0x89,0xff,0x00,0xc8,0x46,0x80,0xb3,0x3e,0x19,0xd3,0xfc, +0x77,0xe2,0x5d,0x25,0x95,0xac,0x7c,0x43,0xaa,0xd9,0x95,0xe4,0x1b,0x7b,0xd9,0x13, +0x1f,0x93,0x57,0x63,0xa7,0x7e,0xd3,0xbf,0x17,0xf4,0x95,0x55,0xb3,0xf8,0xa1,0xe2, +0xfb,0x74,0x5e,0x8a,0x9a,0xdd,0xc8,0x03,0xf0,0xdf,0x5f,0x47,0x5e,0x7f,0xc1,0x20, +0x7e,0x3e,0x5b,0x13,0xe5,0x8f,0x0b,0xdd,0x81,0xd3,0xc9,0xd5,0x58,0x67,0xfe,0xfa, +0x8c,0x57,0x35,0xa9,0xff,0x00,0xc1,0x2b,0xff,0x00,0x68,0xcd,0x3c,0x31,0x8f,0xc2, +0x16,0x77,0xd8,0xff,0x00,0x9f,0x5d,0x5e,0xd8,0xe7,0xe9,0xb9,0xd6,0x80,0xd4,0xf3, +0x8b,0x4f,0xdb,0x7b,0xe3,0xdd,0x96,0x3c,0xaf,0x8b,0x3e,0x29,0x38,0xe9,0xe6,0xdf, +0xb4,0x9f,0xfa,0x16,0x6b,0xa5,0xd3,0x7f,0xe0,0xa3,0xbf,0xb4,0x5e,0x99,0x81,0x1f, +0xc4,0xbb,0xd9,0x80,0xed,0x73,0x69,0x6d,0x2e,0x7f,0xef,0xa8,0xcd,0x56,0xbf,0xff, +0x00,0x82,0x78,0x7e,0xd1,0x3a,0x71,0x3e,0x67,0xc2,0xed,0x52,0x4c,0x7f,0xcf,0x09, +0xed,0xe5,0xff,0x00,0xd0,0x64,0x35,0xcd,0x6a,0x5f,0xb1,0x97,0xc7,0x4d,0x28,0x91, +0x71,0xf0,0x9f,0xc5,0x9c,0x75,0x30,0xe9,0x92,0x4a,0x3f,0x34,0x06,0x80,0xd4,0xf5, +0x8b,0x2f,0xf8,0x2a,0xd7,0xed,0x17,0x68,0xa0,0x3f,0x8a,0x34,0xdb,0xac,0x77,0x9f, +0x46,0xb7,0xe7,0xfe,0xf9,0x51,0x5b,0xf6,0x1f,0xf0,0x57,0xff,0x00,0x8f,0x56,0xa4, +0x79,0xeb,0xe1,0x8b,0xc0,0x3a,0xf9,0xba,0x5b,0x29,0x3f,0xf7,0xcc,0x82,0xbe,0x5b, +0xd4,0xfe,0x04,0xfc,0x49,0xd1,0x5c,0xa5,0xf7,0xc3,0xff,0x00,0x14,0x5a,0x30,0xea, +0x25,0xd1,0xee,0x17,0xff,0x00,0x64,0xae,0x7e,0xf3,0xc1,0x5e,0x21,0xd3,0xce,0x2e, +0xb4,0x1d,0x4e,0xd8,0xff,0x00,0xd3,0x6b,0x39,0x13,0xf9,0xad,0x03,0xd4,0xfb,0xcb, +0x4d,0xff,0x00,0x82,0xd2,0xfc,0x51,0xb7,0x50,0x2f,0x7c,0x15,0xe1,0x5b,0xcf,0x52, +0x82,0xe2,0x23,0xff,0x00,0xa3,0x0d,0x74,0x56,0x5f,0xf0,0x5b,0x5f,0x14,0x2e,0x05, +0xdf,0xc3,0x0d,0x22,0x5f,0x53,0x06,0xa7,0x2a,0x7f,0x34,0x35,0xf9,0xab,0x34,0x12, +0xdb,0xb6,0xd9,0x63,0x78,0x9b,0xd1,0xd4,0x83,0x4c,0xa3,0x40,0xbb,0x3f,0x54,0x74, +0xbf,0xf8,0x2d,0xcd,0xbe,0x40,0xd4,0x7e,0x14,0x4a,0x07,0x73,0x6b,0xad,0x03,0xfa, +0x34,0x35,0xd4,0x58,0xff,0x00,0xc1,0x6b,0xfc,0x07,0x20,0x1f,0x6c,0xf8,0x77,0xe2, +0x38,0x0f,0xfd,0x30,0xb9,0xb7,0x93,0xf9,0x95,0xaf,0xc8,0x6c,0x51,0x45,0x85,0xcc, +0xcf,0xd9,0x9d,0x3b,0xfe,0x0b,0x39,0xf0,0x82,0xe4,0x81,0x77,0xe1,0x8f,0x17,0xd9, +0x67,0xf8,0xbe,0xcd,0x6f,0x20,0x1f,0x94,0xd5,0xd7,0x69,0xdf,0xf0,0x56,0xff,0x00, +0xd9,0xf6,0xf2,0x20,0xd7,0x1a,0x96,0xbd,0xa7,0xb1,0xfe,0x19,0xf4,0x99,0x18,0x8f, +0xfb,0xe0,0xb0,0xaf,0xc3,0x8a,0xb5,0xa4,0xd8,0xbe,0xa7,0xaa,0xd9,0xd9,0xc4,0xbb, +0xa5,0xb8,0x99,0x21,0x50,0x3b,0x96,0x60,0x07,0xf3,0xa2,0xc3,0xb9,0xfd,0x3f,0xe8, +0x3a,0xd5,0xb7,0x88,0xf4,0x4d,0x3f,0x56,0xb3,0x2e,0x6c,0xef,0xed,0xe3,0xba,0x84, +0xc8,0xa5,0x58,0xa3,0xa8,0x65,0xca,0x9e,0x41,0xc1,0x1c,0x1a,0xbf,0x55,0x34,0xab, +0x18,0xf4,0xcd,0x32,0xd2,0xce,0x14,0x11,0xc5,0x6f,0x0a,0x44,0x88,0x3a,0x28,0x55, +0x00,0x0f,0xd2,0xad,0xd4,0x96,0x14,0x51,0x45,0x00,0x72,0x3f,0x14,0xe7,0xfb,0x3f, +0x83,0x6f,0x4f,0xa8,0xc5,0x7c,0x0d,0xe2,0x29,0x37,0xdf,0xdd,0x37,0xab,0x9a,0xfb, +0x9b,0xe3,0x65,0xcf,0x91,0xe0,0xc9,0x87,0xf7,0x8e,0x3f,0x4a,0xf8,0x43,0x5a,0x7d, +0xd3,0x4e,0xde,0xac,0x6b,0xe0,0x33,0xe7,0x7c,0x54,0x23,0xd9,0x1f,0x01,0xc4,0xf3, +0xb2,0x48,0xf1,0x4f,0x1a,0x42,0x35,0x2f,0x88,0x9e,0x12,0xb1,0x64,0xf3,0x16,0xe7, +0x5a,0xb2,0x84,0xa6,0x33,0xb8,0x34,0xe8,0x08,0xfc,0x8d,0x7e,0xcc,0xa0,0x0a,0xa1, +0x40,0xc0,0x1c,0x57,0xe3,0xef,0x87,0xac,0x9f,0x5c,0xfd,0xa4,0xfe,0x19,0x59,0x2f, +0x3b,0xbc,0x47,0x67,0x26,0x3d,0x92,0x40,0xe7,0xff,0x00,0x40,0xaf,0xd8,0x31,0x5f, +0x57,0x97,0x46,0xd4,0x11,0xd7,0xc2,0x71,0xe5,0xcb,0xef,0xdd,0xb1,0x68,0xa2,0x8a, +0xf5,0x0f,0xb4,0x3f,0x3c,0xbf,0x6b,0x4f,0x07,0xde,0xfc,0x28,0xf8,0xc1,0x3e,0xbf, +0x6f,0x19,0x5d,0x0b,0xc4,0x4d,0xf6,0x95,0x78,0xc6,0x04,0x73,0x80,0x04,0xaa,0x7d, +0xc9,0xf9,0xff,0x00,0xe0,0x47,0xd2,0xb9,0x0d,0x2b,0xc6,0x12,0x5d,0xc4,0xaf,0x15, +0xeb,0xe0,0x8e,0xcf,0x5f,0xa1,0xbf,0x13,0xfe,0x1a,0x68,0xdf,0x15,0xfc,0x21,0x77, +0xe1,0xfd,0x6e,0x0f,0x36,0xda,0x61,0xba,0x39,0x57,0x1b,0xe0,0x90,0x0f,0x96,0x44, +0x3d,0x88,0xcf,0xe3,0xc8,0x3c,0x1a,0xfc,0xed,0xf8,0x9f,0xfb,0x2e,0xf8,0xe3,0xe1, +0x16,0xa9,0x33,0xdb,0xac,0x97,0xda,0x46,0xec,0xc3,0x7f,0x6e,0xa4,0xc6,0xc3,0x3c, +0x06,0x1f,0xc2,0x7d,0x8f,0xe1,0x9a,0xf9,0x3c,0xcb,0x2d,0x84,0xe4,0xea,0x6c,0x7e, +0x4f,0x9d,0xe5,0x78,0x9c,0x16,0x22,0x58,0xac,0x22,0x6e,0x13,0x77,0x69,0x74,0x66, +0xfc,0x3e,0x28,0xd4,0x23,0xe6,0x3b,0xf9,0x47,0xfc,0x0e,0xaf,0x43,0xe3,0x9d,0x6e, +0x1f,0xbb,0xa9,0x4b,0xf8,0xb5,0x78,0xb9,0xb9,0xf1,0x3e,0x9f,0xf2,0x4d,0x68,0x5c, +0x8e,0xf8,0xe4,0xd2,0x8f,0x15,0xeb,0x11,0x7d,0xfb,0x09,0x3f,0x23,0x5f,0x35,0xf5, +0x19,0xaf,0x86,0x4b,0xef,0x3c,0x48,0xe2,0x71,0xd1,0x5f,0x0c,0xbe,0xf3,0xdd,0x21, +0xf8,0x9f,0xe2,0x38,0x0f,0xcb,0xa8,0xb9,0xad,0x1b,0x7f,0x8c,0xfe,0x26,0xb7,0xe9, +0x7a,0xcd,0xf5,0xaf,0x9f,0x57,0xc7,0x97,0x91,0xfd,0xfb,0x49,0x57,0xf0,0x35,0x22, +0x7c,0x46,0x2b,0xf7,0xe2,0x90,0x1f,0x71,0x4d,0x61,0x71,0x31,0xf8,0x64,0xfe,0xf3, +0x55,0x99,0x63,0x61,0xba,0x91,0xf4,0x94,0x1f,0xb4,0x1f,0x8a,0x21,0xc7,0xef,0xf3, +0xf8,0xd6,0xa5,0xbf,0xed,0x33,0xe2,0x38,0xb1,0xbc,0x96,0xc7,0xbd,0x7c,0xc2,0x9f, +0x12,0x60,0xfe,0x2d,0xc3,0xf0,0xab,0x31,0xfc,0x44,0xb4,0x60,0x32,0xff,0x00,0xa5, +0x5a,0x58,0xf8,0xed,0x37,0xf7,0x9b,0x47,0x3c,0xc5,0x43,0x79,0x4b,0xee,0x3e,0xa8, +0xb5,0xfd,0xaa,0x75,0x98,0x88,0xf3,0x22,0xdc,0x3f,0x3a,0xd5,0xb7,0xfd,0xac,0xae, +0x86,0x3c,0xcb,0x6c,0xfa,0xfc,0xa2,0xbe,0x4c,0x8f,0xc7,0x96,0x4d,0xff,0x00,0x2d, +0x16,0xac,0xa7,0x8c,0xac,0x9f,0x1f,0xbd,0x43,0xf8,0xd5,0xac,0x46,0x63,0x0f,0xb4, +0xcd,0xe3,0xc4,0x98,0x88,0xef,0x3f,0xc0,0xfa,0xfe,0xd7,0xf6,0xb2,0x84,0xe3,0xce, +0xb6,0xff,0x00,0xc7,0x6b,0x52,0xdb,0xf6,0xab,0xd2,0xe4,0x23,0xcc,0x80,0x0f,0xc0, +0xd7,0xc6,0x69,0xe2,0x8b,0x37,0xe9,0x2a,0xfe,0x06,0xa7,0x4d,0x7a,0xd5,0xfa,0x38, +0x3f,0x8d,0x52,0xcc,0x73,0x18,0x6e,0xff,0x00,0x03,0xaa,0x3c,0x51,0x5b,0xf9,0x91, +0xf6,0xdd,0xbf,0xed,0x3b,0xe1,0xe9,0x00,0xde,0x30,0x4f,0xfb,0x55,0xa9,0x6d,0xfb, +0x43,0xf8,0x66,0x7c,0x66,0x5d,0xbf,0xf0,0x21,0x5f,0x0a,0xae,0xad,0x6e,0xdd,0x1c, +0x54,0x83,0x50,0x84,0xf4,0x93,0xf5,0xad,0x16,0x73,0x8f,0x8e,0xf6,0xfb,0x8e,0xb8, +0x71,0x45,0x4e,0xb6,0x3e,0xf8,0xb7,0xf8,0xdf,0xe1,0x99,0xc8,0xc5,0xd0,0x1f,0x88, +0xad,0x28,0x3e,0x2a,0xf8,0x72,0x71,0x91,0x7e,0xa3,0xf2,0xaf,0xcf,0xa5,0xbf,0x51, +0xf7,0x66,0x23,0xe8,0x6a,0x64,0xd4,0xe4,0x5f,0xbb,0x70,0xc3,0xfe,0x05,0x5a,0xac, +0xfb,0x14,0xbe,0x28,0x2f,0xc4,0xeb,0x8f,0x13,0xcb,0xac,0x51,0xfa,0x19,0x17,0x8f, +0xb4,0x29,0xbe,0xee,0xa1,0x1f,0xe7,0x57,0x23,0xf1,0x4e,0x95,0x2f,0xdd,0xbe,0x84, +0xff,0x00,0xc0,0xab,0xf3,0xbe,0x3d,0x6e,0xf1,0x3e,0xe5,0xe4,0xa3,0xe8,0xf5,0x66, +0x3f,0x15,0xea,0xb1,0x11,0xb7,0x50,0x9b,0xfe,0xfb,0x35,0xb2,0xe2,0x1a,0x8b,0xe2, +0xa7,0xf8,0x9d,0x51,0xe2,0x58,0x3d,0xe0,0x7e,0x88,0xa6,0xb1,0x63,0x27,0xdd,0xbb, +0x88,0xff,0x00,0xc0,0xc5,0x4a,0xb7,0x90,0x3f,0xdd,0x99,0x0f,0xd1,0x85,0x7e,0x7b, +0x43,0xe3,0xfd,0x7a,0x2f,0xbb,0xa8,0xcb,0xf9,0xd5,0xf8,0x3e,0x2b,0x78,0x8e,0x0c, +0x62,0xf9,0xcf,0xd4,0xd6,0xeb,0x88,0xa3,0xf6,0xa9,0xbf,0xbc,0xe8,0x8f,0x11,0xd0, +0x7b,0xc5,0x9f,0x7f,0x09,0x14,0xff,0x00,0x10,0xfc,0xe9,0x73,0xef,0x5f,0x08,0xc1, +0xf1,0xbf,0xc4,0xd0,0x7f,0xcb,0xd1,0x6f,0xc4,0xd6,0x9d,0xb7,0xed,0x11,0xe2,0x58, +0x3a,0xcb,0x9f,0xf8,0x11,0xad,0xe3,0xc4,0x34,0x1e,0xf0,0x67,0x44,0x78,0x83,0x0a, +0xf7,0xb9,0xf6,0xe0,0x34,0x66,0xbe,0x37,0xb6,0xfd,0xa7,0x35,0xf8,0x71,0xbf,0x2d, +0xf8,0xd6,0xad,0xbf,0xed,0x57,0xaa,0x2f,0xfa,0xc8,0x49,0x1f,0x85,0x6d,0x1c,0xfb, +0x08,0xf7,0xbf,0xdc,0x6f,0x1c,0xf3,0x06,0xfe,0xd1,0xf5,0x9e,0x68,0x07,0x35,0xf3, +0x0d,0xbf,0xed,0x65,0x28,0xff,0x00,0x59,0x6f,0x9f,0xf8,0x0e,0x6b,0x52,0xdb,0xf6, +0xb1,0xb5,0x38,0xf3,0x6d,0xc0,0xfc,0x2b,0xa2,0x39,0xd6,0x09,0xfd,0xaf,0xc0,0xe9, +0x8e,0x6d,0x83,0x97,0xdb,0x3e,0x8b,0xa2,0xbc,0x26,0x0f,0xda,0xa3,0x47,0x7c,0x07, +0x88,0x03,0xdf,0xad,0x6a,0x5b,0x7e,0xd2,0xde,0x1e,0x98,0x0d,0xe4,0x2f,0xfc,0x0a, +0xb7,0x8e,0x6b,0x83,0x97,0xfc,0xbc,0x46,0xf1,0xc7,0xe1,0xa5,0xb4,0xd1,0xec,0x54, +0x57,0x98,0xdb,0xfe,0xd0,0x3e,0x19,0x9f,0xfe,0x5b,0x05,0xff,0x00,0x81,0x56,0x9c, +0x1f,0x19,0xfc,0x35,0x36,0x3f,0xd3,0x00,0xfc,0x45,0x74,0x47,0x1d,0x86,0x96,0xd5, +0x17,0xde,0x6e,0xb1,0x34,0x65,0xb4,0xd1,0xdd,0xd1,0x5c,0xa4,0x1f,0x13,0xfc,0x3d, +0x38,0x18,0xbe,0x41,0xf5,0x35,0x76,0x2f,0x1c,0xe8,0x93,0x7d,0xdb,0xf8,0x8f,0xe3, +0x5b,0x2c,0x45,0x29,0x6d,0x25,0xf7,0x9a,0x2a,0xb4,0xde,0xd2,0x46,0xf5,0x15,0x97, +0x1f,0x89,0x74,0xc9,0x47,0xcb,0x7d,0x09,0xff,0x00,0x81,0x55,0x94,0xd5,0xac,0xe4, +0xfb,0xb7,0x51,0x1f,0xf8,0x10,0xad,0x54,0xe2,0xf6,0x65,0xa9,0x27,0xb3,0x2d,0xd1, +0x51,0x0b,0xa8,0x5b,0xa4,0xa8,0x7f,0xe0,0x42,0x9e,0x1d,0x58,0x64,0x10,0x7e,0x86, +0xaa,0xe8,0xab,0x8e,0xa2,0x93,0x34,0x66,0x98,0x0b,0x45,0x26,0x45,0x19,0xa0,0x05, +0xa2,0x93,0x34,0xb4,0x00,0x51,0x45,0x14,0x00,0x51,0x45,0x14,0x00,0x51,0x45,0x14, +0x00,0x51,0x45,0x14,0x00,0x51,0x45,0x14,0x00,0x51,0x45,0x14,0x00,0x51,0x45,0x14, +0x00,0x51,0x45,0x14,0x00,0x94,0x6d,0x06,0x96,0x8a,0x00,0x4c,0x51,0x8a,0x5a,0x28, +0x01,0x31,0x4d,0x31,0xa1,0x04,0x15,0x04,0x1e,0xb9,0x14,0xfa,0x28,0x03,0x1e,0xfb, +0xc1,0xba,0x06,0xa9,0x9f,0xb6,0x68,0x7a,0x6d,0xde,0x7a,0xf9,0xf6,0x91,0xbe,0x7f, +0x31,0x5c,0xe5,0xf7,0xc0,0x6f,0x86,0x7a,0x9e,0xef,0xb5,0xfc,0x3c,0xf0,0xad,0xc9, +0x6e,0xa6,0x5d,0x16,0xd9,0x89,0xfc,0x4a,0x57,0x77,0x45,0x00,0x78,0xd6,0xa9,0xfb, +0x1a,0x7c,0x0b,0xd6,0x15,0xc5,0xcf,0xc2,0x6f,0x09,0x12,0xfd,0x5a,0x2d,0x2a,0x28, +0x9b,0xfe,0xfa,0x40,0x08,0xae,0x2e,0xfb,0xfe,0x09,0xb1,0xfb,0x37,0x5f,0xbb,0xb4, +0x9f,0x0c,0xad,0x23,0x2d,0xd7,0xc8,0xd4,0x6f,0x22,0x03,0xe8,0x16,0x60,0x05,0x7d, +0x33,0x45,0x00,0x7c,0x97,0x7f,0xff,0x00,0x04,0xb0,0xfd,0x9b,0xaf,0x22,0x65,0x8f, +0xc1,0x17,0x56,0x6c,0x7f,0x8e,0x0d,0x6e,0xf4,0x91,0xff,0x00,0x7d,0x4a,0xc3,0xf4, +0xac,0x5d,0x0f,0xfe,0x09,0x3f,0xf0,0x43,0xc3,0x5e,0x2b,0xd2,0x3c,0x41,0xa7,0x37, +0x89,0x21,0xba,0xd2,0xef,0x61,0xbe,0x86,0x17,0xd4,0x52,0x48,0x59,0xe3,0x70,0xe1, +0x58,0x34,0x44,0x95,0x25,0x40,0x23,0x3d,0x3b,0xd7,0xd9,0xd4,0x50,0x2b,0x05,0x14, +0x51,0x40,0xc2,0x8a,0x28,0xa0,0x0f,0x29,0xfd,0xa1,0x2e,0x7c,0x9f,0x0a,0x05,0xce, +0x32,0x58,0xfe,0x95,0xf0,0xf6,0xaa,0xfc,0x48,0x7d,0xcd,0x7d,0x97,0xfb,0x4b,0xdc, +0xf9,0x7a,0x24,0x29,0x9f,0xe1,0x3c,0x57,0xc5,0xda,0xb3,0xe2,0x27,0x3f,0x5a,0xfc, +0xeb,0x38,0x7c,0xd8,0xfb,0x76,0x48,0xfc,0xd3,0x8a,0x27,0xef,0xdb,0xc8,0xe4,0x3e, +0x04,0xda,0x0d,0x63,0xf6,0xc8,0xf8,0x6d,0x01,0xc9,0xf2,0xaf,0xe6,0xb9,0xe3,0xfe, +0x99,0xdb,0xca,0xc3,0xf9,0x57,0xeb,0x58,0xaf,0xcb,0x1f,0xd8,0xe7,0x4f,0x6d,0x5f, +0xf6,0xce,0xd0,0xa5,0x03,0x29,0x61,0xa7,0xdf,0x5d,0x37,0xb0,0xf2,0xbc,0xb1,0xfa, +0xc8,0x2b,0xf5,0x38,0x77,0xaf,0xb7,0xc1,0xab,0x51,0x47,0xd1,0xf0,0xd4,0x39,0x32, +0xca,0x7e,0x62,0xd1,0x45,0x15,0xdc,0x7d,0x40,0x98,0xa6,0xc9,0x0a,0x4a,0xa5,0x5d, +0x43,0xa1,0xe0,0xab,0x0c,0x83,0x4f,0xa2,0x80,0x38,0xad,0x6b,0xe0,0xcf,0x83,0x35, +0xf9,0x1a,0x4b,0xbd,0x02,0xd7,0xcc,0x61,0x82,0xd0,0x83,0x17,0xe8,0xa4,0x0a,0xe5, +0xaf,0x7f,0x65,0x8f,0x01,0x5d,0x9c,0xad,0x95,0xc5,0xbf,0xb4,0x53,0x7f,0xf1,0x40, +0xd7,0xaf,0x51,0x5c,0xd2,0xc3,0x51,0x96,0xf0,0x47,0x24,0xb0,0x98,0x79,0xbb,0xca, +0x9a,0xfb,0x8f,0x09,0xba,0xfd,0x8f,0x3c,0x13,0x36,0x4a,0x4d,0xa8,0x46,0x7d,0xdd, +0x08,0xff,0x00,0xd0,0x2b,0x02,0xff,0x00,0xf6,0x26,0xd0,0x27,0xcf,0xd9,0xf5,0x69, +0x22,0x3f,0xf4,0xd2,0xdc,0x3f,0xf2,0x61,0x5f,0x4a,0x51,0xf8,0xd6,0x4f,0x03,0x87, +0x7f,0x60,0xe7,0x79,0x6e,0x16,0x5f,0x63,0xf3,0x3e,0x50,0xbc,0xfd,0x84,0xec,0x64, +0xe6,0x2d,0x6a,0x17,0x3f,0xed,0xda,0x95,0xff,0x00,0xd9,0x8d,0x73,0xd7,0xdf,0xb0, +0x65,0xd9,0x62,0x20,0xbb,0xd3,0x5c,0x76,0x2c,0x59,0x4f,0xfe,0x81,0x5f,0x68,0x62, +0x8c,0x56,0x4f,0x2e,0xa0,0xfa,0x3f,0xbd,0x98,0xbc,0xa7,0x0a,0xfe,0xcb,0xfb,0xd9, +0xf0,0x8d,0xe7,0xec,0x1d,0xae,0x2a,0xb1,0x8d,0x6c,0x65,0x3d,0x82,0x4d,0x8c,0xfe, +0x78,0xae,0x7a,0xfb,0xf6,0x20,0xf1,0x54,0x07,0xe4,0xd3,0x0b,0x0f,0xfa,0x67,0x70, +0x87,0xff,0x00,0x66,0xaf,0xd0,0xfc,0x51,0x8a,0x87,0x96,0xd3,0xe9,0x27,0xf7,0x9c, +0xf2,0xc8,0xf0,0xb2,0xef,0xf8,0x7f,0x91,0xf9,0xa7,0x7b,0xfb,0x1f,0x78,0xc6,0xd4, +0x90,0xba,0x46,0xa0,0x4f,0xfb,0x1f,0x30,0xfd,0x2b,0x0a,0xef,0xf6,0x69,0xf1,0x85, +0x91,0x3b,0xb4,0xed,0x4e,0x3c,0x7a,0xdb,0xb7,0xf8,0x57,0xea,0x4e,0x29,0x0a,0xe6, +0xa1,0xe5,0xab,0xa4,0xdf,0xe0,0x72,0xcb,0x87,0x70,0xd2,0xeb,0xf8,0x23,0xf2,0x7a, +0xef,0xe0,0xd7,0x8a,0x6c,0x72,0x59,0x6e,0xa3,0x03,0xfb,0xf1,0x11,0x59,0xef,0xe0, +0x3f,0x13,0xdb,0x74,0x91,0xce,0x3d,0x54,0xd7,0xeb,0x83,0x44,0xae,0x30,0xc0,0x11, +0xe8,0x45,0x55,0x9f,0x45,0xb0,0xba,0xff,0x00,0x5d,0x65,0x6f,0x30,0xff,0x00,0x6e, +0x25,0x3f,0xd2,0xb2,0x79,0x6c,0xba,0x4f,0xf0,0x38,0xe5,0xc2,0xf8,0x79,0x76,0xfb, +0xbf,0xe0,0x9f,0x92,0x6d,0xa0,0x78,0xaa,0xdf,0xdf,0xeb,0x9a,0x88,0xa7,0x8a,0x2d, +0xfe,0xf4,0x3b,0xbe,0x86,0xbf,0x57,0xee,0x3c,0x03,0xe1,0xbb,0xa0,0x7c,0xdd,0x07, +0x4d,0x7c,0xf7,0x36,0xa9,0xfe,0x15,0x97,0x73,0xf0,0x6f,0xc1,0x77,0x79,0xf3,0x3c, +0x3b,0x67,0xff,0x00,0x00,0x52,0x9f,0xc8,0x8a,0xc9,0xe5,0xb5,0x3b,0xa6,0x72,0x4b, +0x84,0xe9,0x74,0xb7,0xe2,0x8f,0xcb,0x31,0xaa,0xf8,0x8a,0x0f,0xbf,0x68,0xc6,0x94, +0x78,0xab,0x58,0x8b,0xef,0xd8,0xcb,0xc7,0xfb,0x26,0xbf,0x4d,0xae,0x7f,0x67,0x8f, +0x00,0xdd,0x67,0x3a,0x12,0x46,0x4f,0x74,0x99,0xff,0x00,0xf8,0xaa,0xc5,0xbb,0xfd, +0x94,0xfc,0x09,0x75,0x9d,0xb6,0xf7,0x70,0x67,0xfe,0x79,0xca,0xbf,0xd5,0x4d,0x63, +0x2c,0xb2,0xa7,0xf2,0xc5,0x9c,0xb2,0xe1,0x37,0xd3,0xff,0x00,0x4a,0x67,0xe7,0x32, +0xf8,0xee,0xf6,0x3f,0xbf,0x6b,0x28,0xfc,0x0d,0x4c,0x9f,0x11,0x4a,0x9f,0x9e,0x17, +0x1f,0x85,0x7d,0xf7,0x79,0xfb,0x1c,0x78,0x36,0x7f,0xf5,0x37,0x57,0xd1,0x1f,0xf6, +0x8a,0x37,0xfe,0xca,0x2b,0x02,0xf3,0xf6,0x22,0xd1,0x26,0x72,0x62,0xd6,0x9d,0x17, +0xd1,0xed,0x43,0x1f,0xcf,0x78,0xac,0x1e,0x59,0x3e,0xb4,0x97,0xde,0x73,0x4b,0x85, +0xab,0xaf,0x86,0xff,0x00,0x7a,0x3e,0x2b,0x4f,0x89,0x10,0xff,0x00,0x10,0x65,0xfa, +0x8a,0xb1,0x1f,0xc4,0x4b,0x46,0xea,0xf8,0xaf,0xac,0x2f,0x7f,0x61,0x2b,0x49,0x01, +0xf2,0x35,0x88,0x1d,0xbb,0x09,0x2d,0x8a,0xff,0x00,0x53,0x5c,0xf5,0xe7,0xec,0x19, +0xa8,0x1f,0xf5,0x77,0x5a,0x63,0x8f,0xf7,0x98,0x7f,0xec,0xb5,0x83,0xcb,0x5f,0x5a, +0x4c,0xe7,0x97,0x0e,0xe2,0xe3,0xb3,0x97,0xe0,0xcf,0x9e,0xa3,0xf1,0xed,0x9b,0xff, +0x00,0xcb,0x45,0x15,0x66,0x3f,0x19,0xd9,0x3f,0xfc,0xb5,0x4f,0xce,0xbd,0x7a,0xfb, +0xf6,0x11,0xd7,0xe3,0x62,0x23,0x86,0xce,0x61,0xeb,0x1c,0xc0,0x67,0xf3,0xc5,0x73, +0xf7,0x9f,0xb1,0x27,0x8b,0x21,0xdd,0xb3,0x4a,0x76,0x03,0xfe,0x79,0xdc,0x21,0xff, +0x00,0xd9,0xab,0x09,0x65,0xb1,0x5b,0xd3,0x92,0xf9,0x1c,0xd2,0xc9,0x31,0xd1,0xea, +0xff,0x00,0xf0,0x13,0x89,0x4f,0x14,0xd9,0xbf,0xfc,0xb5,0x4f,0xfb,0xea,0xa7,0x4d, +0x7e,0xd5,0xff,0x00,0x8d,0x4f,0xe2,0x2b,0x4a,0xf7,0xf6,0x43,0xf1,0x8d,0xa0,0x2d, +0xfd,0x8f,0xa8,0x81,0xe9,0x1a,0x16,0xfe,0x42,0xb0,0xef,0x7f,0x66,0xdf,0x17,0x58, +0xf2,0xda,0x76,0xa7,0x17,0xfb,0xf6,0xed,0xfe,0x15,0xcf,0x2c,0xbe,0x9a,0xee,0xbe, +0x47,0x3c,0xb2,0xdc,0x74,0x3a,0xfe,0x0c,0xbe,0xba,0xb5,0xbb,0x7f,0x18,0xa9,0x17, +0x51,0x80,0xff,0x00,0x18,0xae,0x46,0xe7,0xe1,0x07,0x89,0xac,0x8e,0x1b,0xed,0x28, +0x47,0x67,0x88,0xd5,0x17,0xf0,0x2f,0x89,0xad,0x8f,0x12,0x3f,0x1e,0xaa,0x6b,0x17, +0x81,0xa5,0xd2,0x46,0x2f,0x0d,0x8d,0x8f,0x63,0xd0,0x16,0xfa,0x23,0xd2,0x4f,0xd6, +0xa5,0x5b,0xdc,0x7d,0xd9,0x88,0xfc,0x6b,0xcc,0xdb,0x42,0xf1,0x4d,0xbe,0x79,0x27, +0xeb,0x9a,0x66,0xcf,0x13,0x41,0xf7,0xa2,0x2d,0x8f,0x43,0x51,0xfd,0x9f,0x17,0xb4, +0x85,0xc9,0x8d,0x8f,0xd8,0xfc,0x4f,0x55,0x4d,0x52,0x74,0xfb,0xb7,0x4e,0x3e,0x8d, +0x56,0x23,0xd7,0xef,0xe3,0xfb,0x97,0xb2,0x8f,0xa3,0x1a,0xf2,0x1f,0xed,0x5f,0x10, +0xc2,0x3e,0x6b,0x47,0x3f,0x4a,0x51,0xe2,0x9d,0x62,0x3f,0xbf,0x67,0x27,0xfd,0xf3, +0x51,0xfd,0x9d,0x2e,0x92,0x41,0xed,0x31,0xb0,0xde,0x9b,0xfb,0xcf,0x67,0x8f,0xc6, +0x1a,0xc4,0x5f,0x77,0x50,0x97,0xfe,0xfa,0xab,0xb0,0x7c,0x44,0xd7,0xe0,0xfb,0xba, +0x84,0x9f,0x8d,0x78,0x7a,0xf8,0xea,0xf2,0x3f,0xf5,0x96,0xb2,0x8f,0xf8,0x09,0xa9, +0x53,0xe2,0x29,0x5f,0xbf,0x14,0x8b,0xf5,0x14,0x96,0x06,0xbc,0x7e,0x17,0xf8,0x94, +0xb1,0xd8,0xb8,0x6f,0x19,0x23,0xde,0x60,0xf8,0xb7,0xe2,0x48,0x3f,0xe5,0xf4,0x9f, +0xad,0x69,0x43,0xf1,0xd7,0xc4,0xd0,0x81,0x8b,0x8c,0xe3,0xdc,0xd7,0xcf,0x91,0xfc, +0x48,0x87,0xb8,0x65,0xfc,0x2a,0xcc,0x7f,0x11,0x2d,0x5b,0xab,0xe3,0xea,0x2a,0x95, +0x0c,0x5c,0x7e,0x19,0x3f,0xbc,0xd5,0x67,0x18,0x98,0x6e,0xe4,0xbe,0x47,0xd1,0xb6, +0xbf,0xb4,0x67,0x88,0xe0,0x00,0x17,0xcf,0xd0,0xd6,0xa5,0xbf,0xed,0x3f,0xae,0x46, +0x7e,0x70,0xc7,0xf1,0xaf,0x99,0xe3,0xf1,0xed,0x9b,0x7f,0xcb,0x41,0xf8,0xd5,0x98, +0xfc,0x69,0x66,0xf8,0xfd,0xea,0x7e,0x75,0x4a,0x58,0xf8,0x6d,0x26,0x6f,0x1e,0x20, +0xaf,0x1f,0xb6,0xfe,0xe3,0xea,0x5b,0x7f,0xda,0xb3,0x50,0x4c,0x6f,0x84,0x93,0xf4, +0x15,0xa9,0x6b,0xfb,0x58,0x37,0x1e,0x6c,0x39,0xff,0x00,0x80,0xd7,0xc9,0xd1,0xf8, +0xae,0xd1,0xff,0x00,0xe5,0xa2,0x7e,0x75,0x3a,0x78,0x86,0xd5,0xfa,0x3a,0xfe,0x75, +0x6b,0x19,0x98,0xc3,0xed,0x33,0xa6,0x3c,0x4d,0x59,0x7f,0xcb,0xc4,0x7d,0x7f,0x6f, +0xfb,0x56,0xd9,0x39,0xc3,0xc2,0x07,0xd4,0x56,0xad,0xb7,0xed,0x45,0xa2,0xc9,0x8f, +0x31,0x00,0xfc,0x6b,0xe3,0x15,0xd6,0x2d,0xdb,0xf8,0x87,0xe7,0x52,0x2e,0xa5,0x03, +0x7f,0x1e,0x2b,0x45,0x9a,0xe6,0x11,0xdd,0xfe,0x07,0x5c,0x38,0x9a,0xb7,0xf3,0x26, +0x7d,0xbb,0x6d,0xfb,0x48,0x78,0x7a,0x7c,0x6e,0x60,0xbf,0xf0,0x2a,0xd4,0x83,0xe3, +0xdf,0x86,0x66,0xc7,0xef,0xc0,0xff,0x00,0x81,0x0a,0xf8,0x48,0x5f,0x44,0x7a,0x3f, +0xeb,0x4f,0x5b,0xc5,0xea,0x25,0xc7,0xe3,0x5a,0x2c,0xef,0x1b,0x1d,0xd2,0xfb,0x8e, +0xc8,0xf1,0x35,0x5e,0xa9,0x33,0xef,0xd8,0x3e,0x30,0xf8,0x6e,0x7c,0x62,0xec,0x0f, +0xc4,0x55,0xe8,0x7e,0x25,0x78,0x7e,0x7c,0x6d,0xbe,0x4f,0xc6,0xbf,0x3e,0x56,0xf9, +0x86,0x31,0x3b,0x7f,0xdf,0x55,0x3a,0x6a,0xd7,0x51,0xfd,0xcb,0xb9,0x07,0xd1,0xab, +0x65,0xc4,0x18,0x85,0xbc,0x11,0xd5,0x1e,0x25,0x7d,0x60,0x7e,0x86,0x47,0xe3,0x4d, +0x16,0x5c,0x62,0xfe,0x2f,0xc4,0xd5,0xa8,0xfc,0x45,0xa6,0xcb,0xf7,0x6f,0x61,0x3f, +0xf0,0x2a,0xfc,0xf1,0x8f,0xc4,0x7a,0x8c,0x7f,0x76,0xf6,0x51,0xff,0x00,0x02,0xab, +0x91,0x78,0xdf,0x5a,0x87,0xee,0xea,0x12,0x7e,0x75,0xb2,0xe2,0x29,0xaf,0x8a,0x9f, +0xe2,0x74,0x47,0x89,0x21,0xd6,0x07,0xe8,0x52,0xea,0x96,0x8f,0xf7,0x6e,0x62,0x3f, +0x46,0x15,0x2a,0xdc,0x44,0xdd,0x24,0x43,0xf4,0x22,0xbf,0x3f,0x20,0xf8,0x97,0xe2, +0x08,0x08,0xdb,0x7c,0xe7,0xeb,0x57,0xe1,0xf8,0xc5,0xe2,0x48,0x7f,0xe5,0xec,0x9a, +0xde,0x3c,0x45,0x0f,0xb5,0x4d,0x9d,0x31,0xe2,0x2c,0x3b,0xde,0x2c,0xfb,0xdc,0x3a, +0x9e,0x8c,0x0f,0xe3,0x4b,0x9a,0xf8,0x66,0xdf,0xe3,0xdf,0x89,0x2d,0xff,0x00,0xe5, +0xb6,0x7f,0x13,0x5a,0x96,0xdf,0xb4,0x87,0x88,0x21,0xc6,0xe6,0x2d,0xf8,0x9a,0xdd, +0x71,0x0e,0x1d,0xef,0x16,0x8d,0xe3,0x9f,0xe1,0x1e,0xec,0xfb,0x4b,0x38,0xa3,0x22, +0xbe,0x42,0xb7,0xfd,0xa8,0xb5,0x98,0xf1,0xb9,0x0f,0xe7,0x9a,0xd4,0xb5,0xfd,0xab, +0x2e,0xd7,0x1e,0x64,0x44,0xfe,0x15,0xba,0xcf,0xb0,0x8f,0x7b,0xfd,0xc7,0x44,0x73, +0xac,0x1c,0xbe,0xd1,0xf5,0x4e,0x45,0x15,0xf3,0x55,0xb7,0xed,0x5c,0xac,0x47,0x99, +0x00,0x03,0xfd,0xda,0xd5,0xb7,0xfd,0xaa,0x74,0xe6,0xc6,0xf8,0x97,0xf2,0x35,0xbc, +0x73,0x9c,0x14,0xbe,0xd9,0xd1,0x1c,0xd3,0x09,0x2d,0xa6,0x8f,0xa0,0x33,0x4b,0x5e, +0x25,0x6b,0xfb,0x4e,0x68,0xb2,0xfd,0xf0,0x8b,0xf8,0x9a,0xd5,0xb7,0xfd,0xa2,0xfc, +0x3b,0x36,0x01,0x60,0x0f,0xfb,0xd5,0xd1,0x1c,0xcf,0x07,0x2d,0xaa,0x23,0x75,0x8e, +0xc3,0xcb,0x69,0xa3,0xd6,0x28,0xaf,0x3a,0x83,0xe3,0x9f,0x86,0xe6,0xc7,0xfa,0x40, +0x5c,0xff,0x00,0xb4,0x2b,0x46,0xdf,0xe2,0xdf,0x87,0x6e,0x31,0x8b,0xb5,0x1f,0x52, +0x2b,0x75,0x8d,0xc3,0x4b,0x6a,0x8b,0xef,0x36,0x58,0x8a,0x2f,0x69,0x23,0xb4,0xa2, +0xb9,0xa8,0xfe,0x22,0xe8,0x12,0xfd,0xdb,0xf4,0xcd,0x5b,0x8b,0xc6,0x1a,0x44,0xdf, +0x76,0xfa,0x2f,0xc4,0xd6,0xca,0xbd,0x29,0x6d,0x25,0xf7,0x9a,0x2a,0x90,0x7b,0x33, +0x6a,0x8a,0xce,0x4f,0x10,0x69,0xd2,0x7d,0xdb,0xc8,0x5b,0xfe,0x05,0x56,0x13,0x51, +0xb6,0x7e,0x97,0x11,0x1f,0xf8,0x18,0xad,0x14,0xe2,0xf6,0x65,0x73,0x2e,0xe5,0x9a, +0x2a,0x35,0xb8,0x89,0xfe,0xec,0x88,0x7e,0x8d,0x4f,0xdc,0x3d,0x45,0x55,0xca,0x16, +0x8a,0x29,0x33,0x4c,0x05,0xa2,0x93,0x34,0x66,0x80,0x16,0x8a,0x4a,0x33,0x40,0x0b, +0x45,0x14,0x94,0x01,0xf3,0xdf,0xed,0x45,0x77,0xb6,0xde,0x38,0xf3,0xd2,0x3c,0x57, +0xc7,0x5e,0x24,0xbc,0x5b,0x7b,0x39,0x58,0x9c,0x61,0x4d,0x7d,0x53,0xfb,0x54,0x5f, +0x88,0xee,0x4a,0x93,0x8c,0x28,0x02,0xbe,0x1a,0xf8,0x97,0xe2,0x95,0xb6,0xb3,0x78, +0x95,0xf2,0xc4,0x73,0xcd,0x7e,0x79,0x88,0xa6,0xeb,0xe6,0x53,0xf2,0xb1,0xf9,0x1f, +0x13,0xd4,0x73,0xc4,0xaa,0x31,0xdd,0x9e,0xad,0xff,0x00,0x04,0xe8,0xd3,0xe6,0xd6, +0x3f,0x69,0x8f,0x14,0xea,0xe1,0x37,0xda,0x69,0xfe,0x1f,0x92,0x06,0x7c,0xfd,0xd9, +0x25,0xb8,0x8b,0x60,0xfc,0x44,0x4f,0xf9,0x57,0xe9,0x78,0xaf,0x87,0x7f,0xe0,0x96, +0xbe,0x07,0x96,0xcb,0xc1,0x1e,0x34,0xf1,0xa4,0xe0,0x8f,0xed,0xcd,0x42,0x3b,0x3b, +0x70,0xc3,0xac,0x56,0xca,0xd9,0x61,0xf5,0x69,0x98,0x7f,0xc0,0x2b,0xee,0x3a,0xfb, +0xba,0x11,0xe5,0xa6,0x91,0xfa,0x46,0x59,0x43,0xea,0xf8,0x3a,0x74,0xfb,0x20,0xa2, +0x8a,0x2b,0xa0,0xf5,0x02,0x8a,0x28,0xa0,0x02,0x8a,0x28,0xa0,0x02,0x8a,0x28,0xa0, +0x02,0x8a,0x28,0xa0,0x02,0x8a,0x28,0xa0,0x02,0x8a,0x28,0xa0,0x02,0x8a,0x28,0xa0, +0x02,0x8a,0x28,0xa0,0x02,0x8a,0x28,0xa0,0x02,0x93,0x14,0xb4,0x50,0x02,0x62,0x8c, +0x52,0xd1,0x40,0x0d,0x23,0xd2,0x94,0x0a,0x5a,0x28,0x01,0x31,0x46,0xd1,0x4b,0x45, +0x00,0x46,0xd0,0xa3,0x82,0x19,0x15,0x81,0xec,0x45,0x54,0x9b,0x40,0xd3,0x6e,0x46, +0x26,0xd3,0xed,0x65,0x1f,0xed,0xc2,0xa7,0xfa,0x55,0xfa,0x2a,0x5c,0x53,0xdd,0x12, +0xe2,0x9e,0xe8,0xe7,0x6e,0x7e,0x1e,0x78,0x62,0xf3,0xfd,0x76,0x81,0xa7,0x3f,0xfd, +0xbb,0x20,0xfe,0x42,0xb2,0xee,0x7e,0x0b,0xf8,0x26,0xef,0x3e,0x67,0x87,0x2c,0xc6, +0x7f,0xb8,0xa5,0x3f,0x91,0x15,0xdb,0x51,0x59,0xba,0x34,0x9e,0xf1,0x5f,0x71,0x93, +0xa1,0x4a,0x5b,0xc1,0x7d,0xc8,0xf3,0x2b,0xbf,0xd9,0xc7,0xc0,0x37,0x60,0x8f,0xec, +0x51,0x1f,0xba,0x4c,0xff,0x00,0xd4,0x9a,0xc7,0xba,0xfd,0x93,0xfc,0x09,0x70,0x72, +0xb0,0xdd,0xc3,0xec,0x92,0xaf,0xf5,0x53,0x5e,0xcb,0x45,0x64,0xf0,0x94,0x1f,0xd8, +0x46,0x0f,0x03,0x86,0x7b,0xd3,0x5f,0x71,0xe0,0x37,0xbf,0xb1,0xaf,0x84,0x27,0xcf, +0x91,0x77,0x79,0x11,0x3f,0xdf,0xd8,0xf8,0xfd,0x05,0x61,0x5d,0x7e,0xc3,0xba,0x2c, +0xb9,0xf2,0xf5,0xc6,0x5f,0x4d,0xd6,0x80,0xff,0x00,0xec,0xf5,0xf4,0xdd,0x15,0x9b, +0xc0,0xe1,0xdf,0xd9,0xfc,0xcc,0x9e,0x5b,0x84,0x7f,0x63,0xf3,0x3e,0x46,0xd4,0x3f, +0x61,0x38,0x98,0x9f,0xb3,0x6a,0xd6,0x92,0x0f,0xfa,0x69,0x01,0x4f,0xe5,0x9a,0xe7, +0xef,0x3f,0x60,0xcd,0x49,0x89,0xf2,0xee,0xb4,0xb7,0x1d,0xbe,0x77,0x07,0xff,0x00, +0x40,0xaf,0xb6,0x31,0x46,0x2b,0x37,0x97,0x50,0xe9,0x75,0xf3,0x31,0x79,0x46,0x15, +0xf4,0x7f,0x79,0xf0,0x45,0xff,0x00,0xec,0x29,0xe2,0x18,0x81,0x31,0x5b,0x5a,0x4d, +0x8e,0xd1,0xdc,0x00,0x4f,0xe7,0x8a,0xc0,0xba,0xfd,0x89,0xbc,0x5d,0x10,0x24,0x69, +0x12,0x71,0xfd,0xcb,0x84,0x3f,0xc9,0xab,0xf4,0x5b,0x14,0x98,0x35,0x1f,0xd9,0xb4, +0xfa,0x49,0x9c,0xf2,0xc8,0xf0,0xd2,0xea,0xff,0x00,0x0f,0xf2,0x3f,0x33,0x2f,0xbf, +0x64,0xaf,0x18,0x59,0x96,0x1f,0xd8,0xda,0x96,0x47,0xfc,0xf3,0x8d,0x98,0x7e,0x60, +0x56,0x15,0xdf,0xec,0xe7,0xe2,0xcb,0x30,0x49,0xd3,0xf5,0x38,0xc0,0xea,0x5a,0xdd, +0xb1,0xfc,0xab,0xf5,0x47,0x14,0x9b,0x73,0xd6,0xb3,0x79,0x6f,0x6a,0x8c,0xe5,0x97, +0x0e,0xe1,0xe5,0xd7,0xf0,0x47,0xe4,0xbd,0xcf,0xc2,0x3f,0x11,0xd9,0x83,0x93,0x70, +0x9f,0xef,0x46,0x45,0x51,0x93,0xc0,0xfe,0x25,0xb7,0xe9,0x23,0xf1,0xea,0xa6,0xbf, +0x5c,0xde,0xde,0x39,0x06,0x19,0x15,0x87,0xa3,0x0c,0xd5,0x3b,0x8f,0x0f,0x69,0x77, +0x9f,0xeb,0xf4,0xeb,0x49,0xbf,0xdf,0x81,0x5b,0xf9,0x8a,0xcd,0xe5,0xd3,0xe9,0x3f, +0xc0,0xe3,0x9f,0x0b,0xd0,0x97,0x6f,0xbb,0xfe,0x09,0xf9,0x24,0xda,0x1f,0x8a,0x2d, +0xfb,0x96,0xc7,0xd6,0xa3,0x2b,0xe2,0x58,0x3a,0xc5,0xbb,0xe8,0x6b,0xf5,0x7a,0xe3, +0xe1,0xb7,0x85,0x6e,0xb3,0xe6,0xf8,0x7b,0x4d,0x6c,0xf5,0x3f,0x66,0x40,0x7f,0x41, +0x59,0x57,0x5f,0x04,0x7c,0x0f,0x77,0xf7,0xfc,0x3b,0x68,0x3d,0x76,0xee,0x5f,0xe4, +0x6b,0x27,0x96,0xd5,0xee,0x99,0xc7,0x2e,0x14,0xa6,0xf6,0xb7,0xe2,0x7e,0x5a,0xff, +0x00,0x6a,0xf8,0x86,0x1f,0xbd,0x6a,0xc7,0x1e,0x94,0xe1,0xe2,0x9d,0x62,0x2f,0xbf, +0x67,0x27,0xfd,0xf3,0x5f,0xa6,0x37,0x7f,0xb3,0x5f,0x80,0x2e,0xff,0x00,0xe6,0x0c, +0x61,0xff,0x00,0xae,0x73,0x3f,0xf5,0x26,0xb1,0xee,0xbf,0x64,0xbf,0x01,0xdc,0x92, +0x56,0x1b,0xd8,0x7d,0x92,0x65,0xfe,0xaa,0x6b,0x17,0x96,0xd5,0xfe,0x58,0x9c,0xb2, +0xe1,0x3e,0xcb,0xf1,0x7f,0xe4,0x7e,0x74,0x8f,0x1c,0xde,0xc6,0x7e,0x7b,0x59,0x07, +0xe0,0x6a,0x54,0xf8,0x88,0xeb,0xf7,0xe2,0x71,0xf9,0xd7,0xde,0xd7,0xbf,0xb1,0x87, +0x85,0x27,0xcf,0x91,0x7f,0x79,0x0f,0xfb,0xea,0xaf,0xfe,0x15,0x89,0x75,0xfb,0x0e, +0x68,0xf2,0x92,0x63,0xd7,0x18,0x7b,0x35,0xa0,0x3f,0xfb,0x3d,0x61,0x2c,0xb6,0xa7, +0x5a,0x6b,0xef,0x39,0xa5,0xc2,0xd5,0x97,0xc3,0x7f,0xbd,0x1f,0x16,0xc7,0xf1,0x1e, +0x2e,0xe0,0x8a,0xb3,0x1f,0xc4,0x4b,0x66,0xea,0xf5,0xf5,0x5e,0xa1,0xfb,0x08,0x29, +0xcf,0xd9,0xb5,0x6b,0x39,0x07,0x6f,0x36,0x16,0x5f,0xe5,0x9a,0xe7,0xee,0xff,0x00, +0x60,0xbd,0x4c,0x82,0x52,0xe7,0x4a,0x7f,0x6d,0xce,0x3f,0xf6,0x4a,0xc2,0x59,0x6b, +0xeb,0x49,0x9c,0xd2,0xe1,0xcc,0x5c,0x76,0x72,0xfc,0x19,0xf3,0xec,0x7e,0x3d,0xb4, +0x7c,0x66,0x40,0x3e,0xb5,0x66,0x3f,0x1a,0xd9,0xbe,0x3f,0x7a,0xb5,0xea,0xfa,0x87, +0xec,0x2f,0xe2,0x58,0x58,0x88,0xac,0x6d,0xe7,0x03,0xbc,0x57,0x0a,0x07,0xea,0x45, +0x61,0x5e,0x7e,0xc5,0x3e,0x2f,0x81,0x49,0x1a,0x3c,0xa7,0x1f,0xf3,0xce,0x74,0x6f, +0xe4,0xd5,0x83,0xcb,0xa3,0xd6,0x9c,0x97,0xc8,0xe7,0x96,0x49,0x8e,0x8e,0xd2,0x7f, +0xf8,0x09,0xc6,0xc7,0xe2,0xcb,0x47,0xc7,0xef,0x53,0xf3,0xa9,0xd3,0xc4,0x76,0xaf, +0xd2,0x45,0x3f,0x8d,0x5d,0xbc,0xfd,0x93,0x7c,0x61,0x66,0x0b,0x7f,0x62,0xea,0x60, +0x7f,0xb1,0x13,0x37,0xf2,0x15,0x87,0x79,0xfb,0x3b,0xf8,0xb2,0xc7,0xef,0xe9,0xfa, +0x9c,0x5f,0xef,0xdb,0xb0,0xfe,0x95,0xce,0xf0,0x14,0x97,0x46,0xbe,0x47,0x3c,0xb2, +0xec,0x74,0x3e,0xd7,0xe0,0xcd,0x55,0xd6,0xad,0xdb,0xf8,0x87,0xe7,0x52,0x0d,0x4e, +0x06,0xfe,0x31,0x5c,0x6d,0xc7,0xc2,0x9f,0x10,0xda,0x31,0x52,0xd3,0xa1,0x07,0x18, +0x68,0xc8,0xaa,0x72,0x78,0x23,0xc4,0x96,0xfd,0x24,0x63,0x8f,0xf6,0x4d,0x66,0xf0, +0x34,0xba,0x48,0xc1,0xe1,0x71,0xb1,0xec,0xcf,0x41,0x17,0xf0,0xff,0x00,0x7a,0x9e, +0xb7,0x91,0xf6,0x7f,0xd6,0xbc,0xd1,0xb4,0x4f,0x13,0x41,0xdc,0x9f,0x6e,0x69,0xa4, +0x78,0x96,0x0e,0xb1,0x16,0xfc,0x6b,0x37,0x97,0xc5,0xed,0x22,0x7d,0x9e,0x35,0x7d, +0x84,0xfe,0x67,0xa8,0xad,0xe0,0x1d,0x25,0x23,0xf1,0xa9,0x93,0x50,0x95,0x7e,0xed, +0xc3,0x8f,0xa3,0x57,0x93,0xff,0x00,0x6a,0xf8,0x82,0x1f,0xbd,0x6a,0xc7,0x1e,0x94, +0xa3,0xc5,0x3a,0xbc,0x5f,0x7e,0xd2,0x4f,0xfb,0xe6,0xa1,0xe5,0xcf,0xa4,0x90,0x73, +0x62,0xe3,0xbd,0x37,0xf7,0x9e,0xbd,0x1e,0xb5,0x7b,0x11,0xf9,0x2e,0xe4,0x1f,0x47, +0x35,0x65,0x3c,0x55,0xaa,0xc7,0xf7,0x6f,0xa5,0xff,0x00,0xbe,0x8d,0x78,0xe0,0xf1, +0xcd,0xe4,0x7f,0x7e,0xda,0x41,0xff,0x00,0x01,0x35,0x2a,0x7c,0x44,0x61,0xf7,0xa2, +0x71,0x51,0xfd,0x9f,0x55,0x6c,0xff,0x00,0x11,0xac,0x5e,0x26,0x3b,0xc2,0x47,0xb4, +0xc3,0xe3,0xcd,0x72,0x0f,0xbb,0x7d,0x27,0xe2,0x6a,0xec,0x3f,0x14,0x7c,0x43,0x0e, +0x31,0x7a,0xe7,0xea,0x6b,0xc4,0x13,0xe2,0x3c,0x47,0x19,0xdd,0x56,0xa3,0xf8,0x89, +0x6c,0x71,0x97,0x22,0x8f,0xa9,0xe2,0x63,0xb5,0xfe,0xf3,0x45,0x9a,0x57,0x86,0xfc, +0xcb,0xef,0x3d,0xda,0xdf,0xe3,0x4f,0x89,0x20,0xc6,0x2e,0x4f,0xe6,0x6b,0x46,0xdb, +0xe3,0xff,0x00,0x88,0xa0,0xc6,0x64,0x2c,0x7d,0x77,0x57,0x81,0x47,0xe3,0xdb,0x46, +0xff,0x00,0x96,0x95,0x66,0x3f,0x1a,0xda,0x37,0xfc,0xb5,0x5a,0x7c,0x98,0xc8,0x6d, +0x27,0xf7,0x9b,0x47,0x3c,0xad,0x1f,0xb6,0xfe,0xe3,0xe8,0x8b,0x7f,0xda,0x53,0x5f, +0x8b,0x86,0x27,0x1e,0xcd,0x5a,0x96,0xdf,0xb5,0x26,0xab,0x10,0x1b,0xe3,0x63,0xf5, +0x35,0xf3,0x5c,0x7e,0x2d,0xb4,0x7e,0x92,0xaf,0xe7,0x53,0xaf,0x88,0xed,0x5f,0xa3, +0xaf,0xe7,0x56,0xab,0xe3,0xe1,0xb4,0xd9,0xd3,0x1e,0x22,0xac,0xbf,0xe5,0xe1,0xf5, +0x0d,0xb7,0xed,0x59,0x73,0x91,0xe6,0xa1,0xff,0x00,0xbe,0x45,0x6b,0x5b,0x7e,0xd5, +0xb0,0xb6,0x03,0xc2,0x3e,0xa4,0x57,0xc9,0xc9,0xad,0xdb,0xbf,0xf1,0x8f,0xce,0xa5, +0x5d,0x52,0x06,0xfe,0x2a,0xb5,0x98,0x66,0x10,0xfb,0x6f,0xee,0x3a,0xe1,0xc4,0x95, +0x97,0xdb,0x47,0xd8,0x16,0xbf,0xb5,0x26,0x9a,0xc3,0xf7,0xa8,0xbf,0x91,0xad,0x4b, +0x6f,0xda,0x5b,0x44,0x9b,0x19,0x0a,0x3f,0x1a,0xf8,0xb4,0x6a,0x30,0x9e,0x77,0x0a, +0x6b,0xea,0xb0,0x20,0x3f,0x3f,0xeb,0x5b,0x47,0x36,0xc7,0xad,0x2f,0x7f,0x91,0xd4, +0xb8,0x9e,0xac,0x77,0x68,0xfb,0xa2,0xdf,0xf6,0x84,0xf0,0xec,0xa0,0x66,0x50,0x0f, +0xb3,0x0a,0xb7,0x37,0xc7,0x8f,0x0d,0x43,0x6e,0x65,0x7b,0x8c,0x01,0xdb,0x70,0xcd, +0x7e,0x7b,0xdf,0xf8,0xce,0xd6,0xc9,0x09,0x33,0x85,0xc7,0xfb,0x55,0xc0,0x78,0x93, +0xe2,0xcc,0x80,0x34,0x76,0x92,0xb1,0x27,0xbe,0x6b,0xd5,0xa1,0x8f,0xcc,0x2a,0xbd, +0x52,0x17,0xfa,0xd9,0x56,0x4f,0x96,0x9d,0x3e,0x66,0x7b,0xb7,0xed,0x37,0xf1,0xc6, +0xcf,0x5f,0xd5,0xee,0xe4,0xb5,0x93,0x31,0x74,0x8c,0x1e,0xb5,0xf2,0xd7,0x87,0x3c, +0x2b,0xaf,0xfc,0x6d,0xf1,0xe6,0x9f,0xe1,0x8d,0x0a,0x16,0xb8,0xd4,0x35,0x09,0x76, +0x6e,0xfe,0x08,0x63,0xcf,0xcd,0x23,0x9e,0xca,0xa3,0x24,0x9f,0x6f,0x5a,0x93,0xc2, +0xbe,0x13,0xf1,0x57,0xc6,0x6f,0x16,0x41,0xa3,0x68,0x36,0x13,0x6a,0xba,0x95,0xc3, +0x70,0x89,0xf7,0x51,0x7b,0xbb,0xb1,0xe1,0x54,0x77,0x27,0xfa,0x8a,0xfd,0x46,0xfd, +0x97,0x3f,0x65,0xdd,0x1b,0xf6,0x79,0xf0,0xdb,0x39,0x31,0xea,0x5e,0x2b,0xbe,0x41, +0xfd,0xa1,0xa9,0xe3,0x8c,0x75,0xf2,0xa2,0xcf,0x21,0x01,0xfc,0x58,0xf2,0x7b,0x01, +0xe9,0x61,0x70,0xaf,0x99,0xce,0x5b,0xbd,0x5b,0x34,0xcb,0x30,0x15,0x73,0x1c,0x53, +0xc6,0x62,0x3f,0xe0,0x7a,0x23,0xd2,0xfe,0x17,0x7c,0x3e,0xd3,0x7e,0x15,0xf8,0x03, +0x44,0xf0,0xa6,0x92,0x81,0x6c,0x74,0xbb,0x65,0x81,0x5b,0x1c,0xbb,0x75,0x67,0x3e, +0xec,0xc4,0x93,0xf5,0xae,0xaa,0x90,0x0c,0x52,0xd7,0xd0,0x25,0x6d,0x0f,0xd2,0xd2, +0xb2,0xb2,0x0a,0x28,0xa2,0x81,0x85,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14, +0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14, +0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14, +0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14, +0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14, +0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14,0x51,0x40,0x05,0x14, +0x51,0x40,0x05,0x14,0x51,0x40,0x09,0x46,0x29,0x68,0xa0,0x04,0xc5,0x18,0xa5,0xa2, +0x80,0x13,0x6d,0x26,0xda,0x75,0x14,0x01,0x13,0xda,0xc3,0x26,0x77,0xc4,0x8d,0x9e, +0xb9,0x50,0x6a,0x8d,0xc7,0x86,0xb4,0x9b,0xa0,0x44,0xda,0x5d,0x9c,0xca,0x7a,0x89, +0x20,0x43,0xfd,0x2b,0x4e,0x8a,0x97,0x18,0xbd,0xd1,0x2e,0x31,0x7b,0xa3,0x98,0xb9, +0xf8,0x65,0xe1,0x3b,0xb1,0xfb,0xdf,0x0e,0xe9,0xa7,0xe9,0x6c,0x8b,0xfc,0x85,0x65, +0xdd,0x7c,0x0e,0xf0,0x35,0xd9,0x26,0x4f,0x0e,0x5a,0x0f,0xf7,0x37,0x27,0xf2,0x22, +0xbb,0xba,0x2b,0x37,0x42,0x93,0xde,0x2b,0xee,0x31,0x78,0x7a,0x32,0xde,0x0b,0xee, +0x47,0x96,0x5d,0xfe,0xcc,0xfe,0x00,0xbb,0x24,0xff,0x00,0x64,0x34,0x24,0xff,0x00, +0xcf,0x39,0x9b,0x8f,0xcc,0x9a,0xc7,0xba,0xfd,0x91,0xfc,0x0b,0x71,0xf7,0x12,0xf6, +0x13,0xfe,0xcc,0xaa,0x7f,0x9a,0xd7,0xb5,0xd1,0x59,0x3c,0x25,0x07,0xf6,0x11,0x8b, +0xc0,0xe1,0x9f,0xfc,0xbb,0x47,0xcf,0x37,0xbf,0xb1,0x77,0x85,0x67,0x27,0xc8,0xd4, +0x2e,0xe1,0x1e,0x8e,0x88,0xff,0x00,0xcb,0x15,0x8b,0x75,0xfb,0x0d,0x69,0x12,0xe7, +0xcb,0xd7,0x58,0x7a,0x6f,0xb4,0x07,0xff,0x00,0x66,0xaf,0xa8,0x28,0xac,0xde,0x07, +0x0e,0xfe,0xcf,0xe6,0x64,0xf2,0xcc,0x2b,0xfb,0x1f,0x8b,0x3e,0x3e,0xbf,0xfd,0x84, +0x1c,0x93,0xf6,0x7d,0x56,0xc6,0x40,0x7f,0xe7,0xac,0x4c,0xbf,0xc8,0x1a,0xc1,0xbd, +0xfd,0x83,0x35,0x65,0xc9,0x8e,0xe7,0x4b,0x97,0xe8,0xee,0x0f,0xea,0xa2,0xbe,0xdf, +0xa4,0x6e,0x95,0x93,0xcb,0xa8,0x74,0xbf,0xde,0x60,0xf2,0x8c,0x2b,0xe8,0xfe,0xf3, +0xe0,0x0b,0xef,0xd8,0x67,0xc4,0xd1,0x93,0xe5,0xe9,0xf0,0x4c,0x3f,0xe9,0x95,0xc2, +0x0f,0xe6,0x45,0x61,0x5e,0x7e,0xc5,0x7e,0x30,0xb7,0x04,0x8d,0x16,0x63,0xff,0x00, +0x5c,0xe7,0x46,0xfe,0x4c,0x6b,0xf4,0x6c,0x75,0xa0,0x75,0xac,0xde,0x5d,0x4f,0xa4, +0x99,0xcf,0x2c,0x8f,0x0c,0xfa,0xbf,0xc3,0xfc,0x8f,0xcc,0x3b,0xcf,0xd9,0x53,0xc5, +0xd6,0x8c,0x41,0xd1,0x35,0x51,0x8f,0xee,0xc0,0xec,0x3f,0x30,0x2b,0x16,0xfb,0xf6, +0x7b,0xf1,0x56,0x9e,0xa5,0xa4,0xb1,0xd4,0xa1,0x03,0xbb,0xc0,0xc3,0xfa,0x57,0xea, +0xb8,0xe9,0x4d,0x3c,0xd4,0x3c,0xbb,0xb4,0xd9,0xcb,0x2e,0x1d,0xc3,0xbe,0xbf,0x82, +0x3f,0x24,0x67,0xf8,0x59,0xaf,0xda,0x9c,0x16,0x99,0x7f,0xde,0x42,0x2a,0xa3,0xf8, +0x2b,0xc4,0x50,0x1e,0x25,0x6f,0xc4,0x1a,0xfd,0x75,0x96,0xd6,0x19,0x57,0xe7,0x89, +0x1f,0xfd,0xe5,0x06,0xb3,0x2f,0x3c,0x37,0xa4,0x5d,0xff,0x00,0xaf,0xd2,0xec,0xa6, +0xff,0x00,0xae,0x96,0xe8,0xdf,0xcc,0x57,0x34,0xf0,0x72,0x8f,0xdb,0xfc,0x3f,0xe0, +0x9e,0x65,0x5e,0x1d,0xc3,0xc7,0xb7,0xdd,0xff,0x00,0x04,0xfc,0x94,0x9b,0x44,0xf1, +0x2c,0x2b,0xc3,0x13,0xf4,0xcd,0x64,0x5d,0xe8,0x9e,0x28,0x94,0x13,0x99,0x31,0xec, +0x09,0xaf,0xd4,0x6f,0x14,0x78,0x37,0x40,0x44,0x98,0xae,0x87,0xa6,0x83,0x8e,0xa2, +0xd2,0x3f,0xf0,0xac,0x0f,0x06,0xf8,0x4b,0x43,0x9e,0xf1,0xd6,0x5d,0x1b,0x4f,0x91, +0x72,0x38,0x7b,0x54,0x23,0xf9,0x57,0x1c,0x63,0x25,0x2b,0x2b,0x7d,0xc7,0x8f,0x2c, +0x97,0x0c,0xa5,0xca,0x92,0xfb,0x8f,0xcc,0x9b,0x2f,0x86,0x9e,0x2d,0xf1,0x2d,0xd8, +0xb7,0xb3,0xd3,0xef,0x75,0x19,0xd8,0xf1,0x15,0xbc,0x4c,0xed,0xcf,0xb0,0x15,0xf4, +0x27,0xc2,0x4f,0xf8,0x27,0x6f,0x8a,0x7c,0x4d,0x3c,0x37,0x7e,0x31,0xb9,0x5f,0x0d, +0xe9,0x99,0x05,0xa0,0x52,0x24,0xba,0x71,0xd7,0x85,0x1f,0x2a,0xfd,0x58,0xe4,0x7f, +0x76,0xbf,0x46,0x74,0xed,0x2e,0xcf,0x4c,0xb7,0x58,0xac,0xed,0x20,0xb4,0x8c,0x0e, +0x12,0x08,0xd5,0x00,0xfc,0x00,0xab,0x8b,0x5e,0xfd,0x1c,0x3d,0xd2,0x94,0xdd,0xcf, +0xa2,0xc0,0xf0,0xed,0x18,0x5a,0x75,0x26,0xe4,0xbb,0x5a,0xc8,0xe2,0x7e,0x16,0xfc, +0x1b,0xf0,0xa7,0xc1,0xcd,0x0c,0x69,0x9e,0x18,0xd2,0xe3,0xb3,0x46,0x03,0xce,0xb8, +0x6f,0x9a,0x79,0xc8,0xef,0x23,0xf5,0x3f,0x4e,0x83,0xb0,0x15,0xdb,0x8e,0x28,0x1d, +0x29,0x6b,0xd0,0x49,0x25,0x64,0x7d,0x8c,0x29,0xc6,0x9c,0x54,0x20,0xac,0x90,0x51, +0x45,0x14,0xcd,0x02,0x8a,0x28,0xa0,0x0f,0xff,0xd9,}; + +static const unsigned int dummy_align__runtime_shtml = 3; +static const unsigned char data__runtime_shtml[] = { +/* /runtime.shtml (15 chars) */ +0x2f,0x72,0x75,0x6e,0x74,0x69,0x6d,0x65,0x2e,0x73,0x68,0x74,0x6d,0x6c,0x00,0x00, + +/* HTTP header */ +/* "HTTP/1.0 200 OK +" (17 bytes) */ +0x48,0x54,0x54,0x50,0x2f,0x31,0x2e,0x30,0x20,0x32,0x30,0x30,0x20,0x4f,0x4b,0x0d, +0x0a, +/* "Server: lwIP/1.3.1 (http://savannah.nongnu.org/projects/lwip) +" (63 bytes) */ +0x53,0x65,0x72,0x76,0x65,0x72,0x3a,0x20,0x6c,0x77,0x49,0x50,0x2f,0x31,0x2e,0x33, +0x2e,0x31,0x20,0x28,0x68,0x74,0x74,0x70,0x3a,0x2f,0x2f,0x73,0x61,0x76,0x61,0x6e, +0x6e,0x61,0x68,0x2e,0x6e,0x6f,0x6e,0x67,0x6e,0x75,0x2e,0x6f,0x72,0x67,0x2f,0x70, +0x72,0x6f,0x6a,0x65,0x63,0x74,0x73,0x2f,0x6c,0x77,0x69,0x70,0x29,0x0d,0x0a, +/* "Content-type: text/html +Expires: Fri, 10 Apr 2008 14:00:00 GMT +Pragma: no-cache + +" (85 bytes) */ +0x43,0x6f,0x6e,0x74,0x65,0x6e,0x74,0x2d,0x74,0x79,0x70,0x65,0x3a,0x20,0x74,0x65, +0x78,0x74,0x2f,0x68,0x74,0x6d,0x6c,0x0d,0x0a,0x45,0x78,0x70,0x69,0x72,0x65,0x73, +0x3a,0x20,0x46,0x72,0x69,0x2c,0x20,0x31,0x30,0x20,0x41,0x70,0x72,0x20,0x32,0x30, +0x30,0x38,0x20,0x31,0x34,0x3a,0x30,0x30,0x3a,0x30,0x30,0x20,0x47,0x4d,0x54,0x0d, +0x0a,0x50,0x72,0x61,0x67,0x6d,0x61,0x3a,0x20,0x6e,0x6f,0x2d,0x63,0x61,0x63,0x68, +0x65,0x0d,0x0a,0x0d,0x0a, +/* raw file data (758 bytes) */ +0x3c,0x21,0x44,0x4f,0x43,0x54,0x59,0x50,0x45,0x20,0x48,0x54,0x4d,0x4c,0x20,0x50, +0x55,0x42,0x4c,0x49,0x43,0x20,0x22,0x2d,0x2f,0x2f,0x57,0x33,0x43,0x2f,0x2f,0x44, +0x54,0x44,0x20,0x48,0x54,0x4d,0x4c,0x20,0x34,0x2e,0x30,0x31,0x20,0x54,0x72,0x61, +0x6e,0x73,0x69,0x74,0x69,0x6f,0x6e,0x61,0x6c,0x2f,0x2f,0x45,0x4e,0x22,0x20,0x22, +0x68,0x74,0x74,0x70,0x3a,0x2f,0x2f,0x77,0x77,0x77,0x2e,0x77,0x33,0x2e,0x6f,0x72, +0x67,0x2f,0x54,0x52,0x2f,0x68,0x74,0x6d,0x6c,0x34,0x2f,0x6c,0x6f,0x6f,0x73,0x65, +0x2e,0x64,0x74,0x64,0x22,0x3e,0x0d,0x0a,0x3c,0x68,0x74,0x6d,0x6c,0x3e,0x0d,0x0a, +0x20,0x20,0x3c,0x68,0x65,0x61,0x64,0x3e,0x0d,0x0a,0x20,0x20,0x20,0x20,0x3c,0x74, +0x69,0x74,0x6c,0x65,0x3e,0x46,0x72,0x65,0x65,0x52,0x54,0x4f,0x53,0x2e,0x6f,0x72, +0x67,0x20,0x6c,0x77,0x49,0x50,0x20,0x57,0x45,0x42,0x20,0x73,0x65,0x72,0x76,0x65, +0x72,0x20,0x64,0x65,0x6d,0x6f,0x3c,0x2f,0x74,0x69,0x74,0x6c,0x65,0x3e,0x0d,0x0a, +0x20,0x20,0x3c,0x2f,0x68,0x65,0x61,0x64,0x3e,0x0d,0x0a,0x20,0x20,0x3c,0x42,0x4f, +0x44,0x59,0x20,0x6f,0x6e,0x4c,0x6f,0x61,0x64,0x3d,0x22,0x77,0x69,0x6e,0x64,0x6f, +0x77,0x2e,0x73,0x65,0x74,0x54,0x69,0x6d,0x65,0x6f,0x75,0x74,0x28,0x26,0x71,0x75, +0x6f,0x74,0x3b,0x6c,0x6f,0x63,0x61,0x74,0x69,0x6f,0x6e,0x2e,0x68,0x72,0x65,0x66, +0x3d,0x27,0x72,0x75,0x6e,0x74,0x69,0x6d,0x65,0x2e,0x73,0x68,0x74,0x6d,0x6c,0x27, +0x26,0x71,0x75,0x6f,0x74,0x3b,0x2c,0x32,0x30,0x30,0x30,0x29,0x22,0x3e,0x0d,0x0a, +0x3c,0x66,0x6f,0x6e,0x74,0x20,0x66,0x61,0x63,0x65,0x3d,0x22,0x61,0x72,0x69,0x61, +0x6c,0x22,0x3e,0x0d,0x0a,0x3c,0x61,0x20,0x68,0x72,0x65,0x66,0x3d,0x22,0x69,0x6e, +0x64,0x65,0x78,0x2e,0x73,0x68,0x74,0x6d,0x6c,0x22,0x3e,0x54,0x61,0x73,0x6b,0x20, +0x53,0x74,0x61,0x74,0x73,0x3c,0x2f,0x61,0x3e,0x20,0x3c,0x62,0x3e,0x7c,0x3c,0x2f, +0x62,0x3e,0x20,0x3c,0x61,0x20,0x68,0x72,0x65,0x66,0x3d,0x22,0x72,0x75,0x6e,0x74, +0x69,0x6d,0x65,0x2e,0x73,0x68,0x74,0x6d,0x6c,0x22,0x3e,0x52,0x75,0x6e,0x20,0x54, +0x69,0x6d,0x65,0x20,0x53,0x74,0x61,0x74,0x73,0x3c,0x2f,0x61,0x3e,0x20,0x3c,0x62, +0x3e,0x7c,0x3c,0x2f,0x62,0x3e,0x20,0x3c,0x61,0x20,0x68,0x72,0x65,0x66,0x3d,0x22, +0x68,0x74,0x74,0x70,0x3a,0x2f,0x2f,0x77,0x77,0x77,0x2e,0x66,0x72,0x65,0x65,0x72, +0x74,0x6f,0x73,0x2e,0x6f,0x72,0x67,0x2f,0x22,0x3e,0x46,0x72,0x65,0x65,0x52,0x54, +0x4f,0x53,0x20,0x48,0x6f,0x6d,0x65,0x70,0x61,0x67,0x65,0x3c,0x2f,0x61,0x3e,0x20, +0x3c,0x62,0x3e,0x7c,0x3c,0x2f,0x62,0x3e,0x20,0x3c,0x61,0x20,0x68,0x72,0x65,0x66, +0x3d,0x22,0x6c,0x6f,0x67,0x6f,0x2e,0x6a,0x70,0x67,0x22,0x3e,0x33,0x37,0x4b,0x20, +0x6a,0x70,0x67,0x3c,0x2f,0x61,0x3e,0x0d,0x0a,0x3c,0x62,0x72,0x3e,0x3c,0x70,0x3e, +0x0d,0x0a,0x3c,0x68,0x72,0x3e,0x0d,0x0a,0x3c,0x62,0x72,0x3e,0x3c,0x70,0x3e,0x0d, +0x0a,0x3c,0x68,0x32,0x3e,0x52,0x75,0x6e,0x2d,0x74,0x69,0x6d,0x65,0x20,0x73,0x74, +0x61,0x74,0x69,0x73,0x74,0x69,0x63,0x73,0x3c,0x2f,0x68,0x32,0x3e,0x0d,0x0a,0x50, +0x61,0x67,0x65,0x20,0x77,0x69,0x6c,0x6c,0x20,0x72,0x65,0x66,0x72,0x65,0x73,0x68, +0x20,0x65,0x76,0x65,0x72,0x79,0x20,0x32,0x20,0x73,0x65,0x63,0x6f,0x6e,0x64,0x73, +0x2e,0x3c,0x70,0x3e,0x0d,0x0a,0x3c,0x66,0x6f,0x6e,0x74,0x20,0x66,0x61,0x63,0x65, +0x3d,0x22,0x63,0x6f,0x75,0x72,0x69,0x65,0x72,0x22,0x3e,0x3c,0x70,0x72,0x65,0x3e, +0x54,0x61,0x73,0x6b,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20, +0x41,0x62,0x73,0x20,0x54,0x69,0x6d,0x65,0x20,0x20,0x20,0x20,0x20,0x20,0x25,0x20, +0x54,0x69,0x6d,0x65,0x3c,0x62,0x72,0x3e,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a, +0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a, +0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a,0x2a, +0x3c,0x62,0x72,0x3e,0x0d,0x0a,0x3c,0x21,0x2d,0x2d,0x23,0x72,0x75,0x6e,0x5f,0x73, +0x74,0x61,0x74,0x73,0x2d,0x2d,0x3e,0x0d,0x0d,0x0a,0x3c,0x2f,0x70,0x72,0x65,0x3e, +0x3c,0x2f,0x66,0x6f,0x6e,0x74,0x3e,0x0d,0x0a,0x3c,0x2f,0x66,0x6f,0x6e,0x74,0x3e, +0x0d,0x0a,0x3c,0x2f,0x62,0x6f,0x64,0x79,0x3e,0x0d,0x0a,0x3c,0x2f,0x68,0x74,0x6d, +0x6c,0x3e,0x0d,0x0a,0x0d,0x0a,}; + + + +const struct fsdata_file file__404_html[] = { { +file_NULL, +data__404_html, +data__404_html + 12, +sizeof(data__404_html) - 12, +1, +}}; + +const struct fsdata_file file__index_shtml[] = { { +file__404_html, +data__index_shtml, +data__index_shtml + 16, +sizeof(data__index_shtml) - 16, +1, +}}; + +const struct fsdata_file file__logo_jpg[] = { { +file__index_shtml, +data__logo_jpg, +data__logo_jpg + 12, +sizeof(data__logo_jpg) - 12, +1, +}}; + +const struct fsdata_file file__runtime_shtml[] = { { +file__logo_jpg, +data__runtime_shtml, +data__runtime_shtml + 16, +sizeof(data__runtime_shtml) - 16, +1, +}}; + +#define FS_ROOT file__runtime_shtml +#define FS_NUMFILES 4 + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/makefsdata b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/makefsdata new file mode 100644 index 000000000..37b4203e6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/makefsdata @@ -0,0 +1,97 @@ +#!/usr/bin/perl + +open(OUTPUT, "> fsdata.c"); + +chdir("fs"); +open(FILES, "find . -type f |"); + +while($file = ) { + + # Do not include files in CVS directories nor backup files. + if($file =~ /(CVS|~)/) { + next; + } + + chop($file); + + open(HEADER, "> /tmp/header") || die $!; + if($file =~ /404/) { + print(HEADER "HTTP/1.0 404 File not found\r\n"); + } else { + print(HEADER "HTTP/1.0 200 OK\r\n"); + } + print(HEADER "Server: lwIP/pre-0.6 (http://www.sics.se/~adam/lwip/)\r\n"); + if($file =~ /\.html$/) { + print(HEADER "Content-type: text/html\r\n"); + } elsif($file =~ /\.gif$/) { + print(HEADER "Content-type: image/gif\r\n"); + } elsif($file =~ /\.png$/) { + print(HEADER "Content-type: image/png\r\n"); + } elsif($file =~ /\.jpg$/) { + print(HEADER "Content-type: image/jpeg\r\n"); + } elsif($file =~ /\.class$/) { + print(HEADER "Content-type: application/octet-stream\r\n"); + } elsif($file =~ /\.ram$/) { + print(HEADER "Content-type: audio/x-pn-realaudio\r\n"); + } else { + print(HEADER "Content-type: text/plain\r\n"); + } + print(HEADER "\r\n"); + close(HEADER); + + unless($file =~ /\.plain$/ || $file =~ /cgi/) { + system("cat /tmp/header $file > /tmp/file"); + } else { + system("cp $file /tmp/file"); + } + + open(FILE, "/tmp/file"); + unlink("/tmp/file"); + unlink("/tmp/header"); + + $file =~ s/\.//; + $fvar = $file; + $fvar =~ s-/-_-g; + $fvar =~ s-\.-_-g; + print(OUTPUT "static const unsigned char data".$fvar."[] = {\n"); + print(OUTPUT "\t/* $file */\n\t"); + for($j = 0; $j < length($file); $j++) { + printf(OUTPUT "%#02x, ", unpack("C", substr($file, $j, 1))); + } + printf(OUTPUT "0,\n"); + + + $i = 0; + while(read(FILE, $data, 1)) { + if($i == 0) { + print(OUTPUT "\t"); + } + printf(OUTPUT "%#02x, ", unpack("C", $data)); + $i++; + if($i == 10) { + print(OUTPUT "\n"); + $i = 0; + } + } + print(OUTPUT "};\n\n"); + close(FILE); + push(@fvars, $fvar); + push(@files, $file); +} + +for($i = 0; $i < @fvars; $i++) { + $file = $files[$i]; + $fvar = $fvars[$i]; + + if($i == 0) { + $prevfile = "NULL"; + } else { + $prevfile = "file" . $fvars[$i - 1]; + } + print(OUTPUT "const struct fsdata_file file".$fvar."[] = {{$prevfile, data$fvar, "); + print(OUTPUT "data$fvar + ". (length($file) + 1) .", "); + print(OUTPUT "sizeof(data$fvar) - ". (length($file) + 1) ."}};\n\n"); +} + +print(OUTPUT "#define FS_ROOT file$fvars[$i - 1]\n\n"); +print(OUTPUT "#define FS_NUMFILES $i\n"); diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/makefsdata.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/makefsdata.c new file mode 100644 index 000000000..b065caa08 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/makefsdata.c @@ -0,0 +1,610 @@ +/** + * makefsdata: Converts a directory structure for use with the lwIP httpd. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Jim Pettinato + * Simon Goldschmidt + * + * @todo: + * - take TCP_MSS, LWIP_TCP_TIMESTAMPS and + * PAYLOAD_ALIGN_TYPE/PAYLOAD_ALIGNMENT as arguments + */ + +#include +#include +#ifdef WIN32 +#define WIN32_LEAN_AND_MEAN +#include "windows.h" +#else +#include +#endif +#include +#include + +/* Compatibility defines Win32 vs. DOS */ +#ifdef WIN32 + +#define FIND_T WIN32_FIND_DATAA +#define FIND_T_FILENAME(fInfo) (fInfo.cFileName) +#define FIND_T_IS_DIR(fInfo) ((fInfo.dwFileAttributes & FILE_ATTRIBUTE_DIRECTORY) != 0) +#define FIND_T_IS_FILE(fInfo) ((fInfo.dwFileAttributes & FILE_ATTRIBUTE_DIRECTORY) == 0) +#define FIND_RET_T HANDLE +#define FINDFIRST_FILE(path, result) FindFirstFileA(path, result) +#define FINDFIRST_DIR(path, result) FindFirstFileA(path, result) +#define FINDNEXT(ff_res, result) FindNextFileA(ff_res, result) +#define FINDFIRST_SUCCEEDED(ret) (ret != INVALID_HANDLE_VALUE) +#define FINDNEXT_SUCCEEDED(ret) (ret == TRUE) + +#define GETCWD(path, len) GetCurrentDirectoryA(len, path) +#define CHDIR(path) SetCurrentDirectoryA(path) + +#define NEWLINE "\r\n" +#define NEWLINE_LEN 2 + +#else + +#define FIND_T struct fflbk +#define FIND_T_FILENAME(fInfo) (fInfo.ff_name) +#define FIND_T_IS_DIR(fInfo) ((fInfo.ff_attrib & FA_DIREC) == FA_DIREC) +#define FIND_T_IS_FILE(fInfo) (1) +#define FIND_RET_T int +#define FINDFIRST_FILE(path, result) findfirst(path, result, FA_ARCH) +#define FINDFIRST_DIR(path, result) findfirst(path, result, FA_DIREC) +#define FINDNEXT(ff_res, result) FindNextFileA(ff_res, result) +#define FINDFIRST_SUCCEEDED(ret) (ret == 0) +#define FINDNEXT_SUCCEEDED(ret) (ret == 0) + +#define GETCWD(path, len) getcwd(path, len) +#define CHDIR(path) chdir(path) + +#endif + +/* define this to get the header variables we use to build HTTP headers */ +#define LWIP_HTTPD_DYNAMIC_HEADERS 1 +#include "../httpd_structs.h" + +#include "../../../lwip-1.4.0/src/core/ipv4/inet_chksum.c" +#include "../../../lwip-1.4.0/src/core/def.c" + +/** (Your server name here) */ +const char *serverID = "Server: "HTTPD_SERVER_AGENT"\r\n"; + +/* change this to suit your MEM_ALIGNMENT */ +#define PAYLOAD_ALIGNMENT 4 +/* set this to 0 to prevent aligning payload */ +#define ALIGN_PAYLOAD 1 +/* define this to a type that has the required alignment */ +#define PAYLOAD_ALIGN_TYPE "unsigned int" +static int payload_alingment_dummy_counter = 0; + +#define HEX_BYTES_PER_LINE 16 + +#define MAX_PATH_LEN 256 + +#define COPY_BUFSIZE 10240 + +int process_sub(FILE *data_file, FILE *struct_file); +int process_file(FILE *data_file, FILE *struct_file, const char *filename); +int file_write_http_header(FILE *data_file, const char *filename, int file_size, + u16_t *http_hdr_len, u16_t *http_hdr_chksum); +int file_put_ascii(FILE *file, const char *ascii_string, int len, int *i); +int s_put_ascii(char *buf, const char *ascii_string, int len, int *i); +void concat_files(const char *file1, const char *file2, const char *targetfile); + +static unsigned char file_buffer_raw[COPY_BUFSIZE]; +/* 5 bytes per char + 3 bytes per line */ +static char file_buffer_c[COPY_BUFSIZE * 5 + ((COPY_BUFSIZE / HEX_BYTES_PER_LINE) * 3)]; + +char curSubdir[MAX_PATH_LEN]; +char lastFileVar[MAX_PATH_LEN]; +char hdr_buf[4096]; + +unsigned char processSubs = 1; +unsigned char includeHttpHeader = 1; +unsigned char useHttp11 = 0; +unsigned char precalcChksum = 0; + +int main(int argc, char *argv[]) +{ + FIND_T fInfo; + FIND_RET_T fret; + char path[MAX_PATH_LEN]; + char appPath[MAX_PATH_LEN]; + FILE *data_file; + FILE *struct_file; + int filesProcessed; + int i; + char targetfile[MAX_PATH_LEN]; + strcpy(targetfile, "fsdata.c"); + + memset(path, 0, sizeof(path)); + memset(appPath, 0, sizeof(appPath)); + + printf(NEWLINE " makefsdata - HTML to C source converter" NEWLINE); + printf(" by Jim Pettinato - circa 2003 " NEWLINE); + printf(" extended by Simon Goldschmidt - 2009 " NEWLINE NEWLINE); + + strcpy(path, "fs"); + for(i = 1; i < argc; i++) { + if (argv[i][0] == '-') { + if (strstr(argv[i], "-s")) { + processSubs = 0; + } else if (strstr(argv[i], "-e")) { + includeHttpHeader = 0; + } else if (strstr(argv[i], "-11")) { + useHttp11 = 1; + } else if (strstr(argv[i], "-c")) { + precalcChksum = 1; + } else if((argv[i][1] == 'f') && (argv[i][2] == ':')) { + strcpy(targetfile, &argv[i][3]); + printf("Writing to file \"%s\"\n", targetfile); + } + } else { + strcpy(path, argv[i]); + } + } + + /* if command line param or subdir named 'fs' not found spout usage verbiage */ + fret = FINDFIRST_DIR(path, &fInfo); + if (!FINDFIRST_SUCCEEDED(fret)) { + /* if no subdir named 'fs' (or the one which was given) exists, spout usage verbiage */ + printf(" Failed to open directory \"%s\"." NEWLINE NEWLINE, path); + printf(" Usage: htmlgen [targetdir] [-s] [-i] [-f:]" NEWLINE NEWLINE); + printf(" targetdir: relative or absolute path to files to convert" NEWLINE); + printf(" switch -s: toggle processing of subdirectories (default is on)" NEWLINE); + printf(" switch -e: exclude HTTP header from file (header is created at runtime, default is off)" NEWLINE); + printf(" switch -11: include HTTP 1.1 header (1.0 is default)" NEWLINE); + printf(" switch -c: precalculate checksums for all pages (default is off)" NEWLINE); + printf(" switch -f: target filename (default is \"fsdata.c\")" NEWLINE); + printf(" if targetdir not specified, htmlgen will attempt to" NEWLINE); + printf(" process files in subdirectory 'fs'" NEWLINE); + exit(-1); + } + + printf("HTTP %sheader will %s statically included." NEWLINE, + (includeHttpHeader ? (useHttp11 ? "1.1 " : "1.0 ") : ""), + (includeHttpHeader ? "be" : "not be")); + + sprintf(curSubdir, ""); /* start off in web page's root directory - relative paths */ + printf(" Processing all files in directory %s", path); + if (processSubs) { + printf(" and subdirectories..." NEWLINE NEWLINE); + } else { + printf("..." NEWLINE NEWLINE); + } + + GETCWD(appPath, MAX_PATH_LEN); + data_file = fopen("fsdata.tmp", "wb"); + if (data_file == NULL) { + printf("Failed to create file \"fsdata.tmp\"\n"); + exit(-1); + } + struct_file = fopen("fshdr.tmp", "wb"); + if (struct_file == NULL) { + printf("Failed to create file \"fshdr.tmp\"\n"); + exit(-1); + } + + CHDIR(path); + + fprintf(data_file, "#include \"fs.h\"" NEWLINE); + fprintf(data_file, "#include \"lwip/def.h\"" NEWLINE); + fprintf(data_file, "#include \"fsdata.h\"" NEWLINE NEWLINE NEWLINE); + + fprintf(data_file, "#define file_NULL (struct fsdata_file *) NULL" NEWLINE NEWLINE NEWLINE); + + sprintf(lastFileVar, "NULL"); + + filesProcessed = process_sub(data_file, struct_file); + + /* data_file now contains all of the raw data.. now append linked list of + * file header structs to allow embedded app to search for a file name */ + fprintf(data_file, NEWLINE NEWLINE); + fprintf(struct_file, "#define FS_ROOT file_%s" NEWLINE, lastFileVar); + fprintf(struct_file, "#define FS_NUMFILES %d" NEWLINE NEWLINE, filesProcessed); + + fclose(data_file); + fclose(struct_file); + + CHDIR(appPath); + /* append struct_file to data_file */ + printf(NEWLINE "Creating target file..." NEWLINE NEWLINE); + concat_files("fsdata.tmp", "fshdr.tmp", targetfile); + + /* if succeeded, delete the temporary files */ + remove("fsdata.tmp"); + remove("fshdr.tmp"); + + printf(NEWLINE "Processed %d files - done." NEWLINE NEWLINE, filesProcessed); + + return 0; +} + +static void copy_file(const char *filename_in, FILE *fout) +{ + FILE *fin; + size_t len; + fin = fopen(filename_in, "rb"); + if (fin == NULL) { + printf("Failed to open file \"%s\"\n", filename_in); + exit(-1); + } + + while((len = fread(file_buffer_raw, 1, COPY_BUFSIZE, fin)) > 0) + { + fwrite(file_buffer_raw, 1, len, fout); + } + fclose(fin); +} + +void concat_files(const char *file1, const char *file2, const char *targetfile) +{ + FILE *fout; + fout = fopen(targetfile, "wb"); + if (fout == NULL) { + printf("Failed to open file \"%s\"\n", targetfile); + exit(-1); + } + copy_file(file1, fout); + copy_file(file2, fout); + fclose(fout); +} + +int process_sub(FILE *data_file, FILE *struct_file) +{ + FIND_T fInfo; + FIND_RET_T fret; + int filesProcessed = 0; + char oldSubdir[MAX_PATH_LEN]; + + if (processSubs) { + /* process subs recursively */ + strcpy(oldSubdir, curSubdir); + fret = FINDFIRST_DIR("*", &fInfo); + if (FINDFIRST_SUCCEEDED(fret)) { + do { + const char *curName = FIND_T_FILENAME(fInfo); + if (curName == NULL) continue; + if (curName[0] == '.') continue; + if (strcmp(curName, "CVS") == 0) continue; + if (!FIND_T_IS_DIR(fInfo)) continue; + CHDIR(curName); + strcat(curSubdir, "/"); + strcat(curSubdir, curName); + printf(NEWLINE "processing subdirectory %s/..." NEWLINE, curSubdir); + filesProcessed += process_sub(data_file, struct_file); + CHDIR(".."); + strcpy(curSubdir, oldSubdir); + } while (FINDNEXT_SUCCEEDED(FINDNEXT(fret, &fInfo))); + } + } + + fret = FINDFIRST_FILE("*.*", &fInfo); + if (FINDFIRST_SUCCEEDED(fret)) { + /* at least one file in directory */ + do { + if (FIND_T_IS_FILE(fInfo)) { + const char *curName = FIND_T_FILENAME(fInfo); + printf("processing %s/%s..." NEWLINE, curSubdir, curName); + if (process_file(data_file, struct_file, curName) < 0) { + printf(NEWLINE "Error... aborting" NEWLINE); + return -1; + } + filesProcessed++; + } + } while (FINDNEXT_SUCCEEDED(FINDNEXT(fret, &fInfo))); + } + return filesProcessed; +} + +int get_file_size(const char* filename) +{ + FILE *inFile; + int file_size = -1; + inFile = fopen(filename, "rb"); + if (inFile == NULL) { + printf("Failed to open file \"%s\"\n", filename); + exit(-1); + } + fseek(inFile, 0, SEEK_END); + file_size = ftell(inFile); + fclose(inFile); + return file_size; +} + +void process_file_data(const char *filename, FILE *data_file) +{ + FILE *source_file; + size_t len, written, i, src_off=0; + + source_file = fopen(filename, "rb"); + + do { + size_t off = 0; + len = fread(file_buffer_raw, 1, COPY_BUFSIZE, source_file); + if (len > 0) { + for (i = 0; i < len; i++) { + sprintf(&file_buffer_c[off], "0x%02.2x,", file_buffer_raw[i]); + off += 5; + if ((++src_off % HEX_BYTES_PER_LINE) == 0) { + memcpy(&file_buffer_c[off], NEWLINE, NEWLINE_LEN); + off += NEWLINE_LEN; + } + } + written = fwrite(file_buffer_c, 1, off, data_file); + } + } while(len > 0); + fclose(source_file); +} + +int write_checksums(FILE *struct_file, const char *filename, const char *varname, + u16_t hdr_len, u16_t hdr_chksum) +{ + int chunk_size = TCP_MSS; + int offset; + size_t len; + int i = 0; + FILE *f; +#if LWIP_TCP_TIMESTAMPS + /* when timestamps are used, usable space is 12 bytes less per segment */ + chunk_size -= 12; +#endif + + fprintf(struct_file, "#if HTTPD_PRECALCULATED_CHECKSUM" NEWLINE); + fprintf(struct_file, "const struct fsdata_chksum chksums_%s[] = {" NEWLINE, varname); + + memset(file_buffer_raw, 0xab, sizeof(file_buffer_raw)); + f = fopen(filename, "rb"); + if (f == INVALID_HANDLE_VALUE) { + printf("Failed to open file \"%s\"\n", filename); + exit(-1); + } + if (hdr_len > 0) { + /* add checksum for HTTP header */ + fprintf(struct_file, "{%d, 0x%04x, %d}," NEWLINE, 0, hdr_chksum, hdr_len); + i++; + } + for (offset = hdr_len; ; offset += len) { + unsigned short chksum; + len = fread(file_buffer_raw, 1, chunk_size, f); + if (len == 0) { + break; + } + chksum = ~inet_chksum(file_buffer_raw, (u16_t)len); + /* add checksum for data */ + fprintf(struct_file, "{%d, 0x%04x, %d}," NEWLINE, offset, chksum, len); + i++; + } + fclose(f); + fprintf(struct_file, "};" NEWLINE); + fprintf(struct_file, "#endif /* HTTPD_PRECALCULATED_CHECKSUM */" NEWLINE); + return i; +} + +int process_file(FILE *data_file, FILE *struct_file, const char *filename) +{ + char *pch; + char varname[MAX_PATH_LEN]; + int i = 0; + char qualifiedName[MAX_PATH_LEN]; + int file_size; + u16_t http_hdr_chksum = 0; + u16_t http_hdr_len = 0; + int chksum_count = 0; + + /* create qualified name (TODO: prepend slash or not?) */ + sprintf(qualifiedName,"%s/%s", curSubdir, filename); + /* create C variable name */ + strcpy(varname, qualifiedName); + /* convert slashes & dots to underscores */ + while ((pch = strpbrk(varname, "./\\")) != NULL) { + *pch = '_'; + } +#if ALIGN_PAYLOAD + /* to force even alignment of array */ + fprintf(data_file, "static const " PAYLOAD_ALIGN_TYPE " dummy_align_%s = %d;" NEWLINE, varname, payload_alingment_dummy_counter++); +#endif /* ALIGN_PAYLOAD */ + fprintf(data_file, "static const unsigned char data_%s[] = {" NEWLINE, varname); + /* encode source file name (used by file system, not returned to browser) */ + fprintf(data_file, "/* %s (%d chars) */" NEWLINE, qualifiedName, strlen(qualifiedName)+1); + file_put_ascii(data_file, qualifiedName, strlen(qualifiedName)+1, &i); +#if ALIGN_PAYLOAD + /* pad to even number of bytes to assure payload is on aligned boundary */ + while(i % PAYLOAD_ALIGNMENT != 0) { + fprintf(data_file, "0x%02.2x,", 0); + i++; + } +#endif /* ALIGN_PAYLOAD */ + fprintf(data_file, NEWLINE); + + file_size = get_file_size(filename); + if (includeHttpHeader) { + file_write_http_header(data_file, filename, file_size, &http_hdr_len, &http_hdr_chksum); + } + if (precalcChksum) { + chksum_count = write_checksums(struct_file, filename, varname, http_hdr_len, http_hdr_chksum); + } + + /* build declaration of struct fsdata_file in temp file */ + fprintf(struct_file, "const struct fsdata_file file_%s[] = { {" NEWLINE, varname); + fprintf(struct_file, "file_%s," NEWLINE, lastFileVar); + fprintf(struct_file, "data_%s," NEWLINE, varname); + fprintf(struct_file, "data_%s + %d," NEWLINE, varname, i); + fprintf(struct_file, "sizeof(data_%s) - %d," NEWLINE, varname, i); + fprintf(struct_file, "%d," NEWLINE, includeHttpHeader); + if (precalcChksum) { + fprintf(struct_file, "#if HTTPD_PRECALCULATED_CHECKSUM" NEWLINE); + fprintf(struct_file, "%d, chksums_%s," NEWLINE, chksum_count, varname); + fprintf(struct_file, "#endif /* HTTPD_PRECALCULATED_CHECKSUM */" NEWLINE); + } + fprintf(struct_file, "}};" NEWLINE NEWLINE); + strcpy(lastFileVar, varname); + + /* write actual file contents */ + i = 0; + fprintf(data_file, NEWLINE "/* raw file data (%d bytes) */" NEWLINE, file_size); + process_file_data(filename, data_file); + fprintf(data_file, "};" NEWLINE NEWLINE); + + return 0; +} + +int file_write_http_header(FILE *data_file, const char *filename, int file_size, + u16_t *http_hdr_len, u16_t *http_hdr_chksum) +{ + int i = 0; + int response_type = HTTP_HDR_OK; + int file_type = HTTP_HDR_DEFAULT_TYPE; + const char *cur_string; + size_t cur_len; + int written = 0; + size_t hdr_len = 0; + u16_t acc; + const char *file_ext; + int j; + + memset(hdr_buf, 0, sizeof(hdr_buf)); + + if (useHttp11) { + response_type = HTTP_HDR_OK_11; + } + + fprintf(data_file, NEWLINE "/* HTTP header */"); + if (strstr(filename, "404") == filename) { + response_type = HTTP_HDR_NOT_FOUND; + if (useHttp11) { + response_type = HTTP_HDR_NOT_FOUND_11; + } + } else if (strstr(filename, "400") == filename) { + response_type = HTTP_HDR_BAD_REQUEST; + if (useHttp11) { + response_type = HTTP_HDR_BAD_REQUEST_11; + } + } else if (strstr(filename, "501") == filename) { + response_type = HTTP_HDR_NOT_IMPL; + if (useHttp11) { + response_type = HTTP_HDR_NOT_IMPL_11; + } + } + cur_string = g_psHTTPHeaderStrings[response_type]; + cur_len = strlen(cur_string); + fprintf(data_file, NEWLINE "/* \"%s\" (%d bytes) */" NEWLINE, cur_string, cur_len); + written += file_put_ascii(data_file, cur_string, cur_len, &i); + i = 0; + if (precalcChksum) { + memcpy(&hdr_buf[hdr_len], cur_string, cur_len); + hdr_len += cur_len; + } + + cur_string = serverID; + cur_len = strlen(cur_string); + fprintf(data_file, NEWLINE "/* \"%s\" (%d bytes) */" NEWLINE, cur_string, cur_len); + written += file_put_ascii(data_file, cur_string, cur_len, &i); + i = 0; + if (precalcChksum) { + memcpy(&hdr_buf[hdr_len], cur_string, cur_len); + hdr_len += cur_len; + } + + file_ext = filename; + while(strstr(file_ext, ".") != NULL) { + file_ext = strstr(file_ext, "."); + file_ext++; + } + if((file_ext == NULL) || (*file_ext == 0)) { + printf("failed to get extension for file \"%s\", using default.\n", filename); + } else { + for(j = 0; j < NUM_HTTP_HEADERS; j++) { + if(!strcmp(file_ext, g_psHTTPHeaders[j].extension)) { + file_type = g_psHTTPHeaders[j].headerIndex; + break; + } + } + if (j >= NUM_HTTP_HEADERS) { + printf("failed to get file type for extension \"%s\", using default.\n", file_ext); + file_type = HTTP_HDR_DEFAULT_TYPE; + } + } + + if (useHttp11) { + char intbuf[MAX_PATH_LEN]; + memset(intbuf, 0, sizeof(intbuf)); + + cur_string = g_psHTTPHeaderStrings[HTTP_HDR_CONTENT_LENGTH]; + cur_len = strlen(cur_string); + fprintf(data_file, NEWLINE "/* \"%s%d\r\n\" (%d+ bytes) */" NEWLINE, cur_string, file_size, cur_len+2); + written += file_put_ascii(data_file, cur_string, cur_len, &i); + if (precalcChksum) { + memcpy(&hdr_buf[hdr_len], cur_string, cur_len); + hdr_len += cur_len; + } + + _itoa(file_size, intbuf, 10); + strcat(intbuf, "\r\n"); + cur_len = strlen(intbuf); + written += file_put_ascii(data_file, intbuf, cur_len, &i); + i = 0; + if (precalcChksum) { + memcpy(&hdr_buf[hdr_len], intbuf, cur_len); + hdr_len += cur_len; + } + + cur_string = g_psHTTPHeaderStrings[HTTP_HDR_CONN_CLOSE]; + cur_len = strlen(cur_string); + fprintf(data_file, NEWLINE "/* \"%s\" (%d bytes) */" NEWLINE, cur_string, cur_len); + written += file_put_ascii(data_file, cur_string, cur_len, &i); + i = 0; + if (precalcChksum) { + memcpy(&hdr_buf[hdr_len], cur_string, cur_len); + hdr_len += cur_len; + } + } + + cur_string = g_psHTTPHeaderStrings[file_type]; + cur_len = strlen(cur_string); + fprintf(data_file, NEWLINE "/* \"%s\" (%d bytes) */" NEWLINE, cur_string, cur_len); + written += file_put_ascii(data_file, cur_string, cur_len, &i); + i = 0; + if (precalcChksum) { + memcpy(&hdr_buf[hdr_len], cur_string, cur_len); + hdr_len += cur_len; + + LWIP_ASSERT("hdr_len <= 0xffff", hdr_len <= 0xffff); + LWIP_ASSERT("strlen(hdr_buf) == hdr_len", strlen(hdr_buf) == hdr_len); + acc = ~inet_chksum(hdr_buf, (u16_t)hdr_len); + *http_hdr_len = (u16_t)hdr_len; + *http_hdr_chksum = acc; + } + + return written; +} + +int file_put_ascii(FILE *file, const char* ascii_string, int len, int *i) +{ + int x; + for(x = 0; x < len; x++) { + unsigned char cur = ascii_string[x]; + fprintf(file, "0x%02.2x,", cur); + if ((++(*i) % HEX_BYTES_PER_LINE) == 0) { + fprintf(file, NEWLINE); + } + } + return len; +} + +int s_put_ascii(char *buf, const char *ascii_string, int len, int *i) +{ + int x; + int idx = 0; + for(x = 0; x < len; x++) { + unsigned char cur = ascii_string[x]; + sprintf(&buf[idx], "0x%02.2x,", cur); + idx += 5; + if ((++(*i) % HEX_BYTES_PER_LINE) == 0) { + sprintf(&buf[idx], NEWLINE); + idx += NEWLINE_LEN; + } + } + return len; +} diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/makefsdata.exe b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/makefsdata.exe new file mode 100644 index 0000000000000000000000000000000000000000..7d4271d0aa18c7f8eeb905dee82a49bce8ba89ab GIT binary patch literal 46592 zcmeHw3w%_?_5b9BAqEp_VzEZOBGCvW>}EHQ&FAj z-K1r`uC*;#>Q5^aYi-NV+SUqMv;iYTOD!rtMa7>{XuFtHsiqp0y8rK)d-oLrQf+_z zx1Ve>bLY;SIdkUBnKS2}nY~+k?Hw$MF_w%F3Nf}5SNc@)`1H{biqE z>YQIY!(n;*<<4T<>&5oNp)a><6dgnu#O@>OEZ(8B1YOdHBi{;1)3ppCne< z!vT36MEn}LNI-znQ7SWueOaz27f2T&iOrqDnDC7RmJ?TS`kVB`Bz8a|Z9>2TkEPqQ z!tG{6zf9M7z%7goaX1vb(uOD#u*8#bbP9~!P~b9~JSN5-EkOBtz$tLGA;f$t!MFkm zj5%un^AG}f$Tr6SAqlwt0=opL#xM{kSvoFvQ9AmmBsiDbMWk`wfrkvdV)sX3C{;=A zx-11q81=kSpks?G7EJE}G zr9Pp8$FD*(h48(879vG0qRR=mlHh(yAPWf9Q&eLvm6|B;UAn!OQVUgxUZdOhDe9wW z0F&w1y%4Hn9}#`OA_VCK{9`IDrzXEgw;dNFdU7$M2dUs&6g5+H9Yys7@}ojTW=PJl zcc^c7QQdqh_@o|D(*i_yQo$O68!1P$V+NuzD!u1CM7LAw2zACrAiL?-L!|wTNK;Tl za|mC5HKGfMVXHKV&ZfMzly@by(NER%#HNMB-6tt}hVrhY=oX^jca-|55YZJh9*k1U zsUaN|m6^O2yhv?4)vXM%w3CqH(5&Z=$=HfUR zO>*G>7Y;OuBRwO>p(q=gmj)is4243E(sI6&=zH&{`wU~WitIJK#6&}?-!L?sDjJ5w zRDbP|Z`}~{+>E=79ShUy#HJx}ezGz6I95d8Kx)R0!KB(Tf9;rP7~37p6l=$N-XQBM zX}8~iJYJ{g4ZyBnld{P7^e0t)PkUx(JYsn1QRJ~XgBxmJLd{&%V7rG>d3A=H-N#bT zCJe_`gH8hP>-XfG4p20t6R{(rVI-HgZy4hQjDV=PjLb6uv!cl?bgeGRNd)$jco!WInfKVzo9hEDw}XZk(wPc+lN5zhU5Go9uc zX1eNwf5l8cGrhv)xgT_LeNajIfS!zGeE^|Khy1111qYz5B;k{_7}Y`FmV#5Kn_?XQ z(J=lT!VhyQj6X78j$kHW{TZS4XN2o&-?|aL{y>fJ^=E{yKl(5kryUqxXQK7zNM!vv z0(p+A4lG|Wsw1-g9QpM1Cr-0dKf#mgzn-2aXErht)TfS5YPc8B9jS6RKEyJ53f1@N z_>4jSdwfpt#j0QGl5_MFT{=BJ4601t3`mho-5a1zY)b8U6CNA3`>oWo_ef>9-FF-F9<$ohq_(zvRFU#`3H4`dS^_1Um!nX4}RV>hF zhWr_W_wp7}ZRDG1NA7)pqudL4Zh9p5?h}-oBIQCSuLp*(0w!gfLqv_*D#vA~NZHBb zvfl5)1|ADGV)j*-^|b&j8|&Y{0>+NSPJ`2*D%UK!uX`3b%;tG9k!Cc0kc)yHP~_9WGZ z2Y1hLuIa>4Im31k1cb+p_+dty!#T0lQCAw1uS<20xv{Ddf}OY;0|6?m3uR{|@>O*f z>ihe)(`x=W#i5M8Pk2{lEVc*6HTWK|f)O{wWRv_Hma?A$t<4T9tvffB{Sn(WMn*&LXtvq zwy*DQOvB@-HJm1;gGgsQGK~W~?U|SHNH$4G-}3~!8L&e#ETs=2E%ID{A5CY%LDv^4 ze^d+*?mBT3W!2lZATvC)>0pxo9nNWjwXOf(`6#nRra>n!3y+aArX~r+5|pA3G(*sb z^D$h;7zi4Gd_W9;5d}5l3bJIxTwieQ5z5Y#MCHS`B^5#RD0sDw2tBW%%-?qhCcp1- zikUYL$dkt*-@!4&F#G-(lw-G3_oFCp~x8C zz0}ads4a3bjiGF3g!+r6(#;c>CP<~-6PF(OGv`X_#HCM3r3#eVD&LDA!yi*wA9c+r z28d~O!3<=pa&sfL6i+Ojrhy9oAbkx?F04MacCH zq@#C|5Oqgd-7KLY&`@?XyN73oyK;9-BP8o>C{^{>i@!4lvbX0}v0&M7D75TavN&o_ zsD2l`_pMNN`3Xi#gMcgg_FyKimR$>u3fi$T`T2MYfntDj-caWxqmeNO& z_Ly8NEgq}A!@^8Xr_toGF(*aVMO{|Mq|5E^F(?1yV7dK9)&+llQPcAUT(e>O4H91o zg(w;_G1sDc?gz)9I^ow?H^#hku_&O}HV|WPk&xd47(5Vg~Mlrt-6%hNY9ERbrHzM2&58_ z!@nSqc}A<%aesQrDn0fp~zikUa% z*kLp!^1O^EQhgs5AnR#l*_HvLly3~`rRMtjQMjGMldAL$W#ayBx*wGxBg?=c)UY)I z1t&ZBzkiVExtH{f` z6(BNuB>dkF`k5uFaH1*#b zX6kydlh{C4se`uUm>$s*I{<=Y0I@b5uItqL;Oj?-G3kB%>vGVcV9Z>nRg-sNFf^hj*auo&l0cn*T%`Bs>w_>j!Xn zEqoJck~v!Q4k7L6FgJKtnC-5A^HuKj`f8s6)&cR^Hj&!;7>tWk(-WwzmjDx|w)RRH ziS5vWq--j=5+b?S&P$}+nurB-CvRlrWZkrmzzrj@>ZzTwK9_ou^iwJZnd_%92-&09 zHVo_UeTG5Y&{OY3{1|?d^JAZ3mjrY=-TWI4%XM?c*M9+c*_}T;6>f17aPDf?8b;h6 zWMn+Dft0&AT4yt3Hi=EUdiLD#autIgKzaZo{&fJQXxQcJPw^XeiH1RrWe^F~^N(ht zg%AGH_q_L#_C(tagu<{Zg)kU{uVQD2j8Ccw-~X;-H}esfbj~imS^zGT9bGMwIPKVh z8etjVI7fz#UpR(k<#ca*-alyuUC+axsW4k&tB0q@TRJ{|qp3 z^W^);fO|Kqum2VWUByu&Jcu*u+L>)T7lBj^zC?5usB%#Ku;dUtIcp(HBT0rKB&k1x zSpCPMtAEr^P;vVBj-oelxDK_4j8ea9|CjoOEsensp2H@_EXGp0)3PXN7e{%)&;k`#zzed-b{7+C>QKkbDc^y#eCH98%BNWMwtgT^5|aHI{e($ zA^2?keMGW2jncl|34Wdc6`LpEJ5UrgP@7C9}qI7!M6_+ ziOEn=kZZYDwsfilYalGwg!a3<67ebw7W_q|t}(EQI$qD+%1P)HcFsi3*j$VN_O=)L z22WJN-&268#U#}kBdtVK36agKaI1nE8itt5Ix=1{oK3J$3&Brb<<$H8_M`QvXDm0s z#}S0mD8h+F#UL)zNX!bp{|eR00zCObK~;Xn4yi)M4yi_96LC+jfv1)ycsp5sE)P-W z9@<3gPmj||4lo5|bN|O6mBZK%^O5?wgqMehXXgYM@;QXW3v_`fsk7ZjfKBOfLy|lZ z;D!kRUj_LxcQDGf^%FF@Qv#70(uy8P8aYZl$?LZP73sbhpxIGpvrW*Voden=%{Y?3YN> z9H9IkB29{fY}ZXllN3^V1JX8+$JuH#yIMOeUD2C1+l_8-C;N)m)M2;UE#_-Xofc+i zt4yvgN}Z|Fn}mySKzhCf*QMuMjKHJc!VsLS{|%$ah9wd_hhGj)mjZWmhmE*3DNzc8Wd>_>D~)~ zAp;oVah{8uVGpo2PEd7fOjR-|EsIw^u`M6c$D?lDFi~?W)hRFeGL3o$5EHlZl({I?h zPvSQSmUYdgVT5AS_MSb&?O7CJ4mTe}_#&lp^KkWYiH zGYGLfFhAgV$$m(QVF1rCSZhcVlN{K((NOHvAXB*pjh!?;PjS*^VL82&{6wN5A|o`z~qmhGIZ{SuwnDqlmfB)?{-cPMzyJuW8tBtn%CTiv$jxxR(e|$4HMVt8^p4zq> zrMA9%fD2jpscnmB$g+yH+pT`s`ZJK)!c#jXkJ$bSSRv;fbl_NP z$Xs_LRui0pq{E}{;P~J>WdC!|)i`I$&fi10;M_>X!=~7j<;RMIo1Qmdmq?o0UDogT^_dzN}X!aa5)pU#HMqijerj9~qb9)56!F~Ng3a?FAW8s>_8=4}Z9 zd}glf-yh1Q{e@629efDo(zZY-mo^Z*2~UD$z7b}uhs7%zlH1`@w4*UR17TFIT{f;! zF$C~BfT}{`yW-3Kbtg3Cw=5h^4cs@2ID3buBN|JSlb-9*eTi;8 z)5XQ5sbW)dU48J~{k#p)aH7(;50=ph?Uc29(BioEs9NlYx8E%OrSE;uB{-mRVS{*G zYTv7#tfdd_7e5i7dG9A;l7B(6zd7BnYF&Q)b$gP>DYFRu;=Aa<%i0e-^->?M4*VB& zK%)OKYEsj9{t55dVhuX5Taz^dhfc0Z78^65gp=!y!9t0C4jI>p$A?p-Om8Y$*b73N z#meL>VN{JFeU;`sZ-%Bh%bTWYp5aZ=H0OBE6>F21HrECJ#xbT#l^3LI8WkrZWpBim ztx8_f_rCWLiCHK0FqT`No?fqC`O198ycf4)2ND5)ds8SYA$Ts@GzP!^TNvaJ zCzRX5<7J4o)98qxH}SnEk1c&B6henWx#YX*sAUX4|m2 z=bye+pqpuCx=9T_4T^$egJ6(e4Jw)U9NRTtAOn0Bpnx*?JTFtAEaW|#8px9hRQ+fA zy#!9LZ9yg$`Sho0B$Br}(fGEtAl^oiIIRQsb+!)5a8hJL6v{rxdzH1V8+SfE#cW+# zdup%_Gy}`2+L!pV26XeMypzCqdHW}})c=NM^)rxV-b&NP=o>f+rNH-pm4-3ZQ^tVd zxOp2D`7J@8-Ud#BJzT&bFYqOUynO~bz>N#--Ll|i=pSYZ|7rwjJ%}QX=GWPbsEflh zsNgpo_N_b2JQs;ghqX;Z-l_WxM`63L;c2!YTrPO<0nqTEPhW{D3EuSfi-Rj9rVU>$ zWioH+z7$@HYPK0)M<>#K;O$);EESJn=V5b!e77JDrV-Te!D9_*1IOG_dcj0$E{s3N zmijdyVC#Y4&^}^os)QVdmkgBXnQ1$Y=RLRq4x_5Ao6?D)>2XV}Ep^dJ=Z<8DiB!j$kun>E1IDLS8lHMRe40%V8 zkv!Bvc5$f>PUlF{x2?yWPfya%yy;u%4oeZuKA)a?$h=cR*+W1kb6~h0hYrN)B37nD zbo@YUI#eIb4ZuXPggnjwb_5P=8vi}xc*&~%;YDK831lYC*U=ZJ@I5XKedC-L z72q2_89V0B(4P&-;5j(}@U8KjvzlsVpjg%Kdn`yC%GlKZDGQ_AeNGQ77~fd(>REVJ zn*rS;X7zdQ#uL$pAx}oV5s%Y##$XMQ!rOk`laCp{hkeMM zuV9odkM|?q*EfI|s9A9ANiNdj{OZ2{6#&(+;U%r=jMZescVlZ!sIw7u!*w$oAx87gQ;{qbPwie zBD`I}{lke5CHNlaRExhN zQoX5t?`QNTqp%kZVjhA@0)H2svQc(m(xWbrTv7et(+gx0 zLEZTK#vtSn_l(|tFmZh;{O%dOcapph2ELLYhHjl+)%(2n!#U6TcIWqeNSptwZw}mZ z0+m!x2h6kBt>3y2b9ckWX_Q5vZ;JOo&Bi!-hJZWt(le7h77)2{7ZZV8T`HbT8C49-SU0-mxy{XK$JJMCmQR5 zAACeJA~SqGH}u3mZYs$9tAU6``PU#`mdVfn<`;moJz6E*P?!f9yI*d-OKy&r}gt%RsDK@9u`TF-Zn}JLlBN> zO7O}s3~m4!fsHAI3OkcTj~JjXVE+}du|2t=F1YPO;%OdP2K>pMiW0sO{y=&+n;;^}wJURuyYm{z_IGhHeCgpT$@_hq-{ zD6r&bJo4K*+b9?&_s<6tfSe5j=^HM(a>4M^*#3p|2eQ`eO+Jh5P5vS~QwvCzhvaed zX_h>nGI}4u5HvK?xZXkIO0y_t4wcDsXmxlF-TJMApLzZq{S5Qx1bDKQsBLIZ!ZL@i zyg&9q+~nEw>wnzj!Ps-dCg$Ol^AD^i`)I0|+?Tqw3Wi+tc}yy=#R<~n)#pNsipc>o zq5N6=a@~`@!BE^YQ5b&fMo6)L8pZokHY27_9Hb~+G(@%4=4!6exBz^jDvK8mxqP<-Lt6c=r#Sicdm^|tJOewp?#zg&0+zogv8 zFS#4|CBGM!yT6&T6Bp6Iwr%IvMoXNhFF;J6$zpYfbZ9DJH7Q|DN zS^vJ2`*j{yo+te!7kfQiYh5$EQz87*nhz}oM-9A;PYq~#^(fbDM_a+ zPrh}jaJdYhk8jCiD{clJ`Ld#iTHXbYSOlS5@^-}4j}j@#XWV`B6UXnz^0`+(`al(P zpDRv*v6>h<;M<$r^9g0S{(OCmyo;gcCr@>69*PH&kJ0WaTqpPK-~!4Y^&r&QR1x}JuER{q*^F*jRs@$eRcH6wX84;%hrbZrAE_Pn?at#g5zrKkVa$Cgc!m{HTbJ%S544F3(?M|3 zRjHcVbax6ehLeYXqdG&kMMR)DeVD%+PMW`mPBDMsUxXWw-trcnn1-Xq;P!|4jDcf; z9D204%9Dy5df&w@dOxT3C=NHkmxxJpzY{)~;g#of|_;$R%=!C@Q+lKhST z6sK4ymmH3v+~ZshM-hh^&iRe4E9iMTa*@vUm8~QbD+o>Dpn)^x)GJ1~KC1dgYRE#~ zM?GWhIRV2iqw48vnyvn{P<9TQ#8{lA>c5`ERIJ5hoFN+e>)_wW7I>lOh}hKsD9r?` zCe8bzIA4dO)4xyJ(^E=Q!21;5Q!%AsX~vH3tU%3Kv*uv?M)fLQd-O#yQ~R!Ks`$yA zkF?GcuGDH@f1dVb*D>wOp5@i+_1$oeGp_)DCr>O4{u)Yk8{J^pDchSu&8hKDt%X=GRCkcP6|2E5Io17wstd07zt)OrC3=|sfRhS2j=bTuy;^?OfHOAaN8N5c= z+`w>Q)bel72& zyIt>#HG84avf5cLnq&S1(kkeWQ$m5WxAe8QFe*%wqhJARjv-_&5rU3j6hhBa?F7+S zNvR;EN-0HSVa!9ya1^_OXQU{@6XgH1E1z#YBRP=bs6Sx6ehtKzc`~7H`NQ(M2c?Io zX0eFe0JaVY;NBDhN(jA(;qChtm}pzO4OZogG=|=c>!pe{a>b>ho_qzi4uCX=Uh?+^ z;WLEXW2asMyg&wQuq~57#6#GIRofQIcVm4a&t*82i)u#NA+#L=2{ur@KD0@~<@r)G z_Ce6d@>ZHkobIRoTcSGSVu0!g!VcA=92v9S2UKf2>_7pWG{IghqLu&n;u zcuA%2nb4dAzK_ny_*x6(GO%!3&xhpQ&G<$wZn4h-8nC~DIMB;0_%p?94{rSnu@}=# z31h05y_V;sV@rhRWLm}SUY?a@^&4jdByX?et6AR4d2oHOf4jtlf1%`sa>p<*q1+QZ zW_;~P=5Z>I(|Mf9;~6|A+clKCp2ur>+|6STkDWXwS2=cjd2HtK4Ll}E3+0laVsDqn zMjq3nUnqAWk85~b$zvUlOL^$$K>aXII#Z8sxyL{1e)Z)e>w*a zESQ`NJ8>Fg@-xYSFbBfF9f!RLb{|6C4-;5kfU)k*4(48MWo`JGHT>WmYj-o&*5O7l z(GRaNdz*u;=ybAn=St@6TFF-0t<3GVGq=stNx13Sfh*n0Nj5D_N6B*C3Ws@3xz1Kt zu2!haghm^FMbGjTuf^@Lm<20d$Q zWkSd5MaFr`0#$)h$fI|Ul+ByxHm$-h_L*!2U5>7mUETtRYvnxrmS4N2&EuZevD)su zVjR9|M^_gL?T)T8p}NE2w#enk_gK0-`HL-GD?PR{fe2XG*huXug(8JgxCTE9xTw?F zVd(^z#T<(^0;g6eg!v}3P%rg53=>nX78Vd6=r;yA2f`rHwhDn`$<^cY6=z6;LO4AQ zRQ_o+D1>n|gn8pxo=euo= zwi{QQR$20`kV0Fuk}L)Bb$R;`-zZpoc|7iR2#CAQWp{d_@Pzi%bsTLTiznahaal~A zr>kS{G_ACNdd!$OPK?Jb!C_9tA&YNcf@ybJR>lHN1cNyl3o@=B5+2Oi)4*{4(Nvq3 zX6Sa>T^4tlu)t-XD<~C0mD5FoUn(foWeNrUg)3_tr==NPrj?zhGKg({o2ku)ITIat zd5lixX-qrgpf`(EOo5P&5WKaD4Ipem=tihP$dtozKi)Tluo1zDuna+skcBX^p^6ArfEiRfH!pvOvOu=e` z$}kHikI-T7vIx0m`d!jocT`WBEgcq*MZn9Iq)%H}i>1YES=C~7S%AplZt=M6rj8a9 z^xi5 znras;T5M;IQg*;4iZyR*6n||4| zm9J5=uMnt=Dn~F$2rspFwRL#S7Gb6YUtpUV2Nf+Rrp^QP9D-MlmRa4=T*ekigX?h! zZNv|Yv`(S{yjQEh)9IWU?hLR*GLb%IJ?hA~iZZppCiP?W3dUkNEttB@f}6j27E7bU zWw*FvigbS16;gK(GaYexsKJE82Pt$!mnmt?tWX&;j0Vl|>6w z@)g(Zw6yV8lFb!J|E;uiNyM2v9!sawBX}G!2+%%oxL4afZ8jm_igk~_k)F3sFESJI zFuo>lheyEA2ZsfsZRU7;gZdGJr>zX#uz(9~-VPdVDAP82T^f4jaBcDLC&?PiYvwTrb}Bb-DTuZt>I**gWJ#e;TD;70r> zUud(t+DwE&1q@N63vxE)?s8>Cudti=^yQPx9z;TXpn zu6cV~FTVfMTTb$G9VR=T-4*F0AsWa{p@SiIKFm0`dlw+A{gcKMMOR_Fw-5wMaizfRB# zH^*QFEg*zu=BcQN1tuEkep(txcbQg8Gnf_#ArEWwiZvdK`-*t7*}8Bg^qWYJ5)-DJ z=ksRV_M0pYYaU-ZbAc%z9SlRsnZlft^THsEufw_S$o)h-;esIpO6-Vd2zrLKg}T#b zGr8isBds_jjbOF6%WYrTg}Fj-f=u4Y44$|S-a;jqy`7zFTJciLm0cJb3{0+B9%HbI ze+uTcFfNR^!^lE2AFojbbSrRpa8E6InKN?l zL7Bkx_!E%V3g|8bs$~K#c6JlW&Ed|(T${RX?1Jep)JvgYXp;vyf*?S1Af2WB&;^U7;v~;UMCzQks6Fu2~^x6;MK2o(+aHd1n8wFgB2Ex zp+&HJc$U2jYab@oO>woywRx&WKwB03N|@nTflPwC6GXx4WE|3>01{=IIz z3>e@hnNq?>AVhIYEwcq)NEZ-tw&IB~0>ljpJ~&cYOeLp-1`Y!rSJ?z(3+!@XL?=M< z8TexRFZdxabl~9A1x{6*FUaZNhNs59W1#Bg}JoVw36R#q7H@*Gx-x^uaBx2WlN= zFJ>!$aWi2J=P!_r-Ed3w&^}!(pEW|abaLH;)A_izu^XX*7C`IRp?AE{Q>2$JWx3Ek z0^kLtqOFFpF(%<7eRVQ61F*QDZC%inX>1yBG;y6s`j)VhE*5|vo@!{s4z#@n_w}Hy z8rNFDxbbIVE0H=K%cOCOjE&G`fwkb36=Zk}qa^cGc&sg^@tRTAmzbZl>~cGu&+EuU z!5~N4ieLPI87nRSqejXF#(hgX$BDSZj0k}W<*u!0+h5OBdQ@Q)&FMld7j5a>f+cBe1Fhd&8OBqAgs zkYBSEGt`0E4C#oz1Rb3WT{xD`2N6_@7d~D#qojBKcRK zjfp;Fw^-1s8L<^}(Tnl*pl#9*ZG7h1IbGxH{$uSfvWm!3>VOSKJuf}2^;OFnn32`6 z`Aq6}0n&@{7yh`AFxJdpg6I2Ym@u#_EJajiKr5@zC(>D6T%S>^H9UuUOZv(M9Tod& zU`wDi8`)BZcXR+l3-p#9u!O^nU`4GK*33EO1^+rg8(Dy)^&BW63JVZgkWYLj+mPTJ zVjGD`*IQQdEwHOC5*@g&^IBYM&=If2(7lvEkw<+4h?D^jJuqVJV~gZ@8qbdy^pnYd zF$d}!Y8q6XSwnR%yjs2a!!_I1OucP0>4EC97DG!7_6HVVf1ti`NkdB`-yf)w_6Neb z*dJJAY*{KjUslueWeq)FE?smDo-b<~nyc}AxyaaBbq3FuHI^0Ll`XY!8ZBrb<=+Ym zvc14*UhyyH&}8%f4jeE{o^APe7^X=Y{|`7YcXBTLA8`5KqY1p1j=#4QZ|~$+x=+5U zid~FApK$rEnDSXms@QCVQNHWg>XN@od`bxu7AX5E&6vW!d(bIKzIn@ zF@(Jc?Fb_XV+d2wW)6Y^p%S4Up#`BG!G*9E;Re7pB2*&GMo2?QL>L2a-bOfza2Vkr z!ZQf{2s;rTM7R&(E`&P}HXz)BunM6AVFki6gliCL5OfHy0PjEgGdZ6BS>w4lxxwP8 z_PS{2rY3y4tP1Z0Pq=cz{KA9<_Ac`RyUXpN?Fm3u^PFq2T`Xl>ZK%J-uvk@CVD5lB z`JNPhlmzp|YVGj4@ixjCQzQ>G{Owa*aB!@`DVrTB);2mE&e%YTRW9C>Vx?0&m`$?F znmwFi>9%_qyLt+C`|;0M))aXB-4^6&DX+~5$J$FN*3~%N16-2f2z)-p>b6*JWSNAC*RLWN`h`ulkW$VSt{d5+q*lAfVPcmgv{u(Qw$?XR zw=TM7Q6oHd;eDik%myB8$3V(ZLm$B}kwnQzBhux7Tlf=KwZU7a`+WpRP>FA-#C zCpHZkTa(yol~Mx|B%L8>C66^@?m6g(C+fkXw!CcH5~FDb{WsBS+TO-;>3X;^ygS2uK+Zi z?5$|J)xz?D)#Yh5lWS=ujx^XDjvL|MPN*PQI?`mRto(A-vSrt@i#QiNE=Pye*@_L5 zcL>ia$BmZO)h3Ud9Q1?9tzH~`ZM%`J1BDP2Y(CP^UYpd)a}$$W<(x+9VVlM2X~m|k z89U8tiEmx(EoSJVO;@9|A<0G(7tzKf)wh@p-Pro=T4`awNN(t`Se)orOlh^F(}|7G z2oQTAaiPWJ1aB5~VWS*_#J3Tqr!2LbE!Zt~H9Bf(!*@PT@W8FV$j$w0V1ki$n!v}E zNs;nKN4OIEc~ZT}?xtoyKgU>`(jf^K=8Yi{Gt7uHmhx^7V--n@aT<8BeTB>9T7$9Z zPi_pemf)}>guIw}8P0qmxv5Ly4)t4VOBMz8Lz>^GEPjU7SYmnjqa^N-Hd$w?+~?(_ORfvr()=6a(XbF{G65p@BI2Vx(a-oOTfuNI=ZKy ziBsh>1q&^A*uK`!Y-(JPUpkXc_;;C2w07!euCcghR+QtLf%saXrE>)i{{TUkTR+q5 z>MFwtWebi-<#*cY^@Q$TWsh?Ra!0=TUJ>*gbs@JGfnPA+=Ot= z6ukDTHd+kzGp(i$w`C^2&=|oTUpaz52I8dFb@SqA)y<1^8r604!u%{h?T}3tPIBNs zmjjsztP;KZq9#X^tC_7)XlgXgn$~iA`A^G#UcRS%u>9rn*UR57Ur_Poiq49gDgqT- zD;})aUGYB^Z&v)Z0u_Y>witSUs-jI{S8P`tRJ@`XR{TYgs7zI!ue?~PP!=n%RMsl5 zSDKYx<;}|5l;2ivQ~p@_xbnBkmz94|jwnA+rW8&uyrQtYu%@u7@Y=!~3cCw$Dg0*P zU4>f;e_8lw;Y)>oD158%cwwgMJk@MfsYmE!D@W zRQ37li`28!b?WQY4z)+!qyC=ye)VtEhtz*jhtw%W7ZeFa^NNa!78ETmG8eTMtuK10 zXjjo-(ZQmjqDxBWlrAb=QrcE}XX$j!1saW}Lerq>(6}^rYVOuNteID4D621XlzGc` zmyMMrYo}^2)Xvo^wIy1!wq3hU`(N5ewZGARqD|6G)fMTqI*0C?x?Q?K-9g=;{(1dz z{rmc~@=MA~%8liR%HJ$ctvIJ*QAJ(FwH2m{jTLuS3{*T*@#hMrNMNPl<-Lj@E1pmc zD&9~WSA3+Hp}a_0sB8oWH!AN^KC1j*Wl))3cwyn?g{6h_3o}#()m5scs#{c|>Zht5 zs(#h~s9slnph{5BRTryoQ{SoHsotahgF3sYvFQ3DN0F!KmZCe0wiNxQ=;@+h(Yr-S z#b+017hhJaEY=oZTWl`&7Js$)j^ewDA1Xdj{7Ui1#VI8hlq@W1EV-eiqoli}wvoYW$k}HIHcqG;e7BstIXw%9P+xOWC)}epL2E+3RJ;$}ZNbwGG4|ox0!YMs-R02K|ltuj#kx|66}VKc>$rFDkDn_mg#(g!pyF^vu!2=4Fo-cbyD+v;`-uc#n+>s?ZwXGRmE$IzgD~v zz1>oLfARL>Uli{wexi7w_?hBYi;on)UHo40Sn=PAlS-zRWR{#)l2@WADK4ogSyJ-# zlJAskF1e>A}+1O5ZF^ z*PN%hNOP%1snLRaOEgP0of@}hjiyKQJkU3gw$abZQ_ zLd?9j!fzMqFt_ej{YdquDo1TpH>rozNkwTzSMXW$<)YRiOHohJw~96wZ7=#o(axeL ziUx|FDSEExP|@o}e=PcQ(P+`fT%OJ?zPLEAIKNm`tS`Q@xS_Ze{9aXjb8%1cH;V5C zr@vluTglxeKPmZH$-^bHN*ha;mv)u*mWrj{FWp)Cc?aBPmIP;;f` zI?W2q#IIht{Z&cr<-U4m3UHuEp$S2eT>Sxq!eFDy# z!Ox=1RA&|SYX`K0+Wp!C+Jo9d+QZr*?NMz|JEA?V9o3F$PiW!x)urmvb(y*>-3-hk zK{rd6r&H)kb(Ok>I-_ox?gpJr=hSuU*6TLt?$B-4Z2=$H9SJN8ZFrEs7A3tXV_On% z-jK0WWx6s`nWdbe6qK`+$4gF><>&>yPG6~S(chq7ufJQrMb92ekiK^f +#include + + + +// TODO: reference additional headers your program requires here diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/targetver.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/targetver.h new file mode 100644 index 000000000..90e767bfc --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata/targetver.h @@ -0,0 +1,8 @@ +#pragma once + +// Including SDKDDKVer.h defines the highest available Windows platform. + +// If you wish to build your application for a previous Windows platform, include WinSDKVer.h and +// set the _WIN32_WINNT macro to the platform you wish to support before including SDKDDKVer.h. + +#include diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/lwIP_Apps.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/lwIP_Apps.c new file mode 100644 index 000000000..737348182 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/lwIP_Apps.c @@ -0,0 +1,262 @@ +/* + FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd. + + + *************************************************************************** + * * + * FreeRTOS tutorial books are available in pdf and paperback. * + * Complete, revised, and edited pdf reference manuals are also * + * available. * + * * + * Purchasing FreeRTOS documentation will not only help you, by * + * ensuring you get running as quickly as possible and with an * + * in-depth knowledge of how to use FreeRTOS, it will also help * + * the FreeRTOS project to continue with its mission of providing * + * professional grade, cross platform, de facto standard solutions * + * for microcontrollers - completely free of charge! * + * * + * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * + * * + * Thank you for using FreeRTOS, and thank you for your support! * + * * + *************************************************************************** + + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + >>>NOTE<<< The modification to the GPL is included to allow you to + distribute a combined work that includes FreeRTOS without being obliged to + provide the source code for proprietary components outside of the FreeRTOS + kernel. FreeRTOS is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* lwIP core includes */ +#include "lwip/opt.h" +#include "lwip/tcpip.h" +#include "lwip/inet.h" + +/* applications includes */ +#include "apps/httpserver_raw_from_lwIP_download/httpd.h" + +/* include the port-dependent configuration */ +#include "lwipcfg_msvc.h" + +/* Dimensions the cTxBuffer array - which is itself used to hold replies from +command line commands. cTxBuffer is a shared buffer, so protected by the +xTxBufferMutex mutex. */ +#define lwipappsTX_BUFFER_SIZE 1024 + +/* The maximum time to block waiting to obtain the xTxBufferMutex to become +available. */ +#define lwipappsMAX_TIME_TO_WAIT_FOR_TX_BUFFER_MS ( 100 / portTICK_RATE_MS ) + +/* Definitions of the various SSI callback functions within the pccSSITags +array. If pccSSITags is updated, then these definitions must also be updated. */ +#define ssiTASK_STATS_INDEX 0 +#define ssiRUN_TIME_STATS_INDEX 1 + +/*-----------------------------------------------------------*/ + +/* + * The function that implements the lwIP based sockets command interpreter + * server. + */ +extern void vBasicSocketsCommandInterpreterTask( void *pvParameters ); + +/* + * The SSI handler callback function passed to lwIP. + */ +static unsigned short uslwIPAppsSSIHandler( int iIndex, char *pcBuffer, int iBufferLength ); + +/*-----------------------------------------------------------*/ + +/* The SSI strings that are embedded in the served html files. If this array +is changed, then the index position defined by the #defines such as +ssiTASK_STATS_INDEX above must also be updated. */ +static const char *pccSSITags[] = +{ + "rtos_stats", + "run_stats" +}; + +/* Semaphore used to guard the Tx buffer. */ +static xSemaphoreHandle xTxBufferMutex = NULL; + +/* The Tx buffer itself. This is used to hold the text generated by the +execution of command line commands, and (hopefully) the execution of +server side include callbacks. It is a shared buffer so protected by the +xTxBufferMutex mutex. pcLwipAppsBlockingGetTxBuffer() and +vLwipAppsReleaseTxBuffer() are provided to obtain and release the +xTxBufferMutex respectively. pcLwipAppsBlockingGetTxBuffer() must be used with +caution as it has the potential to block. */ +static signed char cTxBuffer[ lwipappsTX_BUFFER_SIZE ]; + +/*-----------------------------------------------------------*/ + +void vStatusCallback( struct netif *pxNetIf ) +{ +char pcMessage[20]; + + if( netif_is_up( pxNetIf ) != 0 ) + { + strcpy( pcMessage, "IP=" ); + strcat( pcMessage, inet_ntoa( *( struct in_addr* ) &( pxNetIf->ip_addr ) ) ); + xil_printf( pcMessage ); + } + else + { + xil_printf( "Network is down" ); + } +} + +/* Called from the TCP/IP thread. */ +void lwIPAppsInit( void *pvArgument ) +{ +ip_addr_t xIPAddr, xNetMask, xGateway; +extern err_t xemacpsif_init( struct netif *netif ); +extern void xemacif_input_thread( void *netif ); +static struct netif xNetIf; + + ( void ) pvArgument; + + /* Set up the network interface. */ + ip_addr_set_zero( &xGateway ); + ip_addr_set_zero( &xIPAddr ); + ip_addr_set_zero( &xNetMask ); + + LWIP_PORT_INIT_GW(&xGateway); + LWIP_PORT_INIT_IPADDR( &xIPAddr ); + LWIP_PORT_INIT_NETMASK(&xNetMask); + + /* Set mac address */ + xNetIf.hwaddr_len = 6; + xNetIf.hwaddr[ 0 ] = configMAC_ADDR0; + xNetIf.hwaddr[ 1 ] = configMAC_ADDR1; + xNetIf.hwaddr[ 2 ] = configMAC_ADDR2; + xNetIf.hwaddr[ 3 ] = configMAC_ADDR3; + xNetIf.hwaddr[ 4 ] = configMAC_ADDR4; + xNetIf.hwaddr[ 5 ] = configMAC_ADDR5; + + netif_set_default( netif_add( &xNetIf, &xIPAddr, &xNetMask, &xGateway, ( void * ) XPAR_XEMACPS_0_BASEADDR, xemacpsif_init, tcpip_input ) ); + netif_set_status_callback( &xNetIf, vStatusCallback ); + #if LWIP_DHCP + { + dhcp_start( &xNetIf ); + } + #else + { + netif_set_up( &xNetIf ); + } + #endif + + /* Install the server side include handler. */ + http_set_ssi_handler( uslwIPAppsSSIHandler, pccSSITags, sizeof( pccSSITags ) / sizeof( char * ) ); + + /* Create the mutex used to ensure mutual exclusive access to the Tx + buffer. */ + xTxBufferMutex = xSemaphoreCreateMutex(); + configASSERT( xTxBufferMutex ); + + /* Create the httpd server from the standard lwIP code. This demonstrates + use of the lwIP raw API. */ + httpd_init(); + + sys_thread_new( "lwIP_In", xemacif_input_thread, &xNetIf, configMINIMAL_STACK_SIZE, configMAC_INPUT_TASK_PRIORITY ); + + /* Create the FreeRTOS defined basic command server. This demonstrates use + of the lwIP sockets API. */ + xTaskCreate( vBasicSocketsCommandInterpreterTask, "CmdInt", configMINIMAL_STACK_SIZE * 5, NULL, configCLI_TASK_PRIORITY, NULL ); +} +/*-----------------------------------------------------------*/ + +static unsigned short uslwIPAppsSSIHandler( int iIndex, char *pcBuffer, int iBufferLength ) +{ +static unsigned int uiUpdateCount = 0; +static char cUpdateString[ 200 ]; +extern char *pcMainGetTaskStatusMessage( void ); + + /* Unused parameter. */ + ( void ) iBufferLength; + + /* The SSI handler function that generates text depending on the index of + the SSI tag encountered. */ + + switch( iIndex ) + { + case ssiTASK_STATS_INDEX : + vTaskList( pcBuffer ); + break; + + case ssiRUN_TIME_STATS_INDEX : + vTaskGetRunTimeStats( pcBuffer ); + break; + } + + /* Include a count of the number of times an SSI function has been executed + in the returned string. */ + uiUpdateCount++; + sprintf( cUpdateString, "\r\n\r\n%u\r\nStatus - %s", uiUpdateCount, pcMainGetTaskStatusMessage() ); + strcat( pcBuffer, cUpdateString ); + + return strlen( pcBuffer ); +} +/*-----------------------------------------------------------*/ + +signed char *pcLwipAppsBlockingGetTxBuffer( void ) +{ +signed char *pcReturn; + + /* Attempt to obtain the semaphore that guards the Tx buffer. */ + if( xSemaphoreTakeRecursive( xTxBufferMutex, lwipappsMAX_TIME_TO_WAIT_FOR_TX_BUFFER_MS ) == pdFAIL ) + { + /* The semaphore could not be obtained before timing out. */ + pcReturn = NULL; + } + else + { + /* The semaphore was obtained successfully. Return a pointer to the + Tx buffer. */ + pcReturn = cTxBuffer; + } + + return pcReturn; +} +/*-----------------------------------------------------------*/ + +void vLwipAppsReleaseTxBuffer( void ) +{ + /* Finished with the Tx buffer. Return the mutex. */ + xSemaphoreGiveRecursive( xTxBufferMutex ); +} + + + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/lwIP_Apps.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/lwIP_Apps.h new file mode 100644 index 000000000..cf6fd02a2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/lwIP_Apps.h @@ -0,0 +1,62 @@ +/* + FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd. + + + *************************************************************************** + * * + * FreeRTOS tutorial books are available in pdf and paperback. * + * Complete, revised, and edited pdf reference manuals are also * + * available. * + * * + * Purchasing FreeRTOS documentation will not only help you, by * + * ensuring you get running as quickly as possible and with an * + * in-depth knowledge of how to use FreeRTOS, it will also help * + * the FreeRTOS project to continue with its mission of providing * + * professional grade, cross platform, de facto standard solutions * + * for microcontrollers - completely free of charge! * + * * + * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * + * * + * Thank you for using FreeRTOS, and thank you for your support! * + * * + *************************************************************************** + + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + >>>NOTE<<< The modification to the GPL is included to allow you to + distribute a combined work that includes FreeRTOS without being obliged to + provide the source code for proprietary components outside of the FreeRTOS + kernel. FreeRTOS is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. You should have received a copy of the GNU General Public + License and the FreeRTOS license exception along with FreeRTOS; if not it + can be viewed here: http://www.freertos.org/a00114.html and also obtained + by writing to Richard Barry, contact details for whom are available on the + FreeRTOS WEB site. + + 1 tab == 4 spaces! + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ +#ifndef LWIP_APPS_H +#define LWIP_APPS_H + +/* Functions used to obtain and release exclusive access to the Tx buffer. The +Get function will block if the Tx buffer is not available - use with care! */ +signed char *pcLwipAppsBlockingGetTxBuffer( void ); +void vLwipAppsReleaseTxBuffer( void ); + +#endif /* LWIP_APPS_H */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/lwipcfg_msvc.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/lwipcfg_msvc.h new file mode 100644 index 000000000..fa35c3c99 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_Apps/lwipcfg_msvc.h @@ -0,0 +1,46 @@ +/** + * Additional settings for the win32 port. + * Copy this to lwipcfg_msvc.h and make the config changes you need. + */ + +/* configuration for this port */ +#define PPP_USERNAME "Admin" +#define PPP_PASSWORD "pass" + + +/** Define this to the GUID of the windows network adapter to use + * or NOT define this if you want PACKET_LIB_ADAPTER_NR to be used */ +/*#define PACKET_LIB_ADAPTER_GUID "00000000-0000-0000-0000-000000000000"*/ +/*#define PACKET_LIB_GET_ADAPTER_NETADDRESS(addr) IP4_ADDR((addr), 192,168,1,0)*/ +/*#define PACKET_LIB_QUIET*/ + +#define LWIP_PORT_INIT_IPADDR(addr) IP4_ADDR((addr), configIP_ADDR0,configIP_ADDR1,configIP_ADDR2,configIP_ADDR3) +#define LWIP_PORT_INIT_GW(addr) IP4_ADDR((addr), 192,168,0,3) +#define LWIP_PORT_INIT_NETMASK(addr) IP4_ADDR((addr), 255,255,255,0) + +/* remember to change this MAC address to suit your needs! + the last octet will be increased by netif->num for each netif */ +#define LWIP_MAC_ADDR_BASE {0x00,0x01,0x02,0x03,0x04,0x05} + +/* configuration for applications */ + +#define LWIP_CHARGEN_APP 0 +#define LWIP_DNS_APP 0 +#define LWIP_HTTPD_APP 1 +/* Set this to 1 to use the netconn http server, + * otherwise the raw api server will be used. */ +/*#define LWIP_HTTPD_APP_NETCONN */ +#define LWIP_NETBIOS_APP 0 +#define LWIP_NETIO_APP 0 +#define LWIP_PING_APP 0 +#define LWIP_RTP_APP 0 +#define LWIP_SHELL_APP 0 +#define LWIP_SNTP_APP 0 +#define LWIP_SOCKET_EXAMPLES_APP 0 +#define LWIP_TCPECHO_APP 0 +/* Set this to 1 to use the netconn tcpecho server, + * otherwise the raw api server will be used. */ +/*#define LWIP_TCPECHO_APP_NETCONN */ +#define LWIP_UDPECHO_APP 0 + + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/arch/bpstruct.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/arch/bpstruct.h new file mode 100644 index 000000000..1d81e3f7b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/arch/bpstruct.h @@ -0,0 +1 @@ +#pragma pack(push,1) diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/arch/cc.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/arch/cc.h new file mode 100644 index 000000000..8c64b5d43 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/arch/cc.h @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __ARCH_CC_H__ +#define __ARCH_CC_H__ + +#if 1 +/* Include some files for defining library routines */ +#include /* printf, fflush, FILE */ +#include /* abort */ +#else +/* Declare fuction prototypes for assert/diag/error - leads to some warnings, + * but good to test if no includes are missing. */ +int printf(const char *format, ...); +void abort(void); +struct _iobuf; +typedef struct _iobuf FILE; +int fflush(FILE *stream); +#endif + + + +/** @todo fix some warnings: don't use #pragma if compiling with cygwin gcc */ +#ifndef __GNUC__ +#include +#pragma warning (disable: 4244) /* disable conversion warning (implicit integer promotion!) */ +#pragma warning (disable: 4127) /* conditional expression is constant */ +#pragma warning (disable: 4996) /* 'strncpy' was declared deprecated */ +#pragma warning (disable: 4103) /* structure packing changed by including file */ +#endif + +#define LWIP_PROVIDE_ERRNO + +/* Define platform endianness (might already be defined) */ +#ifndef BYTE_ORDER +#define BYTE_ORDER LITTLE_ENDIAN +#endif /* BYTE_ORDER */ + +/* Define generic types used in lwIP */ +typedef unsigned char u8_t; +typedef signed char s8_t; +typedef unsigned short u16_t; +typedef signed short s16_t; +typedef unsigned long u32_t; +typedef signed long s32_t; + +typedef size_t mem_ptr_t; +typedef u32_t sys_prot_t; + +/* Define (sn)printf formatters for these lwIP types */ +#define X8_F "02x" +#define U16_F "hu" +#define S16_F "hd" +#define X16_F "hx" +#define U32_F "lu" +#define S32_F "ld" +#define X32_F "lx" +#define SZT_F U32_F + +/* Compiler hints for packing structures */ +#define PACK_STRUCT_STRUCT +#define PACK_STRUCT_USE_INCLUDES + +/* Plaform specific diagnostic output */ +#define LWIP_PLATFORM_DIAG(x) do { printf x; } while(0) + +#define LWIP_PLATFORM_ASSERT(x) do { printf("Assertion \"%s\" failed at line %d in %s\n", \ + x, __LINE__, __FILE__); fflush(NULL); abort(); } while(0) + +#define LWIP_ERROR(message, expression, handler) do { if (!(expression)) { \ + printf("Assertion \"%s\" failed at line %d in %s\n", message, __LINE__, __FILE__); \ + fflush(NULL);handler;} } while(0) + +/* C runtime functions redefined */ +#define snprintf _snprintf + +u32_t dns_lookup_external_hosts_file(const char *name); + +#define LWIP_RAND() ((u32_t)rand()) + +#endif /* __ARCH_CC_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/arch/epstruct.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/arch/epstruct.h new file mode 100644 index 000000000..65898b54b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/arch/epstruct.h @@ -0,0 +1 @@ +#pragma pack(pop) diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/arch/perf.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/arch/perf.h new file mode 100644 index 000000000..089facac1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/arch/perf.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __PERF_H__ +#define __PERF_H__ + +#define PERF_START /* null definition */ +#define PERF_STOP(x) /* null definition */ + +#endif /* __PERF_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/arch/sys_arch.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/arch/sys_arch.h new file mode 100644 index 000000000..f9eae84db --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/arch/sys_arch.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __ARCH_SYS_ARCH_H__ +#define __ARCH_SYS_ARCH_H__ + +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "semphr.h" + +#define SYS_MBOX_NULL ( ( QueueHandle_t ) NULL ) +#define SYS_SEM_NULL ( ( SemaphoreHandle_t ) NULL ) +#define SYS_DEFAULT_THREAD_STACK_DEPTH configMINIMAL_STACK_SIZE + +typedef SemaphoreHandle_t sys_sem_t; +typedef SemaphoreHandle_t sys_mutex_t; +typedef QueueHandle_t sys_mbox_t; +typedef TaskHandle_t sys_thread_t; + +typedef unsigned long sys_prot_t; + +#define sys_mbox_valid( x ) ( ( ( *x ) == NULL) ? pdFALSE : pdTRUE ) +#define sys_mbox_set_invalid( x ) ( ( *x ) = NULL ) +#define sys_sem_valid( x ) ( ( ( *x ) == NULL) ? pdFALSE : pdTRUE ) +#define sys_sem_set_invalid( x ) ( ( *x ) = NULL ) + + +#endif /* __ARCH_SYS_ARCH_H__ */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/netif/xadapter.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/netif/xadapter.h new file mode 100644 index 000000000..3ce71b3b4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/netif/xadapter.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2007-2013 Xilinx, Inc. All rights reserved. + * + * Xilinx, Inc. + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR + * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION + * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE + * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO + * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE + * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#ifndef __XADAPTER_H_ +#define __XADAPTER_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "lwipopts.h" + +#if !NO_SYS +#ifdef OS_IS_XILKERNEL +#include "xmk.h" +#endif +#include "lwip/sys.h" +#endif + +#include "lwip/netif.h" +#include "lwip/ip.h" + +#include "netif/xtopology.h" + +struct xemac_s { + enum xemac_types type; + int topology_index; + void *state; +#if !NO_SYS + sys_sem_t sem_rx_data_available; +#endif +}; + +void lwip_raw_init(); +int xemacif_input(struct netif *netif); +void xemacif_input_thread(struct netif *netif); +struct netif * xemac_add(struct netif *netif, + struct ip_addr *ipaddr, struct ip_addr *netmask, struct ip_addr *gw, + unsigned char *mac_ethernet_address, + unsigned mac_baseaddr); +#ifdef __arm__ +void xemacpsif_resetrx_on_no_rxdata(struct netif *netif); +#endif + +/* global lwip debug variable used for debugging */ +extern int lwip_runtime_debug; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/netif/xaxiemacif.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/netif/xaxiemacif.h new file mode 100644 index 000000000..ae23f05df --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/netif/xaxiemacif.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2010-2013 Xilinx, Inc. All rights reserved. + * + * Xilinx, Inc. + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR + * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION + * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE + * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO + * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE + * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#ifndef __NETIF_XAXIEMACIF_H__ +#define __NETIF_XAXIEMACIF_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "xlwipconfig.h" +#include "lwip/netif.h" +#include "netif/etharp.h" +#include "netif/xadapter.h" + +#include "xparameters.h" +#include "xstatus.h" + +#include "xaxiethernet.h" +#ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET_FIFO +#include "xllfifo.h" +#else +#include "xaxidma.h" +#include "xaxidma_hw.h" +#endif + +#include "netif/xpqueue.h" +#include "xlwipconfig.h" + +void xaxiemacif_setmac(u32_t index, u8_t *addr); +u8_t* xaxiemacif_getmac(u32_t index); +err_t xaxiemacif_init(struct netif *netif); +int xaxiemacif_input(struct netif *netif); + +unsigned get_IEEE_phy_speed(XAxiEthernet *xaxiemacp); +unsigned configure_IEEE_phy_speed(XAxiEthernet *xaxiemacp, unsigned speed); +unsigned Phy_Setup (XAxiEthernet *xaxiemacp); + +/* xaxiemacif_hw.c */ +void xaxiemac_error_handler(XAxiEthernet * Temac); + +/* structure within each netif, encapsulating all information required for + * using a particular temac instance + */ +typedef struct { +#ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET_FIFO + XLlFifo axififo; +#else + XAxiDma axidma; +#endif + XAxiEthernet axi_ethernet; + + /* queue to store overflow packets */ + pq_queue_t *recv_q; + pq_queue_t *send_q; + + /* pointers to memory holding buffer descriptors (used only with SDMA) */ + void *rx_bdspace; + void *tx_bdspace; +} xaxiemacif_s; + +extern xaxiemacif_s xaxiemacif; + +int is_tx_space_available(xaxiemacif_s *emac); + +/* xaxiemacif_dma.c */ +#ifndef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET_FIFO +XStatus init_axi_dma(struct xemac_s *xemac); +int process_sent_bds(XAxiDma_BdRing *txring); + +void axidma_send_handler(void *arg); +XStatus axidma_sgsend(xaxiemacif_s *xaxiemacif, struct pbuf *p); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __NETIF_XAXIEMACIF_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/netif/xemacliteif.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/netif/xemacliteif.h new file mode 100644 index 000000000..8c2918906 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/netif/xemacliteif.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2007-2013 Xilinx, Inc. All rights reserved. + * + * Xilinx, Inc. + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR + * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION + * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE + * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO + * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE + * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#ifndef __NETIF_XEMACLITEIF_H__ +#define __NETIF_XEMACLITEIF_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "lwip/netif.h" +#include "netif/etharp.h" +#include "netif/xpqueue.h" +#include "xemaclite.h" +#include "xemaclite_i.h" +#include "xstatus.h" + +/* structure within each netif, encapsulating all information required for + * using a particular emaclite instance + */ +typedef struct { + XEmacLite *instance; + + /* queue to store overflow packets */ + pq_queue_t *recv_q; + pq_queue_t *send_q; +} xemacliteif_s; + +void xemacliteif_setmac(u32_t index, u8_t *addr); +u8_t* xemacliteif_getmac(u32_t index); +err_t xemacliteif_init(struct netif *netif); +int xemacliteif_input(struct netif *netif); + +#ifdef __cplusplus +} +#endif + +#endif /* __NETIF_XEMACLITEIF_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/netif/xemacpsif.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/netif/xemacpsif.h new file mode 100644 index 000000000..f07f018b4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/netif/xemacpsif.h @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2010-2013 Xilinx, Inc. All rights reserved. + * + * Xilinx, Inc. + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR + * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION + * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE + * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO + * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE + * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#ifndef __NETIF_XEMACPSIF_H__ +#define __NETIF_XEMACPSIF_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "xlwipconfig.h" +#include "lwip/netif.h" +#include "netif/etharp.h" +#include "netif/xadapter.h" + +#include "xstatus.h" +#include "sleep.h" +#include "xparameters.h" +#include "xparameters_ps.h" /* defines XPAR values */ +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" +#include "xil_exception.h" +#include "xpseudo_asm.h" +#include "xil_cache.h" +#include "xil_printf.h" +#include "xuartps.h" +#include "xscugic.h" +#include "xemacps.h" /* defines XEmacPs API */ + +#include "netif/xpqueue.h" +#include "xlwipconfig.h" + +void xemacpsif_setmac(u32_t index, u8_t *addr); +u8_t* xemacpsif_getmac(u32_t index); +err_t xemacpsif_init(struct netif *netif); +int xemacpsif_input(struct netif *netif); +#ifdef NOTNOW_BHILL +unsigned get_IEEE_phy_speed(XLlTemac *xlltemacp); +#endif + +/* xaxiemacif_hw.c */ +void xemacps_error_handler(XEmacPs * Temac); + +/* structure within each netif, encapsulating all information required for + * using a particular temac instance + */ +typedef struct { + XEmacPs emacps; + + /* queue to store overflow packets */ + pq_queue_t *recv_q; + pq_queue_t *send_q; + + /* pointers to memory holding buffer descriptors (used only with SDMA) */ + void *rx_bdspace; + void *tx_bdspace; + + unsigned int last_rx_frms_cntr; + +} xemacpsif_s; + +extern xemacpsif_s xemacpsif; + +int is_tx_space_available(xemacpsif_s *emac); + +/* xaxiemacif_dma.c */ + +XStatus init_axi_dma(struct xemac_s *xemac); +void process_sent_bds(XEmacPs_BdRing *txring); +unsigned Phy_Setup (XEmacPs *xemacpsp); +void emacps_send_handler(void *arg); +XStatus emacps_sgsend(xemacpsif_s *xemacpsif, struct pbuf *p); +void emacps_recv_handler(void *arg); +void emacps_error_handler(void *arg,u8 Direction, u32 ErrorWord); +void setup_rx_bds(XEmacPs_BdRing *rxring); +void HandleTxErrors(struct xemac_s *xemac); +void HandleEmacPsError(struct xemac_s *xemac); +XEmacPs_Config *xemacps_lookup_config(unsigned mac_base); +void init_emacps(xemacpsif_s *xemacps, struct netif *netif); +void setup_isr (struct xemac_s *xemac); +XStatus init_dma(struct xemac_s *xemac); +void start_emacps (xemacpsif_s *xemacps); +void FreeTxRxPBufs(void); +void FreeOnlyTxPBufs(void); +void init_emacps_on_error (xemacpsif_s *xemacps, struct netif *netif); +void clean_dma_txdescs(struct xemac_s *xemac); +void resetrx_on_no_rxdata(xemacpsif_s *xemacpsif); + +#ifdef __cplusplus +} +#endif + +#endif /* __NETIF_XAXIEMACIF_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/netif/xlltemacif.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/netif/xlltemacif.h new file mode 100644 index 000000000..1fc82da66 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/netif/xlltemacif.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2007-2013 Xilinx, Inc. All rights reserved. + * + * Xilinx, Inc. + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR + * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION + * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE + * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO + * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE + * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#ifndef __NETIF_XLLTEMACIF_H__ +#define __NETIF_XLLTEMACIF_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "lwip/netif.h" +#include "netif/etharp.h" +#include "netif/xadapter.h" + +#include "xparameters.h" +#include "xstatus.h" +#include "xlltemac.h" +#include "xlldma.h" +#include "xllfifo.h" +#include "xlldma_bdring.h" + +#include "netif/xpqueue.h" +#include "xlwipconfig.h" + +void xlltemacif_setmac(u32_t index, u8_t *addr); +u8_t* xlltemacif_getmac(u32_t index); +err_t xlltemacif_init(struct netif *netif); +int xlltemacif_input(struct netif *netif); +unsigned get_IEEE_phy_speed(XLlTemac *xlltemacp); +unsigned Phy_Setup (XLlTemac *xlltemacp); +unsigned configure_IEEE_phy_speed(XLlTemac *xlltemacp, unsigned speed); + +/* xlltemacif_hw.c */ +void xlltemac_error_handler(XLlTemac * Temac); + +/* structure within each netif, encapsulating all information required for + * using a particular temac instance + */ +typedef struct { + XLlDma lldma; + XLlFifo llfifo; + XLlTemac lltemac; + + /* queue to store overflow packets */ + pq_queue_t *recv_q; + pq_queue_t *send_q; + + /* pointers to memory holding buffer descriptors (used only with SDMA) */ + void *rx_bdspace; + void *tx_bdspace; +} xlltemacif_s; + +extern xlltemacif_s xlltemacif; + +/* xlltemacif_sdma.c */ +XStatus init_sdma(struct xemac_s *xemac); +int process_sent_bds(XLlDma_BdRing *txring); +void lldma_send_handler(void *arg); +XStatus lldma_sgsend(xlltemacif_s *xlltemacif, struct pbuf *p); + +#ifdef __cplusplus +} +#endif + +#endif /* __NETIF_XLLTEMACIF_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/netif/xpqueue.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/netif/xpqueue.h new file mode 100644 index 000000000..fe89d278e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/netif/xpqueue.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2007-2013 Xilinx, Inc. All rights reserved. + * + * Xilinx, Inc. + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR + * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION + * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE + * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO + * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE + * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#ifndef __LWIP_PBUF_QUEUE_H_ +#define __LWIP_PBUF_QUEUE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define PQ_QUEUE_SIZE 4096 + +typedef struct { + void *data[PQ_QUEUE_SIZE]; + int head, tail, len; +} pq_queue_t; + +pq_queue_t* pq_create_queue(); +int pq_enqueue(pq_queue_t *q, void *p); +void* pq_dequeue(pq_queue_t *q); +int pq_qlength(pq_queue_t *q); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/netif/xtopology.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/netif/xtopology.h new file mode 100644 index 000000000..7620b96b9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/netif/xtopology.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2007-2013 Xilinx, Inc. All rights reserved. + * + * Xilinx, Inc. + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR + * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION + * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE + * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO + * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE + * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#ifndef __XTOPOLOGY_H_ +#define __XTOPOLOGY_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +enum xemac_types { xemac_type_unknown = -1, xemac_type_xps_emaclite, xemac_type_xps_ll_temac, xemac_type_axi_ethernet, xemac_type_emacps }; + +struct xtopology_t { + unsigned emac_baseaddr; + enum xemac_types emac_type; + unsigned intc_baseaddr; + unsigned intc_emac_intr; /* valid only for xemac_type_xps_emaclite */ + unsigned scugic_baseaddr; /* valid only for Zynq */ + unsigned scugic_emac_intr; /* valid only for GEM */ +}; + +extern int xtopology_n_emacs; +extern struct xtopology_t xtopology[]; + +int xtopology_find_index(unsigned base); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/xlwipconfig.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/xlwipconfig.h new file mode 100644 index 000000000..635a9e851 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/include/xlwipconfig.h @@ -0,0 +1,12 @@ +#ifndef __XLWIPCONFIG_H_ +#define __XLWIPCONFIG_H_ + + +/* This is a generated file - do not edit */ + +#define XLWIP_CONFIG_INCLUDE_GEM 1 +#define XLWIP_CONFIG_EMAC_NUMBER 0 +#define XLWIP_CONFIG_N_TX_DESC 64 +#define XLWIP_CONFIG_N_RX_DESC 64 + +#endif diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/netif/xadapter.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/netif/xadapter.c new file mode 100644 index 000000000..065746b18 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/netif/xadapter.c @@ -0,0 +1,274 @@ +/* + * Copyright (c) 2007-2013 Xilinx, Inc. All rights reserved. + * + * Xilinx, Inc. + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR + * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION + * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE + * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO + * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE + * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#include "lwipopts.h" +#include "xlwipconfig.h" + +#if !NO_SYS +#ifdef OS_IS_XILKERNEL +#include "xmk.h" +#include "sys/process.h" +#endif +#endif + +#include "lwip/mem.h" +#include "lwip/stats.h" +#include "lwip/sys.h" +#include "lwip/ip.h" +#include "lwip/tcp.h" +#include "lwip/udp.h" +#include "lwip/tcp_impl.h" + +#include "netif/etharp.h" +#include "netif/xadapter.h" + +#ifdef XLWIP_CONFIG_INCLUDE_EMACLITE +#include "netif/xemacliteif.h" +#endif + +#ifdef XLWIP_CONFIG_INCLUDE_TEMAC +#include "netif/xlltemacif.h" +#endif + +#ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET +#include "netif/xaxiemacif.h" +#endif + +#ifdef XLWIP_CONFIG_INCLUDE_GEM +#include "netif/xemacpsif.h" +#endif + +#if !NO_SYS +#include "lwip/tcpip.h" +#endif + + +/* global lwip debug variable used for debugging */ +int lwip_runtime_debug = 0; + +void +lwip_raw_init() +{ + ip_init(); /* Doesn't do much, it should be called to handle future changes. */ +#if LWIP_UDP + udp_init(); /* Clears the UDP PCB list. */ +#endif +#if LWIP_TCP + tcp_init(); /* Clears the TCP PCB list and clears some internal TCP timers. */ + /* Note: you must call tcp_fasttmr() and tcp_slowtmr() at the */ + /* predefined regular intervals after this initialization. */ +#endif +} + +static enum xemac_types +find_mac_type(unsigned base) +{ + int i; + + for (i = 0; i < xtopology_n_emacs; i++) { + if (xtopology[i].emac_baseaddr == base) + return xtopology[i].emac_type; + } + + return xemac_type_unknown; +} + +int +xtopology_find_index(unsigned base) +{ + int i; + + for (i = 0; i < xtopology_n_emacs; i++) { + if (xtopology[i].emac_baseaddr == base) + return i; + } + + return -1; +} + +/* + * xemac_add: this is a wrapper around lwIP's netif_add function. + * The objective is to provide portability between the different Xilinx MAC's + * This function can be used to add both xps_ethernetlite and xps_ll_temac + * based interfaces + */ +struct netif * +xemac_add(struct netif *netif, + struct ip_addr *ipaddr, struct ip_addr *netmask, struct ip_addr *gw, + unsigned char *mac_ethernet_address, + unsigned mac_baseaddr) +{ + int i; + + /* set mac address */ + netif->hwaddr_len = 6; + for (i = 0; i < 6; i++) + netif->hwaddr[i] = mac_ethernet_address[i]; + + /* initialize based on MAC type */ + switch (find_mac_type(mac_baseaddr)) { + case xemac_type_xps_emaclite: +#ifdef XLWIP_CONFIG_INCLUDE_EMACLITE + return netif_add(netif, ipaddr, netmask, gw, + (void*)mac_baseaddr, + xemacliteif_init, +#if NO_SYS + ethernet_input +#else + tcpip_input +#endif + ); +#else + return NULL; +#endif + case xemac_type_xps_ll_temac: +#ifdef XLWIP_CONFIG_INCLUDE_TEMAC + return netif_add(netif, ipaddr, netmask, gw, + (void*)mac_baseaddr, + xlltemacif_init, +#if NO_SYS + ethernet_input +#else + tcpip_input +#endif + ); +#else + return NULL; +#endif + case xemac_type_axi_ethernet: +#ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET + return netif_add(netif, ipaddr, netmask, gw, + (void*)mac_baseaddr, + xaxiemacif_init, +#if NO_SYS + ethernet_input +#else + tcpip_input +#endif + ); +#else + return NULL; +#endif +#ifdef __arm__ + case xemac_type_emacps: +#ifdef XLWIP_CONFIG_INCLUDE_GEM + return netif_add(netif, ipaddr, netmask, gw, + (void*)mac_baseaddr, + xemacpsif_init, +#if NO_SYS + ethernet_input +#else + tcpip_input +#endif + + ); +#endif +#endif + default: + printf("unable to determine type of EMAC with baseaddress 0x%08x\r\n", + mac_baseaddr); + return NULL; + } +} + +#if !NO_SYS +/* + * The input thread calls lwIP to process any received packets. + * This thread waits until a packet is received (sem_rx_data_available), + * and then calls xemacif_input which processes 1 packet at a time. + */ +void +xemacif_input_thread(struct netif *netif) +{ + struct xemac_s *emac = (struct xemac_s *)netif->state; + while (1) { + /* sleep until there are packets to process + * This semaphore is set by the packet receive interrupt + * routine. + */ + sys_arch_sem_wait( &emac->sem_rx_data_available, 250 / portTICK_PERIOD_MS ); + + /* move all received packets to lwIP */ + xemacif_input(netif); + } +} +#endif + +int +xemacif_input(struct netif *netif) +{ + struct xemac_s *emac = (struct xemac_s *)netif->state; + SYS_ARCH_DECL_PROTECT(lev); + + int n_packets = 0; + + switch (emac->type) { + case xemac_type_xps_emaclite: +#ifdef XLWIP_CONFIG_INCLUDE_EMACLITE + SYS_ARCH_PROTECT(lev); + n_packets = xemacliteif_input(netif); + SYS_ARCH_UNPROTECT(lev); + break; +#else + print("incorrect configuration: xps_ethernetlite drivers not present?"); + while(1); + return 0; +#endif + case xemac_type_xps_ll_temac: +#ifdef XLWIP_CONFIG_INCLUDE_TEMAC + SYS_ARCH_PROTECT(lev); + n_packets = xlltemacif_input(netif); + SYS_ARCH_UNPROTECT(lev); + break; +#else + print("incorrect configuration: xps_ll_temac drivers not present?"); + while(1); + return 0; +#endif + case xemac_type_axi_ethernet: +#ifdef XLWIP_CONFIG_INCLUDE_AXI_ETHERNET + SYS_ARCH_PROTECT(lev); + n_packets = xaxiemacif_input(netif); + SYS_ARCH_UNPROTECT(lev); + break; +#else + print("incorrect configuration: axi_ethernet drivers not present?"); + while(1); + return 0; +#endif +#ifdef __arm__ + case xemac_type_emacps: +#ifdef XLWIP_CONFIG_INCLUDE_GEM + SYS_ARCH_PROTECT(lev); + n_packets = xemacpsif_input(netif); + SYS_ARCH_UNPROTECT(lev); + break; +#else + xil_printf("incorrect configuration: ps7_ethernet drivers not present?\r\n"); + while(1); + return 0; +#endif +#endif + default: + print("incorrect configuration: unknown temac type"); + while(1); + return 0; + } + + return n_packets; +} diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/netif/xemacpsif.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/netif/xemacpsif.c new file mode 100644 index 000000000..2793f65ac --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/netif/xemacpsif.c @@ -0,0 +1,458 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +/* + * Copyright (c) 2010-2013 Xilinx, Inc. All rights reserved. + * + * Xilinx, Inc. + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR + * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION + * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE + * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO + * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE + * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#include +#include + +#include +#include "lwipopts.h" +#include "xlwipconfig.h" +#include "lwip/opt.h" +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/pbuf.h" +#include "lwip/sys.h" +#include "lwip/stats.h" +#include "lwip/igmp.h" + +#include "netif/etharp.h" +#include "netif/xemacpsif.h" +#include "netif/xadapter.h" +#include "netif/xpqueue.h" +#include "xparameters.h" +#include "xuartps.h" +#include "xscugic.h" +#include "xemacps.h" + + +/* Define those to better describe your network interface. */ +#define IFNAME0 't' +#define IFNAME1 'e' + +#if LWIP_IGMP +static err_t xemacpsif_mac_filter_update (struct netif *netif, + struct ip_addr *group, u8_t action); + +static u8_t xemacps_mcast_entry_mask = 0; +#endif + +XEmacPs_Config *mac_config; +struct netif *NetIf; +void FreeTxPBufs(void); +/* + * this function is always called with interrupts off + * this function also assumes that there are available BD's + */ +static err_t _unbuffered_low_level_output(xemacpsif_s *xemacpsif, + struct pbuf *p) +{ + XStatus status = 0; + +#if ETH_PAD_SIZE + pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ +#endif + status = emacps_sgsend(xemacpsif, p); + if (status != XST_SUCCESS) { +#if LINK_STATS + lwip_stats.link.drop++; +#endif + } + +#if ETH_PAD_SIZE + pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ +#endif + +#if LINK_STATS + lwip_stats.link.xmit++; +#endif /* LINK_STATS */ + + return ERR_OK; + +} + +/* + * low_level_output(): + * + * Should do the actual transmission of the packet. The packet is + * contained in the pbuf that is passed to the function. This pbuf + * might be chained. + * + */ + +static err_t low_level_output(struct netif *netif, struct pbuf *p) +{ + SYS_ARCH_DECL_PROTECT(lev); + err_t err; + + struct xemac_s *xemac = (struct xemac_s *)(netif->state); + xemacpsif_s *xemacpsif = (xemacpsif_s *)(xemac->state); + + SYS_ARCH_PROTECT(lev); + + + /* check if space is available to send */ + if (is_tx_space_available(xemacpsif)) { + _unbuffered_low_level_output(xemacpsif, p); + err = ERR_OK; + } else { +#if LINK_STATS + lwip_stats.link.drop++; +#endif + print("pack dropped, no space\r\n"); + err = ERR_MEM; + } + + + SYS_ARCH_UNPROTECT(lev); + return err; +} + +/* + * low_level_input(): + * + * Should allocate a pbuf and transfer the bytes of the incoming + * packet from the interface into the pbuf. + * + */ +static struct pbuf * low_level_input(struct netif *netif) +{ + struct xemac_s *xemac = (struct xemac_s *)(netif->state); + xemacpsif_s *xemacpsif = (xemacpsif_s *)(xemac->state); + struct pbuf *p; + + /* see if there is data to process */ + if (pq_qlength(xemacpsif->recv_q) == 0) + return NULL; + + /* return one packet from receive q */ + p = (struct pbuf *)pq_dequeue(xemacpsif->recv_q); + return p; +} + +/* + * xemacpsif_output(): + * + * This function is called by the TCP/IP stack when an IP packet + * should be sent. It calls the function called low_level_output() to + * do the actual transmission of the packet. + * + */ + +static err_t xemacpsif_output(struct netif *netif, struct pbuf *p, + struct ip_addr *ipaddr) +{ + /* resolve hardware address, then send (or queue) packet */ + return etharp_output(netif, p, ipaddr); +} + +/* + * xemacpsif_input(): + * + * This function should be called when a packet is ready to be read + * from the interface. It uses the function low_level_input() that + * should handle the actual reception of bytes from the network + * interface. + * + * Returns the number of packets read (max 1 packet on success, + * 0 if there are no packets) + * + */ + +int xemacpsif_input(struct netif *netif) +{ + struct eth_hdr *ethhdr; + struct pbuf *p; + SYS_ARCH_DECL_PROTECT(lev); + +#ifdef OS_IS_FREERTOS + while (1) +#endif + { + /* move received packet into a new pbuf */ + SYS_ARCH_PROTECT(lev); + p = low_level_input(netif); + SYS_ARCH_UNPROTECT(lev); + + /* no packet could be read, silently ignore this */ + if (p == NULL) { + return 0; + } + + /* points to packet payload, which starts with an Ethernet header */ + ethhdr = p->payload; + +#if LINK_STATS + lwip_stats.link.recv++; +#endif /* LINK_STATS */ + + switch (htons(ethhdr->type)) { + /* IP or ARP packet? */ + case ETHTYPE_IP: + case ETHTYPE_ARP: +#if PPPOE_SUPPORT + /* PPPoE packet? */ + case ETHTYPE_PPPOEDISC: + case ETHTYPE_PPPOE: +#endif /* PPPOE_SUPPORT */ + /* full packet send to tcpip_thread to process */ + if (netif->input(p, netif) != ERR_OK) { + LWIP_DEBUGF(NETIF_DEBUG, ("xemacpsif_input: IP input error\r\n")); + pbuf_free(p); + p = NULL; + } + break; + + default: + pbuf_free(p); + p = NULL; + break; + } + } + + return 1; +} + + +static err_t low_level_init(struct netif *netif) +{ + unsigned mac_address = (unsigned)(netif->state); + struct xemac_s *xemac; + xemacpsif_s *xemacpsif; + u32 dmacrreg; + + int Status = XST_SUCCESS; + + NetIf = netif; + + xemacpsif = mem_malloc(sizeof *xemacpsif); + if (xemacpsif == NULL) { + LWIP_DEBUGF(NETIF_DEBUG, ("xemacpsif_init: out of memory\r\n")); + return ERR_MEM; + } + + xemac = mem_malloc(sizeof *xemac); + if (xemac == NULL) { + LWIP_DEBUGF(NETIF_DEBUG, ("xemacpsif_init: out of memory\r\n")); + return ERR_MEM; + } + + xemac->state = (void *)xemacpsif; + xemac->topology_index = xtopology_find_index(mac_address); + xemac->type = xemac_type_emacps; + + xemacpsif->send_q = NULL; + xemacpsif->recv_q = pq_create_queue(); + if (!xemacpsif->recv_q) + return ERR_MEM; + + /* maximum transfer unit */ + netif->mtu = XEMACPS_MTU - XEMACPS_HDR_SIZE; + +#if LWIP_IGMP + netif->igmp_mac_filter = xemacpsif_mac_filter_update; +#endif + + netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | + NETIF_FLAG_LINK_UP; + +#if LWIP_IGMP + netif->flags |= NETIF_FLAG_IGMP; +#endif + +#if !NO_SYS + sys_sem_new(&xemac->sem_rx_data_available, 0); +#endif + /* obtain config of this emac */ + mac_config = (XEmacPs_Config *)xemacps_lookup_config((unsigned)netif->state); + + Status = XEmacPs_CfgInitialize(&xemacpsif->emacps, mac_config, + mac_config->BaseAddress); + if (Status != XST_SUCCESS) { + xil_printf("In %s:EmacPs Configuration Failed....\r\n", __func__); + } + + /* initialize the mac */ + init_emacps(xemacpsif, netif); + + dmacrreg = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, + XEMACPS_DMACR_OFFSET); + dmacrreg = dmacrreg | (0x00000010); + XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress, + XEMACPS_DMACR_OFFSET, dmacrreg); + + setup_isr(xemac); + init_dma(xemac); + start_emacps(xemacpsif); + + /* replace the state in netif (currently the emac baseaddress) + * with the mac instance pointer. + */ + netif->state = (void *)xemac; + + return ERR_OK; +} + +void HandleEmacPsError(struct xemac_s *xemac) +{ + xemacpsif_s *xemacpsif; + int Status = XST_SUCCESS; + u32 dmacrreg; + + SYS_ARCH_DECL_PROTECT(lev); + SYS_ARCH_PROTECT(lev); + + FreeTxRxPBufs(); + xemacpsif = (xemacpsif_s *)(xemac->state); + Status = XEmacPs_CfgInitialize(&xemacpsif->emacps, mac_config, + mac_config->BaseAddress); + if (Status != XST_SUCCESS) { + xil_printf("In %s:EmacPs Configuration Failed....\r\n", __func__); + } + /* initialize the mac */ + init_emacps_on_error(xemacpsif, NetIf); + dmacrreg = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, + XEMACPS_DMACR_OFFSET); + dmacrreg = dmacrreg | (0x01000000); + XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress, + XEMACPS_DMACR_OFFSET, dmacrreg); + setup_isr(xemac); + init_dma(xemac); + start_emacps(xemacpsif); + + SYS_ARCH_UNPROTECT(lev); +} + +void HandleTxErrors(struct xemac_s *xemac) +{ + xemacpsif_s *xemacpsif; + u32 netctrlreg; + + SYS_ARCH_DECL_PROTECT(lev); + SYS_ARCH_PROTECT(lev); + xemacpsif = (xemacpsif_s *)(xemac->state); + netctrlreg = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET); + netctrlreg = netctrlreg & (~XEMACPS_NWCTRL_TXEN_MASK); + XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET, netctrlreg); + FreeOnlyTxPBufs(); + + clean_dma_txdescs(xemac); + netctrlreg = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET); + netctrlreg = netctrlreg | (XEMACPS_NWCTRL_TXEN_MASK); + XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET, netctrlreg); + SYS_ARCH_UNPROTECT(lev); +} + + +#if LWIP_IGMP +static err_t xemacpsif_mac_filter_update (struct netif *netif, struct ip_addr *group, + u8_t action) +{ + return 0; +} +#endif + +/* + * xemacpsif_init(): + * + * Should be called at the beginning of the program to set up the + * network interface. It calls the function low_level_init() to do the + * actual setup of the hardware. + * + */ + +err_t xemacpsif_init(struct netif *netif) +{ +#if LWIP_SNMP + /* ifType ethernetCsmacd(6) @see RFC1213 */ + netif->link_type = 6; + /* your link speed here */ + netif->link_speed = ; + netif->ts = 0; + netif->ifinoctets = 0; + netif->ifinucastpkts = 0; + netif->ifinnucastpkts = 0; + netif->ifindiscards = 0; + netif->ifoutoctets = 0; + netif->ifoutucastpkts = 0; + netif->ifoutnucastpkts = 0; + netif->ifoutdiscards = 0; +#endif + + netif->name[0] = IFNAME0; + netif->name[1] = IFNAME1; + netif->output = xemacpsif_output; + netif->linkoutput = low_level_output; + + low_level_init(netif); + return ERR_OK; +} + +/* + * xemacpsif_resetrx_on_no_rxdata(): + * + * Should be called by the user at regular intervals, typically + * from a timer (100 msecond). This is to provide a SW workaround + * for the HW bug (SI #692601). Please refer to the function header + * for the function resetrx_on_no_rxdata in xemacpsif_dma.c to + * know more about the SI. + * + */ + +void xemacpsif_resetrx_on_no_rxdata(struct netif *netif) +{ + struct xemac_s *xemac = (struct xemac_s *)(netif->state); + xemacpsif_s *xemacpsif = (xemacpsif_s *)(xemac->state); + + resetrx_on_no_rxdata(xemacpsif); +} diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/netif/xemacpsif_dma.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/netif/xemacpsif_dma.c new file mode 100644 index 000000000..429b51a7e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/netif/xemacpsif_dma.c @@ -0,0 +1,622 @@ +/* + * Copyright (c) 2010-2013 Xilinx, Inc. All rights reserved. + * + * Xilinx, Inc. + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR + * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION + * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE + * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO + * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE + * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#include "lwipopts.h" +#include "lwip/stats.h" +#include "lwip/sys.h" +#include "lwip/inet_chksum.h" + +#include "netif/xadapter.h" +#include "netif/xemacpsif.h" +#include "xstatus.h" + +#include "xlwipconfig.h" +#include "xparameters.h" +#include "xparameters_ps.h" +#include "xil_exception.h" +#include "xil_mmu.h" +#ifdef CONFIG_XTRACE +#include "xtrace.h" +#endif +#ifdef OS_IS_FREERTOS +#include "FreeRTOS.h" +#include "semphr.h" +#include "timers.h" +#endif + +/*** IMPORTANT: Define PEEP in xemacpsif.h and sys_arch_raw.c + *** to run it on a PEEP board + ***/ + +#define INTC_BASE_ADDR XPAR_SCUGIC_CPU_BASEADDR +#define INTC_DIST_BASE_ADDR XPAR_SCUGIC_DIST_BASEADDR + +/* Byte alignment of BDs */ +#define BD_ALIGNMENT (XEMACPS_DMABD_MINIMUM_ALIGNMENT*2) + +static int tx_pbufs_storage[XLWIP_CONFIG_N_TX_DESC]; +static int rx_pbufs_storage[XLWIP_CONFIG_N_RX_DESC]; + +static int EmacIntrNum; +extern u8 _end; + +#ifdef OS_IS_FREERTOS +extern BaseType_t xInsideISR; +#endif + +#define XEMACPS_BD_TO_INDEX(ringptr, bdptr) \ + (((u32)bdptr - (u32)(ringptr)->BaseBdAddr) / (ringptr)->Separation) + + +int is_tx_space_available(xemacpsif_s *emac) +{ + XEmacPs_BdRing *txring; + int freecnt = 0; + + txring = &(XEmacPs_GetTxRing(&emac->emacps)); + + /* tx space is available as long as there are valid BD's */ + freecnt = XEmacPs_BdRingGetFreeCnt(txring); + return freecnt; +} + +void process_sent_bds(XEmacPs_BdRing *txring) +{ + XEmacPs_Bd *txbdset; + XEmacPs_Bd *CurBdPntr; + int n_bds; + XStatus Status; + int n_pbufs_freed = 0; + unsigned int BdIndex; + struct pbuf *p; + unsigned int *Temp; + + while (1) { + /* obtain processed BD's */ + n_bds = XEmacPs_BdRingFromHwTx(txring, + XLWIP_CONFIG_N_TX_DESC, &txbdset); + if (n_bds == 0) { + return; + } + /* free the processed BD's */ + n_pbufs_freed = n_bds; + CurBdPntr = txbdset; + while (n_pbufs_freed > 0) { + BdIndex = XEMACPS_BD_TO_INDEX(txring, CurBdPntr); + Temp = (unsigned int *)CurBdPntr; + *Temp = 0; + Temp++; + *Temp = 0x80000000; + if (BdIndex == (XLWIP_CONFIG_N_TX_DESC - 1)) { + *Temp = 0xC0000000; + } + + p = (struct pbuf *)tx_pbufs_storage[BdIndex]; + if(p != NULL) { + pbuf_free(p); + } + tx_pbufs_storage[BdIndex] = 0; + CurBdPntr = XEmacPs_BdRingNext(txring, CurBdPntr); + n_pbufs_freed--; + dsb(); + } + + Status = XEmacPs_BdRingFree(txring, n_bds, txbdset); + if (Status != XST_SUCCESS) { + LWIP_DEBUGF(NETIF_DEBUG, ("Failure while freeing in Tx Done ISR\r\n")); + } + } + return; +} + +void vPendableSendCompleteFunction( void *pvParameter, uint32_t ulParameter ) +{ + ( void ) ulParameter; + process_sent_bds(pvParameter); +} + +void emacps_send_handler(void *arg) +{ + struct xemac_s *xemac; + xemacpsif_s *xemacpsif; + XEmacPs_BdRing *TxRingPtr; + unsigned int regval; +#ifdef OS_IS_FREERTOS + xInsideISR++; +#endif + xemac = (struct xemac_s *)(arg); + xemacpsif = (xemacpsif_s *)(xemac->state); + TxRingPtr = &(XEmacPs_GetTxRing(&xemacpsif->emacps)); + regval = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_TXSR_OFFSET); + XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress,XEMACPS_TXSR_OFFSET, regval); + +#ifdef OS_IS_FREERTOS + xInsideISR--; +#endif + + /* If Transmit done interrupt is asserted, process completed BD's - Replaced + a call to process_sent_bds(TxRingPtr); with a pendable function to prevent + the memory allocation files being accessed from the ISR with not redress if + obtaining the mutex fails. */ + { + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + xTimerPendFunctionCallFromISR( vPendableSendCompleteFunction, TxRingPtr, 0, &xHigherPriorityTaskWoken ); + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + } +} + +XStatus emacps_sgsend(xemacpsif_s *xemacpsif, struct pbuf *p) +{ + struct pbuf *q; + int n_pbufs; + XEmacPs_Bd *txbdset, *txbd, *last_txbd = NULL; + XEmacPs_Bd *temp_txbd; + XStatus Status; + XEmacPs_BdRing *txring; + unsigned int BdIndex; + unsigned int lev; + + lev = mfcpsr(); + mtcpsr(lev | 0x000000C0); + +#ifdef PEEP + while((XEmacPs_ReadReg((xemacpsif->emacps).Config.BaseAddress, + XEMACPS_TXSR_OFFSET)) & 0x08); +#endif + txring = &(XEmacPs_GetTxRing(&xemacpsif->emacps)); + + /* first count the number of pbufs */ + for (q = p, n_pbufs = 0; q != NULL; q = q->next) + n_pbufs++; + + /* obtain as many BD's */ + Status = XEmacPs_BdRingAlloc(txring, n_pbufs, &txbdset); + if (Status != XST_SUCCESS) { + mtcpsr(lev); + LWIP_DEBUGF(NETIF_DEBUG, ("sgsend: Error allocating TxBD\r\n")); + return ERR_IF; + } + + for(q = p, txbd = txbdset; q != NULL; q = q->next) { + BdIndex = XEMACPS_BD_TO_INDEX(txring, txbd); + if (tx_pbufs_storage[BdIndex] != 0) { + mtcpsr(lev); + LWIP_DEBUGF(NETIF_DEBUG, ("PBUFS not available\r\n")); + return ERR_IF; + } + + /* Send the data from the pbuf to the interface, one pbuf at a + time. The size of the data in each pbuf is kept in the ->len + variable. */ + Xil_DCacheFlushRange((unsigned int)q->payload, (unsigned)q->len); + + XEmacPs_BdSetAddressTx(txbd, (u32)q->payload); + if (q->len > (XEMACPS_MAX_FRAME_SIZE - 18)) + XEmacPs_BdSetLength(txbd, (XEMACPS_MAX_FRAME_SIZE - 18) & 0x3FFF); + else + XEmacPs_BdSetLength(txbd, q->len & 0x3FFF); + + tx_pbufs_storage[BdIndex] = (int)q; + + pbuf_ref(q); + last_txbd = txbd; + XEmacPs_BdClearLast(txbd); + dsb(); + txbd = XEmacPs_BdRingNext(txring, txbd); + } + XEmacPs_BdSetLast(last_txbd); + dsb(); + /* For fragmented packets, remember the 1st BD allocated for the 1st + packet fragment. The used bit for this BD should be cleared at the end + after clearing out used bits for other fragments. For packets without + just remember the allocated BD. */ + temp_txbd = txbdset; + txbd = txbdset; + txbd = XEmacPs_BdRingNext(txring, txbd); + q = p->next; + for(; q != NULL; q = q->next) { + XEmacPs_BdClearTxUsed(txbd); + txbd = XEmacPs_BdRingNext(txring, txbd); + } + XEmacPs_BdClearTxUsed(temp_txbd); + dsb(); + + Status = XEmacPs_BdRingToHw(txring, n_pbufs, txbdset); + if (Status != XST_SUCCESS) { + mtcpsr(lev); + LWIP_DEBUGF(NETIF_DEBUG, ("sgsend: Error submitting TxBD\r\n")); + return ERR_IF; + } + dsb(); + /* Start transmit */ + XEmacPs_WriteReg((xemacpsif->emacps).Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET, + (XEmacPs_ReadReg((xemacpsif->emacps).Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK)); + dsb(); + mtcpsr(lev); + return Status; +} + +void setup_rx_bds(XEmacPs_BdRing *rxring) +{ + XEmacPs_Bd *rxbd; + XStatus Status; + struct pbuf *p; + unsigned int FreeBds; + unsigned int BdIndex; + unsigned int *Temp; + + FreeBds = XEmacPs_BdRingGetFreeCnt (rxring); + while (FreeBds > 0) { + FreeBds--; + Status = XEmacPs_BdRingAlloc(rxring, 1, &rxbd); + if (Status != XST_SUCCESS) { + LWIP_DEBUGF(NETIF_DEBUG, ("setup_rx_bds: Error allocating RxBD\r\n")); + return; + } + BdIndex = XEMACPS_BD_TO_INDEX(rxring, rxbd); + Temp = (unsigned int *)rxbd; + *Temp = 0; + if (BdIndex == (XLWIP_CONFIG_N_RX_DESC - 1)) { + *Temp = 0x00000002; + } + Temp++; + *Temp = 0; + + p = pbuf_alloc(PBUF_RAW, XEMACPS_MAX_FRAME_SIZE, PBUF_POOL); + if (!p) { +#if LINK_STATS + lwip_stats.link.memerr++; + lwip_stats.link.drop++; +#endif + LWIP_DEBUGF(NETIF_DEBUG, ("unable to alloc pbuf in recv_handler\r\n")); + XEmacPs_BdRingUnAlloc(rxring, 1, rxbd); + dsb(); + return; + } + XEmacPs_BdSetAddressRx(rxbd, (u32)p->payload); + dsb(); + + rx_pbufs_storage[BdIndex] = (int)p; + Status = XEmacPs_BdRingToHw(rxring, 1, rxbd); + if (Status != XST_SUCCESS) { + LWIP_DEBUGF(NETIF_DEBUG, ("Error committing RxBD to hardware: ")); + if (Status == XST_DMA_SG_LIST_ERROR) + LWIP_DEBUGF(NETIF_DEBUG, ("XST_DMA_SG_LIST_ERROR: this function was called out of sequence with XEmacPs_BdRingAlloc()\r\n")); + else + { + LWIP_DEBUGF(NETIF_DEBUG, ("set of BDs was rejected because the first BD did not have its start-of-packet bit set, or the last BD did not have its end-of-packet bit set, or any one of the BD set has 0 as length value\r\n")); + } + return; + } + } +} + +void emacps_recv_handler(void *arg) +{ + struct pbuf *p; + XEmacPs_Bd *rxbdset, *CurBdPtr; + struct xemac_s *xemac; + xemacpsif_s *xemacpsif; + XEmacPs_BdRing *rxring; + volatile int bd_processed; + int rx_bytes, k; + unsigned int BdIndex; + unsigned int regval; + + xemac = (struct xemac_s *)(arg); + xemacpsif = (xemacpsif_s *)(xemac->state); + rxring = &XEmacPs_GetRxRing(&xemacpsif->emacps); + +#ifdef OS_IS_FREERTOS + xInsideISR++; +#endif + /* + * If Reception done interrupt is asserted, call RX call back function + * to handle the processed BDs and then raise the according flag. + */ + regval = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_RXSR_OFFSET); + XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_RXSR_OFFSET, regval); + + resetrx_on_no_rxdata(xemacpsif); + + while(1) { + + bd_processed = XEmacPs_BdRingFromHwRx(rxring, XLWIP_CONFIG_N_RX_DESC, &rxbdset); + + if (bd_processed <= 0) { + break; + } + + for (k = 0, CurBdPtr=rxbdset; k < bd_processed; k++) { + + BdIndex = XEMACPS_BD_TO_INDEX(rxring, CurBdPtr); + p = (struct pbuf *)rx_pbufs_storage[BdIndex]; + + /* + * Adjust the buffer size to the actual number of bytes received. + */ + rx_bytes = XEmacPs_BdGetLength(CurBdPtr); + pbuf_realloc(p, rx_bytes); + Xil_DCacheInvalidateRange((unsigned int)p->payload, (unsigned)XEMACPS_MAX_FRAME_SIZE); + /* store it in the receive queue, + * where it'll be processed by a different handler + */ + if (pq_enqueue(xemacpsif->recv_q, (void*)p) < 0) { +#if LINK_STATS + lwip_stats.link.memerr++; + lwip_stats.link.drop++; +#endif + pbuf_free(p); + } else { +#if !NO_SYS + sys_sem_signal(&xemac->sem_rx_data_available); +#endif + } + CurBdPtr = XEmacPs_BdRingNext( rxring, CurBdPtr); + } + /* free up the BD's */ + XEmacPs_BdRingFree(rxring, bd_processed, rxbdset); + setup_rx_bds(rxring); + } + +#ifdef OS_IS_FREERTOS + xInsideISR--; +#endif + return; +} + +void clean_dma_txdescs(struct xemac_s *xemac) +{ + XEmacPs_Bd BdTemplate; + XEmacPs_BdRing *TxRingPtr; + xemacpsif_s *xemacpsif = (xemacpsif_s *)(xemac->state); + + TxRingPtr = &XEmacPs_GetTxRing(&xemacpsif->emacps); + + XEmacPs_BdClear(&BdTemplate); + XEmacPs_BdSetStatus(&BdTemplate, XEMACPS_TXBUF_USED_MASK); + + /* + * Create the TxBD ring + */ + XEmacPs_BdRingCreate(TxRingPtr, (u32) xemacpsif->tx_bdspace, + (u32) xemacpsif->tx_bdspace, BD_ALIGNMENT, + XLWIP_CONFIG_N_TX_DESC); + XEmacPs_BdRingClone(TxRingPtr, &BdTemplate, XEMACPS_SEND); +} + + +XStatus init_dma(struct xemac_s *xemac) +{ + XEmacPs_Bd BdTemplate; + XEmacPs_BdRing *RxRingPtr, *TxRingPtr; + XEmacPs_Bd *rxbd; + struct pbuf *p; + XStatus Status; + int i; + unsigned int BdIndex; + char *endAdd = (char *) &_end; + /* + * Align the BD starte address to 1 MB boundary. + */ + char *endAdd_aligned = (char *)(((int)endAdd + 0x100000) & (~0xFFFFF)); + xemacpsif_s *xemacpsif = (xemacpsif_s *)(xemac->state); + struct xtopology_t *xtopologyp = &xtopology[xemac->topology_index]; + + /* + * The BDs need to be allocated in uncached memory. Hence the 1 MB + * address range that starts at address 0xFF00000 is made uncached + * by setting appropriate attributes in the translation table. + */ + Xil_SetTlbAttributes((int)endAdd_aligned, 0xc02); // addr, attr + + RxRingPtr = &XEmacPs_GetRxRing(&xemacpsif->emacps); + TxRingPtr = &XEmacPs_GetTxRing(&xemacpsif->emacps); + LWIP_DEBUGF(NETIF_DEBUG, ("RxRingPtr: 0x%08x\r\n", RxRingPtr)); + LWIP_DEBUGF(NETIF_DEBUG, ("TxRingPtr: 0x%08x\r\n", TxRingPtr)); + + xemacpsif->rx_bdspace = (void *)endAdd_aligned; + /* + * We allocate 65536 bytes for Rx BDs which can accomodate a + * maximum of 8192 BDs which is much more than any application + * will ever need. + */ + xemacpsif->tx_bdspace = (void *)(endAdd_aligned + 0x10000); + + LWIP_DEBUGF(NETIF_DEBUG, ("rx_bdspace: 0x%08x\r\n", xemacpsif->rx_bdspace)); + LWIP_DEBUGF(NETIF_DEBUG, ("tx_bdspace: 0x%08x\r\n", xemacpsif->tx_bdspace)); + + if (!xemacpsif->rx_bdspace || !xemacpsif->tx_bdspace) { + xil_printf("%s@%d: Error: Unable to allocate memory for TX/RX buffer descriptors", + __FILE__, __LINE__); + return XST_FAILURE; + } + + /* + * Setup RxBD space. + * + * Setup a BD template for the Rx channel. This template will be copied to + * every RxBD. We will not have to explicitly set these again. + */ + XEmacPs_BdClear(&BdTemplate); + + /* + * Create the RxBD ring + */ + + Status = XEmacPs_BdRingCreate(RxRingPtr, (u32) xemacpsif->rx_bdspace, + (u32) xemacpsif->rx_bdspace, BD_ALIGNMENT, + XLWIP_CONFIG_N_RX_DESC); + + if (Status != XST_SUCCESS) { + LWIP_DEBUGF(NETIF_DEBUG, ("Error setting up RxBD space\r\n")); + return XST_FAILURE; + } + + Status = XEmacPs_BdRingClone(RxRingPtr, &BdTemplate, XEMACPS_RECV); + if (Status != XST_SUCCESS) { + LWIP_DEBUGF(NETIF_DEBUG, ("Error initializing RxBD space\r\n")); + return XST_FAILURE; + } + + XEmacPs_BdClear(&BdTemplate); + XEmacPs_BdSetStatus(&BdTemplate, XEMACPS_TXBUF_USED_MASK); + /* + * Create the TxBD ring + */ + Status = XEmacPs_BdRingCreate(TxRingPtr, (u32) xemacpsif->tx_bdspace, + (u32) xemacpsif->tx_bdspace, BD_ALIGNMENT, + XLWIP_CONFIG_N_TX_DESC); + + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* We reuse the bd template, as the same one will work for both rx and tx. */ + Status = XEmacPs_BdRingClone(TxRingPtr, &BdTemplate, XEMACPS_SEND); + if (Status != XST_SUCCESS) { + return ERR_IF; + } + + /* + * Allocate RX descriptors, 1 RxBD at a time. + */ + for (i = 0; i < XLWIP_CONFIG_N_RX_DESC; i++) { + Status = XEmacPs_BdRingAlloc(RxRingPtr, 1, &rxbd); + if (Status != XST_SUCCESS) { + LWIP_DEBUGF(NETIF_DEBUG, ("init_dma: Error allocating RxBD\r\n")); + return ERR_IF; + } + + p = pbuf_alloc(PBUF_RAW, XEMACPS_MAX_FRAME_SIZE, PBUF_POOL); + if (!p) { +#if LINK_STATS + lwip_stats.link.memerr++; + lwip_stats.link.drop++; +#endif + LWIP_DEBUGF(NETIF_DEBUG, ("unable to alloc pbuf in recv_handler\r\n")); + return -1; + } + + XEmacPs_BdSetAddressRx(rxbd, (u32)p->payload); + + BdIndex = XEMACPS_BD_TO_INDEX(RxRingPtr, rxbd); + rx_pbufs_storage[BdIndex] = (int)p; + + /* Enqueue to HW */ + Status = XEmacPs_BdRingToHw(RxRingPtr, 1, rxbd); + if (Status != XST_SUCCESS) { + LWIP_DEBUGF(NETIF_DEBUG, ("Error: committing RxBD to HW\r\n")); + return XST_FAILURE; + } + } + + /* + * Connect the device driver handler that will be called when an + * interrupt for the device occurs, the handler defined above performs + * the specific interrupt processing for the device. + */ + XScuGic_RegisterHandler(INTC_BASE_ADDR, xtopologyp->scugic_emac_intr, + (Xil_ExceptionHandler)XEmacPs_IntrHandler, + (void *)&xemacpsif->emacps); + /* + * Enable the interrupt for emacps. + */ + XScuGic_EnableIntr(INTC_DIST_BASE_ADDR, (u32) xtopologyp->scugic_emac_intr); + EmacIntrNum = (u32) xtopologyp->scugic_emac_intr; + return 0; +} + +/* + * resetrx_on_no_rxdata(): + * + * It is called at regular intervals through the API xemacpsif_resetrx_on_no_rxdata + * called by the user. + * The EmacPs has a HW bug (SI# 692601) on the Rx path for heavy Rx traffic. + * Under heavy Rx traffic because of the HW bug there are times when the Rx path + * becomes unresponsive. The workaround for it is to check for the Rx path for + * traffic (by reading the stats registers regularly). If the stats register + * does not increment for sometime (proving no Rx traffic), the function resets + * the Rx data path. + * + */ + +void resetrx_on_no_rxdata(xemacpsif_s *xemacpsif) +{ + unsigned long regctrl; + unsigned long tempcntr; + + tempcntr = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_RXCNT_OFFSET); + if ((!tempcntr) && (!(xemacpsif->last_rx_frms_cntr))) { + regctrl = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET); + regctrl &= (~XEMACPS_NWCTRL_RXEN_MASK); + XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET, regctrl); + regctrl = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_NWCTRL_OFFSET); + regctrl |= (XEMACPS_NWCTRL_RXEN_MASK); + XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_NWCTRL_OFFSET, regctrl); + } + xemacpsif->last_rx_frms_cntr = tempcntr; +} + +void FreeTxRxPBufs(void) +{ + int Index; + struct pbuf *p; + + for (Index = 0; Index < XLWIP_CONFIG_N_TX_DESC; Index++) { + if (tx_pbufs_storage[Index] != 0) { + p = (struct pbuf *)tx_pbufs_storage[Index]; + pbuf_free(p); + tx_pbufs_storage[Index] = 0; + } + } + + for (Index = 0; Index < XLWIP_CONFIG_N_RX_DESC; Index++) { + p = (struct pbuf *)rx_pbufs_storage[Index]; + pbuf_free(p); + + } +} + +void FreeOnlyTxPBufs(void) +{ + int Index; + struct pbuf *p; + + for (Index = 0; Index < XLWIP_CONFIG_N_TX_DESC; Index++) { + if (tx_pbufs_storage[Index] != 0) { + p = (struct pbuf *)tx_pbufs_storage[Index]; + pbuf_free(p); + tx_pbufs_storage[Index] = 0; + } + } +} + +void EmacDisableIntr(void) +{ + XScuGic_DisableIntr(INTC_DIST_BASE_ADDR, EmacIntrNum); +} + +void EmacEnableIntr(void) +{ + XScuGic_EnableIntr(INTC_DIST_BASE_ADDR, EmacIntrNum); +} diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/netif/xemacpsif_hw.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/netif/xemacpsif_hw.c new file mode 100644 index 000000000..86209f259 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/netif/xemacpsif_hw.c @@ -0,0 +1,208 @@ +/* + * Copyright (c) 2010-2013 Xilinx, Inc. All rights reserved. + * + * Xilinx, Inc. + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR + * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION + * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE + * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO + * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE + * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#include "netif/xemacpsif.h" +#include "lwipopts.h" + +/*** IMPORTANT: Define PEEP in xemacpsif.h and sys_arch_raw.c + *** to run it on a PEEP board + ***/ + +unsigned int link_speed = 100; + +XEmacPs_Config *xemacps_lookup_config(unsigned mac_base) +{ + extern XEmacPs_Config XEmacPs_ConfigTable[]; + XEmacPs_Config *CfgPtr = NULL; + int i; + + for (i = 0; i < XPAR_XEMACPS_NUM_INSTANCES; i++) { + if (XEmacPs_ConfigTable[i].BaseAddress == mac_base) { + CfgPtr = &XEmacPs_ConfigTable[i]; + break; + } + } + + return (CfgPtr); +} + +void init_emacps(xemacpsif_s *xemacps, struct netif *netif) +{ + unsigned mac_address = (unsigned)(netif->state); + XEmacPs *xemacpsp; + XEmacPs_Config *mac_config; + int Status = XST_SUCCESS; + + /* obtain config of this emac */ + mac_config = (XEmacPs_Config *)xemacps_lookup_config(mac_address); + + /* Does not appear to be used. */ + ( void ) mac_config; + + xemacpsp = &xemacps->emacps; + + /* set mac address */ + Status = XEmacPs_SetMacAddress(xemacpsp, (void*)(netif->hwaddr), 1); + if (Status != XST_SUCCESS) { + xil_printf("In %s:Emac Mac Address set failed...\r\n",__func__); + } + XEmacPs_SetMdioDivisor(xemacpsp, MDC_DIV_224); + link_speed = Phy_Setup(xemacpsp); + XEmacPs_SetOperatingSpeed(xemacpsp, link_speed); + /* Setting the operating speed of the MAC needs a delay. */ + { + volatile int wait; + for (wait=0; wait < 20000; wait++); + } +} + +void init_emacps_on_error (xemacpsif_s *xemacps, struct netif *netif) +{ + unsigned mac_address = (unsigned)(netif->state); + XEmacPs *xemacpsp; + XEmacPs_Config *mac_config; + int Status = XST_SUCCESS; + + /* obtain config of this emac */ + mac_config = (XEmacPs_Config *)xemacps_lookup_config(mac_address); + + /* Does not appear to be used? */ + ( void ) mac_config; + + xemacpsp = &xemacps->emacps; + + /* set mac address */ + Status = XEmacPs_SetMacAddress(xemacpsp, (void*)(netif->hwaddr), 1); + if (Status != XST_SUCCESS) { + xil_printf("In %s:Emac Mac Address set failed...\r\n",__func__); + } + + XEmacPs_SetOperatingSpeed(xemacpsp, link_speed); + + /* Setting the operating speed of the MAC needs a delay. */ + { + volatile int wait; + for (wait=0; wait < 20000; wait++); + } +} + +void setup_isr (struct xemac_s *xemac) +{ + xemacpsif_s *xemacpsif; + + xemacpsif = (xemacpsif_s *)(xemac->state); + /* + * Setup callbacks + */ + XEmacPs_SetHandler(&xemacpsif->emacps, XEMACPS_HANDLER_DMASEND, + (void *) emacps_send_handler, + (void *) xemac); + + XEmacPs_SetHandler(&xemacpsif->emacps, XEMACPS_HANDLER_DMARECV, + (void *) emacps_recv_handler, + (void *) xemac); + + XEmacPs_SetHandler(&xemacpsif->emacps, XEMACPS_HANDLER_ERROR, + (void *) emacps_error_handler, + (void *) xemac); +} + +void start_emacps (xemacpsif_s *xemacps) +{ + /* start the temac */ + XEmacPs_Start(&xemacps->emacps); +} + +void restart_emacps_transmitter (xemacpsif_s *xemacps) { + u32 Reg; + Reg = XEmacPs_ReadReg(xemacps->emacps.Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET); + Reg = Reg & (~XEMACPS_NWCTRL_TXEN_MASK); + XEmacPs_WriteReg(xemacps->emacps.Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET, Reg); + + Reg = XEmacPs_ReadReg(xemacps->emacps.Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET); + Reg = Reg | (XEMACPS_NWCTRL_TXEN_MASK); + XEmacPs_WriteReg(xemacps->emacps.Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET, Reg); +} + +void emacps_error_handler(void *arg,u8 Direction, u32 ErrorWord) +{ + struct xemac_s *xemac; + xemacpsif_s *xemacpsif; + struct xtopology_t *xtopologyp; + XEmacPs *xemacps; + XEmacPs_BdRing *rxring; + XEmacPs_BdRing *txring; + + xemac = (struct xemac_s *)(arg); + xemacpsif = (xemacpsif_s *)(xemac->state); + rxring = &XEmacPs_GetRxRing(&xemacpsif->emacps); + txring = &XEmacPs_GetRxRing(&xemacpsif->emacps); + xtopologyp = &xtopology[xemac->topology_index]; + xemacps = &xemacpsif->emacps; + + /* Do not appear to be used. */ + ( void ) xemacps; + ( void ) xtopologyp; + + if (ErrorWord != 0) { + switch (Direction) { + case XEMACPS_RECV: + if (ErrorWord & XEMACPS_RXSR_HRESPNOK_MASK) { + LWIP_DEBUGF(NETIF_DEBUG, ("Receive DMA error\r\n")); + HandleEmacPsError(xemac); + } + if (ErrorWord & XEMACPS_RXSR_RXOVR_MASK) { + LWIP_DEBUGF(NETIF_DEBUG, ("Receive over run\r\n")); + emacps_recv_handler(arg); + setup_rx_bds(rxring); + } + if (ErrorWord & XEMACPS_RXSR_BUFFNA_MASK) { + LWIP_DEBUGF(NETIF_DEBUG, ("Receive buffer not available\r\n")); + emacps_recv_handler(arg); + setup_rx_bds(rxring); + } + break; + case XEMACPS_SEND: + if (ErrorWord & XEMACPS_TXSR_HRESPNOK_MASK) { + LWIP_DEBUGF(NETIF_DEBUG, ("Transmit DMA error\r\n")); + HandleEmacPsError(xemac); + } + if (ErrorWord & XEMACPS_TXSR_URUN_MASK) { + LWIP_DEBUGF(NETIF_DEBUG, ("Transmit under run\r\n")); + HandleTxErrors(xemac); + } + if (ErrorWord & XEMACPS_TXSR_BUFEXH_MASK) { + LWIP_DEBUGF(NETIF_DEBUG, ("Transmit buffer exhausted\r\n")); + HandleTxErrors(xemac); + } + if (ErrorWord & XEMACPS_TXSR_RXOVR_MASK) { + LWIP_DEBUGF(NETIF_DEBUG, ("Transmit retry excessed limits\r\n")); + HandleTxErrors(xemac); + } + if (ErrorWord & XEMACPS_TXSR_FRAMERX_MASK) { + LWIP_DEBUGF(NETIF_DEBUG, ("Transmit collision\r\n")); + process_sent_bds(txring); + } + break; + } + } +} diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/netif/xemacpsif_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/netif/xemacpsif_hw.h new file mode 100644 index 000000000..923f66185 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/netif/xemacpsif_hw.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2010-2013 Xilinx, Inc. All rights reserved. + * + * Xilinx, Inc. + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR + * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION + * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE + * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO + * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE + * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#ifndef __XEMACPSIF_HW_H_ +#define __XEMACPSIF_HW_H_ + +#include "netif/xemacpsif.h" +#include "lwip/netif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +XEmacPs_Config * lookup_config(unsigned mac_base); + +void init_emacps(xemacpsif_s *xemacpsif, struct netif *netif); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/netif/xemacpsif_physpeed.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/netif/xemacpsif_physpeed.c new file mode 100644 index 000000000..367a9b30f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/netif/xemacpsif_physpeed.c @@ -0,0 +1,558 @@ +/* + * Copyright (c) 2007-2008, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names + * of its contributors may be used to endorse or promote products + * derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Some portions copyright (c) 2010-2013 Xilinx, Inc. All rights reserved. + * + * Xilinx, Inc. + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR + * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION + * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE + * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO + * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE + * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#include "netif/xemacpsif.h" +#include "lwipopts.h" +#include "xparameters_ps.h" +#include "xparameters.h" + +/*** IMPORTANT: Define PEEP in xemacpsif.h and sys_arch_raw.c + *** to run it on a PEEP board + ***/ + +/* Advertisement control register. */ +#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ +#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ +#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ +#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ + +#define ADVERTISE_100_AND_10 (ADVERTISE_10FULL | ADVERTISE_100FULL | \ + ADVERTISE_10HALF | ADVERTISE_100HALF) +#define ADVERTISE_100 (ADVERTISE_100FULL | ADVERTISE_100HALF) +#define ADVERTISE_10 (ADVERTISE_10FULL | ADVERTISE_10HALF) + +#define ADVERTISE_1000 0x0300 + + +#define IEEE_CONTROL_REG_OFFSET 0 +#define IEEE_STATUS_REG_OFFSET 1 +#define IEEE_AUTONEGO_ADVERTISE_REG 4 +#define IEEE_PARTNER_ABILITIES_1_REG_OFFSET 5 +#define IEEE_1000_ADVERTISE_REG_OFFSET 9 +#define IEEE_PARTNER_ABILITIES_3_REG_OFFSET 10 +#define IEEE_COPPER_SPECIFIC_CONTROL_REG 16 +#define IEEE_SPECIFIC_STATUS_REG 17 +#define IEEE_COPPER_SPECIFIC_STATUS_REG_2 19 +#define IEEE_CONTROL_REG_MAC 21 +#define IEEE_PAGE_ADDRESS_REGISTER 22 + + +#define IEEE_CTRL_1GBPS_LINKSPEED_MASK 0x2040 +#define IEEE_CTRL_LINKSPEED_MASK 0x0040 +#define IEEE_CTRL_LINKSPEED_1000M 0x0040 +#define IEEE_CTRL_LINKSPEED_100M 0x2000 +#define IEEE_CTRL_LINKSPEED_10M 0x0000 +#define IEEE_CTRL_RESET_MASK 0x8000 +#define IEEE_CTRL_AUTONEGOTIATE_ENABLE 0x1000 +#if XPAR_GIGE_PCS_PMA_CORE_PRESENT == 1 +#define IEEE_CTRL_RESET 0x9140 +#define IEEE_CTRL_ISOLATE_DISABLE 0xFBFF +#endif +#define IEEE_STAT_AUTONEGOTIATE_CAPABLE 0x0008 +#define IEEE_STAT_AUTONEGOTIATE_COMPLETE 0x0020 +#define IEEE_STAT_AUTONEGOTIATE_RESTART 0x0200 +#define IEEE_STAT_1GBPS_EXTENSIONS 0x0100 +#define IEEE_AN1_ABILITY_MASK 0x1FE0 +#define IEEE_AN3_ABILITY_MASK_1GBPS 0x0C00 +#define IEEE_AN1_ABILITY_MASK_100MBPS 0x0380 +#define IEEE_AN1_ABILITY_MASK_10MBPS 0x0060 +#define IEEE_RGMII_TXRX_CLOCK_DELAYED_MASK 0x0030 + +#define IEEE_ASYMMETRIC_PAUSE_MASK 0x0800 +#define IEEE_PAUSE_MASK 0x0400 +#define IEEE_AUTONEG_ERROR_MASK 0x8000 + +#define PHY_DETECT_REG 1 +#define PHY_DETECT_MASK 0x1808 + +#define XEMACPS_GMII2RGMII_SPEED1000_FD 0x140 +#define XEMACPS_GMII2RGMII_SPEED100_FD 0x2100 +#define XEMACPS_GMII2RGMII_SPEED10_FD 0x100 +#define XEMACPS_GMII2RGMII_REG_NUM 0x10 + +/* Frequency setting */ +#define SLCR_LOCK_ADDR (XPS_SYS_CTRL_BASEADDR + 0x4) +#define SLCR_UNLOCK_ADDR (XPS_SYS_CTRL_BASEADDR + 0x8) +#define SLCR_GEM0_CLK_CTRL_ADDR (XPS_SYS_CTRL_BASEADDR + 0x140) +#define SLCR_GEM1_CLK_CTRL_ADDR (XPS_SYS_CTRL_BASEADDR + 0x144) +#ifdef PEEP +#define SLCR_GEM_10M_CLK_CTRL_VALUE 0x00103031 +#define SLCR_GEM_100M_CLK_CTRL_VALUE 0x00103001 +#define SLCR_GEM_1G_CLK_CTRL_VALUE 0x00103011 +#endif +#define SLCR_LOCK_KEY_VALUE 0x767B +#define SLCR_UNLOCK_KEY_VALUE 0xDF0D +#define SLCR_ADDR_GEM_RST_CTRL (XPS_SYS_CTRL_BASEADDR + 0x214) +#define EMACPS_SLCR_DIV_MASK 0xFC0FC0FF + +#define EMAC0_BASE_ADDRESS 0xE000B000 +#define EMAC1_BASE_ADDRESS 0xE000C000 + +static int detect_phy(XEmacPs *xemacpsp) +{ + u16 phy_reg; + u32 phy_addr; + + for (phy_addr = 31; phy_addr > 0; phy_addr--) { + XEmacPs_PhyRead(xemacpsp, phy_addr, PHY_DETECT_REG, + &phy_reg); + + if ((phy_reg != 0xFFFF) && + ((phy_reg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { + /* Found a valid PHY address */ + LWIP_DEBUGF(NETIF_DEBUG, ("XEmacPs detect_phy: PHY detected at address %d.\r\n", + phy_addr)); + LWIP_DEBUGF(NETIF_DEBUG, ("XEmacPs detect_phy: PHY detected.\r\n")); + return phy_addr; + } + } + + LWIP_DEBUGF(NETIF_DEBUG, ("XEmacPs detect_phy: No PHY detected. Assuming a PHY at address 0\r\n")); + + /* default to zero */ + return 0; +} + +#ifdef PEEP +unsigned get_IEEE_phy_speed(XEmacPs *xemacpsp) +{ + + u16 control; + u16 status; + u16 partner_capabilities; + u16 partner_capabilities_1000; + u16 phylinkspeed; + u32 phy_addr = detect_phy(xemacpsp); + + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, + ADVERTISE_1000); + /* Advertise PHY speed of 100 and 10 Mbps */ + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, + ADVERTISE_100_AND_10); + + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, + &control); + control |= (IEEE_CTRL_AUTONEGOTIATE_ENABLE | + IEEE_STAT_AUTONEGOTIATE_RESTART); + + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, control); + + /* Read PHY control and status registers is successful. */ + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control); + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status); + + if ((control & IEEE_CTRL_AUTONEGOTIATE_ENABLE) && (status & + IEEE_STAT_AUTONEGOTIATE_CAPABLE)) { + + while ( !(status & IEEE_STAT_AUTONEGOTIATE_COMPLETE) ) { + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, + &status); + } + + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_PARTNER_ABILITIES_1_REG_OFFSET, + &partner_capabilities); + + if (status & IEEE_STAT_1GBPS_EXTENSIONS) { + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_PARTNER_ABILITIES_3_REG_OFFSET, + &partner_capabilities_1000); + if (partner_capabilities_1000 & IEEE_AN3_ABILITY_MASK_1GBPS) + return 1000; + } + + if (partner_capabilities & IEEE_AN1_ABILITY_MASK_100MBPS) + return 100; + if (partner_capabilities & IEEE_AN1_ABILITY_MASK_10MBPS) + return 10; + + xil_printf("%s: unknown PHY link speed, setting TEMAC speed to be 10 Mbps\r\n", + __FUNCTION__); + return 10; + + } else { + + /* Update TEMAC speed accordingly */ + if (status & IEEE_STAT_1GBPS_EXTENSIONS) { + /* Get commanded link speed */ + phylinkspeed = control & IEEE_CTRL_1GBPS_LINKSPEED_MASK; + + switch (phylinkspeed) { + case (IEEE_CTRL_LINKSPEED_1000M): + return 1000; + case (IEEE_CTRL_LINKSPEED_100M): + return 100; + case (IEEE_CTRL_LINKSPEED_10M): + return 10; + default: + xil_printf("%s: unknown PHY link speed (%d), setting TEMAC speed to be 10 Mbps\r\n", + __FUNCTION__, phylinkspeed); + return 10; + } + + } else { + + return (control & IEEE_CTRL_LINKSPEED_MASK) ? 100 : 10; + + } + } +} + +#else /* Zynq */ +unsigned get_IEEE_phy_speed(XEmacPs *xemacpsp) +{ + u16 temp; + u16 control; + u16 status; + u16 partner_capabilities; +#if XPAR_GIGE_PCS_PMA_CORE_PRESENT == 1 + u32 phy_addr = XPAR_PCSPMA_SGMII_PHYADDR; +#else + u32 phy_addr = detect_phy(xemacpsp); +#endif + xil_printf("Start PHY autonegotiation \r\n"); + +#if XPAR_GIGE_PCS_PMA_CORE_PRESENT == 1 +#else + XEmacPs_PhyWrite(xemacpsp,phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 2); + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_MAC, &control); + control |= IEEE_RGMII_TXRX_CLOCK_DELAYED_MASK; + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_MAC, control); + + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0); + + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &control); + control |= IEEE_ASYMMETRIC_PAUSE_MASK; + control |= IEEE_PAUSE_MASK; + control |= ADVERTISE_100; + control |= ADVERTISE_10; + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, control); + + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, + &control); + control |= ADVERTISE_1000; + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, + control); + + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0); + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_COPPER_SPECIFIC_CONTROL_REG, + &control); + control |= (7 << 12); /* max number of gigabit attempts */ + control |= (1 << 11); /* enable downshift */ + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_COPPER_SPECIFIC_CONTROL_REG, + control); +#endif + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control); + control |= IEEE_CTRL_AUTONEGOTIATE_ENABLE; + control |= IEEE_STAT_AUTONEGOTIATE_RESTART; +#if XPAR_GIGE_PCS_PMA_CORE_PRESENT == 1 + control &= IEEE_CTRL_ISOLATE_DISABLE; +#endif + + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, control); + + +#if XPAR_GIGE_PCS_PMA_CORE_PRESENT == 1 +#else + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control); + control |= IEEE_CTRL_RESET_MASK; + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, control); + + while (1) { + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control); + if (control & IEEE_CTRL_RESET_MASK) + continue; + else + break; + } +#endif + xil_printf("Waiting for PHY to complete autonegotiation.\r\n"); + + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status); + while ( !(status & IEEE_STAT_AUTONEGOTIATE_COMPLETE) ) { + sleep(1); +#if XPAR_GIGE_PCS_PMA_CORE_PRESENT == 1 +#else + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_COPPER_SPECIFIC_STATUS_REG_2, + &temp); + if (temp & IEEE_AUTONEG_ERROR_MASK) { + xil_printf("Auto negotiation error \r\n"); + } +#endif + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, + &status); + } + + xil_printf("autonegotiation complete \r\n"); + +#if XPAR_GIGE_PCS_PMA_CORE_PRESENT == 1 +#else + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_SPECIFIC_STATUS_REG, &partner_capabilities); +#endif + +#if XPAR_GIGE_PCS_PMA_CORE_PRESENT == 1 + xil_printf("Waiting for Link to be up; Polling for SGMII core Reg \r\n"); + XEmacPs_PhyRead(xemacpsp, phy_addr, 5, &temp); + while(!(temp & 0x8000)) { + XEmacPs_PhyRead(xemacpsp, phy_addr, 5, &temp); + } + if((temp & 0x0C00) == 0x0800) { + XEmacPs_PhyRead(xemacpsp, phy_addr, 0, &temp); + return 1000; + } + else if((temp & 0x0C00) == 0x0400) { + XEmacPs_PhyRead(xemacpsp, phy_addr, 0, &temp); + return 100; + } + else if((temp & 0x0C00) == 0x0000) { + XEmacPs_PhyRead(xemacpsp, phy_addr, 0, &temp); + return 10; + } else { + xil_printf("get_IEEE_phy_speed(): Invalid speed bit value, Deafulting to Speed = 10 Mbps\r\n"); + XEmacPs_PhyRead(xemacpsp, phy_addr, 0, &temp); + XEmacPs_PhyWrite(xemacpsp, phy_addr, 0, 0x0100); + return 10; + } +#else + if ( ((partner_capabilities >> 14) & 3) == 2)/* 1000Mbps */ + return 1000; + else if ( ((partner_capabilities >> 14) & 3) == 1)/* 100Mbps */ + return 100; + else /* 10Mbps */ + return 10; +#endif +} +#endif + +unsigned configure_IEEE_phy_speed(XEmacPs *xemacpsp, unsigned speed) +{ + u16 control; + u32 phy_addr = detect_phy(xemacpsp); + + XEmacPs_PhyWrite(xemacpsp,phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 2); + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_MAC, &control); + control |= IEEE_RGMII_TXRX_CLOCK_DELAYED_MASK; + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_MAC, control); + + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_PAGE_ADDRESS_REGISTER, 0); + + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, &control); + control |= IEEE_ASYMMETRIC_PAUSE_MASK; + control |= IEEE_PAUSE_MASK; + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, control); + + XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, &control); + control &= ~IEEE_CTRL_LINKSPEED_1000M; + control &= ~IEEE_CTRL_LINKSPEED_100M; + control &= ~IEEE_CTRL_LINKSPEED_10M; + + if (speed == 1000) { + control |= IEEE_CTRL_LINKSPEED_1000M; + } + + else if (speed == 100) { + control |= IEEE_CTRL_LINKSPEED_100M; + /* Dont advertise PHY speed of 1000 Mbps */ + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, 0); + /* Dont advertise PHY speed of 10 Mbps */ + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, + ADVERTISE_100); + } + + else if (speed == 10) { + control |= IEEE_CTRL_LINKSPEED_10M; + /* Dont advertise PHY speed of 1000 Mbps */ + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_1000_ADVERTISE_REG_OFFSET, + 0); + /* Dont advertise PHY speed of 100 Mbps */ + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_AUTONEGO_ADVERTISE_REG, + ADVERTISE_10); + } + + XEmacPs_PhyWrite(xemacpsp, phy_addr, IEEE_CONTROL_REG_OFFSET, + control | IEEE_CTRL_RESET_MASK); + { + volatile int wait; + for (wait=0; wait < 100000; wait++); + } + return 0; +} + +static void SetUpSLCRDivisors(int mac_baseaddr, int speed) +{ + volatile u32 slcrBaseAddress; +#ifndef PEEP + u32 SlcrDiv0; + u32 SlcrDiv1; + u32 SlcrTxClkCntrl; +#endif + + *(volatile unsigned int *)(SLCR_UNLOCK_ADDR) = SLCR_UNLOCK_KEY_VALUE; + + if ((unsigned long)mac_baseaddr == EMAC0_BASE_ADDRESS) { + slcrBaseAddress = SLCR_GEM0_CLK_CTRL_ADDR; + } else { + slcrBaseAddress = SLCR_GEM1_CLK_CTRL_ADDR; + } +#ifdef PEEP + if (speed == 1000) { + *(volatile unsigned int *)(slcrBaseAddress) = + SLCR_GEM_1G_CLK_CTRL_VALUE; + } else if (speed == 100) { + *(volatile unsigned int *)(slcrBaseAddress) = + SLCR_GEM_100M_CLK_CTRL_VALUE; + } else { + *(volatile unsigned int *)(slcrBaseAddress) = + SLCR_GEM_10M_CLK_CTRL_VALUE; + } +#else + if (speed == 1000) { + if ((unsigned long)mac_baseaddr == EMAC0_BASE_ADDRESS) { +#ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 + SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0; + SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1; +#endif + } else { +#ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0 + SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0; + SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1; +#endif + } + } else if (speed == 100) { + if ((unsigned long)mac_baseaddr == EMAC0_BASE_ADDRESS) { +#ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 + SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0; + SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1; +#endif + } else { +#ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV0 + SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV0; + SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV1; +#endif + } + } else { + if ((unsigned long)mac_baseaddr == EMAC0_BASE_ADDRESS) { +#ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 + SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0; + SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1; +#endif + } else { +#ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV0 + SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV0; + SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV1; +#endif + } + } + SlcrTxClkCntrl = *(volatile unsigned int *)(slcrBaseAddress); + SlcrTxClkCntrl &= EMACPS_SLCR_DIV_MASK; + SlcrTxClkCntrl |= (SlcrDiv1 << 20); + SlcrTxClkCntrl |= (SlcrDiv0 << 8); + *(volatile unsigned int *)(slcrBaseAddress) = SlcrTxClkCntrl; +#endif + *(volatile unsigned int *)(SLCR_LOCK_ADDR) = SLCR_LOCK_KEY_VALUE; + return; +} + + +unsigned Phy_Setup (XEmacPs *xemacpsp) +{ + unsigned link_speed; + unsigned long conv_present = 0; + unsigned long convspeeddupsetting = 0; + unsigned long convphyaddr = 0; + +#ifdef XPAR_GMII2RGMIICON_0N_ETH0_ADDR + convphyaddr = XPAR_GMII2RGMIICON_0N_ETH0_ADDR; + conv_present = 1; +#else +#ifdef XPAR_GMII2RGMIICON_0N_ETH1_ADDR + convphyaddr = XPAR_GMII2RGMIICON_0N_ETH1_ADDR; + conv_present = 1; +#endif +#endif + +#ifdef CONFIG_LINKSPEED_AUTODETECT + link_speed = get_IEEE_phy_speed(xemacpsp); + if (link_speed == 1000) { + SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,1000); + convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED1000_FD; + } else if (link_speed == 100) { + SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,100); + convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED100_FD; + } else { + SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,10); + convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED10_FD; + } +#elif defined(CONFIG_LINKSPEED1000) + SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,1000); + link_speed = 1000; + configure_IEEE_phy_speed(xemacpsp, link_speed); + convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED1000_FD; + sleep(1); +#elif defined(CONFIG_LINKSPEED100) + SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,100); + link_speed = 100; + configure_IEEE_phy_speed(xemacpsp, link_speed); + convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED100_FD; + sleep(1); +#elif defined(CONFIG_LINKSPEED10) + SetUpSLCRDivisors(xemacpsp->Config.BaseAddress,10); + link_speed = 10; + configure_IEEE_phy_speed(xemacpsp, link_speed); + convspeeddupsetting = XEMACPS_GMII2RGMII_SPEED10_FD; + sleep(1); +#endif + if (conv_present) { + XEmacPs_PhyWrite(xemacpsp, convphyaddr, + XEMACPS_GMII2RGMII_REG_NUM, convspeeddupsetting); + } + + xil_printf("link speed: %d\r\n", link_speed); + return link_speed; +} + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/netif/xpqueue.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/netif/xpqueue.c new file mode 100644 index 000000000..6802c1310 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/netif/xpqueue.c @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2007-13 Xilinx, Inc. All rights reserved. + * + * Xilinx, Inc. + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR + * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION + * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE + * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO + * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE + * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#include + +#include "netif/xpqueue.h" + +#define NUM_QUEUES 2 + +pq_queue_t pq_queue[NUM_QUEUES]; + +pq_queue_t * +pq_create_queue() +{ + static int i; + pq_queue_t *q = NULL; + + if (i >= NUM_QUEUES) { + //xil_printf("ERR: Max Queues allocated\n\r"); + return q; + } + + q = &pq_queue[i++]; + + if (!q) + return q; + + q->head = q->tail = q->len = 0; + + return q; +} + +int +pq_enqueue(pq_queue_t *q, void *p) +{ + if (q->len == PQ_QUEUE_SIZE) + return -1; + + q->data[q->head] = p; + q->head = (q->head + 1)%PQ_QUEUE_SIZE; + q->len++; + + return 0; +} + +void* +pq_dequeue(pq_queue_t *q) +{ + int ptail; + + if (q->len == 0) + return NULL; + + ptail = q->tail; + q->tail = (q->tail + 1)%PQ_QUEUE_SIZE; + q->len--; + + return q->data[ptail]; +} + +int +pq_qlength(pq_queue_t *q) +{ + return q->len; +} diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/netif/xtopology_g.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/netif/xtopology_g.c new file mode 100644 index 000000000..128583e59 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/netif/xtopology_g.c @@ -0,0 +1,15 @@ +#include "netif/xtopology.h" +#include "xparameters.h" + +struct xtopology_t xtopology[] = { + { + 0xE000B000, + xemac_type_emacps, + 0x0, + 0x0, + 0xF8F00100, + 0x36, + }, +}; + +int xtopology_n_emacs = 1; diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/sys_arch.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/sys_arch.c new file mode 100644 index 000000000..2f0ef4049 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/lwIP_port/sys_arch.c @@ -0,0 +1,603 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +//***************************************************************************** +// +// Include OS functionality. +// +//***************************************************************************** + +/* ------------------------ System architecture includes ----------------------------- */ +#include "arch/sys_arch.h" + +/* ------------------------ lwIP includes --------------------------------- */ +#include "lwip/opt.h" + +#include "lwip/debug.h" +#include "lwip/def.h" +#include "lwip/sys.h" +#include "lwip/mem.h" +#include "lwip/stats.h" + +/* Very crude mechanism used to determine if the critical section handling +functions are being called from an interrupt context or not. This relies on +the interrupt handler setting this variable manually. */ +BaseType_t xInsideISR = pdFALSE; + +/*---------------------------------------------------------------------------* + * Routine: sys_mbox_new + *---------------------------------------------------------------------------* + * Description: + * Creates a new mailbox + * Inputs: + * int size -- Size of elements in the mailbox + * Outputs: + * sys_mbox_t -- Handle to new mailbox + *---------------------------------------------------------------------------*/ +err_t sys_mbox_new( sys_mbox_t *pxMailBox, int iSize ) +{ +err_t xReturn = ERR_MEM; + + *pxMailBox = xQueueCreate( iSize, sizeof( void * ) ); + + if( *pxMailBox != NULL ) + { + xReturn = ERR_OK; + SYS_STATS_INC_USED( mbox ); + } + + return xReturn; +} + + +/*---------------------------------------------------------------------------* + * Routine: sys_mbox_free + *---------------------------------------------------------------------------* + * Description: + * Deallocates a mailbox. If there are messages still present in the + * mailbox when the mailbox is deallocated, it is an indication of a + * programming error in lwIP and the developer should be notified. + * Inputs: + * sys_mbox_t mbox -- Handle of mailbox + * Outputs: + * sys_mbox_t -- Handle to new mailbox + *---------------------------------------------------------------------------*/ +void sys_mbox_free( sys_mbox_t *pxMailBox ) +{ +unsigned long ulMessagesWaiting; + + ulMessagesWaiting = uxQueueMessagesWaiting( *pxMailBox ); + configASSERT( ( ulMessagesWaiting == 0 ) ); + + #if SYS_STATS + { + if( ulMessagesWaiting != 0UL ) + { + SYS_STATS_INC( mbox.err ); + } + + SYS_STATS_DEC( mbox.used ); + } + #endif /* SYS_STATS */ + + vQueueDelete( *pxMailBox ); +} + +/*---------------------------------------------------------------------------* + * Routine: sys_mbox_post + *---------------------------------------------------------------------------* + * Description: + * Post the "msg" to the mailbox. + * Inputs: + * sys_mbox_t mbox -- Handle of mailbox + * void *data -- Pointer to data to post + *---------------------------------------------------------------------------*/ +void sys_mbox_post( sys_mbox_t *pxMailBox, void *pxMessageToPost ) +{ + while( xQueueSendToBack( *pxMailBox, &pxMessageToPost, portMAX_DELAY ) != pdTRUE ); +} + +/*---------------------------------------------------------------------------* + * Routine: sys_mbox_trypost + *---------------------------------------------------------------------------* + * Description: + * Try to post the "msg" to the mailbox. Returns immediately with + * error if cannot. + * Inputs: + * sys_mbox_t mbox -- Handle of mailbox + * void *msg -- Pointer to data to post + * Outputs: + * err_t -- ERR_OK if message posted, else ERR_MEM + * if not. + *---------------------------------------------------------------------------*/ +err_t sys_mbox_trypost( sys_mbox_t *pxMailBox, void *pxMessageToPost ) +{ +err_t xReturn; +portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + + if( xInsideISR != pdFALSE ) + { + xReturn = xQueueSendFromISR( *pxMailBox, &pxMessageToPost, &xHigherPriorityTaskWoken ); + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + } + else + { + xReturn = xQueueSend( *pxMailBox, &pxMessageToPost, ( TickType_t ) 0 ); + } + + if( xReturn == pdPASS ) + { + xReturn = ERR_OK; + } + else + { + /* The queue was already full. */ + xReturn = ERR_MEM; + SYS_STATS_INC( mbox.err ); + } + + return xReturn; +} + +/*---------------------------------------------------------------------------* + * Routine: sys_arch_mbox_fetch + *---------------------------------------------------------------------------* + * Description: + * Blocks the thread until a message arrives in the mailbox, but does + * not block the thread longer than "timeout" milliseconds (similar to + * the sys_arch_sem_wait() function). The "msg" argument is a result + * parameter that is set by the function (i.e., by doing "*msg = + * ptr"). The "msg" parameter maybe NULL to indicate that the message + * should be dropped. + * + * The return values are the same as for the sys_arch_sem_wait() function: + * Number of milliseconds spent waiting or SYS_ARCH_TIMEOUT if there was a + * timeout. + * + * Note that a function with a similar name, sys_mbox_fetch(), is + * implemented by lwIP. + * Inputs: + * sys_mbox_t mbox -- Handle of mailbox + * void **msg -- Pointer to pointer to msg received + * u32_t timeout -- Number of milliseconds until timeout + * Outputs: + * u32_t -- SYS_ARCH_TIMEOUT if timeout, else number + * of milliseconds until received. + *---------------------------------------------------------------------------*/ +u32_t sys_arch_mbox_fetch( sys_mbox_t *pxMailBox, void **ppvBuffer, u32_t ulTimeOut ) +{ +void *pvDummy; +TickType_t xStartTime, xEndTime, xElapsed; +unsigned long ulReturn; + + xStartTime = xTaskGetTickCount(); + + if( NULL == ppvBuffer ) + { + ppvBuffer = &pvDummy; + } + + if( ulTimeOut != 0UL ) + { + configASSERT( xInsideISR == ( portBASE_TYPE ) 0 ); + + if( pdTRUE == xQueueReceive( *pxMailBox, &( *ppvBuffer ), ulTimeOut/ portTICK_PERIOD_MS ) ) + { + xEndTime = xTaskGetTickCount(); + xElapsed = ( xEndTime - xStartTime ) * portTICK_PERIOD_MS; + + ulReturn = xElapsed; + } + else + { + /* Timed out. */ + *ppvBuffer = NULL; + ulReturn = SYS_ARCH_TIMEOUT; + } + } + else + { + while( pdTRUE != xQueueReceive( *pxMailBox, &( *ppvBuffer ), portMAX_DELAY ) ); + xEndTime = xTaskGetTickCount(); + xElapsed = ( xEndTime - xStartTime ) * portTICK_PERIOD_MS; + + if( xElapsed == 0UL ) + { + xElapsed = 1UL; + } + + ulReturn = xElapsed; + } + + return ulReturn; +} + +/*---------------------------------------------------------------------------* + * Routine: sys_arch_mbox_tryfetch + *---------------------------------------------------------------------------* + * Description: + * Similar to sys_arch_mbox_fetch, but if message is not ready + * immediately, we'll return with SYS_MBOX_EMPTY. On success, 0 is + * returned. + * Inputs: + * sys_mbox_t mbox -- Handle of mailbox + * void **msg -- Pointer to pointer to msg received + * Outputs: + * u32_t -- SYS_MBOX_EMPTY if no messages. Otherwise, + * return ERR_OK. + *---------------------------------------------------------------------------*/ +u32_t sys_arch_mbox_tryfetch( sys_mbox_t *pxMailBox, void **ppvBuffer ) +{ +void *pvDummy; +unsigned long ulReturn; +long lResult; +portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + + if( ppvBuffer== NULL ) + { + ppvBuffer = &pvDummy; + } + + if( xInsideISR != pdFALSE ) + { + lResult = xQueueReceiveFromISR( *pxMailBox, &( *ppvBuffer ), &xHigherPriorityTaskWoken ); + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + } + else + { + lResult = xQueueReceive( *pxMailBox, &( *ppvBuffer ), 0UL ); + } + + if( lResult == pdPASS ) + { + ulReturn = ERR_OK; + } + else + { + ulReturn = SYS_MBOX_EMPTY; + } + + return ulReturn; +} + +/*---------------------------------------------------------------------------* + * Routine: sys_sem_new + *---------------------------------------------------------------------------* + * Description: + * Creates and returns a new semaphore. The "ucCount" argument specifies + * the initial state of the semaphore. + * NOTE: Currently this routine only creates counts of 1 or 0 + * Inputs: + * sys_mbox_t mbox -- Handle of mailbox + * u8_t ucCount -- Initial ucCount of semaphore (1 or 0) + * Outputs: + * sys_sem_t -- Created semaphore or 0 if could not create. + *---------------------------------------------------------------------------*/ +err_t sys_sem_new( sys_sem_t *pxSemaphore, u8_t ucCount ) +{ +err_t xReturn = ERR_MEM; + + //vSemaphoreCreateBinary( ( *pxSemaphore ) ); + *pxSemaphore = xSemaphoreCreateCounting( 0xffff, ( unsigned long ) ucCount ); + + if( *pxSemaphore != NULL ) + { + if( ucCount == 0U ) + { +// xSemaphoreTake( *pxSemaphore, 1UL ); + } + + xReturn = ERR_OK; + SYS_STATS_INC_USED( sem ); + } + else + { + SYS_STATS_INC( sem.err ); + } + + return xReturn; +} + +/*---------------------------------------------------------------------------* + * Routine: sys_arch_sem_wait + *---------------------------------------------------------------------------* + * Description: + * Blocks the thread while waiting for the semaphore to be + * signaled. If the "timeout" argument is non-zero, the thread should + * only be blocked for the specified time (measured in + * milliseconds). + * + * If the timeout argument is non-zero, the return value is the number of + * milliseconds spent waiting for the semaphore to be signaled. If the + * semaphore wasn't signaled within the specified time, the return value is + * SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore + * (i.e., it was already signaled), the function may return zero. + * + * Notice that lwIP implements a function with a similar name, + * sys_sem_wait(), that uses the sys_arch_sem_wait() function. + * Inputs: + * sys_sem_t sem -- Semaphore to wait on + * u32_t timeout -- Number of milliseconds until timeout + * Outputs: + * u32_t -- Time elapsed or SYS_ARCH_TIMEOUT. + *---------------------------------------------------------------------------*/ +u32_t sys_arch_sem_wait( sys_sem_t *pxSemaphore, u32_t ulTimeout ) +{ +TickType_t xStartTime, xEndTime, xElapsed; +unsigned long ulReturn; + + xStartTime = xTaskGetTickCount(); + + if( ulTimeout != 0UL ) + { + if( xSemaphoreTake( *pxSemaphore, ulTimeout / portTICK_PERIOD_MS ) == pdTRUE ) + { + xEndTime = xTaskGetTickCount(); + xElapsed = (xEndTime - xStartTime) * portTICK_PERIOD_MS; + ulReturn = xElapsed; + } + else + { + ulReturn = SYS_ARCH_TIMEOUT; + } + } + else + { + while( xSemaphoreTake( *pxSemaphore, portMAX_DELAY ) != pdTRUE ); + xEndTime = xTaskGetTickCount(); + xElapsed = ( xEndTime - xStartTime ) * portTICK_PERIOD_MS; + + if( xElapsed == 0UL ) + { + xElapsed = 1UL; + } + + ulReturn = xElapsed; + } + + return ulReturn; +} + +/** Create a new mutex + * @param mutex pointer to the mutex to create + * @return a new mutex */ +err_t sys_mutex_new( sys_mutex_t *pxMutex ) +{ +err_t xReturn = ERR_MEM; + + *pxMutex = xSemaphoreCreateMutex(); + + if( *pxMutex != NULL ) + { + xReturn = ERR_OK; + SYS_STATS_INC_USED( mutex ); + } + else + { + SYS_STATS_INC( mutex.err ); + } + + return xReturn; +} + +/** Lock a mutex + * @param mutex the mutex to lock */ +void sys_mutex_lock( sys_mutex_t *pxMutex ) +{ +BaseType_t xGotSemaphore; +BaseType_t xHigherPriorityTaskWoken = pdFALSE; + + if( xInsideISR == 0 ) + { + while( xSemaphoreTake( *pxMutex, portMAX_DELAY ) != pdPASS ); + } + else + { + xGotSemaphore = xSemaphoreTakeFromISR( *pxMutex, &xHigherPriorityTaskWoken ); + configASSERT( xGotSemaphore ); + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + + /* Prevent compiler warnings if configASSERT() is not defined. */ + ( void ) xGotSemaphore; + } +} + +/** Unlock a mutex + * @param mutex the mutex to unlock */ +void sys_mutex_unlock(sys_mutex_t *pxMutex ) +{ + xSemaphoreGive( *pxMutex ); +} + + +/** Delete a semaphore + * @param mutex the mutex to delete */ +void sys_mutex_free( sys_mutex_t *pxMutex ) +{ + SYS_STATS_DEC( mutex.used ); + vQueueDelete( *pxMutex ); +} + + +/*---------------------------------------------------------------------------* + * Routine: sys_sem_signal + *---------------------------------------------------------------------------* + * Description: + * Signals (releases) a semaphore + * Inputs: + * sys_sem_t sem -- Semaphore to signal + *---------------------------------------------------------------------------*/ +void sys_sem_signal( sys_sem_t *pxSemaphore ) +{ +portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + + if( xInsideISR != pdFALSE ) + { + xSemaphoreGiveFromISR( *pxSemaphore, &xHigherPriorityTaskWoken ); + portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + } + else + { + xSemaphoreGive( *pxSemaphore ); + } +} + +/*---------------------------------------------------------------------------* + * Routine: sys_sem_free + *---------------------------------------------------------------------------* + * Description: + * Deallocates a semaphore + * Inputs: + * sys_sem_t sem -- Semaphore to free + *---------------------------------------------------------------------------*/ +void sys_sem_free( sys_sem_t *pxSemaphore ) +{ + SYS_STATS_DEC(sem.used); + vQueueDelete( *pxSemaphore ); +} + +/*---------------------------------------------------------------------------* + * Routine: sys_init + *---------------------------------------------------------------------------* + * Description: + * Initialize sys arch + *---------------------------------------------------------------------------*/ +void sys_init(void) +{ +} + +u32_t sys_now(void) +{ + return xTaskGetTickCount(); +} + +/*---------------------------------------------------------------------------* + * Routine: sys_thread_new + *---------------------------------------------------------------------------* + * Description: + * Starts a new thread with priority "prio" that will begin its + * execution in the function "thread()". The "arg" argument will be + * passed as an argument to the thread() function. The id of the new + * thread is returned. Both the id and the priority are system + * dependent. + * Inputs: + * char *name -- Name of thread + * void (* thread)(void *arg) -- Pointer to function to run. + * void *arg -- Argument passed into function + * int stacksize -- Required stack amount in bytes + * int prio -- Thread priority + * Outputs: + * sys_thread_t -- Pointer to per-thread timeouts. + *---------------------------------------------------------------------------*/ +sys_thread_t sys_thread_new( const char *pcName, void( *pxThread )( void *pvParameters ), void *pvArg, int iStackSize, int iPriority ) +{ +TaskHandle_t xCreatedTask; +portBASE_TYPE xResult; +sys_thread_t xReturn; + + xResult = xTaskCreate( pxThread, pcName, iStackSize, pvArg, iPriority, &xCreatedTask ); + + if( xResult == pdPASS ) + { + xReturn = xCreatedTask; + } + else + { + xReturn = NULL; + } + + return xReturn; +} + +/*---------------------------------------------------------------------------* + * Routine: sys_arch_protect + *---------------------------------------------------------------------------* + * Description: + * This optional function does a "fast" critical region protection and + * returns the previous protection level. This function is only called + * during very short critical regions. An embedded system which supports + * ISR-based drivers might want to implement this function by disabling + * interrupts. Task-based systems might want to implement this by using + * a mutex or disabling tasking. This function should support recursive + * calls from the same task or interrupt. In other words, + * sys_arch_protect() could be called while already protected. In + * that case the return value indicates that it is already protected. + * + * sys_arch_protect() is only required if your port is supporting an + * operating system. + * Outputs: + * sys_prot_t -- Previous protection level (not used here) + *---------------------------------------------------------------------------*/ +sys_prot_t sys_arch_protect( void ) +{ + if( xInsideISR == pdFALSE ) + { + taskENTER_CRITICAL(); + } + return ( sys_prot_t ) 1; +} + +/*---------------------------------------------------------------------------* + * Routine: sys_arch_unprotect + *---------------------------------------------------------------------------* + * Description: + * This optional function does a "fast" set of critical region + * protection to the value specified by pval. See the documentation for + * sys_arch_protect() for more information. This function is only + * required if your port is supporting an operating system. + * Inputs: + * sys_prot_t -- Previous protection level (not used here) + *---------------------------------------------------------------------------*/ +void sys_arch_unprotect( sys_prot_t xValue ) +{ + (void) xValue; + if( xInsideISR == pdFALSE ) + { + taskEXIT_CRITICAL(); + } +} + +/* + * Prints an assertion messages and aborts execution. + */ +void sys_assert( const char *pcMessage ) +{ + (void) pcMessage; + + for (;;) + { + } +} +/*-------------------------------------------------------------------------* + * End of File: sys_arch.c + *-------------------------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/main_lwIP.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/main_lwIP.c new file mode 100644 index 000000000..af88e29fa --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwIP_Demo/main_lwIP.c @@ -0,0 +1,184 @@ +/* + FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides three demo applications. A simple blinky + * style project, a more comprehensive test and demo application, and an + * lwIP example. The mainSELECTED_APPLICATION setting in main.c is used to + * select between the three. See the notes on using mainSELECTED_APPLICATION + * in main.c. This file implements the simply blinky style version. + * + * NOTE 2: This file only contains the source code that is specific to the + * basic demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware are defined in main.c. + ****************************************************************************** + * + * The lwIP example can be configured to use either a static or dynamic IP + * address: + * + To use a dynamically allocated IP address set LWIP_DHCP to 1 in + * lwipopts.h and connect the target to a network that includes a DHCP + * server. The obtained IP address is printed to the UART console. + * + To use a static IP address set LWIP_DHCP to 0 in lwipopts.h and set + * the static IP address using the configIP_ADDR0 to configIP_ADDR3 + * constants at the bottom of FreeRTOSConfig.h. Constants used to define + * a netmask are also located at the bottom of FreeRTOSConfig.h. + * + * When connected correctly the demo uses the lwIP sockets API to create + * a FreeRTOS+CLI command console, and the lwIP raw API to create a create a + * basic HTTP web server with server side includes that generate dynamic run + * time web pages. See http://www.freertos.org/RTOS-Xilinx-Zynq.html for more + * information. + * + * To connect to FreeRTOS+CLI, open a command prompt and enter "telnet " + * where is the IP address of the target. Once connected type "help" + * to see a list of registered commands. Note this example does not implement + * a real telnet server, it just uses the telnet port number to allow easy + * connection using telnet tools. + * + * To connect to the http server simply type the IP address of the target into + * the address bar of a web browser. + * + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" + +/* Standard demo includes. */ +#include "partest.h" + +/* lwIP includes. */ +#include "lwip/tcpip.h" + +/* The rate at which data is sent to the queue. The 200ms value is converted +to ticks using the portTICK_PERIOD_MS constant. */ +#define mainTIMER_PERIOD_MS ( 200 / portTICK_PERIOD_MS ) + +/* The LED toggled by the Rx task. */ +#define mainTIMER_LED ( 0 ) + +/* A block time of zero just means "don't block". */ +#define mainDONT_BLOCK ( 0 ) + +/*-----------------------------------------------------------*/ + +/* + * The callback for the timer that just toggles an LED to show the system is + * running. + */ +static void prvLEDToggleTimer( TimerHandle_t pxTimer ); + +/* + * Defined in lwIPApps.c. + */ +extern void lwIPAppsInit( void *pvArguments ); + +/*-----------------------------------------------------------*/ + +void main_lwIP( void ) +{ +TimerHandle_t xTimer; + + /* Init lwIP and start lwIP tasks. */ + tcpip_init( lwIPAppsInit, NULL ); + + /* A timer is used to toggle an LED just to show the application is + executing. */ + xTimer = xTimerCreate( "LED", /* Text name to make debugging easier. */ + mainTIMER_PERIOD_MS, /* The timer's period. */ + pdTRUE, /* This is an auto reload timer. */ + NULL, /* ID is not used. */ + prvLEDToggleTimer ); /* The callback function. */ + + /* Start the timer. */ + configASSERT( xTimer ); + xTimerStart( xTimer, mainDONT_BLOCK ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was either insufficient FreeRTOS heap memory available for the idle + and/or timer tasks to be created, or vTaskStartScheduler() was called from + User mode. See the memory management section on the FreeRTOS web site for + more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + mode from which main() is called is set in the C start up code and must be + a privileged mode (not user mode). */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvLEDToggleTimer( TimerHandle_t pxTimer ) +{ + /* Prevent compiler warnings. */ + ( void ) pxTimer; + + /* Just toggle an LED to show the application is running. */ + vParTestToggleLED( mainTIMER_LED ); +} + +/*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwipopts.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwipopts.h new file mode 100644 index 000000000..30025dc2d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwipopts.h @@ -0,0 +1,312 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIPOPTS_H__ +#define __LWIPOPTS_H__ + +#include + +/* Functions used to obtain and release exclusive access to the Tx buffer. The +Get function will block if the Tx buffer is not available - use with care! */ +signed char *pcLwipBlockingGetTxBuffer( void ); +void vLwipAppsReleaseTxBuffer( void ); + +#define CONFIG_LINKSPEED_AUTODETECT 1 +#define OS_IS_FREERTOS + +/* SSI options. */ +#define TCPIP_THREAD_NAME "tcpip" +#define LWIP_HTTPD_MAX_TAG_NAME_LEN 20 +#define LWIP_HTTPD_MAX_TAG_INSERT_LEN 1024 +#define TCPIP_THREAD_PRIO configLWIP_TASK_PRIORITY +#define TCPIP_THREAD_STACKSIZE configMINIMAL_STACK_SIZE * 3 + +#define DEFAULT_TCP_RECVMBOX_SIZE 5 +#define DEFAULT_ACCEPTMBOX_SIZE 5 +#define TCPIP_MBOX_SIZE 10 + +#define NO_SYS 0 +#define LWIP_SOCKET (NO_SYS==0) +#define LWIP_NETCONN 1 + +#define LWIP_SNMP 0 +#define LWIP_IGMP 0 +#define LWIP_ICMP 1 + +/* DNS is not going to be used as this is a simple local example. */ +#define LWIP_DNS 0 + +#define LWIP_HAVE_LOOPIF 0 +#define TCP_LISTEN_BACKLOG 0 +#define LWIP_SO_RCVTIMEO 1 +#define LWIP_SO_RCVBUF 1 + +//#define LWIP_DEBUG +#ifdef LWIP_DEBUG + +#define LWIP_DBG_MIN_LEVEL LWIP_DBG_LEVEL_ALL // LWIP_DBG_LEVEL_SERIOUS +#define PPP_DEBUG LWIP_DBG_OFF +#define MEM_DEBUG LWIP_DBG_OFF +#define MEMP_DEBUG LWIP_DBG_OFF +#define PBUF_DEBUG LWIP_DBG_OFF +#define API_LIB_DEBUG LWIP_DBG_OFF +#define API_MSG_DEBUG LWIP_DBG_OFF +#define TCPIP_DEBUG LWIP_DBG_OFF +#define NETIF_DEBUG LWIP_DBG_OFF +#define SOCKETS_DEBUG LWIP_DBG_OFF +#define DNS_DEBUG LWIP_DBG_OFF +#define AUTOIP_DEBUG LWIP_DBG_OFF +#define DHCP_DEBUG LWIP_DBG_ON +#define IP_DEBUG LWIP_DBG_OFF +#define IP_REASS_DEBUG LWIP_DBG_OFF +#define ICMP_DEBUG LWIP_DBG_OFF +#define IGMP_DEBUG LWIP_DBG_OFF +#define UDP_DEBUG LWIP_DBG_OFF +#define TCP_DEBUG LWIP_DBG_OFF +#define TCP_INPUT_DEBUG LWIP_DBG_OFF +#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF +#define TCP_RTO_DEBUG LWIP_DBG_OFF +#define TCP_CWND_DEBUG LWIP_DBG_OFF +#define TCP_WND_DEBUG LWIP_DBG_OFF +#define TCP_FR_DEBUG LWIP_DBG_OFF +#define TCP_QLEN_DEBUG LWIP_DBG_OFF +#define TCP_RST_DEBUG LWIP_DBG_OFF +#endif + +#define LWIP_DBG_TYPES_ON (LWIP_DBG_ON|LWIP_DBG_TRACE|LWIP_DBG_STATE|LWIP_DBG_FRESH|LWIP_DBG_HALT) + + + +/* ---------- Memory options ---------- */ +/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which + lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2 + byte alignment -> define MEM_ALIGNMENT to 2. */ +/* MSVC port: intel processors don't need 4-byte alignment, + but are faster that way! */ +#define MEM_ALIGNMENT 64 + +/* MEM_SIZE: the size of the heap memory. If the application will send +a lot of data that needs to be copied, this should be set high. */ +#define MEM_SIZE 0x20000 + +/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application + sends a lot of data out of ROM (or other static memory), this + should be set high. */ +#define MEMP_NUM_PBUF 16 + +/* MEMP_NUM_RAW_PCB: the number of UDP protocol control blocks. One + per active RAW "connection". */ +#define LWIP_RAW 0 +#define MEMP_NUM_RAW_PCB 0 + +/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One + per active UDP "connection". */ +#define MEMP_NUM_UDP_PCB 4 + +/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP + connections. */ +#define MEMP_NUM_TCP_PCB 32 + +/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP + connections. */ +#define MEMP_NUM_TCP_PCB_LISTEN 8 + +/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP + segments. */ +#define MEMP_NUM_TCP_SEG 256 + +/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active + timeouts. */ +#define MEMP_NUM_SYS_TIMEOUT 8 + +/* The following four are used only with the sequential API and can be + set to 0 if the application only will use the raw API. */ +/* MEMP_NUM_NETBUF: the number of struct netbufs. */ +#define MEMP_NUM_NETBUF 0 + +/* MEMP_NUM_NETCONN: the number of struct netconns. */ +#define MEMP_NUM_NETCONN 10 + +/* MEMP_NUM_TCPIP_MSG_*: the number of struct tcpip_msg, which is used + for sequential API communication and incoming packets. Used in + src/api/tcpip.c. */ +#define MEMP_NUM_TCPIP_MSG_API 4 +#define MEMP_NUM_TCPIP_MSG_INPKT 4 + +#define MEMP_NUM_ARP_QUEUE 5 + +/* ---------- Pbuf options ---------- */ +/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */ +#define PBUF_POOL_SIZE 256 + +/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */ +#define PBUF_POOL_BUFSIZE 1700 + +/* PBUF_LINK_HLEN: the number of bytes that should be allocated for a + link level header. */ +#define PBUF_LINK_HLEN 16 + +/** SYS_LIGHTWEIGHT_PROT + * define SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection + * for certain critical regions during buffer allocation, deallocation and memory + * allocation and deallocation. + */ +#define SYS_LIGHTWEIGHT_PROT (NO_SYS==0) + + +/* ---------- TCP options ---------- */ +#define LWIP_TCP 1 +#define TCP_TTL 255 + +/* Controls if TCP should queue segments that arrive out of + order. Define to 0 if your device is low on memory. */ +#define TCP_QUEUE_OOSEQ 1 + +/* TCP Maximum segment size. */ +#define TCP_MSS 1460 + +/* TCP sender buffer space (bytes). */ +#define TCP_SND_BUF 8129 + +/* TCP sender buffer space (pbufs). This must be at least = 2 * + TCP_SND_BUF/TCP_MSS for things to work. */ +#define TCP_SND_QUEUELEN (16 * TCP_SND_BUF/TCP_MSS) + +/* TCP writable space (bytes). This must be less than or equal + to TCP_SND_BUF. It is the amount of space which must be + available in the tcp snd_buf for select to return writable */ +#define TCP_SNDLOWAT (TCP_SND_BUF/2) + +/* TCP receive window. */ +#define TCP_WND ( 2048 ) + +/* Maximum number of retransmissions of data segments. */ +#define TCP_MAXRTX 12 + +/* Maximum number of retransmissions of SYN segments. */ +#define TCP_SYNMAXRTX 4 + + +/* ---------- ARP options ---------- */ +#define LWIP_ARP 1 +#define ARP_TABLE_SIZE 10 +#define ARP_QUEUEING 1 + +#define ICMP_TTL 255 + +#define IP_OPTIONS 0 + +/* ---------- IP options ---------- */ +/* Define IP_FORWARD to 1 if you wish to have the ability to forward + IP packets across network interfaces. If you are going to run lwIP + on a device with only one network interface, define this to 0. */ +#define IP_FORWARD 0 + +/* IP reassembly and segmentation.These are orthogonal even + * if they both deal with IP fragments */ +#define IP_REASSEMBLY 0 +#define IP_REASS_MAX_PBUFS 10 +#define MEMP_NUM_REASSDATA 10 +#define IP_FRAG 0 + + +/* ---------- ICMP options ---------- */ +#define ICMP_TTL 255 + + +/* ---------- DHCP options ---------- */ +/* Define LWIP_DHCP to 1 if you want DHCP configuration of + interfaces. */ +#define LWIP_DHCP 0 + +/* 1 if you want to do an ARP check on the offered address + (recommended). */ +#define DHCP_DOES_ARP_CHECK (LWIP_DHCP) + + +/* ---------- AUTOIP options ------- */ +#define LWIP_AUTOIP 0 +#define LWIP_DHCP_AUTOIP_COOP (LWIP_DHCP && LWIP_AUTOIP) + + +/* ---------- UDP options ---------- */ +#define LWIP_UDP 1 +#define LWIP_UDPLITE 1 +#define UDP_TTL 255 + + +/* ---------- Statistics options ---------- */ + +#define LWIP_STATS 1 +#define LWIP_STATS_DISPLAY 0 + +#if LWIP_STATS + #define LINK_STATS 1 + #define IP_STATS 1 + #define ICMP_STATS 0 + #define IGMP_STATS 0 + #define IPFRAG_STATS 0 + #define UDP_STATS 1 + #define TCP_STATS 1 + #define MEM_STATS 1 + #define MEMP_STATS 1 + #define PBUF_STATS 1 + #define SYS_STATS 1 +#endif /* LWIP_STATS */ + + +/* ---------- PPP options ---------- */ + +#define PPP_SUPPORT 0 /* Set > 0 for PPP */ + +#if PPP_SUPPORT + + #define NUM_PPP 1 /* Max PPP sessions. */ + + /* Select modules to enable. Ideally these would be set in the makefile but + * we're limited by the command line length so you need to modify the settings + * in this file. + */ + #define PPPOE_SUPPORT 1 + #define PPPOS_SUPPORT 1 + #define PAP_SUPPORT 1 /* Set > 0 for PAP. */ + #define CHAP_SUPPORT 1 /* Set > 0 for CHAP. */ + #define MSCHAP_SUPPORT 0 /* Set > 0 for MSCHAP (NOT FUNCTIONAL!) */ + #define CBCP_SUPPORT 0 /* Set > 0 for CBCP (NOT FUNCTIONAL!) */ + #define CCP_SUPPORT 0 /* Set > 0 for CCP (NOT FUNCTIONAL!) */ + #define VJ_SUPPORT 1 /* Set > 0 for VJ header compression. */ + #define MD5_SUPPORT 1 /* Set > 0 for MD5 (see also CHAP) */ + +#endif /* PPP_SUPPORT */ + +#define LWIP_NETIF_STATUS_CALLBACK 1 + +#endif /* __LWIPOPTS_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/main.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/main.c new file mode 100644 index 000000000..5019093db --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/main.c @@ -0,0 +1,388 @@ +/* + FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * This project provides three demo applications. A simple blinky style + * project, a more comprehensive test and demo application, and an lwIP example. + * The mainSELECTED_APPLICATION setting (defined in this file) is used to + * select between the three. The simply blinky demo is implemented and + * described in main_blinky.c. The more comprehensive test and demo application + * is implemented and described in main_full.c. The lwIP example is implemented + * and described in main_lwIP.c. + * + * This file implements the code that is not demo specific, including the + * hardware setup and FreeRTOS hook functions. + * + * !!! IMPORTANT NOTE !!! + * The GCC libraries that ship with the Xilinx SDK make use of the floating + * point registers. To avoid this causing corruption it is necessary to avoid + * their use. For this reason main.c contains very basic C implementations of + * the standard C library functions memset(), memcpy() and memcmp(), which are + * are used by FreeRTOS itself. Defining these functions in the project + * prevents the linker pulling them in from the library. Any other standard C + * library functions that are used by the application must likewise be defined + * in C. + * + * ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON + * THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO + * APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT! + * + */ + +/* Standard includes. */ +#include +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Standard demo includes. */ +#include "partest.h" +#include "TimerDemo.h" +#include "QueueOverwrite.h" +#include "EventGroupsDemo.h" + +/* Xilinx includes. */ +#include "platform.h" +#include "xparameters.h" +#include "xscutimer.h" +#include "xscugic.h" +#include "xil_exception.h" + +/* mainSELECTED_APPLICATION is used to select between three demo applications, + * as described at the top of this file. + * + * When mainSELECTED_APPLICATION is set to 0 the simple blinky example will + * be run. + * + * When mainSELECTED_APPLICATION is set to 1 the comprehensive test and demo + * application will be run. + * + * When mainSELECTED_APPLICATION is set to 2 the lwIP example will be run. + */ +#define mainSELECTED_APPLICATION 1 + +/*-----------------------------------------------------------*/ + +/* + * Configure the hardware as necessary to run this demo. + */ +static void prvSetupHardware( void ); + +/* + * See the comments at the top of this file and above the + * mainSELECTED_APPLICATION definition. + */ +#if ( mainSELECTED_APPLICATION == 0 ) + extern void main_blinky( void ); +#elif ( mainSELECTED_APPLICATION == 1 ) + extern void main_full( void ); +#elif ( mainSELECTED_APPLICATION == 2 ) + extern void main_lwIP( void ); +#else + #error Invalid mainSELECTED_APPLICATION setting. See the comments at the top of this file and above the mainSELECTED_APPLICATION definition. +#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */ + +/* + * The Xilinx projects use a BSP that do not allow the start up code to be + * altered easily. Therefore the vector table used by FreeRTOS is defined in + * FreeRTOS_asm_vectors.S, which is part of this project. Switch to use the + * FreeRTOS vector table. + */ +extern void vPortInstallFreeRTOSVectorTable( void ); + +/* Prototypes for the standard FreeRTOS callback/hook functions implemented +within this file. */ +void vApplicationMallocFailedHook( void ); +void vApplicationIdleHook( void ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationTickHook( void ); + +/* The private watchdog is used as the timer that generates run time +stats. This frequency means it will overflow quite quickly. */ +XScuWdt xWatchDogInstance; + +/*-----------------------------------------------------------*/ + +/* The interrupt controller is initialised in this file, and made available to +other modules. */ +XScuGic xInterruptController; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ +extern void main_lwIP( void ); + + /* Configure the hardware ready to run the demo. */ + prvSetupHardware(); + + /* The mainSELECTED_APPLICATION setting is described at the top + of this file. */ + #if( mainSELECTED_APPLICATION == 0 ) + { + main_blinky(); + } + #elif( mainSELECTED_APPLICATION == 1 ) + { + main_full(); + } + #else + { + main_lwIP(); + } + #endif + + /* Don't expect to reach here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ +BaseType_t xStatus; +XScuGic_Config *pxGICConfig; + + /* Ensure no interrupts execute while the scheduler is in an inconsistent + state. Interrupts are automatically enabled when the scheduler is + started. */ + portDISABLE_INTERRUPTS(); + + /* Obtain the configuration of the GIC. */ + pxGICConfig = XScuGic_LookupConfig( XPAR_SCUGIC_SINGLE_DEVICE_ID ); + + /* Sanity check the FreeRTOSConfig.h settings are correct for the + hardware. */ + configASSERT( pxGICConfig ); + configASSERT( pxGICConfig->CpuBaseAddress == ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ) ); + configASSERT( pxGICConfig->DistBaseAddress == configINTERRUPT_CONTROLLER_BASE_ADDRESS ); + + /* Install a default handler for each GIC interrupt. */ + xStatus = XScuGic_CfgInitialize( &xInterruptController, pxGICConfig, pxGICConfig->CpuBaseAddress ); + configASSERT( xStatus == XST_SUCCESS ); + ( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */ + + /* Initialise the LED port. */ + vParTestInitialise(); + + /* The Xilinx projects use a BSP that do not allow the start up code to be + altered easily. Therefore the vector table used by FreeRTOS is defined in + FreeRTOS_asm_vectors.S, which is part of this project. Switch to use the + FreeRTOS vector table. */ + vPortInstallFreeRTOSVectorTable(); +} +/*-----------------------------------------------------------*/ + +void vApplicationMallocFailedHook( void ) +{ + /* Called if a call to pvPortMalloc() fails because there is insufficient + free memory available in the FreeRTOS heap. pvPortMalloc() is called + internally by FreeRTOS API functions that create tasks, queues, software + timers, and semaphores. The size of the FreeRTOS heap is set by the + configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + taskDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +{ + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + function is called if a stack overflow is detected. */ + taskDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ +volatile size_t xFreeHeapSpace; + + /* This is just a trivial example of an idle hook. It is called on each + cycle of the idle task. It must *NOT* attempt to block. In this case the + idle task just queries the amount of FreeRTOS heap that remains. See the + memory management section on the http://www.FreeRTOS.org web site for memory + management options. If there is a lot of heap memory free then the + configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up + RAM. */ + xFreeHeapSpace = xPortGetFreeHeapSize(); + + /* Remove compiler warning about xFreeHeapSpace being set but never used. */ + ( void ) xFreeHeapSpace; +} +/*-----------------------------------------------------------*/ + +void vAssertCalled( const char * pcFile, unsigned long ulLine ) +{ +volatile unsigned long ul = 0; + + ( void ) pcFile; + ( void ) ulLine; + + taskENTER_CRITICAL(); + { + /* Set ul to a non-zero value using the debugger to step out of this + function. */ + while( ul == 0 ) + { + portNOP(); + } + } + taskEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +void vApplicationTickHook( void ) +{ + #if( mainSELECTED_APPLICATION == 1 ) + { + /* The full demo includes a software timer demo/test that requires + prodding periodically from the tick interrupt. */ + vTimerPeriodicISRTests(); + + /* Call the periodic queue overwrite from ISR demo. */ + vQueueOverwritePeriodicISRDemo(); + + /* Call the periodic event group from ISR demo. */ + vPeriodicEventGroupsProcessing(); + } + #endif +} +/*-----------------------------------------------------------*/ + +void *memcpy( void *pvDest, const void *pvSource, size_t ulBytes ) +{ +unsigned char *pcDest = ( unsigned char * ) pvDest, *pcSource = ( unsigned char * ) pvSource; +size_t x; + + for( x = 0; x < ulBytes; x++ ) + { + *pcDest = *pcSource; + pcDest++; + pcSource++; + } + + return pvDest; +} +/*-----------------------------------------------------------*/ + +void *memset( void *pvDest, int iValue, size_t ulBytes ) +{ +unsigned char *pcDest = ( unsigned char * ) pvDest; +size_t x; + + for( x = 0; x < ulBytes; x++ ) + { + *pcDest = ( unsigned char ) iValue; + pcDest++; + } + + return pvDest; +} +/*-----------------------------------------------------------*/ + +int memcmp( const void *pvMem1, const void *pvMem2, size_t ulBytes ) +{ +const unsigned char *pucMem1 = pvMem1, *pucMem2 = pvMem2; +size_t x; + + for( x = 0; x < ulBytes; x++ ) + { + if( pucMem1[ x ] != pucMem2[ x ] ) + { + break; + } + } + + return ulBytes - x; +} +/*-----------------------------------------------------------*/ + +void vInitialiseTimerForRunTimeStats( void ) +{ +XScuWdt_Config *pxWatchDogInstance; +uint32_t ulValue; +const uint32_t ulMaxDivisor = 0xff, ulDivisorShift = 0x08; + + pxWatchDogInstance = XScuWdt_LookupConfig( XPAR_SCUWDT_0_DEVICE_ID ); + XScuWdt_CfgInitialize( &xWatchDogInstance, pxWatchDogInstance, pxWatchDogInstance->BaseAddr ); + + ulValue = XScuWdt_GetControlReg( &xWatchDogInstance ); + ulValue |= ulMaxDivisor << ulDivisorShift; + XScuWdt_SetControlReg( &xWatchDogInstance, ulValue ); + + XScuWdt_LoadWdt( &xWatchDogInstance, UINT_MAX ); + XScuWdt_SetTimerMode( &xWatchDogInstance ); + XScuWdt_Start( &xWatchDogInstance ); +} + + + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/platform.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/platform.c new file mode 100644 index 000000000..ea7849798 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/platform.c @@ -0,0 +1,112 @@ +/****************************************************************************** +* +* (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ + +#include "xparameters.h" +#include "xil_cache.h" + +#include "platform_config.h" + +/* + * Uncomment the following line if ps7 init source files are added in the + * source directory for compiling example outside of SDK. + */ +/*#include "ps7_init.h"*/ + +#ifdef STDOUT_IS_16550 + #include "xuartns550_l.h" + + #define UART_BAUD 9600 +#endif + +void +enable_caches() +{ +#ifdef __PPC__ + Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK); + Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK); +#elif __MICROBLAZE__ +#ifdef XPAR_MICROBLAZE_USE_ICACHE + Xil_ICacheEnable(); +#endif +#ifdef XPAR_MICROBLAZE_USE_DCACHE + Xil_DCacheEnable(); +#endif +#endif +} + +void +disable_caches() +{ + Xil_DCacheDisable(); + Xil_ICacheDisable(); +} + +void +init_uart() +{ +#ifdef STDOUT_IS_16550 + XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD); + XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS); +#endif +#ifdef STDOUT_IS_PS7_UART + /* Bootrom/BSP configures PS7 UART to 115200 bps */ +#endif +} + +void +init_platform() +{ + /* + * If you want to run this example outside of SDK, + * uncomment the following line and also #include "ps7_init.h" at the top. + * Make sure that the ps7_init.c and ps7_init.h files are included + * along with this example source files for compilation. + */ + /* ps7_init();*/ + enable_caches(); + init_uart(); +} + +void +cleanup_platform() +{ + disable_caches(); +} diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/platform.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/platform.h new file mode 100644 index 000000000..efc90882b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/platform.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2008 Xilinx, Inc. All rights reserved. + * + * Xilinx, Inc. + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR + * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION + * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE + * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO + * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE + * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#ifndef __PLATFORM_H_ +#define __PLATFORM_H_ + +#include "platform_config.h" + +void init_platform(); +void cleanup_platform(); + +#endif diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/platform_config.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/platform_config.h new file mode 100644 index 000000000..3e9b7f184 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/platform_config.h @@ -0,0 +1,6 @@ +#ifndef __PLATFORM_CONFIG_H_ +#define __PLATFORM_CONFIG_H_ + +#define STDOUT_IS_PS7_UART +#define UART_DEVICE_ID 0 +#endif diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/printf-stdarg.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/printf-stdarg.c new file mode 100644 index 000000000..117519837 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/printf-stdarg.c @@ -0,0 +1,285 @@ +/* + Copyright 2001, 2002 Georges Menie (www.menie.org) + stdarg version contributed by Christian Ettinger + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU Lesser General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +/* + putchar is the only external dependency for this file, + if you have a working putchar, leave it commented out. + If not, uncomment the define below and + replace outbyte(c) by your own function call. + +*/ + +#define putchar(c) c + +#include + +static void printchar(char **str, int c) +{ + //extern int putchar(int c); + + if (str) { + **str = (char)c; + ++(*str); + } + else + { + (void)putchar(c); + } +} + +#define PAD_RIGHT 1 +#define PAD_ZERO 2 + +static int prints(char **out, const char *string, int width, int pad) +{ + register int pc = 0, padchar = ' '; + + if (width > 0) { + register int len = 0; + register const char *ptr; + for (ptr = string; *ptr; ++ptr) ++len; + if (len >= width) width = 0; + else width -= len; + if (pad & PAD_ZERO) padchar = '0'; + } + if (!(pad & PAD_RIGHT)) { + for ( ; width > 0; --width) { + printchar (out, padchar); + ++pc; + } + } + for ( ; *string ; ++string) { + printchar (out, *string); + ++pc; + } + for ( ; width > 0; --width) { + printchar (out, padchar); + ++pc; + } + + return pc; +} + +/* the following should be enough for 32 bit int */ +#define PRINT_BUF_LEN 12 + +static int printi(char **out, int i, int b, int sg, int width, int pad, int letbase) +{ + char print_buf[PRINT_BUF_LEN]; + register char *s; + register int t, neg = 0, pc = 0; + register unsigned int u = (unsigned int)i; + + if (i == 0) { + print_buf[0] = '0'; + print_buf[1] = '\0'; + return prints (out, print_buf, width, pad); + } + + if (sg && b == 10 && i < 0) { + neg = 1; + u = (unsigned int)-i; + } + + s = print_buf + PRINT_BUF_LEN-1; + *s = '\0'; + + while (u) { + t = (unsigned int)u % b; + if( t >= 10 ) + t += letbase - '0' - 10; + *--s = (char)(t + '0'); + u /= b; + } + + if (neg) { + if( width && (pad & PAD_ZERO) ) { + printchar (out, '-'); + ++pc; + --width; + } + else { + *--s = '-'; + } + } + + return pc + prints (out, s, width, pad); +} + +static int print( char **out, const char *format, va_list args ) +{ + register int width, pad; + register int pc = 0; + char scr[2]; + + for (; *format != 0; ++format) { + if (*format == '%') { + ++format; + width = pad = 0; + if (*format == '\0') break; + if (*format == '%') goto out; + if (*format == '-') { + ++format; + pad = PAD_RIGHT; + } + while (*format == '0') { + ++format; + pad |= PAD_ZERO; + } + for ( ; *format >= '0' && *format <= '9'; ++format) { + width *= 10; + width += *format - '0'; + } + if( *format == 's' ) { + register char *s = (char *)va_arg( args, int ); + pc += prints (out, s?s:"(null)", width, pad); + continue; + } + if( *format == 'd' ) { + pc += printi (out, va_arg( args, int ), 10, 1, width, pad, 'a'); + continue; + } + if( *format == 'x' ) { + pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'a'); + continue; + } + if( *format == 'X' ) { + pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'A'); + continue; + } + if( *format == 'u' ) { + pc += printi (out, va_arg( args, int ), 10, 0, width, pad, 'a'); + continue; + } + if( *format == 'c' ) { + /* char are converted to int then pushed on the stack */ + scr[0] = (char)va_arg( args, int ); + scr[1] = '\0'; + pc += prints (out, scr, width, pad); + continue; + } + } + else { + out: + printchar (out, *format); + ++pc; + } + } + if (out) **out = '\0'; + va_end( args ); + return pc; +} + +int printf(const char *format, ...) +{ + va_list args; + + va_start( args, format ); + return print( 0, format, args ); +} + +int sprintf(char *out, const char *format, ...) +{ + va_list args; + + va_start( args, format ); + return print( &out, format, args ); +} + + +int snprintf( char *buf, unsigned int count, const char *format, ... ) +{ + va_list args; + + ( void ) count; + + va_start( args, format ); + return print( &buf, format, args ); +} + + +#ifdef TEST_PRINTF +int main(void) +{ + char *ptr = "Hello world!"; + char *np = 0; + int i = 5; + unsigned int bs = sizeof(int)*8; + int mi; + char buf[80]; + + mi = (1 << (bs-1)) + 1; + printf("%s\n", ptr); + printf("printf test\n"); + printf("%s is null pointer\n", np); + printf("%d = 5\n", i); + printf("%d = - max int\n", mi); + printf("char %c = 'a'\n", 'a'); + printf("hex %x = ff\n", 0xff); + printf("hex %02x = 00\n", 0); + printf("signed %d = unsigned %u = hex %x\n", -3, -3, -3); + printf("%d %s(s)%", 0, "message"); + printf("\n"); + printf("%d %s(s) with %%\n", 0, "message"); + sprintf(buf, "justif: \"%-10s\"\n", "left"); printf("%s", buf); + sprintf(buf, "justif: \"%10s\"\n", "right"); printf("%s", buf); + sprintf(buf, " 3: %04d zero padded\n", 3); printf("%s", buf); + sprintf(buf, " 3: %-4d left justif.\n", 3); printf("%s", buf); + sprintf(buf, " 3: %4d right justif.\n", 3); printf("%s", buf); + sprintf(buf, "-3: %04d zero padded\n", -3); printf("%s", buf); + sprintf(buf, "-3: %-4d left justif.\n", -3); printf("%s", buf); + sprintf(buf, "-3: %4d right justif.\n", -3); printf("%s", buf); + + return 0; +} + +/* + * if you compile this file with + * gcc -Wall $(YOUR_C_OPTIONS) -DTEST_PRINTF -c printf.c + * you will get a normal warning: + * printf.c:214: warning: spurious trailing `%' in format + * this line is testing an invalid % at the end of the format string. + * + * this should display (on 32bit int machine) : + * + * Hello world! + * printf test + * (null) is null pointer + * 5 = 5 + * -2147483647 = - max int + * char a = 'a' + * hex ff = ff + * hex 00 = 00 + * signed -3 = unsigned 4294967293 = hex fffffffd + * 0 message(s) + * 0 message(s) with % + * justif: "left " + * justif: " right" + * 3: 0003 zero padded + * 3: 3 left justif. + * 3: 3 right justif. + * -3: -003 zero padded + * -3: -3 left justif. + * -3: -3 right justif. + */ + +#endif + + + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/.cproject b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/.cproject new file mode 100644 index 000000000..d2887b0d2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/.cproject @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/.project b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/.project new file mode 100644 index 000000000..f9c3b6151 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/.project @@ -0,0 +1,76 @@ + + + RTOSDemo_bsp + Created by SDK v2014.2 + + ZC702_hw_platform + + + + org.eclipse.cdt.make.core.makeBuilder + + + org.eclipse.cdt.core.errorOutputParser + org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.MakeErrorParser; + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.build.arguments + + + + org.eclipse.cdt.make.core.build.command + make + + + org.eclipse.cdt.make.core.build.target.auto + all + + + org.eclipse.cdt.make.core.build.target.clean + clean + + + org.eclipse.cdt.make.core.build.target.inc + all + + + org.eclipse.cdt.make.core.enableAutoBuild + true + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.enabledIncrementalBuild + true + + + org.eclipse.cdt.make.core.environment + + + + org.eclipse.cdt.make.core.stopOnError + false + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + + com.xilinx.sdk.sw.SwProjectNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.make.core.makeNature + + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/.sdkproject b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/.sdkproject new file mode 100644 index 000000000..3135ec9f7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/.sdkproject @@ -0,0 +1,3 @@ +THIRPARTY=false +PROCESSOR=ps7_cortexa9_0 +MSS_FILE=system.mss diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/Makefile new file mode 100644 index 000000000..5c6f766b3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/Makefile @@ -0,0 +1,31 @@ +# Makefile generated by Xilinx. + +PROCESSOR = ps7_cortexa9_0 +LIBRARIES = ${PROCESSOR}/lib/libxil.a +BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile) +SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES)) + +ifneq (,$(findstring win,$(RDI_PLATFORM))) + SHELL = CMD +endif + +all: libs + @echo 'Finished building libraries' + +include: $(addsuffix /make.include,$(SUBDIRS)) + +libs: $(addsuffix /make.libs,$(SUBDIRS)) + +$(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a + cp -f $< $@ + +%/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,) + @echo "Running Make include in $(subst /make.include,,$@)" + $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=arm-xilinx-eabi-gcc" "ARCHIVER=arm-xilinx-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g" + +%/make.libs: include + @echo "Running Make libs in $(subst /make.libs,,$@)" + $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=arm-xilinx-eabi-gcc" "ARCHIVER=arm-xilinx-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g" + +clean: + rm -f ${PROCESSOR}/lib/libxil.a diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/_profile_timer_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/_profile_timer_hw.h new file mode 100644 index 000000000..19499f7c5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/_profile_timer_hw.h @@ -0,0 +1,292 @@ +////////////////////////////////////////////////////////////////////// +// +// Copyright (c) 2004-11 Xilinx, Inc. All rights reserved. +// Xilinx, Inc. +// +// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR +// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION +// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE +// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO +// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY +// AND FITNESS FOR A PARTICULAR PURPOSE. +// +// $Id: _profile_timer_hw.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $ +// +// _program_timer_hw.h: +// Timer related functions +// +////////////////////////////////////////////////////////////////////// + +#ifndef _PROFILE_TIMER_HW_H +#define _PROFILE_TIMER_HW_H + +#include "profile.h" + +#ifdef PROC_PPC +#if defined __GNUC__ +# define SYNCHRONIZE_IO __asm__ volatile ("eieio") +#elif defined __DCC__ +# define SYNCHRONIZE_IO __asm volatile(" eieio") +#else +# define SYNCHRONIZE_IO +#endif +#endif + +#ifdef PROC_PPC +#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; +#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; } +#else +#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr)); +#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); } +#endif + +#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\ + ProfIo_Out32(((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + \ + (RegOffset)), (ValueToWrite)) + +#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset) \ + ProfIo_In32((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + (RegOffset)) + +#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\ + ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \ + (RegisterValue)) + +#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber) \ + ProfTimerCtr_mReadReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET) + + + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef PROC_PPC +#include "xexception_l.h" +#include "xtime_l.h" +#include "xpseudo_asm.h" +#endif + +#ifdef TIMER_CONNECT_INTC +#include "xintc_l.h" +#include "xintc.h" +#endif // TIMER_CONNECT_INTC + +#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9) +#include "xtmrctr_l.h" +#endif + +#ifdef PROC_CORTEXA9 +#include "xscutimer_hw.h" +#include "xscugic.h" +#endif + +extern unsigned int timer_clk_ticks ; + +//-------------------------------------------------------------------- +// PowerPC Target - Timer related functions +//-------------------------------------------------------------------- +#ifdef PROC_PPC + +#ifdef PPC_PIT_INTERRUPT +unsigned long timer_lo_clk_ticks ; // Clk ticks when Timer is disabled in CG +#endif + +#ifdef PROC_PPC440 +#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE +#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS +#define XREG_SPR_PIT XREG_SPR_DEC +#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT +#endif + +//-------------------------------------------------------------------- +// Disable the Timer - During Profiling +// +// For PIT Timer - +// 1. XTime_PITDisableInterrupt() ; +// 2. Store the remaining timer clk tick +// 3. Stop the PIT Timer +//-------------------------------------------------------------------- + +#ifdef PPC_PIT_INTERRUPT +#define disable_timer() \ + { \ + unsigned long val; \ + val=mfspr(XREG_SPR_TCR); \ + mtspr(XREG_SPR_TCR, val & ~XREG_TCR_PIT_INTERRUPT_ENABLE); \ + timer_lo_clk_ticks = mfspr(XREG_SPR_PIT); \ + mtspr(XREG_SPR_PIT, 0); \ + } +#else +#define disable_timer() \ + { \ + u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \ + u32 tmp_v = ProfIo_In32(addr); \ + tmp_v = tmp_v & ~XTC_CSR_ENABLE_TMR_MASK; \ + ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \ + } +#endif + + + +//-------------------------------------------------------------------- +// Enable the Timer +// +// For PIT Timer - +// 1. Load the remaining timer clk ticks +// 2. XTime_PITEnableInterrupt() ; +//-------------------------------------------------------------------- +#ifdef PPC_PIT_INTERRUPT +#define enable_timer() \ + { \ + unsigned long val; \ + val=mfspr(XREG_SPR_TCR); \ + mtspr(XREG_SPR_PIT, timer_lo_clk_ticks); \ + mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \ + } +#else +#define enable_timer() \ + { \ + u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \ + u32 tmp_v = ProfIo_In32(addr); \ + tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \ + ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \ + } +#endif + + + +//-------------------------------------------------------------------- +// Send Ack to Timer Interrupt +// +// For PIT Timer - +// 1. Load the timer clk ticks +// 2. Enable AutoReload and Interrupt +// 3. Clear PIT Timer Status bits +//-------------------------------------------------------------------- +#ifdef PPC_PIT_INTERRUPT +#define timer_ack() \ + { \ + unsigned long val; \ + mtspr(XREG_SPR_PIT, timer_clk_ticks); \ + mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS); \ + val=mfspr(XREG_SPR_TCR); \ + mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \ + } +#else +#define timer_ack() \ + { \ + unsigned int csr; \ + csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \ + ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \ + } +#endif + +//-------------------------------------------------------------------- +#endif // PROC_PPC +//-------------------------------------------------------------------- + + + + +//-------------------------------------------------------------------- +// MicroBlaze Target - Timer related functions +//-------------------------------------------------------------------- +#ifdef PROC_MICROBLAZE + +//-------------------------------------------------------------------- +// Disable the Timer during Call-Graph Data collection +// +//-------------------------------------------------------------------- +#define disable_timer() \ + { \ + u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \ + u32 tmp_v = ProfIo_In32(addr); \ + tmp_v = tmp_v & ~XTC_CSR_ENABLE_TMR_MASK; \ + ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \ + } + + +//-------------------------------------------------------------------- +// Enable the Timer after Call-Graph Data collection +// +//-------------------------------------------------------------------- +#define enable_timer() \ + { \ + u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \ + u32 tmp_v = ProfIo_In32(addr); \ + tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \ + ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \ + } + + +//-------------------------------------------------------------------- +// Send Ack to Timer Interrupt +// +//-------------------------------------------------------------------- +#define timer_ack() \ + { \ + unsigned int csr; \ + csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \ + ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \ + } + +//-------------------------------------------------------------------- +#endif // PROC_MICROBLAZE +//-------------------------------------------------------------------- + +//-------------------------------------------------------------------- +// Cortex A9 Target - Timer related functions +//-------------------------------------------------------------------- +#ifdef PROC_CORTEXA9 + +//-------------------------------------------------------------------- +// Disable the Timer during Call-Graph Data collection +// +//-------------------------------------------------------------------- +#define disable_timer() \ +{ \ + u32 Reg; \ + Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \ + Reg &= ~XSCUTIMER_CONTROL_ENABLE_MASK;\ + Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\ +} \ + + +//-------------------------------------------------------------------- +// Enable the Timer after Call-Graph Data collection +// +//-------------------------------------------------------------------- +#define enable_timer() \ +{ \ + u32 Reg; \ + Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \ + Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \ + Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\ +} \ + + +//-------------------------------------------------------------------- +// Send Ack to Timer Interrupt +// +//-------------------------------------------------------------------- +#define timer_ack() \ +{ \ + Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_ISR_OFFSET, \ + XSCUTIMER_ISR_EVENT_FLAG_MASK);\ +} + +//-------------------------------------------------------------------- +#endif // PROC_CORTEXA9 +//-------------------------------------------------------------------- + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/bspconfig.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/bspconfig.h new file mode 100644 index 000000000..efc25d1ea --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/bspconfig.h @@ -0,0 +1,16 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSM. +* Version: +* DO NOT EDIT. +* +* v (64-bit) +SW Build (by ) on +Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. +* +* Description: Configurations for Standalone BSP +* +*******************************************************************/ + +#define MICROBLAZE_PVR_NONE diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/mblaze_nt_types.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/mblaze_nt_types.h new file mode 100644 index 000000000..b008b7f55 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/mblaze_nt_types.h @@ -0,0 +1,42 @@ +////////////////////////////////////////////////////////////////////// +// +// Copyright (c) 2002-11 Xilinx, Inc. All rights reserved. +// Xilinx, Inc. +// +// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR +// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION +// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE +// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO +// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY +// AND FITNESS FOR A PARTICULAR PURPOSE. +// +// $Id: mblaze_nt_types.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $ +// +////////////////////////////////////////////////////////////////////// + +#ifndef _MBLAZE_NT_TYPES_H +#define _MBLAZE_NT_TYPES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef char byte; +typedef short half; +typedef int word; +typedef unsigned char ubyte; +typedef unsigned short uhalf; +typedef unsigned int uword; +typedef ubyte boolean; + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/profile.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/profile.h new file mode 100644 index 000000000..6f95903d3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/profile.h @@ -0,0 +1,130 @@ +////////////////////////////////////////////////////////////////////// +// +// Copyright (c) 2002-11 Xilinx, Inc. All rights reserved. +// Xilinx, Inc. +// +// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR +// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION +// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE +// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO +// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE +// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY +// AND FITNESS FOR A PARTICULAR PURPOSE. +// +// $Id: profile.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $ +// +////////////////////////////////////////////////////////////////////// + +#ifndef _PROFILE_H +#define _PROFILE_H 1 + +#include +#include "profile_config.h" + +#ifdef PROC_MICROBLAZE +#include "mblaze_nt_types.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +void _system_init( void ) ; +void _system_clean( void ) ; +void mcount(unsigned long frompc, unsigned long selfpc); +void profile_intr_handler( void ) ; + + + +/**************************************************************************** + * Profiling on hardware - Hash table maintained on hardware and data sent + * to xmd for gmon.out generation. + ****************************************************************************/ +/* + * histogram counters are unsigned shorts (according to the kernel). + */ +#define HISTCOUNTER unsigned short + +struct tostruct { + unsigned long selfpc; + long count; + short link; + unsigned short pad; +}; + +struct fromstruct { + unsigned long frompc ; + short link ; + unsigned short pad ; +} ; + +/* + * general rounding functions. + */ +#define ROUNDDOWN(x,y) (((x)/(y))*(y)) +#define ROUNDUP(x,y) ((((x)+(y)-1)/(y))*(y)) + +/* + * The profiling data structures are housed in this structure. + */ +struct gmonparam { + long int state; + + // Histogram Information + unsigned short *kcount; /* No. of bins in histogram */ + unsigned long kcountsize; /* Histogram samples */ + + // Call-graph Information + struct fromstruct *froms; + unsigned long fromssize; + struct tostruct *tos; + unsigned long tossize; + + // Initialization I/Ps + unsigned long lowpc; + unsigned long highpc; + unsigned long textsize; + //unsigned long cg_froms; + //unsigned long cg_tos; +}; +extern struct gmonparam *_gmonparam; +extern int n_gmon_sections; + +/* + * Possible states of profiling. + */ +#define GMON_PROF_ON 0 +#define GMON_PROF_BUSY 1 +#define GMON_PROF_ERROR 2 +#define GMON_PROF_OFF 3 + +/* + * Sysctl definitions for extracting profiling information from the kernel. + */ +#define GPROF_STATE 0 /* int: profiling enabling variable */ +#define GPROF_COUNT 1 /* struct: profile tick count buffer */ +#define GPROF_FROMS 2 /* struct: from location hash bucket */ +#define GPROF_TOS 3 /* struct: destination/count structure */ +#define GPROF_GMONPARAM 4 /* struct: profiling parameters (see above) */ + +#ifdef __cplusplus +} +#endif + +#endif /* _PROFILE_H */ + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/sleep.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/sleep.h new file mode 100644 index 000000000..4d9dd5abd --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/sleep.h @@ -0,0 +1,58 @@ +/****************************************************************************** +* +* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ + +#ifndef SLEEP_H +#define SLEEP_H + +#ifdef __cplusplus +extern "C" { +#endif + +void nanosleep(unsigned int nanoseconds); +int usleep(unsigned int useconds); +int sleep(unsigned int seconds); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/smc.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/smc.h new file mode 100644 index 000000000..fcfccebaa --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/smc.h @@ -0,0 +1,124 @@ +/****************************************************************************** +* +* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file smc.h +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  11/03/09 Initial release.
+*
+* +* @note None. +* +******************************************************************************/ + +#ifndef SMC_H /* prevent circular inclusions */ +#define SMC_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xparameters.h" +#include "xil_io.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/* Memory controller configuration register offset */ +#define XSMCPSS_MC_STATUS 0x000 /* Controller status reg, RO */ +#define XSMCPSS_MC_INTERFACE_CONFIG 0x004 /* Interface config reg, RO */ +#define XSMCPSS_MC_SET_CONFIG 0x008 /* Set configuration reg, WO */ +#define XSMCPSS_MC_CLR_CONFIG 0x00C /* Clear config reg, WO */ +#define XSMCPSS_MC_DIRECT_CMD 0x010 /* Direct command reg, WO */ +#define XSMCPSS_MC_SET_CYCLES 0x014 /* Set cycles register, WO */ +#define XSMCPSS_MC_SET_OPMODE 0x018 /* Set opmode register, WO */ +#define XSMCPSS_MC_REFRESH_PERIOD_0 0x020 /* Refresh period_0 reg, RW */ +#define XSMCPSS_MC_REFRESH_PERIOD_1 0x024 /* Refresh period_1 reg, RW */ + +/* Chip select configuration register offset */ +#define XSMCPSS_CS_IF0_CHIP_0_OFFSET 0x100 /* Interface 0 chip 0 config */ +#define XSMCPSS_CS_IF0_CHIP_1_OFFSET 0x120 /* Interface 0 chip 1 config */ +#define XSMCPSS_CS_IF0_CHIP_2_OFFSET 0x140 /* Interface 0 chip 2 config */ +#define XSMCPSS_CS_IF0_CHIP_3_OFFSET 0x160 /* Interface 0 chip 3 config */ +#define XSMCPSS_CS_IF1_CHIP_0_OFFSET 0x180 /* Interface 1 chip 0 config */ +#define XSMCPSS_CS_IF1_CHIP_1_OFFSET 0x1A0 /* Interface 1 chip 1 config */ +#define XSMCPSS_CS_IF1_CHIP_2_OFFSET 0x1C0 /* Interface 1 chip 2 config */ +#define XSMCPSS_CS_IF1_CHIP_3_OFFSET 0x1E0 /* Interface 1 chip 3 config */ + +/* User configuration register offset */ +#define XSMCPSS_UC_STATUS_OFFSET 0x200 /* User status reg, RO */ +#define XSMCPSS_UC_CONFIG_OFFSET 0x204 /* User config reg, WO */ + +/* Integration test register offset */ +#define XSMCPSS_IT_OFFSET 0xE00 + +/* ID configuration register offset */ +#define XSMCPSS_ID_PERIP_0_OFFSET 0xFE0 +#define XSMCPSS_ID_PERIP_1_OFFSET 0xFE4 +#define XSMCPSS_ID_PERIP_2_OFFSET 0xFE8 +#define XSMCPSS_ID_PERIP_3_OFFSET 0xFEC +#define XSMCPSS_ID_PCELL_0_OFFSET 0xFF0 +#define XSMCPSS_ID_PCELL_1_OFFSET 0xFF4 +#define XSMCPSS_ID_PCELL_2_OFFSET 0xFF8 +#define XSMCPSS_ID_PCELL_3_OFFSET 0xFFC + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +void XSmc_SramInit (void); +void XSmc_NorInit(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* SMC_H */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/vectors.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/vectors.h new file mode 100644 index 000000000..1b094cd17 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/vectors.h @@ -0,0 +1,90 @@ +/****************************************************************************** +* +* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file vectors.h +* +* This file contains the C level vector prototypes for the ARM Cortex A9 core. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm  10/20/10 Initial version, moved over from bsp area
+*
+* +* @note +* +* None. +* +******************************************************************************/ + +#ifndef _VECTORS_H_ +#define _VECTORS_H_ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/************************** Function Prototypes ******************************/ +void FIQInterrupt(void); +void IRQInterrupt(void); +void SWInterrupt(void); +void DataAbortInterrupt(void); +void PrefetchAbortInterrupt(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xadcps.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xadcps.h new file mode 100644 index 000000000..7306f8d94 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xadcps.h @@ -0,0 +1,568 @@ +/****************************************************************************** +* +* (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xadcps.h +* +* The XAdcPs driver supports the Xilinx XADC/ADC device. +* +* The XADC/ADC device has the following features: +* - 10-bit, 200-KSPS (kilo samples per second) +* Analog-to-Digital Converter (ADC) +* - Monitoring of on-chip supply voltages and temperature +* - 1 dedicated differential analog-input pair and +* 16 auxiliary differential analog-input pairs +* - Automatic alarms based on user defined limits for the on-chip +* supply voltages and temperature +* - Automatic Channel Sequencer, programmable averaging, programmable +* acquisition time for the external inputs, unipolar or differential +* input selection for the external inputs +* - Inbuilt Calibration +* - Optional interrupt request generation +* +* +* The user should refer to the hardware device specification for detailed +* information about the device. +* +* This header file contains the prototypes of driver functions that can +* be used to access the XADC/ADC device. +* +* +* XADC Channel Sequencer Modes +* +* The XADC Channel Sequencer supports the following operating modes: +* +* - Default : This is the default mode after power up. +* In this mode of operation the XADC operates in +* a sequence mode, monitoring the on chip sensors: +* Temperature, VCCINT, and VCCAUX. +* - One pass through sequence : In this mode the XADC +* converts the channels enabled in the Sequencer Channel Enable +* registers for a single pass and then stops. +* - Continuous cycling of sequence : In this mode the XADC +* converts the channels enabled in the Sequencer Channel Enable +* registers continuously. +* - Single channel mode: In this mode the XADC Channel +* Sequencer is disabled and the XADC operates in a +* Single Channel Mode. +* The XADC can operate either in a Continuous or Event +* driven sampling mode in the single channel mode. +* - Simultaneous Sampling Mode: In this mode the XADC Channel +* Sequencer will automatically sequence through eight fixed pairs +* of auxiliary analog input channels for simulataneous conversion. +* - Independent ADC mode: In this mode the first ADC (A) is used to +* is used to implement a fixed monitoring mode similar to the +* default mode but the alarm fucntions ar eenabled. +* The second ADC (B) is available to be used with external analog +* input channels only. +* +* Read the XADC spec for more information about the sequencer modes. +* +* Initialization and Configuration +* +* The device driver enables higher layer software (e.g., an application) to +* communicate to the XADC/ADC device. +* +* XAdcPs_CfgInitialize() API is used to initialize the XADC/ADC +* device. The user needs to first call the XAdcPs_LookupConfig() API which +* returns the Configuration structure pointer which is passed as a parameter to +* the XAdcPs_CfgInitialize() API. +* +* +* Interrupts +* +* The XADC/ADC device supports interrupt driven mode and the default +* operation mode is polling mode. +* +* The interrupt mode is available only if hardware is configured to support +* interrupts. +* +* This driver does not provide a Interrupt Service Routine (ISR) for the device. +* It is the responsibility of the application to provide one if needed. Refer to +* the interrupt example provided with this driver for details on using the +* device in interrupt mode. +* +* +* Virtual Memory +* +* This driver supports Virtual Memory. The RTOS is responsible for calculating +* the correct device base address in Virtual Memory space. +* +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* +* Building the driver +* +* The XAdcPs driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +* +* Limitations of the driver +* +* XADC/ADC device can be accessed through the JTAG port and the PLB +* interface. The driver implementation does not support the simultaneous access +* of the device by both these interfaces. The user has to care of this situation +* in the user application code. +* +*

+* +* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a ssb    12/22/11 First release based on the XPS/AXI xadc driver
+* 1.01a bss    02/18/13	Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
+*			XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
+*			in xadcps.c to fix CR #693371
+* 1.03a bss    11/01/13 Modified xadcps_hw.h to use correct Register offsets
+*			CR#749687
+*
+* +*****************************************************************************/ +#ifndef XADCPS_H /* Prevent circular inclusions */ +#define XADCPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xadcps_hw.h" + +/************************** Constant Definitions ****************************/ + + +/** + * @name Indexes for the different channels. + * @{ + */ +#define XADCPS_CH_TEMP 0x0 /**< On Chip Temperature */ +#define XADCPS_CH_VCCINT 0x1 /**< VCCINT */ +#define XADCPS_CH_VCCAUX 0x2 /**< VCCAUX */ +#define XADCPS_CH_VPVN 0x3 /**< VP/VN Dedicated analog inputs */ +#define XADCPS_CH_VREFP 0x4 /**< VREFP */ +#define XADCPS_CH_VREFN 0x5 /**< VREFN */ +#define XADCPS_CH_VBRAM 0x6 /**< On-chip VBRAM Data Reg, 7 series */ +#define XADCPS_CH_SUPPLY_CALIB 0x07 /**< Supply Calib Data Reg */ +#define XADCPS_CH_ADC_CALIB 0x08 /**< ADC Offset Channel Reg */ +#define XADCPS_CH_GAINERR_CALIB 0x09 /**< Gain Error Channel Reg */ +#define XADCPS_CH_VCCPINT 0x0D /**< On-chip PS VCCPINT Channel , Zynq */ +#define XADCPS_CH_VCCPAUX 0x0E /**< On-chip PS VCCPAUX Channel , Zynq */ +#define XADCPS_CH_VCCPDRO 0x0F /**< On-chip PS VCCPDRO Channel , Zynq */ +#define XADCPS_CH_AUX_MIN 16 /**< Channel number for 1st Aux Channel */ +#define XADCPS_CH_AUX_MAX 31 /**< Channel number for Last Aux channel */ + +/*@}*/ + + +/** + * @name Indexes for reading the Calibration Coefficient Data. + * @{ + */ +#define XADCPS_CALIB_SUPPLY_COEFF 0 /**< Supply Offset Calib Coefficient */ +#define XADCPS_CALIB_ADC_COEFF 1 /**< ADC Offset Calib Coefficient */ +#define XADCPS_CALIB_GAIN_ERROR_COEFF 2 /**< Gain Error Calib Coefficient*/ +/*@}*/ + + +/** + * @name Indexes for reading the Minimum/Maximum Measurement Data. + * @{ + */ +#define XADCPS_MAX_TEMP 0 /**< Maximum Temperature Data */ +#define XADCPS_MAX_VCCINT 1 /**< Maximum VCCINT Data */ +#define XADCPS_MAX_VCCAUX 2 /**< Maximum VCCAUX Data */ +#define XADCPS_MAX_VBRAM 3 /**< Maximum VBRAM Data */ +#define XADCPS_MIN_TEMP 4 /**< Minimum Temperature Data */ +#define XADCPS_MIN_VCCINT 5 /**< Minimum VCCINT Data */ +#define XADCPS_MIN_VCCAUX 6 /**< Minimum VCCAUX Data */ +#define XADCPS_MIN_VBRAM 7 /**< Minimum VBRAM Data */ +#define XADCPS_MAX_VCCPINT 8 /**< Maximum VCCPINT Register , Zynq */ +#define XADCPS_MAX_VCCPAUX 9 /**< Maximum VCCPAUX Register , Zynq */ +#define XADCPS_MAX_VCCPDRO 0xA /**< Maximum VCCPDRO Register , Zynq */ +#define XADCPS_MIN_VCCPINT 0xC /**< Minimum VCCPINT Register , Zynq */ +#define XADCPS_MIN_VCCPAUX 0xD /**< Minimum VCCPAUX Register , Zynq */ +#define XADCPS_MIN_VCCPDRO 0xE /**< Minimum VCCPDRO Register , Zynq */ + +/*@}*/ + + +/** + * @name Alarm Threshold(Limit) Register (ATR) indexes. + * @{ + */ +#define XADCPS_ATR_TEMP_UPPER 0 /**< High user Temperature */ +#define XADCPS_ATR_VCCINT_UPPER 1 /**< VCCINT high voltage limit register */ +#define XADCPS_ATR_VCCAUX_UPPER 2 /**< VCCAUX high voltage limit register */ +#define XADCPS_ATR_OT_UPPER 3 /**< VCCAUX high voltage limit register */ +#define XADCPS_ATR_TEMP_LOWER 4 /**< Upper Over Temperature limit Reg */ +#define XADCPS_ATR_VCCINT_LOWER 5 /**< VCCINT high voltage limit register */ +#define XADCPS_ATR_VCCAUX_LOWER 6 /**< VCCAUX low voltage limit register */ +#define XADCPS_ATR_OT_LOWER 7 /**< Lower Over Temperature limit */ +#define XADCPS_ATR_VBRAM_UPPER_ 8 /**< VRBAM Upper Alarm Reg, 7 Series */ +#define XADCPS_ATR_VCCPINT_UPPER 9 /**< VCCPINT Upper Alarm Reg, Zynq */ +#define XADCPS_ATR_VCCPAUX_UPPER 0xA /**< VCCPAUX Upper Alarm Reg, Zynq */ +#define XADCPS_ATR_VCCPDRO_UPPER 0xB /**< VCCPDRO Upper Alarm Reg, Zynq */ +#define XADCPS_ATR_VBRAM_LOWER 0xC /**< VRBAM Lower Alarm Reg, 7 Series */ +#define XADCPS_ATR_VCCPINT_LOWER 0xD /**< VCCPINT Lower Alarm Reg , Zynq */ +#define XADCPS_ATR_VCCPAUX_LOWER 0xE /**< VCCPAUX Lower Alarm Reg , Zynq */ +#define XADCPS_ATR_VCCPDRO_LOWER 0xF /**< VCCPDRO Lower Alarm Reg , Zynq */ + +/*@}*/ + + +/** + * @name Averaging to be done for the channels. + * @{ + */ +#define XADCPS_AVG_0_SAMPLES 0 /**< No Averaging */ +#define XADCPS_AVG_16_SAMPLES 1 /**< Average 16 samples */ +#define XADCPS_AVG_64_SAMPLES 2 /**< Average 64 samples */ +#define XADCPS_AVG_256_SAMPLES 3 /**< Average 256 samples */ + +/*@}*/ + + +/** + * @name Channel Sequencer Modes of operation + * @{ + */ +#define XADCPS_SEQ_MODE_SAFE 0 /**< Default Safe Mode */ +#define XADCPS_SEQ_MODE_ONEPASS 1 /**< Onepass through Sequencer */ +#define XADCPS_SEQ_MODE_CONTINPASS 2 /**< Continuous Cycling Sequencer */ +#define XADCPS_SEQ_MODE_SINGCHAN 3 /**< Single channel -No Sequencing */ +#define XADCPS_SEQ_MODE_SIMUL_SAMPLING 4 /**< Simultaneous sampling */ +#define XADCPS_SEQ_MODE_INDEPENDENT 8 /**< Independent mode */ + +/*@}*/ + + + +/** + * @name Power Down Modes + * @{ + */ +#define XADCPS_PD_MODE_NONE 0 /**< No Power Down */ +#define XADCPS_PD_MODE_ADCB 1 /**< Power Down ADC B */ +#define XADCPS_PD_MODE_XADC 2 /**< Power Down ADC A and ADC B */ +/*@}*/ + +/**************************** Type Definitions ******************************/ + +/** + * This typedef contains configuration information for the XADC/ADC + * device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Device base address */ +} XAdcPs_Config; + + +/** + * The driver's instance data. The user is required to allocate a variable + * of this type for every XADC/ADC device in the system. A pointer to + * a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XAdcPs_Config Config; /**< XAdcPs_Config of current device */ + u32 IsReady; /**< Device is initialized and ready */ + +} XAdcPs; + +/***************** Macros (Inline Functions) Definitions ********************/ + +/****************************************************************************/ +/** +* +* This macro checks if the XADC device is in Event Sampling mode. +* +* @param InstancePtr is a pointer to the XAdcPs instance. +* +* @return +* - TRUE if the device is in Event Sampling Mode. +* - FALSE if the device is in Continuous Sampling Mode. +* +* @note C-Style signature: +* int XAdcPs_IsEventSamplingMode(XAdcPs *InstancePtr); +* +*****************************************************************************/ +#define XAdcPs_IsEventSamplingModeSet(InstancePtr) \ + (((XAdcPs_ReadInternalReg(InstancePtr, \ + XADCPS_CFR0_OFFSET) & XADCPS_CFR0_EC_MASK) ? \ + TRUE : FALSE)) + + +/****************************************************************************/ +/** +* +* This macro checks if the XADC device is in External Mux mode. +* +* @param InstancePtr is a pointer to the XAdcPs instance. +* +* @return +* - TRUE if the device is in External Mux Mode. +* - FALSE if the device is NOT in External Mux Mode. +* +* @note C-Style signature: +* int XAdcPs_IsExternalMuxMode(XAdcPs *InstancePtr); +* +*****************************************************************************/ +#define XAdcPs_IsExternalMuxModeSet(InstancePtr) \ + (((XAdcPs_ReadInternalReg(InstancePtr, \ + XADCPS_CFR0_OFFSET) & XADCPS_CFR0_MUX_MASK) ? \ + TRUE : FALSE)) + +/****************************************************************************/ +/** +* +* This macro converts XADC Raw Data to Temperature(centigrades). +* +* @param AdcData is the Raw ADC Data from XADC. +* +* @return The Temperature in centigrades. +* +* @note C-Style signature: +* float XAdcPs_RawToTemperature(u32 AdcData); +* +*****************************************************************************/ +#define XAdcPs_RawToTemperature(AdcData) \ + ((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f) + +/****************************************************************************/ +/** +* +* This macro converts XADC/ADC Raw Data to Voltage(volts). +* +* @param AdcData is the XADC/ADC Raw Data. +* +* @return The Voltage in volts. +* +* @note C-Style signature: +* float XAdcPs_RawToVoltage(u32 AdcData); +* +*****************************************************************************/ +#define XAdcPs_RawToVoltage(AdcData) \ + ((((float)(AdcData))* (3.0f))/65536.0f) + +/****************************************************************************/ +/** +* +* This macro converts Temperature in centigrades to XADC/ADC Raw Data. +* +* @param Temperature is the Temperature in centigrades to be +* converted to XADC/ADC Raw Data. +* +* @return The XADC/ADC Raw Data. +* +* @note C-Style signature: +* int XAdcPs_TemperatureToRaw(float Temperature); +* +*****************************************************************************/ +#define XAdcPs_TemperatureToRaw(Temperature) \ + ((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f)) + +/****************************************************************************/ +/** +* +* This macro converts Voltage in Volts to XADC/ADC Raw Data. +* +* @param Voltage is the Voltage in volts to be converted to +* XADC/ADC Raw Data. +* +* @return The XADC/ADC Raw Data. +* +* @note C-Style signature: +* int XAdcPs_VoltageToRaw(float Voltage); +* +*****************************************************************************/ +#define XAdcPs_VoltageToRaw(Voltage) \ + ((int)((Voltage)*65536.0f/3.0f)) + + +/****************************************************************************/ +/** +* +* This macro is used for writing to the XADC Registers using the +* command FIFO. +* +* @param InstancePtr is a pointer to the XAdcPs instance. +* +* @return None. +* +* @note C-Style signature: +* void XAdcPs_WriteFifo(XAdcPs *InstancePtr, u32 Data); +* +*****************************************************************************/ +#define XAdcPs_WriteFifo(InstancePtr, Data) \ + XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XADCPS_CMDFIFO_OFFSET, Data); + + +/****************************************************************************/ +/** +* +* This macro is used for reading from the XADC Registers using the +* data FIFO. +* +* @param InstancePtr is a pointer to the XAdcPs instance. +* +* @return Data read from the FIFO +* +* @note C-Style signature: +* u32 XAdcPs_ReadFifo(XAdcPs *InstancePtr); +* +*****************************************************************************/ +#define XAdcPs_ReadFifo(InstancePtr) \ + XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XADCPS_RDFIFO_OFFSET); + + +/************************** Function Prototypes *****************************/ + + + +/** + * Functions in xadcps_sinit.c + */ +XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId); + +/** + * Functions in xadcps.c + */ +int XAdcPs_CfgInitialize(XAdcPs *InstancePtr, + XAdcPs_Config *ConfigPtr, + u32 EffectiveAddr); + + +u32 XAdcPs_GetStatus(XAdcPs *InstancePtr); + +u32 XAdcPs_GetAlarmOutputStatus(XAdcPs *InstancePtr); + +void XAdcPs_StartAdcConversion(XAdcPs *InstancePtr); + +void XAdcPs_Reset(XAdcPs *InstancePtr); + +u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel); + +u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType); + +u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType); + +void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average); +u8 XAdcPs_GetAvg(XAdcPs *InstancePtr); + +int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr, + u8 Channel, + int IncreaseAcqCycles, + int IsEventMode, + int IsDifferentialMode); + + +void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask); +u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr); + +void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration); +u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr); + +void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode); +u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr); + +void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor); +u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr); + +int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask); +u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr); + +int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask); +u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr); + +int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask); +u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr); + +int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask); +u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr); + +void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value); +u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg); + +void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr); +void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr); + +/** + * Functions in xadcps_selftest.c + */ +int XAdcPs_SelfTest(XAdcPs *InstancePtr); + +/** + * Functions in xadcps_intr.c + */ +void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask); +void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask); +u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr); + +u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr); +void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask); + + +#ifdef __cplusplus +} +#endif + +#endif /* End of protection macro. */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xadcps_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xadcps_hw.h new file mode 100644 index 000000000..101dcb7d7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xadcps_hw.h @@ -0,0 +1,508 @@ +/****************************************************************************** +* +* (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xadcps_hw.h +* +* This header file contains identifiers and basic driver functions (or +* macros) that can be used to access the XADC device through the Device +* Config Interface of the Zynq. +* +* +* Refer to the device specification for more information about this driver. +* +* @note None. +* +* +* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a bss    12/22/11 First release based on the XPS/AXI xadc driver
+* 1.03a bss    11/01/13 Modified macros to use correct Register offsets
+*			CR#749687
+*
+*
+* +*****************************************************************************/ +#ifndef XADCPS_HW_H /* Prevent circular inclusions */ +#define XADCPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions ****************************/ + + +/**@name Register offsets of XADC in the Device Config + * + * The following constants provide access to each of the registers of the + * XADC device. + * @{ + */ + +#define XADCPS_CFG_OFFSET 0x00 /**< Configuration Register */ +#define XADCPS_INT_STS_OFFSET 0x04 /**< Interrupt Status Register */ +#define XADCPS_INT_MASK_OFFSET 0x08 /**< Interrupt Mask Register */ +#define XADCPS_MSTS_OFFSET 0x0C /**< Misc status register */ +#define XADCPS_CMDFIFO_OFFSET 0x10 /**< Command FIFO Register */ +#define XADCPS_RDFIFO_OFFSET 0x14 /**< Read FIFO Register */ +#define XADCPS_MCTL_OFFSET 0x18 /**< Misc control register */ + +/* @} */ + + + + + +/** @name XADC Config Register Bit definitions + * @{ + */ +#define XADCPS_CFG_ENABLE_MASK 0x80000000 /**< Enable access from PS mask */ +#define XADCPS_CFG_CFIFOTH_MASK 0x00F00000 /**< Command FIFO Threshold mask */ +#define XADCPS_CFG_DFIFOTH_MASK 0x000F0000 /**< Data FIFO Threshold mask */ +#define XADCPS_CFG_WEDGE_MASK 0x00002000 /**< Write Edge Mask */ +#define XADCPS_CFG_REDGE_MASK 0x00001000 /**< Read Edge Mask */ +#define XADCPS_CFG_TCKRATE_MASK 0x00000300 /**< Clock freq control */ +#define XADCPS_CFG_IGAP_MASK 0x0000001F /**< Idle Gap between + * successive commands */ +/* @} */ + + +/** @name XADC Interrupt Status/Mask Register Bit definitions + * + * The definitions are same for the Interrupt Status Register and + * Interrupt Mask Register. They are defined only once. + * @{ + */ +#define XADCPS_INTX_ALL_MASK 0x000003FF /**< Alarm Signals Mask */ +#define XADCPS_INTX_CFIFO_LTH_MASK 0x00000200 /**< CMD FIFO less than threshold */ +#define XADCPS_INTX_DFIFO_GTH_MASK 0x00000100 /**< Data FIFO greater than threshold */ +#define XADCPS_INTX_OT_MASK 0x00000080 /**< Over temperature Alarm Status */ +#define XADCPS_INTX_ALM_ALL_MASK 0x0000007F /**< Alarm Signals Mask */ +#define XADCPS_INTX_ALM6_MASK 0x00000040 /**< Alarm 6 Mask */ +#define XADCPS_INTX_ALM5_MASK 0x00000020 /**< Alarm 5 Mask */ +#define XADCPS_INTX_ALM4_MASK 0x00000010 /**< Alarm 4 Mask */ +#define XADCPS_INTX_ALM3_MASK 0x00000008 /**< Alarm 3 Mask */ +#define XADCPS_INTX_ALM2_MASK 0x00000004 /**< Alarm 2 Mask */ +#define XADCPS_INTX_ALM1_MASK 0x00000002 /**< Alarm 1 Mask */ +#define XADCPS_INTX_ALM0_MASK 0x00000001 /**< Alarm 0 Mask */ + +/* @} */ + + +/** @name XADC Miscellaneous Register Bit definitions + * @{ + */ +#define XADCPS_MSTS_CFIFO_LVL_MASK 0x000F0000 /**< Command FIFO Level mask */ +#define XADCPS_MSTS_DFIFO_LVL_MASK 0x0000F000 /**< Data FIFO Level Mask */ +#define XADCPS_MSTS_CFIFOF_MASK 0x00000800 /**< Command FIFO Full Mask */ +#define XADCPS_MSTS_CFIFOE_MASK 0x00000400 /**< Command FIFO Empty Mask */ +#define XADCPS_MSTS_DFIFOF_MASK 0x00000200 /**< Data FIFO Full Mask */ +#define XADCPS_MSTS_DFIFOE_MASK 0x00000100 /**< Data FIFO Empty Mask */ +#define XADCPS_MSTS_OT_MASK 0x00000080 /**< Over Temperature Mask */ +#define XADCPS_MSTS_ALM_MASK 0x0000007F /**< Alarms Mask */ +/* @} */ + + +/** @name XADC Miscellaneous Control Register Bit definitions + * @{ + */ +#define XADCPS_MCTL_RESET_MASK 0x00000010 /**< Reset XADC */ +#define XADCPS_MCTL_FLUSH_MASK 0x00000001 /**< Flush the FIFOs */ +/* @} */ + + +/**@name Internal Register offsets of the XADC + * + * The following constants provide access to each of the internal registers of + * the XADC device. + * @{ + */ + +/* + * XADC Internal Channel Registers + */ +#define XADCPS_TEMP_OFFSET 0x00 /**< On-chip Temperature Reg */ +#define XADCPS_VCCINT_OFFSET 0x01 /**< On-chip VCCINT Data Reg */ +#define XADCPS_VCCAUX_OFFSET 0x02 /**< On-chip VCCAUX Data Reg */ +#define XADCPS_VPVN_OFFSET 0x03 /**< ADC out of VP/VN */ +#define XADCPS_VREFP_OFFSET 0x04 /**< On-chip VREFP Data Reg */ +#define XADCPS_VREFN_OFFSET 0x05 /**< On-chip VREFN Data Reg */ +#define XADCPS_VBRAM_OFFSET 0x06 /**< On-chip VBRAM , 7 Series */ +#define XADCPS_ADC_A_SUPPLY_CALIB_OFFSET 0x08 /**< ADC A Supply Offset Reg */ +#define XADCPS_ADC_A_OFFSET_CALIB_OFFSET 0x09 /**< ADC A Offset Data Reg */ +#define XADCPS_ADC_A_GAINERR_CALIB_OFFSET 0x0A /**< ADC A Gain Error Reg */ +#define XADCPS_VCCPINT_OFFSET 0x0D /**< On-chip VCCPINT Reg, Zynq */ +#define XADCPS_VCCPAUX_OFFSET 0x0E /**< On-chip VCCPAUX Reg, Zynq */ +#define XADCPS_VCCPDRO_OFFSET 0x0F /**< On-chip VCCPDRO Reg, Zynq */ + +/* + * XADC External Channel Registers + */ +#define XADCPS_AUX00_OFFSET 0x10 /**< ADC out of VAUXP0/VAUXN0 */ +#define XADCPS_AUX01_OFFSET 0x11 /**< ADC out of VAUXP1/VAUXN1 */ +#define XADCPS_AUX02_OFFSET 0x12 /**< ADC out of VAUXP2/VAUXN2 */ +#define XADCPS_AUX03_OFFSET 0x13 /**< ADC out of VAUXP3/VAUXN3 */ +#define XADCPS_AUX04_OFFSET 0x14 /**< ADC out of VAUXP4/VAUXN4 */ +#define XADCPS_AUX05_OFFSET 0x15 /**< ADC out of VAUXP5/VAUXN5 */ +#define XADCPS_AUX06_OFFSET 0x16 /**< ADC out of VAUXP6/VAUXN6 */ +#define XADCPS_AUX07_OFFSET 0x17 /**< ADC out of VAUXP7/VAUXN7 */ +#define XADCPS_AUX08_OFFSET 0x18 /**< ADC out of VAUXP8/VAUXN8 */ +#define XADCPS_AUX09_OFFSET 0x19 /**< ADC out of VAUXP9/VAUXN9 */ +#define XADCPS_AUX10_OFFSET 0x1A /**< ADC out of VAUXP10/VAUXN10 */ +#define XADCPS_AUX11_OFFSET 0x1B /**< ADC out of VAUXP11/VAUXN11 */ +#define XADCPS_AUX12_OFFSET 0x1C /**< ADC out of VAUXP12/VAUXN12 */ +#define XADCPS_AUX13_OFFSET 0x1D /**< ADC out of VAUXP13/VAUXN13 */ +#define XADCPS_AUX14_OFFSET 0x1E /**< ADC out of VAUXP14/VAUXN14 */ +#define XADCPS_AUX15_OFFSET 0x1F /**< ADC out of VAUXP15/VAUXN15 */ + +/* + * XADC Registers for Maximum/Minimum data captured for the + * on chip Temperature/VCCINT/VCCAUX data. + */ +#define XADCPS_MAX_TEMP_OFFSET 0x20 /**< Max Temperature Reg */ +#define XADCPS_MAX_VCCINT_OFFSET 0x21 /**< Max VCCINT Register */ +#define XADCPS_MAX_VCCAUX_OFFSET 0x22 /**< Max VCCAUX Register */ +#define XADCPS_MAX_VCCBRAM_OFFSET 0x23 /**< Max BRAM Register, 7 series */ +#define XADCPS_MIN_TEMP_OFFSET 0x24 /**< Min Temperature Reg */ +#define XADCPS_MIN_VCCINT_OFFSET 0x25 /**< Min VCCINT Register */ +#define XADCPS_MIN_VCCAUX_OFFSET 0x26 /**< Min VCCAUX Register */ +#define XADCPS_MIN_VCCBRAM_OFFSET 0x27 /**< Min BRAM Register, 7 series */ +#define XADCPS_MAX_VCCPINT_OFFSET 0x28 /**< Max VCCPINT Register, Zynq */ +#define XADCPS_MAX_VCCPAUX_OFFSET 0x29 /**< Max VCCPAUX Register, Zynq */ +#define XADCPS_MAX_VCCPDRO_OFFSET 0x2A /**< Max VCCPDRO Register, Zynq */ +#define XADCPS_MIN_VCCPINT_OFFSET 0x2C /**< Min VCCPINT Register, Zynq */ +#define XADCPS_MIN_VCCPAUX_OFFSET 0x2D /**< Min VCCPAUX Register, Zynq */ +#define XADCPS_MIN_VCCPDRO_OFFSET 0x2E /**< Min VCCPDRO Register,Zynq */ + /* Undefined 0x2F to 0x3E */ +#define XADCPS_FLAG_OFFSET 0x3F /**< Flag Register */ + +/* + * XADC Configuration Registers + */ +#define XADCPS_CFR0_OFFSET 0x40 /**< Configuration Register 0 */ +#define XADCPS_CFR1_OFFSET 0x41 /**< Configuration Register 1 */ +#define XADCPS_CFR2_OFFSET 0x42 /**< Configuration Register 2 */ + +/* Test Registers 0x43 to 0x47 */ + +/* + * XADC Sequence Registers + */ +#define XADCPS_SEQ00_OFFSET 0x48 /**< Seq Reg 00 Adc Channel Selection */ +#define XADCPS_SEQ01_OFFSET 0x49 /**< Seq Reg 01 Adc Channel Selection */ +#define XADCPS_SEQ02_OFFSET 0x4A /**< Seq Reg 02 Adc Average Enable */ +#define XADCPS_SEQ03_OFFSET 0x4B /**< Seq Reg 03 Adc Average Enable */ +#define XADCPS_SEQ04_OFFSET 0x4C /**< Seq Reg 04 Adc Input Mode Select */ +#define XADCPS_SEQ05_OFFSET 0x4D /**< Seq Reg 05 Adc Input Mode Select */ +#define XADCPS_SEQ06_OFFSET 0x4E /**< Seq Reg 06 Adc Acquisition Select */ +#define XADCPS_SEQ07_OFFSET 0x4F /**< Seq Reg 07 Adc Acquisition Select */ + +/* + * XADC Alarm Threshold/Limit Registers (ATR) + */ +#define XADCPS_ATR_TEMP_UPPER_OFFSET 0x50 /**< Temp Upper Alarm Register */ +#define XADCPS_ATR_VCCINT_UPPER_OFFSET 0x51 /**< VCCINT Upper Alarm Reg */ +#define XADCPS_ATR_VCCAUX_UPPER_OFFSET 0x52 /**< VCCAUX Upper Alarm Reg */ +#define XADCPS_ATR_OT_UPPER_OFFSET 0x53 /**< Over Temp Upper Alarm Reg */ +#define XADCPS_ATR_TEMP_LOWER_OFFSET 0x54 /**< Temp Lower Alarm Register */ +#define XADCPS_ATR_VCCINT_LOWER_OFFSET 0x55 /**< VCCINT Lower Alarm Reg */ +#define XADCPS_ATR_VCCAUX_LOWER_OFFSET 0x56 /**< VCCAUX Lower Alarm Reg */ +#define XADCPS_ATR_OT_LOWER_OFFSET 0x57 /**< Over Temp Lower Alarm Reg */ +#define XADCPS_ATR_VBRAM_UPPER_OFFSET 0x58 /**< VBRAM Upper Alarm, 7 series */ +#define XADCPS_ATR_VCCPINT_UPPER_OFFSET 0x59 /**< VCCPINT Upper Alarm, Zynq */ +#define XADCPS_ATR_VCCPAUX_UPPER_OFFSET 0x5A /**< VCCPAUX Upper Alarm, Zynq */ +#define XADCPS_ATR_VCCPDRO_UPPER_OFFSET 0x5B /**< VCCPDRO Upper Alarm, Zynq */ +#define XADCPS_ATR_VBRAM_LOWER_OFFSET 0x5C /**< VRBAM Lower Alarm, 7 Series */ +#define XADCPS_ATR_VCCPINT_LOWER_OFFSET 0x5D /**< VCCPINT Lower Alarm, Zynq */ +#define XADCPS_ATR_VCCPAUX_LOWER_OFFSET 0x5E /**< VCCPAUX Lower Alarm, Zynq */ +#define XADCPS_ATR_VCCPDRO_LOWER_OFFSET 0x5F /**< VCCPDRO Lower Alarm, Zynq */ + +/* Undefined 0x60 to 0x7F */ + +/*@}*/ + + + +/** + * @name Configuration Register 0 (CFR0) mask(s) + * @{ + */ +#define XADCPS_CFR0_CAL_AVG_MASK 0x8000 /**< Averaging enable Mask */ +#define XADCPS_CFR0_AVG_VALID_MASK 0x3000 /**< Averaging bit Mask */ +#define XADCPS_CFR0_AVG1_MASK 0x0000 /**< No Averaging */ +#define XADCPS_CFR0_AVG16_MASK 0x1000 /**< Average 16 samples */ +#define XADCPS_CFR0_AVG64_MASK 0x2000 /**< Average 64 samples */ +#define XADCPS_CFR0_AVG256_MASK 0x3000 /**< Average 256 samples */ +#define XADCPS_CFR0_AVG_SHIFT 12 /**< Averaging bits shift */ +#define XADCPS_CFR0_MUX_MASK 0x0800 /**< External Mask Enable */ +#define XADCPS_CFR0_DU_MASK 0x0400 /**< Bipolar/Unipolar mode */ +#define XADCPS_CFR0_EC_MASK 0x0200 /**< Event driven/ + * Continuous mode selection + */ +#define XADCPS_CFR0_ACQ_MASK 0x0100 /**< Add acquisition by 6 ADCCLK */ +#define XADCPS_CFR0_CHANNEL_MASK 0x001F /**< Channel number bit Mask */ + +/*@}*/ + +/** + * @name Configuration Register 1 (CFR1) mask(s) + * @{ + */ +#define XADCPS_CFR1_SEQ_VALID_MASK 0xF000 /**< Sequence bit Mask */ +#define XADCPS_CFR1_SEQ_SAFEMODE_MASK 0x0000 /**< Default Safe Mode */ +#define XADCPS_CFR1_SEQ_ONEPASS_MASK 0x1000 /**< Onepass through Seq */ +#define XADCPS_CFR1_SEQ_CONTINPASS_MASK 0x2000 /**< Continuous Cycling Seq */ +#define XADCPS_CFR1_SEQ_SINGCHAN_MASK 0x3000 /**< Single channel - No Seq */ +#define XADCPS_CFR1_SEQ_SIMUL_SAMPLING_MASK 0x4000 /**< Simulataneous Sampling Mask */ +#define XADCPS_CFR1_SEQ_INDEPENDENT_MASK 0x8000 /**< Independent Mode */ +#define XADCPS_CFR1_SEQ_SHIFT 12 /**< Sequence bit shift */ +#define XADCPS_CFR1_ALM_VCCPDRO_MASK 0x0800 /**< Alm 6 - VCCPDRO, Zynq */ +#define XADCPS_CFR1_ALM_VCCPAUX_MASK 0x0400 /**< Alm 5 - VCCPAUX, Zynq */ +#define XADCPS_CFR1_ALM_VCCPINT_MASK 0x0200 /**< Alm 4 - VCCPINT, Zynq */ +#define XADCPS_CFR1_ALM_VBRAM_MASK 0x0100 /**< Alm 3 - VBRAM, 7 series */ +#define XADCPS_CFR1_CAL_VALID_MASK 0x00F0 /**< Valid Calibration Mask */ +#define XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK 0x0080 /**< Calibration 3 -Power + Supply Gain/Offset + Enable */ +#define XADCPS_CFR1_CAL_PS_OFFSET_MASK 0x0040 /**< Calibration 2 -Power + Supply Offset Enable */ +#define XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x0020 /**< Calibration 1 -ADC Gain + Offset Enable */ +#define XADCPS_CFR1_CAL_ADC_OFFSET_MASK 0x0010 /**< Calibration 0 -ADC Offset + Enable */ +#define XADCPS_CFR1_CAL_DISABLE_MASK 0x0000 /**< No Calibration */ +#define XADCPS_CFR1_ALM_ALL_MASK 0x0F0F /**< Mask for all alarms */ +#define XADCPS_CFR1_ALM_VCCAUX_MASK 0x0008 /**< Alarm 2 - VCCAUX Enable */ +#define XADCPS_CFR1_ALM_VCCINT_MASK 0x0004 /**< Alarm 1 - VCCINT Enable */ +#define XADCPS_CFR1_ALM_TEMP_MASK 0x0002 /**< Alarm 0 - Temperature */ +#define XADCPS_CFR1_OT_MASK 0x0001 /**< Over Temperature Enable */ + +/*@}*/ + +/** + * @name Configuration Register 2 (CFR2) mask(s) + * @{ + */ +#define XADCPS_CFR2_CD_VALID_MASK 0xFF00 /** +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 1.00a adk 1/31/14 Added in bsp common folder for backward compatibility +* +* +******************************************************************************/ + +#ifndef XBASIC_TYPES_H /* prevent circular inclusions */ +#define XBASIC_TYPES_H /* by using protection macros */ + +/** @name Legacy types + * Deprecated legacy types. + * @{ + */ +typedef unsigned char Xuint8; /**< unsigned 8-bit */ +typedef char Xint8; /**< signed 8-bit */ +typedef unsigned short Xuint16; /**< unsigned 16-bit */ +typedef short Xint16; /**< signed 16-bit */ +typedef unsigned long Xuint32; /**< unsigned 32-bit */ +typedef long Xint32; /**< signed 32-bit */ +typedef float Xfloat32; /**< 32-bit floating point */ +typedef double Xfloat64; /**< 64-bit double precision FP */ +typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */ + +#if !defined __XUINT64__ +typedef struct +{ + Xuint32 Upper; + Xuint32 Lower; +} Xuint64; +#endif + +/** @name New types + * New simple types. + * @{ + */ +#ifndef __KERNEL__ +#ifndef XIL_TYPES_H +typedef Xuint32 u32; +typedef Xuint16 u16; +typedef Xuint8 u8; +#endif +#else +#include +#endif + +#ifndef TRUE +# define TRUE 1 +#endif + +#ifndef FALSE +# define FALSE 0 +#endif + +#ifndef NULL +#define NULL 0 +#endif + +/* + * Xilinx NULL, TRUE and FALSE legacy support. Deprecated. + * Please use NULL, TRUE and FALSE + */ +#define XNULL NULL +#define XTRUE TRUE +#define XFALSE FALSE + +/* + * This file is deprecated and users + * should use xil_types.h and xil_assert.h\n\r + */ +#warning The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert. +#warning Please refer the Standalone BSP UG647 for further details + + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xcanps.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xcanps.h new file mode 100644 index 000000000..162f3190a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xcanps.h @@ -0,0 +1,570 @@ +/****************************************************************************** +* +* (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcanps.h +* +* The Xilinx CAN driver component. This component supports the Xilinx +* CAN Controller. +* +* The CAN Controller supports the following features: +* - Confirms to the ISO 11898-1, CAN 2.0A and CAN 2.0B standards. +* - Supports both Standard (11 bit Identifier) and Extended (29 bit +* Identifier) frames. +* - Supports Bit Rates up to 1 Mbps. +* - Transmit message object FIFO with a user configurable depth of +* up to 64 message objects. +* - Transmit prioritization through one TX High Priority Buffer. +* - Receive message object FIFO with a user configurable depth of +* up to 64 message objects. +* - Watermark interrupts for Rx FIFO with configurable Watermark. +* - Acceptance filtering with 4 acceptance filters. +* - Sleep mode with automatic wake up. +* - Loop Back mode for diagnostic applications. +* - Snoop mode for diagnostic applications. +* - Maskable Error and Status Interrupts. +* - Readable Error Counters. +* - External PHY chip required. +* - Receive Timestamp. +* +* The device driver supports all the features listed above, if applicable. +* +* Driver Description +* +* The device driver enables higher layer software (e.g., an application) to +* communicate to the CAN. The driver handles transmission and reception of +* CAN frames, as well as configuration of the controller. The driver is simply a +* pass-through mechanism between a protocol stack and the CAN. A single device +* driver can support multiple CANs. +* +* Since the driver is a simple pass-through mechanism between a protocol stack +* and the CAN, no assembly or disassembly of CAN frames is done at the +* driver-level. This assumes that the protocol stack passes a correctly +* formatted CAN frame to the driver for transmission, and that the driver +* does not validate the contents of an incoming frame +* +* Operation Modes +* +* The CAN controller supports the following modes of operation: +* - Configuration Mode: In this mode the CAN timing parameters and +* Baud Rate Pre-scalar parameters can be changed. In this mode the CAN +* controller loses synchronization with the CAN bus and drives a +* constant recessive bit on the bus line. The Error Counter Register are +* reset. The CAN controller does not receive or transmit any messages +* even if there are pending transmit requests from the TX FIFO or the TX +* High Priority Buffer. The Storage FIFOs and the CAN configuration +* registers are still accessible. +* - Normal Mode:In Normal Mode the CAN controller participates in bus +* communication, by transmitting and receiving messages. +* - Sleep Mode: In Sleep Mode the CAN Controller does not transmit any +* messages. However, if any other node transmits a message, then the CAN +* Controller receives the transmitted message and exits from Sleep Mode. +* If there are new transmission requests from either the TX FIFO or the +* TX High Priority Buffer when the CAN Controller is in Sleep Mode, these +* requests are not serviced, and the CAN Controller continues to remain +* in Sleep Mode. Interrupts are generated when the CAN controller enters +* Sleep mode or Wakes up from Sleep mode. +* - Loop Back Mode: In Loop Back mode, the CAN controller transmits a +* recessive bit stream on to the CAN Bus. Any message that is transmitted +* is looped back to the ‘Rx’ line and acknowledged. The CAN controller +* thus receives any message that it transmits. It does not participate in +* normal bus communication and does not receive any messages that are +* transmitted by other CAN nodes. This mode is used for diagnostic +* purposes. +* - Snoop Mode: In Snoop mode, the CAN controller transmits a +* recessive bit stream on to the CAN Bus and does not participate +* in normal bus communication but receives messages that are transmitted +* by other CAN nodes. This mode is used for diagnostic purposes. +* +* +* Buffer Alignment +* +* It is important to note that frame buffers passed to the driver must be +* 32-bit aligned. +* +* Receive Address Filtering +* +* The device can be set to accept frames whose Identifiers match any of the +* 4 filters set in the Acceptance Filter Mask/ID registers. +* +* The incoming Identifier is masked with the bits in the Acceptance Filter Mask +* Register. This value is compared with the result of masking the bits in the +* Acceptance Filter ID Register with the Acceptance Filter Mask Register. If +* both these values are equal, the message will be stored in the RX FIFO. +* +* Acceptance Filtering is performed by each of the defined acceptance filters. +* If the incoming identifier passes through any acceptance filter then the +* frame is stored in the RX FIFO. +* +* If the Accpetance Filters are not set up then all the received messages are +* stroed in the RX FIFO. +* +* PHY Communication +* +* This driver does not provide any mechanism for directly programming PHY. +* +* Interrupts +* +* The driver has no dependencies on the interrupt controller. The driver +* provides an interrupt handler. User of this driver needs to provide +* callback functions. An interrupt handler example is available with +* the driver. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Device Reset +* +* Bus Off interrupt that can occur in the device requires a device reset. +* The user is responsible for resetting the device and re-configuring it +* based on its needs (the driver does not save the current configuration). +* When integrating into an RTOS, these reset and re-configure obligations are +* taken care of by the OS adapter software if it exists for that RTOS. +* +* Device Configuration +* +* The device can be configured in various ways during the FPGA implementation +* process. Configuration parameters are stored in the xcanps_g.c files. +* A table is defined where each entry contains configuration information +* for a CAN device. This information includes such things as the base address +* of the memory-mapped device. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The XCanPs driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +*

+* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+* 1.01a bss    12/27/11 Added the APIs XCanPs_SetTxIntrWatermark and
+* 			XCanPs_GetTxIntrWatermark.
+*			Updated the Register/bit definitions
+*                       Changed XCANPS_RXFWIR_RXFLL_MASK to XCANPS_WIR_FW_MASK
+*                       Changed XCANPS_RXWIR_OFFSET to XCANPS_WIR_OFFSET
+*			Added XCANPS_IXR_TXFEMP_MASK for Tx Fifo Empty
+*			Changed XCANPS_IXR_RXFLL_MASK to
+*			XCANPS_IXR_RXFWMFLL_MASK
+* 			Changed
+*			XCANPS_TXBUF_ID_OFFSET to XCANPS_TXHPB_ID_OFFSET
+* 			XCANPS_TXBUF_DLC_OFFSET to XCANPS_TXHPB_DLC_OFFSET
+*			XCANPS_TXBUF_DW1_OFFSET to XCANPS_TXHPB_DW1_OFFSET
+*			XCANPS_TXBUF_DW2_OFFSET to XCANPS_TXHPB_DW2_OFFSET
+*
+* +******************************************************************************/ +#ifndef XCANPS_H /* prevent circular inclusions */ +#define XCANPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xcanps_hw.h" + +/************************** Constant Definitions *****************************/ + +/** @name CAN operation modes + * @{ + */ +#define XCANPS_MODE_CONFIG 0x00000001 /**< Configuration mode */ +#define XCANPS_MODE_NORMAL 0x00000002 /**< Normal mode */ +#define XCANPS_MODE_LOOPBACK 0x00000004 /**< Loop Back mode */ +#define XCANPS_MODE_SLEEP 0x00000008 /**< Sleep mode */ +#define XCANPS_MODE_SNOOP 0x00000010 /**< Snoop mode */ +/* @} */ + +/** @name Callback identifiers used as parameters to XCanPs_SetHandler() + * @{ + */ +#define XCANPS_HANDLER_SEND 1 /**< Handler type for frame sending interrupt */ +#define XCANPS_HANDLER_RECV 2 /**< Handler type for frame reception interrupt*/ +#define XCANPS_HANDLER_ERROR 3 /**< Handler type for error interrupt */ +#define XCANPS_HANDLER_EVENT 4 /**< Handler type for all other interrupts */ +/* @} */ + +/**************************** Type Definitions *******************************/ + +/** + * This typedef contains configuration information for a device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddr; /**< Register base address */ +} XCanPs_Config; + +/******************************************************************************/ +/** + * Callback type for frame sending and reception interrupts. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the callback functions, and passed back to the + * upper layer when the callback is invoked. +*******************************************************************************/ +typedef void (*XCanPs_SendRecvHandler) (void *CallBackRef); + +/******************************************************************************/ +/** + * Callback type for error interrupt. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the callback functions, and passed back to the + * upper layer when the callback is invoked. + * @param ErrorMask is a bit mask indicating the cause of the error. Its + * value equals 'OR'ing one or more XCANPS_ESR_* values defined in + * xcanps_hw.h +*******************************************************************************/ +typedef void (*XCanPs_ErrorHandler) (void *CallBackRef, u32 ErrorMask); + +/******************************************************************************/ +/** + * Callback type for all kinds of interrupts except sending frame interrupt, + * receiving frame interrupt, and error interrupt. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the callback functions, and passed back to the + * upper layer when the callback is invoked. + * @param Mask is a bit mask indicating the pending interrupts. Its value + * equals 'OR'ing one or more XCANPS_IXR_* defined in xcanps_hw.h +*******************************************************************************/ +typedef void (*XCanPs_EventHandler) (void *CallBackRef, u32 Mask); + +/** + * The XCanPs driver instance data. The user is required to allocate a + * variable of this type for every CAN device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XCanPs_Config CanConfig; /**< Device configuration */ + u32 IsReady; /**< Device is initialized and ready */ + + /** + * Callback and callback reference for TXOK interrupt. + */ + XCanPs_SendRecvHandler SendHandler; + void *SendRef; + + /** + * Callback and callback reference for RXOK/RXNEMP/RXFLL interrupts. + */ + XCanPs_SendRecvHandler RecvHandler; + void *RecvRef; + + /** + * Callback and callback reference for ERROR interrupt. + */ + XCanPs_ErrorHandler ErrorHandler; + void *ErrorRef; + + /** + * Callback and callback reference for RXOFLW/RXUFLW/TXBFLL/TXFLL/ + * Wakeup/Sleep/Bus off/ARBLST interrupts. + */ + XCanPs_EventHandler EventHandler; + void *EventRef; + +} XCanPs; + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* This macro checks if the transmission is complete. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if the transmission is done. +* - FALSE if the transmission is not done. +* +* @note C-Style signature: +* int XCanPs_IsTxDone(XCanPs *InstancePtr); +* +*******************************************************************************/ +#define XCanPs_IsTxDone(InstancePtr) \ + ((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_ISR_OFFSET) & XCANPS_IXR_TXOK_MASK) ? TRUE : FALSE) + + +/****************************************************************************/ +/** +* +* This macro checks if the transmission FIFO is full. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if TX FIFO is full. +* - FALSE if the TX FIFO is NOT full. +* +* @note C-Style signature: +* int XCanPs_IsTxFifoFull(XCanPs *InstancePtr); +* +*****************************************************************************/ +#define XCanPs_IsTxFifoFull(InstancePtr) \ + ((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_SR_OFFSET) & XCANPS_SR_TXFLL_MASK) ? TRUE : FALSE) + + +/****************************************************************************/ +/** +* +* This macro checks if the Transmission High Priority Buffer is full. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if the TX High Priority Buffer is full. +* - FALSE if the TX High Priority Buffer is NOT full. +* +* @note C-Style signature: +* int XCanPs_IsHighPriorityBufFull(XCanPs *InstancePtr); +* +*****************************************************************************/ +#define XCanPs_IsHighPriorityBufFull(InstancePtr) \ + ((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_SR_OFFSET) & XCANPS_SR_TXBFLL_MASK) ? TRUE : FALSE) + + +/****************************************************************************/ +/** +* +* This macro checks if the receive FIFO is empty. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if RX FIFO is empty. +* - FALSE if the RX FIFO is NOT empty. +* +* @note C-Style signature: +* int XCanPs_IsRxEmpty(XCanPs *InstancePtr); +* +*****************************************************************************/ +#define XCanPs_IsRxEmpty(InstancePtr) \ + ((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_ISR_OFFSET) & XCANPS_IXR_RXNEMP_MASK) ? FALSE : TRUE) + + +/****************************************************************************/ +/** +* +* This macro checks if the CAN device is ready for the driver to change +* Acceptance Filter Identifier Registers (AFIR) and Acceptance Filter Mask +* Registers (AFMR). +* +* AFIR and AFMR for a filter are changeable only after the filter is disabled +* and this routine returns FALSE. The filter can be disabled using the +* XCanPs_AcceptFilterDisable function. +* +* Use the XCanPs_Accept_* functions for configuring the acceptance filters. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if the device is busy and NOT ready to accept writes to +* AFIR and AFMR. +* - FALSE if the device is ready to accept writes to AFIR and +* AFMR. +* +* @note C-Style signature: +* int XCanPs_IsAcceptFilterBusy(XCanPs *InstancePtr); +* +*****************************************************************************/ +#define XCanPs_IsAcceptFilterBusy(InstancePtr) \ + ((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_SR_OFFSET) & XCANPS_SR_ACFBSY_MASK) ? TRUE : FALSE) + + +/****************************************************************************/ +/** +* +* This macro calculates CAN message identifier value given identifier field +* values. +* +* @param StandardId contains Standard Message ID value. +* @param SubRemoteTransReq contains Substitute Remote Transmission +* Request value. +* @param IdExtension contains Identifier Extension value. +* @param ExtendedId contains Extended Message ID value. +* @param RemoteTransReq contains Remote Transmission Request value. +* +* @return Message Identifier value. +* +* @note C-Style signature: +* u32 XCanPs_CreateIdValue(u32 StandardId, +* u32 SubRemoteTransReq, +* u32 IdExtension, u32 ExtendedId, +* u32 RemoteTransReq); +* +* Read the CAN specification for meaning of each parameter. +* +*****************************************************************************/ +#define XCanPs_CreateIdValue(StandardId, SubRemoteTransReq, IdExtension, \ + ExtendedId, RemoteTransReq) \ + ((((StandardId) << XCANPS_IDR_ID1_SHIFT) & XCANPS_IDR_ID1_MASK) | \ + (((SubRemoteTransReq) << XCANPS_IDR_SRR_SHIFT) & XCANPS_IDR_SRR_MASK)|\ + (((IdExtension) << XCANPS_IDR_IDE_SHIFT) & XCANPS_IDR_IDE_MASK) | \ + (((ExtendedId) << XCANPS_IDR_ID2_SHIFT) & XCANPS_IDR_ID2_MASK) | \ + ((RemoteTransReq) & XCANPS_IDR_RTR_MASK)) + + +/****************************************************************************/ +/** +* +* This macro calculates value for Data Length Code register given Data +* Length Code value. +* +* @param DataLengCode indicates Data Length Code value. +* +* @return Value that can be assigned to Data Length Code register. +* +* @note C-Style signature: +* u32 XCanPs_CreateDlcValue(u32 DataLengCode); +* +* Read the CAN specification for meaning of Data Length Code. +* +*****************************************************************************/ +#define XCanPs_CreateDlcValue(DataLengCode) \ + (((DataLengCode) << XCANPS_DLCR_DLC_SHIFT) & XCANPS_DLCR_DLC_MASK) + + +/****************************************************************************/ +/** +* +* This macro clears the timestamp in the Timestamp Control Register. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return None. +* +* @note C-Style signature: +* void XCanPs_ClearTimestamp(XCanPs *InstancePtr); +* +*****************************************************************************/ +#define XCanPs_ClearTimestamp(InstancePtr) \ + XCanPs_WriteReg((InstancePtr)->CanConfig.BaseAddr, \ + XCANPS_TCR_OFFSET, XCANPS_TCR_CTS_MASK) + +/************************** Function Prototypes ******************************/ + +/* + * Functions in xcanps.c + */ +int XCanPs_CfgInitialize(XCanPs *InstancePtr, XCanPs_Config *ConfigPtr, + u32 EffectiveAddr); + +void XCanPs_Reset(XCanPs *InstancePtr); +u8 XCanPs_GetMode(XCanPs *InstancePtr); +void XCanPs_EnterMode(XCanPs *InstancePtr, u8 OperationMode); +u32 XCanPs_GetStatus(XCanPs *InstancePtr); +void XCanPs_GetBusErrorCounter(XCanPs *InstancePtr, u8 *RxErrorCount, + u8 *TxErrorCount); +u32 XCanPs_GetBusErrorStatus(XCanPs *InstancePtr); +void XCanPs_ClearBusErrorStatus(XCanPs *InstancePtr, u32 Mask); +int XCanPs_Send(XCanPs *InstancePtr, u32 *FramePtr); +int XCanPs_Recv(XCanPs *InstancePtr, u32 *FramePtr); +int XCanPs_SendHighPriority(XCanPs *InstancePtr, u32 *FramePtr); +void XCanPs_AcceptFilterEnable(XCanPs *InstancePtr, u32 FilterIndexes); +void XCanPs_AcceptFilterDisable(XCanPs *InstancePtr, u32 FilterIndexes); +u32 XCanPs_AcceptFilterGetEnabled(XCanPs *InstancePtr); +int XCanPs_AcceptFilterSet(XCanPs *InstancePtr, u32 FilterIndex, + u32 MaskValue, u32 IdValue); +void XCanPs_AcceptFilterGet(XCanPs *InstancePtr, u32 FilterIndex, + u32 *MaskValue, u32 *IdValue); + +int XCanPs_SetBaudRatePrescaler(XCanPs *InstancePtr, u8 Prescaler); +u8 XCanPs_GetBaudRatePrescaler(XCanPs *InstancePtr); +int XCanPs_SetBitTiming(XCanPs *InstancePtr, u8 SyncJumpWidth, + u8 TimeSegment2, u8 TimeSegment1); +void XCanPs_GetBitTiming(XCanPs *InstancePtr, u8 *SyncJumpWidth, + u8 *TimeSegment2, u8 *TimeSegment1); + +int XCanPs_SetRxIntrWatermark(XCanPs *InstancePtr, u8 Threshold); +u8 XCanPs_GetRxIntrWatermark(XCanPs *InstancePtr); + +/* + * Diagnostic functions in xcanps_selftest.c + */ +int XCanPs_SelfTest(XCanPs *InstancePtr); + +/* + * Functions in xcanps_intr.c + */ +void XCanPs_IntrEnable(XCanPs *InstancePtr, u32 Mask); +void XCanPs_IntrDisable(XCanPs *InstancePtr, u32 Mask); +u32 XCanPs_IntrGetEnabled(XCanPs *InstancePtr); +u32 XCanPs_IntrGetStatus(XCanPs *InstancePtr); +void XCanPs_IntrClear(XCanPs *InstancePtr, u32 Mask); +void XCanPs_IntrHandler(void *InstancePtr); +int XCanPs_SetHandler(XCanPs *InstancePtr, u32 HandlerType, + void *CallBackFunc, void *CallBackRef); + +/* + * Functions in xcanps_sinit.c + */ +XCanPs_Config *XCanPs_LookupConfig(u16 DeviceId); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xcanps_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xcanps_hw.h new file mode 100644 index 000000000..22f456f86 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xcanps_hw.h @@ -0,0 +1,375 @@ +/****************************************************************************** +* +* (c) Copyright 2010-2013 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcanps_hw.h +* +* This header file contains the identifiers and basic driver functions (or +* macros) that can be used to access the device. Other driver functions +* are defined in xcanps.h. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+* 1.01a sbs    12/27/11 Updated the Register/bit definitions
+*                       Changed XCANPS_RXFWIR_RXFLL_MASK to XCANPS_WIR_FW_MASK
+*                       Changed XCANPS_RXWIR_OFFSET to XCANPS_WIR_OFFSET
+*			Added XCANPS_IXR_TXFEMP_MASK for Tx Fifo Empty
+*			Changed XCANPS_IXR_RXFLL_MASK to
+*			XCANPS_IXR_RXFWMFLL_MASK
+* 			Changed
+*			XCANPS_TXBUF_ID_OFFSET to XCANPS_TXHPB_ID_OFFSET
+* 			XCANPS_TXBUF_DLC_OFFSET to XCANPS_TXHPB_DLC_OFFSET
+*			XCANPS_TXBUF_DW1_OFFSET  to XCANPS_TXHPB_DW1_OFFSET
+*			XCANPS_TXBUF_DW2_OFFSET  to XCANPS_TXHPB_DW2_OFFSET
+* 1.02a adk   08/08/13  Updated for inclding the function prototype
+*
+* +******************************************************************************/ + +#ifndef XCANPS_HW_H /* prevent circular inclusions */ +#define XCANPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register offsets for the CAN. Each register is 32 bits. + * @{ + */ +#define XCANPS_SRR_OFFSET 0x00 /**< Software Reset Register */ +#define XCANPS_MSR_OFFSET 0x04 /**< Mode Select Register */ +#define XCANPS_BRPR_OFFSET 0x08 /**< Baud Rate Prescaler */ +#define XCANPS_BTR_OFFSET 0x0C /**< Bit Timing Register */ +#define XCANPS_ECR_OFFSET 0x10 /**< Error Counter Register */ +#define XCANPS_ESR_OFFSET 0x14 /**< Error Status Register */ +#define XCANPS_SR_OFFSET 0x18 /**< Status Register */ + +#define XCANPS_ISR_OFFSET 0x1C /**< Interrupt Status Register */ +#define XCANPS_IER_OFFSET 0x20 /**< Interrupt Enable Register */ +#define XCANPS_ICR_OFFSET 0x24 /**< Interrupt Clear Register */ +#define XCANPS_TCR_OFFSET 0x28 /**< Timestamp Control Register */ +#define XCANPS_WIR_OFFSET 0x2C /**< Watermark Interrupt Reg */ + +#define XCANPS_TXFIFO_ID_OFFSET 0x30 /**< TX FIFO ID */ +#define XCANPS_TXFIFO_DLC_OFFSET 0x34 /**< TX FIFO DLC */ +#define XCANPS_TXFIFO_DW1_OFFSET 0x38 /**< TX FIFO Data Word 1 */ +#define XCANPS_TXFIFO_DW2_OFFSET 0x3C /**< TX FIFO Data Word 2 */ + +#define XCANPS_TXHPB_ID_OFFSET 0x40 /**< TX High Priority Buffer ID */ +#define XCANPS_TXHPB_DLC_OFFSET 0x44 /**< TX High Priority Buffer DLC */ +#define XCANPS_TXHPB_DW1_OFFSET 0x48 /**< TX High Priority Buf Data 1 */ +#define XCANPS_TXHPB_DW2_OFFSET 0x4C /**< TX High Priority Buf Data Word 2 */ + +#define XCANPS_RXFIFO_ID_OFFSET 0x50 /**< RX FIFO ID */ +#define XCANPS_RXFIFO_DLC_OFFSET 0x54 /**< RX FIFO DLC */ +#define XCANPS_RXFIFO_DW1_OFFSET 0x58 /**< RX FIFO Data Word 1 */ +#define XCANPS_RXFIFO_DW2_OFFSET 0x5C /**< RX FIFO Data Word 2 */ + +#define XCANPS_AFR_OFFSET 0x60 /**< Acceptance Filter Register */ +#define XCANPS_AFMR1_OFFSET 0x64 /**< Acceptance Filter Mask 1 */ +#define XCANPS_AFIR1_OFFSET 0x68 /**< Acceptance Filter ID 1 */ +#define XCANPS_AFMR2_OFFSET 0x6C /**< Acceptance Filter Mask 2 */ +#define XCANPS_AFIR2_OFFSET 0x70 /**< Acceptance Filter ID 2 */ +#define XCANPS_AFMR3_OFFSET 0x74 /**< Acceptance Filter Mask 3 */ +#define XCANPS_AFIR3_OFFSET 0x78 /**< Acceptance Filter ID 3 */ +#define XCANPS_AFMR4_OFFSET 0x7C /**< Acceptance Filter Mask 4 */ +#define XCANPS_AFIR4_OFFSET 0x80 /**< Acceptance Filter ID 4 */ +/* @} */ + +/** @name Software Reset Register (SRR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_SRR_CEN_MASK 0x00000002 /**< Can Enable */ +#define XCANPS_SRR_SRST_MASK 0x00000001 /**< Reset */ +/* @} */ + +/** @name Mode Select Register (MSR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_MSR_SNOOP_MASK 0x00000004 /**< Snoop Mode Select */ +#define XCANPS_MSR_LBACK_MASK 0x00000002 /**< Loop Back Mode Select */ +#define XCANPS_MSR_SLEEP_MASK 0x00000001 /**< Sleep Mode Select */ +/* @} */ + +/** @name Baud Rate Prescaler register (BRPR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_BRPR_BRP_MASK 0x000000FF /**< Baud Rate Prescaler */ +/* @} */ + +/** @name Bit Timing Register (BTR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_BTR_SJW_MASK 0x00000180 /**< Synchronization Jump Width */ +#define XCANPS_BTR_SJW_SHIFT 7 +#define XCANPS_BTR_TS2_MASK 0x00000070 /**< Time Segment 2 */ +#define XCANPS_BTR_TS2_SHIFT 4 +#define XCANPS_BTR_TS1_MASK 0x0000000F /**< Time Segment 1 */ +/* @} */ + +/** @name Error Counter Register (ECR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_ECR_REC_MASK 0x0000FF00 /**< Receive Error Counter */ +#define XCANPS_ECR_REC_SHIFT 8 +#define XCANPS_ECR_TEC_MASK 0x000000FF /**< Transmit Error Counter */ +/* @} */ + +/** @name Error Status Register (ESR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_ESR_ACKER_MASK 0x00000010 /**< ACK Error */ +#define XCANPS_ESR_BERR_MASK 0x00000008 /**< Bit Error */ +#define XCANPS_ESR_STER_MASK 0x00000004 /**< Stuff Error */ +#define XCANPS_ESR_FMER_MASK 0x00000002 /**< Form Error */ +#define XCANPS_ESR_CRCER_MASK 0x00000001 /**< CRC Error */ +/* @} */ + +/** @name Status Register (SR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_SR_SNOOP_MASK 0x00001000 /**< Snoop Mask */ +#define XCANPS_SR_ACFBSY_MASK 0x00000800 /**< Acceptance Filter busy */ +#define XCANPS_SR_TXFLL_MASK 0x00000400 /**< TX FIFO is full */ +#define XCANPS_SR_TXBFLL_MASK 0x00000200 /**< TX High Priority Buffer full */ +#define XCANPS_SR_ESTAT_MASK 0x00000180 /**< Error Status */ +#define XCANPS_SR_ESTAT_SHIFT 7 +#define XCANPS_SR_ERRWRN_MASK 0x00000040 /**< Error Warning */ +#define XCANPS_SR_BBSY_MASK 0x00000020 /**< Bus Busy */ +#define XCANPS_SR_BIDLE_MASK 0x00000010 /**< Bus Idle */ +#define XCANPS_SR_NORMAL_MASK 0x00000008 /**< Normal Mode */ +#define XCANPS_SR_SLEEP_MASK 0x00000004 /**< Sleep Mode */ +#define XCANPS_SR_LBACK_MASK 0x00000002 /**< Loop Back Mode */ +#define XCANPS_SR_CONFIG_MASK 0x00000001 /**< Configuration Mode */ +/* @} */ + +/** @name Interrupt Status/Enable/Clear Register Bit Definitions and Masks + * @{ + */ +#define XCANPS_IXR_TXFEMP_MASK 0x00004000 /**< Tx Fifo Empty Interrupt */ +#define XCANPS_IXR_TXFWMEMP_MASK 0x00002000 /**< Tx Fifo Watermark Empty */ +#define XCANPS_IXR_RXFWMFLL_MASK 0x00001000 /**< Rx FIFO Watermark Full */ +#define XCANPS_IXR_WKUP_MASK 0x00000800 /**< Wake up Interrupt */ +#define XCANPS_IXR_SLP_MASK 0x00000400 /**< Sleep Interrupt */ +#define XCANPS_IXR_BSOFF_MASK 0x00000200 /**< Bus Off Interrupt */ +#define XCANPS_IXR_ERROR_MASK 0x00000100 /**< Error Interrupt */ +#define XCANPS_IXR_RXNEMP_MASK 0x00000080 /**< RX FIFO Not Empty Interrupt */ +#define XCANPS_IXR_RXOFLW_MASK 0x00000040 /**< RX FIFO Overflow Interrupt */ +#define XCANPS_IXR_RXUFLW_MASK 0x00000020 /**< RX FIFO Underflow Interrupt */ +#define XCANPS_IXR_RXOK_MASK 0x00000010 /**< New Message Received Intr */ +#define XCANPS_IXR_TXBFLL_MASK 0x00000008 /**< TX High Priority Buf Full */ +#define XCANPS_IXR_TXFLL_MASK 0x00000004 /**< TX FIFO Full Interrupt */ +#define XCANPS_IXR_TXOK_MASK 0x00000002 /**< TX Successful Interrupt */ +#define XCANPS_IXR_ARBLST_MASK 0x00000001 /**< Arbitration Lost Interrupt */ +#define XCANPS_IXR_ALL (XCANPS_IXR_RXFWMFLL_MASK | \ + XCANPS_IXR_WKUP_MASK | \ + XCANPS_IXR_SLP_MASK | \ + XCANPS_IXR_BSOFF_MASK | \ + XCANPS_IXR_ERROR_MASK | \ + XCANPS_IXR_RXNEMP_MASK | \ + XCANPS_IXR_RXOFLW_MASK | \ + XCANPS_IXR_RXUFLW_MASK | \ + XCANPS_IXR_RXOK_MASK | \ + XCANPS_IXR_TXBFLL_MASK | \ + XCANPS_IXR_TXFLL_MASK | \ + XCANPS_IXR_TXOK_MASK | \ + XCANPS_IXR_ARBLST_MASK) +/* @} */ + +/** @name CAN Timestamp Control Register (TCR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_TCR_CTS_MASK 0x00000001 /**< Clear Timestamp counter mask */ +/* @} */ + +/** @name CAN Watermark Register (WIR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_WIR_FW_MASK 0x0000003F /**< Rx Full Threshold mask */ +#define XCANPS_WIR_EW_MASK 0x00003F00 /**< Tx Empty Threshold mask */ +#define XCANPS_WIR_EW_SHIFT 0x00000008 /**< Tx Empty Threshold shift */ + +/* @} */ + +/** @name CAN Frame Identifier (TX High Priority Buffer/TX/RX/Acceptance Filter + Mask/Acceptance Filter ID) + * @{ + */ +#define XCANPS_IDR_ID1_MASK 0xFFE00000 /**< Standard Messg Identifier */ +#define XCANPS_IDR_ID1_SHIFT 21 +#define XCANPS_IDR_SRR_MASK 0x00100000 /**< Substitute Remote TX Req */ +#define XCANPS_IDR_SRR_SHIFT 20 +#define XCANPS_IDR_IDE_MASK 0x00080000 /**< Identifier Extension */ +#define XCANPS_IDR_IDE_SHIFT 19 +#define XCANPS_IDR_ID2_MASK 0x0007FFFE /**< Extended Message Ident */ +#define XCANPS_IDR_ID2_SHIFT 1 +#define XCANPS_IDR_RTR_MASK 0x00000001 /**< Remote TX Request */ +/* @} */ + +/** @name CAN Frame Data Length Code (TX High Priority Buffer/TX/RX) + * @{ + */ +#define XCANPS_DLCR_DLC_MASK 0xF0000000 /**< Data Length Code */ +#define XCANPS_DLCR_DLC_SHIFT 28 +#define XCANPS_DLCR_TIMESTAMP_MASK 0x0000FFFF /**< Timestamp Mask (Rx only) */ + +/* @} */ + +/** @name CAN Frame Data Word 1 (TX High Priority Buffer/TX/RX) + * @{ + */ +#define XCANPS_DW1R_DB0_MASK 0xFF000000 /**< Data Byte 0 */ +#define XCANPS_DW1R_DB0_SHIFT 24 +#define XCANPS_DW1R_DB1_MASK 0x00FF0000 /**< Data Byte 1 */ +#define XCANPS_DW1R_DB1_SHIFT 16 +#define XCANPS_DW1R_DB2_MASK 0x0000FF00 /**< Data Byte 2 */ +#define XCANPS_DW1R_DB2_SHIFT 8 +#define XCANPS_DW1R_DB3_MASK 0x000000FF /**< Data Byte 3 */ +/* @} */ + +/** @name CAN Frame Data Word 2 (TX High Priority Buffer/TX/RX) + * @{ + */ +#define XCANPS_DW2R_DB4_MASK 0xFF000000 /**< Data Byte 4 */ +#define XCANPS_DW2R_DB4_SHIFT 24 +#define XCANPS_DW2R_DB5_MASK 0x00FF0000 /**< Data Byte 5 */ +#define XCANPS_DW2R_DB5_SHIFT 16 +#define XCANPS_DW2R_DB6_MASK 0x0000FF00 /**< Data Byte 6 */ +#define XCANPS_DW2R_DB6_SHIFT 8 +#define XCANPS_DW2R_DB7_MASK 0x000000FF /**< Data Byte 7 */ +/* @} */ + +/** @name Acceptance Filter Register (AFR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_AFR_UAF4_MASK 0x00000008 /**< Use Acceptance Filter No.4 */ +#define XCANPS_AFR_UAF3_MASK 0x00000004 /**< Use Acceptance Filter No.3 */ +#define XCANPS_AFR_UAF2_MASK 0x00000002 /**< Use Acceptance Filter No.2 */ +#define XCANPS_AFR_UAF1_MASK 0x00000001 /**< Use Acceptance Filter No.1 */ +#define XCANPS_AFR_UAF_ALL_MASK (XCANPS_AFR_UAF4_MASK | \ + XCANPS_AFR_UAF3_MASK | \ + XCANPS_AFR_UAF2_MASK | \ + XCANPS_AFR_UAF1_MASK) +/* @} */ + +/** @name CAN frame length constants + * @{ + */ +#define XCANPS_MAX_FRAME_SIZE 16 /**< Maximum CAN frame length in bytes */ +/* @} */ + +/* For backwards compatibilty */ +#define XCANPS_TXBUF_ID_OFFSET XCANPS_TXHPB_ID_OFFSET +#define XCANPS_TXBUF_DLC_OFFSET XCANPS_TXHPB_DLC_OFFSET +#define XCANPS_TXBUF_DW1_OFFSET XCANPS_TXHPB_DW1_OFFSET +#define XCANPS_TXBUF_DW2_OFFSET XCANPS_TXHPB_DW2_OFFSET + +#define XCANPS_RXFWIR_RXFLL_MASK XCANPS_WIR_FW_MASK +#define XCANPS_RXWIR_OFFSET XCANPS_WIR_OFFSET +#define XCANPS_IXR_RXFLL_MASK XCANPS_IXR_RXFWMFLL_MASK + + + + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* This macro reads the given register. +* +* @param BaseAddr is the base address of the device. +* @param RegOffset is the register offset to be read. +* +* @return The 32-bit value of the register +* +* @note None. +* +*****************************************************************************/ +#define XCanPs_ReadReg(BaseAddr, RegOffset) \ + Xil_In32((BaseAddr) + (RegOffset)) + + +/****************************************************************************/ +/** +* +* This macro writes the given register. +* +* @param BaseAddr is the base address of the device. +* @param RegOffset is the register offset to be written. +* @param Data is the 32-bit value to write to the register. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#define XCanPs_WriteReg(BaseAddr, RegOffset, Data) \ + Xil_Out32((BaseAddr) + (RegOffset), (Data)) + +/************************** Function Prototypes ******************************/ +/* + * Perform reset operation to the CanPs interface + */ +void XCanPs_ResetHw(u32 BaseAddr); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h new file mode 100644 index 000000000..0933143a4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h @@ -0,0 +1,49 @@ +/* $Id: xcpu_cortexa9.h,v 1.1.2.1 2011/02/11 09:30:37 kkatna Exp $ */ +/****************************************************************************** +* +* (c) Copyright 2011 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcpu_cortexa9.h +* +* dummy file +* +******************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xdebug.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xdebug.h new file mode 100644 index 000000000..8ab5e212c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xdebug.h @@ -0,0 +1,61 @@ +#ifndef XDEBUG +#define XDEBUG + +#undef DEBUG + +#if defined(DEBUG) && !defined(NDEBUG) + +#ifndef XDEBUG_WARNING +#define XDEBUG_WARNING +#warning DEBUG is enabled +#endif + +int printf(const char *format, ...); + +#define XDBG_DEBUG_ERROR 0x00000001 /* error condition messages */ +#define XDBG_DEBUG_GENERAL 0x00000002 /* general debug messages */ +#define XDBG_DEBUG_ALL 0xFFFFFFFF /* all debugging data */ + +#define XDBG_DEBUG_FIFO_REG 0x00000100 /* display register reads/writes */ +#define XDBG_DEBUG_FIFO_RX 0x00000101 /* receive debug messages */ +#define XDBG_DEBUG_FIFO_TX 0x00000102 /* transmit debug messages */ +#define XDBG_DEBUG_FIFO_ALL 0x0000010F /* all fifo debug messages */ + +#define XDBG_DEBUG_TEMAC_REG 0x00000400 /* display register reads/writes */ +#define XDBG_DEBUG_TEMAC_RX 0x00000401 /* receive debug messages */ +#define XDBG_DEBUG_TEMAC_TX 0x00000402 /* transmit debug messages */ +#define XDBG_DEBUG_TEMAC_ALL 0x0000040F /* all temac debug messages */ + +#define XDBG_DEBUG_TEMAC_ADPT_RX 0x00000800 /* receive debug messages */ +#define XDBG_DEBUG_TEMAC_ADPT_TX 0x00000801 /* transmit debug messages */ +#define XDBG_DEBUG_TEMAC_ADPT_IOCTL 0x00000802 /* ioctl debug messages */ +#define XDBG_DEBUG_TEMAC_ADPT_MISC 0x00000803 /* debug msg for other routines */ +#define XDBG_DEBUG_TEMAC_ADPT_ALL 0x0000080F /* all temac adapter debug messages */ + +#define xdbg_current_types (XDBG_DEBUG_ERROR) + +#define xdbg_stmnt(x) x + +/* In VxWorks, if _WRS_GNU_VAR_MACROS is defined, special syntax is needed for + * macros that accept variable number of arguments + */ +#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS) +#define xdbg_printf(type, args...) (((type) & xdbg_current_types) ? printf (## args) : 0) +#else /* ANSI Syntax */ +#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0) +#endif + +#else /* defined(DEBUG) && !defined(NDEBUG) */ + +#define xdbg_stmnt(x) + +/* See VxWorks comments above */ +#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS) +#define xdbg_printf(type, args...) +#else /* ANSI Syntax */ +#define xdbg_printf(...) +#endif + +#endif /* defined(DEBUG) && !defined(NDEBUG) */ + +#endif /* XDEBUG */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xdevcfg.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xdevcfg.h new file mode 100644 index 000000000..d40321251 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xdevcfg.h @@ -0,0 +1,389 @@ +/****************************************************************************** +* +* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdevcfg.h +* +* The is the main header file for the Device Configuration Interface of the Zynq +* device. The device configuration interface has three main functionality. +* 1. AXI-PCAP +* 2. Security Policy +* 3. XADC +* This current version of the driver supports only the AXI-PCAP and Security +* Policy blocks. There is a separate driver for XADC. +* +* AXI-PCAP is used for download/upload an encrypted or decrypted bitstream. +* DMA embedded in the AXI PCAP provides the master interface to +* the Device configuration block for any DMA transfers. The data transfer can +* take place between the Tx/RxFIFOs of AXI-PCAP and memory (on chip +* RAM/DDR/peripheral memory). +* +* The current driver only supports the downloading the FPGA bitstream and +* readback of the decrypted image (sort of loopback). +* The driver does not know what information needs to be written to the FPGA to +* readback FPGA configuration register or memory data. The application above the +* driver should take care of creating the data that needs to be downloaded to +* the FPGA so that the bitstream can be readback. +* This driver also does not support the reading of the internal registers of the +* PCAP. The driver has no knowledge of the PCAP internals. +* +* Initialization and Configuration +* +* The device driver enables higher layer software (e.g., an application) to +* communicate with the Device Configuration device. +* +* XDcfg_CfgInitialize() API is used to initialize the Device Configuration +* Interface. The user needs to first call the XDcfg_LookupConfig() API which +* returns the Configuration structure pointer which is passed as a parameter to +* the XDcfg_CfgInitialize() API. +* +* Interrupts +* The Driver implements an interrupt handler to support the interrupts provided +* by this interface. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The XDcfg driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +* +*

+* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.00a nm  05/31/12 Updated the driver for CR 660835 so that input length for
+*		     source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
+*		     APIs is words (32 bit) and not bytes.
+* 		     Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
+*		     to add information that 2 LSBs of the Source/Destination
+*		     address when equal to 2Â’b01 indicate the last DMA command
+*		     of an overall transfer.
+*		     Destination Address passed to this API for secure transfers
+*		     instead of using 0xFFFFFFFF for CR 662197. This issue was
+*		     resulting in the failure of secure transfers of
+*		     non-bitstream images.
+* 2.01a nm  07/07/12 Updated the XDcfg_IntrClear function to directly
+*		     set the mask instead of oring it with the
+*		     value read from the interrupt status register
+* 		     Added defines for the PS Version bits,
+*	             removed the FIFO Flush bits from the
+*		     Miscellaneous Control Reg.
+*		     Added XDcfg_GetPsVersion, XDcfg_SelectIcapInterface
+*		     and XDcfg_SelectPcapInterface APIs for CR 643295
+*		     The user has to call the XDcfg_SelectIcapInterface API
+*		     for the PL reconfiguration using AXI HwIcap.
+*		     Updated the XDcfg_Transfer API to clear the
+*		     QUARTER_PCAP_RATE_EN bit in the control register for
+*		     non secure writes for CR 675543.
+* 2.02a nm  01/31/13 Fixed CR# 679335.
+* 		     Added Setting and Clearing the internal PCAP loopback.
+*		     Removed code for enabling/disabling AES engine as BootROM
+*		     locks down this setting.
+*		     Fixed CR# 681976.
+*		     Skip Checking the PCFG_INIT in case of non-secure DMA
+*		     loopback.
+*		     Fixed CR# 699558.
+*		     XDcfg_Transfer fails to transfer data in loopback mode.
+*		     Fixed CR# 701348.
+*                    Peripheral test fails with  Running
+* 		     DcfgSelfTestExample() in SECURE bootmode.
+* 2.03a nm  04/19/13 Fixed CR# 703728.
+*		     Updated the register definitions as per the latest TRM
+*		     version UG585 (v1.4) November 16, 2012.
+* 3.0   adk 10/12/13 Updated as per the New Tcl API's
+* 3.0   kpc 21/02/14 Added function prototype for XDcfg_ClearControlRegister
+*
+* +******************************************************************************/ +#ifndef XDCFG_H /* prevent circular inclusions */ +#define XDCFG_H /* by using protection macros */ + +/***************************** Include Files *********************************/ + +#include "xdevcfg_hw.h" +#include "xstatus.h" +#include "xil_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ + +/* Types of PCAP transfers */ + +#define XDCFG_NON_SECURE_PCAP_WRITE 1 +#define XDCFG_SECURE_PCAP_WRITE 2 +#define XDCFG_PCAP_READBACK 3 +#define XDCFG_CONCURRENT_SECURE_READ_WRITE 4 +#define XDCFG_CONCURRENT_NONSEC_READ_WRITE 5 + + +/**************************** Type Definitions *******************************/ +/** +* The handler data type allows the user to define a callback function to +* respond to interrupt events in the system. This function is executed +* in interrupt context, so amount of processing should be minimized. +* +* @param CallBackRef is the callback reference passed in by the upper +* layer when setting the callback functions, and passed back to +* the upper layer when the callback is invoked. Its type is +* unimportant to the driver component, so it is a void pointer. +* @param Status is the Interrupt status of the XDcfg device. +*/ +typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status); + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddr; /**< Base address of the device */ +} XDcfg_Config; + +/** + * The XDcfg driver instance data. + */ +typedef struct { + XDcfg_Config Config; /**< Hardware Configuration */ + u32 IsReady; /**< Device is initialized and ready */ + u32 IsStarted; /**< Device Configuration Interface + * is running + */ + XDcfg_IntrHandler StatusHandler; /* Event handler function */ + void *CallBackRef; /* Callback reference for event handler */ +} XDcfg; + +/****************************************************************************/ +/** +* +* Unlock the Device Config Interface block. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return None. +* +* @note C-style signature: +* void XDcfg_Unlock(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_Unlock(InstancePtr) \ + XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, \ + XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA) + + + +/****************************************************************************/ +/** +* +* Get the version number of the PS from the Miscellaneous Control Register. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return Version of the PS. +* +* @note C-style signature: +* void XDcfg_GetPsVersion(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_GetPsVersion(InstancePtr) \ + ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \ + XDCFG_MCTRL_OFFSET)) & \ + XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \ + XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT + + + +/****************************************************************************/ +/** +* +* Read the multiboot config register value. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return None. +* +* @note C-style signature: +* u32 XDcfg_ReadMultiBootConfig(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_ReadMultiBootConfig(InstancePtr) \ + XDcfg_ReadReg((InstancePtr)->Config.BaseAddr + \ + XDCFG_MULTIBOOT_ADDR_OFFSET) + + +/****************************************************************************/ +/** +* +* Selects ICAP interface for reconfiguration after the initial configuration +* of the PL. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return None. +* +* @note C-style signature: +* void XDcfg_SelectIcapInterface(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_SelectIcapInterface(InstancePtr) \ + XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \ + ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \ + & ( ~XDCFG_CTRL_PCAP_PR_MASK))) + +/****************************************************************************/ +/** +* +* Selects PCAP interface for reconfiguration after the initial configuration +* of the PL. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return None. +* +* @note C-style signature: +* void XDcfg_SelectPcapInterface(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_SelectPcapInterface(InstancePtr) \ + XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \ + ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \ + | XDCFG_CTRL_PCAP_PR_MASK)) + + + +/************************** Function Prototypes ******************************/ + +/* + * Lookup configuration in xdevcfg_sinit.c. + */ +XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId); + +/* + * Selftest function in xdevcfg_selftest.c + */ +int XDcfg_SelfTest(XDcfg *InstancePtr); + +/* + * Interface functions in xdevcfg.c + */ +int XDcfg_CfgInitialize(XDcfg *InstancePtr, + XDcfg_Config *ConfigPtr, u32 EffectiveAddress); + +void XDcfg_EnablePCAP(XDcfg *InstancePtr); + +void XDcfg_DisablePCAP(XDcfg *InstancePtr); + +void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask); + +void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask); + +u32 XDcfg_GetControlRegister(XDcfg *InstancePtr); + +void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data); + +u32 XDcfg_GetLockRegister(XDcfg *InstancePtr); + +void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data); + +u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr); + +void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data); + +u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr); + +void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data); + +u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr); + +void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask); + +u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr); + +u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr); + +void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr, + u32 SrcWordLength, u32 DestWordLength); + +u32 XDcfg_Transfer(XDcfg *InstancePtr, + void *SourcePtr, u32 SrcWordLength, + void *DestPtr, u32 DestWordLength, + u32 TransferType); + +/* + * Interrupt related function prototypes implemented in xdevcfg_intr.c + */ +void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask); + +void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask); + +u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr); + +u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr); + +void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask); + +void XDcfg_InterruptHandler(XDcfg *InstancePtr); + +void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc, + void *CallBackRef); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h new file mode 100644 index 000000000..3f06b5d0c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h @@ -0,0 +1,401 @@ +/****************************************************************************** +* +* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdevcfg_hw.h +* +* This file contains the hardware interface to the Device Config Interface. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.01a nm  08/01/12 Added defines for the PS Version bits,
+*	             removed the FIFO Flush bits from the
+*		     Miscellaneous Control Reg
+* 2.03a nm  04/19/13 Fixed CR# 703728.
+*		     Updated the register definitions as per the latest TRM
+*		     version UG585 (v1.4) November 16, 2012.
+* 2.04a	kpc	10/07/13 Added function prototype.	
+* 3.00a	kpc	25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
+*
+* +******************************************************************************/ +#ifndef XDCFG_HW_H /* prevent circular inclusions */ +#define XDCFG_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * Offsets of registers from the start of the device + * @{ + */ + +#define XDCFG_CTRL_OFFSET 0x00 /**< Control Register */ +#define XDCFG_LOCK_OFFSET 0x04 /**< Lock Register */ +#define XDCFG_CFG_OFFSET 0x08 /**< Configuration Register */ +#define XDCFG_INT_STS_OFFSET 0x0C /**< Interrupt Status Register */ +#define XDCFG_INT_MASK_OFFSET 0x10 /**< Interrupt Mask Register */ +#define XDCFG_STATUS_OFFSET 0x14 /**< Status Register */ +#define XDCFG_DMA_SRC_ADDR_OFFSET 0x18 /**< DMA Source Address Register */ +#define XDCFG_DMA_DEST_ADDR_OFFSET 0x1C /**< DMA Destination Address Reg */ +#define XDCFG_DMA_SRC_LEN_OFFSET 0x20 /**< DMA Source Transfer Length */ +#define XDCFG_DMA_DEST_LEN_OFFSET 0x24 /**< DMA Destination Transfer */ +#define XDCFG_ROM_SHADOW_OFFSET 0x28 /**< DMA ROM Shadow Register */ +#define XDCFG_MULTIBOOT_ADDR_OFFSET 0x2C /**< Multi BootAddress Pointer */ +#define XDCFG_SW_ID_OFFSET 0x30 /**< Software ID Register */ +#define XDCFG_UNLOCK_OFFSET 0x34 /**< Unlock Register */ +#define XDCFG_MCTRL_OFFSET 0x80 /**< Miscellaneous Control Reg */ + +/* @} */ + +/** @name Control Register Bit definitions + * @{ + */ + +#define XDCFG_CTRL_FORCE_RST_MASK 0x80000000 /**< Force into + * Secure Reset + */ +#define XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000 /**< Program signal to + * Reset FPGA + */ +#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x20000000 /**< Control PL POR timer */ +#define XDCFG_CTRL_PCAP_PR_MASK 0x08000000 /**< Enable PCAP for PR */ +#define XDCFG_CTRL_PCAP_MODE_MASK 0x04000000 /**< Enable PCAP */ +#define XDCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000 /**< Enable PCAP send data + * to FPGA every 4 PCAP + * cycles + */ +#define XDCFG_CTRL_MULTIBOOT_EN_MASK 0x01000000 /**< Multiboot Enable */ +#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK 0x00800000 /**< JTAG Chain Disable */ +#define XDCFG_CTRL_USER_MODE_MASK 0x00008000 /**< User Mode Mask */ +#define XDCFG_CTRL_PCFG_AES_FUSE_MASK 0x00001000 /**< AES key source */ +#define XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 /**< AES Enable Mask */ +#define XDCFG_CTRL_SEU_EN_MASK 0x00000100 /**< SEU Enable Mask */ +#define XDCFG_CTRL_SEC_EN_MASK 0x00000080 /**< Secure/Non Secure + * Status mask + */ +#define XDCFG_CTRL_SPNIDEN_MASK 0x00000040 /**< Secure Non Invasive + * Debug Enable + */ +#define XDCFG_CTRL_SPIDEN_MASK 0x00000020 /**< Secure Invasive + * Debug Enable + */ +#define XDCFG_CTRL_NIDEN_MASK 0x00000010 /**< Non-Invasive Debug + * Enable + */ +#define XDCFG_CTRL_DBGEN_MASK 0x00000008 /**< Invasive Debug + * Enable + */ +#define XDCFG_CTRL_DAP_EN_MASK 0x00000007 /**< DAP Enable Mask */ + +/* @} */ + +/** @name Lock register bit definitions + * @{ + */ + +#define XDCFG_LOCK_AES_EFUSE_MASK 0x00000010 /**< Lock AES Efuse bit */ +#define XDCFG_LOCK_AES_EN_MASK 0x00000008 /**< Lock AES_EN update */ +#define XDCFG_LOCK_SEU_MASK 0x00000004 /**< Lock SEU_En update */ +#define XDCFG_LOCK_SEC_MASK 0x00000002 /**< Lock SEC_EN and + * USER_MODE + */ +#define XDCFG_LOCK_DBG_MASK 0x00000001 /**< This bit locks + * security config + * including: DAP_En, + * DBGEN,, + * NIDEN, SPNIEN + */ +/*@}*/ + + + +/** @name Config Register Bit definitions + * @{ + */ +#define XDCFG_CFG_RFIFO_TH_MASK 0x00000C00 /**< Read FIFO + * Threshold Mask + */ +#define XDCFG_CFG_WFIFO_TH_MASK 0x00000300 /**< Write FIFO Threshold + * Mask + */ +#define XDCFG_CFG_RCLK_EDGE_MASK 0x00000080 /**< Read data active + * clock edge + */ +#define XDCFG_CFG_WCLK_EDGE_MASK 0x00000040 /**< Write data active + * clock edge + */ +#define XDCFG_CFG_DISABLE_SRC_INC_MASK 0x00000020 /**< Disable Source address + * increment mask + */ +#define XDCFG_CFG_DISABLE_DST_INC_MASK 0x00000010 /**< Disable Destination + * address increment + * mask + */ +/* @} */ + + +/** @name Interrupt Status/Mask Register Bit definitions + * @{ + */ +#define XDCFG_IXR_PSS_GTS_USR_B_MASK 0x80000000 /**< Tri-state IO during + * HIZ + */ +#define XDCFG_IXR_PSS_FST_CFG_B_MASK 0x40000000 /**< First configuration + * done + */ +#define XDCFG_IXR_PSS_GPWRDWN_B_MASK 0x20000000 /**< Global power down */ +#define XDCFG_IXR_PSS_GTS_CFG_B_MASK 0x10000000 /**< Tri-state IO during + * configuration + */ +#define XDCFG_IXR_PSS_CFG_RESET_B_MASK 0x08000000 /**< PL configuration + * reset + */ +#define XDCFG_IXR_AXI_WTO_MASK 0x00800000 /**< AXI Write Address + * or Data or response + * timeout + */ +#define XDCFG_IXR_AXI_WERR_MASK 0x00400000 /**< AXI Write response + * error + */ +#define XDCFG_IXR_AXI_RTO_MASK 0x00200000 /**< AXI Read Address or + * response timeout + */ +#define XDCFG_IXR_AXI_RERR_MASK 0x00100000 /**< AXI Read response + * error + */ +#define XDCFG_IXR_RX_FIFO_OV_MASK 0x00040000 /**< Rx FIFO Overflow */ +#define XDCFG_IXR_WR_FIFO_LVL_MASK 0x00020000 /**< Tx FIFO less than + * threshold */ +#define XDCFG_IXR_RD_FIFO_LVL_MASK 0x00010000 /**< Rx FIFO greater than + * threshold */ +#define XDCFG_IXR_DMA_CMD_ERR_MASK 0x00008000 /**< Illegal DMA command */ +#define XDCFG_IXR_DMA_Q_OV_MASK 0x00004000 /**< DMA command queue + * overflow + */ +#define XDCFG_IXR_DMA_DONE_MASK 0x00002000 /**< DMA Command Done */ +#define XDCFG_IXR_D_P_DONE_MASK 0x00001000 /**< DMA and PCAP + * transfers Done + */ +#define XDCFG_IXR_P2D_LEN_ERR_MASK 0x00000800 /**< PCAP to DMA transfer + * length error + */ +#define XDCFG_IXR_PCFG_HMAC_ERR_MASK 0x00000040 /**< HMAC error mask */ +#define XDCFG_IXR_PCFG_SEU_ERR_MASK 0x00000020 /**< SEU Error mask */ +#define XDCFG_IXR_PCFG_POR_B_MASK 0x00000010 /**< FPGA POR mask */ +#define XDCFG_IXR_PCFG_CFG_RST_MASK 0x00000008 /**< FPGA Reset mask */ +#define XDCFG_IXR_PCFG_DONE_MASK 0x00000004 /**< Done Signal Mask */ +#define XDCFG_IXR_PCFG_INIT_PE_MASK 0x00000002 /**< Detect Positive edge + * of Init Signal + */ +#define XDCFG_IXR_PCFG_INIT_NE_MASK 0x00000001 /**< Detect Negative edge + * of Init Signal + */ +#define XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WTO_MASK | \ + XDCFG_IXR_AXI_WERR_MASK | \ + XDCFG_IXR_AXI_RTO_MASK | \ + XDCFG_IXR_AXI_RERR_MASK | \ + XDCFG_IXR_RX_FIFO_OV_MASK | \ + XDCFG_IXR_DMA_CMD_ERR_MASK |\ + XDCFG_IXR_DMA_Q_OV_MASK | \ + XDCFG_IXR_P2D_LEN_ERR_MASK |\ + XDCFG_IXR_PCFG_HMAC_ERR_MASK) + + +#define XDCFG_IXR_ALL_MASK 0x00F7F8EF + + + +/* @} */ + + +/** @name Status Register Bit definitions + * @{ + */ +#define XDCFG_STATUS_DMA_CMD_Q_F_MASK 0x80000000 /**< DMA command + * Queue full + */ +#define XDCFG_STATUS_DMA_CMD_Q_E_MASK 0x40000000 /**< DMA command + * Queue empty + */ +#define XDCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 /**< Number of + * completed DMA + * transfers + */ +#define XDCFG_STATUS_RX_FIFO_LVL_MASK 0x01F000000 /**< Rx FIFO level */ +#define XDCFG_STATUS_TX_FIFO_LVL_MASK 0x0007F000 /**< Tx FIFO level */ + +#define XDCFG_STATUS_PSS_GTS_USR_B 0x00000800 /**< Tri-state IO + * during HIZ + */ +#define XDCFG_STATUS_PSS_FST_CFG_B 0x00000400 /**< First PL config + * done + */ +#define XDCFG_STATUS_PSS_GPWRDWN_B 0x00000200 /**< Global power down */ +#define XDCFG_STATUS_PSS_GTS_CFG_B 0x00000100 /**< Tri-state IO during + * config + */ +#define XDCFG_STATUS_SECURE_RST_MASK 0x00000080 /**< Secure Reset + * POR Status + */ +#define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 0x00000040 /**< Illegal APB + * access + */ +#define XDCFG_STATUS_PSS_CFG_RESET_B 0x00000020 /**< PL config + * reset status + */ +#define XDCFG_STATUS_PCFG_INIT_MASK 0x00000010 /**< FPGA Init + * Status + */ +#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008 + /**< BBRAM key + * disable + */ +#define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004 /**< Efuse Security + * Enable Status + */ +#define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK 0x00000002 /**< EFuse JTAG + * Disable + * status + */ +/* @} */ + + +/** @name DMA Source/Destination Transfer Length Register Bit definitions + * @{ + */ +#define XDCFG_DMA_LEN_MASK 0x7FFFFFF /**< Length Mask */ +/*@}*/ + + + + +/** @name Miscellaneous Control Register Bit definitions + * @{ + */ +#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK 0xF0000000 /**< PS Version Mask */ +#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28 /**< PS Version Shift */ +#define XDCFG_MCTRL_PCAP_LPBK_MASK 0x00000010 /**< PCAP loopback mask */ +/* @} */ + +/** @name FIFO Threshold Bit definitions + * @{ + */ + +#define XDCFG_CFG_FIFO_QUARTER 0x0 /**< Quarter empty */ +#define XDCFG_CFG_FIFO_HALF 0x1 /**< Half empty */ +#define XDCFG_CFG_FIFO_3QUARTER 0x2 /**< 3/4 empty */ +#define XDCFG_CFG_FIFO_EMPTY 0x4 /**< Empty */ +/* @}*/ + + +/* Miscellaneous constant values */ +#define XDCFG_DMA_INVALID_ADDRESS 0xFFFFFFFF /**< Invalid DMA address */ +#define XDCFG_UNLOCK_DATA 0x757BDF0D /**< First APB access data*/ +#define XDCFG_BASE_ADDRESS 0xF8007000 /**< Device Config base + * address + */ +#define XDCFG_CONFIG_RESET_VALUE 0x508 /**< Config reg reset value */ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Read the given register. +* +* @param BaseAddr is the base address of the device +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note C-style signature: +* u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset) +* +*****************************************************************************/ +#define XDcfg_ReadReg(BaseAddr, RegOffset) \ + Xil_In32((BaseAddr) + (RegOffset)) + +/****************************************************************************/ +/** +* +* Write to the given register. +* +* @param BaseAddr is the base address of the device +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note C-style signature: +* void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define XDcfg_WriteReg(BaseAddr, RegOffset, Data) \ + Xil_Out32((BaseAddr) + (RegOffset), (Data)) + +/************************** Function Prototypes ******************************/ +/* + * Perform reset operation to the devcfg interface + */ +void XDcfg_ResetHw(u32 BaseAddr); +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xdmaps.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xdmaps.h new file mode 100644 index 000000000..02de2a5ec --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xdmaps.h @@ -0,0 +1,325 @@ +/***************************************************************************** +* +* (c) Copyright 2009-2013 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +*****************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdmaps.h +* +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  	Date     Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	hbm    08/19/10 First Release
+* 1.01a nm     12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
+*		        the maximum number of channels.
+*		        Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
+*                       with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h.
+*			Added the tcl file to automatically generate the
+*			xparameters.h
+* 1.02a sg     05/16/12 Made changes for doxygen and moved some function
+*			header from the xdmaps.h file to xdmaps.c file
+*			Other cleanup for coding guidelines and CR 657109
+*			and CR 657898
+*			The xdmaps_example_no_intr.c example is removed
+*			as it is using interrupts  and is similar to
+*			the interrupt example - CR 652477
+* 1.03a sg     07/16/2012 changed inline to __inline for CR665681
+* 1.04a nm     10/22/2012 Fixed CR# 681671.
+* 1.05a nm     04/15/2013 Fixed CR# 704396. Removed warnings when compiled
+*			  with -Wall and -Wextra option in bsp.
+*	       05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
+*			  function description.
+*			  Fixed CR# 704396. Removed unused variables
+*			  UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
+*			  function.
+* 1.07a asa    11/02/13. Made changes to fix compilation issues for iarcc.
+*			   Removed the PDBG prints. By default they were always
+*			   defined out and never used. The PDBG is non-standard for
+*			   Xilinx drivers and no other driver does something similar.
+*			   Since there is no easy way to fix compilation issues with
+*			   the IARCC compiler around PDBG, it is better to remove it.
+*			   Users can always use xil_printfs if they want to debug.
+* 2.0   adk    10/12/13  Updated as per the New Tcl API's
+*
+* +*****************************************************************************/ + +#ifndef XDMAPS_H /* prevent circular inclusions */ +#define XDMAPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xparameters.h" +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" + +#include "xdmaps_hw.h" + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Base address of device (IPIF) */ +} XDmaPs_Config; + + +/** DMA channle control structure. It's for AXI bus transaction. + * This struct will be translated into a 32-bit channel control register value. + */ +typedef struct { + unsigned int EndianSwapSize; /**< Endian swap size. */ + unsigned int DstCacheCtrl; /**< Destination cache control */ + unsigned int DstProtCtrl; /**< Destination protection control */ + unsigned int DstBurstLen; /**< Destination burst length */ + unsigned int DstBurstSize; /**< Destination burst size */ + unsigned int DstInc; /**< Destination incrementing or fixed + * address */ + unsigned int SrcCacheCtrl; /**< Source cache control */ + unsigned int SrcProtCtrl; /**< Source protection control */ + unsigned int SrcBurstLen; /**< Source burst length */ + unsigned int SrcBurstSize; /**< Source burst size */ + unsigned int SrcInc; /**< Source incrementing or fixed + * address */ +} XDmaPs_ChanCtrl; + +/** DMA block descriptor stucture. + */ +typedef struct { + u32 SrcAddr; /**< Source starting address */ + u32 DstAddr; /**< Destination starting address */ + unsigned int Length; /**< Number of bytes for the block */ +} XDmaPs_BD; + +/** + * A DMA command consisits of a channel control struct, a block descriptor, + * a user defined program, a pointer pointing to generated DMA program, and + * execution result. + * + */ +typedef struct { + XDmaPs_ChanCtrl ChanCtrl; /**< Channel Control Struct */ + XDmaPs_BD BD; /**< Together with SgLength field, + * it's a scatter-gather list. + */ + void *UserDmaProg; /**< If user wants the driver to + * execute their own DMA program, + * this field points to the DMA + * program. + */ + int UserDmaProgLength; /**< The length of user defined + * DMA program. + */ + + void *GeneratedDmaProg; /**< The DMA program genreated + * by the driver. This field will be + * set if a user invokes the DMA + * program generation function. Or + * the DMA command is finished and + * a user informs the driver not to + * release the program buffer. + * This field has two purposes, one + * is to ask the driver to generate + * a DMA program while the DMAC is + * performaning DMA transactions. The + * other purpose is to debug the + * driver. + */ + int GeneratedDmaProgLength; /**< The length of the DMA program + * generated by the driver + */ + int DmaStatus; /**< 0 on success, otherwise error code + */ + u32 ChanFaultType; /**< Channel fault type in case of fault + */ + u32 ChanFaultPCAddr; /**< Channel fault PC address + */ +} XDmaPs_Cmd; + +/** + * It's the done handler a user can set for a channel + */ +typedef void (*XDmaPsDoneHandler) (unsigned int Channel, + XDmaPs_Cmd *DmaCmd, + void *CallbackRef); + +/** + * It's the fault handler a user can set for a channel + */ +typedef void (*XDmaPsFaultHandler) (unsigned int Channel, + XDmaPs_Cmd *DmaCmd, + void *CallbackRef); + +#define XDMAPS_MAX_CHAN_BUFS 2 +#define XDMAPS_CHAN_BUF_LEN 128 + +/** + * The XDmaPs_ProgBuf is the struct for a DMA program buffer. + */ +typedef struct { + char Buf[XDMAPS_CHAN_BUF_LEN]; /**< The actual buffer the holds the + * content */ + unsigned Len; /**< The actual length of the DMA + * program in bytes. */ + int Allocated; /**< A tag indicating whether the + * buffer is allocated or not */ +} XDmaPs_ProgBuf; + +/** + * The XDmaPs_ChannelData is a struct to book keep individual channel of + * the DMAC. + */ +typedef struct { + unsigned DevId; /**< Device id indicating which DMAC */ + unsigned ChanId; /**< Channel number of the DMAC */ + XDmaPs_ProgBuf ProgBufPool[XDMAPS_MAX_CHAN_BUFS]; /**< A pool of + program buffers*/ + XDmaPsDoneHandler DoneHandler; /**< Done interrupt handler */ + void *DoneRef; /**< Done interrupt callback data */ + XDmaPs_Cmd *DmaCmdToHw; /**< DMA command being executed */ + XDmaPs_Cmd *DmaCmdFromHw; /**< DMA command that is finished. + * This field is for debugging purpose + */ + int HoldDmaProg; /**< A tag indicating whether to hold the + * DMA program after the DMA is done. + */ + +} XDmaPs_ChannelData; + +/** + * The XDmaPs driver instance data structure. A pointer to an instance data + * structure is passed around by functions to refer to a specific driver + * instance. + */ +typedef struct { + XDmaPs_Config Config; /**< Configuration data structure */ + int IsReady; /**< Device is Ready */ + int CacheLength; /**< icache length */ + XDmaPsFaultHandler FaultHandler; /**< fault interrupt handler */ + void *FaultRef; /**< fault call back data */ + XDmaPs_ChannelData Chans[XDMAPS_CHANNELS_PER_DEV]; + /**< + * channel data + */ +} XDmaPs; + +/* + * Functions implemented in xdmaps.c + */ +int XDmaPs_CfgInitialize(XDmaPs *InstPtr, + XDmaPs_Config *Config, + u32 EffectiveAddr); + +int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel, + XDmaPs_Cmd *Cmd, + int HoldDmaProg); + +int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel); +int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel, + XDmaPs_Cmd *Cmd); +int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel, + XDmaPs_Cmd *Cmd); +void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd); + + +int XDmaPs_ResetManager(XDmaPs *InstPtr); +int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel); + + +int XDmaPs_SetDoneHandler(XDmaPs *InstPtr, + unsigned Channel, + XDmaPsDoneHandler DoneHandler, + void *CallbackRef); + +int XDmaPs_SetFaultHandler(XDmaPs *InstPtr, + XDmaPsFaultHandler FaultHandler, + void *CallbackRef); + +void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd); + +/** + * Driver done interrupt service routines for the channels. + * We need this done ISR mainly because the driver needs to release the + * DMA program buffer. This is the one that connects the GIC + */ +void XDmaPs_DoneISR_0(XDmaPs *InstPtr); +void XDmaPs_DoneISR_1(XDmaPs *InstPtr); +void XDmaPs_DoneISR_2(XDmaPs *InstPtr); +void XDmaPs_DoneISR_3(XDmaPs *InstPtr); +void XDmaPs_DoneISR_4(XDmaPs *InstPtr); +void XDmaPs_DoneISR_5(XDmaPs *InstPtr); +void XDmaPs_DoneISR_6(XDmaPs *InstPtr); +void XDmaPs_DoneISR_7(XDmaPs *InstPtr); + +/** + * Driver fault interrupt service routine + */ +void XDmaPs_FaultISR(XDmaPs *InstPtr); + + +/* + * Static loopup function implemented in xdmaps_sinit.c + */ +XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId); + + +/* + * self-test functions in xdmaps_selftest.c + */ +int XDmaPs_SelfTest(XDmaPs *InstPtr); + + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xdmaps_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xdmaps_hw.h new file mode 100644 index 000000000..1fc33e547 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xdmaps_hw.h @@ -0,0 +1,299 @@ +/****************************************************************************** +* +* (c) Copyright 2009-2013 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xdmaps_hw.h +* +* This header file contains the hardware interface of an XDmaPs device. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who   Date     Changes
+* ----- ----  -------- ----------------------------------------------
+* 1.00a	hbm   08/18/10 First Release
+* 1.01a nm    12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
+*		       the maximum number of channels.
+*		       Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
+*                      with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h
+* 1.02a sg    05/16/12 Made changes for doxygen
+* 1.06a kpc   07/10/13 Added function prototype
+*
+* +******************************************************************************/ + +#ifndef XDMAPS_HW_H /* prevent circular inclusions */ +#define XDMAPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * + * Register offsets for the DMAC. + * @{ + */ + +#define XDMAPS_DS_OFFSET 0x000 /* DMA Status Register */ +#define XDMAPS_DPC_OFFSET 0x004 /* DMA Program Counter Rregister */ +#define XDMAPS_INTEN_OFFSET 0X020 /* DMA Interrupt Enable Register */ +#define XDMAPS_ES_OFFSET 0x024 /* DMA Event Status Register */ +#define XDMAPS_INTSTATUS_OFFSET 0x028 /* DMA Interrupt Status Register + */ +#define XDMAPS_INTCLR_OFFSET 0x02c /* DMA Interrupt Clear Register */ +#define XDMAPS_FSM_OFFSET 0x030 /* DMA Fault Status DMA Manager + * Register + */ +#define XDMAPS_FSC_OFFSET 0x034 /* DMA Fault Status DMA Chanel Register + */ +#define XDMAPS_FTM_OFFSET 0x038 /* DMA Fault Type DMA Manager Register */ + +#define XDMAPS_FTC0_OFFSET 0x040 /* DMA Fault Type for DMA Channel 0 */ +/* + * The offset for the rest of the FTC registers is calculated as + * FTC0 + dev_chan_num * 4 + */ +#define XDmaPs_FTCn_OFFSET(ch) (XDMAPS_FTC0_OFFSET + (ch) * 4) + +#define XDMAPS_CS0_OFFSET 0x100 /* Channel Status for DMA Channel 0 */ +/* + * The offset for the rest of the CS registers is calculated as + * CS0 + * dev_chan_num * 0x08 + */ +#define XDmaPs_CSn_OFFSET(ch) (XDMAPS_CS0_OFFSET + (ch) * 8) + +#define XDMAPS_CPC0_OFFSET 0x104 /* Channel Program Counter for DMA + * Channel 0 + */ +/* + * The offset for the rest of the CPC registers is calculated as + * CPC0 + dev_chan_num * 0x08 + */ +#define XDmaPs_CPCn_OFFSET(ch) (XDMAPS_CPC0_OFFSET + (ch) * 8) + +#define XDMAPS_SA_0_OFFSET 0x400 /* Source Address Register for DMA + * Channel 0 + */ +/* The offset for the rest of the SA registers is calculated as + * SA_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_SA_n_OFFSET(ch) (XDMAPS_SA_0_OFFSET + (ch) * 0x20) + +#define XDMAPS_DA_0_OFFSET 0x404 /* Destination Address Register for + * DMA Channel 0 + */ +/* The offset for the rest of the DA registers is calculated as + * DA_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_DA_n_OFFSET(ch) (XDMAPS_DA_0_OFFSET + (ch) * 0x20) + +#define XDMAPS_CC_0_OFFSET 0x408 /* Channel Control Register for + * DMA Channel 0 + */ +/* + * The offset for the rest of the CC registers is calculated as + * CC_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_CC_n_OFFSET(ch) (XDMAPS_CC_0_OFFSET + (ch) * 0x20) + +#define XDMAPS_LC0_0_OFFSET 0x40C /* Loop Counter 0 for DMA Channel 0 */ +/* + * The offset for the rest of the LC0 registers is calculated as + * LC_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_LC0_n_OFFSET(ch) (XDMAPS_LC0_0_OFFSET + (ch) * 0x20) +#define XDMAPS_LC1_0_OFFSET 0x410 /* Loop Counter 1 for DMA Channel 0 */ +/* + * The offset for the rest of the LC1 registers is calculated as + * LC_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_LC1_n_OFFSET(ch) (XDMAPS_LC1_0_OFFSET + (ch) * 0x20) + +#define XDMAPS_DBGSTATUS_OFFSET 0xD00 /* Debug Status Register */ +#define XDMAPS_DBGCMD_OFFSET 0xD04 /* Debug Command Register */ +#define XDMAPS_DBGINST0_OFFSET 0xD08 /* Debug Instruction 0 Register */ +#define XDMAPS_DBGINST1_OFFSET 0xD0C /* Debug Instruction 1 Register */ + +#define XDMAPS_CR0_OFFSET 0xE00 /* Configuration Register 0 */ +#define XDMAPS_CR1_OFFSET 0xE04 /* Configuration Register 1 */ +#define XDMAPS_CR2_OFFSET 0xE08 /* Configuration Register 2 */ +#define XDMAPS_CR3_OFFSET 0xE0C /* Configuration Register 3 */ +#define XDMAPS_CR4_OFFSET 0xE10 /* Configuration Register 4 */ +#define XDMAPS_CRDN_OFFSET 0xE14 /* Configuration Register Dn */ + +#define XDMAPS_PERIPH_ID_0_OFFSET 0xFE0 /* Peripheral Identification + * Register 0 + */ +#define XDMAPS_PERIPH_ID_1_OFFSET 0xFE4 /* Peripheral Identification + * Register 1 + */ +#define XDMAPS_PERIPH_ID_2_OFFSET 0xFE8 /* Peripheral Identification + * Register 2 + */ +#define XDMAPS_PERIPH_ID_3_OFFSET 0xFEC /* Peripheral Identification + * Register 3 + */ +#define XDMAPS_PCELL_ID_0_OFFSET 0xFF0 /* PrimeCell Identification + * Register 0 + */ +#define XDMAPS_PCELL_ID_1_OFFSET 0xFF4 /* PrimeCell Identification + * Register 1 + */ +#define XDMAPS_PCELL_ID_2_OFFSET 0xFF8 /* PrimeCell Identification + * Register 2 + */ +#define XDMAPS_PCELL_ID_3_OFFSET 0xFFC /* PrimeCell Identification + * Register 3 + */ + +/* + * Some useful register masks + */ +#define XDMAPS_DS_DMA_STATUS 0x0F /* DMA status mask */ +#define XDMAPS_DS_DMA_STATUS_STOPPED 0x00 /* debug status busy mask */ + +#define XDMAPS_DBGSTATUS_BUSY 0x01 /* debug status busy mask */ + +#define XDMAPS_CS_ACTIVE_MASK 0x07 /* channel status active mask, + * llast 3 bits of CS register + */ + +#define XDMAPS_CR1_I_CACHE_LEN_MASK 0x07 /* i_cache_len mask */ + + +/* + * XDMAPS_DBGINST0 - constructs the word for the Debug Instruction-0 Register. + * @b1: Instruction byte 1 + * @b0: Instruction byte 0 + * @ch: Channel number + * @dbg_th: Debug thread encoding: 0 = DMA manager thread, 1 = DMA channel + */ +#define XDmaPs_DBGINST0(b1, b0, ch, dbg_th) \ + (((b1) << 24) | ((b0) << 16) | (((ch) & 0x7) << 8) | ((dbg_th & 0x1))) + +/* @} */ + +/** @name Control Register + * + * The Control register (CR) controls the major functions of the device. + * + * Control Register Bit Definition + */ + +/* @}*/ + + +#define XDMAPS_CHANNELS_PER_DEV 8 + + +/** @name Mode Register + * + * The mode register (MR) defines the mode of transfer as well as the data + * format. If this register is modified during transmission or reception, + * data validity cannot be guaranteed. + * + * Mode Register Bit Definition + * @{ + */ + +/* @} */ + + +/** @name Interrupt Registers + * + * Interrupt control logic uses the interrupt enable register (IER) and the + * interrupt disable register (IDR) to set the value of the bits in the + * interrupt mask register (IMR). The IMR determines whether to pass an + * interrupt to the interrupt status register (ISR). + * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an + * interrupt. IMR and ISR are read only, and IER and IDR are write only. + * Reading either IER or IDR returns 0x00. + * + * All four registers have the same bit definitions. + * + * @{ + */ + +/* @} */ +#define XDMAPS_INTCLR_ALL_MASK 0xFF + +#define XDmaPs_ReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (RegOffset)) + +/***************************************************************************/ +/** +* Write a DMAC register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the base address of the device. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note +* C-Style signature: +* void XDmaPs_WriteReg(u32 BaseAddress, int RegOffset, +* u32 RegisterValue) +******************************************************************************/ +#define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ + Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue)) +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes *****************************/ +/* + * Perform reset operation to the dmaps interface + */ +void XDmaPs_ResetHw(u32 BaseAddr); +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xemacps.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xemacps.h new file mode 100644 index 000000000..643ba2cf6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xemacps.h @@ -0,0 +1,721 @@ +/***************************************************************************** +* +* (c) Copyright 2010-11 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +*****************************************************************************/ +/****************************************************************************/ +/** + * + * @file xemacps.h + * + * The Xilinx Embedded Processor Block Ethernet driver. + * + * For a full description of XEMACPS features, please see the hardware spec. + * This driver supports the following features: + * - Memory mapped access to host interface registers + * - Statistics counter registers for RMON/MIB + * - API for interrupt driven frame transfers for hardware configured DMA + * - Virtual memory support + * - Unicast, broadcast, and multicast receive address filtering + * - Full and half duplex operation + * - Automatic PAD & FCS insertion and stripping + * - Flow control + * - Support up to four 48bit addresses + * - Address checking for four specific 48bit addresses + * - VLAN frame support + * - Pause frame support + * - Large frame support up to 1536 bytes + * - Checksum offload + * + * Driver Description + * + * The device driver enables higher layer software (e.g., an application) to + * communicate to the XEmacPs. The driver handles transmission and reception + * of Ethernet frames, as well as configuration and control. No pre or post + * processing of frame data is performed. The driver does not validate the + * contents of an incoming frame in addition to what has already occurred in + * hardware. + * A single device driver can support multiple devices even when those devices + * have significantly different configurations. + * + * Initialization & Configuration + * + * The XEmacPs_Config structure is used by the driver to configure itself. + * This configuration structure is typically created by the tool-chain based + * on hardware build properties. + * + * The driver instance can be initialized in + * + * - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a + * configuration structure provided by the caller. If running in a system + * with address translation, the provided virtual memory base address + * replaces the physical address present in the configuration structure. + * + * The device supports DMA only as current development plan. No FIFO mode is + * supported. The driver expects to start the DMA channels and expects that + * the user has set up the buffer descriptor lists. + * + * Interrupts and Asynchronous Callbacks + * + * The driver has no dependencies on the interrupt controller. When an + * interrupt occurs, the handler will perform a small amount of + * housekeeping work, determine the source of the interrupt, and call the + * appropriate callback function. All callbacks are registered by the user + * level application. + * + * Virtual Memory + * + * All virtual to physical memory mappings must occur prior to accessing the + * driver API. + * + * For DMA transactions, user buffers supplied to the driver must be in terms + * of their physical address. + * + * DMA + * + * The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames. + * These BDs are typically chained together into a list the hardware follows + * when transferring data in and out of the packet buffers. Each BD describes + * a memory region containing either a full or partial Ethernet packet. + * + * Interrupt coalescing is not suppoted from this built-in DMA engine. + * + * This API requires the user to understand how the DMA operates. The + * following paragraphs provide some explanation, but the user is encouraged + * to read documentation in xemacps_bdring.h as well as study example code + * that accompanies this driver. + * + * The API is designed to get BDs to and from the DMA engine in the most + * efficient means possible. The first step is to establish a memory region + * to contain all BDs for a specific channel. This is done with + * XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will + * follow as BDs are processed. The ring will consist of a user defined number + * of BDs which will all be partially initialized. For example on the transmit + * channel, the driver will initialize all BDs' so that they are configured + * for transmit. The more fields that can be permanently setup at + * initialization, then the fewer accesses will be needed to each BD while + * the DMA engine is in operation resulting in better throughput and CPU + * utilization. The best case initialization would require the user to set + * only a frame buffer address and length prior to submitting the BD to the + * engine. + * + * BDs move through the engine with the help of functions + * XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(), + * and XEmacPs_BdRingFree(). + * All these functions handle BDs that are in place. That is, there are no + * copies of BDs kept anywhere and any BD the user interacts with is an actual + * BD from the same ring hardware accesses. + * + * BDs in the ring go through a series of states as follows: + * 1. Idle. The driver controls BDs in this state. + * 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to + * reserve BD(s). Once allocated, the user may setup the BD(s) with + * frame buffer address, length, and other attributes. The user controls + * BDs in this state. + * 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs + * in this state are either waiting to be processed by hardware, are in + * process, or have been processed. The DMA engine controls BDs in this + * state. + * 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the + * user. Once retrieved, the user can examine each BD for the outcome of + * the DMA transfer. The user controls BDs in this state. After examining + * the BDs the user calls XEmacPs_BdRingFree() which places the BDs back + * into state 1. + * + * Each of the four BD accessor functions operate on a set of BDs. A set is + * defined as a segment of the BD ring consisting of one or more BDs. The user + * views the set as a pointer to the first BD along with the number of BDs for + * that set. The set can be navigated by using macros XEmacPs_BdNext(). The + * user must exercise extreme caution when changing BDs in a set as there is + * nothing to prevent doing a mBdNext past the end of the set and modifying a + * BD out of bounds. + * + * XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as + * XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in + * tandem. The same BD set retrieved with BdRingAlloc should be the same one + * provided to hardware with BdRingToHw. Same goes with BdRingFromHw and + * BdRIngFree. + * + * Alignment & Data Cache Restrictions + * + * Due to the design of the hardware, all RX buffers, BDs need to be 4-byte + * aligned. Please reference xemacps_bd.h for cache related macros. + * + * DMA Tx: + * + * - If frame buffers exist in cached memory, then they must be flushed + * prior to committing them to hardware. + * + * DMA Rx: + * + * - If frame buffers exist in cached memory, then the cache must be + * invalidated for the memory region containing the frame prior to data + * access + * + * Both cache invalidate/flush are taken care of in driver code. + * + * Buffer Copying + * + * The driver is designed for a zero-copy buffer scheme. That is, the driver + * will not copy buffers. This avoids potential throughput bottlenecks within + * the driver. If byte copying is required, then the transfer will take longer + * to complete. + * + * Checksum Offloading + * + * The Embedded Processor Block Ethernet can be configured to perform IP, TCP + * and UDP checksum offloading in both receive and transmit directions. + * + * IP packets contain a 16-bit checksum field, which is the 16-bit 1s + * complement of the 1s complement sum of all 16-bit words in the header. + * TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit + * 1s complement of the 1s complement sum of all 16-bit words in the header, + * the data and a conceptual pseudo header. + * + * To calculate these checksums in software requires each byte of the packet + * to be read. For TCP and UDP this can use a large amount of processing power. + * Offloading the checksum calculation to hardware can result in significant + * performance improvements. + * + * The transmit checksum offload is only available to use DMA in packet buffer + * mode. This is because the complete frame to be transmitted must be read + * into the packet buffer memory before the checksum can be calculated and + * written to the header at the beginning of the frame. + * + * For IP, TCP or UDP receive checksum offload to be useful, the operating + * system containing the protocol stack must be aware that this offload is + * available so that it can make use of the fact that the hardware has verified + * the checksum. + * + * When receive checksum offloading is enabled in the hardware, the IP header + * checksum is checked, where the packet meets the following criteria: + * + * 1. If present, the VLAN header must be four octets long and the CFI bit + * must not be set. + * 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP + * encoding. + * 3. IP v4 packet. + * 4. IP header is of a valid length. + * 5. Good IP header checksum. + * 6. No IP fragmentation. + * 7. TCP or UDP packet. + * + * When an IP, TCP or UDP frame is received, the receive buffer descriptor + * gives an indication if the hardware was able to verify the checksums. + * There is also an indication if the frame had SNAP encapsulation. These + * indication bits will replace the type ID match indication bits when the + * receive checksum offload is enabled. + * + * If any of the checksums are verified incorrect by the hardware, the packet + * is discarded and the appropriate statistics counter incremented. + * + * PHY Interfaces + * + * RGMII 1.3 is the only interface supported. + * + * Asserts + * + * Asserts are used within all Xilinx drivers to enforce constraints on + * parameters. Asserts can be turned off on a system-wide basis by defining, + * at compile time, the NDEBUG identifier. By default, asserts are turned on + * and it is recommended that users leave asserts on during development. For + * deployment use -DNDEBUG compiler switch to remove assert code. + * + * @note + * + * Xilinx drivers are typically composed of two parts, one is the driver + * and the other is the adapter. The driver is independent of OS and processor + * and is intended to be highly portable. The adapter is OS-specific and + * facilitates communication between the driver and an OS. + * This driver is intended to be RTOS and processor independent. Any needs for + * dynamic memory management, threads or thread mutual exclusion, or cache + * control must be satisfied bythe layer above this driver. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy  01/10/10 First release
+ * 1.00a asa  11/21/11 The function XEmacPs_BdRingFromHwTx in file
+ *		       xemacps_bdring.c is modified. Earlier it was checking for
+ *		       "BdLimit"(passed argument) number of BDs for finding out
+ *		       which BDs are successfully processed. Now one more check
+ *		       is added. It looks for BDs till the current BD pointer
+ *		       reaches HwTail. By doing this processing time is saved.
+ * 1.00a asa  01/24/12 The function XEmacPs_BdRingFromHwTx in file
+ *		       xemacps_bdring.c is modified. Now start of packet is
+ *		       searched for returning the number of BDs processed.
+ * 1.02a asa  11/05/12 Added a new API for deleting an entry from the HASH
+ *		       registers. Added a new API to set the bust length.
+ *		       Added some new hash-defines.
+ * 1.03a asa  01/23/12 Fix for CR #692702 which updates error handling for
+ *		       Rx errors. Under heavy Rx traffic, there will be a large
+ *		       number of errors related to receive buffer not available.
+ *		       Because of a HW bug (SI #692601), under such heavy errors,
+ *		       the Rx data path can become unresponsive. To reduce the
+ *		       probabilities for hitting this HW bug, the SW writes to
+ *		       bit 18 to flush a packet from Rx DPRAM immediately. The
+ *		       changes for it are done in the function
+ *		       XEmacPs_IntrHandler.
+ * 1.05a asa  09/23/13 Cache operations on BDs are not required and hence
+ *		       removed. It is expected that all BDs are allocated in
+ *		       from uncached area.
+ * 1.06a asa  11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+ *				to 0x1fff. This fixes the CR#744902.
+ *			  Made changes in example file xemacps_example.h to fix compilation
+ *			  issues with iarcc compiler.
+ * 2.0   adk  10/12/13 Updated as per the New Tcl API's
+ *
+ * + ****************************************************************************/ + +#ifndef XEMACPS_H /* prevent circular inclusions */ +#define XEMACPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xemacps_hw.h" +#include "xemacps_bd.h" +#include "xemacps_bdring.h" + +/************************** Constant Definitions ****************************/ + +/* + * Device information + */ +#define XEMACPS_DEVICE_NAME "xemacps" +#define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC" + + +/** @name Configuration options + * + * Device configuration options. See the XEmacPs_SetOptions(), + * XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to + * use options. + * + * The default state of the options are noted and are what the device and + * driver will be set to after calling XEmacPs_Reset() or + * XEmacPs_Initialize(). + * + * @{ + */ + +#define XEMACPS_PROMISC_OPTION 0x00000001 +/**< Accept all incoming packets. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_FRAME1536_OPTION 0x00000002 +/**< Frame larger than 1516 support for Tx & Rx. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_VLAN_OPTION 0x00000004 +/**< VLAN Rx & Tx frame support. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010 +/**< Enable recognition of flow control frames on Rx + * This option defaults to enabled (set) */ + +#define XEMACPS_FCS_STRIP_OPTION 0x00000020 +/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not + * stripped. + * This option defaults to enabled (set) */ + +#define XEMACPS_FCS_INSERT_OPTION 0x00000040 +/**< Generate FCS field and add PAD automatically for outgoing frames. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080 +/**< Enable Length/Type error checking for incoming frames. When this option is + * set, the MAC will filter frames that have a mismatched type/length field + * and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these + * types of frames are encountered. When this option is cleared, the MAC will + * allow these types of frames to be received. + * + * This option defaults to disabled (cleared) */ + +#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100 +/**< Enable the transmitter. + * This option defaults to enabled (set) */ + +#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200 +/**< Enable the receiver + * This option defaults to enabled (set) */ + +#define XEMACPS_BROADCAST_OPTION 0x00000400 +/**< Allow reception of the broadcast address + * This option defaults to enabled (set) */ + +#define XEMACPS_MULTICAST_OPTION 0x00000800 +/**< Allows reception of multicast addresses programmed into hash + * This option defaults to disabled (clear) */ + +#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000 +/**< Enable the RX checksum offload + * This option defaults to enabled (set) */ + +#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000 +/**< Enable the TX checksum offload + * This option defaults to enabled (set) */ + + +#define XEMACPS_DEFAULT_OPTIONS \ + (XEMACPS_FLOW_CONTROL_OPTION | \ + XEMACPS_FCS_INSERT_OPTION | \ + XEMACPS_FCS_STRIP_OPTION | \ + XEMACPS_BROADCAST_OPTION | \ + XEMACPS_LENTYPE_ERR_OPTION | \ + XEMACPS_TRANSMITTER_ENABLE_OPTION | \ + XEMACPS_RECEIVER_ENABLE_OPTION | \ + XEMACPS_RX_CHKSUM_ENABLE_OPTION | \ + XEMACPS_TX_CHKSUM_ENABLE_OPTION) + +/**< Default options set when device is initialized or reset */ +/*@}*/ + +/** @name Callback identifiers + * + * These constants are used as parameters to XEmacPs_SetHandler() + * @{ + */ +#define XEMACPS_HANDLER_DMASEND 1 +#define XEMACPS_HANDLER_DMARECV 2 +#define XEMACPS_HANDLER_ERROR 3 +/*@}*/ + +/* Constants to determine the configuration of the hardware device. They are + * used to allow the driver to verify it can operate with the hardware. + */ +#define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */ + +/* The next few constants help upper layers determine the size of memory + * pools used for Ethernet buffers and descriptor lists. + */ +#define XEMACPS_MAC_ADDR_SIZE 6 /* size of Ethernet header */ + +#define XEMACPS_MTU 1500 /* max MTU size of Ethernet frame */ +#define XEMACPS_HDR_SIZE 14 /* size of Ethernet header */ +#define XEMACPS_HDR_VLAN_SIZE 18 /* size of Ethernet header with VLAN */ +#define XEMACPS_TRL_SIZE 4 /* size of Ethernet trailer (FCS) */ +#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \ + XEMACPS_TRL_SIZE) +#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \ + XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE) + +/* DMACR Bust length hash defines */ + +#define XEMACPS_SINGLE_BURST 1 +#define XEMACPS_4BYTE_BURST 4 +#define XEMACPS_8BYTE_BURST 8 +#define XEMACPS_16BYTE_BURST 16 + + +/**************************** Type Definitions ******************************/ +/** @name Typedefs for callback functions + * + * These callbacks are invoked in interrupt context. + * @{ + */ +/** + * Callback invoked when frame(s) have been sent or received in interrupt + * driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler(). + * + * @param CallBackRef is user data assigned when the callback was set. + * + * @note + * See xemacps_hw.h for bitmasks definitions and the device hardware spec for + * further information on their meaning. + * + */ +typedef void (*XEmacPs_Handler) (void *CallBackRef); + +/** + * Callback when an asynchronous error occurs. To set this callback, invoke + * XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType + * paramter. + * + * @param CallBackRef is user data assigned when the callback was set. + * @param Direction defines either receive or transmit error(s) has occurred. + * @param ErrorWord definition varies with Direction + * + */ +typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction, + u32 ErrorWord); + +/*@}*/ + +/** + * This typedef contains configuration information for a device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress;/**< Physical base address of IPIF registers */ +} XEmacPs_Config; + + +/** + * The XEmacPs driver instance data. The user is required to allocate a + * structure of this type for every XEmacPs device in the system. A pointer + * to a structure of this type is then passed to the driver API functions. + */ +typedef struct XEmacPs { + XEmacPs_Config Config; /* Hardware configuration */ + u32 IsStarted; /* Device is currently started */ + u32 IsReady; /* Device is initialized and ready */ + u32 Options; /* Current options word */ + + XEmacPs_BdRing TxBdRing; /* Transmit BD ring */ + XEmacPs_BdRing RxBdRing; /* Receive BD ring */ + + XEmacPs_Handler SendHandler; + XEmacPs_Handler RecvHandler; + void *SendRef; + void *RecvRef; + + XEmacPs_ErrHandler ErrorHandler; + void *ErrorRef; + +} XEmacPs; + + +/***************** Macros (Inline Functions) Definitions ********************/ + +/****************************************************************************/ +/** +* Retrieve the Tx ring object. This object can be used in the various Ring +* API functions. +* +* @param InstancePtr is the DMA channel to operate on. +* +* @return TxBdRing attribute +* +* @note +* C-style signature: +* XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing) + +/****************************************************************************/ +/** +* Retrieve the Rx ring object. This object can be used in the various Ring +* API functions. +* +* @param InstancePtr is the DMA channel to operate on. +* +* @return RxBdRing attribute +* +* @note +* C-style signature: +* XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing) + +/****************************************************************************/ +/** +* +* Enable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to enable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntEnable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_IER_OFFSET, \ + (Mask & XEMACPS_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* Disable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to disable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntDisable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_IDR_OFFSET, \ + (Mask & XEMACPS_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* This macro triggers trasmit circuit to send data currently in TX buffer(s). +* +* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. +* +* @return +* +* @note +* +* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_Transmit(InstancePtr) \ + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, \ + XEMACPS_NWCTRL_OFFSET, \ + (XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, \ + XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK)) + +/****************************************************************************/ +/** +* +* This macro determines if the device is configured with checksum offloading +* on the receive channel +* +* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. +* +* @return +* +* Boolean TRUE if the device is configured with checksum offloading, or +* FALSE otherwise. +* +* @note +* +* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_IsRxCsum(InstancePtr) \ + ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) \ + ? TRUE : FALSE) + +/****************************************************************************/ +/** +* +* This macro determines if the device is configured with checksum offloading +* on the transmit channel +* +* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. +* +* @return +* +* Boolean TRUE if the device is configured with checksum offloading, or +* FALSE otherwise. +* +* @note +* +* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_IsTxCsum(InstancePtr) \ + ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) \ + ? TRUE : FALSE) + +/************************** Function Prototypes *****************************/ + +/* + * Initialization functions in xemacps.c + */ +int XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr, + u32 EffectiveAddress); +void XEmacPs_Start(XEmacPs *InstancePtr); +void XEmacPs_Stop(XEmacPs *InstancePtr); +void XEmacPs_Reset(XEmacPs *InstancePtr); + +/* + * Lookup configuration in xemacps_sinit.c + */ +XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId); + +/* + * Interrupt-related functions in xemacps_intr.c + * DMA only and FIFO is not supported. This DMA does not support coalescing. + */ +int XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType, + void *FuncPtr, void *CallBackRef); +void XEmacPs_IntrHandler(void *InstancePtr); + +/* + * MAC configuration/control functions in XEmacPs_control.c + */ +int XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options); +int XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options); +u32 XEmacPs_GetOptions(XEmacPs *InstancePtr); + +int XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index); +void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index); + +int XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr); +void XEmacPs_ClearHash(XEmacPs *InstancePtr); +void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr); + +void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, + XEmacPs_MdcDiv Divisor); +void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed); +u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr); +int XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress, + u32 RegisterNum, u16 *PhyDataPtr); +int XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress, + u32 RegisterNum, u16 PhyData); +int XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index); + +int XEmacPs_SendPausePacket(XEmacPs *InstancePtr); +void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, int BLength); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xemacps_bd.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xemacps_bd.h new file mode 100644 index 000000000..8bf33cfa5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xemacps_bd.h @@ -0,0 +1,737 @@ +/* $Id: xemacps_bd.h,v 1.1.2.1 2011/01/20 03:39:02 sadanan Exp $ */ +/****************************************************************************** +* +* (c) Copyright 2010 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** + * + * @file xemacps_bd.h + * + * This header provides operations to manage buffer descriptors in support + * of scatter-gather DMA. + * + * The API exported by this header defines abstracted macros that allow the + * user to read/write specific BD fields. + * + * Buffer Descriptors + * + * A buffer descriptor (BD) defines a DMA transaction. The macros defined by + * this header file allow access to most fields within a BD to tailor a DMA + * transaction according to user and hardware requirements. See the hardware + * IP DMA spec for more information on BD fields and how they affect transfers. + * + * The XEmacPs_Bd structure defines a BD. The organization of this structure + * is driven mainly by the hardware for use in scatter-gather DMA transfers. + * + * Performance + * + * Limiting I/O to BDs can improve overall performance of the DMA channel. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy  01/10/10 First release
+ *
+ * + * *************************************************************************** + */ + +#ifndef XEMACPS_BD_H /* prevent circular inclusions */ +#define XEMACPS_BD_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include +#include "xil_types.h" +#include "xil_assert.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/* Minimum BD alignment */ +#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4 + +/** + * The XEmacPs_Bd is the type for buffer descriptors (BDs). + */ +#define XEMACPS_BD_NUM_WORDS 2 +typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS]; + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** + * Zero out BD fields + * + * @param BdPtr is the BD pointer to operate on + * + * @return Nothing + * + * @note + * C-style signature: + * void XEmacPs_BdClear(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClear(BdPtr) \ + memset((BdPtr), 0, sizeof(XEmacPs_Bd)) + +/****************************************************************************/ +/** +* +* Read the given Buffer Descriptor word. +* +* @param BaseAddress is the base address of the BD to read +* @param Offset is the word offset to be read +* +* @return The 32-bit value of the field +* +* @note +* C-style signature: +* u32 XEmacPs_BdRead(u32 BaseAddress, u32 Offset) +* +*****************************************************************************/ +#define XEmacPs_BdRead(BaseAddress, Offset) \ + (*(u32*)((u32)(BaseAddress) + (u32)(Offset))) + +/****************************************************************************/ +/** +* +* Write the given Buffer Descriptor word. +* +* @param BaseAddress is the base address of the BD to write +* @param Offset is the word offset to be written +* @param Data is the 32-bit value to write to the field +* +* @return None. +* +* @note +* C-style signature: +* void XEmacPs_BdWrite(u32 BaseAddress, u32 Offset, u32 Data) +* +*****************************************************************************/ +#define XEmacPs_BdWrite(BaseAddress, Offset, Data) \ + (*(u32*)((u32)(BaseAddress) + (u32)(Offset)) = (Data)) + +/*****************************************************************************/ +/** + * Set the BD's Address field (word 0). + * + * @param BdPtr is the BD pointer to operate on + * @param Addr is the value to write to BD's status field. + * + * @note : + * + * C-style signature: + * void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, u32 Addr) + * + *****************************************************************************/ +#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr))) + + +/*****************************************************************************/ +/** + * Set the BD's Address field (word 0). + * + * @param BdPtr is the BD pointer to operate on + * @param Addr is the value to write to BD's status field. + * + * @note : Due to some bits are mixed within recevie BD's address field, + * read-modify-write is performed. + * + * C-style signature: + * void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, u32 Addr) + * + *****************************************************************************/ +#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + ~XEMACPS_RXBUF_ADD_MASK) | (u32)(Addr))) + + +/*****************************************************************************/ +/** + * Set the BD's Status field (word 1). + * + * @param BdPtr is the BD pointer to operate on + * @param Data is the value to write to BD's status field. + * + * @note + * C-style signature: + * void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, u32 Data) + * + *****************************************************************************/ +#define XEmacPs_BdSetStatus(BdPtr, Data) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | Data) + + +/*****************************************************************************/ +/** + * Retrieve the BD's Packet DMA transfer status word (word 1). + * + * @param BdPtr is the BD pointer to operate on + * + * @return Status word + * + * @note + * C-style signature: + * u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr) + * + * Due to the BD bit layout differences in transmit and receive. User's + * caution is required. + *****************************************************************************/ +#define XEmacPs_BdGetStatus(BdPtr) \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) + + +/*****************************************************************************/ +/** + * Get the address (bits 0..31) of the BD's buffer address (word 0) + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u32 XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdGetBufAddr(BdPtr) \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET)) + + +/*****************************************************************************/ +/** + * Set transfer length in bytes for the given BD. The length must be set each + * time a BD is submitted to hardware. + * + * @param BdPtr is the BD pointer to operate on + * @param LenBytes is the number of bytes to transfer. + * + * @note + * C-style signature: + * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes) + * + *****************************************************************************/ +#define XEmacPs_BdSetLength(BdPtr, LenBytes) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes))) + + +/*****************************************************************************/ +/** + * Retrieve the BD length field. + * + * For Tx channels, the returned value is the same as that written with + * XEmacPs_BdSetLength(). + * + * For Rx channels, the returned value is the size of the received packet. + * + * @param BdPtr is the BD pointer to operate on + * + * @return Length field processed by hardware or set by + * XEmacPs_BdSetLength(). + * + * @note + * C-style signature: + * u32 XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr) + * XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK. + * + *****************************************************************************/ +#define XEmacPs_BdGetLength(BdPtr) \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_LEN_MASK) + + +/*****************************************************************************/ +/** + * Test whether the given BD has been marked as the last BD of a packet. + * + * @param BdPtr is the BD pointer to operate on + * + * @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise + * + * @note + * C-style signature: + * u32 XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsLast(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_EOF_MASK) ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Tell the DMA engine that the given transmit BD marks the end of the current + * packet to be processed. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdSetLast(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_LAST_MASK)) + + +/*****************************************************************************/ +/** + * Tell the DMA engine that the current packet does not end with the given + * BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearLast(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_LAST_MASK)) + + +/*****************************************************************************/ +/** + * Set this bit to mark the last descriptor in the receive buffer descriptor + * list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdSetRxWrap(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \ + XEMACPS_RXBUF_WRAP_MASK)) + + +/*****************************************************************************/ +/** + * Determine the wrap bit of the receive BD which indicates end of the + * BD list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u32 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxWrap(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + XEMACPS_RXBUF_WRAP_MASK) ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Sets this bit to mark the last descriptor in the transmit buffer + * descriptor list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdSetTxWrap(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_WRAP_MASK)) + + +/*****************************************************************************/ +/** + * Determine the wrap bit of the transmit BD which indicates end of the + * BD list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u32 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxWrap(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_WRAP_MASK) ? TRUE : FALSE) + + +/*****************************************************************************/ +/* + * Must clear this bit to enable the MAC to write data to the receive + * buffer. Hardware sets this bit once it has successfully written a frame to + * memory. Once set, software has to clear the bit before the buffer can be + * used again. This macro clear the new bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearRxNew(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + ~XEMACPS_RXBUF_NEW_MASK)) + + +/*****************************************************************************/ +/** + * Determine the new bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u32 XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxNew(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + XEMACPS_RXBUF_NEW_MASK) ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Software sets this bit to disable the buffer to be read by the hardware. + * Hardware sets this bit for the first buffer of a frame once it has been + * successfully transmitted. This macro sets this bit of transmit BD to avoid + * confusion. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdSetTxUsed(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_USED_MASK)) + + +/*****************************************************************************/ +/** + * Software clears this bit to enable the buffer to be read by the hardware. + * Hardware sets this bit for the first buffer of a frame once it has been + * successfully transmitted. This macro clears this bit of transmit BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearTxUsed(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_USED_MASK)) + + +/*****************************************************************************/ +/** + * Determine the used bit of the transmit BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u32 XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxUsed(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_USED_MASK) ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if a frame fails to be transmitted due to too many retries. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u32 XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxRetry(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_RETRY_MASK) ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if a frame fails to be transmitted due to data can not be + * feteched in time or buffers are exhausted. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u32 XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxUrun(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_URUN_MASK) ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if a frame fails to be transmitted due to buffer is exhausted + * mid-frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u32 XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxExh(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_EXH_MASK) ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Sets this bit, no CRC will be appended to the current frame. This control + * bit must be set for the first buffer in a frame and will be ignored for + * the subsequent buffers of a frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * This bit must be clear when using the transmit checksum generation offload, + * otherwise checksum generation and substitution will not occur. + * + * C-style signature: + * u32 XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdSetTxNoCRC(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_NOCRC_MASK)) + + +/*****************************************************************************/ +/** + * Clear this bit, CRC will be appended to the current frame. This control + * bit must be set for the first buffer in a frame and will be ignored for + * the subsequent buffers of a frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * This bit must be clear when using the transmit checksum generation offload, + * otherwise checksum generation and substitution will not occur. + * + * C-style signature: + * u32 XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearTxNoCRC(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_NOCRC_MASK)) + + +/*****************************************************************************/ +/** + * Determine the broadcast bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u32 XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxBcast(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_BCAST_MASK) ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the multicast hash bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u32 XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxMultiHash(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_MULTIHASH_MASK) ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the unicast hash bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u32 XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxUniHash(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_UNIHASH_MASK) ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if the received frame is a VLAN Tagged frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u32 XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxVlan(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_VLAN_MASK) ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if the received frame has Type ID of 8100h and null VLAN + * identifier(Priority tag). + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u32 XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxPri(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_PRI_MASK) ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if the received frame's Concatenation Format Indicator (CFI) of + * the frames VLANTCI field was set. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u32 XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxCFI(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_CFI_MASK) ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the End Of Frame (EOF) bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u32 XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxEOF(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_EOF_MASK) ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the Start Of Frame (SOF) bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u32 XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxSOF(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_SOF_MASK) ? TRUE : FALSE) + + +/************************** Function Prototypes ******************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xemacps_bdring.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xemacps_bdring.h new file mode 100644 index 000000000..9c50d618e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xemacps_bdring.h @@ -0,0 +1,242 @@ +/* $Id: xemacps_bdring.h,v 1.1.2.1 2011/01/20 03:39:02 sadanan Exp $ */ +/****************************************************************************** +* +* (c) Copyright 2010 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xemacps_bdring.h +* +* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs +* DMA functionalities. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release
+*
+* +******************************************************************************/ + +#ifndef XEMACPS_BDRING_H /* prevent curcular inclusions */ +#define XEMACPS_BDRING_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + + +/**************************** Type Definitions *******************************/ + +/** This is an internal structure used to maintain the DMA list */ +typedef struct { + u32 PhysBaseAddr;/**< Physical address of 1st BD in list */ + u32 BaseBdAddr; /**< Virtual address of 1st BD in list */ + u32 HighBdAddr; /**< Virtual address of last BD in the list */ + u32 Length; /**< Total size of ring in bytes */ + u32 RunState; /**< Flag to indicate DMA is started */ + u32 Separation; /**< Number of bytes between the starting address + of adjacent BDs */ + XEmacPs_Bd *FreeHead; + /**< First BD in the free group */ + XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */ + XEmacPs_Bd *HwHead; /**< First BD in the work group */ + XEmacPs_Bd *HwTail; /**< Last BD in the work group */ + XEmacPs_Bd *PostHead; + /**< First BD in the post-work group */ + XEmacPs_Bd *BdaRestart; + /**< BDA to load when channel is started */ + unsigned HwCnt; /**< Number of BDs in work group */ + unsigned PreCnt; /**< Number of BDs in pre-work group */ + unsigned FreeCnt; /**< Number of allocatable BDs in the free group */ + unsigned PostCnt; /**< Number of BDs in post-work group */ + unsigned AllCnt; /**< Total Number of BDs for channel */ +} XEmacPs_BdRing; + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** +* Use this macro at initialization time to determine how many BDs will fit +* in a BD list within the given memory constraints. +* +* The results of this macro can be provided to XEmacPs_BdRingCreate(). +* +* @param Alignment specifies what byte alignment the BDs must fall on and +* must be a power of 2 to get an accurate calculation (32, 64, 128,...) +* @param Bytes is the number of bytes to be used to store BDs. +* +* @return Number of BDs that can fit in the given memory area +* +* @note +* C-style signature: +* u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes) +* +******************************************************************************/ +#define XEmacPs_BdRingCntCalc(Alignment, Bytes) \ + (u32)((Bytes) / ((sizeof(XEmacPs_Bd) + ((Alignment)-1)) & \ + ~((Alignment)-1))) + +/*****************************************************************************/ +/** +* Use this macro at initialization time to determine how many bytes of memory +* is required to contain a given number of BDs at a given alignment. +* +* @param Alignment specifies what byte alignment the BDs must fall on. This +* parameter must be a power of 2 to get an accurate calculation (32, 64, +* 128,...) +* @param NumBd is the number of BDs to calculate memory size requirements for +* +* @return The number of bytes of memory required to create a BD list with the +* given memory constraints. +* +* @note +* C-style signature: +* u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd) +* +******************************************************************************/ +#define XEmacPs_BdRingMemCalc(Alignment, NumBd) \ + (u32)((sizeof(XEmacPs_Bd) + ((Alignment)-1)) & \ + ~((Alignment)-1)) * (NumBd) + +/****************************************************************************/ +/** +* Return the total number of BDs allocated by this channel with +* XEmacPs_BdRingCreate(). +* +* @param RingPtr is the DMA channel to operate on. +* +* @return The total number of BDs allocated for this channel. +* +* @note +* C-style signature: +* u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr) +* +*****************************************************************************/ +#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt) + +/****************************************************************************/ +/** +* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre- +* processing. +* +* @param RingPtr is the DMA channel to operate on. +* +* @return The number of BDs currently allocatable. +* +* @note +* C-style signature: +* u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr) +* +*****************************************************************************/ +#define XEmacPs_BdRingGetFreeCnt(RingPtr) ((RingPtr)->FreeCnt) + +/****************************************************************************/ +/** +* Return the next BD from BdPtr in a list. +* +* @param RingPtr is the DMA channel to operate on. +* @param BdPtr is the BD to operate on. +* +* @return The next BD in the list relative to the BdPtr parameter. +* +* @note +* C-style signature: +* XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr, +* XEmacPs_Bd *BdPtr) +* +*****************************************************************************/ +#define XEmacPs_BdRingNext(RingPtr, BdPtr) \ + (((u32)(BdPtr) >= (RingPtr)->HighBdAddr) ? \ + (XEmacPs_Bd*)(RingPtr)->BaseBdAddr : \ + (XEmacPs_Bd*)((u32)(BdPtr) + (RingPtr)->Separation)) + +/****************************************************************************/ +/** +* Return the previous BD from BdPtr in the list. +* +* @param RingPtr is the DMA channel to operate on. +* @param BdPtr is the BD to operate on +* +* @return The previous BD in the list relative to the BdPtr parameter. +* +* @note +* C-style signature: +* XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr, +* XEmacPs_Bd *BdPtr) +* +*****************************************************************************/ +#define XEmacPs_BdRingPrev(RingPtr, BdPtr) \ + (((u32)(BdPtr) <= (RingPtr)->BaseBdAddr) ? \ + (XEmacPs_Bd*)(RingPtr)->HighBdAddr : \ + (XEmacPs_Bd*)((u32)(BdPtr) - (RingPtr)->Separation)) + +/************************** Function Prototypes ******************************/ + +/* + * Scatter gather DMA related functions in xemacps_bdring.c + */ +int XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, u32 PhysAddr, + u32 VirtAddr, u32 Alignment, unsigned BdCount); +int XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr, + u8 Direction); +int XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, unsigned NumBd, + XEmacPs_Bd ** BdSetPtr); +int XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, unsigned NumBd, + XEmacPs_Bd * BdSetPtr); +int XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, unsigned NumBd, + XEmacPs_Bd * BdSetPtr); +int XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, unsigned NumBd, + XEmacPs_Bd * BdSetPtr); +unsigned XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, unsigned BdLimit, + XEmacPs_Bd ** BdSetPtr); +unsigned XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, unsigned BdLimit, + XEmacPs_Bd ** BdSetPtr); +int XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction); + +#ifdef __cplusplus +} +#endif + + +#endif /* end of protection macros */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xemacps_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xemacps_hw.h new file mode 100644 index 000000000..4ae27afd8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xemacps_hw.h @@ -0,0 +1,605 @@ +/****************************************************************************** +* +* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xemacps_hw.h +* +* This header file contains identifiers and low-level driver functions (or +* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device. +* High-level driver functions are defined in xemacps.h. +* +* @note +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release.
+* 1.02a asa  11/05/12 Added hash defines for DMACR burst length configuration.
+* 1.05a kpc  28/06/13 Added XEmacPs_ResetHw function prototype
+* 1.06a asa  11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+*					  to 0x1fff. This fixes the CR#744902.
+*
+* +******************************************************************************/ + +#ifndef XEMACPS_HW_H /* prevent circular inclusions */ +#define XEMACPS_HW_H /* by using protection macros */ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ + +#define XEMACPS_MAX_MAC_ADDR 4 /**< Maxmum number of mac address + supported */ +#define XEMACPS_MAX_TYPE_ID 4 /**< Maxmum number of type id supported */ +#define XEMACPS_BD_ALIGNMENT 4 /**< Minimum buffer descriptor alignment + on the local bus */ +#define XEMACPS_RX_BUF_ALIGNMENT 4 /**< Minimum buffer alignment when using + options that impose alignment + restrictions on the buffer data on + the local bus */ + +/** @name Direction identifiers + * + * These are used by several functions and callbacks that need + * to specify whether an operation specifies a send or receive channel. + * @{ + */ +#define XEMACPS_SEND 1 /**< send direction */ +#define XEMACPS_RECV 2 /**< receive direction */ +/*@}*/ + +/** @name MDC clock division + * currently supporting 8, 16, 32, 48, 64, 96, 128, 224. + * @{ + */ +typedef enum { MDC_DIV_8 = 0, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48, + MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224 +} XEmacPs_MdcDiv; + +/*@}*/ + +#define XEMACPS_RX_BUF_SIZE 1536 /**< Specify the receive buffer size in + bytes, 64, 128, ... 10240 */ +#define XEMACPS_RX_BUF_UNIT 64 /**< Number of receive buffer bytes as a + unit, this is HW setup */ + +#define XEMACPS_MAX_RXBD 128 /**< Size of RX buffer descriptor queues */ +#define XEMACPS_MAX_TXBD 128 /**< Size of TX buffer descriptor queues */ + +#define XEMACPS_MAX_HASH_BITS 64 /**< Maximum value for hash bits. 2**6 */ + +/* Register offset definitions. Unless otherwise noted, register access is + * 32 bit. Names are self explained here. + */ + +#define XEMACPS_NWCTRL_OFFSET 0x00000000 /**< Network Control reg */ +#define XEMACPS_NWCFG_OFFSET 0x00000004 /**< Network Config reg */ +#define XEMACPS_NWSR_OFFSET 0x00000008 /**< Network Status reg */ + +#define XEMACPS_DMACR_OFFSET 0x00000010 /**< DMA Control reg */ +#define XEMACPS_TXSR_OFFSET 0x00000014 /**< TX Status reg */ +#define XEMACPS_RXQBASE_OFFSET 0x00000018 /**< RX Q Base address reg */ +#define XEMACPS_TXQBASE_OFFSET 0x0000001C /**< TX Q Base address reg */ +#define XEMACPS_RXSR_OFFSET 0x00000020 /**< RX Status reg */ + +#define XEMACPS_ISR_OFFSET 0x00000024 /**< Interrupt Status reg */ +#define XEMACPS_IER_OFFSET 0x00000028 /**< Interrupt Enable reg */ +#define XEMACPS_IDR_OFFSET 0x0000002C /**< Interrupt Disable reg */ +#define XEMACPS_IMR_OFFSET 0x00000030 /**< Interrupt Mask reg */ + +#define XEMACPS_PHYMNTNC_OFFSET 0x00000034 /**< Phy Maintaince reg */ +#define XEMACPS_RXPAUSE_OFFSET 0x00000038 /**< RX Pause Time reg */ +#define XEMACPS_TXPAUSE_OFFSET 0x0000003C /**< TX Pause Time reg */ + +#define XEMACPS_HASHL_OFFSET 0x00000080 /**< Hash Low address reg */ +#define XEMACPS_HASHH_OFFSET 0x00000084 /**< Hash High address reg */ + +#define XEMACPS_LADDR1L_OFFSET 0x00000088 /**< Specific1 addr low reg */ +#define XEMACPS_LADDR1H_OFFSET 0x0000008C /**< Specific1 addr high reg */ +#define XEMACPS_LADDR2L_OFFSET 0x00000090 /**< Specific2 addr low reg */ +#define XEMACPS_LADDR2H_OFFSET 0x00000094 /**< Specific2 addr high reg */ +#define XEMACPS_LADDR3L_OFFSET 0x00000098 /**< Specific3 addr low reg */ +#define XEMACPS_LADDR3H_OFFSET 0x0000009C /**< Specific3 addr high reg */ +#define XEMACPS_LADDR4L_OFFSET 0x000000A0 /**< Specific4 addr low reg */ +#define XEMACPS_LADDR4H_OFFSET 0x000000A4 /**< Specific4 addr high reg */ + +#define XEMACPS_MATCH1_OFFSET 0x000000A8 /**< Type ID1 Match reg */ +#define XEMACPS_MATCH2_OFFSET 0x000000AC /**< Type ID2 Match reg */ +#define XEMACPS_MATCH3_OFFSET 0x000000B0 /**< Type ID3 Match reg */ +#define XEMACPS_MATCH4_OFFSET 0x000000B4 /**< Type ID4 Match reg */ + +#define XEMACPS_STRETCH_OFFSET 0x000000BC /**< IPG Stretch reg */ + +#define XEMACPS_OCTTXL_OFFSET 0x00000100 /**< Octects transmitted Low + reg */ +#define XEMACPS_OCTTXH_OFFSET 0x00000104 /**< Octects transmitted High + reg */ + +#define XEMACPS_TXCNT_OFFSET 0x00000108 /**< Error-free Frmaes + transmitted counter */ +#define XEMACPS_TXBCCNT_OFFSET 0x0000010C /**< Error-free Broadcast + Frames counter*/ +#define XEMACPS_TXMCCNT_OFFSET 0x00000110 /**< Error-free Multicast + Frame counter */ +#define XEMACPS_TXPAUSECNT_OFFSET 0x00000114 /**< Pause Frames Transmitted + Counter */ +#define XEMACPS_TX64CNT_OFFSET 0x00000118 /**< Error-free 64 byte Frames + Transmitted counter */ +#define XEMACPS_TX65CNT_OFFSET 0x0000011C /**< Error-free 65-127 byte + Frames Transmitted + counter */ +#define XEMACPS_TX128CNT_OFFSET 0x00000120 /**< Error-free 128-255 byte + Frames Transmitted + counter*/ +#define XEMACPS_TX256CNT_OFFSET 0x00000124 /**< Error-free 256-511 byte + Frames transmitted + counter */ +#define XEMACPS_TX512CNT_OFFSET 0x00000128 /**< Error-free 512-1023 byte + Frames transmitted + counter */ +#define XEMACPS_TX1024CNT_OFFSET 0x0000012C /**< Error-free 1024-1518 byte + Frames transmitted + counter */ +#define XEMACPS_TX1519CNT_OFFSET 0x00000130 /**< Error-free larger than + 1519 byte Frames + transmitted counter */ +#define XEMACPS_TXURUNCNT_OFFSET 0x00000134 /**< TX under run error + counter */ + +#define XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138 /**< Single Collision Frame + Counter */ +#define XEMACPS_MULTICOLLCNT_OFFSET 0x0000013C /**< Multiple Collision Frame + Counter */ +#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140 /**< Excessive Collision Frame + Counter */ +#define XEMACPS_LATECOLLCNT_OFFSET 0x00000144 /**< Late Collision Frame + Counter */ +#define XEMACPS_TXDEFERCNT_OFFSET 0x00000148 /**< Deferred Transmission + Frame Counter */ +#define XEMACPS_TXCSENSECNT_OFFSET 0x0000014C /**< Transmit Carrier Sense + Error Counter */ + +#define XEMACPS_OCTRXL_OFFSET 0x00000150 /**< Octects Received register + Low */ +#define XEMACPS_OCTRXH_OFFSET 0x00000154 /**< Octects Received register + High */ + +#define XEMACPS_RXCNT_OFFSET 0x00000158 /**< Error-free Frames + Received Counter */ +#define XEMACPS_RXBROADCNT_OFFSET 0x0000015C /**< Error-free Broadcast + Frames Received Counter */ +#define XEMACPS_RXMULTICNT_OFFSET 0x00000160 /**< Error-free Multicast + Frames Received Counter */ +#define XEMACPS_RXPAUSECNT_OFFSET 0x00000164 /**< Pause Frames + Received Counter */ +#define XEMACPS_RX64CNT_OFFSET 0x00000168 /**< Error-free 64 byte Frames + Received Counter */ +#define XEMACPS_RX65CNT_OFFSET 0x0000016C /**< Error-free 65-127 byte + Frames Received Counter */ +#define XEMACPS_RX128CNT_OFFSET 0x00000170 /**< Error-free 128-255 byte + Frames Received Counter */ +#define XEMACPS_RX256CNT_OFFSET 0x00000174 /**< Error-free 256-512 byte + Frames Received Counter */ +#define XEMACPS_RX512CNT_OFFSET 0x00000178 /**< Error-free 512-1023 byte + Frames Received Counter */ +#define XEMACPS_RX1024CNT_OFFSET 0x0000017C /**< Error-free 1024-1518 byte + Frames Received Counter */ +#define XEMACPS_RX1519CNT_OFFSET 0x00000180 /**< Error-free 1519-max byte + Frames Received Counter */ +#define XEMACPS_RXUNDRCNT_OFFSET 0x00000184 /**< Undersize Frames Received + Counter */ +#define XEMACPS_RXOVRCNT_OFFSET 0x00000188 /**< Oversize Frames Received + Counter */ +#define XEMACPS_RXJABCNT_OFFSET 0x0000018C /**< Jabbers Received + Counter */ +#define XEMACPS_RXFCSCNT_OFFSET 0x00000190 /**< Frame Check Sequence + Error Counter */ +#define XEMACPS_RXLENGTHCNT_OFFSET 0x00000194 /**< Length Field Error + Counter */ +#define XEMACPS_RXSYMBCNT_OFFSET 0x00000198 /**< Symbol Error Counter */ +#define XEMACPS_RXALIGNCNT_OFFSET 0x0000019C /**< Alignment Error Counter */ +#define XEMACPS_RXRESERRCNT_OFFSET 0x000001A0 /**< Receive Resource Error + Counter */ +#define XEMACPS_RXORCNT_OFFSET 0x000001A4 /**< Receive Overrun Counter */ +#define XEMACPS_RXIPCCNT_OFFSET 0x000001A8 /**< IP header Checksum Error + Counter */ +#define XEMACPS_RXTCPCCNT_OFFSET 0x000001AC /**< TCP Checksum Error + Counter */ +#define XEMACPS_RXUDPCCNT_OFFSET 0x000001B0 /**< UDP Checksum Error + Counter */ +#define XEMACPS_LAST_OFFSET 0x000001B4 /**< Last statistic counter + offset, for clearing */ + +#define XEMACPS_1588_SEC_OFFSET 0x000001D0 /**< 1588 second counter */ +#define XEMACPS_1588_NANOSEC_OFFSET 0x000001D4 /**< 1588 nanosecond counter */ +#define XEMACPS_1588_ADJ_OFFSET 0x000001D8 /**< 1588 nanosecond + adjustment counter */ +#define XEMACPS_1588_INC_OFFSET 0x000001DC /**< 1588 nanosecond + increment counter */ +#define XEMACPS_PTP_TXSEC_OFFSET 0x000001E0 /**< 1588 PTP transmit second + counter */ +#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4 /**< 1588 PTP transmit + nanosecond counter */ +#define XEMACPS_PTP_RXSEC_OFFSET 0x000001E8 /**< 1588 PTP receive second + counter */ +#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001EC /**< 1588 PTP receive + nanosecond counter */ +#define XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0 /**< 1588 PTP peer transmit + second counter */ +#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4 /**< 1588 PTP peer transmit + nanosecond counter */ +#define XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8 /**< 1588 PTP peer receive + second counter */ +#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FC /**< 1588 PTP peer receive + nanosecond counter */ + +/* Define some bit positions for registers. */ + +/** @name network control register bit definitions + * @{ + */ +#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000 /**< Flush a packet from + Rx SRAM */ +#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800 /**< Transmit zero quantum + pause frame */ +#define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800 /**< Transmit pause frame */ +#define XEMACPS_NWCTRL_HALTTX_MASK 0x00000400 /**< Halt transmission + after current frame */ +#define XEMACPS_NWCTRL_STARTTX_MASK 0x00000200 /**< Start tx (tx_go) */ + +#define XEMACPS_NWCTRL_STATWEN_MASK 0x00000080 /**< Enable writing to + stat counters */ +#define XEMACPS_NWCTRL_STATINC_MASK 0x00000040 /**< Increment statistic + registers */ +#define XEMACPS_NWCTRL_STATCLR_MASK 0x00000020 /**< Clear statistic + registers */ +#define XEMACPS_NWCTRL_MDEN_MASK 0x00000010 /**< Enable MDIO port */ +#define XEMACPS_NWCTRL_TXEN_MASK 0x00000008 /**< Enable transmit */ +#define XEMACPS_NWCTRL_RXEN_MASK 0x00000004 /**< Enable receive */ +#define XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002 /**< local loopback */ +/*@}*/ + +/** @name network configuration register bit definitions + * @{ + */ +#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000 /**< disable rejection of + non-standard preamble */ +#define XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000 /**< enable transmit IPG */ +#define XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000 /**< disable rejection of + FCS error */ +#define XEMACPS_NWCFG_HDRXEN_MASK 0x02000000 /**< RX half duplex */ +#define XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000 /**< enable RX checksum + offload */ +#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000 /**< Do not copy pause + Frames to memory */ +#define XEMACPS_NWCFG_MDC_SHIFT_MASK 18 /**< shift bits for MDC */ +#define XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000 /**< MDC Mask PCLK divisor */ +#define XEMACPS_NWCFG_FCSREM_MASK 0x00020000 /**< Discard FCS from + received frames */ +#define XEMACPS_NWCFG_LENGTHERRDSCRD_MASK 0x00010000 +/**< RX length error discard */ +#define XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000 /**< RX buffer offset */ +#define XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000 /**< Enable pause RX */ +#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000 /**< Retry test */ +#define XEMACPS_NWCFG_EXTADDRMATCHEN_MASK 0x00000200 +/**< External address match enable */ +#define XEMACPS_NWCFG_1000_MASK 0x00000400 /**< 1000 Mbps */ +#define XEMACPS_NWCFG_1536RXEN_MASK 0x00000100 /**< Enable 1536 byte + frames reception */ +#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080 /**< Receive unicast hash + frames */ +#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040 /**< Receive multicast hash + frames */ +#define XEMACPS_NWCFG_BCASTDI_MASK 0x00000020 /**< Do not receive + broadcast frames */ +#define XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010 /**< Copy all frames */ +#define XEMACPS_NWCFG_JUMBO_MASK 0x00000008 /**< Jumbo frames */ +#define XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004 /**< Receive only VLAN + frames */ +#define XEMACPS_NWCFG_FDEN_MASK 0x00000002 /**< full duplex */ +#define XEMACPS_NWCFG_100_MASK 0x00000001 /**< 100 Mbps */ +#define XEMACPS_NWCFG_RESET_MASK 0x00080000 /**< reset value */ +/*@}*/ + +/** @name network status register bit definitaions + * @{ + */ +#define XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004 /**< PHY management idle */ +#define XEMACPS_NWSR_MDIO_MASK 0x00000002 /**< Status of mdio_in */ +/*@}*/ + + +/** @name MAC address register word 1 mask + * @{ + */ +#define XEMACPS_LADDR_MACH_MASK 0x0000FFFF /**< Address bits[47:32] + bit[31:0] are in BOTTOM */ +/*@}*/ + + +/** @name DMA control register bit definitions + * @{ + */ +#define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000 /**< Mask bit for RX buffer + size */ +#define XEMACPS_DMACR_RXBUF_SHIFT 16 /**< Shift bit for RX buffer + size */ +#define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800 /**< enable/disable TX + checksum offload */ +#define XEMACPS_DMACR_TXSIZE_MASK 0x00000400 /**< TX buffer memory size */ +#define XEMACPS_DMACR_RXSIZE_MASK 0x00000300 /**< RX buffer memory size */ +#define XEMACPS_DMACR_ENDIAN_MASK 0x00000080 /**< endian configuration */ +#define XEMACPS_DMACR_BLENGTH_MASK 0x0000001F /**< buffer burst length */ +#define XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001 /**< single AHB bursts */ +#define XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004 /**< 4 bytes AHB bursts */ +#define XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008 /**< 8 bytes AHB bursts */ +#define XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010 /**< 16 bytes AHB bursts */ +/*@}*/ + +/** @name transmit status register bit definitions + * @{ + */ +#define XEMACPS_TXSR_HRESPNOK_MASK 0x00000100 /**< Transmit hresp not OK */ +#define XEMACPS_TXSR_URUN_MASK 0x00000040 /**< Transmit underrun */ +#define XEMACPS_TXSR_TXCOMPL_MASK 0x00000020 /**< Transmit completed OK */ +#define XEMACPS_TXSR_BUFEXH_MASK 0x00000010 /**< Transmit buffs exhausted + mid frame */ +#define XEMACPS_TXSR_TXGO_MASK 0x00000008 /**< Status of go flag */ +#define XEMACPS_TXSR_RXOVR_MASK 0x00000004 /**< Retry limit exceeded */ +#define XEMACPS_TXSR_FRAMERX_MASK 0x00000002 /**< Collision tx frame */ +#define XEMACPS_TXSR_USEDREAD_MASK 0x00000001 /**< TX buffer used bit set */ + +#define XEMACPS_TXSR_ERROR_MASK (XEMACPS_TXSR_HRESPNOK_MASK | \ + XEMACPS_TXSR_URUN_MASK | \ + XEMACPS_TXSR_BUFEXH_MASK | \ + XEMACPS_TXSR_RXOVR_MASK | \ + XEMACPS_TXSR_FRAMERX_MASK | \ + XEMACPS_TXSR_USEDREAD_MASK) +/*@}*/ + +/** + * @name receive status register bit definitions + * @{ + */ +#define XEMACPS_RXSR_HRESPNOK_MASK 0x00000008 /**< Receive hresp not OK */ +#define XEMACPS_RXSR_RXOVR_MASK 0x00000004 /**< Receive overrun */ +#define XEMACPS_RXSR_FRAMERX_MASK 0x00000002 /**< Frame received OK */ +#define XEMACPS_RXSR_BUFFNA_MASK 0x00000001 /**< RX buffer used bit set */ + +#define XEMACPS_RXSR_ERROR_MASK (XEMACPS_RXSR_HRESPNOK_MASK | \ + XEMACPS_RXSR_RXOVR_MASK | \ + XEMACPS_RXSR_BUFFNA_MASK) +/*@}*/ + +/** + * @name interrupts bit definitions + * Bits definitions are same in XEMACPS_ISR_OFFSET, + * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET + * @{ + */ +#define XEMACPS_IXR_PTPPSTX_MASK 0x02000000 /**< PTP Psync transmitted */ +#define XEMACPS_IXR_PTPPDRTX_MASK 0x01000000 /**< PTP Pdelay_req + transmitted */ +#define XEMACPS_IXR_PTPSTX_MASK 0x00800000 /**< PTP Sync transmitted */ +#define XEMACPS_IXR_PTPDRTX_MASK 0x00400000 /**< PTP Delay_req transmitted + */ +#define XEMACPS_IXR_PTPPSRX_MASK 0x00200000 /**< PTP Psync received */ +#define XEMACPS_IXR_PTPPDRRX_MASK 0x00100000 /**< PTP Pdelay_req received */ +#define XEMACPS_IXR_PTPSRX_MASK 0x00080000 /**< PTP Sync received */ +#define XEMACPS_IXR_PTPDRRX_MASK 0x00040000 /**< PTP Delay_req received */ +#define XEMACPS_IXR_PAUSETX_MASK 0x00004000 /**< Pause frame transmitted */ +#define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000 /**< Pause time has reached + zero */ +#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000 /**< Pause frame received */ +#define XEMACPS_IXR_HRESPNOK_MASK 0x00000800 /**< hresp not ok */ +#define XEMACPS_IXR_RXOVR_MASK 0x00000400 /**< Receive overrun occurred */ +#define XEMACPS_IXR_TXCOMPL_MASK 0x00000080 /**< Frame transmitted ok */ +#define XEMACPS_IXR_TXEXH_MASK 0x00000040 /**< Transmit err occurred or + no buffers*/ +#define XEMACPS_IXR_RETRY_MASK 0x00000020 /**< Retry limit exceeded */ +#define XEMACPS_IXR_URUN_MASK 0x00000010 /**< Transmit underrun */ +#define XEMACPS_IXR_TXUSED_MASK 0x00000008 /**< Tx buffer used bit read */ +#define XEMACPS_IXR_RXUSED_MASK 0x00000004 /**< Rx buffer used bit read */ +#define XEMACPS_IXR_FRAMERX_MASK 0x00000002 /**< Frame received ok */ +#define XEMACPS_IXR_MGMNT_MASK 0x00000001 /**< PHY management complete */ +#define XEMACPS_IXR_ALL_MASK 0x00007FFF /**< Everything! */ + +#define XEMACPS_IXR_TX_ERR_MASK (XEMACPS_IXR_TXEXH_MASK | \ + XEMACPS_IXR_RETRY_MASK | \ + XEMACPS_IXR_URUN_MASK | \ + XEMACPS_IXR_TXUSED_MASK) + + +#define XEMACPS_IXR_RX_ERR_MASK (XEMACPS_IXR_HRESPNOK_MASK | \ + XEMACPS_IXR_RXUSED_MASK | \ + XEMACPS_IXR_RXOVR_MASK) + +/*@}*/ + +/** @name PHY Maintenance bit definitions + * @{ + */ +#define XEMACPS_PHYMNTNC_OP_MASK 0x40020000 /**< operation mask bits */ +#define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000 /**< read operation */ +#define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000 /**< write operation */ +#define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000 /**< Address bits */ +#define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000 /**< register bits */ +#define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFF /**< data bits */ +#define XEMACPS_PHYMNTNC_PHYAD_SHIFT_MASK 23 /**< Shift bits for PHYAD */ +#define XEMACPS_PHYMNTNC_PHREG_SHIFT_MASK 18 /**< Shift bits for PHREG */ +/*@}*/ + +/* Transmit buffer descriptor status words offset + * @{ + */ +#define XEMACPS_BD_ADDR_OFFSET 0x00000000 /**< word 0/addr of BDs */ +#define XEMACPS_BD_STAT_OFFSET 0x00000004 /**< word 1/status of BDs */ +/* + * @} + */ + +/* Transmit buffer descriptor status words bit positions. + * Transmit buffer descriptor consists of two 32-bit registers, + * the first - word0 contains a 32-bit address pointing to the location of + * the transmit data. + * The following register - word1, consists of various information to control + * the XEmacPs transmit process. After transmit, this is updated with status + * information, whether the frame was transmitted OK or why it had failed. + * @{ + */ +#define XEMACPS_TXBUF_USED_MASK 0x80000000 /**< Used bit. */ +#define XEMACPS_TXBUF_WRAP_MASK 0x40000000 /**< Wrap bit, last descriptor */ +#define XEMACPS_TXBUF_RETRY_MASK 0x20000000 /**< Retry limit exceeded */ +#define XEMACPS_TXBUF_URUN_MASK 0x10000000 /**< Transmit underrun occurred */ +#define XEMACPS_TXBUF_EXH_MASK 0x08000000 /**< Buffers exhausted */ +#define XEMACPS_TXBUF_TCP_MASK 0x04000000 /**< Late collision. */ +#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000 /**< No CRC */ +#define XEMACPS_TXBUF_LAST_MASK 0x00008000 /**< Last buffer */ +#define XEMACPS_TXBUF_LEN_MASK 0x00003FFF /**< Mask for length field */ +/* + * @} + */ + +/* Receive buffer descriptor status words bit positions. + * Receive buffer descriptor consists of two 32-bit registers, + * the first - word0 contains a 32-bit word aligned address pointing to the + * address of the buffer. The lower two bits make up the wrap bit indicating + * the last descriptor and the ownership bit to indicate it has been used by + * the XEmacPs. + * The following register - word1, contains status information regarding why + * the frame was received (the filter match condition) as well as other + * useful info. + * @{ + */ +#define XEMACPS_RXBUF_BCAST_MASK 0x80000000 /**< Broadcast frame */ +#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000 /**< Multicast hashed frame */ +#define XEMACPS_RXBUF_UNIHASH_MASK 0x20000000 /**< Unicast hashed frame */ +#define XEMACPS_RXBUF_EXH_MASK 0x08000000 /**< buffer exhausted */ +#define XEMACPS_RXBUF_AMATCH_MASK 0x06000000 /**< Specific address + matched */ +#define XEMACPS_RXBUF_IDFOUND_MASK 0x01000000 /**< Type ID matched */ +#define XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000 /**< ID matched mask */ +#define XEMACPS_RXBUF_VLAN_MASK 0x00200000 /**< VLAN tagged */ +#define XEMACPS_RXBUF_PRI_MASK 0x00100000 /**< Priority tagged */ +#define XEMACPS_RXBUF_VPRI_MASK 0x000E0000 /**< Vlan priority */ +#define XEMACPS_RXBUF_CFI_MASK 0x00010000 /**< CFI frame */ +#define XEMACPS_RXBUF_EOF_MASK 0x00008000 /**< End of frame. */ +#define XEMACPS_RXBUF_SOF_MASK 0x00004000 /**< Start of frame. */ +#define XEMACPS_RXBUF_LEN_MASK 0x00001FFF /**< Mask for length field */ + +#define XEMACPS_RXBUF_WRAP_MASK 0x00000002 /**< Wrap bit, last BD */ +#define XEMACPS_RXBUF_NEW_MASK 0x00000001 /**< Used bit.. */ +#define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFC /**< Mask for address */ +/* + * @} + */ + +/* + * Define appropriate I/O access method to mempry mapped I/O or other + * intarfce if necessary. + */ + +#define XEmacPs_In32 Xil_In32 +#define XEmacPs_Out32 Xil_Out32 + + +/****************************************************************************/ +/** +* +* Read the given register. +* +* @param BaseAddress is the base address of the device +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note +* C-style signature: +* u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset) +* +*****************************************************************************/ +#define XEmacPs_ReadReg(BaseAddress, RegOffset) \ + XEmacPs_In32((BaseAddress) + (RegOffset)) + + +/****************************************************************************/ +/** +* +* Write the given register. +* +* @param BaseAddress is the base address of the device +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note +* C-style signature: +* void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset, +* u32 Data) +* +*****************************************************************************/ +#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \ + XEmacPs_Out32((BaseAddress) + (RegOffset), (Data)) + +/************************** Function Prototypes *****************************/ +/* + * Perform reset operation to the emacps interface + */ +void XEmacPs_ResetHw(u32 BaseAddr); + +#ifdef __cplusplus + } +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xenv.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xenv.h new file mode 100644 index 000000000..27cb76810 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xenv.h @@ -0,0 +1,177 @@ +/****************************************************************************** +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" +* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND +* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, +* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION +* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE. +* +* (c) Copyright 2002 Xilinx Inc. +* All rights reserved. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xenv.h +* +* Defines common services that are typically found in a host operating. +* environment. This include file simply includes an OS specific file based +* on the compile-time constant BUILD_ENV_*, where * is the name of the target +* environment. +* +* All services are defined as macros. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b ch   10/24/02 Added XENV_LINUX
+* 1.00a rmm  04/17/02 First release
+*
+* +******************************************************************************/ + +#ifndef XENV_H /* prevent circular inclusions */ +#define XENV_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Select which target environment we are operating under + */ + +/* VxWorks target environment */ +#if defined XENV_VXWORKS +#include "xenv_vxworks.h" + +/* Linux target environment */ +#elif defined XENV_LINUX +#include "xenv_linux.h" + +/* Unit test environment */ +#elif defined XENV_UNITTEST +#include "ut_xenv.h" + +/* Integration test environment */ +#elif defined XENV_INTTEST +#include "int_xenv.h" + +/* Standalone environment selected */ +#else +#include "xenv_standalone.h" +#endif + + +/* + * The following comments specify the types and macro wrappers that are + * expected to be defined by the target specific header files + */ + +/**************************** Type Definitions *******************************/ + +/*****************************************************************************/ +/** + * + * XENV_TIME_STAMP + * + * A structure that contains a time stamp used by other time stamp macros + * defined below. This structure is processor dependent. + */ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** + * + * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes) + * + * Copies a non-overlapping block of memory. + * + * @param DestPtr is the destination address to copy data to. + * @param SrcPtr is the source address to copy data from. + * @param Bytes is the number of bytes to copy. + * + * @return None + */ + +/*****************************************************************************/ +/** + * + * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes) + * + * Fills an area of memory with constant data. + * + * @param DestPtr is the destination address to set. + * @param Data contains the value to set. + * @param Bytes is the number of bytes to set. + * + * @return None + */ +/*****************************************************************************/ +/** + * + * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr) + * + * Samples the processor's or external timer's time base counter. + * + * @param StampPtr is the storage for the retrieved time stamp. + * + * @return None + */ + +/*****************************************************************************/ +/** + * + * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr) + * + * Computes the delta between the two time stamps. + * + * @param Stamp1Ptr - First sampled time stamp. + * @param Stamp1Ptr - Sedond sampled time stamp. + * + * @return An unsigned int value with units of microseconds. + */ + +/*****************************************************************************/ +/** + * + * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr) + * + * Computes the delta between the two time stamps. + * + * @param Stamp1Ptr - First sampled time stamp. + * @param Stamp1Ptr - Sedond sampled time stamp. + * + * @return An unsigned int value with units of milliseconds. + */ + +/*****************************************************************************//** + * + * XENV_USLEEP(unsigned delay) + * + * Delay the specified number of microseconds. + * + * @param delay is the number of microseconds to delay. + * + * @return None + */ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xenv_standalone.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xenv_standalone.h new file mode 100644 index 000000000..f2b2b6887 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xenv_standalone.h @@ -0,0 +1,356 @@ +/****************************************************************************** +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" +* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND +* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, +* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION +* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE. +* +* (c) Copyright 2002-2008 Xilinx Inc. +* All rights reserved. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xenv_standalone.h +* +* Defines common services specified by xenv.h. +* +* @note +* This file is not intended to be included directly by driver code. +* Instead, the generic xenv.h file is intended to be included by driver +* code. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a wgr  02/28/07 Added cache handling macros.
+* 1.00a wgr  02/27/07 Simplified code. Deprecated old-style macro names.
+* 1.00a rmm  01/24/06 Implemented XENV_USLEEP. Assume implementation is being
+*                     used under Xilinx standalone BSP.
+* 1.00a xd   11/03/04 Improved support for doxygen.
+* 1.00a rmm  03/21/02 First release
+* 1.00a wgr  03/22/07 Converted to new coding style.
+* 1.00a rpm  06/29/07 Added udelay macro for standalone
+* 1.00a xd   07/19/07 Included xparameters.h as XPAR_ constants are referred
+*                     to in MICROBLAZE section
+* 1.00a ecm  09/19/08 updated for v7.20 of Microblaze, new functionality
+*
+*
+* +* +******************************************************************************/ + +#ifndef XENV_STANDALONE_H +#define XENV_STANDALONE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +/****************************************************************************** + * + * Get the processor dependent includes + * + ******************************************************************************/ + +#include + +#if defined __MICROBLAZE__ +# include "mb_interface.h" +# include "xparameters.h" /* XPAR constants used below in MB section */ + +#elif defined __PPC__ +# include "sleep.h" +# include "xcache_l.h" /* also include xcache_l.h for caching macros */ +#endif + +/****************************************************************************** + * + * MEMCPY / MEMSET related macros. + * + * The following are straight forward implementations of memset and memcpy. + * + * NOTE: memcpy may not work if source and target memory area are overlapping. + * + ******************************************************************************/ +/*****************************************************************************/ +/** + * + * Copies a non-overlapping block of memory. + * + * @param DestPtr + * Destination address to copy data to. + * + * @param SrcPtr + * Source address to copy data from. + * + * @param Bytes + * Number of bytes to copy. + * + * @return None. + * + * @note + * The use of XENV_MEM_COPY is deprecated. Use memcpy() instead. + * + * @note + * This implemention MAY BREAK work if source and target memory + * area are overlapping. + * + *****************************************************************************/ + +#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \ + memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes) + + + +/*****************************************************************************/ +/** + * + * Fills an area of memory with constant data. + * + * @param DestPtr + * Destination address to copy data to. + * + * @param Data + * Value to set. + * + * @param Bytes + * Number of bytes to copy. + * + * @return None. + * + * @note + * The use of XENV_MEM_FILL is deprecated. Use memset() instead. + * + *****************************************************************************/ + +#define XENV_MEM_FILL(DestPtr, Data, Bytes) \ + memset((void *) DestPtr, (int) Data, (size_t) Bytes) + + + +/****************************************************************************** + * + * TIME related macros + * + ******************************************************************************/ + +/** + * A structure that contains a time stamp used by other time stamp macros + * defined below. This structure is processor dependent. + */ +typedef int XENV_TIME_STAMP; + +/*****************************************************************************/ +/** + * + * Time is derived from the 64 bit PPC timebase register + * + * @param StampPtr is the storage for the retrieved time stamp. + * + * @return None. + * + * @note + * + * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr) + *

+ * This macro must be implemented by the user. + * + *****************************************************************************/ +#define XENV_TIME_STAMP_GET(StampPtr) + +/*****************************************************************************/ +/** + * + * This macro is not yet implemented and always returns 0. + * + * @param Stamp1Ptr is the first sampled time stamp. + * @param Stamp2Ptr is the second sampled time stamp. + * + * @return 0 + * + * @note + * + * This macro must be implemented by the user. + * + *****************************************************************************/ +#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0) + +/*****************************************************************************/ +/** + * + * This macro is not yet implemented and always returns 0. + * + * @param Stamp1Ptr is the first sampled time stamp. + * @param Stamp2Ptr is the second sampled time stamp. + * + * @return 0 + * + * @note + * + * This macro must be implemented by the user. + * + *****************************************************************************/ +#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0) + +/*****************************************************************************/ +/** + * XENV_USLEEP(unsigned delay) + * + * Delay the specified number of microseconds. Not implemented without OS + * support. + * + * @param delay + * Number of microseconds to delay. + * + * @return None. + * + *****************************************************************************/ + +#ifdef __PPC__ +#define XENV_USLEEP(delay) usleep(delay) +#define udelay(delay) usleep(delay) +#else +#define XENV_USLEEP(delay) +#define udelay(delay) +#endif + + +/****************************************************************************** + * + * CACHE handling macros / mappings + * + ******************************************************************************/ +/****************************************************************************** + * + * Processor independent macros + * + ******************************************************************************/ + +#define XCACHE_ENABLE_CACHE() \ + { XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); } + +#define XCACHE_DISABLE_CACHE() \ + { XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); } + + +/****************************************************************************** + * + * MicroBlaze case + * + * NOTE: Currently the following macros will only work on systems that contain + * only ONE MicroBlaze processor. Also, the macros will only be enabled if the + * system is built using a xparameters.h file. + * + ******************************************************************************/ + +#if defined __MICROBLAZE__ + +/* Check if MicroBlaze data cache was built into the core. + */ +#if (XPAR_MICROBLAZE_USE_DCACHE == 1) +# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache() +# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache() +# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache() + +# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \ + microblaze_invalidate_dcache_range((int)(Addr), (int)(Len)) + +#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1) +# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache() +# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \ + microblaze_flush_dcache_range((int)(Addr), (int)(Len)) +#else +# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache() +# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \ + microblaze_invalidate_dcache_range((int)(Addr), (int)(Len)) +#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/ + +#else +# define XCACHE_ENABLE_DCACHE() +# define XCACHE_DISABLE_DCACHE() +# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) +# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) +#endif /*XPAR_MICROBLAZE_USE_DCACHE*/ + + +/* Check if MicroBlaze instruction cache was built into the core. + */ +#if (XPAR_MICROBLAZE_USE_ICACHE == 1) +# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache() +# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache() + +# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache() + +# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \ + microblaze_invalidate_icache_range((int)(Addr), (int)(Len)) + +#else +# define XCACHE_ENABLE_ICACHE() +# define XCACHE_DISABLE_ICACHE() +#endif /*XPAR_MICROBLAZE_USE_ICACHE*/ + + +/****************************************************************************** + * + * PowerPC case + * + * Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a + * specific memory region (0x80000001). Each bit (0-30) in the regions + * bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB + * range. + * + * regions --> cached address range + * ------------|-------------------------------------------------- + * 0x80000000 | [0, 0x7FFFFFF] + * 0x00000001 | [0xF8000000, 0xFFFFFFFF] + * 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF] + * + ******************************************************************************/ + +#elif defined __PPC__ + +#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001) +#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache() +#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001) +#define XCACHE_DISABLE_ICACHE() XCache_DisableICache() + +#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \ + XCache_InvalidateDCacheRange((unsigned int)(Addr), (unsigned)(Len)) + +#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \ + XCache_FlushDCacheRange((unsigned int)(Addr), (unsigned)(Len)) + +#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache() + + +/****************************************************************************** + * + * Unknown processor / architecture + * + ******************************************************************************/ + +#else +/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */ +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef XENV_STANDALONE_H */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xgpiops.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xgpiops.h new file mode 100644 index 000000000..f04e62da3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xgpiops.h @@ -0,0 +1,264 @@ +/****************************************************************************** +* +* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xgpiops.h +* +* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO +* Controller. +* +* The GPIO Controller supports the following features: +* - 4 banks +* - Masked writes (There are no masked reads) +* - Bypass mode +* - Configurable Interrupts (Level/Edge) +* +* This driver is intended to be RTOS and processor independent. Any needs for +* dynamic memory management, threads or thread mutual exclusion, virtual +* memory, or cache control must be satisfied by the layer above this driver. + +* This driver supports all the features listed above, if applicable. +* +* Driver Description +* +* The device driver enables higher layer software (e.g., an application) to +* communicate to the GPIO. +* +* Interrupts +* +* The driver provides interrupt management functions and an interrupt handler. +* Users of this driver need to provide callback functions. An interrupt handler +* example is available with the driver. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The XGpioPs driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +*

+* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 1.01a sv   04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
+*                     XGpioPs_GetMode, XGpioPs_GetModePin as they are not
+*		      relevant to Zynq device.The interrupts are disabled
+*		      for output pins on all banks during initialization.
+* 1.02a hk   08/22/13 Added low level reset API
+* 2.1   hk   04/29/14 Use Input data register DATA_RO for read. CR# 771667.
+*
+*
+* +******************************************************************************/ +#ifndef XGPIOPS_H /* prevent circular inclusions */ +#define XGPIOPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xgpiops_hw.h" + +/************************** Constant Definitions *****************************/ + +/** @name Interrupt types + * @{ + * The following constants define the interrupt types that can be set for each + * GPIO pin. + */ +#define XGPIOPS_IRQ_TYPE_EDGE_RISING 0 /**< Interrupt on Rising edge */ +#define XGPIOPS_IRQ_TYPE_EDGE_FALLING 1 /**< Interrupt Falling edge */ +#define XGPIOPS_IRQ_TYPE_EDGE_BOTH 2 /**< Interrupt on both edges */ +#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 3 /**< Interrupt on high level */ +#define XGPIOPS_IRQ_TYPE_LEVEL_LOW 4 /**< Interrupt on low level */ +/*@}*/ + +#define XGPIOPS_BANK0 0 /**< GPIO Bank 0 */ +#define XGPIOPS_BANK1 1 /**< GPIO Bank 1 */ +#define XGPIOPS_BANK2 2 /**< GPIO Bank 2 */ +#define XGPIOPS_BANK3 3 /**< GPIO Bank 3 */ + +#define XGPIOPS_MAX_BANKS 4 /**< Max banks in a GPIO device */ +#define XGPIOPS_BANK_MAX_PINS 32 /**< Max pins in a GPIO bank */ + +#define XGPIOPS_DEVICE_MAX_PIN_NUM 118 /*< Max pins in the GPIO device + * 0 - 31, Bank 0 + * 32 - 53, Bank 1 + * 54 - 85, Bank 2 + * 86 - 117, Bank 3 + */ + +/**************************** Type Definitions *******************************/ + +/****************************************************************************/ +/** + * This handler data type allows the user to define a callback function to + * handle the interrupts for the GPIO device. The application using this + * driver is expected to define a handler of this type, to support interrupt + * driven mode. The handler executes in an interrupt context such that minimal + * processing should be performed. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the callback functions for a GPIO bank. It is + * passed back to the upper layer when the callback is invoked. Its + * type is not important to the driver component, so it is a void + * pointer. + * @param Bank is the bank for which the interrupt status has changed. + * @param Status is the Interrupt status of the GPIO bank. + * + *****************************************************************************/ +typedef void (*XGpioPs_Handler) (void *CallBackRef, int Bank, u32 Status); + +/** + * This typedef contains configuration information for a device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddr; /**< Register base address */ +} XGpioPs_Config; + +/** + * The XGpioPs driver instance data. The user is required to allocate a + * variable of this type for the GPIO device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XGpioPs_Config GpioConfig; /**< Device configuration */ + u32 IsReady; /**< Device is initialized and ready */ + XGpioPs_Handler Handler; /**< Status handlers for all banks */ + void *CallBackRef; /**< Callback ref for bank handlers */ +} XGpioPs; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/* + * Functions in xgpiops.c + */ +int XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr, + u32 EffectiveAddr); + +/* + * Bank APIs in xgpiops.c + */ +u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank); +void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data); +void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction); +u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank); +void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 Enable); +u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank); +void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank); + +/* + * Pin APIs in xgpiops.c + */ +int XGpioPs_ReadPin(XGpioPs *InstancePtr, int Pin); +void XGpioPs_WritePin(XGpioPs *InstancePtr, int Pin, int Data); +void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, int Pin, int Direction); +int XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, int Pin); +void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, int Pin, int Enable); +int XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, int Pin); + +/* + * Diagnostic functions in xgpiops_selftest.c + */ +int XGpioPs_SelfTest(XGpioPs *InstancePtr); + +/* + * Functions in xgpiops_intr.c + */ +/* + * Bank APIs in xgpiops_intr.c + */ +void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask); +void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask); +u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank); +u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank); +void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask); +void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType, + u32 IntrPolarity, u32 IntrOnAny); +void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType, + u32 *IntrPolarity, u32 *IntrOnAny); +void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef, + XGpioPs_Handler FuncPtr); +void XGpioPs_IntrHandler(XGpioPs *InstancePtr); + +/* + * Pin APIs in xgpiops_intr.c + */ +void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, int Pin, u8 IrqType); +u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, int Pin); + +void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, int Pin); +void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, int Pin); +int XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, int Pin); +int XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, int Pin); +void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, int Pin); + +/* + * Functions in xgpiops_sinit.c + */ +XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xgpiops_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xgpiops_hw.h new file mode 100644 index 000000000..6c9ef5e0e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xgpiops_hw.h @@ -0,0 +1,159 @@ +/****************************************************************************** +* +* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xgpiops_hw.h +* +* This header file contains the identifiers and basic driver functions (or +* macros) that can be used to access the device. Other driver functions +* are defined in xgpiops.h. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 1.02a hk   08/22/13 Added low level reset API function prototype and
+*                     related constant definitions
+*
+* +******************************************************************************/ +#ifndef XGPIOPS_HW_H /* prevent circular inclusions */ +#define XGPIOPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register offsets for the GPIO. Each register is 32 bits. + * @{ + */ +#define XGPIOPS_DATA_LSW_OFFSET 0x000 /* Mask and Data Register LSW, WO */ +#define XGPIOPS_DATA_MSW_OFFSET 0x004 /* Mask and Data Register MSW, WO */ +#define XGPIOPS_DATA_OFFSET 0x040 /* Data Register, RW */ +#define XGPIOPS_DATA_RO_OFFSET 0x060 /* Data Register - Input, RO */ +#define XGPIOPS_DIRM_OFFSET 0x204 /* Direction Mode Register, RW */ +#define XGPIOPS_OUTEN_OFFSET 0x208 /* Output Enable Register, RW */ +#define XGPIOPS_INTMASK_OFFSET 0x20C /* Interrupt Mask Register, RO */ +#define XGPIOPS_INTEN_OFFSET 0x210 /* Interrupt Enable Register, WO */ +#define XGPIOPS_INTDIS_OFFSET 0x214 /* Interrupt Disable Register, WO*/ +#define XGPIOPS_INTSTS_OFFSET 0x218 /* Interrupt Status Register, RO */ +#define XGPIOPS_INTTYPE_OFFSET 0x21C /* Interrupt Type Register, RW */ +#define XGPIOPS_INTPOL_OFFSET 0x220 /* Interrupt Polarity Register, RW */ +#define XGPIOPS_INTANY_OFFSET 0x224 /* Interrupt On Any Register, RW */ +/* @} */ + +/** @name Register offsets for each Bank. + * @{ + */ +#define XGPIOPS_DATA_MASK_OFFSET 0x8 /* Data/Mask Registers offset */ +#define XGPIOPS_DATA_BANK_OFFSET 0x4 /* Data Registers offset */ +#define XGPIOPS_REG_MASK_OFFSET 0x40 /* Registers offset */ +/* @} */ + +/* For backwards compatibility */ +#define XGPIOPS_BYPM_MASK_OFFSET XGPIOPS_REG_MASK_OFFSET + +/** @name Interrupt type reset values for each bank + * @{ + */ +#define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFF +#define XGPIOPS_INTTYPE_BANK1_RESET 0x3FFFFFFF +#define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFF +#define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFF +/* @} */ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* This macro reads the given register. +* +* @param BaseAddr is the base address of the device. +* @param RegOffset is the register offset to be read. +* +* @return The 32-bit value of the register +* +* @note None. +* +*****************************************************************************/ +#define XGpioPs_ReadReg(BaseAddr, RegOffset) \ + Xil_In32((BaseAddr) + (RegOffset)) + +/****************************************************************************/ +/** +* +* This macro writes to the given register. +* +* @param BaseAddr is the base address of the device. +* @param RegOffset is the offset of the register to be written. +* @param Data is the 32-bit value to write to the register. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \ + Xil_Out32((BaseAddr) + (RegOffset), (Data)) + +/************************** Function Prototypes ******************************/ + +void XGpioPs_ResetHw(u32 BaseAddress); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XGPIOPS_HW_H */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xiicps.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xiicps.h new file mode 100644 index 000000000..92afb51a0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xiicps.h @@ -0,0 +1,410 @@ +/****************************************************************************** +* +* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xiicps.h +* +* This is an implementation of IIC driver in the PS block. The device can +* be either a master or a slave on the IIC bus. This implementation supports +* both interrupt mode transfer and polled mode transfer. Only 7-bit address +* is used in the driver, although the hardware also supports 10-bit address. +* +* IIC is a 2-wire serial interface. The master controls the clock, so it can +* regulate when it wants to send or receive data. The slave is under control of +* the master, it must respond quickly since it has no control of the clock and +* must send/receive data as fast or as slow as the master does. +* +* The higher level software must implement a higher layer protocol to inform +* the slave what to send to the master. +* +* Initialization & Configuration +* +* The XIicPs_Config structure is used by the driver to configure itself. This +* configuration structure is typically created by the tool-chain based on HW +* build properties. +* +* To support multiple runtime loading and initialization strategies employed by +* various operating systems, the driver instance can be initialized in the +* following way: +* +* - XIicPs_LookupConfig(DeviceId) - Use the device identifier to find +* the static configuration structure defined in xiicps_g.c. This is +* setup by the tools. For some operating systems the config structure +* will be initialized by the software and this call is not needed. +* +* - XIicPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a +* configuration structure provided by the caller. If running in a +* system with address translation, the provided virtual memory base +* address replaces the physical address in the configuration +* structure. +* +* Multiple Masters +* +* More than one master can exist, bus arbitration is defined in the IIC +* standard. Lost of arbitration causes arbitration loss interrupt on the device. +* +* Multiple Slaves +* +* Multiple slaves are supported by selecting them with unique addresses. It is +* up to the system designer to be sure all devices on the IIC bus have +* unique addresses. +* +* Addressing +* +* The IIC hardware can use 7 or 10 bit addresses. The driver provides the +* ability to control which address size is sent in messages as a master to a +* slave device. +* +* FIFO Size +* The hardware FIFO is 32 bytes deep. The user must know the limitations of +* other IIC devices on the bus. Some are only able to receive a limited number +* of bytes in a single transfer. +* +* Data Rates +* +* The data rate is set by values in the control register. The formula for +* determining the correct register values is: +* Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1)) +* +* When the device is configured as a slave, the slck setting controls the +* sample rate and so must be set to be at least as fast as the fastest scl +* expected to be seen in the system. +* +* Polled Mode Operation +* +* This driver supports polled mode transfers. +* +* Interrupts +* +* The user must connect the interrupt handler of the driver, +* XIicPs_InterruptHandler to an interrupt system such that it will be called +* when an interrupt occurs. This function does not save and restore the +* processor context such that the user must provide this processing. +* +* The driver handles the following interrupts: +* - Transfer complete +* - More Data +* - Transfer not Acknowledged +* - Transfer Time out +* - Monitored slave ready - master mode only +* - Receive Overflow +* - Transmit FIFO overflow +* - Receive FIFO underflow +* - Arbitration lost +* +* Bus Busy +* +* Bus busy is checked before the setup of a master mode device, to avoid +* unnecessary arbitration loss interrupt. +* +* RTOS Independence +* +* This driver is intended to be RTOS and processor independent. It works with +* physical addresses only. Any needs for dynamic memory management, threads or +* thread mutual exclusion, virtual memory, or cache control must be satisfied by +* the layer above this driver. +* +* @note +* . Less than FIFO size transfers work for both 100 KHz and 400 KHz. +* . Larger than FIFO size interrupt-driven transfers are not reliable on +* busy systems where interrupt latency is high. +* . Larger than FIFO size interrupt-driven transfers are not reliable for +* data rate of 400 KHz. +* . Larger than FIFO size polled mode transfers work reliably. +* +* 
 MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- -----------------------------------------------
+* 1.00a drg/jz  01/30/08 First release
+* 1.00a sdm     09/21/11 Fixed an issue in the XIicPs_SetOptions and
+*			 XIicPs_ClearOptions where the InstancePtr->Options
+*			 was not updated correctly.
+* 			 Updated the InstancePtr->Options in the
+*			 XIicPs_CfgInitialize by calling XIicPs_GetOptions.
+*			 Updated the XIicPs_SetupMaster to not check for
+*			 Bus Busy condition when the Hold Bit is set.
+*			 Removed some unused variables.
+* 1.01a sg      03/30/12 Fixed an issue in XIicPs_MasterSendPolled where a
+*			 check for transfer completion is added, which indicates
+*			 the completion of current transfer.
+* 1.02a sg	08/29/12 Updated the logic to arrive at the best divisors
+*			 to achieve I2C clock with minimum error for
+*			 CR #674195
+* 1.03a hk  05/04/13 Initialized BestDivA and BestDivB to 0.
+*			 This is fix for CR#704398 to remove warning.
+* 2.0   hk  03/07/14 Added check for error status in the while loop that
+*                    checks for completion.
+*                    (XIicPs_MasterSendPolled function). CR# 762244, 764875.
+*                    Limited frequency set when 100KHz or 400KHz is
+*                    selected. This is a hardware limitation. CR#779290.
+* 2.1   hk  04/24/14 Fix for CR# 789821 to handle >14 byte transfers.
+*                    Explicitly reset CR and clear FIFO in Abort function
+*                    and state the same in the comments. CR# 784254.
+*                    Fix for CR# 761060 - provision for repeated start.
+*
+*
+* +******************************************************************************/ + +#ifndef XIICPS_H /* prevent circular inclusions */ +#define XIICPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xiicps_hw.h" + +/************************** Constant Definitions *****************************/ + +/** @name Configuration options + * + * The following options may be specified or retrieved for the device and + * enable/disable additional features of the IIC. Each of the options + * are bit fields, so more than one may be specified. + * + * @{ + */ +#define XIICPS_7_BIT_ADDR_OPTION 0x01 /**< 7-bit address mode */ +#define XIICPS_10_BIT_ADDR_OPTION 0x02 /**< 10-bit address mode */ +#define XIICPS_SLAVE_MON_OPTION 0x04 /**< Slave monitor mode */ +#define XIICPS_REP_START_OPTION 0x08 /**< Repeated Start */ +/*@}*/ + +/** @name Callback events + * + * These constants specify the handler events that are passed to an application + * event handler from the driver. These constants are bit masks such that + * more than one event can be passed to the handler. + * + * @{ + */ +#define XIICPS_EVENT_COMPLETE_SEND 0x0001 /**< Transmit Complete Event*/ +#define XIICPS_EVENT_COMPLETE_RECV 0x0002 /**< Receive Complete Event*/ +#define XIICPS_EVENT_TIME_OUT 0x0004 /**< Transfer timed out */ +#define XIICPS_EVENT_ERROR 0x0008 /**< Receive error */ +#define XIICPS_EVENT_ARB_LOST 0x0010 /**< Arbitration lost */ +#define XIICPS_EVENT_NACK 0x0020 /**< NACK Received */ +#define XIICPS_EVENT_SLAVE_RDY 0x0040 /**< Slave ready */ +#define XIICPS_EVENT_RX_OVR 0x0080 /**< RX overflow */ +#define XIICPS_EVENT_TX_OVR 0x0100 /**< TX overflow */ +#define XIICPS_EVENT_RX_UNF 0x0200 /**< RX underflow */ +/*@}*/ + +/** @name Role constants + * + * These constants are used to pass into the device setup routines to + * set up the device according to transfer direction. + */ +#define SENDING_ROLE 1 /**< Transfer direction is sending */ +#define RECVING_ROLE 0 /**< Transfer direction is receiving */ + +/* Maximum transfer size */ +#define XIICPS_MAX_TRANSFER_SIZE (255 - 3) + +/**************************** Type Definitions *******************************/ + +/** +* The handler data type allows the user to define a callback function to +* respond to interrupt events in the system. This function is executed +* in interrupt context, so amount of processing should be minimized. +* +* @param CallBackRef is the callback reference passed in by the upper +* layer when setting the callback functions, and passed back to +* the upper layer when the callback is invoked. Its type is +* not important to the driver, so it is a void pointer. +* @param StatusEvent indicates one or more status events that occurred. +*/ +typedef void (*XIicPs_IntrHandler) (void *CallBackRef, u32 StatusEvent); + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Base address of the device */ + u32 InputClockHz; /**< Input clock frequency */ +} XIicPs_Config; + +/** + * The XIicPs driver instance data. The user is required to allocate a + * variable of this type for each IIC device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XIicPs_Config Config; /* Configuration structure */ + u32 IsReady; /* Device is initialized and ready */ + u32 Options; /* Options set in the device */ + + u8 *SendBufferPtr; /* Pointer to send buffer */ + u8 *RecvBufferPtr; /* Pointer to recv buffer */ + int SendByteCount; /* Number of bytes still expected to send */ + int RecvByteCount; /* Number of bytes still expected to receive */ + int CurrByteCount; /* No. of bytes expected in current transfer */ + + int UpdateTxSize; /* If tx size register has to be updated */ + int IsSend; /* Whether master is sending or receiving */ + int IsRepeatedStart; /* Indicates if user set repeated start */ + + XIicPs_IntrHandler StatusHandler; /* Event handler function */ + void *CallBackRef; /* Callback reference for event handler */ +} XIicPs; + +/***************** Macros (Inline Functions) Definitions *********************/ +/****************************************************************************/ +/* +* +* Place one byte into the transmit FIFO. +* +* @param InstancePtr is the instance of IIC +* +* @return None. +* +* @note C-Style signature: +* void XIicPs_SendByte(XIicPs *InstancePtr) +* +*****************************************************************************/ +#define XIicPs_SendByte(InstancePtr) \ +{ \ + XIicPs_Out32((InstancePtr)->Config.BaseAddress \ + + XIICPS_DATA_OFFSET, \ + *(InstancePtr)->SendBufferPtr ++); \ + (InstancePtr)->SendByteCount --; \ +} + +/****************************************************************************/ +/* +* +* Receive one byte from FIFO. +* +* @param InstancePtr is the instance of IIC +* +* @return None. +* +* @note C-Style signature: +* u8 XIicPs_RecvByte(XIicPs *InstancePtr) +* +*****************************************************************************/ +#define XIicPs_RecvByte(InstancePtr) \ +{ \ + *(InstancePtr)->RecvBufferPtr ++ = \ + (u8)XIicPs_In32((InstancePtr)->Config.BaseAddress \ + + XIICPS_DATA_OFFSET); \ + (InstancePtr)->RecvByteCount --; \ +} + +/************************** Function Prototypes ******************************/ + +/* + * Function for configuration lookup, in xiicps_sinit.c + */ +XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId); + +/* + * Functions for general setup, in xiicps.c + */ +int XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config * Config, + u32 EffectiveAddr); + +void XIicPs_Abort(XIicPs *InstancePtr); +void XIicPs_Reset(XIicPs *InstancePtr); + +int XIicPs_BusIsBusy(XIicPs *InstancePtr); + +/* + * Functions for interrupts, in xiicps_intr.c + */ +void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef, + XIicPs_IntrHandler FuncPtr); + +/* + * Functions for device as master, in xiicps_master.c + */ +void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount, + u16 SlaveAddr); +void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount, + u16 SlaveAddr); +int XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount, + u16 SlaveAddr); +int XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount, + u16 SlaveAddr); +void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr); +void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr); +void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr); + +/* + * Functions for device as slave, in xiicps_slave.c + */ +void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr); +void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount); +void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount); +int XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount); +int XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount); +void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr); + +/* + * Functions for selftest, in xiicps_selftest.c + */ +int XIicPs_SelfTest(XIicPs *InstancePtr); + +/* + * Functions for setting and getting data rate, in xiicps_options.c + */ +int XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options); +int XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options); +u32 XIicPs_GetOptions(XIicPs *InstancePtr); + +int XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz); +u32 XIicPs_GetSClk(XIicPs *InstancePtr); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xiicps_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xiicps_hw.h new file mode 100644 index 000000000..406892c7c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xiicps_hw.h @@ -0,0 +1,388 @@ +/****************************************************************************** +* +* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xiicps_hw.h +* +* This header file contains the hardware definition for an IIC device. +* It includes register definitions and interface functions to read/write +* the registers. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who 	Date     Changes
+* ----- ------  -------- -----------------------------------------------
+* 1.00a drg/jz  01/30/10 First release
+* 1.04a kpc		11/07/13 Added function prototype. 
+*
+* +******************************************************************************/ +#ifndef XIICPS_HW_H /* prevent circular inclusions */ +#define XIICPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * + * Register offsets for the IIC. + * @{ + */ +#define XIICPS_CR_OFFSET 0x00 /**< 32-bit Control */ +#define XIICPS_SR_OFFSET 0x04 /**< Status */ +#define XIICPS_ADDR_OFFSET 0x08 /**< IIC Address */ +#define XIICPS_DATA_OFFSET 0x0C /**< IIC FIFO Data */ +#define XIICPS_ISR_OFFSET 0x10 /**< Interrupt Status */ +#define XIICPS_TRANS_SIZE_OFFSET 0x14 /**< Transfer Size */ +#define XIICPS_SLV_PAUSE_OFFSET 0x18 /**< Slave monitor pause */ +#define XIICPS_TIME_OUT_OFFSET 0x1C /**< Time Out */ +#define XIICPS_IMR_OFFSET 0x20 /**< Interrupt Enabled Mask */ +#define XIICPS_IER_OFFSET 0x24 /**< Interrupt Enable */ +#define XIICPS_IDR_OFFSET 0x28 /**< Interrupt Disable */ +/* @} */ + +/** @name Control Register + * + * This register contains various control bits that + * affects the operation of the IIC controller. Read/Write. + * @{ + */ + +#define XIICPS_CR_DIV_A_MASK 0x0000C000 /**< Clock Divisor A */ +#define XIICPS_CR_DIV_A_SHIFT 14 /**< Clock Divisor A shift */ +#define XIICPS_DIV_A_MAX 4 /**< Maximum value of Divisor A */ +#define XIICPS_CR_DIV_B_MASK 0x00003F00 /**< Clock Divisor B */ +#define XIICPS_CR_DIV_B_SHIFT 8 /**< Clock Divisor B shift */ +#define XIICPS_CR_CLR_FIFO_MASK 0x00000040 /**< Clear FIFO, auto clears*/ +#define XIICPS_CR_SLVMON_MASK 0x00000020 /**< Slave monitor mode */ +#define XIICPS_CR_HOLD_MASK 0x00000010 /**< Hold bus 1=Hold scl, + 0=terminate transfer */ +#define XIICPS_CR_ACKEN_MASK 0x00000008 /**< Enable TX of ACK when + Master receiver*/ +#define XIICPS_CR_NEA_MASK 0x00000004 /**< Addressing Mode 1=7 bit, + 0=10 bit */ +#define XIICPS_CR_MS_MASK 0x00000002 /**< Master mode bit 1=Master, + 0=Slave */ +#define XIICPS_CR_RD_WR_MASK 0x00000001 /**< Read or Write Master + transfer 0=Transmitter, + 1=Receiver*/ +#define XIICPS_CR_RESET_VALUE 0 /**< Reset value of the Control + register */ +/* @} */ + +/** @name IIC Status Register + * + * This register is used to indicate status of the IIC controller. Read only + * @{ + */ +#define XIICPS_SR_BA_MASK 0x00000100 /**< Bus Active Mask */ +#define XIICPS_SR_RXOVF_MASK 0x00000080 /**< Receiver Overflow Mask */ +#define XIICPS_SR_TXDV_MASK 0x00000040 /**< Transmit Data Valid Mask */ +#define XIICPS_SR_RXDV_MASK 0x00000020 /**< Receiver Data Valid Mask */ +#define XIICPS_SR_RXRW_MASK 0x00000008 /**< Receive read/write Mask */ +/* @} */ + +/** @name IIC Address Register + * + * Normal addressing mode uses add[6:0]. Extended addressing mode uses add[9:0]. + * A write access to this register always initiates a transfer if the IIC is in + * master mode. Read/Write + * @{ + */ +#define XIICPS_ADDR_MASK 0x000003FF /**< IIC Address Mask */ +/* @} */ + +/** @name IIC Data Register + * + * When written to, the data register sets data to transmit. When read from, the + * data register reads the last received byte of data. Read/Write + * @{ + */ +#define XIICPS_DATA_MASK 0x000000FF /**< IIC Data Mask */ +/* @} */ + +/** @name IIC Interrupt Registers + * + * IIC Interrupt Status Register + * + * This register holds the interrupt status flags for the IIC controller. Some + * of the flags are level triggered + * - i.e. are set as long as the interrupt condition exists. Other flags are + * edge triggered, which means they are set one the interrupt condition occurs + * then remain set until they are cleared by software. + * The interrupts are cleared by writing a one to the interrupt bit position + * in the Interrupt Status Register. Read/Write. + * + * IIC Interrupt Enable Register + * + * This register is used to enable interrupt sources for the IIC controller. + * Writing a '1' to a bit in this register clears the corresponding bit in the + * IIC Interrupt Mask register. Write only. + * + * IIC Interrupt Disable Register + * + * This register is used to disable interrupt sources for the IIC controller. + * Writing a '1' to a bit in this register sets the corresponding bit in the + * IIC Interrupt Mask register. Write only. + * + * IIC Interrupt Mask Register + * + * This register shows the enabled/disabled status of each IIC controller + * interrupt source. A bit set to 1 will ignore the corresponding interrupt in + * the status register. A bit set to 0 means the interrupt is enabled. + * All mask bits are set and all interrupts are disabled after reset. Read only. + * + * All four registers have the same bit definitions. They are only defined once + * for each of the Interrupt Enable Register, Interrupt Disable Register, + * Interrupt Mask Register, and Interrupt Status Register + * @{ + */ + +#define XIICPS_IXR_ARB_LOST_MASK 0x00000200 /**< Arbitration Lost Interrupt + mask */ +#define XIICPS_IXR_RX_UNF_MASK 0x00000080 /**< FIFO Recieve Underflow + Interrupt mask */ +#define XIICPS_IXR_TX_OVR_MASK 0x00000040 /**< Transmit Overflow + Interrupt mask */ +#define XIICPS_IXR_RX_OVR_MASK 0x00000020 /**< Receive Overflow Interrupt + mask */ +#define XIICPS_IXR_SLV_RDY_MASK 0x00000010 /**< Monitored Slave Ready + Interrupt mask */ +#define XIICPS_IXR_TO_MASK 0x00000008 /**< Transfer Time Out + Interrupt mask */ +#define XIICPS_IXR_NACK_MASK 0x00000004 /**< NACK Interrupt mask */ +#define XIICPS_IXR_DATA_MASK 0x00000002 /**< Data Interrupt mask */ +#define XIICPS_IXR_COMP_MASK 0x00000001 /**< Transfer Complete + Interrupt mask */ +#define XIICPS_IXR_DEFAULT_MASK 0x000002FF /**< Default ISR Mask */ +#define XIICPS_IXR_ALL_INTR_MASK 0x000002FF /**< All ISR Mask */ +/* @} */ + + +/** @name IIC Transfer Size Register +* +* The register's meaning varies according to the operating mode as follows: +* - Master transmitter mode: number of data bytes still not transmitted minus +* one +* - Master receiver mode: number of data bytes that are still expected to be +* received +* - Slave transmitter mode: number of bytes remaining in the FIFO after the +* master terminates the transfer +* - Slave receiver mode: number of valid data bytes in the FIFO +* +* This register is cleared if CLR_FIFO bit in the control register is set. +* Read/Write +* @{ +*/ +#define XIICPS_TRANS_SIZE_MASK 0x0000003F /**< IIC Transfer Size Mask */ +#define XIICPS_FIFO_DEPTH 16 /**< Number of bytes in the FIFO */ +#define XIICPS_DATA_INTR_DEPTH 14 /**< Number of bytes at DATA intr */ +/* @} */ + + +/** @name IIC Slave Monitor Pause Register +* +* This register is associated with the slave monitor mode of the I2C interface. +* It is meaningful only when the module is in master mode and bit SLVMON in the +* control register is set. +* +* This register defines the pause interval between consecutive attempts to +* address the slave once a write to an I2C address register is done by the +* host. It represents the number of sclk cycles minus one between two attempts. +* +* The reset value of the register is 0, which results in the master repeatedly +* trying to access the slave immediately after unsuccessful attempt. +* Read/Write +* @{ +*/ +#define XIICPS_SLV_PAUSE_MASK 0x0000000F /**< Slave monitor pause mask */ +/* @} */ + + +/** @name IIC Time Out Register +* +* The value of time out register represents the time out interval in number of +* sclk cycles minus one. +* +* When the accessed slave holds the sclk line low for longer than the time out +* period, thus prohibiting the I2C interface in master mode to complete the +* current transfer, an interrupt is generated and TO interrupt flag is set. +* +* The reset value of the register is 0x1f. +* Read/Write +* @{ + */ +#define XIICPS_TIME_OUT_MASK 0x000000FF /**< IIC Time Out mask */ +#define XIICPS_TO_RESET_VALUE 0x0000001F /**< IIC Time Out reset value */ +/* @} */ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +#define XIicPs_In32 Xil_In32 +#define XIicPs_Out32 Xil_Out32 + +/****************************************************************************/ +/** +* Read an IIC register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to select the specific register. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u32 XIicPs_ReadReg(u32 BaseAddress. int RegOffset) +* +******************************************************************************/ +#define XIicPs_ReadReg(BaseAddress, RegOffset) \ + XIicPs_In32((BaseAddress) + (RegOffset)) + +/***************************************************************************/ +/** +* Write an IIC register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to select the specific register. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XIicPs_WriteReg(u32 BaseAddress, int RegOffset, u32 RegisterValue) +* +******************************************************************************/ +#define XIicPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ + XIicPs_Out32((BaseAddress) + (RegOffset), (RegisterValue)) + +/***************************************************************************/ +/** +* Read the interrupt enable register. +* +* @param BaseAddress contains the base address of the device. +* +* @return Current bit mask that represents currently enabled interrupts. +* +* @note C-Style signature: +* u32 XIicPs_ReadIER(u32 BaseAddress) +* +******************************************************************************/ +#define XIicPs_ReadIER(BaseAddress) \ + XIicPs_ReadReg((BaseAddress), XIICPS_IER_OFFSET) + +/***************************************************************************/ +/** +* Write to the interrupt enable register. +* +* @param BaseAddress contains the base address of the device. +* +* @param IntrMask is the interrupts to be enabled. +* +* @return None. +* +* @note C-Style signature: +* void XIicPs_EnabledInterrupts(u32 BaseAddress, u32 IntrMask) +* +******************************************************************************/ +#define XIicPs_EnableInterrupts(BaseAddress, IntrMask) \ + XIicPs_WriteReg((BaseAddress), XIICPS_IER_OFFSET, (IntrMask)) + +/***************************************************************************/ +/** +* Disable all interrupts. +* +* @param BaseAddress contains the base address of the device. +* +* @return None. +* +* @note C-Style signature: +* void XIicPs_DisableAllInterrupts(u32 BaseAddress) +* +******************************************************************************/ +#define XIicPs_DisableAllInterrupts(BaseAddress) \ + XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \ + XIICPS_IXR_ALL_INTR_MASK) + +/***************************************************************************/ +/** +* Disable selected interrupts. +* +* @param BaseAddress contains the base address of the device. +* +* @param IntrMask is the interrupts to be disabled. +* +* @return None. +* +* @note C-Style signature: +* void XIicPs_DisableInterrupts(u32 BaseAddress, u32 IntrMask) +* +******************************************************************************/ +#define XIicPs_DisableInterrupts(BaseAddress, IntrMask) \ + XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \ + (IntrMask)) + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ +/* + * Perform reset operation to the I2c interface + */ +void XIicPs_ResetHw(u32 BaseAddr); +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_assert.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_assert.h new file mode 100644 index 000000000..d08663b7c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_assert.h @@ -0,0 +1,196 @@ +/****************************************************************************** +* +* (c) Copyright 2009 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_assert.h +* +* This file contains assert related functions. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 First release
+*
+* +******************************************************************************/ + +#ifndef XIL_ASSERT_H /* prevent circular inclusions */ +#define XIL_ASSERT_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + + +/***************************** Include Files *********************************/ + + +/************************** Constant Definitions *****************************/ + +#define XIL_ASSERT_NONE 0 +#define XIL_ASSERT_OCCURRED 1 +#define XNULL NULL + +extern unsigned int Xil_AssertStatus; +extern void Xil_Assert(const char *, int); +void XNullHandler(void *NullParameter); + +/** + * This data type defines a callback to be invoked when an + * assert occurs. The callback is invoked only when asserts are enabled + */ +typedef void (*Xil_AssertCallback) (const char *File, int Line); + +/***************** Macros (Inline Functions) Definitions *********************/ + +#ifndef NDEBUG + +/*****************************************************************************/ +/** +* This assert macro is to be used for functions that do not return anything +* (void). This in conjunction with the Xil_AssertWait boolean can be used to +* accomodate tests so that asserts which fail allow execution to continue. +* +* @param expression is the expression to evaluate. If it evaluates to +* false, the assert occurs. +* +* @return Returns void unless the Xil_AssertWait variable is true, in which +* case no return is made and an infinite loop is entered. +* +* @note None. +* +******************************************************************************/ +#define Xil_AssertVoid(Expression) \ +{ \ + if (Expression) { \ + Xil_AssertStatus = XIL_ASSERT_NONE; \ + } else { \ + Xil_Assert(__FILE__, __LINE__); \ + Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ + return; \ + } \ +} + +/*****************************************************************************/ +/** +* This assert macro is to be used for functions that do return a value. This in +* conjunction with the Xil_AssertWait boolean can be used to accomodate tests +* so that asserts which fail allow execution to continue. +* +* @param expression is the expression to evaluate. If it evaluates to false, +* the assert occurs. +* +* @return Returns 0 unless the Xil_AssertWait variable is true, in which +* case no return is made and an infinite loop is entered. +* +* @note None. +* +******************************************************************************/ +#define Xil_AssertNonvoid(Expression) \ +{ \ + if (Expression) { \ + Xil_AssertStatus = XIL_ASSERT_NONE; \ + } else { \ + Xil_Assert(__FILE__, __LINE__); \ + Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ + return 0; \ + } \ +} + +/*****************************************************************************/ +/** +* Always assert. This assert macro is to be used for functions that do not +* return anything (void). Use for instances where an assert should always +* occur. +* +* @return Returns void unless the Xil_AssertWait variable is true, in which +* case no return is made and an infinite loop is entered. +* +* @note None. +* +******************************************************************************/ +#define Xil_AssertVoidAlways() \ +{ \ + Xil_Assert(__FILE__, __LINE__); \ + Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ + return; \ +} + +/*****************************************************************************/ +/** +* Always assert. This assert macro is to be used for functions that do return +* a value. Use for instances where an assert should always occur. +* +* @return Returns void unless the Xil_AssertWait variable is true, in which +* case no return is made and an infinite loop is entered. +* +* @note None. +* +******************************************************************************/ +#define Xil_AssertNonvoidAlways() \ +{ \ + Xil_Assert(__FILE__, __LINE__); \ + Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ + return 0; \ +} + + +#else + +#define Xil_AssertVoid(Expression) +#define Xil_AssertVoidAlways() +#define Xil_AssertNonvoid(Expression) +#define Xil_AssertNonvoidAlways() + +#endif + +/************************** Function Prototypes ******************************/ + +void Xil_AssertSetCallback(Xil_AssertCallback Routine); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_cache.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_cache.h new file mode 100644 index 000000000..e1e0adaac --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_cache.h @@ -0,0 +1,84 @@ +/****************************************************************************** +* +* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_cache.h +* +* Contains required functions for the ARM cache functionality +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  01/29/10 First release
+* 3.04a sdm  01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
+*		      APIs.
+*
+* +******************************************************************************/ +#ifndef XIL_CACHE_H +#define XIL_CACHE_H + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void Xil_DCacheEnable(void); +void Xil_DCacheDisable(void); +void Xil_DCacheInvalidate(void); +void Xil_DCacheInvalidateRange(unsigned int adr, unsigned len); +void Xil_DCacheFlush(void); +void Xil_DCacheFlushRange(unsigned int adr, unsigned len); + +void Xil_ICacheEnable(void); +void Xil_ICacheDisable(void); +void Xil_ICacheInvalidate(void); +void Xil_ICacheInvalidateRange(unsigned int adr, unsigned len); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_cache_l.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_cache_l.h new file mode 100644 index 000000000..d0c3f40e6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_cache_l.h @@ -0,0 +1,103 @@ +/****************************************************************************** +* +* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_cache_l.h +* +* Contains L1 and L2 specific functions for the ARM cache functionality +* used by xcache.c. This functionality is being made available here for +* more sophisticated users. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  01/24/10 First release
+*
+* +******************************************************************************/ +#ifndef XIL_CACHE_MACH_H +#define XIL_CACHE_MACH_H + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Function Prototypes ******************************/ + +void Xil_DCacheInvalidateLine(unsigned int adr); +void Xil_DCacheFlushLine(unsigned int adr); +void Xil_DCacheStoreLine(unsigned int adr); +void Xil_ICacheInvalidateLine(unsigned int adr); + +void Xil_L1DCacheEnable(void); +void Xil_L1DCacheDisable(void); +void Xil_L1DCacheInvalidate(void); +void Xil_L1DCacheInvalidateLine(unsigned int adr); +void Xil_L1DCacheInvalidateRange(unsigned int adr, unsigned len); +void Xil_L1DCacheFlush(void); +void Xil_L1DCacheFlushLine(unsigned int adr); +void Xil_L1DCacheFlushRange(unsigned int adr, unsigned len); +void Xil_L1DCacheStoreLine(unsigned int adr); + +void Xil_L1ICacheEnable(void); +void Xil_L1ICacheDisable(void); +void Xil_L1ICacheInvalidate(void); +void Xil_L1ICacheInvalidateLine(unsigned int adr); +void Xil_L1ICacheInvalidateRange(unsigned int adr, unsigned len); + +void Xil_L2CacheEnable(void); +void Xil_L2CacheDisable(void); +void Xil_L2CacheInvalidate(void); +void Xil_L2CacheInvalidateLine(unsigned int adr); +void Xil_L2CacheInvalidateRange(unsigned int adr, unsigned len); +void Xil_L2CacheFlush(void); +void Xil_L2CacheFlushLine(unsigned int adr); +void Xil_L2CacheFlushRange(unsigned int adr, unsigned len); +void Xil_L2CacheStoreLine(unsigned int adr); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h new file mode 100644 index 000000000..3ad8965df --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h @@ -0,0 +1,103 @@ +/****************************************************************************** +* +* (c) Copyright 2009 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_cache_vxworks.h +* +* Contains the cache related functions for VxWorks that is wrapped by +* xil_cache. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  12/11/09 Initial release
+*
+*
+* +* @note +* +******************************************************************************/ + +#ifndef XIL_CACHE_VXWORKS_H +#define XIL_CACHE_VXWORKS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "vxWorks.h" +#include "vxLib.h" +#include "sysLibExtra.h" +#include "cacheLib.h" + +#if (CPU_FAMILY==PPC) + +#define Xil_DCacheEnable() cacheEnable(DATA_CACHE) + +#define Xil_DCacheDisable() cacheDisable(DATA_CACHE) + +#define Xil_DCacheInvalidateRange(Addr, Len) \ + cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len)) + +#define Xil_DCacheFlushRange(Addr, Len) \ + cacheFlush(DATA_CACHE, (void *)(Addr), (Len)) + +#define Xil_ICacheEnable() cacheEnable(INSTRUCTION_CACHE) + +#define Xil_ICacheDisable() cacheDisable(INSTRUCTION_CACHE) + +#define Xil_ICacheInvalidateRange(Addr, Len) \ + cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len)) + + +#else +#error "Unknown processor / architecture. Must be PPC for VxWorks." +#endif + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_errata.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_errata.h new file mode 100644 index 000000000..bb09eef3f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_errata.h @@ -0,0 +1,117 @@ +/******************************************************************************* +* +* (c) Copyright 2013 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +*******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_errata.h +* +* This header file contains Cortex A9 and PL310 Errata definitions. +* +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a srt  04/18/13 First release
+*
+* +******************************************************************************/ +#ifndef XIL_ERRATA_H +#define XIL_ERRATA_H + +#define ENABLE_ARM_ERRATA 1 + +#ifdef ENABLE_ARM_ERRATA +/* Cortex A9 ARM Errata */ + +/* + * Errata No: 742230 + * Description: DMB operation may be faulty + */ +#define CONFIG_ARM_ERRATA_742230 1 + +/* + * Errata No: 743622 + * Description: Faulty hazard checking in the Store Buffer may lead + * to data corruption. + */ +#define CONFIG_ARM_ERRATA_743622 1 + +/* + * Errata No: 775420 + * Description: A data cache maintenance operation which aborts, + * might lead to deadlock + */ +#define CONFIG_ARM_ERRATA_775420 1 + +/* + * Errata No: 794073 + * Description: Speculative instruction fetches with MMU disabled + * might not comply with architectural requirements + */ +#define CONFIG_ARM_ERRATA_794073 1 + + +/* PL310 L2 Cache Errata */ + +/* + * Errata No: 588369 + * Description: Clean & Invalidate maintenance operations do not + * invalidate clean lines + */ +#define CONFIG_PL310_ERRATA_588369 1 + +/* + * Errata No: 727915 + * Description: Background Clean and Invalidate by Way operation + * can cause data corruption + */ +#define CONFIG_PL310_ERRATA_727915 1 + +/* + * Errata No: 753970 + * Description: Cache sync operation may be faulty + */ +#define CONFIG_PL310_ERRATA_753970 1 + +#endif /* ENABLE_ARM_ERRATA */ + +#endif /* XIL_ERRATA_H */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_exception.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_exception.h new file mode 100644 index 000000000..dfe2285e8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_exception.h @@ -0,0 +1,231 @@ +/****************************************************************************** +* +* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_exception.h +* +* This header file contains ARM Cortex A9 specific exception related APIs. +* For exception related functions that can be used across all Xilinx supported +* processors, please use xil_exception.h. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  11/04/09 First release
+*
+* +******************************************************************************/ + +#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */ +#define XIL_EXCEPTION_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xpseudo_asm.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions ****************************/ + +#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE +#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE +#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE) + +#define XIL_EXCEPTION_ID_FIRST 0 +#define XIL_EXCEPTION_ID_RESET 0 +#define XIL_EXCEPTION_ID_UNDEFINED_INT 1 +#define XIL_EXCEPTION_ID_SWI_INT 2 +#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3 +#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4 +#define XIL_EXCEPTION_ID_IRQ_INT 5 +#define XIL_EXCEPTION_ID_FIQ_INT 6 +#define XIL_EXCEPTION_ID_LAST 6 + +/* + * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors. + */ +#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT + +/**************************** Type Definitions ******************************/ + +/** + * This typedef is the exception handler function. + */ +typedef void (*Xil_ExceptionHandler)(void *data); +typedef void (*Xil_InterruptHandler)(void *data); + +/***************** Macros (Inline Functions) Definitions ********************/ + +/****************************************************************************/ +/** +* Enable Exceptions. +* +* @param Mask for exceptions to be enabled. +* +* @return None. +* +* @note If bit is 0, exception is enabled. +* C-Style signature: void Xil_ExceptionEnableMask(Mask); +* +******************************************************************************/ +#ifdef __GNUC__ +#define Xil_ExceptionEnableMask(Mask) \ + mtcpsr(mfcpsr() & ~ (Mask & XIL_EXCEPTION_ALL)) +#else +#define Xil_ExceptionEnableMask(Mask) \ + { register unsigned int Reg __asm("cpsr"); \ + mtcpsr(Reg & ~ (Mask & XIL_EXCEPTION_ALL)) } +#endif + +/****************************************************************************/ +/** +* Enable the IRQ exception. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +#define Xil_ExceptionEnable() \ + Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ) + +/****************************************************************************/ +/** +* Disable Exceptions. +* +* @param Mask for exceptions to be enabled. +* +* @return None. +* +* @note If bit is 1, exception is disabled. +* C-Style signature: Xil_ExceptionDisableMask(Mask); +* +******************************************************************************/ +#ifdef __GNUC__ +#define Xil_ExceptionDisableMask(Mask) \ + mtcpsr(mfcpsr() | (Mask & XIL_EXCEPTION_ALL)) +#else +#define Xil_ExceptionDisableMask(Mask) \ + { register unsigned int Reg __asm("cpsr"); \ + mtcpsr(Reg | (Mask & XIL_EXCEPTION_ALL)) } +#endif + +/****************************************************************************/ +/** +* Disable the IRQ exception. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +#define Xil_ExceptionDisable() \ + Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ) + +/****************************************************************************/ +/** +* Enable nested interrupts by clearing the I and F bits it CPSR +* +* @return None. +* +* @note This macro is supposed to be used from interrupt handlers. In the +* interrupt handler the interrupts are disabled by default (I and F +* are 1). To allow nesting of interrupts, this macro should be +* used. It clears the I and F bits by changing the ARM mode to +* system mode. Once these bits are cleared and provided the +* preemption of interrupt conditions are met in the GIC, nesting of +* interrupts will start happening. +* Caution: This macro must be used with caution. Before calling this +* macro, the user must ensure that the source of the current IRQ +* is appropriately cleared. Otherwise, as soon as we clear the I and +* F bits, there can be an infinite loop of interrupts with an +* eventual crash (all the stack space getting consumed). +******************************************************************************/ +#define Xil_EnableNestedInterrupts() \ + __asm__ __volatile__ ("mrs lr, spsr"); \ + __asm__ __volatile__ ("stmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \ + __asm__ __volatile__ ("stmfd sp!, {lr}"); + +/****************************************************************************/ +/** +* Disable the nested interrupts by setting the I and F bits. +* +* @return None. +* +* @note This macro is meant to be called in the interrupt service routines. +* This macro cannot be used independently. It can only be used when +* nesting of interrupts have been enabled by using the macro +* Xil_EnableNestedInterrupts(). In a typical flow, the user first +* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate +* point. The user then must call this macro before exiting the interrupt +* service routine. This macro puts the ARM back in IRQ/FIQ mode and +* hence sets back the I and F bits. +******************************************************************************/ +#define Xil_DisableNestedInterrupts() \ + __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr cpsr_c, #0x92"); \ + __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr spsr_cxsf, lr"); + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +extern void Xil_ExceptionRegisterHandler(u32 id, + Xil_ExceptionHandler handler, + void *data); + +extern void Xil_ExceptionRemoveHandler(u32 id); + +extern void Xil_ExceptionInit(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XIL_EXCEPTION_H */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_hal.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_hal.h new file mode 100644 index 000000000..b58c7eb8a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_hal.h @@ -0,0 +1,71 @@ +/****************************************************************************** +* +* (c) Copyright 2009 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_hal.h +* +* Contains all the HAL header files. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/28/09 Initial release
+*
+*
+* +* @note +* +******************************************************************************/ + +#ifndef XIL_HAL_H +#define XIL_HAL_H + +#include "xil_cache.h" +#include "xil_io.h" +#include "xil_assert.h" +#include "xil_exception.h" +#include "xil_types.h" + +#endif + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_io.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_io.h new file mode 100644 index 000000000..06e83bfa8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_io.h @@ -0,0 +1,254 @@ +/****************************************************************************** +* +* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_io.h +* +* This file contains the interface for the general IO component, which +* encapsulates the Input/Output functions for processors that do not +* require any special I/O handling. +* +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  10/24/09 First release
+* 1.00a sdm      07/21/10 Added Xil_Htonl/s, Xil_Ntohl/s
+* 3.07a asa	     08/31/12 Added xil_printf.h include
+* 3.08a sgd	     11/05/12 Reverted SYNC macros definitions
+*
+******************************************************************************/ + +#ifndef XIL_IO_H /* prevent circular inclusions */ +#define XIL_IO_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xpseudo_asm.h" +#include "xil_printf.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +#if defined __GNUC__ +# define SYNCHRONIZE_IO dmb() +# define INST_SYNC isb() +# define DATA_SYNC dsb() +#else +# define SYNCHRONIZE_IO +# define INST_SYNC +# define DATA_SYNC +#endif /* __GNUC__ */ + +/*****************************************************************************/ +/** +* +* Perform an big-endian input operation for a 16-bit memory location +* by reading from the specified address and returning the Value read from +* that address. +* +* @param Addr contains the address to perform the input operation at. +* +* @return The Value read from the specified input address with the +* proper endianness. The return Value has the same endianness +* as that of the processor, i.e. if the processor is +* little-engian, the return Value is the byte-swapped Value read +* from the address. +* +* @note None. +* +******************************************************************************/ +#define Xil_In16LE(Addr) Xil_In16(Addr) + +/*****************************************************************************/ +/** +* +* Perform a big-endian input operation for a 32-bit memory location +* by reading from the specified address and returning the Value read from +* that address. +* +* @param Addr contains the address to perform the input operation at. +* +* @return The Value read from the specified input address with the +* proper endianness. The return Value has the same endianness +* as that of the processor, i.e. if the processor is +* little-engian, the return Value is the byte-swapped Value read +* from the address. +* +* +* @note None. +* +******************************************************************************/ +#define Xil_In32LE(Addr) Xil_In32(Addr) + +/*****************************************************************************/ +/** +* +* Perform a big-endian output operation for a 16-bit memory location +* by writing the specified Value to the specified address. +* +* @param Addr contains the address to perform the output operation at. +* @param Value contains the Value to be output at the specified address. +* The Value has the same endianness as that of the processor. +* If the processor is little-endian, the byte-swapped Value is +* written to the address. +* +* +* @return None +* +* @note None. +* +******************************************************************************/ +#define Xil_Out16LE(Addr, Value) Xil_Out16(Addr, Value) + +/*****************************************************************************/ +/** +* +* Perform a big-endian output operation for a 32-bit memory location +* by writing the specified Value to the specified address. +* +* @param Addr contains the address to perform the output operation at. +* @param Value contains the Value to be output at the specified address. +* The Value has the same endianness as that of the processor. +* If the processor is little-endian, the byte-swapped Value is +* written to the address. +* +* @return None +* +* @note None. +* +******************************************************************************/ +#define Xil_Out32LE(Addr, Value) Xil_Out32(Addr, Value) + +/*****************************************************************************/ +/** +* +* Convert a 32-bit number from host byte order to network byte order. +* +* @param Data the 32-bit number to be converted. +* +* @return The converted 32-bit number in network byte order. +* +* @note None. +* +******************************************************************************/ +#define Xil_Htonl(Data) Xil_EndianSwap32(Data) + +/*****************************************************************************/ +/** +* +* Convert a 16-bit number from host byte order to network byte order. +* +* @param Data the 16-bit number to be converted. +* +* @return The converted 16-bit number in network byte order. +* +* @note None. +* +******************************************************************************/ +#define Xil_Htons(Data) Xil_EndianSwap16(Data) + +/*****************************************************************************/ +/** +* +* Convert a 32-bit number from network byte order to host byte order. +* +* @param Data the 32-bit number to be converted. +* +* @return The converted 32-bit number in host byte order. +* +* @note None. +* +******************************************************************************/ +#define Xil_Ntohl(Data) Xil_EndianSwap32(Data) + +/*****************************************************************************/ +/** +* +* Convert a 16-bit number from network byte order to host byte order. +* +* @param Data the 16-bit number to be converted. +* +* @return The converted 16-bit number in host byte order. +* +* @note None. +* +******************************************************************************/ +#define Xil_Ntohs(Data) Xil_EndianSwap16(Data) + +/************************** Function Prototypes ******************************/ + +/* The following functions allow the software to be transportable across + * processors which may use memory mapped I/O or I/O which is mapped into a + * seperate address space. + */ +u8 Xil_In8(u32 Addr); +u16 Xil_In16(u32 Addr); +u32 Xil_In32(u32 Addr); + +void Xil_Out8(u32 Addr, u8 Value); +void Xil_Out16(u32 Addr, u16 Value); +void Xil_Out32(u32 Addr, u32 Value); + +u16 Xil_In16BE(u32 Addr); +u32 Xil_In32BE(u32 Addr); +void Xil_Out16BE(u32 Addr, u16 Value); +void Xil_Out32BE(u32 Addr, u32 Value); + +u16 Xil_EndianSwap16(u16 Data); +u32 Xil_EndianSwap32(u32 Data); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_macroback.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_macroback.h new file mode 100644 index 000000000..c614daaf5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_macroback.h @@ -0,0 +1,1069 @@ +/*********************************************************************/ +/** + * (c) Copyright 2010 Xilinx, Inc. All rights reserved. + * + * This file contains confidential and proprietary information + * of Xilinx, Inc. and is protected under U.S. and + * international copyright and other intellectual property + * laws. + * + * DISCLAIMER + * This disclaimer is not a license and does not grant any + * rights to the materials distributed herewith. Except as + * otherwise provided in a valid license issued to you by + * Xilinx, and to the maximum extent permitted by applicable + * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + * (2) Xilinx shall not be liable (whether in contract or tort, + * including negligence, or under any other theory of + * liability) for any loss or damage of any kind or nature + * related to, arising under or in connection with these + * materials, including for any direct, or any indirect, + * special, incidental, or consequential loss or damage + * (including loss of data, profits, goodwill, or any type of + * loss or damage suffered as a result of any action brought + * by a third party) even if such damage or loss was + * reasonably foreseeable or Xilinx had been advised of the + * possibility of the same. + * + * CRITICAL APPLICATIONS + * Xilinx products are not designed or intended to be fail- + * safe, or for use in any application requiring fail-safe + * performance, such as life-support or safety devices or + * systems, Class III medical devices, nuclear facilities, + * applications related to the deployment of airbags, or any + * other applications that could lead to death, personal + * injury, or severe property or environmental damage + * (individually and collectively, "Critical + * Applications"). Customer assumes the sole risk and + * liability of any use of Xilinx products in Critical + * Applications, subject only to applicable laws and + * regulations governing limitations on product liability. + * + * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + * PART OF THIS FILE AT ALL TIMES. + *********************************************************************/ + +/*********************************************************************/ +/** + * @file xil_macroback.h + * + * This header file is meant to bring back the removed _m macros. + * This header file must be included last. + * The following macros are not defined here due to the driver change: + * XGpio_mSetDataDirection + * XGpio_mGetDataReg + * XGpio_mSetDataReg + * XIIC_RESET + * XIIC_CLEAR_STATS + * XSpi_mReset + * XSysAce_mSetCfgAddr + * XSysAce_mIsCfgDone + * XTft_mSetPixel + * XTft_mGetPixel + * XWdtTb_mEnableWdt + * XWdtTb_mDisbleWdt + * XWdtTb_mRestartWdt + * XWdtTb_mGetTimebaseReg + * XWdtTb_mHasReset + * + * Please refer the corresonding driver document for replacement. + * + *********************************************************************/ + +#ifndef XIL_MACROBACK_H +#define XIL_MACROBACK_H + +/*********************************************************************/ +/** + * Macros for Driver XCan + * + *********************************************************************/ +#ifndef XCan_mReadReg +#define XCan_mReadReg XCan_ReadReg +#endif + +#ifndef XCan_mWriteReg +#define XCan_mWriteReg XCan_WriteReg +#endif + +#ifndef XCan_mIsTxDone +#define XCan_mIsTxDone XCan_IsTxDone +#endif + +#ifndef XCan_mIsTxFifoFull +#define XCan_mIsTxFifoFull XCan_IsTxFifoFull +#endif + +#ifndef XCan_mIsHighPriorityBufFull +#define XCan_mIsHighPriorityBufFull XCan_IsHighPriorityBufFull +#endif + +#ifndef XCan_mIsRxEmpty +#define XCan_mIsRxEmpty XCan_IsRxEmpty +#endif + +#ifndef XCan_mIsAcceptFilterBusy +#define XCan_mIsAcceptFilterBusy XCan_IsAcceptFilterBusy +#endif + +#ifndef XCan_mCreateIdValue +#define XCan_mCreateIdValue XCan_CreateIdValue +#endif + +#ifndef XCan_mCreateDlcValue +#define XCan_mCreateDlcValue XCan_CreateDlcValue +#endif + +/*********************************************************************/ +/** + * Macros for Driver XDmaCentral + * + *********************************************************************/ +#ifndef XDmaCentral_mWriteReg +#define XDmaCentral_mWriteReg XDmaCentral_WriteReg +#endif + +#ifndef XDmaCentral_mReadReg +#define XDmaCentral_mReadReg XDmaCentral_ReadReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XDsAdc + * + *********************************************************************/ +#ifndef XDsAdc_mWriteReg +#define XDsAdc_mWriteReg XDsAdc_WriteReg +#endif + +#ifndef XDsAdc_mReadReg +#define XDsAdc_mReadReg XDsAdc_ReadReg +#endif + +#ifndef XDsAdc_mIsEmpty +#define XDsAdc_mIsEmpty XDsAdc_IsEmpty +#endif + +#ifndef XDsAdc_mSetFstmReg +#define XDsAdc_mSetFstmReg XDsAdc_SetFstmReg +#endif + +#ifndef XDsAdc_mGetFstmReg +#define XDsAdc_mGetFstmReg XDsAdc_GetFstmReg +#endif + +#ifndef XDsAdc_mEnableConversion +#define XDsAdc_mEnableConversion XDsAdc_EnableConversion +#endif + +#ifndef XDsAdc_mDisableConversion +#define XDsAdc_mDisableConversion XDsAdc_DisableConversion +#endif + +#ifndef XDsAdc_mGetFifoOccyReg +#define XDsAdc_mGetFifoOccyReg XDsAdc_GetFifoOccyReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XDsDac + * + *********************************************************************/ +#ifndef XDsDac_mWriteReg +#define XDsDac_mWriteReg XDsDac_WriteReg +#endif + +#ifndef XDsDac_mReadReg +#define XDsDac_mReadReg XDsDac_ReadReg +#endif + +#ifndef XDsDac_mIsEmpty +#define XDsDac_mIsEmpty XDsDac_IsEmpty +#endif + +#ifndef XDsDac_mFifoIsFull +#define XDsDac_mFifoIsFull XDsDac_FifoIsFull +#endif + +#ifndef XDsDac_mGetVacancy +#define XDsDac_mGetVacancy XDsDac_GetVacancy +#endif + +/*********************************************************************/ +/** + * Macros for Driver XEmacLite + * + *********************************************************************/ +#ifndef XEmacLite_mReadReg +#define XEmacLite_mReadReg XEmacLite_ReadReg +#endif + +#ifndef XEmacLite_mWriteReg +#define XEmacLite_mWriteReg XEmacLite_WriteReg +#endif + +#ifndef XEmacLite_mGetTxStatus +#define XEmacLite_mGetTxStatus XEmacLite_GetTxStatus +#endif + +#ifndef XEmacLite_mSetTxStatus +#define XEmacLite_mSetTxStatus XEmacLite_SetTxStatus +#endif + +#ifndef XEmacLite_mGetRxStatus +#define XEmacLite_mGetRxStatus XEmacLite_GetRxStatus +#endif + +#ifndef XEmacLite_mSetRxStatus +#define XEmacLite_mSetRxStatus XEmacLite_SetRxStatus +#endif + +#ifndef XEmacLite_mIsTxDone +#define XEmacLite_mIsTxDone XEmacLite_IsTxDone +#endif + +#ifndef XEmacLite_mIsRxEmpty +#define XEmacLite_mIsRxEmpty XEmacLite_IsRxEmpty +#endif + +#ifndef XEmacLite_mNextTransmitAddr +#define XEmacLite_mNextTransmitAddr XEmacLite_NextTransmitAddr +#endif + +#ifndef XEmacLite_mNextReceiveAddr +#define XEmacLite_mNextReceiveAddr XEmacLite_NextReceiveAddr +#endif + +#ifndef XEmacLite_mIsMdioConfigured +#define XEmacLite_mIsMdioConfigured XEmacLite_IsMdioConfigured +#endif + +#ifndef XEmacLite_mIsLoopbackConfigured +#define XEmacLite_mIsLoopbackConfigured XEmacLite_IsLoopbackConfigured +#endif + +#ifndef XEmacLite_mGetReceiveDataLength +#define XEmacLite_mGetReceiveDataLength XEmacLite_GetReceiveDataLength +#endif + +#ifndef XEmacLite_mGetTxActive +#define XEmacLite_mGetTxActive XEmacLite_GetTxActive +#endif + +#ifndef XEmacLite_mSetTxActive +#define XEmacLite_mSetTxActive XEmacLite_SetTxActive +#endif + +/*********************************************************************/ +/** + * Macros for Driver XGpio + * + *********************************************************************/ +#ifndef XGpio_mWriteReg +#define XGpio_mWriteReg XGpio_WriteReg +#endif + +#ifndef XGpio_mReadReg +#define XGpio_mReadReg XGpio_ReadReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XHwIcap + * + *********************************************************************/ +#ifndef XHwIcap_mFifoWrite +#define XHwIcap_mFifoWrite XHwIcap_FifoWrite +#endif + +#ifndef XHwIcap_mFifoRead +#define XHwIcap_mFifoRead XHwIcap_FifoRead +#endif + +#ifndef XHwIcap_mSetSizeReg +#define XHwIcap_mSetSizeReg XHwIcap_SetSizeReg +#endif + +#ifndef XHwIcap_mGetControlReg +#define XHwIcap_mGetControlReg XHwIcap_GetControlReg +#endif + +#ifndef XHwIcap_mStartConfig +#define XHwIcap_mStartConfig XHwIcap_StartConfig +#endif + +#ifndef XHwIcap_mStartReadBack +#define XHwIcap_mStartReadBack XHwIcap_StartReadBack +#endif + +#ifndef XHwIcap_mGetStatusReg +#define XHwIcap_mGetStatusReg XHwIcap_GetStatusReg +#endif + +#ifndef XHwIcap_mIsTransferDone +#define XHwIcap_mIsTransferDone XHwIcap_IsTransferDone +#endif + +#ifndef XHwIcap_mIsDeviceBusy +#define XHwIcap_mIsDeviceBusy XHwIcap_IsDeviceBusy +#endif + +#ifndef XHwIcap_mIntrGlobalEnable +#define XHwIcap_mIntrGlobalEnable XHwIcap_IntrGlobalEnable +#endif + +#ifndef XHwIcap_mIntrGlobalDisable +#define XHwIcap_mIntrGlobalDisable XHwIcap_IntrGlobalDisable +#endif + +#ifndef XHwIcap_mIntrGetStatus +#define XHwIcap_mIntrGetStatus XHwIcap_IntrGetStatus +#endif + +#ifndef XHwIcap_mIntrDisable +#define XHwIcap_mIntrDisable XHwIcap_IntrDisable +#endif + +#ifndef XHwIcap_mIntrEnable +#define XHwIcap_mIntrEnable XHwIcap_IntrEnable +#endif + +#ifndef XHwIcap_mIntrGetEnabled +#define XHwIcap_mIntrGetEnabled XHwIcap_IntrGetEnabled +#endif + +#ifndef XHwIcap_mIntrClear +#define XHwIcap_mIntrClear XHwIcap_IntrClear +#endif + +#ifndef XHwIcap_mGetWrFifoVacancy +#define XHwIcap_mGetWrFifoVacancy XHwIcap_GetWrFifoVacancy +#endif + +#ifndef XHwIcap_mGetRdFifoOccupancy +#define XHwIcap_mGetRdFifoOccupancy XHwIcap_GetRdFifoOccupancy +#endif + +#ifndef XHwIcap_mSliceX2Col +#define XHwIcap_mSliceX2Col XHwIcap_SliceX2Col +#endif + +#ifndef XHwIcap_mSliceY2Row +#define XHwIcap_mSliceY2Row XHwIcap_SliceY2Row +#endif + +#ifndef XHwIcap_mSliceXY2Slice +#define XHwIcap_mSliceXY2Slice XHwIcap_SliceXY2Slice +#endif + +#ifndef XHwIcap_mReadReg +#define XHwIcap_mReadReg XHwIcap_ReadReg +#endif + +#ifndef XHwIcap_mWriteReg +#define XHwIcap_mWriteReg XHwIcap_WriteReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XIic + * + *********************************************************************/ +#ifndef XIic_mReadReg +#define XIic_mReadReg XIic_ReadReg +#endif + +#ifndef XIic_mWriteReg +#define XIic_mWriteReg XIic_WriteReg +#endif + +#ifndef XIic_mEnterCriticalRegion +#define XIic_mEnterCriticalRegion XIic_IntrGlobalDisable +#endif + +#ifndef XIic_mExitCriticalRegion +#define XIic_mExitCriticalRegion XIic_IntrGlobalEnable +#endif + +#ifndef XIIC_GINTR_DISABLE +#define XIIC_GINTR_DISABLE XIic_IntrGlobalDisable +#endif + +#ifndef XIIC_GINTR_ENABLE +#define XIIC_GINTR_ENABLE XIic_IntrGlobalEnable +#endif + +#ifndef XIIC_IS_GINTR_ENABLED +#define XIIC_IS_GINTR_ENABLED XIic_IsIntrGlobalEnabled +#endif + +#ifndef XIIC_WRITE_IISR +#define XIIC_WRITE_IISR XIic_WriteIisr +#endif + +#ifndef XIIC_READ_IISR +#define XIIC_READ_IISR XIic_ReadIisr +#endif + +#ifndef XIIC_WRITE_IIER +#define XIIC_WRITE_IIER XIic_WriteIier +#endif + +#ifndef XIic_mClearIisr +#define XIic_mClearIisr XIic_ClearIisr +#endif + +#ifndef XIic_mSend7BitAddress +#define XIic_mSend7BitAddress XIic_Send7BitAddress +#endif + +#ifndef XIic_mDynSend7BitAddress +#define XIic_mDynSend7BitAddress XIic_DynSend7BitAddress +#endif + +#ifndef XIic_mDynSendStartStopAddress +#define XIic_mDynSendStartStopAddress XIic_DynSendStartStopAddress +#endif + +#ifndef XIic_mDynSendStop +#define XIic_mDynSendStop XIic_DynSendStop +#endif + +#ifndef XIic_mSend10BitAddrByte1 +#define XIic_mSend10BitAddrByte1 XIic_Send10BitAddrByte1 +#endif + +#ifndef XIic_mSend10BitAddrByte2 +#define XIic_mSend10BitAddrByte2 XIic_Send10BitAddrByte2 +#endif + +#ifndef XIic_mSend7BitAddr +#define XIic_mSend7BitAddr XIic_Send7BitAddr +#endif + +#ifndef XIic_mDisableIntr +#define XIic_mDisableIntr XIic_DisableIntr +#endif + +#ifndef XIic_mEnableIntr +#define XIic_mEnableIntr XIic_EnableIntr +#endif + +#ifndef XIic_mClearIntr +#define XIic_mClearIntr XIic_ClearIntr +#endif + +#ifndef XIic_mClearEnableIntr +#define XIic_mClearEnableIntr XIic_ClearEnableIntr +#endif + +#ifndef XIic_mFlushRxFifo +#define XIic_mFlushRxFifo XIic_FlushRxFifo +#endif + +#ifndef XIic_mFlushTxFifo +#define XIic_mFlushTxFifo XIic_FlushTxFifo +#endif + +#ifndef XIic_mReadRecvByte +#define XIic_mReadRecvByte XIic_ReadRecvByte +#endif + +#ifndef XIic_mWriteSendByte +#define XIic_mWriteSendByte XIic_WriteSendByte +#endif + +#ifndef XIic_mSetControlRegister +#define XIic_mSetControlRegister XIic_SetControlRegister +#endif + +/*********************************************************************/ +/** + * Macros for Driver XIntc + * + *********************************************************************/ +#ifndef XIntc_mMasterEnable +#define XIntc_mMasterEnable XIntc_MasterEnable +#endif + +#ifndef XIntc_mMasterDisable +#define XIntc_mMasterDisable XIntc_MasterDisable +#endif + +#ifndef XIntc_mEnableIntr +#define XIntc_mEnableIntr XIntc_EnableIntr +#endif + +#ifndef XIntc_mDisableIntr +#define XIntc_mDisableIntr XIntc_DisableIntr +#endif + +#ifndef XIntc_mAckIntr +#define XIntc_mAckIntr XIntc_AckIntr +#endif + +#ifndef XIntc_mGetIntrStatus +#define XIntc_mGetIntrStatus XIntc_GetIntrStatus +#endif + +/*********************************************************************/ +/** + * Macros for Driver XLlDma + * + *********************************************************************/ +#ifndef XLlDma_mBdRead +#define XLlDma_mBdRead XLlDma_BdRead +#endif + +#ifndef XLlDma_mBdWrite +#define XLlDma_mBdWrite XLlDma_BdWrite +#endif + +#ifndef XLlDma_mWriteReg +#define XLlDma_mWriteReg XLlDma_WriteReg +#endif + +#ifndef XLlDma_mReadReg +#define XLlDma_mReadReg XLlDma_ReadReg +#endif + +#ifndef XLlDma_mBdClear +#define XLlDma_mBdClear XLlDma_BdClear +#endif + +#ifndef XLlDma_mBdSetStsCtrl +#define XLlDma_mBdSetStsCtrl XLlDma_BdSetStsCtrl +#endif + +#ifndef XLlDma_mBdGetStsCtrl +#define XLlDma_mBdGetStsCtrl XLlDma_BdGetStsCtrl +#endif + +#ifndef XLlDma_mBdSetLength +#define XLlDma_mBdSetLength XLlDma_BdSetLength +#endif + +#ifndef XLlDma_mBdGetLength +#define XLlDma_mBdGetLength XLlDma_BdGetLength +#endif + +#ifndef XLlDma_mBdSetId +#define XLlDma_mBdSetId XLlDma_BdSetId +#endif + +#ifndef XLlDma_mBdGetId +#define XLlDma_mBdGetId XLlDma_BdGetId +#endif + +#ifndef XLlDma_mBdSetBufAddr +#define XLlDma_mBdSetBufAddr XLlDma_BdSetBufAddr +#endif + +#ifndef XLlDma_mBdGetBufAddr +#define XLlDma_mBdGetBufAddr XLlDma_BdGetBufAddr +#endif + +#ifndef XLlDma_mBdGetLength +#define XLlDma_mBdGetLength XLlDma_BdGetLength +#endif + +#ifndef XLlDma_mGetTxRing +#define XLlDma_mGetTxRing XLlDma_GetTxRing +#endif + +#ifndef XLlDma_mGetRxRing +#define XLlDma_mGetRxRing XLlDma_GetRxRing +#endif + +#ifndef XLlDma_mGetCr +#define XLlDma_mGetCr XLlDma_GetCr +#endif + +#ifndef XLlDma_mSetCr +#define XLlDma_mSetCr XLlDma_SetCr +#endif + +#ifndef XLlDma_mBdRingCntCalc +#define XLlDma_mBdRingCntCalc XLlDma_BdRingCntCalc +#endif + +#ifndef XLlDma_mBdRingMemCalc +#define XLlDma_mBdRingMemCalc XLlDma_BdRingMemCalc +#endif + +#ifndef XLlDma_mBdRingGetCnt +#define XLlDma_mBdRingGetCnt XLlDma_BdRingGetCnt +#endif + +#ifndef XLlDma_mBdRingGetFreeCnt +#define XLlDma_mBdRingGetFreeCnt XLlDma_BdRingGetFreeCnt +#endif + +#ifndef XLlDma_mBdRingSnapShotCurrBd +#define XLlDma_mBdRingSnapShotCurrBd XLlDma_BdRingSnapShotCurrBd +#endif + +#ifndef XLlDma_mBdRingNext +#define XLlDma_mBdRingNext XLlDma_BdRingNext +#endif + +#ifndef XLlDma_mBdRingPrev +#define XLlDma_mBdRingPrev XLlDma_BdRingPrev +#endif + +#ifndef XLlDma_mBdRingGetSr +#define XLlDma_mBdRingGetSr XLlDma_BdRingGetSr +#endif + +#ifndef XLlDma_mBdRingSetSr +#define XLlDma_mBdRingSetSr XLlDma_BdRingSetSr +#endif + +#ifndef XLlDma_mBdRingGetCr +#define XLlDma_mBdRingGetCr XLlDma_BdRingGetCr +#endif + +#ifndef XLlDma_mBdRingSetCr +#define XLlDma_mBdRingSetCr XLlDma_BdRingSetCr +#endif + +#ifndef XLlDma_mBdRingBusy +#define XLlDma_mBdRingBusy XLlDma_BdRingBusy +#endif + +#ifndef XLlDma_mBdRingIntEnable +#define XLlDma_mBdRingIntEnable XLlDma_BdRingIntEnable +#endif + +#ifndef XLlDma_mBdRingIntDisable +#define XLlDma_mBdRingIntDisable XLlDma_BdRingIntDisable +#endif + +#ifndef XLlDma_mBdRingIntGetEnabled +#define XLlDma_mBdRingIntGetEnabled XLlDma_BdRingIntGetEnabled +#endif + +#ifndef XLlDma_mBdRingGetIrq +#define XLlDma_mBdRingGetIrq XLlDma_BdRingGetIrq +#endif + +#ifndef XLlDma_mBdRingAckIrq +#define XLlDma_mBdRingAckIrq XLlDma_BdRingAckIrq +#endif + +/*********************************************************************/ +/** + * Macros for Driver XMbox + * + *********************************************************************/ +#ifndef XMbox_mWriteReg +#define XMbox_mWriteReg XMbox_WriteReg +#endif + +#ifndef XMbox_mReadReg +#define XMbox_mReadReg XMbox_ReadReg +#endif + +#ifndef XMbox_mWriteMBox +#define XMbox_mWriteMBox XMbox_WriteMBox +#endif + +#ifndef XMbox_mReadMBox +#define XMbox_mReadMBox XMbox_ReadMBox +#endif + +#ifndef XMbox_mFSLReadMBox +#define XMbox_mFSLReadMBox XMbox_FSLReadMBox +#endif + +#ifndef XMbox_mFSLWriteMBox +#define XMbox_mFSLWriteMBox XMbox_FSLWriteMBox +#endif + +#ifndef XMbox_mFSLIsEmpty +#define XMbox_mFSLIsEmpty XMbox_FSLIsEmpty +#endif + +#ifndef XMbox_mFSLIsFull +#define XMbox_mFSLIsFull XMbox_FSLIsFull +#endif + +#ifndef XMbox_mIsEmpty +#define XMbox_mIsEmpty XMbox_IsEmptyHw +#endif + +#ifndef XMbox_mIsFull +#define XMbox_mIsFull XMbox_IsFullHw +#endif + +/*********************************************************************/ +/** + * Macros for Driver XMpmc + * + *********************************************************************/ +#ifndef XMpmc_mReadReg +#define XMpmc_mReadReg XMpmc_ReadReg +#endif + +#ifndef XMpmc_mWriteReg +#define XMpmc_mWriteReg XMpmc_WriteReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XMutex + * + *********************************************************************/ +#ifndef XMutex_mWriteReg +#define XMutex_mWriteReg XMutex_WriteReg +#endif + +#ifndef XMutex_mReadReg +#define XMutex_mReadReg XMutex_ReadReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XPcie + * + *********************************************************************/ +#ifndef XPcie_mReadReg +#define XPcie_mReadReg XPcie_ReadReg +#endif + +#ifndef XPcie_mWriteReg +#define XPcie_mWriteReg XPcie_WriteReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XSpi + * + *********************************************************************/ +#ifndef XSpi_mIntrGlobalEnable +#define XSpi_mIntrGlobalEnable XSpi_IntrGlobalEnable +#endif + +#ifndef XSpi_mIntrGlobalDisable +#define XSpi_mIntrGlobalDisable XSpi_IntrGlobalDisable +#endif + +#ifndef XSpi_mIsIntrGlobalEnabled +#define XSpi_mIsIntrGlobalEnabled XSpi_IsIntrGlobalEnabled +#endif + +#ifndef XSpi_mIntrGetStatus +#define XSpi_mIntrGetStatus XSpi_IntrGetStatus +#endif + +#ifndef XSpi_mIntrClear +#define XSpi_mIntrClear XSpi_IntrClear +#endif + +#ifndef XSpi_mIntrEnable +#define XSpi_mIntrEnable XSpi_IntrEnable +#endif + +#ifndef XSpi_mIntrDisable +#define XSpi_mIntrDisable XSpi_IntrDisable +#endif + +#ifndef XSpi_mIntrGetEnabled +#define XSpi_mIntrGetEnabled XSpi_IntrGetEnabled +#endif + +#ifndef XSpi_mSetControlReg +#define XSpi_mSetControlReg XSpi_SetControlReg +#endif + +#ifndef XSpi_mGetControlReg +#define XSpi_mGetControlReg XSpi_GetControlReg +#endif + +#ifndef XSpi_mGetStatusReg +#define XSpi_mGetStatusReg XSpi_GetStatusReg +#endif + +#ifndef XSpi_mSetSlaveSelectReg +#define XSpi_mSetSlaveSelectReg XSpi_SetSlaveSelectReg +#endif + +#ifndef XSpi_mGetSlaveSelectReg +#define XSpi_mGetSlaveSelectReg XSpi_GetSlaveSelectReg +#endif + +#ifndef XSpi_mEnable +#define XSpi_mEnable XSpi_Enable +#endif + +#ifndef XSpi_mDisable +#define XSpi_mDisable XSpi_Disable +#endif + +/*********************************************************************/ +/** + * Macros for Driver XSysAce + * + *********************************************************************/ +#ifndef XSysAce_mGetControlReg +#define XSysAce_mGetControlReg XSysAce_GetControlReg +#endif + +#ifndef XSysAce_mSetControlReg +#define XSysAce_mSetControlReg XSysAce_SetControlReg +#endif + +#ifndef XSysAce_mOrControlReg +#define XSysAce_mOrControlReg XSysAce_OrControlReg +#endif + +#ifndef XSysAce_mAndControlReg +#define XSysAce_mAndControlReg XSysAce_AndControlReg +#endif + +#ifndef XSysAce_mGetErrorReg +#define XSysAce_mGetErrorReg XSysAce_GetErrorReg +#endif + +#ifndef XSysAce_mGetStatusReg +#define XSysAce_mGetStatusReg XSysAce_GetStatusReg +#endif + +#ifndef XSysAce_mWaitForLock +#define XSysAce_mWaitForLock XSysAce_WaitForLock +#endif + +#ifndef XSysAce_mEnableIntr +#define XSysAce_mEnableIntr XSysAce_EnableIntr +#endif + +#ifndef XSysAce_mDisableIntr +#define XSysAce_mDisableIntr XSysAce_DisableIntr +#endif + +#ifndef XSysAce_mIsReadyForCmd +#define XSysAce_mIsReadyForCmd XSysAce_IsReadyForCmd +#endif + +#ifndef XSysAce_mIsMpuLocked +#define XSysAce_mIsMpuLocked XSysAce_IsMpuLocked +#endif + +#ifndef XSysAce_mIsIntrEnabled +#define XSysAce_mIsIntrEnabled XSysAce_IsIntrEnabled +#endif + +/*********************************************************************/ +/** + * Macros for Driver XSysMon + * + *********************************************************************/ +#ifndef XSysMon_mIsEventSamplingModeSet +#define XSysMon_mIsEventSamplingModeSet XSysMon_IsEventSamplingModeSet +#endif + +#ifndef XSysMon_mIsDrpBusy +#define XSysMon_mIsDrpBusy XSysMon_IsDrpBusy +#endif + +#ifndef XSysMon_mIsDrpLocked +#define XSysMon_mIsDrpLocked XSysMon_IsDrpLocked +#endif + +#ifndef XSysMon_mRawToTemperature +#define XSysMon_mRawToTemperature XSysMon_RawToTemperature +#endif + +#ifndef XSysMon_mRawToVoltage +#define XSysMon_mRawToVoltage XSysMon_RawToVoltage +#endif + +#ifndef XSysMon_mTemperatureToRaw +#define XSysMon_mTemperatureToRaw XSysMon_TemperatureToRaw +#endif + +#ifndef XSysMon_mVoltageToRaw +#define XSysMon_mVoltageToRaw XSysMon_VoltageToRaw +#endif + +#ifndef XSysMon_mReadReg +#define XSysMon_mReadReg XSysMon_ReadReg +#endif + +#ifndef XSysMon_mWriteReg +#define XSysMon_mWriteReg XSysMon_WriteReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XTmrCtr + * + *********************************************************************/ +#ifndef XTimerCtr_mReadReg +#define XTimerCtr_mReadReg XTimerCtr_ReadReg +#endif + +#ifndef XTmrCtr_mWriteReg +#define XTmrCtr_mWriteReg XTmrCtr_WriteReg +#endif + +#ifndef XTmrCtr_mSetControlStatusReg +#define XTmrCtr_mSetControlStatusReg XTmrCtr_SetControlStatusReg +#endif + +#ifndef XTmrCtr_mGetControlStatusReg +#define XTmrCtr_mGetControlStatusReg XTmrCtr_GetControlStatusReg +#endif + +#ifndef XTmrCtr_mGetTimerCounterReg +#define XTmrCtr_mGetTimerCounterReg XTmrCtr_GetTimerCounterReg +#endif + +#ifndef XTmrCtr_mSetLoadReg +#define XTmrCtr_mSetLoadReg XTmrCtr_SetLoadReg +#endif + +#ifndef XTmrCtr_mGetLoadReg +#define XTmrCtr_mGetLoadReg XTmrCtr_GetLoadReg +#endif + +#ifndef XTmrCtr_mEnable +#define XTmrCtr_mEnable XTmrCtr_Enable +#endif + +#ifndef XTmrCtr_mDisable +#define XTmrCtr_mDisable XTmrCtr_Disable +#endif + +#ifndef XTmrCtr_mEnableIntr +#define XTmrCtr_mEnableIntr XTmrCtr_EnableIntr +#endif + +#ifndef XTmrCtr_mDisableIntr +#define XTmrCtr_mDisableIntr XTmrCtr_DisableIntr +#endif + +#ifndef XTmrCtr_mLoadTimerCounterReg +#define XTmrCtr_mLoadTimerCounterReg XTmrCtr_LoadTimerCounterReg +#endif + +#ifndef XTmrCtr_mHasEventOccurred +#define XTmrCtr_mHasEventOccurred XTmrCtr_HasEventOccurred +#endif + +/*********************************************************************/ +/** + * Macros for Driver XUartLite + * + *********************************************************************/ +#ifndef XUartLite_mUpdateStats +#define XUartLite_mUpdateStats XUartLite_UpdateStats +#endif + +#ifndef XUartLite_mWriteReg +#define XUartLite_mWriteReg XUartLite_WriteReg +#endif + +#ifndef XUartLite_mReadReg +#define XUartLite_mReadReg XUartLite_ReadReg +#endif + +#ifndef XUartLite_mClearStats +#define XUartLite_mClearStats XUartLite_ClearStats +#endif + +#ifndef XUartLite_mSetControlReg +#define XUartLite_mSetControlReg XUartLite_SetControlReg +#endif + +#ifndef XUartLite_mGetStatusReg +#define XUartLite_mGetStatusReg XUartLite_GetStatusReg +#endif + +#ifndef XUartLite_mIsReceiveEmpty +#define XUartLite_mIsReceiveEmpty XUartLite_IsReceiveEmpty +#endif + +#ifndef XUartLite_mIsTransmitFull +#define XUartLite_mIsTransmitFull XUartLite_IsTransmitFull +#endif + +#ifndef XUartLite_mIsIntrEnabled +#define XUartLite_mIsIntrEnabled XUartLite_IsIntrEnabled +#endif + +#ifndef XUartLite_mEnableIntr +#define XUartLite_mEnableIntr XUartLite_EnableIntr +#endif + +#ifndef XUartLite_mDisableIntr +#define XUartLite_mDisableIntr XUartLite_DisableIntr +#endif + +/*********************************************************************/ +/** + * Macros for Driver XUartNs550 + * + *********************************************************************/ +#ifndef XUartNs550_mUpdateStats +#define XUartNs550_mUpdateStats XUartNs550_UpdateStats +#endif + +#ifndef XUartNs550_mReadReg +#define XUartNs550_mReadReg XUartNs550_ReadReg +#endif + +#ifndef XUartNs550_mWriteReg +#define XUartNs550_mWriteReg XUartNs550_WriteReg +#endif + +#ifndef XUartNs550_mClearStats +#define XUartNs550_mClearStats XUartNs550_ClearStats +#endif + +#ifndef XUartNs550_mGetLineStatusReg +#define XUartNs550_mGetLineStatusReg XUartNs550_GetLineStatusReg +#endif + +#ifndef XUartNs550_mGetLineControlReg +#define XUartNs550_mGetLineControlReg XUartNs550_GetLineControlReg +#endif + +#ifndef XUartNs550_mSetLineControlReg +#define XUartNs550_mSetLineControlReg XUartNs550_SetLineControlReg +#endif + +#ifndef XUartNs550_mEnableIntr +#define XUartNs550_mEnableIntr XUartNs550_EnableIntr +#endif + +#ifndef XUartNs550_mDisableIntr +#define XUartNs550_mDisableIntr XUartNs550_DisableIntr +#endif + +#ifndef XUartNs550_mIsReceiveData +#define XUartNs550_mIsReceiveData XUartNs550_IsReceiveData +#endif + +#ifndef XUartNs550_mIsTransmitEmpty +#define XUartNs550_mIsTransmitEmpty XUartNs550_IsTransmitEmpty +#endif + +/*********************************************************************/ +/** + * Macros for Driver XUsb + * + *********************************************************************/ +#ifndef XUsb_mReadReg +#define XUsb_mReadReg XUsb_ReadReg +#endif + +#ifndef XUsb_mWriteReg +#define XUsb_mWriteReg XUsb_WriteReg +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h new file mode 100644 index 000000000..ed628566c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h @@ -0,0 +1,286 @@ +/****************************************************************************** +* +* (c) Copyright 2013 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xil_misc_psreset_api.h +* +* This file contains the various register defintions and function prototypes for +* implementing the reset functionality of zynq ps devices +* +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 1.00b kpc 03/07/13 First release. +* +* +******************************************************************************/ + +#ifndef XIL_MISC_RESET_H /* prevent circular inclusions */ +#define XIL_MISC_RESET_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + + +/***************************** Include Files *********************************/ +#include "xil_types.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ +#define XDDRC_CTRL_BASEADDR 0xF8006000 +#define XSLCR_BASEADDR 0xF8000000 +/**< OCM configuration register */ +#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x910) +/**< SLCR unlock register */ +#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x8) +/**< SLCR GEM0 rx clock control register */ +#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x138) +/**< SLCR GEM1 rx clock control register */ +#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x13C) +/**< SLCR GEM0 clock control register */ +#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x140) +/**< SLCR GEM1 clock control register */ +#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x144) +/**< SLCR SMC clock control register */ +#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x148) +/**< SLCR GEM reset control register */ +#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x214) +/**< SLCR USB0 clock control register */ +#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x130) +/**< SLCR USB1 clock control register */ +#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x134) +/**< SLCR USB1 reset control register */ +#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x210) +/**< SLCR SMC reset control register */ +#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x234) +/**< SLCR Level shifter enable register */ +#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x900) +/**< SLCR ARM pll control register */ +#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x100) +/**< SLCR DDR pll control register */ +#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x104) +/**< SLCR IO pll control register */ +#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x108) +/**< SLCR ARM pll configuration register */ +#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x110) +/**< SLCR DDR pll configuration register */ +#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x114) +/**< SLCR IO pll configuration register */ +#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x118) +/**< SLCR ARM clock control register */ +#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x120) +/**< SLCR DDR clock control register */ +#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x124) +/**< SLCR MIO pin address register */ +#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x700) +/**< SLCR DMAC reset control address register */ +#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x20C) +/**< SLCR USB reset control address register */ +#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x210) +/**< SLCR GEM reset control address register */ +#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x214) +/**< SLCR SDIO reset control address register */ +#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x218) +/**< SLCR SPI reset control address register */ +#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x21C) +/**< SLCR CAN reset control address register */ +#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x220) +/**< SLCR I2C reset control address register */ +#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x224) +/**< SLCR UART reset control address register */ +#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x228) +/**< SLCR GPIO reset control address register */ +#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x22C) +/**< SLCR LQSPI reset control address register */ +#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x230) +/**< SLCR SMC reset control address register */ +#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x234) +/**< SLCR OCM reset control address register */ +#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x238) + +/**< SMC mem controller clear config register */ +#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0C +/**< SMC idlecount configuration register */ +#define XSMC_REFRESH_PERIOD_0_OFFSET 0x20 +#define XSMC_REFRESH_PERIOD_1_OFFSET 0x24 +/**< SMC ECC configuration register */ +#define XSMC_ECC_MEMCFG1_OFFSET 0x404 +/**< SMC ECC command 1 register */ +#define XSMC_ECC_MEMCMD1_OFFSET 0x404 +/**< SMC ECC command 2 register */ +#define XSMC_ECC_MEMCMD2_OFFSET 0x404 + +/**< SLCR unlock code */ +#define XSLCR_UNLOCK_CODE 0x0000DF0D + +/**< SMC mem clear configuration mask */ +#define XSMC_MEMC_CLR_CONFIG_MASK 0x5F +/**< SMC ECC memconfig 1 reset value */ +#define XSMC_ECC_MEMCFG1_RESET_VAL 0x43 +/**< SMC ECC memcommand 1 reset value */ +#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080 +/**< SMC ECC memcommand 2 reset value */ +#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585 + +/**< DDR controller reset bit mask */ +#define XDDRPS_CTRL_RESET_MASK 0x1 +/**< SLCR OCM configuration reset value*/ +#define XSLCR_OCM_CFG_RESETVAL 0x8 +/**< SLCR OCM bank selection mask*/ +#define XSLCR_OCM_CFG_HIADDR_MASK 0xF +/**< SLCR level shifter enable mask*/ +#define XSLCR_LVL_SHFTR_EN_MASK 0xF + +/**< SLCR PLL register reset values */ +#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008 +#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008 +#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008 +#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0 +#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0 +#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0 +#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400 +#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003 + +/**< SLCR MIO register default values */ +#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601 +#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601 + +/**< SLCR Reset control registers default values */ +#define XSLCR_DMAC_RST_CTRL_VAL 0x1 +#define XSLCR_GEM_RST_CTRL_VAL 0xF3 +#define XSLCR_USB_RST_CTRL_VAL 0x3 +#define XSLCR_I2C_RST_CTRL_VAL 0x3 +#define XSLCR_SPI_RST_CTRL_VAL 0xF +#define XSLCR_UART_RST_CTRL_VAL 0xF +#define XSLCR_QSPI_RST_CTRL_VAL 0x3 +#define XSLCR_GPIO_RST_CTRL_VAL 0x1 +#define XSLCR_SMC_RST_CTRL_VAL 0x3 +#define XSLCR_OCM_RST_CTRL_VAL 0x1 +#define XSLCR_SDIO_RST_CTRL_VAL 0x33 +#define XSLCR_CAN_RST_CTRL_VAL 0x3 +/**************************** Type Definitions *******************************/ + +/* the following data type is used to hold a null terminated version string + * consisting of the following format, "X.YYX" + */ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ +/* + * Performs reset operation to the ddr interface + */ +void XDdr_ResetHw(); +/* + * Map the ocm region to post bootrom state + */ +void XOcm_Remap(); +/* + * Performs the smc interface reset + */ +void XSmc_ResetHw(u32 BaseAddress); +/* + * updates the MIO registers with reset values + */ +void XSlcr_MioWriteResetValues(); +/* + * updates the PLL and clock registers with reset values + */ +void XSlcr_PllWriteResetValues(); +/* + * Disables the level shifters + */ +void XSlcr_DisableLevelShifters(); +/* + * provides softreset to the GPIO interface + */ +void XSlcr_GpioPsReset(void); +/* + * provides softreset to the DMA interface + */ +void XSlcr_DmaPsReset(void); +/* + * provides softreset to the SMC interface + */ +void XSlcr_SmcPsReset(void); +/* + * provides softreset to the CAN interface + */ +void XSlcr_CanPsReset(void); +/* + * provides softreset to the Uart interface + */ +void XSlcr_UartPsReset(void); +/* + * provides softreset to the I2C interface + */ +void XSlcr_I2cPsReset(void); +/* + * provides softreset to the SPI interface + */ +void XSlcr_SpiPsReset(void); +/* + * provides softreset to the QSPI interface + */ +void XSlcr_QspiPsReset(void); +/* + * provides softreset to the USB interface + */ +void XSlcr_UsbPsReset(void); +/* + * provides softreset to the GEM interface + */ +void XSlcr_EmacPsReset(void); +/* + * provides softreset to the OCM interface + */ +void XSlcr_OcmReset(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* XIL_MISC_RESET_H */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_mmu.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_mmu.h new file mode 100644 index 000000000..37dc1806f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_mmu.h @@ -0,0 +1,87 @@ +/****************************************************************************** +* +* (c) Copyright 2012 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xil_mmu.h +* +* +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  01/12/12 Initial version
+*
+* +* @note +* +* None. +* +******************************************************************************/ + +#ifndef XIL_MMU_H +#define XIL_MMU_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/***************************** Include Files *********************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +void Xil_SetTlbAttributes(u32 addr, u32 attrib); +void Xil_EnableMMU(void); +void Xil_DisableMMU(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XIL_MMU_H */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_printf.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_printf.h new file mode 100644 index 000000000..89a051c23 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_printf.h @@ -0,0 +1,47 @@ + #ifndef XIL_PRINTF_H + #define XIL_PRINTF_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include "xparameters.h" +#include "xil_types.h" + +/*----------------------------------------------------*/ +/* Use the following parameter passing structure to */ +/* make xil_printf re-entrant. */ +/*----------------------------------------------------*/ + +struct params_s; + + +/*---------------------------------------------------*/ +/* The purpose of this routine is to output data the */ +/* same as the standard printf function without the */ +/* overhead most run-time libraries involve. Usually */ +/* the printf brings in many kilobytes of code and */ +/* that is unacceptable in most embedded systems. */ +/*---------------------------------------------------*/ + +typedef char* charptr; +typedef int (*func_ptr)(int c); + +/* */ +void padding( const int l_flag, struct params_s *par); +void outs( charptr lp, struct params_s *par); +void outnum( const long n, const long base, struct params_s *par); +int getnum( charptr* linep); +void xil_printf( const char *ctrl1, ...); +void print( const char *ptr); +void outbyte (char); +char inbyte(void); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_testcache.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_testcache.h new file mode 100644 index 000000000..db6d29652 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_testcache.h @@ -0,0 +1,71 @@ +/****************************************************************************** +* +* +* (c) Copyright 2009 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_testcache.h +* +* This file contains utility functions to test cache. +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 1.00a hbm 07/29/09 First release +* +******************************************************************************/ + +#ifndef XIL_TESTCACHE_H /* prevent circular inclusions */ +#define XIL_TESTCACHE_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +extern int Xil_TestDCacheRange(void); +extern int Xil_TestDCacheAll(void); +extern int Xil_TestICacheRange(void); +extern int Xil_TestICacheAll(void); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_testio.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_testio.h new file mode 100644 index 000000000..33a8286f1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_testio.h @@ -0,0 +1,101 @@ +/****************************************************************************** +* +* (c) Copyright 2009 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_testmemend.h +* +* This file contains utility functions to teach endian related memory +* IO functions. +* +* Memory test description +* +* A subset of the memory tests can be selected or all of the tests can be run +* in order. If there is an error detected by a subtest, the test stops and the +* failure code is returned. Further tests are not run even if all of the tests +* are selected. +* +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00 hbm  08/05/09 First release
+*
+* +******************************************************************************/ + +#ifndef XIL_TESTIO_H /* prevent circular inclusions */ +#define XIL_TESTIO_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ + + +#define XIL_TESTIO_DEFAULT 0 +#define XIL_TESTIO_LE 1 +#define XIL_TESTIO_BE 2 + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +extern int Xil_TestIO8(u8 *Addr, int Len, u8 Value); +extern int Xil_TestIO16(u16 *Addr, int Len, u16 Value, int Kind, int Swap); +extern int Xil_TestIO32(u32 *Addr, int Len, u32 Value, int Kind, int Swap); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_testmem.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_testmem.h new file mode 100644 index 000000000..74e131d5b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_testmem.h @@ -0,0 +1,173 @@ +/****************************************************************************** +* +* +* (c) Copyright 2009 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_testmem.h +* +* This file contains utility functions to test memory. +* +* Memory test description +* +* A subset of the memory tests can be selected or all of the tests can be run +* in order. If there is an error detected by a subtest, the test stops and the +* failure code is returned. Further tests are not run even if all of the tests +* are selected. +* +* Subtest descriptions: +* 
+* XIL_TESTMEM_ALLMEMTESTS:
+*       Runs all of the following tests
+*
+* XIL_TESTMEM_INCREMENT:
+*       Incrementing Value Test.
+*       This test starts at 'XIL_TESTMEM_INIT_VALUE' and uses the
+*	incrementing value as the test value for memory.
+*
+* XIL_TESTMEM_WALKONES:
+*       Walking Ones Test.
+*       This test uses a walking '1' as the test value for memory.
+*       location 1 = 0x00000001
+*       location 2 = 0x00000002
+*       ...
+*
+* XIL_TESTMEM_WALKZEROS:
+*       Walking Zero's Test.
+*       This test uses the inverse value of the walking ones test
+*       as the test value for memory.
+*       location 1 = 0xFFFFFFFE
+*       location 2 = 0xFFFFFFFD
+*       ...
+*
+* XIL_TESTMEM_INVERSEADDR:
+*       Inverse Address Test.
+*       This test uses the inverse of the address of the location under test
+*       as the test value for memory.
+*
+* XIL_TESTMEM_FIXEDPATTERN:
+*       Fixed Pattern Test.
+*       This test uses the provided patters as the test value for memory.
+*       If zero is provided as the pattern the test uses '0xDEADBEEF".
+*
+* +* WARNING +* +* The tests are DESTRUCTIVE. Run before any initialized memory spaces +* have been set up. +* +* The address provided to the memory tests is not checked for +* validity except for the NULL case. It is possible to provide a code-space +* pointer for this test to start with and ultimately destroy executable code +* causing random failures. +* +* @note +* +* Used for spaces where the address range of the region is smaller than +* the data width. If the memory range is greater than 2 ** width, +* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will +* repeat on a boundry of a power of two making it more difficult to detect +* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR +* tests suffer the same problem. Ideally, if large blocks of memory are to be +* tested, break them up into smaller regions of memory to allow the test +* patterns used not to repeat over the region tested. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  08/25/09 First release
+*
+* +******************************************************************************/ + +#ifndef XIL_TESTMEM_H /* prevent circular inclusions */ +#define XIL_TESTMEM_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + +/* xutil_memtest defines */ + +#define XIL_TESTMEM_INIT_VALUE 1 + +/** @name Memory subtests + * @{ + */ +/** + * See the detailed description of the subtests in the file description. + */ +#define XIL_TESTMEM_ALLMEMTESTS 0 +#define XIL_TESTMEM_INCREMENT 1 +#define XIL_TESTMEM_WALKONES 2 +#define XIL_TESTMEM_WALKZEROS 3 +#define XIL_TESTMEM_INVERSEADDR 4 +#define XIL_TESTMEM_FIXEDPATTERN 5 +#define XIL_TESTMEM_MAXTEST XIL_TESTMEM_FIXEDPATTERN +/* @} */ + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +/* xutil_testmem prototypes */ + +extern int Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest); +extern int Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest); +extern int Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_types.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_types.h new file mode 100644 index 000000000..087ddb530 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xil_types.h @@ -0,0 +1,173 @@ +/****************************************************************************** +* +* (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_types.h +* +* This file contains basic types for Xilinx software IP. + +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 First release
+* 3.03a sdm  05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+*
+* +******************************************************************************/ + +#ifndef XIL_TYPES_H /* prevent circular inclusions */ +#define XIL_TYPES_H /* by using protection macros */ + + +/************************** Constant Definitions *****************************/ + +#ifndef TRUE +# define TRUE 1 +#endif + +#ifndef FALSE +# define FALSE 0 +#endif + +#ifndef NULL +#define NULL 0 +#endif + +#define XIL_COMPONENT_IS_READY 0x11111111 /**< component has been initialized */ +#define XIL_COMPONENT_IS_STARTED 0x22222222 /**< component has been started */ + +/** @name New types + * New simple types. + * @{ + */ +#ifndef __KERNEL__ +#ifndef XBASIC_TYPES_H +/** + * guarded against xbasic_types.h. + */ +typedef unsigned char u8; +typedef unsigned short u16; +typedef unsigned long u32; + +#define __XUINT64__ +typedef struct +{ + u32 Upper; + u32 Lower; +} Xuint64; + + +/*****************************************************************************/ +/** +* Return the most significant half of the 64 bit data type. +* +* @param x is the 64 bit word. +* +* @return The upper 32 bits of the 64 bit word. +* +* @note None. +* +******************************************************************************/ +#define XUINT64_MSW(x) ((x).Upper) + +/*****************************************************************************/ +/** +* Return the least significant half of the 64 bit data type. +* +* @param x is the 64 bit word. +* +* @return The lower 32 bits of the 64 bit word. +* +* @note None. +* +******************************************************************************/ +#define XUINT64_LSW(x) ((x).Lower) + +#endif /* XBASIC_TYPES_H */ + +/** + * xbasic_types.h does not typedef s* or u64 + */ +typedef unsigned long long u64; + +typedef char s8; +typedef short s16; +typedef long s32; +typedef long long s64; +#else +#include +#endif + + +/** + * This data type defines an interrupt handler for a device. + * The argument points to the instance of the component + */ +typedef void (*XInterruptHandler) (void *InstancePtr); + +/** + * This data type defines an exception handler for a processor. + * The argument points to the instance of the component + */ +typedef void (*XExceptionHandler) (void *InstancePtr); + +/*@}*/ + + +/************************** Constant Definitions *****************************/ + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +#ifndef NULL +#define NULL 0 +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xl2cc.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xl2cc.h new file mode 100644 index 000000000..13b6f763d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xl2cc.h @@ -0,0 +1,180 @@ +/****************************************************************************** +* +* (c) Copyright 2011-13 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xl2cc.h +* +* This file contains the address definitions for the PL310 Level-2 Cache +* Controller. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  02/01/10 Initial version
+* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
+*		      'xil_errata.h' for errata description
+*
+* +* @note +* +* None. +* +******************************************************************************/ + +#ifndef _XL2CC_H_ +#define _XL2CC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ +/* L2CC Register Offsets */ +#define XPS_L2CC_ID_OFFSET 0x0000 +#define XPS_L2CC_TYPE_OFFSET 0x0004 +#define XPS_L2CC_CNTRL_OFFSET 0x0100 +#define XPS_L2CC_AUX_CNTRL_OFFSET 0x0104 +#define XPS_L2CC_TAG_RAM_CNTRL_OFFSET 0x0108 +#define XPS_L2CC_DATA_RAM_CNTRL_OFFSET 0x010C + +#define XPS_L2CC_EVNT_CNTRL_OFFSET 0x0200 +#define XPS_L2CC_EVNT_CNT1_CTRL_OFFSET 0x0204 +#define XPS_L2CC_EVNT_CNT0_CTRL_OFFSET 0x0208 +#define XPS_L2CC_EVNT_CNT1_VAL_OFFSET 0x020C +#define XPS_L2CC_EVNT_CNT0_VAL_OFFSET 0x0210 + +#define XPS_L2CC_IER_OFFSET 0x0214 /* Interrupt Mask */ +#define XPS_L2CC_IPR_OFFSET 0x0218 /* Masked interrupt status */ +#define XPS_L2CC_ISR_OFFSET 0x021C /* Raw Interrupt Status */ +#define XPS_L2CC_IAR_OFFSET 0x0220 /* Interrupt Clear */ + +#define XPS_L2CC_CACHE_SYNC_OFFSET 0x0730 /* Cache Sync */ +#define XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET 0x0740 /* Dummy Register for Cache Sync */ +#define XPS_L2CC_CACHE_INVLD_PA_OFFSET 0x0770 /* Cache Invalid by PA */ +#define XPS_L2CC_CACHE_INVLD_WAY_OFFSET 0x077C /* Cache Invalid by Way */ +#define XPS_L2CC_CACHE_CLEAN_PA_OFFSET 0x07B0 /* Cache Clean by PA */ +#define XPS_L2CC_CACHE_CLEAN_INDX_OFFSET 0x07B8 /* Cache Clean by Index */ +#define XPS_L2CC_CACHE_CLEAN_WAY_OFFSET 0x07BC /* Cache Clean by Way */ +#define XPS_L2CC_CACHE_INV_CLN_PA_OFFSET 0x07F0 /* Cache Invalidate and Clean by PA */ +#define XPS_L2CC_CACHE_INV_CLN_INDX_OFFSET 0x07F8 /* Cache Invalidate and Clean by Index */ +#define XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET 0x07FC /* Cache Invalidate and Clean by Way */ + +#define XPS_L2CC_CACHE_DLCKDWN_0_WAY_OFFSET 0x0900 /* Cache Data Lockdown 0 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_0_WAY_OFFSET 0x0904 /* Cache Instruction Lockdown 0 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_1_WAY_OFFSET 0x0908 /* Cache Data Lockdown 1 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_1_WAY_OFFSET 0x090C /* Cache Instruction Lockdown 1 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_2_WAY_OFFSET 0x0910 /* Cache Data Lockdown 2 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_2_WAY_OFFSET 0x0914 /* Cache Instruction Lockdown 2 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_3_WAY_OFFSET 0x0918 /* Cache Data Lockdown 3 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_3_WAY_OFFSET 0x091C /* Cache Instruction Lockdown 3 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_4_WAY_OFFSET 0x0920 /* Cache Data Lockdown 4 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_4_WAY_OFFSET 0x0924 /* Cache Instruction Lockdown 4 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_5_WAY_OFFSET 0x0928 /* Cache Data Lockdown 5 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_5_WAY_OFFSET 0x092C /* Cache Instruction Lockdown 5 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_6_WAY_OFFSET 0x0930 /* Cache Data Lockdown 6 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_6_WAY_OFFSET 0x0934 /* Cache Instruction Lockdown 6 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_7_WAY_OFFSET 0x0938 /* Cache Data Lockdown 7 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_7_WAY_OFFSET 0x093C /* Cache Instruction Lockdown 7 by Way */ + +#define XPS_L2CC_CACHE_LCKDWN_LINE_ENABLE_OFFSET 0x0950 /* Cache Lockdown Line Enable */ +#define XPS_L2CC_CACHE_UUNLOCK_ALL_WAY_OFFSET 0x0954 /* Cache Unlock All Lines by Way */ + +#define XPS_L2CC_ADDR_FILTER_START_OFFSET 0x0C00 /* Start of address filtering */ +#define XPS_L2CC_ADDR_FILTER_END_OFFSET 0x0C04 /* Start of address filtering */ + +#define XPS_L2CC_DEBUG_CTRL_OFFSET 0x0F40 /* Debug Control Register */ + +/* XPS_L2CC_CNTRL_OFFSET bit masks */ +#define XPS_L2CC_ENABLE_MASK 0x00000001 /* enables the L2CC */ + +/* XPS_L2CC_AUX_CNTRL_OFFSET bit masks */ +#define XPS_L2CC_AUX_EBRESPE_MASK 0x40000000 /* Early BRESP Enable */ +#define XPS_L2CC_AUX_IPFE_MASK 0x20000000 /* Instruction Prefetch Enable */ +#define XPS_L2CC_AUX_DPFE_MASK 0x10000000 /* Data Prefetch Enable */ +#define XPS_L2CC_AUX_NSIC_MASK 0x08000000 /* Non-secure interrupt access control */ +#define XPS_L2CC_AUX_NSLE_MASK 0x04000000 /* Non-secure lockdown enable */ +#define XPS_L2CC_AUX_CRP_MASK 0x02000000 /* Cache replacement policy */ +#define XPS_L2CC_AUX_FWE_MASK 0x01800000 /* Force write allocate */ +#define XPS_L2CC_AUX_SAOE_MASK 0x00400000 /* Shared attribute override enable */ +#define XPS_L2CC_AUX_PE_MASK 0x00200000 /* Parity enable */ +#define XPS_L2CC_AUX_EMBE_MASK 0x00100000 /* Event monitor bus enable */ +#define XPS_L2CC_AUX_WAY_SIZE_MASK 0x000E0000 /* Way-size */ +#define XPS_L2CC_AUX_ASSOC_MASK 0x00010000 /* Associativity */ +#define XPS_L2CC_AUX_SAIE_MASK 0x00002000 /* Shared attribute invalidate enable */ +#define XPS_L2CC_AUX_EXCL_CACHE_MASK 0x00001000 /* Exclusive cache configuration */ +#define XPS_L2CC_AUX_SBDLE_MASK 0x00000800 /* Store buffer device limitation Enable */ +#define XPS_L2CC_AUX_HPSODRE_MASK 0x00000400 /* High Priority for SO and Dev Reads Enable */ +#define XPS_L2CC_AUX_FLZE_MASK 0x00000001 /* Full line of zero enable */ + +#define XPS_L2CC_AUX_REG_DEFAULT_MASK 0x72360000 /* Enable all prefetching, */ + /* Cache replacement policy, Parity enable, */ + /* Event monitor bus enable and Way Size (64 KB) */ +#define XPS_L2CC_AUX_REG_ZERO_MASK 0xFFF1FFFF /* */ + +#define XPS_L2CC_TAG_RAM_DEFAULT_MASK 0x00000111 /* latency for TAG RAM */ +#define XPS_L2CC_DATA_RAM_DEFAULT_MASK 0x00000121 /* latency for DATA RAM */ + +/* Interrupt bit masks */ +#define XPS_L2CC_IXR_DECERR_MASK 0x00000100 /* DECERR from L3 */ +#define XPS_L2CC_IXR_SLVERR_MASK 0x00000080 /* SLVERR from L3 */ +#define XPS_L2CC_IXR_ERRRD_MASK 0x00000040 /* Error on L2 data RAM (Read) */ +#define XPS_L2CC_IXR_ERRRT_MASK 0x00000020 /* Error on L2 tag RAM (Read) */ +#define XPS_L2CC_IXR_ERRWD_MASK 0x00000010 /* Error on L2 data RAM (Write) */ +#define XPS_L2CC_IXR_ERRWT_MASK 0x00000008 /* Error on L2 tag RAM (Write) */ +#define XPS_L2CC_IXR_PARRD_MASK 0x00000004 /* Parity Error on L2 data RAM (Read) */ +#define XPS_L2CC_IXR_PARRT_MASK 0x00000002 /* Parity Error on L2 tag RAM (Read) */ +#define XPS_L2CC_IXR_ECNTR_MASK 0x00000001 /* Event Counter1/0 Overflow Increment */ + +/* Address filtering mask and enable bit */ +#define XPS_L2CC_ADDR_FILTER_VALID_MASK 0xFFF00000 /* Address filtering valid bits*/ +#define XPS_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001 /* Address filtering enable bit*/ + +/* Debug control bits */ +#define XPS_L2CC_DEBUG_SPIDEN_MASK 0x00000004 /* Debug SPIDEN bit */ +#define XPS_L2CC_DEBUG_DWB_MASK 0x00000002 /* Debug DWB bit, forces write through */ +#define XPS_L2CC_DEBUG_DCL_MASK 0x00000002 /* Debug DCL bit, disables cache line fill */ + +#ifdef __cplusplus +} +#endif + +#endif /* protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xl2cc_counter.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xl2cc_counter.h new file mode 100644 index 000000000..30952b1dc --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xl2cc_counter.h @@ -0,0 +1,117 @@ +/****************************************************************************** +* +* (c) Copyright 2011-13 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xl2cc_counter.h +* +* This header file contains APIs for configuring and controlling the event +* counters in PL310 L2 cache controller. +* PL310 has 2 event counters which can be used to count a variety of events +* like DRHIT, DRREQ, DWHIT, DWREQ, etc. This file defines configurations, +* where value configures the event counters to count a set of events. +* +* XL2cc_EventCtrInit API can be used to select a set of events and +* XL2cc_EventCtrStart configures the event counters and starts the counters. +* XL2cc_EventCtrStop diables the event counters and returns the counter values. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm  07/11/11 First release
+* 3.07a asa  08/30/12 Updated for CR 675636 to provide the L2 Base Address
+*		      inside the APIs
+*
+* +******************************************************************************/ + +#ifndef L2CCCOUNTER_H /* prevent circular inclusions */ +#define L2CCCOUNTER_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xpseudo_asm.h" +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/************************** Constant Definitions ****************************/ + +/* + * The following constants define the event codes for the event counters. + */ +#define XL2CC_CO 0x1 +#define XL2CC_DRHIT 0x2 +#define XL2CC_DRREQ 0x3 +#define XL2CC_DWHIT 0x4 +#define XL2CC_DWREQ 0x5 +#define XL2CC_DWTREQ 0x6 +#define XL2CC_IRHIT 0x7 +#define XL2CC_IRREQ 0x8 +#define XL2CC_WA 0x9 +#define XL2CC_IPFALLOC 0xa +#define XL2CC_EPFHIT 0xb +#define XL2CC_EPFALLOC 0xc +#define XL2CC_SRRCVD 0xd +#define XL2CC_SRCONF 0xe +#define XL2CC_EPFRCVD 0xf + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +void XL2cc_EventCtrInit(int Event0, int Event1); +void XL2cc_EventCtrStart(void); +void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* L2CCCOUNTER_H */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xparameters.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xparameters.h new file mode 100644 index 000000000..70c826619 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xparameters.h @@ -0,0 +1,475 @@ +/* Definition for CPU ID */ +#define XPAR_CPU_ID 0 + +/* Definitions for peripheral PS7_CORTEXA9_0 */ +#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_CORTEXA9_0 */ +#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687 + + +/******************************************************************/ + +#include "xparameters_ps.h" + +#define STDIN_BASEADDRESS 0xE0001000 +#define STDOUT_BASEADDRESS 0xE0001000 + +/******************************************************************/ + +/* Definitions for driver CANPS */ +#define XPAR_XCANPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_CAN_0 */ +#define XPAR_PS7_CAN_0_DEVICE_ID 0 +#define XPAR_PS7_CAN_0_BASEADDR 0xE0008000 +#define XPAR_PS7_CAN_0_HIGHADDR 0xE0008FFF +#define XPAR_PS7_CAN_0_CAN_CLK_FREQ_HZ 23809523 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_CAN_0 */ +#define XPAR_XCANPS_0_DEVICE_ID XPAR_PS7_CAN_0_DEVICE_ID +#define XPAR_XCANPS_0_BASEADDR 0xE0008000 +#define XPAR_XCANPS_0_HIGHADDR 0xE0008FFF +#define XPAR_XCANPS_0_CAN_CLK_FREQ_HZ 23809523 + + +/******************************************************************/ + +/* Definitions for driver DEVCFG */ +#define XPAR_XDCFG_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_DEV_CFG_0 */ +#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0 +#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000 +#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_DEV_CFG_0 */ +#define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID +#define XPAR_XDCFG_0_BASEADDR 0xF8007000 +#define XPAR_XDCFG_0_HIGHADDR 0xF80070FF + + +/******************************************************************/ + +/* Definitions for driver DMAPS */ +#define XPAR_XDMAPS_NUM_INSTANCES 2 + +/* Definitions for peripheral PS7_DMA_NS */ +#define XPAR_PS7_DMA_NS_DEVICE_ID 0 +#define XPAR_PS7_DMA_NS_BASEADDR 0xF8004000 +#define XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF + + +/* Definitions for peripheral PS7_DMA_S */ +#define XPAR_PS7_DMA_S_DEVICE_ID 1 +#define XPAR_PS7_DMA_S_BASEADDR 0xF8003000 +#define XPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_DMA_NS */ +#define XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_ID +#define XPAR_XDMAPS_0_BASEADDR 0xF8004000 +#define XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF + +/* Canonical definitions for peripheral PS7_DMA_S */ +#define XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_ID +#define XPAR_XDMAPS_1_BASEADDR 0xF8003000 +#define XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF + + +/******************************************************************/ + +/* Definitions for driver EMACPS */ +#define XPAR_XEMACPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_ETHERNET_0 */ +#define XPAR_PS7_ETHERNET_0_DEVICE_ID 0 +#define XPAR_PS7_ETHERNET_0_BASEADDR 0xE000B000 +#define XPAR_PS7_ETHERNET_0_HIGHADDR 0xE000BFFF +#define XPAR_PS7_ETHERNET_0_ENET_CLK_FREQ_HZ 25000000 +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 8 +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 1 +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 8 +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 5 +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 8 +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 50 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_ETHERNET_0 */ +#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID +#define XPAR_XEMACPS_0_BASEADDR 0xE000B000 +#define XPAR_XEMACPS_0_HIGHADDR 0xE000BFFF +#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 25000000 +#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 8 +#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1 +#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 8 +#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 5 +#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 8 +#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50 + + +/******************************************************************/ + + +/* Definitions for peripheral PS7_AFI_0 */ +#define XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000 +#define XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFF + + +/* Definitions for peripheral PS7_AFI_1 */ +#define XPAR_PS7_AFI_1_S_AXI_BASEADDR 0xF8009000 +#define XPAR_PS7_AFI_1_S_AXI_HIGHADDR 0xF8009FFF + + +/* Definitions for peripheral PS7_AFI_2 */ +#define XPAR_PS7_AFI_2_S_AXI_BASEADDR 0xF800A000 +#define XPAR_PS7_AFI_2_S_AXI_HIGHADDR 0xF800AFFF + + +/* Definitions for peripheral PS7_AFI_3 */ +#define XPAR_PS7_AFI_3_S_AXI_BASEADDR 0xF800B000 +#define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF + + +/* Definitions for peripheral PS7_CORESIGHT_COMP_0 */ +#define XPAR_PS7_CORESIGHT_COMP_0_S_AXI_BASEADDR 0xF8800000 +#define XPAR_PS7_CORESIGHT_COMP_0_S_AXI_HIGHADDR 0xF88FFFFF + + +/* Definitions for peripheral PS7_DDR_0 */ +#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000 +#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x3FFFFFFF + + +/* Definitions for peripheral PS7_DDRC_0 */ +#define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000 +#define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF + + +/* Definitions for peripheral PS7_GLOBALTIMER_0 */ +#define XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR 0xF8F00200 +#define XPAR_PS7_GLOBALTIMER_0_S_AXI_HIGHADDR 0xF8F002FF + + +/* Definitions for peripheral PS7_GPV_0 */ +#define XPAR_PS7_GPV_0_S_AXI_BASEADDR 0xF8900000 +#define XPAR_PS7_GPV_0_S_AXI_HIGHADDR 0xF89FFFFF + + +/* Definitions for peripheral PS7_INTC_DIST_0 */ +#define XPAR_PS7_INTC_DIST_0_S_AXI_BASEADDR 0xF8F01000 +#define XPAR_PS7_INTC_DIST_0_S_AXI_HIGHADDR 0xF8F01FFF + + +/* Definitions for peripheral PS7_IOP_BUS_CONFIG_0 */ +#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000 +#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF + + +/* Definitions for peripheral PS7_L2CACHEC_0 */ +#define XPAR_PS7_L2CACHEC_0_S_AXI_BASEADDR 0xF8F02000 +#define XPAR_PS7_L2CACHEC_0_S_AXI_HIGHADDR 0xF8F02FFF + + +/* Definitions for peripheral PS7_OCMC_0 */ +#define XPAR_PS7_OCMC_0_S_AXI_BASEADDR 0xF800C000 +#define XPAR_PS7_OCMC_0_S_AXI_HIGHADDR 0xF800CFFF + + +/* Definitions for peripheral PS7_PL310_0 */ +#define XPAR_PS7_PL310_0_S_AXI_BASEADDR 0xF8F02000 +#define XPAR_PS7_PL310_0_S_AXI_HIGHADDR 0xF8F02FFF + + +/* Definitions for peripheral PS7_PMU_0 */ +#define XPAR_PS7_PMU_0_S_AXI_BASEADDR 0xF8891000 +#define XPAR_PS7_PMU_0_S_AXI_HIGHADDR 0xF8891FFF +#define XPAR_PS7_PMU_0_PMU1_S_AXI_BASEADDR 0xF8893000 +#define XPAR_PS7_PMU_0_PMU1_S_AXI_HIGHADDR 0xF8893FFF + + +/* Definitions for peripheral PS7_QSPI_LINEAR_0 */ +#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000 +#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xFCFFFFFF + + +/* Definitions for peripheral PS7_RAM_0 */ +#define XPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000 +#define XPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0003FFFF + + +/* Definitions for peripheral PS7_RAM_1 */ +#define XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFC0000 +#define XPAR_PS7_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF + + +/* Definitions for peripheral PS7_SCUC_0 */ +#define XPAR_PS7_SCUC_0_S_AXI_BASEADDR 0xF8F00000 +#define XPAR_PS7_SCUC_0_S_AXI_HIGHADDR 0xF8F000FC + + +/* Definitions for peripheral PS7_SLCR_0 */ +#define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000 +#define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF + + +/******************************************************************/ + +/* Definitions for driver GPIOPS */ +#define XPAR_XGPIOPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_GPIO_0 */ +#define XPAR_PS7_GPIO_0_DEVICE_ID 0 +#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000 +#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_GPIO_0 */ +#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID +#define XPAR_XGPIOPS_0_BASEADDR 0xE000A000 +#define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF + + +/******************************************************************/ + +/* Definitions for driver IICPS */ +#define XPAR_XIICPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_I2C_0 */ +#define XPAR_PS7_I2C_0_DEVICE_ID 0 +#define XPAR_PS7_I2C_0_BASEADDR 0xE0004000 +#define XPAR_PS7_I2C_0_HIGHADDR 0xE0004FFF +#define XPAR_PS7_I2C_0_I2C_CLK_FREQ_HZ 111111115 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_I2C_0 */ +#define XPAR_XIICPS_0_DEVICE_ID XPAR_PS7_I2C_0_DEVICE_ID +#define XPAR_XIICPS_0_BASEADDR 0xE0004000 +#define XPAR_XIICPS_0_HIGHADDR 0xE0004FFF +#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 111111115 + + +/******************************************************************/ + +/* Definitions for driver QSPIPS */ +#define XPAR_XQSPIPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_QSPI_0 */ +#define XPAR_PS7_QSPI_0_DEVICE_ID 0 +#define XPAR_PS7_QSPI_0_BASEADDR 0xE000D000 +#define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF +#define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 200000000 +#define XPAR_PS7_QSPI_0_QSPI_MODE 0 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_QSPI_0 */ +#define XPAR_XQSPIPS_0_DEVICE_ID XPAR_PS7_QSPI_0_DEVICE_ID +#define XPAR_XQSPIPS_0_BASEADDR 0xE000D000 +#define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF +#define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 200000000 +#define XPAR_XQSPIPS_0_QSPI_MODE 0 + + +/******************************************************************/ + + +/***Definitions for Core_nIRQ/nFIQ interrupts ****/ +/* Definitions for driver SCUGIC */ +#define XPAR_XSCUGIC_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_SCUGIC_0 */ +#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0 +#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100 +#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FF +#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_SCUGIC_0 */ +#define XPAR_SCUGIC_0_DEVICE_ID 0 +#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100 +#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FF +#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000 + + +/******************************************************************/ + +/* Definitions for driver SCUTIMER */ +#define XPAR_XSCUTIMER_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_SCUTIMER_0 */ +#define XPAR_PS7_SCUTIMER_0_DEVICE_ID 0 +#define XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600 +#define XPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061F + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_SCUTIMER_0 */ +#define XPAR_XSCUTIMER_0_DEVICE_ID XPAR_PS7_SCUTIMER_0_DEVICE_ID +#define XPAR_XSCUTIMER_0_BASEADDR 0xF8F00600 +#define XPAR_XSCUTIMER_0_HIGHADDR 0xF8F0061F + + +/******************************************************************/ + +/* Definitions for driver SCUWDT */ +#define XPAR_XSCUWDT_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_SCUWDT_0 */ +#define XPAR_PS7_SCUWDT_0_DEVICE_ID 0 +#define XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620 +#define XPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_SCUWDT_0 */ +#define XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_ID +#define XPAR_SCUWDT_0_BASEADDR 0xF8F00620 +#define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF + + +/******************************************************************/ + +/* Definitions for driver SDPS */ +#define XPAR_XSDPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_SD_0 */ +#define XPAR_PS7_SD_0_DEVICE_ID 0 +#define XPAR_PS7_SD_0_BASEADDR 0xE0100000 +#define XPAR_PS7_SD_0_HIGHADDR 0xE0100FFF +#define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_SD_0 */ +#define XPAR_XSDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_ID +#define XPAR_XSDPS_0_BASEADDR 0xE0100000 +#define XPAR_XSDPS_0_HIGHADDR 0xE0100FFF +#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 50000000 + + +/******************************************************************/ + +/* Definitions for driver TTCPS */ +#define XPAR_XTTCPS_NUM_INSTANCES 3 + +/* Definitions for peripheral PS7_TTC_0 */ +#define XPAR_PS7_TTC_0_DEVICE_ID 0 +#define XPAR_PS7_TTC_0_BASEADDR 0XF8001000 +#define XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 111111115 +#define XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0 +#define XPAR_PS7_TTC_1_DEVICE_ID 1 +#define XPAR_PS7_TTC_1_BASEADDR 0XF8001004 +#define XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 111111115 +#define XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0 +#define XPAR_PS7_TTC_2_DEVICE_ID 2 +#define XPAR_PS7_TTC_2_BASEADDR 0XF8001008 +#define XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 111111115 +#define XPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_TTC_0 */ +#define XPAR_XTTCPS_0_DEVICE_ID XPAR_PS7_TTC_0_DEVICE_ID +#define XPAR_XTTCPS_0_BASEADDR 0xF8001000 +#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 111111115 +#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0 + +#define XPAR_XTTCPS_1_DEVICE_ID XPAR_PS7_TTC_1_DEVICE_ID +#define XPAR_XTTCPS_1_BASEADDR 0xF8001004 +#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 111111115 +#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0 + +#define XPAR_XTTCPS_2_DEVICE_ID XPAR_PS7_TTC_2_DEVICE_ID +#define XPAR_XTTCPS_2_BASEADDR 0xF8001008 +#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 111111115 +#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0 + + +/******************************************************************/ + +/* Definitions for driver UARTPS */ +#define XPAR_XUARTPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_UART_1 */ +#define XPAR_PS7_UART_1_DEVICE_ID 0 +#define XPAR_PS7_UART_1_BASEADDR 0xE0001000 +#define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF +#define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 50000000 +#define XPAR_PS7_UART_1_HAS_MODEM 0 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_UART_1 */ +#define XPAR_XUARTPS_0_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID +#define XPAR_XUARTPS_0_BASEADDR 0xE0001000 +#define XPAR_XUARTPS_0_HIGHADDR 0xE0001FFF +#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 50000000 +#define XPAR_XUARTPS_0_HAS_MODEM 0 + + +/******************************************************************/ + +/* Definitions for driver USBPS */ +#define XPAR_XUSBPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_USB_0 */ +#define XPAR_PS7_USB_0_DEVICE_ID 0 +#define XPAR_PS7_USB_0_BASEADDR 0xE0002000 +#define XPAR_PS7_USB_0_HIGHADDR 0xE0002FFF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_USB_0 */ +#define XPAR_XUSBPS_0_DEVICE_ID XPAR_PS7_USB_0_DEVICE_ID +#define XPAR_XUSBPS_0_BASEADDR 0xE0002000 +#define XPAR_XUSBPS_0_HIGHADDR 0xE0002FFF + + +/******************************************************************/ + +/* Definitions for driver XADCPS */ +#define XPAR_XADCPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_XADC_0 */ +#define XPAR_PS7_XADC_0_DEVICE_ID 0 +#define XPAR_PS7_XADC_0_BASEADDR 0xF8007100 +#define XPAR_PS7_XADC_0_HIGHADDR 0xF8007120 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_XADC_0 */ +#define XPAR_XADCPS_0_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID +#define XPAR_XADCPS_0_BASEADDR 0xF8007100 +#define XPAR_XADCPS_0_HIGHADDR 0xF8007120 + + +/******************************************************************/ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xparameters_ps.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xparameters_ps.h new file mode 100644 index 000000000..766e1705b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xparameters_ps.h @@ -0,0 +1,334 @@ +/****************************************************************************** +* +* (c) Copyright 2010-2013 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xparameters_ps.h +* +* This file contains the address definitions for the hard peripherals +* attached to the ARM Cortex A9 core. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 02/01/10 Initial version
+* 3.04a sdm     02/02/12 Removed some of the defines as they are being generated through
+*                        driver tcl
+*
+* +* @note +* +* None. +* +******************************************************************************/ + +#ifndef _XPARAMETERS_PS_H_ +#define _XPARAMETERS_PS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ + +/* + * This block contains constant declarations for the peripherals + * within the hardblock + */ + +/* Canonical definitions for DDR MEMORY */ +#define XPAR_DDR_MEM_BASEADDR 0x00000000 +#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFF + +/* Canonical definitions for Interrupts */ +#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID +#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID +#define XPAR_XUSBPS_0_INTR XPS_USB0_INT_ID +#define XPAR_XUSBPS_1_INTR XPS_USB1_INT_ID +#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID +#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID +#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID +#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID +#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID +#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID +#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID +#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID +#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID +#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID +#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID +#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID +#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID +#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID +#define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID +#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID +#define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID +#define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID +#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID +#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID +#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID +#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID +#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID +#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID +#define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID + + +#define XPAR_XQSPIPS_0_LINEAR_BASEADDR XPS_QSPI_LINEAR_BASEADDR +#define XPAR_XPARPORTPS_CTRL_BASEADDR XPS_PARPORT_CRTL_BASEADDR + + + +/* Canonical definitions for DMAC */ + + +/* Canonical definitions for WDT */ + +/* Canonical definitions for SLCR */ +#define XPAR_XSLCR_NUM_INSTANCES 1 +#define XPAR_XSLCR_0_DEVICE_ID 0 +#define XPAR_XSLCR_0_BASEADDR XPS_SYS_CTRL_BASEADDR + +/* Canonical definitions for SCU GIC */ +#define XPAR_SCUGIC_NUM_INSTANCES 1 +#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0 +#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x0100) +#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x1000) +#define XPAR_SCUGIC_ACK_BEFORE 0 + +/* Canonical definitions for Global Timer */ +#define XPAR_GLOBAL_TMR_NUM_INSTANCES 1 +#define XPAR_GLOBAL_TMR_DEVICE_ID 0 +#define XPAR_GLOBAL_TMR_BASEADDR (XPS_SCU_PERIPH_BASE + 0x200) +#define XPAR_GLOBAL_TMR_INTR XPS_GLOBAL_TMR_INT_ID + + +/* Xilinx Parallel Flash Library (XilFlash) User Settings */ +#define XPAR_AXI_EMC + + +#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ + + +/* + * This block contains constant declarations for the peripherals + * within the hardblock. These have been put for bacwards compatibilty + */ + +#define XPS_PERIPHERAL_BASEADDR 0xE0000000 +#define XPS_UART0_BASEADDR 0xE0000000 +#define XPS_UART1_BASEADDR 0xE0001000 +#define XPS_USB0_BASEADDR 0xE0002000 +#define XPS_USB1_BASEADDR 0xE0003000 +#define XPS_I2C0_BASEADDR 0xE0004000 +#define XPS_I2C1_BASEADDR 0xE0005000 +#define XPS_SPI0_BASEADDR 0xE0006000 +#define XPS_SPI1_BASEADDR 0xE0007000 +#define XPS_CAN0_BASEADDR 0xE0008000 +#define XPS_CAN1_BASEADDR 0xE0009000 +#define XPS_GPIO_BASEADDR 0xE000A000 +#define XPS_GEM0_BASEADDR 0xE000B000 +#define XPS_GEM1_BASEADDR 0xE000C000 +#define XPS_QSPI_BASEADDR 0xE000D000 +#define XPS_PARPORT_CRTL_BASEADDR 0xE000E000 +#define XPS_SDIO0_BASEADDR 0xE0100000 +#define XPS_SDIO1_BASEADDR 0xE0101000 +#define XPS_IOU_BUS_CFG_BASEADDR 0xE0200000 +#define XPS_NAND_BASEADDR 0xE1000000 +#define XPS_PARPORT0_BASEADDR 0xE2000000 +#define XPS_PARPORT1_BASEADDR 0xE4000000 +#define XPS_QSPI_LINEAR_BASEADDR 0xFC000000 +#define XPS_SYS_CTRL_BASEADDR 0xF8000000 /* AKA SLCR */ +#define XPS_TTC0_BASEADDR 0xF8001000 +#define XPS_TTC1_BASEADDR 0xF8002000 +#define XPS_DMAC0_SEC_BASEADDR 0xF8003000 +#define XPS_DMAC0_NON_SEC_BASEADDR 0xF8004000 +#define XPS_WDT_BASEADDR 0xF8005000 +#define XPS_DDR_CTRL_BASEADDR 0xF8006000 +#define XPS_DEV_CFG_APB_BASEADDR 0xF8007000 +#define XPS_AFI0_BASEADDR 0xF8008000 +#define XPS_AFI1_BASEADDR 0xF8009000 +#define XPS_AFI2_BASEADDR 0xF800A000 +#define XPS_AFI3_BASEADDR 0xF800B000 +#define XPS_OCM_BASEADDR 0xF800C000 +#define XPS_EFUSE_BASEADDR 0xF800D000 +#define XPS_CORESIGHT_BASEADDR 0xF8800000 +#define XPS_TOP_BUS_CFG_BASEADDR 0xF8900000 +#define XPS_SCU_PERIPH_BASE 0xF8F00000 +#define XPS_L2CC_BASEADDR 0xF8F02000 +#define XPS_SAM_RAM_BASEADDR 0xFFFC0000 +#define XPS_FPGA_AXI_S0_BASEADDR 0x40000000 +#define XPS_FPGA_AXI_S1_BASEADDR 0x80000000 +#define XPS_IOU_S_SWITCH_BASEADDR 0xE0000000 +#define XPS_PERIPH_APB_BASEADDR 0xF8000000 + +/* Shared Peripheral Interrupts (SPI) */ +#define XPS_CORE_PARITY0_INT_ID 32 +#define XPS_CORE_PARITY1_INT_ID 33 +#define XPS_L2CC_INT_ID 34 +#define XPS_OCMINTR_INT_ID 35 +#define XPS_ECC_INT_ID 36 +#define XPS_PMU0_INT_ID 37 +#define XPS_PMU1_INT_ID 38 +#define XPS_SYSMON_INT_ID 39 +#define XPS_DVC_INT_ID 40 +#define XPS_WDT_INT_ID 41 +#define XPS_TTC0_0_INT_ID 42 +#define XPS_TTC0_1_INT_ID 43 +#define XPS_TTC0_2_INT_ID 44 +#define XPS_DMA0_ABORT_INT_ID 45 +#define XPS_DMA0_INT_ID 46 +#define XPS_DMA1_INT_ID 47 +#define XPS_DMA2_INT_ID 48 +#define XPS_DMA3_INT_ID 49 +#define XPS_SMC_INT_ID 50 +#define XPS_QSPI_INT_ID 51 +#define XPS_GPIO_INT_ID 52 +#define XPS_USB0_INT_ID 53 +#define XPS_GEM0_INT_ID 54 +#define XPS_GEM0_WAKE_INT_ID 55 +#define XPS_SDIO0_INT_ID 56 +#define XPS_I2C0_INT_ID 57 +#define XPS_SPI0_INT_ID 58 +#define XPS_UART0_INT_ID 59 +#define XPS_CAN0_INT_ID 60 +#define XPS_FPGA0_INT_ID 61 +#define XPS_FPGA1_INT_ID 62 +#define XPS_FPGA2_INT_ID 63 +#define XPS_FPGA3_INT_ID 64 +#define XPS_FPGA4_INT_ID 65 +#define XPS_FPGA5_INT_ID 66 +#define XPS_FPGA6_INT_ID 67 +#define XPS_FPGA7_INT_ID 68 +#define XPS_TTC1_0_INT_ID 69 +#define XPS_TTC1_1_INT_ID 70 +#define XPS_TTC1_2_INT_ID 71 +#define XPS_DMA4_INT_ID 72 +#define XPS_DMA5_INT_ID 73 +#define XPS_DMA6_INT_ID 74 +#define XPS_DMA7_INT_ID 75 +#define XPS_USB1_INT_ID 76 +#define XPS_GEM1_INT_ID 77 +#define XPS_GEM1_WAKE_INT_ID 78 +#define XPS_SDIO1_INT_ID 79 +#define XPS_I2C1_INT_ID 80 +#define XPS_SPI1_INT_ID 81 +#define XPS_UART1_INT_ID 82 +#define XPS_CAN1_INT_ID 83 +#define XPS_FPGA8_INT_ID 84 +#define XPS_FPGA9_INT_ID 85 +#define XPS_FPGA10_INT_ID 86 +#define XPS_FPGA11_INT_ID 87 +#define XPS_FPGA12_INT_ID 88 +#define XPS_FPGA13_INT_ID 89 +#define XPS_FPGA14_INT_ID 90 +#define XPS_FPGA15_INT_ID 91 + +/* Private Peripheral Interrupts (PPI) */ +#define XPS_GLOBAL_TMR_INT_ID 27 /* SCU Global Timer interrupt */ +#define XPS_FIQ_INT_ID 28 /* FIQ from FPGA fabric */ +#define XPS_SCU_TMR_INT_ID 29 /* SCU Private Timer interrupt */ +#define XPS_SCU_WDT_INT_ID 30 /* SCU Private WDT interrupt */ +#define XPS_IRQ_INT_ID 31 /* IRQ from FPGA fabric */ + + +/* REDEFINES for TEST APP */ +/* Definitions for UART */ +#define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID +#define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID +#define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID +#define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID +#define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID +#define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID +#define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID +#define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID +#define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID +#define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID +#define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID +#define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID +#define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID +#define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID +#define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID +#define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID +#define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID +#define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID +#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID +#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID + +#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID + +/* For backwards compatibilty */ +#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ +#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ +#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ +#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ +#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ + +#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ + +#ifdef XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ +#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ +#endif + +#ifdef XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ +#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ +#endif + +#define XPAR_SCUTIMER_DEVICE_ID 0 +#define XPAR_SCUWDT_DEVICE_ID 0 + + +#ifdef __cplusplus +} +#endif + +#endif /* protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xpm_counter.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xpm_counter.h new file mode 100644 index 000000000..2ef3f9fab --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xpm_counter.h @@ -0,0 +1,580 @@ +/****************************************************************************** +* +* (c) Copyright 2011-13 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xpm_counter.h +* +* This header file contains APIs for configuring and controlling the Cortex-A9 +* Performance Monitor Events. +* Cortex-A9 Performance Monitor has 6 event counters which can be used to +* count a variety of events described in Coretx-A9 TRM. This file defines +* configurations, where value configures the event counters to count a +* set of events. +* +* Xpm_SetEvents can be used to set the event counters to count a set of events +* and Xpm_GetEventCounters can be used to read the counter values. +* +* @note +* +* This file doesn't handle the Cortex-A9 cycle counter, as the cycle counter is +* being used for time keeping. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm  07/11/11 First release
+*
+* +******************************************************************************/ + +#ifndef XPMCOUNTER_H /* prevent circular inclusions */ +#define XPMCOUNTER_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include +#include "xpseudo_asm.h" +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/************************** Constant Definitions ****************************/ + +/* Number of performance counters */ +#define XPM_CTRCOUNT 6 + +/* The following constants define the Cortex-A9 Performance Monitor Events */ + +/* + * Software increment. The register is incremented only on writes to the + * Software Increment Register + */ +#define XPM_EVENT_SOFTINCR 0x00 + +/* + * Instruction fetch that causes a refill at (at least) the lowest level(s) of + * instruction or unified cache. Includes the speculative linefills in the + * count + */ +#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01 + +/* + * Instruction fetch that causes a TLB refill at (at least) the lowest level of + * TLB. Includes the speculative requests in the count + */ +#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02 + +/* + * Data read or write operation that causes a refill at (at least) the lowest + * level(s)of data or unified cache. Counts the number of allocations performed + * in the Data Cache due to a read or a write + */ +#define XPM_EVENT_DATA_CACHEREFILL 0x03 + +/* + * Data read or write operation that causes a cache access at (at least) the + * lowest level(s) of data or unified cache. This includes speculative reads + */ +#define XPM_EVENT_DATA_CACHEACCESS 0x04 + +/* + * Data read or write operation that causes a TLB refill at (at least) the + * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI, + * CP15 Cache operation by MVA and CP15 VA to PA operations + */ +#define XPM_EVENT_DATA_TLBREFILL 0x05 + +/* + * Data read architecturally executed. Counts the number of data read + * instructions accepted by the Load Store Unit. This includes counting the + * speculative and aborted LDR/LDM, as well as the reads due to the SWP + * instructions + */ +#define XPM_EVENT_DATA_READS 0x06 + +/* + * Data write architecturally executed. Counts the number of data write + * instructions accepted by the Load Store Unit. This includes counting the + * speculative and aborted STR/STM, as well as the writes due to the SWP + * instructions + */ +#define XPM_EVENT_DATA_WRITE 0x07 + +/* Exception taken. Counts the number of exceptions architecturally taken.*/ +#define XPM_EVENT_EXCEPTION 0x09 + +/* Exception return architecturally executed.*/ +#define XPM_EVENT_EXCEPRETURN 0x0A + +/* + * Change to ContextID retired. Counts the number of instructions + * architecturally executed writing into the ContextID Register + */ +#define XPM_EVENT_CHANGECONTEXT 0x0B + +/* + * Software change of PC, except by an exception, architecturally executed. + * Count the number of PC changes architecturally executed, excluding the PC + * changes due to taken exceptions + */ +#define XPM_EVENT_SW_CHANGEPC 0x0C + +/* + * Immediate branch architecturally executed (taken or not taken). This includes + * the branches which are flushed due to a previous load/store which aborts + * late + */ +#define XPM_EVENT_IMMEDBRANCH 0x0D + +/* + * Unaligned access architecturally executed. Counts the number of aborted + * unaligned accessed architecturally executed, and the number of not-aborted + * unaligned accesses, including the speculative ones + */ +#define XPM_EVENT_UNALIGNEDACCESS 0x0F + +/* + * Branch mispredicted/not predicted. Counts the number of mispredicted or + * not-predicted branches executed. This includes the branches which are flushed + * due to a previous load/store which aborts late + */ +#define XPM_EVENT_BRANCHMISS 0x10 + +/* + * Counts clock cycles when the Cortex-A9 processor is not in WFE/WFI. This + * event is not exported on the PMUEVENT bus + */ +#define XPM_EVENT_CLOCKCYCLES 0x11 + +/* + * Branches or other change in program flow that could have been predicted by + * the branch prediction resources of the processor. This includes the branches + * which are flushed due to a previous load/store which aborts late + */ +#define XPM_EVENT_BRANCHPREDICT 0x12 + +/* + * Java bytecode execute. Counts the number of Java bytecodes being decoded, + * including speculative ones + */ +#define XPM_EVENT_JAVABYTECODE 0x40 + +/* + * Software Java bytecode executed. Counts the number of software java bytecodes + * being decoded, including speculative ones + */ +#define XPM_EVENT_SWJAVABYTECODE 0x41 + +/* + * Jazelle backward branches executed. Counts the number of Jazelle taken + * branches being executed. This includes the branches which are flushed due + * to a previous load/store which aborts late + */ +#define XPM_EVENT_JAVABACKBRANCH 0x42 + +/* + * Coherent linefill miss Counts the number of coherent linefill requests + * performed by the Cortex-A9 processor which also miss in all the other + * Cortex-A9 processors, meaning that the request is sent to the external + * memory + */ +#define XPM_EVENT_COHERLINEMISS 0x50 + +/* + * Coherent linefill hit. Counts the number of coherent linefill requests + * performed by the Cortex-A9 processor which hit in another Cortex-A9 + * processor, meaning that the linefill data is fetched directly from the + * relevant Cortex-A9 cache + */ +#define XPM_EVENT_COHERLINEHIT 0x51 + +/* + * Instruction cache dependent stall cycles. Counts the number of cycles where + * the processor is ready to accept new instructions, but does not receive any + * due to the instruction side not being able to provide any and the + * instruction cache is currently performing at least one linefill + */ +#define XPM_EVENT_INSTRSTALL 0x60 + +/* + * Data cache dependent stall cycles. Counts the number of cycles where the core + * has some instructions that it cannot issue to any pipeline, and the Load + * Store unit has at least one pending linefill request, and no pending + */ +#define XPM_EVENT_DATASTALL 0x61 + +/* + * Main TLB miss stall cycles. Counts the number of cycles where the processor + * is stalled waiting for the completion of translation table walks from the + * main TLB. The processor stalls can be due to the instruction side not being + * able to provide the instructions, or to the data side not being able to + * provide the necessary data, due to them waiting for the main TLB translation + * table walk to complete + */ +#define XPM_EVENT_MAINTLBSTALL 0x62 + +/* + * Counts the number of STREX instructions architecturally executed and + * passed + */ +#define XPM_EVENT_STREXPASS 0x63 + +/* + * Counts the number of STREX instructions architecturally executed and + * failed + */ +#define XPM_EVENT_STREXFAIL 0x64 + +/* + * Data eviction. Counts the number of eviction requests due to a linefill in + * the data cache + */ +#define XPM_EVENT_DATAEVICT 0x65 + +/* + * Counts the number of cycles where the issue stage does not dispatch any + * instruction because it is empty or cannot dispatch any instructions + */ +#define XPM_EVENT_NODISPATCH 0x66 + +/* + * Counts the number of cycles where the issue stage is empty + */ +#define XPM_EVENT_ISSUEEMPTY 0x67 + +/* + * Counts the number of instructions going through the Register Renaming stage. + * This number is an approximate number of the total number of instructions + * speculatively executed, and even more approximate of the total number of + * instructions architecturally executed. The approximation depends mainly on + * the branch misprediction rate. + * The renaming stage can handle two instructions in the same cycle so the event + * is two bits long: + * - b00 no instructions renamed + * - b01 one instruction renamed + * - b10 two instructions renamed + */ +#define XPM_EVENT_INSTRRENAME 0x68 + +/* + * Counts the number of procedure returns whose condition codes do not fail, + * excluding all returns from exception. This count includes procedure returns + * which are flushed due to a previous load/store which aborts late. + * Only the following instructions are reported: + * - BX R14 + * - MOV PC LR + * - POP {..,pc} + * - LDR pc,[sp],#offset + * The following instructions are not reported: + * - LDMIA R9!,{..,PC} (ThumbEE state only) + * - LDR PC,[R9],#offset (ThumbEE state only) + * - BX R0 (Rm != R14) + * - MOV PC,R0 (Rm != R14) + * - LDM SP,{...,PC} (writeback not specified) + * - LDR PC,[SP,#offset] (wrong addressing mode) + */ +#define XPM_EVENT_PREDICTFUNCRET 0x6E + +/* + * Counts the number of instructions being executed in the main execution + * pipeline of the processor, the multiply pipeline and arithmetic logic unit + * pipeline. The counted instructions are still speculative + */ +#define XPM_EVENT_MAINEXEC 0x70 + +/* + * Counts the number of instructions being executed in the processor second + * execution pipeline (ALU). The counted instructions are still speculative + */ +#define XPM_EVENT_SECEXEC 0x71 + +/* + * Counts the number of instructions being executed in the Load/Store unit. The + * counted instructions are still speculative + */ +#define XPM_EVENT_LDRSTR 0x72 + +/* + * Counts the number of Floating-point instructions going through the Register + * Rename stage. Instructions are still speculative in this stage. + *Two floating-point instructions can be renamed in the same cycle so the event + * is two bitslong: + *0b00 no floating-point instruction renamed + *0b01 one floating-point instruction renamed + *0b10 two floating-point instructions renamed + */ +#define XPM_EVENT_FLOATRENAME 0x73 + +/* + * Counts the number of Neon instructions going through the Register Rename + * stage.Instructions are still speculative in this stage. + * Two NEON instructions can be renamed in the same cycle so the event is two + * bits long: + *0b00 no NEON instruction renamed + *0b01 one NEON instruction renamed + *0b10 two NEON instructions renamed + */ +#define XPM_EVENT_NEONRENAME 0x74 + +/* + * Counts the number of cycles where the processor is stalled because PLD slots + * are all full + */ +#define XPM_EVENT_PLDSTALL 0x80 + +/* + * Counts the number of cycles when the processor is stalled and the data side + * is stalled too because it is full and executing writes to the external + * memory + */ +#define XPM_EVENT_WRITESTALL 0x81 + +/* + * Counts the number of stall cycles due to main TLB misses on requests issued + * by the instruction side + */ +#define XPM_EVENT_INSTRTLBSTALL 0x82 + +/* + * Counts the number of stall cycles due to main TLB misses on requests issued + * by the data side + */ +#define XPM_EVENT_DATATLBSTALL 0x83 + +/* + * Counts the number of stall cycles due to micro TLB misses on the instruction + * side. This event does not include main TLB miss stall cycles that are already + * counted in the corresponding main TLB event + */ +#define XPM_EVENT_INSTR_uTLBSTALL 0x84 + +/* + * Counts the number of stall cycles due to micro TLB misses on the data side. + * This event does not include main TLB miss stall cycles that are already + * counted in the corresponding main TLB event + */ +#define XPM_EVENT_DATA_uTLBSTALL 0x85 + +/* + * Counts the number of stall cycles because of the execution of a DMB memory + * barrier. This includes all DMB instructions being executed, even + * speculatively + */ +#define XPM_EVENT_DMB_STALL 0x86 + +/* + * Counts the number of cycles during which the integer core clock is enabled + */ +#define XPM_EVENT_INT_CLKEN 0x8A + +/* + * Counts the number of cycles during which the Data Engine clock is enabled + */ +#define XPM_EVENT_DE_CLKEN 0x8B + +/* + * Counts the number of ISB instructions architecturally executed + */ +#define XPM_EVENT_INSTRISB 0x90 + +/* + * Counts the number of DSB instructions architecturally executed + */ +#define XPM_EVENT_INSTRDSB 0x91 + +/* + * Counts the number of DMB instructions speculatively executed + */ +#define XPM_EVENT_INSTRDMB 0x92 + +/* + * Counts the number of external interrupts executed by the processor + */ +#define XPM_EVENT_EXTINT 0x93 + +/* + * PLE cache line request completed + */ +#define XPM_EVENT_PLE_LRC 0xA0 + +/* + * PLE cache line request skipped + */ +#define XPM_EVENT_PLE_LRS 0xA1 + +/* + * PLE FIFO flush + */ +#define XPM_EVENT_PLE_FLUSH 0xA2 + +/* + * PLE request complete + */ +#define XPM_EVENT_PLE_CMPL 0xA3 + +/* + * PLE FIFO overflow + */ +#define XPM_EVENT_PLE_OVFL 0xA4 + +/* + * PLE request programmed + */ +#define XPM_EVENT_PLE_PROG 0xA5 + +/* + * The following constants define the configurations for Cortex-A9 Performance + * Monitor Events. Each configuration configures the event counters for a set + * of events. + * ----------------------------------------------- + * Config PmCtr0... PmCtr5 + * ----------------------------------------------- + * XPM_CNTRCFG1 { XPM_EVENT_SOFTINCR, + * XPM_EVENT_INSRFETCH_CACHEREFILL, + * XPM_EVENT_INSTRFECT_TLBREFILL, + * XPM_EVENT_DATA_CACHEREFILL, + * XPM_EVENT_DATA_CACHEACCESS, + * XPM_EVENT_DATA_TLBREFILL } + * + * XPM_CNTRCFG2 { XPM_EVENT_DATA_READS, + * XPM_EVENT_DATA_WRITE, + * XPM_EVENT_EXCEPTION, + * XPM_EVENT_EXCEPRETURN, + * XPM_EVENT_CHANGECONTEXT, + * XPM_EVENT_SW_CHANGEPC } + * + * XPM_CNTRCFG3 { XPM_EVENT_IMMEDBRANCH, + * XPM_EVENT_UNALIGNEDACCESS, + * XPM_EVENT_BRANCHMISS, + * XPM_EVENT_CLOCKCYCLES, + * XPM_EVENT_BRANCHPREDICT, + * XPM_EVENT_JAVABYTECODE } + * + * XPM_CNTRCFG4 { XPM_EVENT_SWJAVABYTECODE, + * XPM_EVENT_JAVABACKBRANCH, + * XPM_EVENT_COHERLINEMISS, + * XPM_EVENT_COHERLINEHIT, + * XPM_EVENT_INSTRSTALL, + * XPM_EVENT_DATASTALL } + * + * XPM_CNTRCFG5 { XPM_EVENT_MAINTLBSTALL, + * XPM_EVENT_STREXPASS, + * XPM_EVENT_STREXFAIL, + * XPM_EVENT_DATAEVICT, + * XPM_EVENT_NODISPATCH, + * XPM_EVENT_ISSUEEMPTY } + * + * XPM_CNTRCFG6 { XPM_EVENT_INSTRRENAME, + * XPM_EVENT_PREDICTFUNCRET, + * XPM_EVENT_MAINEXEC, + * XPM_EVENT_SECEXEC, + * XPM_EVENT_LDRSTR, + * XPM_EVENT_FLOATRENAME } + * + * XPM_CNTRCFG7 { XPM_EVENT_NEONRENAME, + * XPM_EVENT_PLDSTALL, + * XPM_EVENT_WRITESTALL, + * XPM_EVENT_INSTRTLBSTALL, + * XPM_EVENT_DATATLBSTALL, + * XPM_EVENT_INSTR_uTLBSTALL } + * + * XPM_CNTRCFG8 { XPM_EVENT_DATA_uTLBSTALL, + * XPM_EVENT_DMB_STALL, + * XPM_EVENT_INT_CLKEN, + * XPM_EVENT_DE_CLKEN, + * XPM_EVENT_INSTRISB, + * XPM_EVENT_INSTRDSB } + * + * XPM_CNTRCFG9 { XPM_EVENT_INSTRDMB, + * XPM_EVENT_EXTINT, + * XPM_EVENT_PLE_LRC, + * XPM_EVENT_PLE_LRS, + * XPM_EVENT_PLE_FLUSH, + * XPM_EVENT_PLE_CMPL } + * + * XPM_CNTRCFG10 { XPM_EVENT_PLE_OVFL, + * XPM_EVENT_PLE_PROG, + * XPM_EVENT_PLE_LRC, + * XPM_EVENT_PLE_LRS, + * XPM_EVENT_PLE_FLUSH, + * XPM_EVENT_PLE_CMPL } + * + * XPM_CNTRCFG11 { XPM_EVENT_DATASTALL, + * XPM_EVENT_INSRFETCH_CACHEREFILL, + * XPM_EVENT_INSTRFECT_TLBREFILL, + * XPM_EVENT_DATA_CACHEREFILL, + * XPM_EVENT_DATA_CACHEACCESS, + * XPM_EVENT_DATA_TLBREFILL } + */ +#define XPM_CNTRCFG1 0 +#define XPM_CNTRCFG2 1 +#define XPM_CNTRCFG3 2 +#define XPM_CNTRCFG4 3 +#define XPM_CNTRCFG5 4 +#define XPM_CNTRCFG6 5 +#define XPM_CNTRCFG7 6 +#define XPM_CNTRCFG8 7 +#define XPM_CNTRCFG9 8 +#define XPM_CNTRCFG10 9 +#define XPM_CNTRCFG11 10 + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +/* Interface fuctions to access perfromance counters from abstraction layer */ +void Xpm_SetEvents(int PmcrCfg); +void Xpm_GetEventCounters(u32 *PmCtrValue); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xpseudo_asm.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xpseudo_asm.h new file mode 100644 index 000000000..22a168b72 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xpseudo_asm.h @@ -0,0 +1,62 @@ +/******************************************************************************* +* +* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +*******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xpseudo_asm.h +* +* This header file contains macros for using inline assembler code. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  10/18/09 First release
+* 3.04a sdm  01/02/12 Remove redundant dsb in mcr instruction.
+*
+* +******************************************************************************/ +#include "xreg_cortexa9.h" +#ifdef __GNUC__ + #include "xpseudo_asm_gcc.h" +#else + #include "xpseudo_asm_rvct.h" +#endif diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h new file mode 100644 index 000000000..52fac3b34 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h @@ -0,0 +1,183 @@ +/****************************************************************************** +* +* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xpseudo_asm_gcc.h +* +* This header file contains macros for using inline assembler code. It is +* written specifically for the GNU compiler. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  10/28/09 First release
+*
+* +******************************************************************************/ + +#ifndef XPSEUDO_ASM_GCC_H /* prevent circular inclusions */ +#define XPSEUDO_ASM_GCC_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/* necessary for pre-processor */ +#define stringify(s) tostring(s) +#define tostring(s) #s + +/* pseudo assembler instructions */ +#define mfcpsr() ({unsigned int rval; \ + __asm__ __volatile__(\ + "mrs %0, cpsr\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) + +#define mtcpsr(v) __asm__ __volatile__(\ + "msr cpsr,%0\n"\ + : : "r" (v)\ + ) + +#define cpsiei() __asm__ __volatile__("cpsie i\n") +#define cpsidi() __asm__ __volatile__("cpsid i\n") + +#define cpsief() __asm__ __volatile__("cpsie f\n") +#define cpsidf() __asm__ __volatile__("cpsid f\n") + + + +#define mtgpr(rn, v) __asm__ __volatile__(\ + "mov r" stringify(rn) ", %0 \n"\ + : : "r" (v)\ + ) + +#define mfgpr(rn) ({unsigned int rval; \ + __asm__ __volatile__(\ + "mov %0,r" stringify(rn) "\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) + +/* memory synchronization operations */ + +/* Instruction Synchronization Barrier */ +#define isb() __asm__ __volatile__ ("isb" : : : "memory") + +/* Data Synchronization Barrier */ +#define dsb() __asm__ __volatile__ ("dsb" : : : "memory") + +/* Data Memory Barrier */ +#define dmb() __asm__ __volatile__ ("dmb" : : : "memory") + + +/* Memory Operations */ +#define ldr(adr) ({unsigned long rval; \ + __asm__ __volatile__(\ + "ldr %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) + +#define ldrb(adr) ({unsigned char rval; \ + __asm__ __volatile__(\ + "ldrb %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) + +#define str(adr, val) __asm__ __volatile__(\ + "str %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) + +#define strb(adr, val) __asm__ __volatile__(\ + "strb %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) + +/* Count leading zeroes (clz) */ +#define clz(arg) ({unsigned char rval; \ + __asm__ __volatile__(\ + "clz %0,%1"\ + : "=r" (rval) : "r" (arg)\ + );\ + rval;\ + }) + +/* CP15 operations */ +#define mtcp(rn, v) __asm__ __volatile__(\ + "mcr " rn "\n"\ + : : "r" (v)\ + ); + +#define mfcp(rn) ({unsigned int rval; \ + __asm__ __volatile__(\ + "mrc " rn "\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XPSEUDO_ASM_GCC_H */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xqspips.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xqspips.h new file mode 100644 index 000000000..6a9e7f8b1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xqspips.h @@ -0,0 +1,790 @@ +/****************************************************************************** +* +* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xqspips.h +* +* This file contains the implementation of the XQspiPs driver. It supports only +* master mode. User documentation for the driver functions is contained in this +* file in the form of comment blocks at the front of each function. +* +* A QSPI device connects to an QSPI bus through a 4-wire serial interface. +* The QSPI bus is a full-duplex, synchronous bus that facilitates communication +* between one master and one slave. The device is always full-duplex, +* which means that for every byte sent, one is received, and vice-versa. +* The master controls the clock, so it can regulate when it wants to +* send or receive data. The slave is under control of the master, it must +* respond quickly since it has no control of the clock and must send/receive +* data as fast or as slow as the master does. +* +* Linear Mode +* The Linear Quad-SPI Controller extends the existing Quad-SPI ControllerÂ’s +* functionality by adding a linear addressing scheme that allows the SPI flash +* memory subsystem to behave like a typical ROM device. The new feature hides +* the normal SPI protocol from a master reading from the SPI flash memory. The +* feature improves both the user friendliness and the overall read memory +* throughput over that of the current Quad-SPI Controller by lessening the +* amount of software overheads required and by the use of the faster AXI +* interface. +* +* Initialization & Configuration +* +* The XQspiPs_Config structure is used by the driver to configure itself. This +* configuration structure is typically created by the tool-chain based on HW +* build properties. +* +* To support multiple runtime loading and initialization strategies employed by +* various operating systems, the driver instance can be initialized in the +* following way: +* - XQspiPs_LookupConfig(DeviceId) - Use the device identifier to find +* static configuration structure defined in xqspips_g.c. This is setup +* by the tools. For some operating systems the config structure will be +* initialized by the software and this call is not needed. +* - XQspiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a +* configuration structure provided by the caller. If running in a system +* with address translation, the provided virtual memory base address +* replaces the physical address present in the configuration structure. +* +* Multiple Masters +* +* More than one master can exist, but arbitration is the responsibility of +* the higher layer software. The device driver does not perform any type of +* arbitration. +* +* Modes of Operation +* +* There are four modes to perform a data transfer and the selection of a mode +* is based on Chip Select(CS) and Start. These two options individually, can +* be controlled either by software(Manual) or hardware(Auto). +* - Auto CS: Chip select is automatically asserted as soon as the first word +* is written into the TXFIFO and de asserted when the TXFIFO becomes +* empty +* - Manual CS: Software must assert and de assert CS. +* - Auto Start: Data transmission starts as soon as there is data in the +* TXFIFO and stalls when the TXFIFO is empty +* - Manual Start: Software must start data transmission at the beginning of +* the transaction or whenever the TXFIFO has become empty +* +* The preferred combination is Manual CS and Auto Start. +* In this combination, the software asserts CS before loading any data into +* TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it +* out until TXFIFO becomes empty. The software reads the RXFIFO whenever the +* data is available. If no further data, software disables CS. +* +* Risks/challenges of other combinations: +* - Manual CS and Manual Start: Manual Start bit should be set after each +* TXFIFO write otherwise there could be a race condition where the TXFIFO +* becomes empty before the new word is written. In that case the +* transmission stops. +* - Auto CS with Manual or Auto Start: It is very difficult for software to +* keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is de asserted. +* This results in a single transaction to be split into multiple pieces each +* with its own chip select. This will result in garbage data to be sent. +* +* Interrupts +* +* The user must connect the interrupt handler of the driver, +* XQspiPs_InterruptHandler, to an interrupt system such that it will be +* called when an interrupt occurs. This function does not save and restore +* the processor context such that the user must provide this processing. +* +* The driver handles the following interrupts: +* - Data Transmit Register/FIFO Underflow +* - Data Receive Register/FIFO Not Empty +* - Data Transmit Register/FIFO Overwater +* - Data Receive Register/FIFO Overrun +* +* The Data Transmit Register/FIFO Overwater interrupt -- indicates that the +* QSPI device has transmitted the data available to transmit, and now its data +* register and FIFO is ready to accept more data. The driver uses this +* interrupt to indicate progress while sending data. The driver may have +* more data to send, in which case the data transmit register and FIFO is +* filled for subsequent transmission. When this interrupt arrives and all +* the data has been sent, the driver invokes the status callback with a +* value of XST_SPI_TRANSFER_DONE to inform the upper layer software that +* all data has been sent. +* +* The Data Transmit Register/FIFO Underflow interrupt -- indicates that, +* as slave, the QSPI device was required to transmit but there was no data +* available to transmit in the transmit register (or FIFO). This may not +* be an error if the master is not expecting data. But in the case where +* the master is expecting data, this serves as a notification of such a +* condition. The driver reports this condition to the upper layer +* software through the status handler. +* +* The Data Receive Register/FIFO Overrun interrupt -- indicates that the QSPI +* device received data and subsequently dropped the data because the data +* receive register and FIFO was full. The driver reports this condition to the +* upper layer software through the status handler. This likely indicates a +* problem with the higher layer protocol, or a problem with the slave +* performance. +* +* +* Polled Operation +* +* Transfer in polled mode is supported through a separate interface function +* XQspiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode, +* this function blocks until all data has been sent/received. +* +* Device Busy +* +* Some operations are disallowed when the device is busy. The driver tracks +* whether a device is busy. The device is considered busy when a data transfer +* request is outstanding, and is considered not busy only when that transfer +* completes (or is aborted with a mode fault error). +* +* Device Configuration +* +* The device can be configured in various ways during the FPGA implementation +* process. Configuration parameters are stored in the xqspips_g.c file or +* passed in via XQspiPs_CfgInitialize(). A table is defined where each entry +* contains configuration information for an QSPI device, including the base +* address for the device. +* +* RTOS Independence +* +* This driver is intended to be RTOS and processor independent. It works with +* physical addresses only. Any needs for dynamic memory management, threads or +* thread mutual exclusion, virtual memory, or cache control must be satisfied +* by the layer above this driver. +* +* NOTE: This driver was always tested with endianess set to little-endian. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a sdm 11/25/10 First release, based on the PS SPI driver...
+* 1.01a sdm 11/22/11 Added TCL file for generating QSPI parameters
+*		     in xparameters.h
+* 2.00a kka 07/25/12 Added a few register defines for CR 670297
+* 		     Removed code related to mode fault for CR 671468
+*		     The XQspiPs_SetSlaveSelect has been modified to remove
+*		     the argument of the slave select as the QSPI controller
+*		     only supports one slave.
+* 		     XQspiPs_GetSlaveSelect API has been removed
+* 		     Added a flag ShiftReadData to the instance structure
+*.		     and is used in the XQspiPs_GetReadData API.
+*		     The ShiftReadData Flag indicates whether the data
+*		     read from the Rx FIFO needs to be shifted
+*		     in cases where the data is less than 4  bytes
+* 		     Removed the selection for the following options:
+*		     Master mode (XQSPIPS_MASTER_OPTION) and
+*		     Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
+*		     as the QSPI driver supports the Master mode
+*		     and Flash Interface mode and doesnot support
+*		     Slave mode or the legacy mode.
+*		     Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
+*		     APIs so that the last argument (IsInst) specifying whether
+*		     it is instruction or data has been removed. The first byte
+*		     in the SendBufPtr argument of these APIs specify the
+*		     instruction to be sent to the Flash Device.
+*		     This version of the driver fixes CRs 670197/663787/
+*		     670297/671468.
+* 		     Added the option for setting the Holdb_dr bit in the
+*		     configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
+*		     is the option to be used for setting this bit in the
+*		     configuration register.
+*		     The XQspiPs_PolledTransfer function has been updated
+*		     to fill the data to fifo depth.
+* 2.01a sg  02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
+*		     Added macros for Set/Get Rx Watermark. Changed QSPI
+*		     Enable/Disable macro argument from BaseAddress to
+*		     Instance Pointer. Added DelayNss argument to SetDelays
+*		     and GetDelays API's.
+*		     Created macros XQspiPs_IsManualStart and
+*		     XQspiPs_IsManualChipSelect.
+*		     Changed QSPI transfer logic for polled and interrupt
+*		     modes to be based on filled tx fifo count and receive
+*		     based on it. RXNEMPTY interrupt is not used.
+*		     Added assertions to XQspiPs_LqspiRead function.
+*		     SetDelays and GetDelays API's include DelayNss parameter.
+*		     Added defines for DelayNss,Rx Watermark,Interrupts
+*		     which need write to clear. Removed Read zeros mask from
+*		     LQSPI Config register. Renamed Fixed burst error to
+*		     data FSM error in  LQSPI Status register.
+*
+* 2.02a hk  05/07/13 Added ConnectionMode to config structure.
+*			 Corresponds to C_QSPI_MODE - 0:Single, 1:Stacked, 2:Parallel
+*			 Added enable and disable to the XQspiPs_LqspiRead() function
+*			 Removed XQspi_Reset() in Set_Options() function when
+*			 LQSPI_MODE_OPTION is set.
+*            Added instructions for bank selection, die erase and
+*            flag status register to the flash instruction table
+*            Handling for instructions not in flash instruction
+*			 table added. Checking for Tx FIFO empty when switching from
+*			 TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
+*            byte count 3 (spansion), instruction size and TXD register
+*			 changed accordingly. CR# 712502 and 703869.
+*            Added prefix to constant definitions for ConnectionMode
+*            Added (#ifdef linear base address) in the Linear read function.
+*            Changed  XPAR_XQSPIPS_0_LINEAR_BASEADDR to
+*            XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
+*            XQspiPs_LqspiRead function. Fix for CR#718141.
+*
+* 2.03a hk  09/17/13 Modified polled and interrupt transfers to make use of
+*                    thresholds. This is to improve performance.
+*                    Added API's for QSPI reset and
+*                    linear mode initialization for boot.
+*                    Added RX and TX threshold reset to one in XQspiPs_Abort.
+*                    Added RX threshold reset(1) after transfer in polled and
+*                    interrupt transfers. Made changes to make sure threshold
+*                    change is done only when no transfer is in progress.
+*                    Updated linear init API for parallel and stacked modes.
+*                    CR#737760.
+*
+*
+* +******************************************************************************/ +#ifndef XQSPIPS_H /* prevent circular inclusions */ +#define XQSPIPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xqspips_hw.h" +#include + +/************************** Constant Definitions *****************************/ + +/** @name Configuration options + * + * The following options are supported to enable/disable certain features of + * an QSPI device. Each of the options is a bit mask, so more than one may be + * specified. + * + * + * The Active Low Clock option configures the device's clock polarity. + * Setting this option means the clock is active low and the SCK signal idles + * high. By default, the clock is active high and SCK idles low. + * + * The Clock Phase option configures the QSPI device for one of two + * transfer formats. A clock phase of 0, the default, means data is valid on + * the first SCK edge (rising or falling) after the slave select (SS) signal + * has been asserted. A clock phase of 1 means data is valid on the second SCK + * edge (rising or falling) after SS has been asserted. + * + * + * The QSPI Force Slave Select option is used to enable manual control of + * the slave select signal. + * 0: The SPI_SS signal is controlled by the QSPI controller during + * transfers. (Default) + * 1: The SPI_SS signal is forced active (driven low) regardless of any + * transfers in progress. + * + * NOTE: The driver will handle setting and clearing the Slave Select when + * the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the + * QSPI clock to be set to a faster speed. If the QSPI clock is too fast, the + * processor cannot empty and refill the FIFOs before the TX FIFO is empty + * When the QSPI hardware is controlling the Slave Select signals, this + * will cause slave to be de-selected and terminate the transfer. + * + * The Manual Start option is used to enable manual control of + * the Start command to perform data transfer. + * 0: The Start command is controlled by the QSPI controller during + * transfers(Default). Data transmission starts as soon as there is data in + * the TXFIFO and stalls when the TXFIFO is empty + * 1: The Start command must be issued by software to perform data transfer. + * Bit 15 of Configuration register is used to issue Start command. This bit + * must be set whenever TXFIFO is filled with new data. + * + * NOTE: The driver will set the Manual Start Enable bit in Configuration + * Register, if Manual Start option is selected. Software will issue + * Manual Start command whenever TXFIFO is filled with data. When there is + * no further data, driver will clear the Manual Start Enable bit. + * + * @{ + */ +#define XQSPIPS_CLK_ACTIVE_LOW_OPTION 0x2 /**< Active Low Clock option */ +#define XQSPIPS_CLK_PHASE_1_OPTION 0x4 /**< Clock Phase one option */ +#define XQSPIPS_FORCE_SSELECT_OPTION 0x10 /**< Force Slave Select */ +#define XQSPIPS_MANUAL_START_OPTION 0x20 /**< Manual Start enable */ +#define XQSPIPS_LQSPI_MODE_OPTION 0x80 /**< Linear QPSI mode */ +#define XQSPIPS_HOLD_B_DRIVE_OPTION 0x100 /**< Drive HOLD_B Pin */ +/*@}*/ + + +/** @name QSPI Clock Prescaler options + * The QSPI Clock Prescaler Configuration bits are used to program master mode + * bit rate. The bit rate can be programmed in divide-by-two decrements from + * pclk/2 to pclk/256. + * + * @{ + */ +#define XQSPIPS_CLK_PRESCALE_2 0x00 /**< PCLK/2 Prescaler */ +#define XQSPIPS_CLK_PRESCALE_4 0x01 /**< PCLK/4 Prescaler */ +#define XQSPIPS_CLK_PRESCALE_8 0x02 /**< PCLK/8 Prescaler */ +#define XQSPIPS_CLK_PRESCALE_16 0x03 /**< PCLK/16 Prescaler */ +#define XQSPIPS_CLK_PRESCALE_32 0x04 /**< PCLK/32 Prescaler */ +#define XQSPIPS_CLK_PRESCALE_64 0x05 /**< PCLK/64 Prescaler */ +#define XQSPIPS_CLK_PRESCALE_128 0x06 /**< PCLK/128 Prescaler */ +#define XQSPIPS_CLK_PRESCALE_256 0x07 /**< PCLK/256 Prescaler */ + +/*@}*/ + + +/** @name Callback events + * + * These constants specify the handler events that are passed to + * a handler from the driver. These constants are not bit masks such that + * only one will be passed at a time to the handler. + * + * @{ + */ +#define XQSPIPS_EVENT_TRANSFER_DONE 2 /**< Transfer done */ +#define XQSPIPS_EVENT_TRANSMIT_UNDERRUN 3 /**< TX FIFO empty */ +#define XQSPIPS_EVENT_RECEIVE_OVERRUN 4 /**< Receive data loss because + RX FIFO full */ +/*@}*/ + +/** @name Flash commands + * + * The following constants define most of the commands supported by flash + * devices. Users can add more commands supported by the flash devices + * + * @{ + */ +#define XQSPIPS_FLASH_OPCODE_WRSR 0x01 /* Write status register */ +#define XQSPIPS_FLASH_OPCODE_PP 0x02 /* Page program */ +#define XQSPIPS_FLASH_OPCODE_NORM_READ 0x03 /* Normal read data bytes */ +#define XQSPIPS_FLASH_OPCODE_WRDS 0x04 /* Write disable */ +#define XQSPIPS_FLASH_OPCODE_RDSR1 0x05 /* Read status register 1 */ +#define XQSPIPS_FLASH_OPCODE_WREN 0x06 /* Write enable */ +#define XQSPIPS_FLASH_OPCODE_FAST_READ 0x0B /* Fast read data bytes */ +#define XQSPIPS_FLASH_OPCODE_BE_4K 0x20 /* Erase 4KiB block */ +#define XQSPIPS_FLASH_OPCODE_RDSR2 0x35 /* Read status register 2 */ +#define XQSPIPS_FLASH_OPCODE_DUAL_READ 0x3B /* Dual read data bytes */ +#define XQSPIPS_FLASH_OPCODE_BE_32K 0x52 /* Erase 32KiB block */ +#define XQSPIPS_FLASH_OPCODE_QUAD_READ 0x6B /* Quad read data bytes */ +#define XQSPIPS_FLASH_OPCODE_ERASE_SUS 0x75 /* Erase suspend */ +#define XQSPIPS_FLASH_OPCODE_ERASE_RES 0x7A /* Erase resume */ +#define XQSPIPS_FLASH_OPCODE_RDID 0x9F /* Read JEDEC ID */ +#define XQSPIPS_FLASH_OPCODE_BE 0xC7 /* Erase whole flash block */ +#define XQSPIPS_FLASH_OPCODE_SE 0xD8 /* Sector erase (usually 64KB)*/ +#define XQSPIPS_FLASH_OPCODE_DUAL_IO_READ 0xBB /* Read data using Dual I/O */ +#define XQSPIPS_FLASH_OPCODE_QUAD_IO_READ 0xEB /* Read data using Quad I/O */ +#define XQSPIPS_FLASH_OPCODE_BRWR 0x17 /* Bank Register Write */ +#define XQSPIPS_FLASH_OPCODE_BRRD 0x16 /* Bank Register Read */ +/* Extende Address Register Write - Micron's equivalent of Bank Register */ +#define XQSPIPS_FLASH_OPCODE_EARWR 0xC5 +/* Extende Address Register Read - Micron's equivalent of Bank Register */ +#define XQSPIPS_FLASH_OPCODE_EARRD 0xC8 +#define XQSPIPS_FLASH_OPCODE_DIE_ERASE 0xC4 +#define XQSPIPS_FLASH_OPCODE_READ_FLAG_SR 0x70 +#define XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR 0x50 +#define XQSPIPS_FLASH_OPCODE_READ_LOCK_REG 0xE8 /* Lock register Read */ +#define XQSPIPS_FLASH_OPCODE_WRITE_LOCK_REG 0xE5 /* Lock Register Write */ + +/*@}*/ + +/** @name Instruction size + * + * The following constants define numbers 1 to 4. + * Used to identify whether TXD0,1,2 or 3 is to be used. + * + * @{ + */ +#define XQSPIPS_SIZE_ONE 1 +#define XQSPIPS_SIZE_TWO 2 +#define XQSPIPS_SIZE_THREE 3 +#define XQSPIPS_SIZE_FOUR 4 + +/*@}*/ + +/** @name ConnectionMode + * + * The following constants are the possible values of ConnectionMode in + * Config structure. + * + * @{ + */ +#define XQSPIPS_CONNECTION_MODE_SINGLE 0 +#define XQSPIPS_CONNECTION_MODE_STACKED 1 +#define XQSPIPS_CONNECTION_MODE_PARALLEL 2 + +/*@}*/ + +/** @name FIFO threshold value + * + * This is the Rx FIFO threshold (in words) that was found to be most + * optimal in terms of performance + * + * @{ + */ +#define XQSPIPS_RXFIFO_THRESHOLD_OPT 32 + +/*@}*/ + +/**************************** Type Definitions *******************************/ +/** + * The handler data type allows the user to define a callback function to + * handle the asynchronous processing for the QSPI device. The application + * using this driver is expected to define a handler of this type to support + * interrupt driven mode. The handler executes in an interrupt context, so + * only minimal processing should be performed. + * + * @param CallBackRef is the callback reference passed in by the upper + * layer when setting the callback functions, and passed back to + * the upper layer when the callback is invoked. Its type is + * not important to the driver, so it is a void pointer. + * @param StatusEvent holds one or more status events that have occurred. + * See the XQspiPs_SetStatusHandler() for details on the status + * events that can be passed in the callback. + * @param ByteCount indicates how many bytes of data were successfully + * transferred. This may be less than the number of bytes + * requested if the status event indicates an error. + */ +typedef void (*XQspiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent, + unsigned ByteCount); + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Base address of the device */ + u32 InputClockHz; /**< Input clock frequency */ + u8 ConnectionMode; /**< Single, Stacked and Parallel mode */ +} XQspiPs_Config; + +/** + * The XQspiPs driver instance data. The user is required to allocate a + * variable of this type for every QSPI device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XQspiPs_Config Config; /**< Configuration structure */ + u32 IsReady; /**< Device is initialized and ready */ + + u8 *SendBufferPtr; /**< Buffer to send (state) */ + u8 *RecvBufferPtr; /**< Buffer to receive (state) */ + int RequestedBytes; /**< Number of bytes to transfer (state) */ + int RemainingBytes; /**< Number of bytes left to transfer(state) */ + u32 IsBusy; /**< A transfer is in progress (state) */ + XQspiPs_StatusHandler StatusHandler; + void *StatusRef; /**< Callback reference for status handler */ + u32 ShiftReadData; /**< Flag to indicate whether the data + * read from the Rx FIFO needs to be shifted + * in cases where the data is less than 4 + * bytes + */ +} XQspiPs; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/* +* +* Check in OptionsTable if Manual Start Option is enabled or disabled. +* +* @param InstancePtr is a pointer to the XQspiPs instance. +* +* @return +* - TRUE if option is set +* - FALSE if option is not set +* +* @note C-Style signature: +* u8 XQspiPs_IsManualStart(XQspiPs *InstancePtr); +* +*****************************************************************************/ +#define XQspiPs_IsManualStart(InstancePtr) \ + ((XQspiPs_GetOptions(InstancePtr) & \ + XQSPIPS_MANUAL_START_OPTION) ? TRUE : FALSE) + +/****************************************************************************/ +/* +* +* Check in OptionsTable if Manual Chip Select Option is enabled or disabled. +* +* @param InstancePtr is a pointer to the XSpiPs instance. +* +* @return +* - TRUE if option is set +* - FALSE if option is not set +* +* @note C-Style signature: +* u8 XQspiPs_IsManualChipSelect(XQspiPs *InstancePtr); +* +*****************************************************************************/ +#define XQspiPs_IsManualChipSelect(InstancePtr) \ + ((XQspiPs_GetOptions(InstancePtr) & \ + XQSPIPS_FORCE_SSELECT_OPTION) ? TRUE : FALSE) + +/****************************************************************************/ +/** +* +* Set the contents of the slave idle count register. +* +* @param InstancePtr is a pointer to the XQspiPs instance. +* @param RegisterValue is the value to be written, valid values are +* 0-255. +* +* @return None +* +* @note +* C-Style signature: +* void XQspiPs_SetSlaveIdle(XQspiPs *InstancePtr, u32 RegisterValue) +* +*****************************************************************************/ +#define XQspiPs_SetSlaveIdle(InstancePtr, RegisterValue) \ + XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \ + XQSPIPS_SICR_OFFSET, (RegisterValue)) + +/****************************************************************************/ +/** +* +* Get the contents of the slave idle count register. Use the XQSPIPS_SICR_* +* constants defined in xqspips_hw.h to interpret the bit-mask returned. +* +* @param InstancePtr is a pointer to the XQspiPs instance. +* +* @return An 8-bit value representing Slave Idle Count. +* +* @note C-Style signature: +* u32 XQspiPs_GetSlaveIdle(XQspiPs *InstancePtr) +* +*****************************************************************************/ +#define XQspiPs_GetSlaveIdle(InstancePtr) \ + XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + \ + XQSPIPS_SICR_OFFSET) + +/****************************************************************************/ +/** +* +* Set the contents of the transmit FIFO watermark register. +* +* @param InstancePtr is a pointer to the XQspiPs instance. +* @param RegisterValue is the value to be written, valid values are 1-63. +* +* @return None. +* +* @note +* C-Style signature: +* void XQspiPs_SetTXWatermark(XQspiPs *InstancePtr, u32 RegisterValue) +* +*****************************************************************************/ +#define XQspiPs_SetTXWatermark(InstancePtr, RegisterValue) \ + XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \ + XQSPIPS_TXWR_OFFSET, (RegisterValue)) + +/****************************************************************************/ +/** +* +* Get the contents of the transmit FIFO watermark register. +* Valid values are in the range 1-63. +* +* @param InstancePtr is a pointer to the XQspiPs instance. +* +* @return A 6-bit value representing Tx Watermark level. +* +* @note C-Style signature: +* u32 XQspiPs_GetTXWatermark(XQspiPs *InstancePtr) +* +*****************************************************************************/ +#define XQspiPs_GetTXWatermark(InstancePtr) \ + XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET) + +/****************************************************************************/ +/** +* +* Set the contents of the receive FIFO watermark register. +* +* @param InstancePtr is a pointer to the XQspiPs instance. +* @param RegisterValue is the value to be written, valid values are 1-63. +* +* @return None. +* +* @note +* C-Style signature: +* void XQspiPs_SetRXWatermark(XQspiPs *InstancePtr, u32 RegisterValue) +* +*****************************************************************************/ +#define XQspiPs_SetRXWatermark(InstancePtr, RegisterValue) \ + XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \ + XQSPIPS_RXWR_OFFSET, (RegisterValue)) + +/****************************************************************************/ +/** +* +* Get the contents of the receive FIFO watermark register. +* Valid values are in the range 1-63. +* +* @param InstancePtr is a pointer to the XQspiPs instance. +* +* @return A 6-bit value representing Rx Watermark level. +* +* @note C-Style signature: +* u32 XQspiPs_GetRXWatermark(XQspiPs *InstancePtr) +* +*****************************************************************************/ +#define XQspiPs_GetRXWatermark(InstancePtr) \ + XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET) + +/****************************************************************************/ +/** +* +* Enable the device and uninhibit master transactions. +* +* @param InstancePtr is a pointer to the XQspiPs instance. +* +* @return None. +* +* @note C-Style signature: +* void XQspiPs_Enable(XQspiPs *InstancePtr) +* +*****************************************************************************/ +#define XQspiPs_Enable(InstancePtr) \ + XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \ + XQSPIPS_ER_ENABLE_MASK) + +/****************************************************************************/ +/** +* +* Disable the device. +* +* @param InstancePtr is a pointer to the XQspiPs instance. +* +* @return None. +* +* @note C-Style signature: +* void XQspiPs_Disable(XQspiPs *InstancePtr) +* +*****************************************************************************/ +#define XQspiPs_Disable(InstancePtr) \ + XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0) + +/****************************************************************************/ +/** +* +* Set the contents of the Linear QSPI Configuration register. +* +* @param InstancePtr is a pointer to the XQspiPs instance. +* @param RegisterValue is the value to be written to the Linear QSPI +* configuration register. +* +* @return None. +* +* @note +* C-Style signature: +* void XQspiPs_SetLqspiConfigReg(XQspiPs *InstancePtr, +* u32 RegisterValue) +* +*****************************************************************************/ +#define XQspiPs_SetLqspiConfigReg(InstancePtr, RegisterValue) \ + XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \ + XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue)) + +/****************************************************************************/ +/** +* +* Get the contents of the Linear QSPI Configuration register. +* +* @param InstancePtr is a pointer to the XQspiPs instance. +* +* @return A 32-bit value representing the contents of the LQSPI Config +* register. +* +* @note C-Style signature: +* u32 XQspiPs_GetLqspiConfigReg(u32 *InstancePtr) +* +*****************************************************************************/ +#define XQspiPs_GetLqspiConfigReg(InstancePtr) \ + XQspiPs_In32((InstancePtr->Config.BaseAddress) + \ + XQSPIPS_LQSPI_CR_OFFSET) + +/************************** Function Prototypes ******************************/ + +/* + * Initialization function, implemented in xqspips_sinit.c + */ +XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId); + +/* + * Functions implemented in xqspips.c + */ +int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config * Config, + u32 EffectiveAddr); +void XQspiPs_Reset(XQspiPs *InstancePtr); +void XQspiPs_Abort(XQspiPs *InstancePtr); + +int XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr, + unsigned ByteCount); +int XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr, + u8 *RecvBufPtr, unsigned ByteCount); +int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr, + u32 Address, unsigned ByteCount); + +int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr); + +void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef, + XQspiPs_StatusHandler FuncPtr); +void XQspiPs_InterruptHandler(void *InstancePtr); + +/* + * Functions for selftest, in xqspips_selftest.c + */ +int XQspiPs_SelfTest(XQspiPs *InstancePtr); + +/* + * Functions for options, in xqspips_options.c + */ +int XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options); +u32 XQspiPs_GetOptions(XQspiPs *InstancePtr); + +int XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler); +u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr); + +int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn, + u8 DelayAfter, u8 DelayInit); +void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn, + u8 *DelayAfter, u8 *DelayInit); +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xqspips_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xqspips_hw.h new file mode 100644 index 000000000..8e77c75ab --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xqspips_hw.h @@ -0,0 +1,381 @@ +/****************************************************************************** +* +* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xqspips_hw.h +* +* This header file contains the identifiers and basic HW access driver +* functions (or macros) that can be used to access the device. Other driver +* functions are defined in xqspips.h. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00  sdm 11/25/10 First release
+* 2.00a ka  07/25/12 Added a few register defines for CR 670297
+*		     and removed some defines of reserved fields for
+*		     CR 671468
+*		     Added define XQSPIPS_CR_HOLD_B_MASK for Holdb_dr
+*		     bit in Configuration register.
+* 2.01a sg  02/03/13 Added defines for DelayNss,Rx Watermark,Interrupts
+*		     which need write to clear. Removed Read zeros mask from
+*		     LQSPI Config register.
+* 2.03a hk  08/22/13 Added prototypes of API's for QSPI reset and
+*                    linear mode initialization for boot. Added related
+*                    constant definitions.
+*
+*
+* +******************************************************************************/ +#ifndef XQSPIPS_HW_H /* prevent circular inclusions */ +#define XQSPIPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" +#include "xparameters.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * + * Register offsets from the base address of an QSPI device. + * @{ + */ +#define XQSPIPS_CR_OFFSET 0x00 /**< Configuration Register */ +#define XQSPIPS_SR_OFFSET 0x04 /**< Interrupt Status */ +#define XQSPIPS_IER_OFFSET 0x08 /**< Interrupt Enable */ +#define XQSPIPS_IDR_OFFSET 0x0c /**< Interrupt Disable */ +#define XQSPIPS_IMR_OFFSET 0x10 /**< Interrupt Enabled Mask */ +#define XQSPIPS_ER_OFFSET 0x14 /**< Enable/Disable Register */ +#define XQSPIPS_DR_OFFSET 0x18 /**< Delay Register */ +#define XQSPIPS_TXD_00_OFFSET 0x1C /**< Transmit 4-byte inst/data */ +#define XQSPIPS_RXD_OFFSET 0x20 /**< Data Receive Register */ +#define XQSPIPS_SICR_OFFSET 0x24 /**< Slave Idle Count */ +#define XQSPIPS_TXWR_OFFSET 0x28 /**< Transmit FIFO Watermark */ +#define XQSPIPS_RXWR_OFFSET 0x2C /**< Receive FIFO Watermark */ +#define XQSPIPS_GPIO_OFFSET 0x30 /**< GPIO Register */ +#define XQSPIPS_LPBK_DLY_ADJ_OFFSET 0x38 /**< Loopback Delay Adjust Reg */ +#define XQSPIPS_TXD_01_OFFSET 0x80 /**< Transmit 1-byte inst */ +#define XQSPIPS_TXD_10_OFFSET 0x84 /**< Transmit 2-byte inst */ +#define XQSPIPS_TXD_11_OFFSET 0x88 /**< Transmit 3-byte inst */ +#define XQSPIPS_LQSPI_CR_OFFSET 0xA0 /**< Linear QSPI config register */ +#define XQSPIPS_LQSPI_SR_OFFSET 0xA4 /**< Linear QSPI status register */ +#define XQSPIPS_MOD_ID_OFFSET 0xFC /**< Module ID register */ + +/* @} */ + +/** @name Configuration Register + * + * This register contains various control bits that + * affect the operation of the QSPI device. Read/Write. + * @{ + */ + +#define XQSPIPS_CR_IFMODE_MASK 0x80000000 /**< Flash mem interface mode */ +#define XQSPIPS_CR_ENDIAN_MASK 0x04000000 /**< Tx/Rx FIFO endianness */ +#define XQSPIPS_CR_MANSTRT_MASK 0x00010000 /**< Manual Transmission Start */ +#define XQSPIPS_CR_MANSTRTEN_MASK 0x00008000 /**< Manual Transmission Start + Enable */ +#define XQSPIPS_CR_SSFORCE_MASK 0x00004000 /**< Force Slave Select */ +#define XQSPIPS_CR_SSCTRL_MASK 0x00000400 /**< Slave Select Decode */ +#define XQSPIPS_CR_SSCTRL_SHIFT 10 /**< Slave Select Decode shift */ +#define XQSPIPS_CR_DATA_SZ_MASK 0x000000C0 /**< Size of word to be + transferred */ +#define XQSPIPS_CR_PRESC_MASK 0x00000038 /**< Prescaler Setting */ +#define XQSPIPS_CR_PRESC_SHIFT 3 /**< Prescaler shift */ +#define XQSPIPS_CR_PRESC_MAXIMUM 0x07 /**< Prescaler maximum value */ + +#define XQSPIPS_CR_CPHA_MASK 0x00000004 /**< Phase Configuration */ +#define XQSPIPS_CR_CPOL_MASK 0x00000002 /**< Polarity Configuration */ + +#define XQSPIPS_CR_MSTREN_MASK 0x00000001 /**< Master Mode Enable */ + +#define XQSPIPS_CR_HOLD_B_MASK 0x00080000 /**< HOLD_B Pin Drive Enable */ + +/* Deselect the Slave select line and set the transfer size to 32 at reset */ +#define XQSPIPS_CR_RESET_STATE (XQSPIPS_CR_IFMODE_MASK | \ + XQSPIPS_CR_SSCTRL_MASK | \ + XQSPIPS_CR_DATA_SZ_MASK | \ + XQSPIPS_CR_MSTREN_MASK) +/* @} */ + + +/** @name QSPI Interrupt Registers + * + * QSPI Status Register + * + * This register holds the interrupt status flags for an QSPI device. Some + * of the flags are level triggered, which means that they are set as long + * as the interrupt condition exists. Other flags are edge triggered, + * which means they are set once the interrupt condition occurs and remain + * set until they are cleared by software. The interrupts are cleared by + * writing a '1' to the interrupt bit position in the Status Register. + * Read/Write. + * + * QSPI Interrupt Enable Register + * + * This register is used to enable chosen interrupts for an QSPI device. + * Writing a '1' to a bit in this register sets the corresponding bit in the + * QSPI Interrupt Mask register. Write only. + * + * QSPI Interrupt Disable Register + * + * This register is used to disable chosen interrupts for an QSPI device. + * Writing a '1' to a bit in this register clears the corresponding bit in the + * QSPI Interrupt Mask register. Write only. + * + * QSPI Interrupt Mask Register + * + * This register shows the enabled/disabled interrupts of an QSPI device. + * Read only. + * + * All four registers have the same bit definitions. They are only defined once + * for each of the Interrupt Enable Register, Interrupt Disable Register, + * Interrupt Mask Register, and Channel Interrupt Status Register + * @{ + */ + +#define XQSPIPS_IXR_TXUF_MASK 0x00000040 /**< QSPI Tx FIFO Underflow */ +#define XQSPIPS_IXR_RXFULL_MASK 0x00000020 /**< QSPI Rx FIFO Full */ +#define XQSPIPS_IXR_RXNEMPTY_MASK 0x00000010 /**< QSPI Rx FIFO Not Empty */ +#define XQSPIPS_IXR_TXFULL_MASK 0x00000008 /**< QSPI Tx FIFO Full */ +#define XQSPIPS_IXR_TXOW_MASK 0x00000004 /**< QSPI Tx FIFO Overwater */ +#define XQSPIPS_IXR_RXOVR_MASK 0x00000001 /**< QSPI Rx FIFO Overrun */ +#define XQSPIPS_IXR_DFLT_MASK 0x00000025 /**< QSPI default interrupts + mask */ +#define XQSPIPS_IXR_WR_TO_CLR_MASK 0x00000041 /**< Interrupts which + need write to clear */ +#define XQSPIPS_ISR_RESET_STATE 0x00000004 /**< Default to tx/rx empty */ +#define XQSPIPS_IXR_DISABLE_ALL 0x0000007D /**< Disable all interrupts */ +/* @} */ + + +/** @name Enable Register + * + * This register is used to enable or disable an QSPI device. + * Read/Write + * @{ + */ +#define XQSPIPS_ER_ENABLE_MASK 0x00000001 /**< QSPI Enable Bit Mask */ +/* @} */ + + +/** @name Delay Register + * + * This register is used to program timing delays in + * slave mode. Read/Write + * @{ + */ +#define XQSPIPS_DR_NSS_MASK 0xFF000000 /**< Delay to de-assert slave select + between two words mask */ +#define XQSPIPS_DR_NSS_SHIFT 24 /**< Delay to de-assert slave select + between two words shift */ +#define XQSPIPS_DR_BTWN_MASK 0x00FF0000 /**< Delay Between Transfers + mask */ +#define XQSPIPS_DR_BTWN_SHIFT 16 /**< Delay Between Transfers shift */ +#define XQSPIPS_DR_AFTER_MASK 0x0000FF00 /**< Delay After Transfers mask */ +#define XQSPIPS_DR_AFTER_SHIFT 8 /**< Delay After Transfers shift */ +#define XQSPIPS_DR_INIT_MASK 0x000000FF /**< Delay Initially mask */ +/* @} */ + +/** @name Slave Idle Count Registers + * + * This register defines the number of pclk cycles the slave waits for a the + * QSPI clock to become stable in quiescent state before it can detect the start + * of the next transfer in CPHA = 1 mode. + * Read/Write + * + * @{ + */ +#define XQSPIPS_SICR_MASK 0x000000FF /**< Slave Idle Count Mask */ +/* @} */ + + +/** @name Transmit FIFO Watermark Register + * + * This register defines the watermark setting for the Transmit FIFO. + * + * @{ + */ +#define XQSPIPS_TXWR_MASK 0x0000003F /**< Transmit Watermark Mask */ +#define XQSPIPS_TXWR_RESET_VALUE 0x00000001 /**< Transmit Watermark + * register reset value */ + +/* @} */ + +/** @name Receive FIFO Watermark Register + * + * This register defines the watermark setting for the Receive FIFO. + * + * @{ + */ +#define XQSPIPS_RXWR_MASK 0x0000003F /**< Receive Watermark Mask */ +#define XQSPIPS_RXWR_RESET_VALUE 0x00000001 /**< Receive Watermark + * register reset value */ + +/* @} */ + +/** @name FIFO Depth + * + * This macro provides the depth of transmit FIFO and receive FIFO. + * + * @{ + */ +#define XQSPIPS_FIFO_DEPTH 63 /**< FIFO depth (words) */ +/* @} */ + + +/** @name Linear QSPI Configuration Register + * + * This register contains various control bits that + * affect the operation of the Linear QSPI controller. Read/Write. + * + * @{ + */ +#define XQSPIPS_LQSPI_CR_LINEAR_MASK 0x80000000 /**< LQSPI mode enable */ +#define XQSPIPS_LQSPI_CR_TWO_MEM_MASK 0x40000000 /**< Both memories or one */ +#define XQSPIPS_LQSPI_CR_SEP_BUS_MASK 0x20000000 /**< Seperate memory bus */ +#define XQSPIPS_LQSPI_CR_U_PAGE_MASK 0x10000000 /**< Upper memory page */ +#define XQSPIPS_LQSPI_CR_MODE_EN_MASK 0x02000000 /**< Enable mode bits */ +#define XQSPIPS_LQSPI_CR_MODE_ON_MASK 0x01000000 /**< Mode on */ +#define XQSPIPS_LQSPI_CR_MODE_BITS_MASK 0x00FF0000 /**< Mode value for dual I/O + or quad I/O */ +#define XQSPIPS_LQSPI_CR_DUMMY_MASK 0x00000700 /**< Number of dummy bytes + between addr and return + read data */ +#define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FF /**< Read instr code */ +#define XQSPIPS_LQSPI_CR_RST_STATE 0x8000016B /**< Default CR value */ +/* @} */ + +/** @name Linear QSPI Status Register + * + * This register contains various status bits of the Linear QSPI controller. + * Read/Write. + * + * @{ + */ +#define XQSPIPS_LQSPI_SR_D_FSM_ERR_MASK 0x00000004 /**< AXI Data FSM Error + received */ +#define XQSPIPS_LQSPI_SR_WR_RECVD_MASK 0x00000002 /**< AXI write command + received */ +/* @} */ + + +/** @name Loopback Delay Adjust Register + * + * This register contains various bit masks of Loopback Delay Adjust Register. + * + * @{ + */ + +#define XQSPIPS_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020 /**< Loopback Bit */ + +/* @} */ + + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +#define XQspiPs_In32 Xil_In32 +#define XQspiPs_Out32 Xil_Out32 + +/****************************************************************************/ +/** +* Read a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to the target register. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u32 XQspiPs_ReadReg(u32 BaseAddress. int RegOffset) +* +******************************************************************************/ +#define XQspiPs_ReadReg(BaseAddress, RegOffset) \ + XQspiPs_In32((BaseAddress) + (RegOffset)) + +/***************************************************************************/ +/** +* Write to a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to target register. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XQspiPs_WriteReg(u32 BaseAddress, int RegOffset, +* u32 RegisterValue) +* +******************************************************************************/ +#define XQspiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ + XQspiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue)) + +/************************** Function Prototypes ******************************/ + +/* + * Functions implemented in xqspips_hw.c + */ +void XQspiPs_ResetHw(u32 BaseAddress); +void XQspiPs_LinearInit(u32 BaseAddress); + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h new file mode 100644 index 000000000..0a3a7b0fa --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h @@ -0,0 +1,599 @@ +/******************************************************************************* +* +* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +*******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xreg_cortexa9.h +* +* This header file contains definitions for using inline assembler code. It is +* written specifically for the GNU, ARMCC compiler. +* +* All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along +* with the positions of the bits within the registers. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  10/20/09 First release
+*
+* +******************************************************************************/ +#ifndef XREG_CORTEXA9_H +#define XREG_CORTEXA9_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* GPRs */ +#define XREG_GPR0 r0 +#define XREG_GPR1 r1 +#define XREG_GPR2 r2 +#define XREG_GPR3 r3 +#define XREG_GPR4 r4 +#define XREG_GPR5 r5 +#define XREG_GPR6 r6 +#define XREG_GPR7 r7 +#define XREG_GPR8 r8 +#define XREG_GPR9 r9 +#define XREG_GPR10 r10 +#define XREG_GPR11 r11 +#define XREG_GPR12 r12 +#define XREG_GPR13 r13 +#define XREG_GPR14 r14 +#define XREG_GPR15 r15 +#define XREG_CPSR cpsr + +/* Coprocessor number defines */ +#define XREG_CP0 0 +#define XREG_CP1 1 +#define XREG_CP2 2 +#define XREG_CP3 3 +#define XREG_CP4 4 +#define XREG_CP5 5 +#define XREG_CP6 6 +#define XREG_CP7 7 +#define XREG_CP8 8 +#define XREG_CP9 9 +#define XREG_CP10 10 +#define XREG_CP11 11 +#define XREG_CP12 12 +#define XREG_CP13 13 +#define XREG_CP14 14 +#define XREG_CP15 15 + +/* Coprocessor control register defines */ +#define XREG_CR0 cr0 +#define XREG_CR1 cr1 +#define XREG_CR2 cr2 +#define XREG_CR3 cr3 +#define XREG_CR4 cr4 +#define XREG_CR5 cr5 +#define XREG_CR6 cr6 +#define XREG_CR7 cr7 +#define XREG_CR8 cr8 +#define XREG_CR9 cr9 +#define XREG_CR10 cr10 +#define XREG_CR11 cr11 +#define XREG_CR12 cr12 +#define XREG_CR13 cr13 +#define XREG_CR14 cr14 +#define XREG_CR15 cr15 + +/* Current Processor Status Register (CPSR) Bits */ +#define XREG_CPSR_THUMB_MODE 0x20 +#define XREG_CPSR_MODE_BITS 0x1F +#define XREG_CPSR_SYSTEM_MODE 0x1F +#define XREG_CPSR_UNDEFINED_MODE 0x1B +#define XREG_CPSR_DATA_ABORT_MODE 0x17 +#define XREG_CPSR_SVC_MODE 0x13 +#define XREG_CPSR_IRQ_MODE 0x12 +#define XREG_CPSR_FIQ_MODE 0x11 +#define XREG_CPSR_USER_MODE 0x10 + +#define XREG_CPSR_IRQ_ENABLE 0x80 +#define XREG_CPSR_FIQ_ENABLE 0x40 + +#define XREG_CPSR_N_BIT 0x80000000 +#define XREG_CPSR_Z_BIT 0x40000000 +#define XREG_CPSR_C_BIT 0x20000000 +#define XREG_CPSR_V_BIT 0x10000000 + + +/* CP15 defines */ +#if defined (__GNUC__) +/* C0 Register defines */ +#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0" +#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1" +#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2" +#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3" +#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5" + +#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0" +#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1" +#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2" +#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4" +#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5" +#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6" +#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7" + +#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0" +#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1" +#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2" +#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3" +#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4" + +#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0" +#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1" +#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7" + +#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0" + +/* C1 Register Defines */ +#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0" +#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1" +#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2" + +#define XREG_CP15_SECURE_CONFIG "p15, 0, %0, c1, c1, 0" +#define XREG_CP15_SECURE_DEBUG_ENABLE "p15, 0, %0, c1, c1, 1" +#define XREG_CP15_NS_ACCESS_CONTROL "p15, 0, %0, c1, c1, 2" +#define XREG_CP15_VIRTUAL_CONTROL "p15, 0, %0, c1, c1, 3" + +#else /* RVCT */ +/* C0 Register defines */ +#define XREG_CP15_MAIN_ID "cp15:0:c0:c0:0" +#define XREG_CP15_CACHE_TYPE "cp15:0:c0:c0:1" +#define XREG_CP15_TCM_TYPE "cp15:0:c0:c0:2" +#define XREG_CP15_TLB_TYPE "cp15:0:c0:c0:3" +#define XREG_CP15_MULTI_PROC_AFFINITY "cp15:0:c0:c0:5" + +#define XREG_CP15_PROC_FEATURE_0 "cp15:0:c0:c1:0" +#define XREG_CP15_PROC_FEATURE_1 "cp15:0:c0:c1:1" +#define XREG_CP15_DEBUG_FEATURE_0 "cp15:0:c0:c1:2" +#define XREG_CP15_MEMORY_FEATURE_0 "cp15:0:c0:c1:4" +#define XREG_CP15_MEMORY_FEATURE_1 "cp15:0:c0:c1:5" +#define XREG_CP15_MEMORY_FEATURE_2 "cp15:0:c0:c1:6" +#define XREG_CP15_MEMORY_FEATURE_3 "cp15:0:c0:c1:7" + +#define XREG_CP15_INST_FEATURE_0 "cp15:0:c0:c2:0" +#define XREG_CP15_INST_FEATURE_1 "cp15:0:c0:c2:1" +#define XREG_CP15_INST_FEATURE_2 "cp15:0:c0:c2:2" +#define XREG_CP15_INST_FEATURE_3 "cp15:0:c0:c2:3" +#define XREG_CP15_INST_FEATURE_4 "cp15:0:c0:c2:4" + +#define XREG_CP15_CACHE_SIZE_ID "cp15:1:c0:c0:0" +#define XREG_CP15_CACHE_LEVEL_ID "cp15:1:c0:c0:1" +#define XREG_CP15_AUXILARY_ID "cp15:1:c0:c0:7" + +#define XREG_CP15_CACHE_SIZE_SEL "cp15:2:c0:c0:0" + +/* C1 Register Defines */ +#define XREG_CP15_SYS_CONTROL "cp15:0:c1:c0:0" +#define XREG_CP15_AUX_CONTROL "cp15:0:c1:c0:1" +#define XREG_CP15_CP_ACCESS_CONTROL "cp15:0:c1:c0:2" + +#define XREG_CP15_SECURE_CONFIG "cp15:0:c1:c1:0" +#define XREG_CP15_SECURE_DEBUG_ENABLE "cp15:0:c1:c1:1" +#define XREG_CP15_NS_ACCESS_CONTROL "cp15:0:c1:c1:2" +#define XREG_CP15_VIRTUAL_CONTROL "cp15:0:c1:c1:3" +#endif + +/* XREG_CP15_CONTROL bit defines */ +#define XREG_CP15_CONTROL_TE_BIT 0x40000000 +#define XREG_CP15_CONTROL_AFE_BIT 0x20000000 +#define XREG_CP15_CONTROL_TRE_BIT 0x10000000 +#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000 +#define XREG_CP15_CONTROL_EE_BIT 0x02000000 +#define XREG_CP15_CONTROL_HA_BIT 0x00020000 +#define XREG_CP15_CONTROL_RR_BIT 0x00004000 +#define XREG_CP15_CONTROL_V_BIT 0x00002000 +#define XREG_CP15_CONTROL_I_BIT 0x00001000 +#define XREG_CP15_CONTROL_Z_BIT 0x00000800 +#define XREG_CP15_CONTROL_SW_BIT 0x00000400 +#define XREG_CP15_CONTROL_B_BIT 0x00000080 +#define XREG_CP15_CONTROL_C_BIT 0x00000004 +#define XREG_CP15_CONTROL_A_BIT 0x00000002 +#define XREG_CP15_CONTROL_M_BIT 0x00000001 + +#if defined (__GNUC__) +/* C2 Register Defines */ +#define XREG_CP15_TTBR0 "p15, 0, %0, c2, c0, 0" +#define XREG_CP15_TTBR1 "p15, 0, %0, c2, c0, 1" +#define XREG_CP15_TTB_CONTROL "p15, 0, %0, c2, c0, 2" + +/* C3 Register Defines */ +#define XREG_CP15_DOMAIN_ACCESS_CTRL "p15, 0, %0, c3, c0, 0" + +/* C4 Register Defines */ +/* Not Used */ + +/* C5 Register Defines */ +#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0" +#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1" + +#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0" +#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1" + +/* C6 Register Defines */ +#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0" +#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2" + +/* C7 Register Defines */ +#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4" + +#define XREG_CP15_INVAL_IC_POU_IS "p15, 0, %0, c7, c1, 0" +#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "p15, 0, %0, c7, c1, 6" + +#define XREG_CP15_PHYS_ADDR "p15, 0, %0, c7, c4, 0" + +#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0" +#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1" + +/* The CP15 register access below has been deprecated in favor of the new + * isb instruction in Cortex A9. + */ +#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4" +#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6" + +#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1" +#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2" + +#define XREG_CP15_VA_TO_PA_CURRENT_0 "p15, 0, %0, c7, c8, 0" +#define XREG_CP15_VA_TO_PA_CURRENT_1 "p15, 0, %0, c7, c8, 1" +#define XREG_CP15_VA_TO_PA_CURRENT_2 "p15, 0, %0, c7, c8, 2" +#define XREG_CP15_VA_TO_PA_CURRENT_3 "p15, 0, %0, c7, c8, 3" + +#define XREG_CP15_VA_TO_PA_OTHER_0 "p15, 0, %0, c7, c8, 4" +#define XREG_CP15_VA_TO_PA_OTHER_1 "p15, 0, %0, c7, c8, 5" +#define XREG_CP15_VA_TO_PA_OTHER_2 "p15, 0, %0, c7, c8, 6" +#define XREG_CP15_VA_TO_PA_OTHER_3 "p15, 0, %0, c7, c8, 7" + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1" +#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2" + +/* The next two CP15 register accesses below have been deprecated in favor + * of the new dsb and dmb instructions in Cortex A9. + */ +#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4" +#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5" + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1" + +#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1" + +#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1" +#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2" + +/* C8 Register Defines */ +#define XREG_CP15_INVAL_TLB_IS "p15, 0, %0, c8, c3, 0" +#define XREG_CP15_INVAL_TLB_MVA_IS "p15, 0, %0, c8, c3, 1" +#define XREG_CP15_INVAL_TLB_ASID_IS "p15, 0, %0, c8, c3, 2" +#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "p15, 0, %0, c8, c3, 3" + +#define XREG_CP15_INVAL_ITLB_UNLOCKED "p15, 0, %0, c8, c5, 0" +#define XREG_CP15_INVAL_ITLB_MVA "p15, 0, %0, c8, c5, 1" +#define XREG_CP15_INVAL_ITLB_ASID "p15, 0, %0, c8, c5, 2" + +#define XREG_CP15_INVAL_DTLB_UNLOCKED "p15, 0, %0, c8, c6, 0" +#define XREG_CP15_INVAL_DTLB_MVA "p15, 0, %0, c8, c6, 1" +#define XREG_CP15_INVAL_DTLB_ASID "p15, 0, %0, c8, c6, 2" + +#define XREG_CP15_INVAL_UTLB_UNLOCKED "p15, 0, %0, c8, c7, 0" +#define XREG_CP15_INVAL_UTLB_MVA "p15, 0, %0, c8, c7, 1" +#define XREG_CP15_INVAL_UTLB_ASID "p15, 0, %0, c8, c7, 2" +#define XREG_CP15_INVAL_UTLB_MVA_ASID "p15, 0, %0, c8, c7, 3" + +/* C9 Register Defines */ +#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0" +#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1" +#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2" +#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3" +#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4" +#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5" + +#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0" +#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1" +#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2" + +#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0" +#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1" +#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2" + +/* C10 Register Defines */ +#define XREG_CP15_TLB_LOCKDWN "p15, 0, %0, c10, c0, 0" + +#define XREG_CP15_PRI_MEM_REMAP "p15, 0, %0, c10, c2, 0" +#define XREG_CP15_NORM_MEM_REMAP "p15, 0, %0, c10, c2, 1" + +/* C11 Register Defines */ +/* Not used */ + +/* C12 Register Defines */ +#define XREG_CP15_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 0" +#define XREG_CP15_MONITOR_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 1" + +#define XREG_CP15_INTERRUPT_STATUS "p15, 0, %0, c12, c1, 0" +#define XREG_CP15_VIRTUALIZATION_INTR "p15, 0, %0, c12, c1, 1" + +/* C13 Register Defines */ +#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1" +#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2" +#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3" +#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4" + +/* C14 Register Defines */ +/* not used */ + +/* C15 Register Defines */ +#define XREG_CP15_POWER_CTRL "p15, 0, %0, c15, c0, 0" +#define XREG_CP15_CONFIG_BASE_ADDR "p15, 4, %0, c15, c0, 0" + +#define XREG_CP15_READ_TLB_ENTRY "p15, 5, %0, c15, c4, 2" +#define XREG_CP15_WRITE_TLB_ENTRY "p15, 5, %0, c15, c4, 4" + +#define XREG_CP15_MAIN_TLB_VA "p15, 5, %0, c15, c5, 2" + +#define XREG_CP15_MAIN_TLB_PA "p15, 5, %0, c15, c6, 2" + +#define XREG_CP15_MAIN_TLB_ATTR "p15, 5, %0, c15, c7, 2" + +#else +/* C2 Register Defines */ +#define XREG_CP15_TTBR0 "cp15:0:c2:c0:0" +#define XREG_CP15_TTBR1 "cp15:0:c2:c0:1" +#define XREG_CP15_TTB_CONTROL "cp15:0:c2:c0:2" + +/* C3 Register Defines */ +#define XREG_CP15_DOMAIN_ACCESS_CTRL "cp15:0:c3:c0:0" + +/* C4 Register Defines */ +/* Not Used */ + +/* C5 Register Defines */ +#define XREG_CP15_DATA_FAULT_STATUS "cp15:0:c5:c0:0" +#define XREG_CP15_INST_FAULT_STATUS "cp15:0:c5:c0:1" + +#define XREG_CP15_AUX_DATA_FAULT_STATUS "cp15:0:c5:c1:0" +#define XREG_CP15_AUX_INST_FAULT_STATUS "cp15:0:c5:c1:1" + +/* C6 Register Defines */ +#define XREG_CP15_DATA_FAULT_ADDRESS "cp15:0:c6:c0:0" +#define XREG_CP15_INST_FAULT_ADDRESS "cp15:0:c6:c0:2" + +/* C7 Register Defines */ +#define XREG_CP15_NOP "cp15:0:c7:c0:4" + +#define XREG_CP15_INVAL_IC_POU_IS "cp15:0:c7:c1:0" +#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "cp15:0:c7:c1:6" + +#define XREG_CP15_PHYS_ADDR "cp15:0:c7:c4:0" + +#define XREG_CP15_INVAL_IC_POU "cp15:0:c7:c5:0" +#define XREG_CP15_INVAL_IC_LINE_MVA_POU "cp15:0:c7:c5:1" + +/* The CP15 register access below has been deprecated in favor of the new + * isb instruction in Cortex A9. + */ +#define XREG_CP15_INST_SYNC_BARRIER "cp15:0:c7:c5:4" +#define XREG_CP15_INVAL_BRANCH_ARRAY "cp15:0:c7:c5:6" + +#define XREG_CP15_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c6:1" +#define XREG_CP15_INVAL_DC_LINE_SW "cp15:0:c7:c6:2" + +#define XREG_CP15_VA_TO_PA_CURRENT_0 "cp15:0:c7:c8:0" +#define XREG_CP15_VA_TO_PA_CURRENT_1 "cp15:0:c7:c8:1" +#define XREG_CP15_VA_TO_PA_CURRENT_2 "cp15:0:c7:c8:2" +#define XREG_CP15_VA_TO_PA_CURRENT_3 "cp15:0:c7:c8:3" + +#define XREG_CP15_VA_TO_PA_OTHER_0 "cp15:0:c7:c8:4" +#define XREG_CP15_VA_TO_PA_OTHER_1 "cp15:0:c7:c8:5" +#define XREG_CP15_VA_TO_PA_OTHER_2 "cp15:0:c7:c8:6" +#define XREG_CP15_VA_TO_PA_OTHER_3 "cp15:0:c7:c8:7" + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "cp15:0:c7:c10:1" +#define XREG_CP15_CLEAN_DC_LINE_SW "cp15:0:c7:c10:2" + +/* The next two CP15 register accesses below have been deprecated in favor + * of the new dsb and dmb instructions in Cortex A9. + */ +#define XREG_CP15_DATA_SYNC_BARRIER "cp15:0:c7:c10:4" +#define XREG_CP15_DATA_MEMORY_BARRIER "cp15:0:c7:c10:5" + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "cp15:0:c7:c11:1" + +#define XREG_CP15_NOP2 "cp15:0:c7:c13:1" + +#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c14:1" +#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "cp15:0:c7:c14:2" + +/* C8 Register Defines */ +#define XREG_CP15_INVAL_TLB_IS "cp15:0:c8:c3:0" +#define XREG_CP15_INVAL_TLB_MVA_IS "cp15:0:c8:c3:1" +#define XREG_CP15_INVAL_TLB_ASID_IS "cp15:0:c8:c3:2" +#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "cp15:0:c8:c3:3" + +#define XREG_CP15_INVAL_ITLB_UNLOCKED "cp15:0:c8:c5:0" +#define XREG_CP15_INVAL_ITLB_MVA "cp15:0:c8:c5:1" +#define XREG_CP15_INVAL_ITLB_ASID "cp15:0:c8:c5:2" + +#define XREG_CP15_INVAL_DTLB_UNLOCKED "cp15:0:c8:c6:0" +#define XREG_CP15_INVAL_DTLB_MVA "cp15:0:c8:c6:1" +#define XREG_CP15_INVAL_DTLB_ASID "cp15:0:c8:c6:2" + +#define XREG_CP15_INVAL_UTLB_UNLOCKED "cp15:0:c8:c7:0" +#define XREG_CP15_INVAL_UTLB_MVA "cp15:0:c8:c7:1" +#define XREG_CP15_INVAL_UTLB_ASID "cp15:0:c8:c7:2" +#define XREG_CP15_INVAL_UTLB_MVA_ASID "cp15:0:c8:c7:3" + +/* C9 Register Defines */ +#define XREG_CP15_PERF_MONITOR_CTRL "cp15:0:c9:c12:0" +#define XREG_CP15_COUNT_ENABLE_SET "cp15:0:c9:c12:1" +#define XREG_CP15_COUNT_ENABLE_CLR "cp15:0:c9:c12:2" +#define XREG_CP15_V_FLAG_STATUS "cp15:0:c9:c12:3" +#define XREG_CP15_SW_INC "cp15:0:c9:c12:4" +#define XREG_CP15_EVENT_CNTR_SEL "cp15:0:c9:c12:5" + +#define XREG_CP15_PERF_CYCLE_COUNTER "cp15:0:c9:c13:0" +#define XREG_CP15_EVENT_TYPE_SEL "cp15:0:c9:c13:1" +#define XREG_CP15_PERF_MONITOR_COUNT "cp15:0:c9:c13:2" + +#define XREG_CP15_USER_ENABLE "cp15:0:c9:c14:0" +#define XREG_CP15_INTR_ENABLE_SET "cp15:0:c9:c14:1" +#define XREG_CP15_INTR_ENABLE_CLR "cp15:0:c9:c14:2" + +/* C10 Register Defines */ +#define XREG_CP15_TLB_LOCKDWN "cp15:0:c10:c0:0" + +#define XREG_CP15_PRI_MEM_REMAP "cp15:0:c10:c2:0" +#define XREG_CP15_NORM_MEM_REMAP "cp15:0:c10:c2:1" + +/* C11 Register Defines */ +/* Not used */ + +/* C12 Register Defines */ +#define XREG_CP15_VEC_BASE_ADDR "cp15:0:c12:c0:0" +#define XREG_CP15_MONITOR_VEC_BASE_ADDR "cp15:0:c12:c0:1" + +#define XREG_CP15_INTERRUPT_STATUS "cp15:0:c12:c1:0" +#define XREG_CP15_VIRTUALIZATION_INTR "cp15:0:c12:c1:1" + +/* C13 Register Defines */ +#define XREG_CP15_CONTEXT_ID "cp15:0:c13:c0:1" +#define USER_RW_THREAD_PID "cp15:0:c13:c0:2" +#define USER_RO_THREAD_PID "cp15:0:c13:c0:3" +#define USER_PRIV_THREAD_PID "cp15:0:c13:c0:4" + +/* C14 Register Defines */ +/* not used */ + +/* C15 Register Defines */ +#define XREG_CP15_POWER_CTRL "cp15:0:c15:c0:0" +#define XREG_CP15_CONFIG_BASE_ADDR "cp15:4:c15:c0:0" + +#define XREG_CP15_READ_TLB_ENTRY "cp15:5:c15:c4:2" +#define XREG_CP15_WRITE_TLB_ENTRY "cp15:5:c15:c4:4" + +#define XREG_CP15_MAIN_TLB_VA "cp15:5:c15:c5:2" + +#define XREG_CP15_MAIN_TLB_PA "cp15:5:c15:c6:2" + +#define XREG_CP15_MAIN_TLB_ATTR "cp15:5:c15:c7:2" +#endif + + +/* MPE register definitions */ +#define XREG_FPSID c0 +#define XREG_FPSCR c1 +#define XREG_MVFR1 c6 +#define XREG_MVFR0 c7 +#define XREG_FPEXC c8 +#define XREG_FPINST c9 +#define XREG_FPINST2 c10 + +/* FPSID bits */ +#define XREG_FPSID_IMPLEMENTER_BIT (24) +#define XREG_FPSID_IMPLEMENTER_MASK (0xFF << FPSID_IMPLEMENTER_BIT) +#define XREG_FPSID_SOFTWARE (1<<23) +#define XREG_FPSID_ARCH_BIT (16) +#define XREG_FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT) +#define XREG_FPSID_PART_BIT (8) +#define XREG_FPSID_PART_MASK (0xFF << FPSID_PART_BIT) +#define XREG_FPSID_VARIANT_BIT (4) +#define XREG_FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT) +#define XREG_FPSID_REV_BIT (0) +#define XREG_FPSID_REV_MASK (0xF << FPSID_REV_BIT) + +/* FPSCR bits */ +#define XREG_FPSCR_N_BIT (1 << 31) +#define XREG_FPSCR_Z_BIT (1 << 30) +#define XREG_FPSCR_C_BIT (1 << 29) +#define XREG_FPSCR_V_BIT (1 << 28) +#define XREG_FPSCR_QC (1 << 27) +#define XREG_FPSCR_AHP (1 << 26) +#define XREG_FPSCR_DEFAULT_NAN (1 << 25) +#define XREG_FPSCR_FLUSHTOZERO (1 << 24) +#define XREG_FPSCR_ROUND_NEAREST (0 << 22) +#define XREG_FPSCR_ROUND_PLUSINF (1 << 22) +#define XREG_FPSCR_ROUND_MINUSINF (2 << 22) +#define XREG_FPSCR_ROUND_TOZERO (3 << 22) +#define XREG_FPSCR_RMODE_BIT (22) +#define XREG_FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT) +#define XREG_FPSCR_STRIDE_BIT (20) +#define XREG_FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT) +#define XREG_FPSCR_LENGTH_BIT (16) +#define XREG_FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT) +#define XREG_FPSCR_IDC (1 << 7) +#define XREG_FPSCR_IXC (1 << 4) +#define XREG_FPSCR_UFC (1 << 3) +#define XREG_FPSCR_OFC (1 << 2) +#define XREG_FPSCR_DZC (1 << 1) +#define XREG_FPSCR_IOC (1 << 0) + +/* MVFR0 bits */ +#define XREG_MVFR0_RMODE_BIT (28) +#define XREG_MVFR0_RMODE_MASK (0xF << XREG_MVFR0_RMODE_BIT) +#define XREG_MVFR0_SHORT_VEC_BIT (24) +#define XREG_MVFR0_SHORT_VEC_MASK (0xF << XREG_MVFR0_SHORT_VEC_BIT) +#define XREG_MVFR0_SQRT_BIT (20) +#define XREG_MVFR0_SQRT_MASK (0xF << XREG_MVFR0_SQRT_BIT) +#define XREG_MVFR0_DIVIDE_BIT (16) +#define XREG_MVFR0_DIVIDE_MASK (0xF << XREG_MVFR0_DIVIDE_BIT) +#define XREG_MVFR0_EXEC_TRAP_BIT (12) +#define XREG_MVFR0_EXEC_TRAP_MASK (0xF << XREG_MVFR0_EXEC_TRAP_BIT) +#define XREG_MVFR0_DP_BIT (8) +#define XREG_MVFR0_DP_MASK (0xF << XREG_MVFR0_DP_BIT) +#define XREG_MVFR0_SP_BIT (4) +#define XREG_MVFR0_SP_MASK (0xF << XREG_MVFR0_SP_BIT) +#define XREG_MVFR0_A_SIMD_BIT (0) +#define XREG_MVFR0_A_SIMD_MASK (0xF << MVFR0_A_SIMD_BIT) + +/* FPEXC bits */ +#define XREG_FPEXC_EX (1 << 31) +#define XREG_FPEXC_EN (1 << 30) +#define XREG_FPEXC_DEX (1 << 29) + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XREG_CORTEXA9_H */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xscugic.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xscugic.h new file mode 100644 index 000000000..9a43efbb3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xscugic.h @@ -0,0 +1,324 @@ +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xscugic.h +* +* The generic interrupt controller driver component. +* +* The interrupt controller driver uses the idea of priority for the various +* handlers. Priority is an integer within the range of 1 and 31 inclusive with +* default of 1 being the highest priority interrupt source. The priorities +* of the various sources can be dynamically altered as needed through +* hardware configuration. +* +* The generic interrupt controller supports the following +* features: +* +* - specific individual interrupt enabling/disabling +* - specific individual interrupt acknowledging +* - attaching specific callback function to handle interrupt source +* - assigning desired priority to interrupt source if default is not +* acceptable. +* +* Details about connecting the interrupt handler of the driver are contained +* in the source file specific to interrupt processing, xscugic_intr.c. +* +* This driver is intended to be RTOS and processor independent. It works with +* physical addresses only. Any needs for dynamic memory management, threads +* or thread mutual exclusion, virtual memory, or cache control must be +* satisfied by the layer above this driver. +* +* Interrupt Vector Tables +* +* The device ID of the interrupt controller device is used by the driver as a +* direct index into the configuration data table. The user should populate the +* vector table with handlers and callbacks at run-time using the +* XScuGic_Connect() and XScuGic_Disconnect() functions. +* +* Each vector table entry corresponds to a device that can generate an +* interrupt. Each entry contains an interrupt handler function and an +* argument to be passed to the handler when an interrupt occurs. The +* user must use XScuGic_Connect() when the interrupt handler takes an +* argument other than the base address. +* +* Nested Interrupts Processing +* +* Nested interrupts are not supported by this driver. +* +* NOTE: +* The generic interrupt controller is not a part of the snoop control unit +* as indicated by the prefix "scu" in the name of the driver. +* It is an independent module in APU. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00a drg  01/19/00 First release
+* 1.01a sdm  11/09/11 The XScuGic and XScuGic_Config structures have changed.
+*		      The HandlerTable (of type XScuGic_VectorTableEntry) is
+*		      moved to XScuGic_Config structure from XScuGic structure.
+*
+*		      The "Config" entry in XScuGic structure is made as
+*		      pointer for better efficiency.
+*
+*		      A new file named as xscugic_hw.c is now added. It is
+*		      to implement low level driver routines without using
+*		      any xscugic instance pointer. They are useful when the
+*		      user wants to use xscugic through device id or
+*		      base address. The driver routines provided are explained
+*		      below.
+*		      XScuGic_DeviceInitialize that takes device id as
+*		      argument and initializes the device (without calling
+*		      XScuGic_CfgInitialize).
+*		      XScuGic_DeviceInterruptHandler that takes device id
+*		      as argument and calls appropriate handlers from the
+*		      HandlerTable.
+*		      XScuGic_RegisterHandler that registers a new handler
+*		      by taking xscugic hardware base address as argument.
+*		      LookupConfigByBaseAddress is used to return the
+*		      corresponding config structure from XScuGic_ConfigTable
+*		      based on the scugic base address passed.
+* 1.02a sdm  12/20/11 Removed AckBeforeService from the XScuGic_Config
+*		      structure.
+* 1.03a srt  02/27/13 Moved Offset calculation macros from *.c and *_hw.c to
+*		      *_hw.h
+*		      Added APIs
+*			- XScuGic_SetPriTrigTypeByDistAddr()
+*			- XScuGic_GetPriTrigTypeByDistAddr()
+*		      (CR 702687)
+*			Added support to direct interrupts to the appropriate CPU. Earlier
+*			  interrupts were directed to CPU1 (hard coded). Now depending
+*			  upon the CPU selected by the user (xparameters.h), interrupts
+*			  will be directed to the relevant CPU. This fixes CR 699688.
+* 1.04a hk   05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
+*			  XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
+*			  Moved functions XScuGic_SetPriTrigTypeByDistAddr and
+*             XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
+*			  This is fix for CR#705621.
+* 1.05a hk   06/26/13 Modified tcl to export external interrupts correctly to
+*                     xparameters.h. Fix for CR's 690505, 708928 & 719359.
+* 2.0   adk  12/10/13 Updated as per the New Tcl API's
+* 2.1   adk  25/04/14 Fixed the CR:789373 changes are made in the driver tcl file.
+*
+*
+* +******************************************************************************/ + +#ifndef XSCUGIC_H /* prevent circular inclusions */ +#define XSCUGIC_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xil_io.h" +#include "xscugic_hw.h" +#include "xil_exception.h" + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + +/* The following data type defines each entry in an interrupt vector table. + * The callback reference is the base address of the interrupting device + * for the low level driver and an instance pointer for the high level driver. + */ +typedef struct +{ + Xil_InterruptHandler Handler; + void *CallBackRef; +} XScuGic_VectorTableEntry; + +/** + * This typedef contains configuration information for the device. + */ +typedef struct +{ + u16 DeviceId; /**< Unique ID of device */ + u32 CpuBaseAddress; /**< CPU Interface Register base address */ + u32 DistBaseAddress; /**< Distributor Register base address */ + XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**< + Vector table of interrupt handlers */ +} XScuGic_Config; + +/** + * The XScuGic driver instance data. The user is required to allocate a + * variable of this type for every intc device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct +{ + XScuGic_Config *Config; /**< Configuration table entry */ + u32 IsReady; /**< Device is initialized and ready */ + u32 UnhandledInterrupts; /**< Intc Statistics */ +} XScuGic; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Write the given CPU Interface register +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note +* C-style signature: +* void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \ +(XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \ + ((u32)Data))) + +/****************************************************************************/ +/** +* +* Read the given CPU Interface register +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note +* C-style signature: +* u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset) +* +*****************************************************************************/ +#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \ + (XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset))) + +/****************************************************************************/ +/** +* +* Write the given Distributor Interface register +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note +* C-style signature: +* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \ +(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \ + ((u32)Data))) + +/****************************************************************************/ +/** +* +* Read the given Distributor Interface register +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note +* C-style signature: +* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset) +* +*****************************************************************************/ +#define XScuGic_DistReadReg(InstancePtr, RegOffset) \ +(XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset))) + +/************************** Function Prototypes ******************************/ + +/* + * Required functions in xscugic.c + */ + +int XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id, + Xil_InterruptHandler Handler, void *CallBackRef); +void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id); + +void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id); +void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id); + +int XScuGic_CfgInitialize(XScuGic *InstancePtr, XScuGic_Config *ConfigPtr, + u32 EffectiveAddr); + +int XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id); + +void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, + u8 *Priority, u8 *Trigger); +void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, + u8 Priority, u8 Trigger); + +/* + * Initialization functions in xscugic_sinit.c + */ +XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId); + +/* + * Interrupt functions in xscugic_intr.c + */ +void XScuGic_InterruptHandler(XScuGic *InstancePtr); + +/* + * Self-test functions in xscugic_selftest.c + */ +int XScuGic_SelfTest(XScuGic *InstancePtr); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xscugic_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xscugic_hw.h new file mode 100644 index 000000000..0530ee8c0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xscugic_hw.h @@ -0,0 +1,641 @@ +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xscugic_hw.h +* +* This header file contains identifiers and HW access functions (or +* macros) that can be used to access the device. The user should refer to the +* hardware device specification for more details of the device operation. +* The driver functions/APIs are defined in xscugic.h. +* +* This GIC device has two parts, a distributor and CPU interface(s). Each part +* has separate register definition sections. +* +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 1.01a sdm  11/09/11 "xil_exception.h" added as include.
+*		      Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
+*		      added to enable or disable interrupts based on
+*		      Distributor Register base address. Normally users use
+*		      XScuGic instance and call XScuGic_Enable or
+*		      XScuGic_Disable to enable/disable interrupts. These
+*		      new macros are provided when user does not want to
+*		      use an instance pointer but still wants to enable or
+*		      disable interrupts.
+*		      Function prototypes for functions (present in newly
+*		      added file xscugic_hw.c) are added.
+* 1.03a srt  02/27/13 Moved Offset calculation macros from *_hw.c (CR
+*		      702687).
+* 1.04a hk   05/04/13 Fix for CR#705621. Moved function prototypes
+*			  XScuGic_SetPriTrigTypeByDistAddr and
+*             XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
+*
+*
+* +******************************************************************************/ + +#ifndef XSCUGIC_HW_H /* prevent circular inclusions */ +#define XSCUGIC_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" +#include "xil_exception.h" + +/************************** Constant Definitions *****************************/ + +/* + * The maximum number of interrupts supported by the hardware. + */ +#define XSCUGIC_MAX_NUM_INTR_INPUTS 95 + +/* + * The maximum priority value that can be used in the GIC. + */ +#define XSCUGIC_MAX_INTR_PRIO_VAL 248 +#define XSCUGIC_INTR_PRIO_MASK 0xF8 + +/** @name Distributor Interface Register Map + * + * Define the offsets from the base address for all Distributor registers of + * the interrupt controller, some registers may be reserved in the hardware + * device. + * @{ + */ +#define XSCUGIC_DIST_EN_OFFSET 0x00000000 /**< Distributor Enable + Register */ +#define XSCUGIC_IC_TYPE_OFFSET 0x00000004 /**< Interrupt Controller + Type Register */ +#define XSCUGIC_DIST_IDENT_OFFSET 0x00000008 /**< Implementor ID + Register */ +#define XSCUGIC_SECURITY_OFFSET 0x00000080 /**< Interrupt Security + Register */ +#define XSCUGIC_ENABLE_SET_OFFSET 0x00000100 /**< Enable Set + Register */ +#define XSCUGIC_DISABLE_OFFSET 0x00000180 /**< Enable Clear Register */ +#define XSCUGIC_PENDING_SET_OFFSET 0x00000200 /**< Pending Set + Register */ +#define XSCUGIC_PENDING_CLR_OFFSET 0x00000280 /**< Pending Clear + Register */ +#define XSCUGIC_ACTIVE_OFFSET 0x00000300 /**< Active Status Register */ +#define XSCUGIC_PRIORITY_OFFSET 0x00000400 /**< Priority Level Register */ +#define XSCUGIC_SPI_TARGET_OFFSET 0x00000800 /**< SPI Target + Register 0x800-0x8FB */ +#define XSCUGIC_INT_CFG_OFFSET 0x00000C00 /**< Interrupt Configuration + Register 0xC00-0xCFC */ +#define XSCUGIC_PPI_STAT_OFFSET 0x00000D00 /**< PPI Status Register */ +#define XSCUGIC_SPI_STAT_OFFSET 0x00000D04 /**< SPI Status Register + 0xd04-0xd7C */ +#define XSCUGIC_AHB_CONFIG_OFFSET 0x00000D80 /**< AHB Configuration + Register */ +#define XSCUGIC_SFI_TRIG_OFFSET 0x00000F00 /**< Software Triggered + Interrupt Register */ +#define XSCUGIC_PERPHID_OFFSET 0x00000FD0 /**< Peripheral ID Reg */ +#define XSCUGIC_PCELLID_OFFSET 0x00000FF0 /**< Pcell ID Register */ +/* @} */ + +/** @name Distributor Enable Register + * Controls if the distributor response to external interrupt inputs. + * @{ + */ +#define XSCUGIC_EN_INT_MASK 0x00000001 /**< Interrupt In Enable */ +/* @} */ + +/** @name Interrupt Controller Type Register + * @{ + */ +#define XSCUGIC_LSPI_MASK 0x0000F800 /**< Number of Lockable + Shared Peripheral + Interrupts*/ +#define XSCUGIC_DOMAIN_MASK 0x00000400 /**< Number os Security domains*/ +#define XSCUGIC_CPU_NUM_MASK 0x000000E0 /**< Number of CPU Interfaces */ +#define XSCUGIC_NUM_INT_MASK 0x0000001F /**< Number of Interrupt IDs */ +/* @} */ + +/** @name Implementor ID Register + * Implementor and revision information. + * @{ + */ +#define XSCUGIC_REV_MASK 0x00FFF000 /**< Revision Number */ +#define XSCUGIC_IMPL_MASK 0x00000FFF /**< Implementor */ +/* @} */ + +/** @name Interrupt Security Registers + * Each bit controls the security level of an interrupt, either secure or non + * secure. These registers can only be accessed using secure read and write. + * There are registers for each of the CPU interfaces at offset 0x080. A + * register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x084. + * @{ + */ +#define XSCUGIC_INT_NS_MASK 0x00000001 /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Enable Set Register + * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is + * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a + * bit to 0. + * There are registers for each of the CPU interfaces at offset 0x100. With up + * to 8 registers aliased to the same address. A register set for the SPI + * interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x104. + * @{ + */ +#define XSCUGIC_INT_EN_MASK 0x00000001 /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Enable Clear Register + * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is + * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and + * sets the corresponding bit to 0. + * There are registers for each of the CPU interfaces at offset 0x180. With up + * to 8 registers aliased to the same address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x184. + * @{ + */ +#define XSCUGIC_INT_CLR_MASK 0x00000001 /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Pending Set Register + * Each bit controls the Pending or Active and Pending state of an interrupt, a + * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets + * an interrupt to the pending state. + * There are registers for each of the CPU interfaces at offset 0x200. With up + * to 8 registers aliased to the same address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x204. + * @{ + */ +#define XSCUGIC_PEND_SET_MASK 0x00000001 /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Pending Clear Register + * Each bit can clear the Pending or Active and Pending state of an interrupt, a + * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 + * clears the pending state of an interrupt. + * There are registers for each of the CPU interfaces at offset 0x280. With up + * to 8 registers aliased to the same address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x284. + * @{ + */ +#define XSCUGIC_PEND_CLR_MASK 0x00000001 /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Active Status Register + * Each bit provides the Active status of an interrupt, a + * 0 is not Active, a 1 is Active. This is a read only register. + * There are registers for each of the CPU interfaces at offset 0x300. With up + * to 8 registers aliased to each address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x380. + * @{ + */ +#define XSCUGIC_ACTIVE_MASK 0x00000001 /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Priority Level Register + * Each byte in a Priority Level Register sets the priority level of an + * interrupt. Reading the register provides the priority level of an interrupt. + * There are registers for each of the CPU interfaces at offset 0x400 through + * 0x41C. With up to 8 registers aliased to each address. + * 0 is highest priority, 0xFF is lowest. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 255 of these registers staring at location 0x420. + * @{ + */ +#define XSCUGIC_PRIORITY_MASK 0x000000FF /**< Each Byte corresponds to an + INT_ID */ +#define XSCUGIC_PRIORITY_MAX 0x000000FF /**< Highest value of a priority + actually the lowest priority*/ +/* @} */ + +/** @name SPI Target Register 0x800-0x8FB + * Each byte references a separate SPI and programs which of the up to 8 CPU + * interfaces are sent a Pending interrupt. + * There are registers for each of the CPU interfaces at offset 0x800 through + * 0x81C. With up to 8 registers aliased to each address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 255 of these registers staring at location 0x820. + * + * This driver does not support multiple CPU interfaces. These are included + * for complete documentation. + * @{ + */ +#define XSCUGIC_SPI_CPU7_MASK 0x00000080 /**< CPU 7 Mask*/ +#define XSCUGIC_SPI_CPU6_MASK 0x00000040 /**< CPU 6 Mask*/ +#define XSCUGIC_SPI_CPU5_MASK 0x00000020 /**< CPU 5 Mask*/ +#define XSCUGIC_SPI_CPU4_MASK 0x00000010 /**< CPU 4 Mask*/ +#define XSCUGIC_SPI_CPU3_MASK 0x00000008 /**< CPU 3 Mask*/ +#define XSCUGIC_SPI_CPU2_MASK 0x00000003 /**< CPU 2 Mask*/ +#define XSCUGIC_SPI_CPU1_MASK 0x00000002 /**< CPU 1 Mask*/ +#define XSCUGIC_SPI_CPU0_MASK 0x00000001 /**< CPU 0 Mask*/ +/* @} */ + +/** @name Interrupt Configuration Register 0xC00-0xCFC + * The interrupt configuration registers program an SFI to be active HIGH level + * sensitive or rising edge sensitive. + * Each bit pair describes the configuration for an INT_ID. + * SFI Read Only b10 always + * PPI Read Only depending on how the PPIs are configured. + * b01 Active HIGH level sensitive + * b11 Rising edge sensitive + * SPI LSB is read only. + * b01 Active HIGH level sensitive + * b11 Rising edge sensitive/ + * There are registers for each of the CPU interfaces at offset 0xC00 through + * 0xC04. With up to 8 registers aliased to each address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 255 of these registers staring at location 0xC08. + * @{ + */ +#define XSCUGIC_INT_CFG_MASK 0x00000003 /**< */ +/* @} */ + +/** @name PPI Status Register + * Enables an external AMBA master to access the status of the PPI inputs. + * A CPU can only read the status of its local PPI signals and cannot read the + * status for other CPUs. + * This register is aliased for each CPU interface. + * @{ + */ +#define XSCUGIC_PPI_C15_MASK 0x00008000 /**< PPI Status */ +#define XSCUGIC_PPI_C14_MASK 0x00004000 /**< PPI Status */ +#define XSCUGIC_PPI_C13_MASK 0x00002000 /**< PPI Status */ +#define XSCUGIC_PPI_C12_MASK 0x00001000 /**< PPI Status */ +#define XSCUGIC_PPI_C11_MASK 0x00000800 /**< PPI Status */ +#define XSCUGIC_PPI_C10_MASK 0x00000400 /**< PPI Status */ +#define XSCUGIC_PPI_C09_MASK 0x00000200 /**< PPI Status */ +#define XSCUGIC_PPI_C08_MASK 0x00000100 /**< PPI Status */ +#define XSCUGIC_PPI_C07_MASK 0x00000080 /**< PPI Status */ +#define XSCUGIC_PPI_C06_MASK 0x00000040 /**< PPI Status */ +#define XSCUGIC_PPI_C05_MASK 0x00000020 /**< PPI Status */ +#define XSCUGIC_PPI_C04_MASK 0x00000010 /**< PPI Status */ +#define XSCUGIC_PPI_C03_MASK 0x00000008 /**< PPI Status */ +#define XSCUGIC_PPI_C02_MASK 0x00000004 /**< PPI Status */ +#define XSCUGIC_PPI_C01_MASK 0x00000002 /**< PPI Status */ +#define XSCUGIC_PPI_C00_MASK 0x00000001 /**< PPI Status */ +/* @} */ + +/** @name SPI Status Register 0xd04-0xd7C + * Enables an external AMBA master to access the status of the SPI inputs. + * There are up to 63 registers if the maximum number of SPI inputs are + * configured. + * @{ + */ +#define XSCUGIC_SPI_N_MASK 0x00000001 /**< Each bit corresponds to an SPI + input */ +/* @} */ + +/** @name AHB Configuration Register + * Provides the status of the CFGBIGEND input signal and allows the endianess + * of the GIC to be set. + * @{ + */ +#define XSCUGIC_AHB_END_MASK 0x00000004 /**< 0-GIC uses little Endian, + 1-GIC uses Big Endian */ +#define XSCUGIC_AHB_ENDOVR_MASK 0x00000002 /**< 0-Uses CFGBIGEND control, + 1-use the AHB_END bit */ +#define XSCUGIC_AHB_TIE_OFF_MASK 0x00000001 /**< State of CFGBIGEND */ + +/* @} */ + +/** @name Software Triggered Interrupt Register + * Controls issueing of software interrupts. + * @{ + */ +#define XSCUGIC_SFI_SELFTRIG_MASK 0x02010000 +#define XSCUGIC_SFI_TRIG_TRGFILT_MASK 0x03000000 /**< Target List filter + b00-Use the target List + b01-All CPUs except requester + b10-To Requester + b11-reserved */ +#define XSCUGIC_SFI_TRIG_CPU_MASK 0x00FF0000 /**< CPU Target list */ +#define XSCUGIC_SFI_TRIG_SATT_MASK 0x00008000 /**< 0= Use a secure interrupt */ +#define XSCUGIC_SFI_TRIG_INTID_MASK 0x0000000F /**< Set to the INTID + signaled to the CPU*/ +/* @} */ + +/** @name CPU Interface Register Map + * + * Define the offsets from the base address for all CPU registers of the + * interrupt controller, some registers may be reserved in the hardware device. + * @{ + */ +#define XSCUGIC_CONTROL_OFFSET 0x00000000 /**< CPU Interface Control + Register */ +#define XSCUGIC_CPU_PRIOR_OFFSET 0x00000004 /**< Priority Mask Reg */ +#define XSCUGIC_BIN_PT_OFFSET 0x00000008 /**< Binary Point Register */ +#define XSCUGIC_INT_ACK_OFFSET 0x0000000C /**< Interrupt ACK Reg */ +#define XSCUGIC_EOI_OFFSET 0x00000010 /**< End of Interrupt Reg */ +#define XSCUGIC_RUN_PRIOR_OFFSET 0x00000014 /**< Running Priority Reg */ +#define XSCUGIC_HI_PEND_OFFSET 0x00000018 /**< Highest Pending Interrupt + Register */ +#define XSCUGIC_ALIAS_BIN_PT_OFFSET 0x0000001C /**< Aliased non-Secure + Binary Point Register */ + +/**< 0x00000020 to 0x00000FBC are reserved and should not be read or written + * to. */ +/* @} */ + + +/** @name Control Register + * CPU Interface Control register definitions + * All bits are defined here although some are not available in the non-secure + * mode. + * @{ + */ +#define XSCUGIC_CNTR_SBPR_MASK 0x00000010 /**< Secure Binary Pointer, + 0=separate registers, + 1=both use bin_pt_s */ +#define XSCUGIC_CNTR_FIQEN_MASK 0x00000008 /**< Use nFIQ_C for secure + interrupts, + 0= use IRQ for both, + 1=Use FIQ for secure, IRQ for non*/ +#define XSCUGIC_CNTR_ACKCTL_MASK 0x00000004 /**< Ack control for secure or non secure */ +#define XSCUGIC_CNTR_EN_NS_MASK 0x00000002 /**< Non Secure enable */ +#define XSCUGIC_CNTR_EN_S_MASK 0x00000001 /**< Secure enable, 0=Disabled, 1=Enabled */ +/* @} */ + +/** @name Priority Mask Register + * Priority Mask register definitions + * The CPU interface does not send interrupt if the level of the interrupt is + * lower than the level of the register. + * @{ + */ +#define XSCUGIC_PRIORITY_MASK 0x000000FF /**< All interrupts */ +/* @} */ + +/** @name Binary Point Register + * Binary Point register definitions + * @{ + */ + +#define XSCUGIC_BIN_PT_MASK 0x00000007 /**< Binary point mask value + Value Secure Non-secure + b000 0xFE 0xFF + b001 0xFC 0xFE + b010 0xF8 0xFC + b011 0xF0 0xF8 + b100 0xE0 0xF0 + b101 0xC0 0xE0 + b110 0x80 0xC0 + b111 0x00 0x80 + */ +/*@}*/ + +/** @name Interrupt Acknowledge Register + * Interrupt Acknowledge register definitions + * Identifies the current Pending interrupt, and the CPU ID for software + * interrupts. + */ +#define XSCUGIC_ACK_INTID_MASK 0x000003FF /**< Interrupt ID */ +#define XSCUGIC_CPUID_MASK 0x00000C00 /**< CPU ID */ +/* @} */ + +/** @name End of Interrupt Register + * End of Interrupt register definitions + * Allows the CPU to signal the GIC when it completes an interrupt service + * routine. + */ +#define XSCUGIC_EOI_INTID_MASK 0x000003FF /**< Interrupt ID */ + +/* @} */ + +/** @name Running Priority Register + * Running Priority register definitions + * Identifies the interrupt priority level of the highest priority active + * interrupt. + */ +#define XSCUGIC_RUN_PRIORITY_MASK 0x00000FF /**< Interrupt Priority */ +/* @} */ + +/* + * Highest Pending Interrupt register definitions + * Identifies the interrupt priority of the highest priority pending interupt + */ +#define XSCUGIC_PEND_INTID_MASK 0x000003FF /**< Pending Interrupt ID */ +#define XSCUGIC_CPUID_MASK 0x00000C00 /**< CPU ID */ +/* @} */ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Read the Interrupt Configuration Register offset for an interrupt id. +* +* @param InterruptID is the interrupt number. +* +* @return The 32-bit value of the offset +* +* @note +* +*****************************************************************************/ +#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \ + (XSCUGIC_INT_CFG_OFFSET + ((InterruptID/16) * 4)) + +/****************************************************************************/ +/** +* +* Read the Interrupt Priority Register offset for an interrupt id. +* +* @param InterruptID is the interrupt number. +* +* @return The 32-bit value of the offset +* +* @note +* +*****************************************************************************/ +#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \ + (XSCUGIC_PRIORITY_OFFSET + ((InterruptID/4) * 4)) + +/****************************************************************************/ +/** +* +* Read the SPI Target Register offset for an interrupt id. +* +* @param InterruptID is the interrupt number. +* +* @return The 32-bit value of the offset +* +* @note +* +*****************************************************************************/ +#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \ + (XSCUGIC_SPI_TARGET_OFFSET + ((InterruptID/4) * 4)) + +/****************************************************************************/ +/** +* +* Read the Interrupt Clear-Enable Register offset for an interrupt ID +* +* @param Register is the register offset for the clear/enable bank. +* @param InterruptID is the interrupt number. +* +* @return The 32-bit value of the offset +* +* @note +* +*****************************************************************************/ +#define XSCUGIC_ENABLE_DISABLE_OFFSET_CALC(Register, InterruptID) \ + (Register + ((InterruptID/32) * 4)) + +/****************************************************************************/ +/** +* +* Read the given Intc register. +* +* @param BaseAddress is the base address of the device. +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note +* C-style signature: +* u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset) +* +*****************************************************************************/ +#define XScuGic_ReadReg(BaseAddress, RegOffset) \ + (Xil_In32((BaseAddress) + (RegOffset))) + + +/****************************************************************************/ +/** +* +* Write the given Intc register. +* +* @param BaseAddress is the base address of the device. +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note +* C-style signature: +* void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \ + (Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)Data))) + + +/****************************************************************************/ +/** +* +* Enable specific interrupt(s) in the interrupt controller. +* +* @param DistBaseAddress is the Distributor Register base address of the +* device +* @param Int_Id is the ID of the interrupt source and should be in the +* range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1 +* +* @return None. +* +* @note C-style signature: +* void XScuGic_EnableIntr(u32 DistBaseAddress, u32 Int_Id); +* +*****************************************************************************/ +#define XScuGic_EnableIntr(DistBaseAddress, Int_Id) \ + XScuGic_WriteReg((DistBaseAddress), \ + XSCUGIC_ENABLE_SET_OFFSET + ((Int_Id / 32) * 4), \ + (1 << (Int_Id % 32))) + +/****************************************************************************/ +/** +* +* Disable specific interrupt(s) in the interrupt controller. +* +* @param DistBaseAddress is the Distributor Register base address of the +* device +* @param Int_Id is the ID of the interrupt source and should be in the +* range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1 +* +* +* @return None. +* +* @note C-style signature: +* void XScuGic_DisableIntr(u32 DistBaseAddress, u32 Int_Id); +* +*****************************************************************************/ +#define XScuGic_DisableIntr(DistBaseAddress, Int_Id) \ + XScuGic_WriteReg((DistBaseAddress), \ + XSCUGIC_DISABLE_OFFSET + ((Int_Id / 32) * 4), \ + (1 << (Int_Id % 32))) + + +/************************** Function Prototypes ******************************/ + +void XScuGic_DeviceInterruptHandler(void *DeviceId); +int XScuGic_DeviceInitialize(u32 DeviceId); +void XScuGic_RegisterHandler(u32 BaseAddress, int InterruptId, + Xil_InterruptHandler Handler, void *CallBackRef); +void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, + u8 Priority, u8 Trigger); +void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, + u8 *Priority, u8 *Trigger); +/************************** Variable Definitions *****************************/ +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xscutimer.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xscutimer.h new file mode 100644 index 000000000..1912b1061 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xscutimer.h @@ -0,0 +1,370 @@ +/****************************************************************************** +* +* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xscutimer.h +* +* The timer driver supports the Cortex A9 private timer. +* +* The timer driver supports the following features: +* - Normal mode and Auto reload mode +* - Interrupts (Interrupt handler is not provided in this driver. Application +* has to register it's own handler) +* +* Initialization and Configuration +* +* The device driver enables higher layer software (e.g., an application) to +* communicate with the Timer. +* +* XScuTimer_CfgInitialize() API is used to initialize the Timer. The +* user needs to first call the XScuTimer_LookupConfig() API which returns +* the Configuration structure pointer which is passed as a parameter to +* the XScuTimer_CfgInitialize() API. +* +* Interrupts +* +* The Timer hardware supports interrupts. +* +* This driver does not provide a Interrupt Service Routine (ISR) for the device. +* It is the responsibility of the application to provide one if needed. Refer to +* the interrupt example provided with this driver for details on using the +* Timer in interrupt mode. +* +* Virtual Memory +* +* This driver supports Virtual Memory. The RTOS is responsible for calculating +* the correct device base address in Virtual Memory space. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The XScuTimer driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +* +*

+* +* NOTE: +* The timer is not a part of the snoop control unit as indicated by the +* prefix "scu" in the name of the driver. +* It is an independent module in APU. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm  03/10/10 First release
+* 1.02a sg  07/17/12 Included xil_assert.h for CR 667947. This is an issue
+*		     when the xstatus.h in the common driver overwrites
+*		     the xstatus.h of the standalone BSP during the
+*		     libgen.
+*
+* +******************************************************************************/ +#ifndef XSCUTIMER_H /* prevent circular inclusions */ +#define XSCUTIMER_H /* by using protection macros */ + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xscutimer_hw.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddr; /**< Base address of the device */ +} XScuTimer_Config; + +/** + * The XScuTimer driver instance data. The user is required to allocate a + * variable of this type for every timer device in the system. + * A pointer to a variable of this type is then passed to the driver API + * functions. + */ +typedef struct { + XScuTimer_Config Config; /**< Hardware Configuration */ + u32 IsReady; /**< Device is initialized and ready */ + u32 IsStarted; /**< Device timer is running */ +} XScuTimer; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Check if the timer has expired. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return +* - TRUE if the timer has expired. +* - FALSE if the timer has not expired. +* +* @note C-style signature: +* int XScuTimer_IsExpired(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_IsExpired(InstancePtr) \ + ((XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_ISR_OFFSET) & \ + XSCUTIMER_ISR_EVENT_FLAG_MASK) == \ + XSCUTIMER_ISR_EVENT_FLAG_MASK) + +/****************************************************************************/ +/** +* +* Re-start the timer. This macro will read the timer load register +* and writes the same value to load register to update the counter register. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_RestartTimer(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_RestartTimer(InstancePtr) \ + XScuTimer_LoadTimer(InstancePtr, \ + XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_LOAD_OFFSET)) + +/****************************************************************************/ +/** +* +* Write to the timer load register. This will also update the +* timer counter register with the new value. This macro can be used to +* change the time-out value. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* @param Value is the count to be loaded in to the load register. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_LoadTimer(XScuTimer *InstancePtr, u32 Value) +* +******************************************************************************/ +#define XScuTimer_LoadTimer(InstancePtr, Value) \ + XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_LOAD_OFFSET, Value) + +/****************************************************************************/ +/** +* +* Returns the current timer counter register value. It can be called at any +* time. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return Contents of the timer counter register. +* +* @note C-style signature: + u32 XScuTimer_GetCounterValue(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_GetCounterValue(InstancePtr) \ + XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_COUNTER_OFFSET) + +/****************************************************************************/ +/** +* +* Enable auto-reload mode. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_EnableAutoReload(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_EnableAutoReload(InstancePtr) \ + XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET, \ + (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET) | \ + XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)) + +/****************************************************************************/ +/** +* +* Disable auto-reload mode. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_DisableAutoReload(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_DisableAutoReload(InstancePtr) \ + XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET, \ + (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET) & \ + ~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))) + +/****************************************************************************/ +/** +* +* Enable the Timer interrupt. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_EnableInterrupt(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_EnableInterrupt(InstancePtr) \ + XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET, \ + (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET) | \ + XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)) + +/****************************************************************************/ +/** +* +* Disable the Timer interrupt. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_DisableInterrupt(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_DisableInterrupt(InstancePtr) \ + XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET, \ + (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET) & \ + ~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))) + +/*****************************************************************************/ +/** +* +* This function reads the interrupt status. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_GetInterruptStatus(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_GetInterruptStatus(InstancePtr) \ + XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_ISR_OFFSET) + +/*****************************************************************************/ +/** +* +* This function clears the interrupt status. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_ClearInterruptStatus(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_ClearInterruptStatus(InstancePtr) \ + XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK) + +/************************** Function Prototypes ******************************/ + +/* + * Lookup configuration in xscutimer_sinit.c + */ +XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId); + +/* + * Selftest function in xscutimer_selftest.c + */ +int XScuTimer_SelfTest(XScuTimer *InstancePtr); + +/* + * Interface functions in xscutimer.c + */ +int XScuTimer_CfgInitialize(XScuTimer *InstancePtr, + XScuTimer_Config *ConfigPtr, u32 EffectiveAddress); +void XScuTimer_Start(XScuTimer *InstancePtr); +void XScuTimer_Stop(XScuTimer *InstancePtr); +void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue); +u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xscutimer_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xscutimer_hw.h new file mode 100644 index 000000000..d18cf6366 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xscutimer_hw.h @@ -0,0 +1,292 @@ +/****************************************************************************** +* +* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xscutimer_hw.h +* +* This file contains the hardware interface to the Timer. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm  03/10/10 First release
+* 1.01a sdm 02/02/12 Added low level macros to read/write load, counter, control
+*		     and interrupt registers
+* 1.02a  sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+*		     when the xstatus.h in the common driver overwrites
+*		     the xstatus.h of the standalone BSP during the
+*		     libgen.
+*
+* +******************************************************************************/ +#ifndef XSCUTIMER_HW_H /* prevent circular inclusions */ +#define XSCUTIMER_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_types.h" +#include "xil_io.h" +#include "xil_assert.h" +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * Offsets of registers from the start of the device + * @{ + */ + +#define XSCUTIMER_LOAD_OFFSET 0x00 /**< Timer Load Register */ +#define XSCUTIMER_COUNTER_OFFSET 0x04 /**< Timer Counter Register */ +#define XSCUTIMER_CONTROL_OFFSET 0x08 /**< Timer Control Register */ +#define XSCUTIMER_ISR_OFFSET 0x0C /**< Timer Interrupt + Status Register */ +/* @} */ + +/** @name Timer Control register + * This register bits control the prescaler, Intr enable, + * auto-reload and timer enable. + * @{ + */ + +#define XSCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00 /**< Prescaler */ +#define XSCUTIMER_CONTROL_PRESCALER_SHIFT 8 +#define XSCUTIMER_CONTROL_IRQ_ENABLE_MASK 0x00000004 /**< Intr enable */ +#define XSCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002 /**< Auto-reload */ +#define XSCUTIMER_CONTROL_ENABLE_MASK 0x00000001 /**< Timer enable */ +/* @} */ + +/** @name Interrupt Status register + * This register indicates the Timer counter register has reached zero. + * @{ + */ + +#define XSCUTIMER_ISR_EVENT_FLAG_MASK 0x00000001 /**< Event flag */ +/*@}*/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Write to the timer load register. This will also update the +* timer counter register with the new value. This macro can be used to +* change the time-out value. +* +* @param BaseAddr is the base address of the scu timer. +* @param Value is the count to be loaded in to the load register. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_SetLoadReg(u32 BaseAddr, u32 Value) +* +******************************************************************************/ +#define XScuTimer_SetLoadReg(BaseAddr, Value) \ + XScuTimer_WriteReg(BaseAddr, XSCUTIMER_LOAD_OFFSET, Value) + +/****************************************************************************/ +/** +* +* Returns the current timer load register value. +* +* @param BaseAddr is the base address of the scu timer. +* +* @return Contents of the timer load register. +* +* @note C-style signature: +* u32 XScuTimer_GetLoadReg(u32 BaseAddr) +* +******************************************************************************/ +#define XScuTimer_GetLoadReg(BaseAddr) \ + XScuTimer_ReadReg(BaseAddr, XSCUTIMER_LOAD_OFFSET) + +/****************************************************************************/ +/** +* +* Write to the timer counter register. +* +* @param BaseAddr is the base address of the scu timer. +* @param Value is the count to be loaded in to the counter register. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_SetCounterReg(u32 BaseAddr, u32 Value) +* +******************************************************************************/ +#define XScuTimer_SetCounterReg(BaseAddr, Value) \ + XScuTimer_WriteReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET, Value) + +/****************************************************************************/ +/** +* +* Returns the current timer counter register value. +* +* @param BaseAddr is the base address of the scu timer. +* +* @return Contents of the timer counter register. +* +* @note C-style signature: + u32 XScuTimer_GetCounterReg(u32 BaseAddr) +* +******************************************************************************/ +#define XScuTimer_GetCounterReg(BaseAddr) \ + XScuTimer_ReadReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET) + +/****************************************************************************/ +/** +* +* Write to the timer load register. This will also update the +* timer counter register with the new value. This macro can be used to +* change the time-out value. +* +* @param BaseAddr is the base address of the scu timer. +* @param Value is the count to be loaded in to the load register. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_SetControlReg(u32 BaseAddr, u32 Value) +* +******************************************************************************/ +#define XScuTimer_SetControlReg(BaseAddr, Value) \ + XScuTimer_WriteReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET, Value) + +/****************************************************************************/ +/** +* +* Returns the current timer load register value. +* +* @param BaseAddr is the base address of the scu timer. +* +* @return Contents of the timer load register. +* +* @note C-style signature: + u32 XScuTimer_GetControlReg(u32 BaseAddr) +* +******************************************************************************/ +#define XScuTimer_GetControlReg(BaseAddr) \ + XScuTimer_ReadReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET) + +/****************************************************************************/ +/** +* +* Write to the timer counter register. +* +* @param BaseAddr is the base address of the scu timer. +* @param Value is the count to be loaded in to the counter register. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_SetIntrReg(u32 BaseAddr, u32 Value) +* +******************************************************************************/ +#define XScuTimer_SetIntrReg(BaseAddr, Value) \ + XScuTimer_WriteReg(BaseAddr, XSCUTIMER_ISR_OFFSET, Value) + +/****************************************************************************/ +/** +* +* Returns the current timer counter register value. +* +* @param BaseAddr is the base address of the scu timer. +* +* @return Contents of the timer counter register. +* +* @note C-style signature: + u32 XScuTimer_GetIntrReg(u32 BaseAddr) +* +******************************************************************************/ +#define XScuTimer_GetIntrReg(BaseAddr) \ + XScuTimer_ReadReg(BaseAddr, XSCUTIMER_ISR_OFFSET) + +/****************************************************************************/ +/** +* +* Read from the given Timer register. +* +* @param BaseAddr is the base address of the device +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note C-style signature: +* u32 XScuTimer_ReadReg(u32 BaseAddr, u32 RegOffset) +* +*****************************************************************************/ +#define XScuTimer_ReadReg(BaseAddr, RegOffset) \ + Xil_In32((BaseAddr) + (RegOffset)) + +/****************************************************************************/ +/** +* +* Write to the given Timer register. +* +* @param BaseAddr is the base address of the device +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define XScuTimer_WriteReg(BaseAddr, RegOffset, Data) \ + Xil_Out32((BaseAddr) + (RegOffset), (Data)) + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xscuwdt.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xscuwdt.h new file mode 100644 index 000000000..6ed40d0df --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xscuwdt.h @@ -0,0 +1,389 @@ +/****************************************************************************** +* +* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xscuwdt.h +* +* The Xilinx SCU watchdog timer driver (XScuWdt) supports the Xilinx SCU private +* watchdog timer hardware. +* +* The XScuWdt driver supports the following features: +* - Watchdog mode +* - Timer mode +* - Auto reload (timer mode only) +* +* The watchdog counter register is a down counter and starts decrementing when +* the watchdog is started. +* In watchdog mode, when the counter reaches 0, the Reset flag is set in the +* Reset status register and the WDRESETREQ pin is asserted, causing a system +* reset. The Reset flag is not reset by normal processor reset and is cleared +* when written with a value of 1. This enables the user to differentiate a +* normal reset and a reset caused by watchdog time-out. The user needs to call +* XScuWdt_RestartWdt() periodically, to avoid the watchdog from being timed-out. +* +* The IsWdtExpired function can be used to check if the watchdog was the cause +* of the last reset. In this situation, call Initialize then call IsWdtExpired. +* If the result is true, watchdog timeout caused the last system reset. The +* application then needs to clear the Reset flag. +* +* In timer mode, when the counter reaches 0, the Event flag is set in the +* Interrupt status register and if interrupts are enabled, interrupt ID 30 is +* set as pending in the interrupt distributor. The IsTimerExpired function +* is used to check if the watchdog counter has decremented to 0 in timer mode. +* If auto-reload mode is enabled, the Counter register is automatically reloaded +* from the Load register. +* +* Initialization and Configuration +* +* The device driver enables higher layer software (e.g., an application) to +* communicate with the Watchdog Timer. +* +* XScuWdt_CfgInitialize() API is used to initialize the Watchdog Timer. The +* user needs to first call the XScuWdt_LookupConfig() API which returns +* the Configuration structure pointer which is passed as a parameter to +* the XScuWdt_CfgInitialize() API. +* +* Interrupts +* +* The SCU Watchdog Timer supports interrupts in Timer mode. +* +* This driver does not provide a Interrupt Service Routine (ISR) for the device. +* It is the responsibility of the application to provide one if needed. Refer to +* the interrupt example provided with this driver for details on using the +* Timer in interrupt mode. +* +* Virtual Memory +* +* This driver supports Virtual Memory. The RTOS is responsible for calculating +* the correct device base address in Virtual Memory space. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The XScuWdt driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +* +*

+* +* NOTE: +* The watchdog timer is not a part of the snoop control unit as indicated +* by the prefix "scu" in the name of the driver. +* It is an independent module in APU. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 1.02a  sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+*		     when the xstatus.h in the common driver overwrites
+*		     the xstatus.h of the standalone BSP during the
+*		     libgen.
+*
+* +******************************************************************************/ +#ifndef XSCUWDT_H /* prevent circular inclusions */ +#define XSCUWDT_H /* by using protection macros */ + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xscuwdt_hw.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddr; /**< Base address of the device */ +} XScuWdt_Config; + +/** + * The XScuWdt driver instance data. The user is required to allocate a + * variable of this type for every watchdog/timer device in the system. + * A pointer to a variable of this type is then passed to the driver API + * functions. + */ +typedef struct { + XScuWdt_Config Config;/**< Hardware Configuration */ + u32 IsReady; /**< Device is initialized and ready */ + u32 IsStarted; /**< Device watchdog timer is running */ +} XScuWdt; + +/***************** Macros (Inline Functions) Definitions *********************/ +/****************************************************************************/ +/** +* +* This function is used to check if the watchdog has timed-out and the last +* reset was caused by the watchdog reset. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* +* @return +* - TRUE if the watchdog has expired. +* - FALSE if the watchdog has not expired. +* +* @note C-style signature: +* int XScuWdt_IsWdtExpired(XScuWdt *InstancePtr) +* +******************************************************************************/ +#define XScuWdt_IsWdtExpired(InstancePtr) \ + ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_RST_STS_OFFSET) & \ + XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK) + +/****************************************************************************/ +/** +* +* This function is used to check if the watchdog counter has reached 0 in timer +* mode. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* +* @return +* - TRUE if the watchdog has expired. +* - FALSE if the watchdog has not expired. +* +* @note C-style signature: +* int XScuWdt_IsTimerExpired(XScuWdt *InstancePtr) +* +******************************************************************************/ +#define XScuWdt_IsTimerExpired(InstancePtr) \ + ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_ISR_OFFSET) & \ + XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK) + +/****************************************************************************/ +/** +* +* Re-start the watchdog timer. This macro will read the watchdog load register +* and write the same value to load register to update the counter register. +* An application needs to call this function periodically to keep the watchdog +* from asserting the WDRESETREQ reset request output pin. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* +* @return None. +* +* @note C-style signature: +* void XScuWdt_RestartWdt(XScuWdt *InstancePtr) +* +******************************************************************************/ +#define XScuWdt_RestartWdt(InstancePtr) \ + XScuWdt_LoadWdt(InstancePtr, \ + (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_LOAD_OFFSET))) + +/****************************************************************************/ +/** +* +* Write to the watchdog timer load register. This will also update the +* watchdog counter register with the new value. This macro can be used to +* change the time-out value. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* @param Value is the value to be written to the Watchdog Load register. +* +* @return None. +* +* @note C-style signature: +* void XScuWdt_LoadWdt(XScuWdt *InstancePtr, u32 Value) +* +******************************************************************************/ +#define XScuWdt_LoadWdt(InstancePtr, Value) \ + XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_LOAD_OFFSET, Value) + +/****************************************************************************/ +/** +* +* Put the watchdog timer in Watchdog mode by setting the WD mode bit of the +* Watchdog control register. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* +* @return None. +* +* @note C-style signature: +* void XScuWdt_SetWdMode(XScuWdt *InstancePtr) +* +******************************************************************************/ +#define XScuWdt_SetWdMode(InstancePtr) \ + XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_CONTROL_OFFSET, \ + (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_CONTROL_OFFSET) | \ + XSCUWDT_CONTROL_WD_MODE_MASK)) + +/****************************************************************************/ +/** +* +* Put the watchdog timer in Timer mode by writing 0x12345678 and 0x87654321 +* successively to the Watchdog Disable Register. +* The software must write 0x12345678 and 0x87654321 successively to the +* Watchdog Disable Register so that the watchdog mode bit in the Watchdog +* Control Register is set to zero. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* +* @return None. +* +* @note C-style signature: +* void XScuWdt_SetTimerMode(XScuWdt *InstancePtr) +* +******************************************************************************/ +#define XScuWdt_SetTimerMode(InstancePtr) \ +{ \ + XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_DISABLE_OFFSET, \ + XSCUWDT_DISABLE_VALUE1); \ + XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_DISABLE_OFFSET, \ + XSCUWDT_DISABLE_VALUE2); \ +} + +/****************************************************************************/ +/** +* +* Get the contents of the watchdog control register. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* +* @return Contents of the watchdog control register. +* +* @note C-style signature: + u32 XScuWdt_GetControlReg(XScuWdt *InstancePtr) +* +******************************************************************************/ +#define XScuWdt_GetControlReg(InstancePtr) \ + XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_CONTROL_OFFSET) + +/****************************************************************************/ +/** +* +* Write to the watchdog control register. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* @param ControlReg is the value to be written to the watchdog control +* register. +* +* @return None. +* +* @note C-style signature: + void XScuWdt_SetControlReg(XScuWdt *InstancePtr, u32 ControlReg) +* +******************************************************************************/ +#define XScuWdt_SetControlReg(InstancePtr, ControlReg) \ + XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_CONTROL_OFFSET, ControlReg) + +/****************************************************************************/ +/** +* +* Enable auto-reload mode. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* +* @return None. +* +* @note C-style signature: +* void XScuWdt_EnableAutoReload(XScuWdt *InstancePtr) +* +******************************************************************************/ +#define XScuWdt_EnableAutoReload(InstancePtr) \ + XScuWdt_SetControlReg((InstancePtr), \ + (XScuWdt_GetControlReg(InstancePtr) | \ + XSCUWDT_CONTROL_AUTO_RELOAD_MASK)) + +/************************** Function Prototypes ******************************/ + +/* + * Lookup configuration in xscuwdt_sinit.c. + */ +XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId); + +/* + * Selftest function in xscuwdt_selftest.c + */ +int XScuWdt_SelfTest(XScuWdt *InstancePtr); + +/* + * Interface functions in xscuwdt.c + */ +int XScuWdt_CfgInitialize(XScuWdt *InstancePtr, + XScuWdt_Config *ConfigPtr, u32 EffectiveAddress); + +void XScuWdt_Start(XScuWdt *InstancePtr); + +void XScuWdt_Stop(XScuWdt *InstancePtr); + +/* + * Self-test function in xwdttb_selftest.c. + */ +int XScuWdt_SelfTest(XScuWdt *InstancePtr); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xscuwdt_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xscuwdt_hw.h new file mode 100644 index 000000000..9bf23046d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xscuwdt_hw.h @@ -0,0 +1,187 @@ +/****************************************************************************** +* +* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xscuwdt_hw.h +* +* This file contains the hardware interface to the Xilinx SCU private Watch Dog +* Timer (XSCUWDT). +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 1.01a bss 02/27/12 Updated the register offsets to start at 0x0 instead
+*                    of 0x20 as the base address obtained from the tools
+*		     starts at 0x20.
+* 1.02a  sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+*		     when the xstatus.h in the common driver overwrites
+*		     the xstatus.h of the standalone BSP during the
+*		     libgen.
+*
+* +******************************************************************************/ +#ifndef XSCUWDT_HW_H /* prevent circular inclusions */ +#define XSCUWDT_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_io.h" +#include "xil_assert.h" +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * Offsets of registers from the start of the device. The WDT registers start at + * an offset 0x20 + * @{ + */ + +#define XSCUWDT_LOAD_OFFSET 0x00 /**< Watchdog Load Register */ +#define XSCUWDT_COUNTER_OFFSET 0x04 /**< Watchdog Counter Register */ +#define XSCUWDT_CONTROL_OFFSET 0x08 /**< Watchdog Control Register */ +#define XSCUWDT_ISR_OFFSET 0x0C /**< Watchdog Interrupt Status Register */ +#define XSCUWDT_RST_STS_OFFSET 0x10 /**< Watchdog Reset Status Register */ +#define XSCUWDT_DISABLE_OFFSET 0x14 /**< Watchdog Disable Register */ +/* @} */ + +/** @name Watchdog Control register + * This register bits control the prescaler, WD/Timer mode, Intr enable, + * auto-reload, watchdog enable. + * @{ + */ + +#define XSCUWDT_CONTROL_PRESCALER_MASK 0x0000FF00 /**< Prescaler */ +#define XSCUWDT_CONTROL_PRESCALER_SHIFT 8 +#define XSCUWDT_CONTROL_WD_MODE_MASK 0x00000008 /**< Watchdog/Timer mode */ +#define XSCUWDT_CONTROL_IT_ENABLE_MASK 0x00000004 /**< Intr enable (in + timer mode) */ +#define XSCUWDT_CONTROL_AUTO_RELOAD_MASK 0x00000002 /**< Auto-reload (in + timer mode) */ +#define XSCUWDT_CONTROL_WD_ENABLE_MASK 0x00000001 /**< Watchdog enable */ +/* @} */ + +/** @name Interrupt Status register + * This register indicates the Counter register has reached zero in Counter + * mode. + * @{ + */ + +#define XSCUWDT_ISR_EVENT_FLAG_MASK 0x00000001 /**< Event flag */ +/*@}*/ + +/** @name Reset Status register + * This register indicates the Counter register has reached zero in Watchdog + * mode and a reset request is sent. + * @{ + */ + +#define XSCUWDT_RST_STS_RESET_FLAG_MASK 0x00000001 /**< Time out occured */ +/*@}*/ + +/** @name Disable register + * This register is used to switch from watchdog mode to timer mode. + * The software must write 0x12345678 and 0x87654321 successively to the + * Watchdog Disable Register so that the watchdog mode bit in the Watchdog + * Control Register is set to zero. + * @{ + */ +#define XSCUWDT_DISABLE_VALUE1 0x12345678 /**< Watchdog mode disable + value 1 */ +#define XSCUWDT_DISABLE_VALUE2 0x87654321 /**< Watchdog mode disable + value 2 */ +/*@}*/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Read the given register. +* +* @param BaseAddr is the base address of the device +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note C-style signature: +* u32 XScuWdt_ReadReg(u32 BaseAddr, u32 RegOffset) +* +*****************************************************************************/ +#define XScuWdt_ReadReg(BaseAddr, RegOffset) \ + Xil_In32((BaseAddr) + (RegOffset)) + +/****************************************************************************/ +/** +* +* Write the given register. +* +* @param BaseAddr is the base address of the device +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note C-style signature: +* void XScuWdt_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define XScuWdt_WriteReg(BaseAddr, RegOffset, Data) \ + Xil_Out32((BaseAddr) + (RegOffset), (Data)) + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xsdps.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xsdps.h new file mode 100644 index 000000000..e9f3e2ecf --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xsdps.h @@ -0,0 +1,192 @@ +/****************************************************************************** +* +* (c) Copyright 2013-2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xsdps.h +* +* This file contains the implementation of XSdPs driver. +* This driver is used initialize read from and write to the SD card. +* Features such as switching bus width to 4-bit and switching to high speed, +* changing clock frequency, block size etc. are supported. +* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however +* is done using 1-bit bus width and 400KHz clock frequency. +* SD commands are classified as broadcast and addressed. Commands can be +* those with response only (using only command line) or +* response + data (using command and data lines). +* Only one command can be sent at a time. During a data transfer however, +* when dsta lines are in use, certain commands (which use only the command +* line) can be sent, most often to obtain status. +* This driver does not support multi card slots at present. +* +* Intialization: +* This includes initialization on the host controller side to select +* clock frequency, bus power and default transfer related parameters. +* The default voltage is 3.3V. +* On the SD card side, the initialization and identification state diagram is +* implemented. This resets the card, gives it a unique address/ID and +* identifies key card related specifications. +* +* Data transfer: +* The SD card is put in tranfer state to read from or write to it. +* The default block size is 512 bytes and if supported, +* default bus width is 4-bit and bus speed is High speed. +* The read and write functions are implemented in polled mode using ADMA2. +* +* At any point, when key parameters such as block size or +* clock/speed or bus width are modified, this driver takes care of +* maintaining the same selection on host and card. +* All error bits in host controller are monitored by the driver and in the +* event one of them is set, driver will clear the interrupt status and +* communicate failure to the upper layer. +* +* File system use: +* This driver can be used with xilffs library to read and write files to SD. +* (Please refer to procedure in diskio.c). The file system read/write example +* in polled mode can used for reference. +* +* There is no example for using SD driver without file system at present. +* However, the driver can be used without the file system. The glue layer +* in filesytem can be used as reference for the same. The block count +* passed to the read/write function in one call is limited by the ADMA2 +* descriptor table and hence care will have to be taken to call read/write +* API's in a loop for large file sizes. +* +* Interrupt mode is not supported because it offers no improvement when used +* with file system. +* +* eMMC support: +* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK. +* The features of eMMC supported by the driver will depend on those supported +* by the host controller. The current driver supports read/write on eMMC card +* using 4-bit and high speed mode currently. +* +* Features not supported include - card write protect, password setting, +* lock/unlock, interrupts, SDMA mode, programmed I/O mode and +* 64-bit addressed ADMA2, erase/pre-erase commands. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.0   hk      03/07/14 Version number revised.
+* 2.1   hk     04/18/14 Increase sleep for eMMC switch command.
+*                       Add sleep for microblaze designs. CR# 781117.
+*
+*
+* +******************************************************************************/ + + +#ifndef SDPS_H_ +#define SDPS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "xstatus.h" +#include "xsdps_hw.h" +#include + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Base address of the device */ + u32 InputClockHz; /**< Input clock frequency */ +} XSdPs_Config; + +/* + * ADMA2 descriptor table + */ +typedef struct { + u16 Attribute; /**< Attributes of descriptor */ + u16 Length; /**< Length of current dma transfer */ + u32 Address; /**< Address of current dma transfer */ +} XSdPs_Adma2Descriptor; + +/** + * The XSdPs driver instance data. The user is required to allocate a + * variable of this type for every SD device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XSdPs_Config Config; /**< Configuration structure */ + u32 IsReady; /**< Device is initialized and ready */ + u32 Host_Caps; /**< Capabilities of host controller */ + u32 HCS; /**< High capacity support in card */ + u32 CardID[4]; /**< Card ID */ + u32 RelCardAddr; /**< Relative Card Address */ + XSdPs_Adma2Descriptor Adma2_DescrTbl[32]; /**< ADMA Descriptors */ +} XSdPs; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ +XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId); +int XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr, + u32 EffectiveAddr); +int XSdPs_SdCardInitialize(XSdPs *InstancePtr); +int XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff); +int XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff); +int XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize); +int XSdPs_Select_Card (XSdPs *InstancePtr); +int XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq); +int XSdPs_Change_BusWidth(XSdPs *InstancePtr); +int XSdPs_Change_BusSpeed(XSdPs *InstancePtr); +int XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR); +int XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff); +int XSdPs_Pullup(XSdPs *InstancePtr); +int XSdPs_MmcCardInitialize(XSdPs *InstancePtr); +int XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff); + +#ifdef __cplusplus +} +#endif + +#endif /* SD_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xsdps_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xsdps_hw.h new file mode 100644 index 000000000..32ef073c4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xsdps_hw.h @@ -0,0 +1,614 @@ +/****************************************************************************** +* +* (c) Copyright 2013-2014 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xsdps_hw.h +* +* This header file contains the identifiers and basic HW access driver +* functions (or macros) that can be used to access the device. Other driver +* functions are defined in xsdps.h. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+*
+*
+* +******************************************************************************/ + +#ifndef SD_HW_H_ +#define SD_HW_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" +#include "xparameters.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * + * Register offsets from the base address of an SD device. + * @{ + */ + +#define XSDPS_SDMA_SYS_ADDR_OFFSET 0x00 /**< SDMA System Address + Register */ +#define XSDPS_BLK_SIZE_OFFSET 0x04 /**< Block Size Register */ +#define XSDPS_BLK_CNT_OFFSET 0x06 /**< Block Count Register */ +#define XSDPS_ARGMT_OFFSET 0x08 /**< Argument Register */ +#define XSDPS_XFER_MODE_OFFSET 0x0C /**< Transfer Mode Register */ +#define XSDPS_CMD_OFFSET 0x0E /**< Command Register */ +#define XSDPS_RESP0_OFFSET 0x10 /**< Response0 Register */ +#define XSDPS_RESP1_OFFSET 0x14 /**< Response1 Register */ +#define XSDPS_RESP2_OFFSET 0x18 /**< Response2 Register */ +#define XSDPS_RESP3_OFFSET 0x1C /**< Response3 Register */ +#define XSDPS_BUF_DAT_PORT_OFFSET 0x20 /**< Buffer Data Port */ +#define XSDPS_PRES_STATE_OFFSET 0x24 /**< Present State */ +#define XSDPS_HOST_CTRL1_OFFSET 0x28 /**< Host Control 1 */ +#define XSDPS_POWER_CTRL_OFFSET 0x29 /**< Power Control */ +#define XSDPS_BLK_GAP_CTRL_OFFSET 0x2A /**< Block Gap Control */ +#define XSDPS_WAKE_UP_CTRL_OFFSET 0x2B /**< Wake Up Control */ +#define XSDPS_CLK_CTRL_OFFSET 0x2C /**< Clock Control */ +#define XSDPS_TIMEOUT_CTRL_OFFSET 0x2E /**< Timeout Control */ +#define XSDPS_SW_RST_OFFSET 0x2F /**< Software Reset */ +#define XSDPS_NORM_INTR_STS_OFFSET 0x30 /**< Normal Interrupt + Status Register */ +#define XSDPS_ERR_INTR_STS_OFFSET 0x32 /**< Error Interrupt + Status Register */ +#define XSDPS_NORM_INTR_STS_EN_OFFSET 0x34 /**< Normal Interrupt + Status Enable Register */ +#define XSDPS_ERR_INTR_STS_EN_OFFSET 0x36 /**< Error Interrupt + Status Enable Register */ +#define XSDPS_NORM_INTR_SIG_EN_OFFSET 0x38 /**< Normal Interrupt + Signal Enable Register */ +#define XSDPS_ERR_INTR_SIG_EN_OFFSET 0x3A /**< Error Interrupt + Signal Enable Register */ + +#define XSDPS_AUTO_CMD12_ERR_STS_OFFSET 0x3C /**< Auto CMD12 Error Status + Register */ +#define XSDPS_HOST_CTRL2_OFFSET 0x3E /**< Host Control2 Register */ +#define XSDPS_CAPS_OFFSET 0x40 /**< Capabilities Register */ +#define XSDPS_CAPS_EXT_OFFSET 0x44 /**< Capabilities Extended */ +#define XSDPS_MAX_CURR_CAPS_OFFSET 0x48 /**< Maximum Current + Capabilities Register */ +#define XSDPS_MAX_CURR_CAPS_EXT_OFFSET 0x4C /**< Maximum Current + Capabilities Ext Register */ +#define XSDPS_FE_ERR_INT_STS_OFFSET 0x52 /**< Force Event for + Error Interrupt Status */ +#define XSDPS_FE_AUTO_CMD12_EIS_OFFSET 0x50 /**< Auto CM12 Error Interrupt + Status Register */ +#define XSDPS_ADMA_ERR_STS_OFFSET 0x54 /**< ADMA Error Status + Register */ +#define XSDPS_ADMA_SAR_OFFSET 0x58 /**< ADMA System Address + Register */ +#define XSDPS_ADMA_SAR_EXT_OFFSET 0x5C /**< ADMA System Address + Extended Register */ +#define XSDPS_PRE_VAL_1_OFFSET 0x60 /**< Preset Value Register */ +#define XSDPS_PRE_VAL_2_OFFSET 0x64 /**< Preset Value Register */ +#define XSDPS_PRE_VAL_3_OFFSET 0x68 /**< Preset Value Register */ +#define XSDPS_PRE_VAL_4_OFFSET 0x6C /**< Preset Value Register */ +#define XSDPS_SHARED_BUS_CTRL_OFFSET 0xE0 /**< Shared Bus Control + Register */ +#define XSDPS_SLOT_INTR_STS_OFFSET 0xFC /**< Slot Interrupt Status + Register */ +#define XSDPS_HOST_CTRL_VER_OFFSET 0xFE /**< Host Controller Version + Register */ + +/* @} */ + +/** @name Control Register - Host control, Power control, + * Block Gap control and Wakeup control + * + * This register contains bits for various configuration options of + * the SD host controller. Read/Write apart from the reserved bits. + * @{ + */ + +#define XSDPS_HC_LED_MASK 0x00000001 /**< LED Control */ +#define XSDPS_HC_WIDTH_MASK 0x00000002 /**< Bus width */ +#define XSDPS_HC_SPEED_MASK 0x00000004 /**< High Speed */ +#define XSDPS_HC_DMA_MASK 0x00000018 /**< DMA Mode Select */ +#define XSDPS_HC_DMA_SDMA_MASK 0x00000000 /**< SDMA Mode */ +#define XSDPS_HC_DMA_ADMA1_MASK 0x00000008 /**< ADMA1 Mode */ +#define XSDPS_HC_DMA_ADMA2_32_MASK 0x00000010 /**< ADMA2 Mode - 32 bit */ +#define XSDPS_HC_DMA_ADMA2_64_MASK 0x00000018 /**< ADMA2 Mode - 64 bit */ +#define XSDPS_HC_EXT_BUS_WIDTH 0x00000020 /**< Bus width - 8 bit */ +#define XSDPS_HC_CARD_DET_TL_MASK 0x00000040 /**< Card Detect Tst Lvl */ +#define XSDPS_HC_CARD_DET_SD_MASK 0x00000080 /**< Card Detect Sig Det */ + +#define XSDPS_PC_BUS_PWR_MASK 0x00000001 /**< Bus Power Control */ +#define XSDPS_PC_BUS_VSEL_MASK 0x0000000E /**< Bus Voltage Select */ +#define XSDPS_PC_BUS_VSEL_3V3_MASK 0x0000000E /**< Bus Voltage 3.3V */ +#define XSDPS_PC_BUS_VSEL_3V0_MASK 0x0000000C /**< Bus Voltage 3.0V */ +#define XSDPS_PC_BUS_VSEL_1V8_MASK 0x0000000A /**< Bus Voltage 1.8V */ + +#define XSDPS_BGC_STP_REQ_MASK 0x00000001 /**< Block Gap Stop Req */ +#define XSDPS_BGC_CNT_REQ_MASK 0x00000002 /**< Block Gap Cont Req */ +#define XSDPS_BGC_RWC_MASK 0x00000004 /**< Block Gap Rd Wait */ +#define XSDPS_BGC_INTR_MASK 0x00000008 /**< Block Gap Intr */ +#define XSDPS_BGC_SPI_MODE_MASK 0x00000010 /**< Block Gap SPI Mode */ +#define XSDPS_BGC_BOOT_EN_MASK 0x00000020 /**< Block Gap Boot Enb */ +#define XSDPS_BGC_ALT_BOOT_EN_MASK 0x00000040 /**< Block Gap Alt BootEn */ +#define XSDPS_BGC_BOOT_ACK_MASK 0x00000080 /**< Block Gap Boot Ack */ + +#define XSDPS_WC_WUP_ON_INTR_MASK 0x00000001 /**< Wakeup Card Intr */ +#define XSDPS_WC_WUP_ON_INSRT_MASK 0x00000002 /**< Wakeup Card Insert */ +#define XSDPS_WC_WUP_ON_REM_MASK 0x00000004 /**< Wakeup Card Removal */ + +/* @} */ + +/** @name Control Register - Clock control, Timeout control & Software reset + * + * This register contains bits for configuration options of clock, timeout and + * software reset. + * Read/Write except for Inter_Clock_Stable bit (read only) and reserved bits. + * @{ + */ + +#define XSDPS_CC_INT_CLK_EN_MASK 0x00000001 +#define XSDPS_CC_INT_CLK_STABLE_MASK 0x00000002 +#define XSDPS_CC_SD_CLK_EN_MASK 0x00000004 +#define XSDPS_CC_SD_CLK_GEN_SEL_MASK 0x00000020 +#define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK 0x000000C0 +#define XSDPS_CC_SDCLK_FREQ_SEL_MASK 0x0000FF00 +#define XSDPS_CC_SDCLK_FREQ_D256_MASK 0x00008000 +#define XSDPS_CC_SDCLK_FREQ_D128_MASK 0x00004000 +#define XSDPS_CC_SDCLK_FREQ_D64_MASK 0x00002000 +#define XSDPS_CC_SDCLK_FREQ_D32_MASK 0x00001000 +#define XSDPS_CC_SDCLK_FREQ_D16_MASK 0x00000800 +#define XSDPS_CC_SDCLK_FREQ_D8_MASK 0x00000400 +#define XSDPS_CC_SDCLK_FREQ_D4_MASK 0x00000200 +#define XSDPS_CC_SDCLK_FREQ_D2_MASK 0x00000100 +#define XSDPS_CC_SDCLK_FREQ_BASE_MASK 0x00000000 + +#define XSDPS_TC_CNTR_VAL_MASK 0x0000000F + +#define XSDPS_SWRST_ALL_MASK 0x00000001 +#define XSDPS_SWRST_CMD_LINE_MASK 0x00000002 +#define XSDPS_SWRST_DAT_LINE_MASK 0x00000004 + +#define XSDPS_CC_MAX_NUM_OF_DIV 9 +#define XSDPS_CC_DIV_SHIFT 8 + +/* @} */ + +/** @name SD Interrupt Registers + * + * Normal and Error Interrupt Status Register + * This register shows the normal and error interrupt status. + * Status enable register affects reads of this register. + * If Signal enable register is set and the corresponding status bit is set, + * interrupt is generated. + * Write to clear except + * Error_interrupt and Card_Interrupt bits - Read only + * + * Normal and Error Interrupt Status Enable Register + * Setting this register bits enables Interrupt status. + * Read/Write except Fixed_to_0 bit (Read only) + * + * Normal and Error Interrupt Signal Enable Register + * This register is used to select which interrupt status is + * indicated to the Host System as the interrupt. + * Read/Write except Fixed_to_0 bit (Read only) + * + * All three registers have same bit definitions + * @{ + */ + +#define XSDPS_INTR_CC_MASK 0x00000001 /**< Command Complete */ +#define XSDPS_INTR_TC_MASK 0x00000002 /**< Transfer Complete */ +#define XSDPS_INTR_BGE_MASK 0x00000004 /**< Block Gap Event */ +#define XSDPS_INTR_DMA_MASK 0x00000008 /**< DMA Interrupt */ +#define XSDPS_INTR_BWR_MASK 0x00000010 /**< Buffer Write Ready */ +#define XSDPS_INTR_BRR_MASK 0x00000020 /**< Buffer Read Ready */ +#define XSDPS_INTR_CARD_INSRT_MASK 0x00000040 /**< Card Insert */ +#define XSDPS_INTR_CARD_REM_MASK 0x00000080 /**< Card Remove */ +#define XSDPS_INTR_CARD_MASK 0x00000100 /**< Card Interrupt */ +#define XSDPS_INTR_INT_A_MASK 0x00000200 /**< INT A Interrupt */ +#define XSDPS_INTR_INT_B_MASK 0x00000400 /**< INT B Interrupt */ +#define XSDPS_INTR_INT_C_MASK 0x00000800 /**< INT C Interrupt */ +#define XSDPS_INTR_RE_TUNING_MASK 0x00001000 /**< Re-Tuning Interrupt */ +#define XSDPS_INTR_BOOT_TERM_MASK 0x00002000 /**< Boot Terminate + Interrupt */ +#define XSDPS_INTR_BOOT_ACK_RECV_MASK 0x00004000 /**< Boot Ack Recv + Interrupt */ +#define XSDPS_INTR_ERR_MASK 0x00008000 /**< Error Interrupt */ +#define XSDPS_NORM_INTR_ALL_MASK 0x0000FFFF + +#define XSDPS_INTR_ERR_CT_MASK 0x00000001 /**< Command Timeout + Error */ +#define XSDPS_INTR_ERR_CCRC_MASK 0x00000002 /**< Command CRC Error */ +#define XSDPS_INTR_ERR_CEB_MASK 0x00000004 /**< Command End Bit + Error */ +#define XSDPS_INTR_ERR_CI_MASK 0x00000008 /**< Command Index Error */ +#define XSDPS_INTR_ERR_DT_MASK 0x00000010 /**< Data Timeout Error */ +#define XSDPS_INTR_ERR_DCRC_MASK 0x00000020 /**< Data CRC Error */ +#define XSDPS_INTR_ERR_DEB_MASK 0x00000040 /**< Data End Bit Error */ +#define XSDPS_INTR_ERR_I_LMT_MASK 0x00000080 /**< Current Limit Error */ +#define XSDPS_INTR_ERR_AUTO_CMD12_MASK 0x00000100 /**< Auto CMD12 Error */ +#define XSDPS_INTR_ERR_ADMA_MASK 0x00000200 /**< ADMA Error */ +#define XSDPS_INTR_ERR_TR_MASK 0x00001000 /**< Tuning Error */ +#define XSDPS_INTR_VEND_SPF_ERR_MASK 0x0000E000 /**< Vendor Specific + Error */ +#define XSDPS_ERROR_INTR_ALL_MASK 0x0000F3FF /**< Mask for error bits */ +/* @} */ + +/** @name Block Size and Block Count Register + * + * This register contains the block count for current transfer, + * block size and SDMA buffer size. + * Read/Write except for reserved bits. + * @{ + */ + +#define XSDPS_BLK_SIZE_MASK 0x00000FFF /**< Transfer Block Size */ +#define XSDPS_SDMA_BUFF_SIZE_MASK 0x00007000 /**< Host SDMA Buffer Size */ +#define XSDPS_BLK_CNT_MASK 0x0000FFFF /**< Block Count for + Current Transfer */ + +/* @} */ + +/** @name Transfer Mode and Command Register + * + * The Transfer Mode register is used to control the data transfers and + * Command register is used for command generation + * Read/Write except for reserved bits. + * @{ + */ + +#define XSDPS_TM_DMA_EN_MASK 0x00000001 /**< DMA Enable */ +#define XSDPS_TM_BLK_CNT_EN_MASK 0x00000002 /**< Block Count Enable */ +#define XSDPS_TM_AUTO_CMD12_EN_MASK 0x00000004 /**< Auto CMD12 Enable */ +#define XSDPS_TM_DAT_DIR_SEL_MASK 0x00000010 /**< Data Transfer + Direction Select */ +#define XSDPS_TM_MUL_SIN_BLK_SEL_MASK 0x00000020 /**< Multi/Single + Block Select */ + +#define XSDPS_CMD_RESP_SEL_MASK 0x00000003 /**< Response Type + Select */ +#define XSDPS_CMD_RESP_NONE_MASK 0x00000000 /**< No Response */ +#define XSDPS_CMD_RESP_L136_MASK 0x00000001 /**< Response length 138 */ +#define XSDPS_CMD_RESP_L48_MASK 0x00000002 /**< Response length 48 */ +#define XSDPS_CMD_RESP_L48_BSY_CHK_MASK 0x00000003 /**< Response length 48 & + check busy after + response */ +#define XSDPS_CMD_CRC_CHK_EN_MASK 0x00000008 /**< Command CRC Check + Enable */ +#define XSDPS_CMD_INX_CHK_EN_MASK 0x00000010 /**< Command Index Check + Enable */ +#define XSDPS_DAT_PRESENT_SEL_MASK 0x00000020 /**< Data Present Select */ +#define XSDPS_CMD_TYPE_MASK 0x000000C0 /**< Command Type */ +#define XSDPS_CMD_TYPE_NORM_MASK 0x00000000 /**< CMD Type - Normal */ +#define XSDPS_CMD_TYPE_SUSPEND_MASK 0x00000040 /**< CMD Type - Suspend */ +#define XSDPS_CMD_TYPE_RESUME_MASK 0x00000080 /**< CMD Type - Resume */ +#define XSDPS_CMD_TYPE_ABORT_MASK 0x000000C0 /**< CMD Type - Abort */ +#define XSDPS_CMD_MASK 0x00003F00 /**< Command Index Mask - + Set to CMD0-63, + AMCD0-63 */ + +/* @} */ + +/** @name Capabilities Register + * + * Capabilities register is a read only register which contains + * information about the host controller. + * Sufficient if read once after power on. + * Read Only + * @{ + */ +#define XSDPS_CAP_TOUT_CLK_FREQ_MASK 0x0000003F /**< Timeout clock freq + select */ +#define XSDPS_CAP_TOUT_CLK_UNIT_MASK 0x00000080 /**< Timeout clock unit - + MHz/KHz */ +#define XSDPS_CAP_MAX_BLK_LEN_MASK 0x00030000 /**< Max block length */ +#define XSDPS_CAP_MAX_BLK_LEN_512B_MASK 0x00000000 /**< Max block 512 bytes */ +#define XSDPS_CAP_EXT_MEDIA_BUS_MASK 0x00040000 /**< Extended media bus */ +#define XSDPS_CAP_ADMA2_MASK 0x00080000 /**< ADMA2 support */ +#define XSDPS_CAP_HIGH_SPEED_MASK 0x00200000 /**< High speed support */ +#define XSDPS_CAP_SDMA_MASK 0x00400000 /**< SDMA support */ +#define XSDPS_CAP_SUSP_RESUME_MASK 0x00800000 /**< Suspend/Resume + support */ +#define XSDPS_CAP_VOLT_3V3_MASK 0x01000000 /**< 3.3V support */ +#define XSDPS_CAP_VOLT_3V0_MASK 0x02000000 /**< 3.0V support */ +#define XSDPS_CAP_VOLT_1V8_MASK 0x04000000 /**< 1.8V support */ +#define XSDPS_CAP_INTR_MODE_MASK 0x08000000 /**< Interrupt mode + support */ +#define XSDPS_CAP_SYS_BUS_64_MASK 0x10000000 /**< 64 bit system bus + support */ +#define XSDPS_CAP_SPI_MODE_MASK 0x20000000 /**< SPI mode */ +#define XSDPS_CAP_SPI_BLOCK_MODE_MASK 0x20000000 /**< SPI block mode */ +/* @} */ + +/** @name Present State Register + * + * Gives the current status of the host controller + * Read Only + * @{ + */ + +#define XSDPS_PSR_INHIBIT_CMD_MASK 0x00000001 /**< Command inhibit - CMD */ +#define XSDPS_PSR_INHIBIT_DAT_MASK 0x00000002 /**< Command Inhibit - DAT */ +#define XSDPS_PSR_DAT_ACTIVE_MASK 0x00000004 /**< DAT line active */ +#define XSDPS_PSR_WR_ACTIVE_MASK 0x00000100 /**< Write transfer active */ +#define XSDPS_PSR_RD_ACTIVE_MASK 0x00000200 /**< Read transfer active */ +#define XSDPS_PSR_BUFF_WR_EN_MASK 0x00000400 /**< Buffer write enable */ +#define XSDPS_PSR_BUFF_RD_EN_MASK 0x00000800 /**< Buffer read enable */ +#define XSDPS_PSR_CARD_INSRT_MASK 0x00010000 /**< Card inserted */ +#define XSDPS_PSR_CARD_STABLE_MASK 0x00020000 /**< Card state stable */ +#define XSDPS_PSR_CARD_DPL_MASK 0x00040000 /**< Card detect pin level */ +#define XSDPS_PSR_WPS_PL_MASK 0x00080000 /**< Write protect switch + pin level */ + +/* @} */ + +/** @name Block size mask for 512 bytes + * + * Block size mask for 512 bytes - This is the default block size. + * @{ + */ + +#define XSDPS_BLK_SIZE_512_MASK 0x200 + +/* @} */ + +/** @name Commands + * + * Constant definitions for commands and response related to SD + * @{ + */ + +#define XSDPS_APP_CMD_PREFIX 0x8000 +#define CMD0 0x0000 +#define CMD1 0x0100 +#define CMD2 0x0200 +#define CMD3 0x0300 +#define CMD4 0x0400 +#define CMD5 0x0500 +#define CMD6 0x0600 +#define ACMD6 (XSDPS_APP_CMD_PREFIX + 0x0600) +#define CMD7 0x0700 +#define CMD8 0x0800 +#define CMD9 0x0900 +#define CMD10 0x0A00 +#define CMD12 0x0C00 +#define ACMD13 (XSDPS_APP_CMD_PREFIX + 0x0D00) +#define CMD16 0x1000 +#define CMD17 0x1100 +#define CMD18 0x1200 +#define CMD23 0x1700 +#define ACMD23 (XSDPS_APP_CMD_PREFIX + 0x1700) +#define CMD24 0x1800 +#define CMD25 0x1900 +#define CMD41 0x2900 +#define ACMD41 (XSDPS_APP_CMD_PREFIX + 0x2900) +#define ACMD42 (XSDPS_APP_CMD_PREFIX + 0x2A00) +#define ACMD51 (XSDPS_APP_CMD_PREFIX + 0x3300) +#define CMD52 0x3400 +#define CMD55 0x3700 +#define CMD58 0x3A00 + +#define RESP_NONE XSDPS_CMD_RESP_NONE_MASK +#define RESP_R1 XSDPS_CMD_RESP_L48_MASK | XSDPS_CMD_CRC_CHK_EN_MASK | \ + XSDPS_CMD_INX_CHK_EN_MASK + +#define RESP_R1B XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \ + XSDPS_CMD_CRC_CHK_EN_MASK | XSDPS_CMD_INX_CHK_EN_MASK + +#define RESP_R2 XSDPS_CMD_RESP_L136_MASK | XSDPS_CMD_CRC_CHK_EN_MASK +#define RESP_R3 XSDPS_CMD_RESP_L48_MASK + +#define RESP_R6 XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \ + XSDPS_CMD_CRC_CHK_EN_MASK | XSDPS_CMD_INX_CHK_EN_MASK + +/* @} */ + +/** @name ADMA2 Descriptor related definitions + * + * ADMA2 Descriptor related definitions + * @{ + */ + +#define XSDPS_DESC_MAX_LENGTH 65536 + +#define XSDPS_DESC_VALID (0x1 << 0) +#define XSDPS_DESC_END (0x1 << 1) +#define XSDPS_DESC_INT (0x1 << 2) +#define XSDPS_DESC_TRAN (0x2 << 4) + +/* @} */ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +#define XSdPs_In32 Xil_In32 +#define XSdPs_Out32 Xil_Out32 + +#define XSdPs_In16 Xil_In16 +#define XSdPs_Out16 Xil_Out16 + +#define XSdPs_In8 Xil_In8 +#define XSdPs_Out8 Xil_Out8 + +/****************************************************************************/ +/** +* Read a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to the target register. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset) +* +******************************************************************************/ +#define XSdPs_ReadReg(BaseAddress, RegOffset) \ + XSdPs_In32((BaseAddress) + (RegOffset)) + +/***************************************************************************/ +/** +* Write to a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to target register. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset, +* u32 RegisterValue) +* +******************************************************************************/ +#define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ + XSdPs_Out32((BaseAddress) + (RegOffset), (RegisterValue)) + +/****************************************************************************/ +/** +* Read a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to the target register. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset) +* +******************************************************************************/ +#define XSdPs_ReadReg16(BaseAddress, RegOffset) \ + XSdPs_In16((BaseAddress) + (RegOffset)) + +/***************************************************************************/ +/** +* Write to a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to target register. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset, +* u16 RegisterValue) +* +******************************************************************************/ +#define XSdPs_WriteReg16(BaseAddress, RegOffset, RegisterValue) \ + XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue)) + +/****************************************************************************/ +/** +* Read a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to the target register. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset) +* +******************************************************************************/ +#define XSdPs_ReadReg8(BaseAddress, RegOffset) \ + XSdPs_In8((BaseAddress) + (RegOffset)) + +/***************************************************************************/ +/** +* Write to a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to target register. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset, +* u8 RegisterValue) +* +******************************************************************************/ +#define XSdPs_WriteReg8(BaseAddress, RegOffset, RegisterValue) \ + XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue)) + +/***************************************************************************/ +/** +* Macro to get present status register +* +* @param BaseAddress contains the base address of the device. +* +* @return None. +* +* @note C-Style signature: +* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset, +* u8 RegisterValue) +* +******************************************************************************/ +#define XSdPs_GetPresentStatusReg(BaseAddress) \ + XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET)) + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* SD_HW_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xstatus.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xstatus.h new file mode 100644 index 000000000..76d2a94c7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xstatus.h @@ -0,0 +1,439 @@ +/****************************************************************************** +* +* (c) Copyright 2002-2013 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xstatus.h +* +* This file contains Xilinx software status codes. Status codes have their +* own data type called int. These codes are used throughout the Xilinx +* device drivers. +* +******************************************************************************/ + +#ifndef XSTATUS_H /* prevent circular inclusions */ +#define XSTATUS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" + +/************************** Constant Definitions *****************************/ + +/*********************** Common statuses 0 - 500 *****************************/ + +#define XST_SUCCESS 0L +#define XST_FAILURE 1L +#define XST_DEVICE_NOT_FOUND 2L +#define XST_DEVICE_BLOCK_NOT_FOUND 3L +#define XST_INVALID_VERSION 4L +#define XST_DEVICE_IS_STARTED 5L +#define XST_DEVICE_IS_STOPPED 6L +#define XST_FIFO_ERROR 7L /* an error occurred during an + operation with a FIFO such as + an underrun or overrun, this + error requires the device to + be reset */ +#define XST_RESET_ERROR 8L /* an error occurred which requires + the device to be reset */ +#define XST_DMA_ERROR 9L /* a DMA error occurred, this error + typically requires the device + using the DMA to be reset */ +#define XST_NOT_POLLED 10L /* the device is not configured for + polled mode operation */ +#define XST_FIFO_NO_ROOM 11L /* a FIFO did not have room to put + the specified data into */ +#define XST_BUFFER_TOO_SMALL 12L /* the buffer is not large enough + to hold the expected data */ +#define XST_NO_DATA 13L /* there was no data available */ +#define XST_REGISTER_ERROR 14L /* a register did not contain the + expected value */ +#define XST_INVALID_PARAM 15L /* an invalid parameter was passed + into the function */ +#define XST_NOT_SGDMA 16L /* the device is not configured for + scatter-gather DMA operation */ +#define XST_LOOPBACK_ERROR 17L /* a loopback test failed */ +#define XST_NO_CALLBACK 18L /* a callback has not yet been + registered */ +#define XST_NO_FEATURE 19L /* device is not configured with + the requested feature */ +#define XST_NOT_INTERRUPT 20L /* device is not configured for + interrupt mode operation */ +#define XST_DEVICE_BUSY 21L /* device is busy */ +#define XST_ERROR_COUNT_MAX 22L /* the error counters of a device + have maxed out */ +#define XST_IS_STARTED 23L /* used when part of device is + already started i.e. + sub channel */ +#define XST_IS_STOPPED 24L /* used when part of device is + already stopped i.e. + sub channel */ +#define XST_DATA_LOST 26L /* driver defined error */ +#define XST_RECV_ERROR 27L /* generic receive error */ +#define XST_SEND_ERROR 28L /* generic transmit error */ +#define XST_NOT_ENABLED 29L /* a requested service is not + available because it has not + been enabled */ + +/***************** Utility Component statuses 401 - 500 *********************/ + +#define XST_MEMTEST_FAILED 401L /* memory test failed */ + + +/***************** Common Components statuses 501 - 1000 *********************/ + +/********************* Packet Fifo statuses 501 - 510 ************************/ + +#define XST_PFIFO_LACK_OF_DATA 501L /* not enough data in FIFO */ +#define XST_PFIFO_NO_ROOM 502L /* not enough room in FIFO */ +#define XST_PFIFO_BAD_REG_VALUE 503L /* self test, a register value + was invalid after reset */ +#define XST_PFIFO_ERROR 504L /* generic packet FIFO error */ +#define XST_PFIFO_DEADLOCK 505L /* packet FIFO is reporting + * empty and full simultaneously + */ + +/************************** DMA statuses 511 - 530 ***************************/ + +#define XST_DMA_TRANSFER_ERROR 511L /* self test, DMA transfer + failed */ +#define XST_DMA_RESET_REGISTER_ERROR 512L /* self test, a register value + was invalid after reset */ +#define XST_DMA_SG_LIST_EMPTY 513L /* scatter gather list contains + no buffer descriptors ready + to be processed */ +#define XST_DMA_SG_IS_STARTED 514L /* scatter gather not stopped */ +#define XST_DMA_SG_IS_STOPPED 515L /* scatter gather not running */ +#define XST_DMA_SG_LIST_FULL 517L /* all the buffer desciptors of + the scatter gather list are + being used */ +#define XST_DMA_SG_BD_LOCKED 518L /* the scatter gather buffer + descriptor which is to be + copied over in the scatter + list is locked */ +#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /* no buffer descriptors have been + put into the scatter gather + list to be commited */ +#define XST_DMA_SG_COUNT_EXCEEDED 521L /* the packet count threshold + specified was larger than the + total # of buffer descriptors + in the scatter gather list */ +#define XST_DMA_SG_LIST_EXISTS 522L /* the scatter gather list has + already been created */ +#define XST_DMA_SG_NO_LIST 523L /* no scatter gather list has + been created */ +#define XST_DMA_SG_BD_NOT_COMMITTED 524L /* the buffer descriptor which was + being started was not committed + to the list */ +#define XST_DMA_SG_NO_DATA 525L /* the buffer descriptor to start + has already been used by the + hardware so it can't be reused + */ +#define XST_DMA_SG_LIST_ERROR 526L /* general purpose list access + error */ +#define XST_DMA_BD_ERROR 527L /* general buffer descriptor + error */ + +/************************** IPIF statuses 531 - 550 ***************************/ + +#define XST_IPIF_REG_WIDTH_ERROR 531L /* an invalid register width + was passed into the function */ +#define XST_IPIF_RESET_REGISTER_ERROR 532L /* the value of a register at + reset was not valid */ +#define XST_IPIF_DEVICE_STATUS_ERROR 533L /* a write to the device interrupt + status register did not read + back correctly */ +#define XST_IPIF_DEVICE_ACK_ERROR 534L /* the device interrupt status + register did not reset when + acked */ +#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /* the device interrupt enable + register was not updated when + other registers changed */ +#define XST_IPIF_IP_STATUS_ERROR 536L /* a write to the IP interrupt + status register did not read + back correctly */ +#define XST_IPIF_IP_ACK_ERROR 537L /* the IP interrupt status register + did not reset when acked */ +#define XST_IPIF_IP_ENABLE_ERROR 538L /* IP interrupt enable register was + not updated correctly when other + registers changed */ +#define XST_IPIF_DEVICE_PENDING_ERROR 539L /* The device interrupt pending + register did not indicate the + expected value */ +#define XST_IPIF_DEVICE_ID_ERROR 540L /* The device interrupt ID register + did not indicate the expected + value */ +#define XST_IPIF_ERROR 541L /* generic ipif error */ + +/****************** Device specific statuses 1001 - 4095 *********************/ + +/********************* Ethernet statuses 1001 - 1050 *************************/ + +#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /* Memory space is not big enough + * to hold the minimum number of + * buffers or descriptors */ +#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /* Memory allocation failed */ +#define XST_EMAC_MII_READ_ERROR 1003L /* MII read error */ +#define XST_EMAC_MII_BUSY 1004L /* An MII operation is in progress */ +#define XST_EMAC_OUT_OF_BUFFERS 1005L /* Driver is out of buffers */ +#define XST_EMAC_PARSE_ERROR 1006L /* Invalid driver init string */ +#define XST_EMAC_COLLISION_ERROR 1007L /* Excess deferral or late + * collision on polled send */ + +/*********************** UART statuses 1051 - 1075 ***************************/ +#define XST_UART + +#define XST_UART_INIT_ERROR 1051L +#define XST_UART_START_ERROR 1052L +#define XST_UART_CONFIG_ERROR 1053L +#define XST_UART_TEST_FAIL 1054L +#define XST_UART_BAUD_ERROR 1055L +#define XST_UART_BAUD_RANGE 1056L + + +/************************ IIC statuses 1076 - 1100 ***************************/ + +#define XST_IIC_SELFTEST_FAILED 1076 /* self test failed */ +#define XST_IIC_BUS_BUSY 1077 /* bus found busy */ +#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /* mastersend attempted with */ + /* general call address */ +#define XST_IIC_STAND_REG_RESET_ERROR 1079 /* A non parameterizable reg */ + /* value after reset not valid */ +#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /* Tx fifo included in design */ + /* value after reset not valid */ +#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /* Rx fifo included in design */ + /* value after reset not valid */ +#define XST_IIC_TBA_REG_RESET_ERROR 1082 /* 10 bit addr incl in design */ + /* value after reset not valid */ +#define XST_IIC_CR_READBACK_ERROR 1083 /* Read of the control register */ + /* didn't return value written */ +#define XST_IIC_DTR_READBACK_ERROR 1084 /* Read of the data Tx reg */ + /* didn't return value written */ +#define XST_IIC_DRR_READBACK_ERROR 1085 /* Read of the data Receive reg */ + /* didn't return value written */ +#define XST_IIC_ADR_READBACK_ERROR 1086 /* Read of the data Tx reg */ + /* didn't return value written */ +#define XST_IIC_TBA_READBACK_ERROR 1087 /* Read of the 10 bit addr reg */ + /* didn't return written value */ +#define XST_IIC_NOT_SLAVE 1088 /* The device isn't a slave */ + +/*********************** ATMC statuses 1101 - 1125 ***************************/ + +#define XST_ATMC_ERROR_COUNT_MAX 1101L /* the error counters in the ATM + controller hit the max value + which requires the statistics + to be cleared */ + +/*********************** Flash statuses 1126 - 1150 **************************/ + +#define XST_FLASH_BUSY 1126L /* Flash is erasing or programming + */ +#define XST_FLASH_READY 1127L /* Flash is ready for commands */ +#define XST_FLASH_ERROR 1128L /* Flash had detected an internal + error. Use XFlash_DeviceControl + to retrieve device specific codes + */ +#define XST_FLASH_ERASE_SUSPENDED 1129L /* Flash is in suspended erase state + */ +#define XST_FLASH_WRITE_SUSPENDED 1130L /* Flash is in suspended write state + */ +#define XST_FLASH_PART_NOT_SUPPORTED 1131L /* Flash type not supported by + driver */ +#define XST_FLASH_NOT_SUPPORTED 1132L /* Operation not supported */ +#define XST_FLASH_TOO_MANY_REGIONS 1133L /* Too many erase regions */ +#define XST_FLASH_TIMEOUT_ERROR 1134L /* Programming or erase operation + aborted due to a timeout */ +#define XST_FLASH_ADDRESS_ERROR 1135L /* Accessed flash outside its + addressible range */ +#define XST_FLASH_ALIGNMENT_ERROR 1136L /* Write alignment error */ +#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /* Couldn't return immediately from + write/erase function with + XFL_NON_BLOCKING_WRITE/ERASE + option cleared */ +#define XST_FLASH_CFI_QUERY_ERROR 1138L /* Failed to query the device */ + +/*********************** SPI statuses 1151 - 1175 ****************************/ + +#define XST_SPI_MODE_FAULT 1151 /* master was selected as slave */ +#define XST_SPI_TRANSFER_DONE 1152 /* data transfer is complete */ +#define XST_SPI_TRANSMIT_UNDERRUN 1153 /* slave underruns transmit register */ +#define XST_SPI_RECEIVE_OVERRUN 1154 /* device overruns receive register */ +#define XST_SPI_NO_SLAVE 1155 /* no slave has been selected yet */ +#define XST_SPI_TOO_MANY_SLAVES 1156 /* more than one slave is being + * selected */ +#define XST_SPI_NOT_MASTER 1157 /* operation is valid only as master */ +#define XST_SPI_SLAVE_ONLY 1158 /* device is configured as slave-only + */ +#define XST_SPI_SLAVE_MODE_FAULT 1159 /* slave was selected while disabled */ +#define XST_SPI_SLAVE_MODE 1160 /* device has been addressed as slave */ +#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /* device received data in slave mode */ + +#define XST_SPI_COMMAND_ERROR 1162 /* unrecognised command - qspi only */ + +/********************** OPB Arbiter statuses 1176 - 1200 *********************/ + +#define XST_OPBARB_INVALID_PRIORITY 1176 /* the priority registers have either + * one master assigned to two or more + * priorities, or one master not + * assigned to any priority + */ +#define XST_OPBARB_NOT_SUSPENDED 1177 /* an attempt was made to modify the + * priority levels without first + * suspending the use of priority + * levels + */ +#define XST_OPBARB_PARK_NOT_ENABLED 1178 /* bus parking by id was enabled but + * bus parking was not enabled + */ +#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /* the arbiter must be in fixed + * priority mode to allow the + * priorities to be changed + */ + +/************************ Intc statuses 1201 - 1225 **************************/ + +#define XST_INTC_FAIL_SELFTEST 1201 /* self test failed */ +#define XST_INTC_CONNECT_ERROR 1202 /* interrupt already in use */ + +/********************** TmrCtr statuses 1226 - 1250 **************************/ + +#define XST_TMRCTR_TIMER_FAILED 1226 /* self test failed */ + +/********************** WdtTb statuses 1251 - 1275 ***************************/ + +#define XST_WDTTB_TIMER_FAILED 1251L + +/********************** PlbArb statuses 1276 - 1300 **************************/ + +#define XST_PLBARB_FAIL_SELFTEST 1276L + +/********************** Plb2Opb statuses 1301 - 1325 *************************/ + +#define XST_PLB2OPB_FAIL_SELFTEST 1301L + +/********************** Opb2Plb statuses 1326 - 1350 *************************/ + +#define XST_OPB2PLB_FAIL_SELFTEST 1326L + +/********************** SysAce statuses 1351 - 1360 **************************/ + +#define XST_SYSACE_NO_LOCK 1351L /* No MPU lock has been granted */ + +/********************** PCI Bridge statuses 1361 - 1375 **********************/ + +#define XST_PCI_INVALID_ADDRESS 1361L + +/********************** FlexRay constants 1400 - 1409 *************************/ + +#define XST_FR_TX_ERROR 1400 +#define XST_FR_TX_BUSY 1401 +#define XST_FR_BUF_LOCKED 1402 +#define XST_FR_NO_BUF 1403 + +/****************** USB constants 1410 - 1420 *******************************/ + +#define XST_USB_ALREADY_CONFIGURED 1410 +#define XST_USB_BUF_ALIGN_ERROR 1411 +#define XST_USB_NO_DESC_AVAILABLE 1412 +#define XST_USB_BUF_TOO_BIG 1413 +#define XST_USB_NO_BUF 1414 + +/****************** HWICAP constants 1421 - 1429 *****************************/ + +#define XST_HWICAP_WRITE_DONE 1421 + + +/****************** AXI VDMA constants 1430 - 1440 *****************************/ + +#define XST_VDMA_MISMATCH_ERROR 1430 + +/*********************** NAND Flash statuses 1441 - 1459 *********************/ + +#define XST_NAND_BUSY 1441L /* Flash is erasing or + * programming + */ +#define XST_NAND_READY 1442L /* Flash is ready for commands + */ +#define XST_NAND_ERROR 1443L /* Flash had detected an + * internal error. + */ +#define XST_NAND_PART_NOT_SUPPORTED 1444L /* Flash type not supported by + * driver + */ +#define XST_NAND_OPT_NOT_SUPPORTED 1445L /* Operation not supported + */ +#define XST_NAND_TIMEOUT_ERROR 1446L /* Programming or erase + * operation aborted due to a + * timeout + */ +#define XST_NAND_ADDRESS_ERROR 1447L /* Accessed flash outside its + * addressible range + */ +#define XST_NAND_ALIGNMENT_ERROR 1448L /* Write alignment error + */ +#define XST_NAND_PARAM_PAGE_ERROR 1449L /* Failed to read parameter + * page of the device + */ +#define XST_NAND_CACHE_ERROR 1450L /* Flash page buffer error + */ + +#define XST_NAND_WRITE_PROTECTED 1451L /* Flash is write protected + */ + +/**************************** Type Definitions *******************************/ + +typedef int XStatus; + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xtime_l.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xtime_l.h new file mode 100644 index 000000000..e6550d3ce --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xtime_l.h @@ -0,0 +1,96 @@ +/****************************************************************************** +* +* (c) Copyright 2009-13 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xtime_l.h +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 1.00a rp/sdm 11/03/09 Initial release.
+* 3.06a sgd    05/15/12 Upadted get/set time functions to make use Global Timer
+* 3.06a asa    06/17/12 Reverted back the changes to make use Global Timer.
+* 3.07a sgd    07/05/12 Upadted get/set time functions to make use Global Timer
+*
+* +* @note None. +* +******************************************************************************/ + +#ifndef XTIME_H /* prevent circular inclusions */ +#define XTIME_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xparameters.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +typedef unsigned long long XTime; + +/************************** Constant Definitions *****************************/ +#define GLOBAL_TMR_BASEADDR XPAR_GLOBAL_TMR_BASEADDR +#define GTIMER_COUNTER_LOWER_OFFSET 0x00 +#define GTIMER_COUNTER_UPPER_OFFSET 0x04 +#define GTIMER_CONTROL_OFFSET 0x08 + + +/* Global Timer is always clocked at half of the CPU frequency */ +#define COUNTS_PER_SECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2) +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +void XTime_SetTime(XTime Xtime); +void XTime_GetTime(XTime *Xtime); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XTIME_H */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xttcps.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xttcps.h new file mode 100644 index 000000000..2afdffe5d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xttcps.h @@ -0,0 +1,417 @@ +/* $Id: xttcps.h,v 1.1.2.1 2011/01/20 04:08:59 sadanan Exp $ */ +/****************************************************************************** +* +* (c) Copyright 2010 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xttcps.h +* +* This is the driver for one 16-bit timer counter in the Triple Timer Counter +* (TTC) module in the Ps block. +* +* The TTC module provides three independent timer/counter modules that can each +* be clocked using either the system clock (pclk) or an externally driven +* clock (ext_clk). In addition, each counter can independently prescale its +* selected clock input (divided by 2 to 65536). Counters can be set to +* decrement or increment. +* +* Each of the counters can be programmed to generate interrupt pulses: +* . At a regular, predefined period, that is on a timed interval +* . When the counter registers overflow +* . When the count matches any one of the three 'match' registers +* +* Therefore, up to six different events can trigger a timer interrupt: three +* match interrupts, an overflow interrupt, an interval interrupt and an event +* timer interrupt. Note that the overflow interrupt and the interval interrupt +* are mutually exclusive. +* +* Initialization & Configuration +* +* An XTtcPs_Config structure is used to configure a driver instance. +* Information in the XTtcPs_Config structure is the hardware properties +* about the device. +* +* A driver instance is initialized through +* XTtcPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr). Where CfgPtr +* is a pointer to the XTtcPs_Config structure, it can be looked up statically +* through XTtcPs_LookupConfig(DeviceID), or passed in by the caller. The +* EffectiveAddr can be the static base address of the device or virtual +* mapped address if address translation is supported. +* +* Interrupts +* +* Interrupt handler is not provided by the driver, as handling of interrupt +* is application specific. +* +* @note +* The default setting for a timer/counter is: +* - Overflow Mode +* - Internal clock (pclk) selected +* - Counter disabled +* - All Interrupts disabled +* - Output waveforms disabled +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -----------------------------------------------------
+* 1.00a drg/jz 01/20/10 First release..
+* 2.0   adk    12/10/13 Updated as per the New Tcl API's
+*
+*
+* +******************************************************************************/ + +#ifndef XTTCPS_H /* prevent circular inclusions */ +#define XTTCPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xttcps_hw.h" +#include "xstatus.h" + +/************************** Constant Definitions *****************************/ + +/** @name Configuration options + * + * Options for the device. Each of the options is bit field, so more than one + * options can be specified. + * + * @{ + */ +#define XTTCPS_OPTION_EXTERNAL_CLK 0x0001 /**< External clock source */ +#define XTTCPS_OPTION_CLK_EDGE_NEG 0x0002 /**< Clock on trailing edge for + external clock*/ +#define XTTCPS_OPTION_INTERVAL_MODE 0x0004 /**< Interval mode */ +#define XTTCPS_OPTION_DECREMENT 0x0008 /**< Decrement the counter */ +#define XTTCPS_OPTION_MATCH_MODE 0x0010 /**< Match mode */ +#define XTTCPS_OPTION_WAVE_DISABLE 0x0020 /**< No waveform output */ +#define XTTCPS_OPTION_WAVE_POLARITY 0x0040 /**< Waveform polarity */ +/*@}*/ + +/**************************** Type Definitions *******************************/ + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID for device */ + u32 BaseAddress; /**< Base address for device */ + u32 InputClockHz; /**< Input clock frequency */ +} XTtcPs_Config; + +/** + * The XTtcPs driver instance data. The user is required to allocate a + * variable of this type for each PS timer/counter device in the system. A + * pointer to a variable of this type is then passed to various driver API + * functions. + */ +typedef struct { + XTtcPs_Config Config; /**< Configuration structure */ + u32 IsReady; /**< Device is initialized and ready */ +} XTtcPs; + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/* + * Internal helper macros + */ +#define InstReadReg(InstancePtr, RegOffset) \ + (Xil_In32(((InstancePtr)->Config.BaseAddress) + (RegOffset))) + +#define InstWriteReg(InstancePtr, RegOffset, Data) \ + (Xil_Out32(((InstancePtr)->Config.BaseAddress) + (RegOffset), (Data))) + +/*****************************************************************************/ +/** +* +* This function starts the counter/timer without resetting the counter value. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* +* @return None +* +* @note C-style signature: +* void XTtcPs_Start(XTtcPs *InstancePtr) +* +****************************************************************************/ +#define XTtcPs_Start(InstancePtr) \ + InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \ + (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \ + ~XTTCPS_CNT_CNTRL_DIS_MASK)) + +/*****************************************************************************/ +/** +* +* This function stops the counter/timer. This macro may be called at any time +* to stop the counter. The counter holds the last value until it is reset, +* restarted or enabled. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* +* @return None +* +* @note C-style signature: +* void XTtcPs_Stop(XTtcPs *InstancePtr) +* +****************************************************************************/ +#define XTtcPs_Stop(InstancePtr) \ + InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \ + (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \ + XTTCPS_CNT_CNTRL_DIS_MASK)) + +/*****************************************************************************/ +/** +* +* This function checks whether the timer counter has already started. +* +* @param InstancePtr is a pointer to the XTtcPs instance +* +* @return Non-zero if the device has started, '0' otherwise. +* +* @note C-style signature: +* int XTtcPs_IsStarted(XTtcPs *InstancePtr) +* +****************************************************************************/ +#define XTtcPs_IsStarted(InstancePtr) \ + (int)((InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \ + XTTCPS_CNT_CNTRL_DIS_MASK) == 0) + +/*****************************************************************************/ +/** +* +* This function returns the current 16-bit counter value. It may be called at +* any time. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* +* @return 16-bit counter value. +* +* @note C-style signature: +* u16 XTtcPs_GetCounterValue(XTtcPs *InstancePtr) +* +****************************************************************************/ +#define XTtcPs_GetCounterValue(InstancePtr) \ + (u16)InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET) + +/*****************************************************************************/ +/** +* +* This function sets the interval value to be used in interval mode. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* @param Value is the 16-bit value to be set in the interval register. +* +* @return None +* +* @note C-style signature: +* void XTtcPs_SetInterval(XTtcPs *InstancePtr, u16 Value) +* +****************************************************************************/ +#define XTtcPs_SetInterval(InstancePtr, Value) \ + InstWriteReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET, (Value)) + +/*****************************************************************************/ +/** +* +* This function gets the interval value from the interval register. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* +* @return 16-bit interval value +* +* @note C-style signature: +* u16 XTtcPs_GetInterval(XTtcPs *InstancePtr) +* +****************************************************************************/ +#define XTtcPs_GetInterval(InstancePtr) \ + (u16)InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET) + +/*****************************************************************************/ +/** +* +* This macro resets the count register. It may be called at any time. The +* counter is reset to either 0 or 0xFFFF, or the interval value, depending on +* the increment/decrement mode. The state of the counter, as started or +* stopped, is not affected by calling reset. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* +* @return None +* +* @note C-style signature: +* void XTtcPs_ResetCounterValue(XTtcPs *InstancePtr) +* +****************************************************************************/ +#define XTtcPs_ResetCounterValue(InstancePtr) \ + InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \ + (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \ + XTTCPS_CNT_CNTRL_RST_MASK)) + +/*****************************************************************************/ +/** +* +* This function enables the interrupts. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* @param InterruptMask defines which interrupt should be enabled. +* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*. +* This is a bit mask, all set bits will be enabled, cleared bits +* will not be disabled. +* +* @return None. +* +* @note +* C-style signature: +* void XTtcPs_EnableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask) +* +******************************************************************************/ +#define XTtcPs_EnableInterrupts(InstancePtr, InterruptMask) \ + InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET, \ + (InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) | \ + (InterruptMask))) + +/*****************************************************************************/ +/** +* +* This function disables the interrupts. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* @param InterruptMask defines which interrupt should be disabled. +* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*. +* This is a bit mask, all set bits will be disabled, cleared bits +* will not be disabled. +* +* @return None. +* +* @note +* C-style signature: +* void XTtcPs_DisableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask) +* +******************************************************************************/ +#define XTtcPs_DisableInterrupts(InstancePtr, InterruptMask) \ + InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET, \ + (InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) & \ + ~(InterruptMask))) + +/*****************************************************************************/ +/** +* +* This function reads the interrupt status. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* +* @return None. +* +* @note C-style signature: +* u32 XTtcPs_GetInterruptStatus(XTtcPs *InstancePtr) +* +******************************************************************************/ +#define XTtcPs_GetInterruptStatus(InstancePtr) \ + InstReadReg((InstancePtr), XTTCPS_ISR_OFFSET) + +/*****************************************************************************/ +/** +* +* This function clears the interrupt status. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* @param InterruptMask defines which interrupt should be cleared. +* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*. +* This is a bit mask, all set bits will be cleared, cleared bits +* will not be cleared. +* +* @return None. +* +* @note +* C-style signature: +* void XTtcPs_ClearInterruptStatus(XTtcPs *InstancePtr, u32 InterruptMask) +* +******************************************************************************/ +#define XTtcPs_ClearInterruptStatus(InstancePtr, InterruptMask) \ + InstWriteReg((InstancePtr), XTTCPS_ISR_OFFSET, \ + (InterruptMask)) + + +/************************** Function Prototypes ******************************/ + +/* + * Initialization functions in xttcps_sinit.c + */ +XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId); + +/* + * Required functions, in xttcps.c + */ +int XTtcPs_CfgInitialize(XTtcPs *InstancePtr, + XTtcPs_Config * ConfigPtr, u32 EffectiveAddr); + +void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value); +u16 XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex); + +void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue); +u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr); + +void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq, + u16 *Interval, u8 *Prescaler); + +/* + * Functions for options, in file xttcps_options.c + */ +int XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options); +u32 XTtcPs_GetOptions(XTtcPs *InstancePtr); + +/* + * Function for self-test, in file xttcps_selftest.c + */ +int XTtcPs_SelfTest(XTtcPs *InstancePtr); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xttcps_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xttcps_hw.h new file mode 100644 index 000000000..5f361e088 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xttcps_hw.h @@ -0,0 +1,218 @@ +/* $Id: xttcps_hw.h,v 1.1.2.1 2011/01/20 04:08:59 sadanan Exp $ */ +/****************************************************************************** +* +* (c) Copyright 2010 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xttcps_hw.h +* +* This file defines the hardware interface to one of the three timer counters +* in the Ps block. +* +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -------------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+*
+*
+* +******************************************************************************/ + +#ifndef XTTCPS_HW_H /* prevent circular inclusions */ +#define XTTCPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * + * Register offsets from the base address of the device. + * + * @{ + */ +#define XTTCPS_CLK_CNTRL_OFFSET 0x00000000 /**< Clock Control Register */ +#define XTTCPS_CNT_CNTRL_OFFSET 0x0000000C /**< Counter Control Register*/ +#define XTTCPS_COUNT_VALUE_OFFSET 0x00000018 /**< Current Counter Value */ +#define XTTCPS_INTERVAL_VAL_OFFSET 0x00000024 /**< Interval Count Value */ +#define XTTCPS_MATCH_0_OFFSET 0x00000030 /**< Match 1 value */ +#define XTTCPS_MATCH_1_OFFSET 0x0000003C /**< Match 2 value */ +#define XTTCPS_MATCH_2_OFFSET 0x00000048 /**< Match 3 value */ +#define XTTCPS_ISR_OFFSET 0x00000054 /**< Interrupt Status Register */ +#define XTTCPS_IER_OFFSET 0x00000060 /**< Interrupt Enable Register */ +/* @} */ + +/** @name Clock Control Register + * Clock Control Register definitions + * @{ + */ +#define XTTCPS_CLK_CNTRL_PS_EN_MASK 0x00000001 /**< Prescale enable */ +#define XTTCPS_CLK_CNTRL_PS_VAL_MASK 0x0000001E /**< Prescale value */ +#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT 1 /**< Prescale shift */ +#define XTTCPS_CLK_CNTRL_PS_DISABLE 16 /**< Prescale disable */ +#define XTTCPS_CLK_CNTRL_SRC_MASK 0x00000020 /**< Clock source */ +#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK 0x00000040 /**< External Clock edge */ +/* @} */ + +/** @name Counter Control Register + * Counter Control Register definitions + * @{ + */ +#define XTTCPS_CNT_CNTRL_DIS_MASK 0x00000001 /**< Disable the counter */ +#define XTTCPS_CNT_CNTRL_INT_MASK 0x00000002 /**< Interval mode */ +#define XTTCPS_CNT_CNTRL_DECR_MASK 0x00000004 /**< Decrement mode */ +#define XTTCPS_CNT_CNTRL_MATCH_MASK 0x00000008 /**< Match mode */ +#define XTTCPS_CNT_CNTRL_RST_MASK 0x00000010 /**< Reset counter */ +#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK 0x00000020 /**< Enable waveform */ +#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK 0x00000040 /**< Waveform polarity */ +#define XTTCPS_CNT_CNTRL_RESET_VALUE 0x00000021 /**< Reset value */ +/* @} */ + +/** @name Current Counter Value Register + * Current Counter Value Register definitions + * @{ + */ +#define XTTCPS_COUNT_VALUE_MASK 0x0000FFFF /**< 16-bit counter value */ +/* @} */ + +/** @name Interval Value Register + * Interval Value Register is the maximum value the counter will count up or + * down to. + * @{ + */ +#define XTTCPS_INTERVAL_VAL_MASK 0x0000FFFF /**< 16-bit Interval value*/ +/* @} */ + +/** @name Match Registers + * Definitions for Match registers, each timer counter has three match + * registers. + * @{ + */ +#define XTTCPS_MATCH_MASK 0x0000FFFF /**< 16-bit Match value */ +#define XTTCPS_NUM_MATCH_REG 3 /**< Num of Match reg */ +/* @} */ + +/** @name Interrupt Registers + * Following register bit mask is for all interrupt registers. + * + * @{ + */ +#define XTTCPS_IXR_INTERVAL_MASK 0x00000001 /**< Interval Interrupt */ +#define XTTCPS_IXR_MATCH_0_MASK 0x00000002 /**< Match 1 Interrupt */ +#define XTTCPS_IXR_MATCH_1_MASK 0x00000004 /**< Match 2 Interrupt */ +#define XTTCPS_IXR_MATCH_2_MASK 0x00000008 /**< Match 3 Interrupt */ +#define XTTCPS_IXR_CNT_OVR_MASK 0x00000010 /**< Counter Overflow */ +#define XTTCPS_IXR_ALL_MASK 0x0000001F /**< All valid Interrupts */ +/* @} */ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Read the given Timer Counter register. +* +* @param BaseAddress is the base address of the timer counter device. +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note C-style signature: +* u32 XTtcPs_ReadReg(u32 BaseAddress, u32 RegOffset) +* +*****************************************************************************/ +#define XTtcPs_ReadReg(BaseAddress, RegOffset) \ + (Xil_In32((BaseAddress) + (RegOffset))) + +/****************************************************************************/ +/** +* +* Write the given Timer Counter register. +* +* @param BaseAddress is the base address of the timer counter device. +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note C-style signature: +* void XTtcPs_WriteReg(XTtcPs BaseAddress, u32 RegOffset, +* u32 Data) +* +*****************************************************************************/ +#define XTtcPs_WriteReg(BaseAddress, RegOffset, Data) \ + (Xil_Out32((BaseAddress) + (RegOffset), (Data))) + +/****************************************************************************/ +/** +* +* Calculate a match register offset using the Match Register index. +* +* @param MatchIndex is the 0-2 value of the match register +* +* @return MATCH_N_OFFSET. +* +* @note C-style signature: +* u32 XTtcPs_Match_N_Offset(u8 MatchIndex) +* +*****************************************************************************/ +#define XTtcPs_Match_N_Offset(MatchIndex) \ + (XTTCPS_MATCH_0_OFFSET + (12 * (MatchIndex))) + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ +#ifdef __cplusplus +} +#endif +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xuartps.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xuartps.h new file mode 100644 index 000000000..4687bbe1f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xuartps.h @@ -0,0 +1,513 @@ +/***************************************************************************** +* +* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +*****************************************************************************/ +/****************************************************************************/ +/** +* +* @file xuartps.h +* +* This driver supports the following features: +* +* - Dynamic data format (baud rate, data bits, stop bits, parity) +* - Polled mode +* - Interrupt driven mode +* - Transmit and receive FIFOs (32 byte FIFO depth) +* - Access to the external modem control lines +* +* Initialization & Configuration +* +* The XUartPs_Config structure is used by the driver to configure itself. +* Fields inside this structure are properties of XUartPs based on its hardware +* build. +* +* To support multiple runtime loading and initialization strategies employed +* by various operating systems, the driver instance can be initialized in the +* following way: +* +* - XUartPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a +* configuration structure provided by the caller. If running in a system +* with address translation, the parameter EffectiveAddr should be the +* virtual address. +* +* Baud Rate +* +* The UART has an internal baud rate generator, which furnishes the baud rate +* clock for both the receiver and the transmitter. Ther input clock frequency +* can be either the master clock or the master clock divided by 8, configured +* through the mode register. +* +* Accompanied with the baud rate divider register, the baud rate is determined +* by: +* 
+*	baud_rate = input_clock / (bgen * (bdiv + 1)
+*
+* where bgen is the value of the baud rate generator, and bdiv is the value of +* baud rate divider. +* +* Interrupts +* +* The FIFOs are not flushed when the driver is initialized, but a function is +* provided to allow the user to reset the FIFOs if desired. +* +* The driver defaults to no interrupts at initialization such that interrupts +* must be enabled if desired. An interrupt is generated for one of the +* following conditions. +* +* - A change in the modem signals +* - Data in the receive FIFO for a configuable time without receiver activity +* - A parity error +* - A framing error +* - An overrun error +* - Transmit FIFO is full +* - Transmit FIFO is empty +* - Receive FIFO is full +* - Receive FIFO is empty +* - Data in the receive FIFO equal to the receive threshold +* +* The application can control which interrupts are enabled using the +* XUartPs_SetInterruptMask() function. +* +* In order to use interrupts, it is necessary for the user to connect the +* driver interrupt handler, XUartPs_InterruptHandler(), to the interrupt +* system of the application. A separate handler should be provided by the +* application to communicate with the interrupt system, and conduct +* application specific interrupt handling. An application registers its own +* handler through the XUartPs_SetHandler() function. +* +* Data Transfer +* +* The functions, XUartPs_Send() and XUartPs_Recv(), are provided in the +* driver to allow data to be sent and received. They can be used in either +* polled or interrupt mode. +* +* @note +* +* The default configuration for the UART after initialization is: +* +* - 9,600 bps or XPAR_DFT_BAUDRATE if defined +* - 8 data bits +* - 1 stop bit +* - no parity +* - FIFO's are enabled with a receive threshold of 8 bytes +* - The RX timeout is enabled with a timeout of 1 (4 char times) +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00a	drg/jz 01/12/10 First Release
+* 1.00a sdm    09/27/11 Fixed compiler warnings and also a bug
+*		        in XUartPs_SetFlowDelay where the value was not
+*			being written to the register.
+* 1.01a sdm    12/20/11 Removed the InputClockHz parameter from the XUartPs
+*			instance structure and the driver is updated to use
+*			InputClockHz parameter from the XUartPs_Config config
+*			structure.
+*			Added a parameter to XUartPs_Config structure which
+*			specifies whether the user has selected Modem pins
+*			to be connected to MIO or FMIO.
+*			Added the tcl file to generate the xparameters.h
+* 1.02a sg     05/16/12	Changed XUARTPS_RXWM_MASK to 0x3F for CR 652540 fix.
+* 1.03a sg     07/16/12 Updated XUARTPS_FORMAT_7_BITS and XUARTPS_FORMAT_6_BITS
+*			with the correct values for CR 666724
+* 			Added defines for XUARTPS_IXR_TOVR,  XUARTPS_IXR_TNFUL
+*			and XUARTPS_IXR_TTRIG.
+*			Modified the name of these defines
+*			XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+*			XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+*			XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+*			XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk     08/22/13 Added API for uart reset and related
+*			constant definitions.
+* 2.0   hk      03/07/14 Version number revised.
+* 2.1   hk     04/16/14 Change XUARTPS_MAX_RATE to 921600. CR# 780625.
+*
+*
+* +*****************************************************************************/ + +#ifndef XUARTPS_H /* prevent circular inclusions */ +#define XUARTPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xuartps_hw.h" + +/************************** Constant Definitions ****************************/ + +/* + * The following constants indicate the max and min baud rates and these + * numbers are based only on the testing that has been done. The hardware + * is capable of other baud rates. + */ +#define XUARTPS_MAX_RATE 921600 +#define XUARTPS_MIN_RATE 110 + +#define XUARTPS_DFT_BAUDRATE 115200 /* Default baud rate */ + +/** @name Configuration options + * @{ + */ +/** + * These constants specify the options that may be set or retrieved + * with the driver, each is a unique bit mask such that multiple options + * may be specified. These constants indicate the available options + * in active state. + * + */ + +#define XUARTPS_OPTION_SET_BREAK 0x0080 /**< Starts break transmission */ +#define XUARTPS_OPTION_STOP_BREAK 0x0040 /**< Stops break transmission */ +#define XUARTPS_OPTION_RESET_TMOUT 0x0020 /**< Reset the receive timeout */ +#define XUARTPS_OPTION_RESET_TX 0x0010 /**< Reset the transmitter */ +#define XUARTPS_OPTION_RESET_RX 0x0008 /**< Reset the receiver */ +#define XUARTPS_OPTION_ASSERT_RTS 0x0004 /**< Assert the RTS bit */ +#define XUARTPS_OPTION_ASSERT_DTR 0x0002 /**< Assert the DTR bit */ +#define XUARTPS_OPTION_SET_FCM 0x0001 /**< Turn on flow control mode */ +/*@}*/ + + +/** @name Channel Operational Mode + * + * The UART can operate in one of four modes: Normal, Local Loopback, Remote + * Loopback, or automatic echo. + * + * @{ + */ + +#define XUARTPS_OPER_MODE_NORMAL 0x00 /**< Normal Mode */ +#define XUARTPS_OPER_MODE_AUTO_ECHO 0x01 /**< Auto Echo Mode */ +#define XUARTPS_OPER_MODE_LOCAL_LOOP 0x02 /**< Local Loopback Mode */ +#define XUARTPS_OPER_MODE_REMOTE_LOOP 0x03 /**< Remote Loopback Mode */ + +/* @} */ + +/** @name Data format values + * + * These constants specify the data format that the driver supports. + * The data format includes the number of data bits, the number of stop + * bits and parity. + * + * @{ + */ +#define XUARTPS_FORMAT_8_BITS 0 /**< 8 data bits */ +#define XUARTPS_FORMAT_7_BITS 2 /**< 7 data bits */ +#define XUARTPS_FORMAT_6_BITS 3 /**< 6 data bits */ + +#define XUARTPS_FORMAT_NO_PARITY 4 /**< No parity */ +#define XUARTPS_FORMAT_MARK_PARITY 3 /**< Mark parity */ +#define XUARTPS_FORMAT_SPACE_PARITY 2 /**< parity */ +#define XUARTPS_FORMAT_ODD_PARITY 1 /**< Odd parity */ +#define XUARTPS_FORMAT_EVEN_PARITY 0 /**< Even parity */ + +#define XUARTPS_FORMAT_2_STOP_BIT 2 /**< 2 stop bits */ +#define XUARTPS_FORMAT_1_5_STOP_BIT 1 /**< 1.5 stop bits */ +#define XUARTPS_FORMAT_1_STOP_BIT 0 /**< 1 stop bit */ +/*@}*/ + +/** @name Callback events + * + * These constants specify the handler events that an application can handle + * using its specific handler function. Note that these constants are not bit + * mask, so only one event can be passed to an application at a time. + * + * @{ + */ +#define XUARTPS_EVENT_RECV_DATA 1 /**< Data receiving done */ +#define XUARTPS_EVENT_RECV_TOUT 2 /**< A receive timeout occurred */ +#define XUARTPS_EVENT_SENT_DATA 3 /**< Data transmission done */ +#define XUARTPS_EVENT_RECV_ERROR 4 /**< A receive error detected */ +#define XUARTPS_EVENT_MODEM 5 /**< Modem status changed */ +/*@}*/ + + +/**************************** Type Definitions ******************************/ + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Base address of device (IPIF) */ + u32 InputClockHz;/**< Input clock frequency */ + int ModemPinsConnected; /** Specifies whether modem pins are connected + * to MIO or FMIO */ +} XUartPs_Config; + +/* + * Keep track of state information about a data buffer in the interrupt mode. + */ +typedef struct { + u8 *NextBytePtr; + unsigned int RequestedBytes; + unsigned int RemainingBytes; +} XUartPsBuffer; + +/** + * Keep track of data format setting of a device. + */ +typedef struct { + u32 BaudRate; /**< In bps, ie 1200 */ + u32 DataBits; /**< Number of data bits */ + u32 Parity; /**< Parity */ + u8 StopBits; /**< Number of stop bits */ +} XUartPsFormat; + +/******************************************************************************/ +/** + * This data type defines a handler that an application defines to communicate + * with interrupt system to retrieve state information about an application. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the handler, and is passed back to the upper layer + * when the handler is called. It is used to find the device driver + * instance. + * @param Event contains one of the event constants indicating events that + * have occurred. + * @param EventData contains the number of bytes sent or received at the + * time of the call for send and receive events and contains the + * modem status for modem events. + * + ******************************************************************************/ +typedef void (*XUartPs_Handler) (void *CallBackRef, u32 Event, + unsigned int EventData); + +/** + * The XUartPs driver instance data structure. A pointer to an instance data + * structure is passed around by functions to refer to a specific driver + * instance. + */ +typedef struct { + XUartPs_Config Config; /* Configuration data structure */ + u32 InputClockHz; /* Input clock frequency */ + u32 IsReady; /* Device is initialized and ready */ + u32 BaudRate; /* Current baud rate */ + + XUartPsBuffer SendBuffer; + XUartPsBuffer ReceiveBuffer; + + XUartPs_Handler Handler; + void *CallBackRef; /* Callback reference for event handler */ +} XUartPs; + + +/***************** Macros (Inline Functions) Definitions ********************/ + +/****************************************************************************/ +/** +* Get the UART Channel Status Register. +* +* @param InstancePtr is a pointer to the XUartPs instance. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u16 XUartPs_GetChannelStatus(XUartPs *InstancePtr) +* +******************************************************************************/ +#define XUartPs_GetChannelStatus(InstancePtr) \ + Xil_In32(((InstancePtr)->Config.BaseAddress) + XUARTPS_SR_OFFSET) + +/****************************************************************************/ +/** +* Get the UART Mode Control Register. +* +* @param InstancePtr is a pointer to the XUartPs instance. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u32 XUartPs_GetControl(XUartPs *InstancePtr) +* +******************************************************************************/ +#define XUartPs_GetModeControl(InstancePtr) \ + Xil_In32(((InstancePtr)->Config.BaseAddress) + XUARTPS_CR_OFFSET) + +/****************************************************************************/ +/** +* Set the UART Mode Control Register. +* +* @param InstancePtr is a pointer to the XUartPs instance. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XUartPs_SetModeControl(XUartPs *InstancePtr, u16 RegisterValue) +* +******************************************************************************/ +#define XUartPs_SetModeControl(InstancePtr, RegisterValue) \ + Xil_Out32(((InstancePtr)->Config.BaseAddress) + XUARTPS_CR_OFFSET, \ + (RegisterValue)) + +/****************************************************************************/ +/** +* Enable the transmitter and receiver of the UART. +* +* @param InstancePtr is a pointer to the XUartPs instance. +* +* @return None. +* +* @note C-Style signature: +* void XUartPs_EnableUart(XUartPs *InstancePtr) +* +******************************************************************************/ +#define XUartPs_EnableUart(InstancePtr) \ + Xil_Out32(((InstancePtr)->Config.BaseAddress + XUARTPS_CR_OFFSET), \ + ((Xil_In32((InstancePtr)->Config.BaseAddress + XUARTPS_CR_OFFSET) & \ + ~XUARTPS_CR_EN_DIS_MASK) | (XUARTPS_CR_RX_EN | XUARTPS_CR_TX_EN))) + +/****************************************************************************/ +/** +* Disable the transmitter and receiver of the UART. +* +* @param InstancePtr is a pointer to the XUartPs instance. +* +* @return None. +* +* @note C-Style signature: +* void XUartPs_DisableUart(XUartPs *InstancePtr) +* +******************************************************************************/ +#define XUartPs_DisableUart(InstancePtr) \ + Xil_Out32(((InstancePtr)->Config.BaseAddress + XUARTPS_CR_OFFSET), \ + (((Xil_In32((InstancePtr)->Config.BaseAddress + XUARTPS_CR_OFFSET)) & \ + ~XUARTPS_CR_EN_DIS_MASK) | (XUARTPS_CR_RX_DIS | XUARTPS_CR_TX_DIS))) + +/****************************************************************************/ +/** +* Determine if the transmitter FIFO is empty. +* +* @param InstancePtr is a pointer to the XUartPs instance. +* +* @return +* - TRUE if a byte can be sent +* - FALSE if the Transmitter Fifo is not empty +* +* @note C-Style signature: +* u32 XUartPs_IsTransmitEmpty(XUartPs InstancePtr) +* +******************************************************************************/ +#define XUartPs_IsTransmitEmpty(InstancePtr) \ + ((Xil_In32(((InstancePtr)->Config.BaseAddress) + XUARTPS_SR_OFFSET) & \ + XUARTPS_SR_TXEMPTY) == XUARTPS_SR_TXEMPTY) + + +/************************** Function Prototypes *****************************/ + +/* + * Static lookup function implemented in xuartps_sinit.c + */ +XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId); + +/* + * Interface functions implemented in xuartps.c + */ +int XUartPs_CfgInitialize(XUartPs *InstancePtr, + XUartPs_Config * Config, u32 EffectiveAddr); + +unsigned int XUartPs_Send(XUartPs *InstancePtr, u8 *BufferPtr, + unsigned int NumBytes); + +unsigned int XUartPs_Recv(XUartPs *InstancePtr, u8 *BufferPtr, + unsigned int NumBytes); + +int XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate); + +/* + * Options functions in xuartps_options.c + */ +void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options); + +u16 XUartPs_GetOptions(XUartPs *InstancePtr); + +void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel); + +u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr); + +u16 XUartPs_GetModemStatus(XUartPs *InstancePtr); + +u32 XUartPs_IsSending(XUartPs *InstancePtr); + +u8 XUartPs_GetOperMode(XUartPs *InstancePtr); + +void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode); + +u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr); + +void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue); + +u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr); + +void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout); + +int XUartPs_SetDataFormat(XUartPs *InstancePtr, XUartPsFormat * Format); +void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * Format); + +/* + * interrupt functions in xuartps_intr.c + */ +u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr); + +void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask); + +void XUartPs_InterruptHandler(XUartPs *InstancePtr); + +void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr, + void *CallBackRef); + +/* + * self-test functions in xuartps_selftest.c + */ +int XUartPs_SelfTest(XUartPs *InstancePtr); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xuartps_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xuartps_hw.h new file mode 100644 index 000000000..768e38027 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xuartps_hw.h @@ -0,0 +1,432 @@ +/****************************************************************************** +* +* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xuartps_hw.h +* +* This header file contains the hardware interface of an XUartPs device. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	drg/jz 01/12/10 First Release
+* 1.03a sg     09/04/12 Added defines for XUARTPS_IXR_TOVR,  XUARTPS_IXR_TNFUL
+*			and XUARTPS_IXR_TTRIG.
+*			Modified the names of these defines
+*			XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+*			XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+*			XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+*			XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk     08/22/13 Added prototype for uart reset and related
+*			constant definitions.
+*
+*
+* +******************************************************************************/ +#ifndef XUARTPS_HW_H /* prevent circular inclusions */ +#define XUARTPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * + * Register offsets for the UART. + * @{ + */ +#define XUARTPS_CR_OFFSET 0x00 /**< Control Register [8:0] */ +#define XUARTPS_MR_OFFSET 0x04 /**< Mode Register [9:0] */ +#define XUARTPS_IER_OFFSET 0x08 /**< Interrupt Enable [12:0] */ +#define XUARTPS_IDR_OFFSET 0x0C /**< Interrupt Disable [12:0] */ +#define XUARTPS_IMR_OFFSET 0x10 /**< Interrupt Mask [12:0] */ +#define XUARTPS_ISR_OFFSET 0x14 /**< Interrupt Status [12:0]*/ +#define XUARTPS_BAUDGEN_OFFSET 0x18 /**< Baud Rate Generator [15:0] */ +#define XUARTPS_RXTOUT_OFFSET 0x1C /**< RX Timeout [7:0] */ +#define XUARTPS_RXWM_OFFSET 0x20 /**< RX FIFO Trigger Level [5:0] */ +#define XUARTPS_MODEMCR_OFFSET 0x24 /**< Modem Control [5:0] */ +#define XUARTPS_MODEMSR_OFFSET 0x28 /**< Modem Status [8:0] */ +#define XUARTPS_SR_OFFSET 0x2C /**< Channel Status [14:0] */ +#define XUARTPS_FIFO_OFFSET 0x30 /**< FIFO [7:0] */ +#define XUARTPS_BAUDDIV_OFFSET 0x34 /**< Baud Rate Divider [7:0] */ +#define XUARTPS_FLOWDEL_OFFSET 0x38 /**< Flow Delay [5:0] */ +#define XUARTPS_TXWM_OFFSET 0x44 /**< TX FIFO Trigger Level [5:0] */ +/* @} */ + +/** @name Control Register + * + * The Control register (CR) controls the major functions of the device. + * + * Control Register Bit Definition + */ + +#define XUARTPS_CR_STOPBRK 0x00000100 /**< Stop transmission of break */ +#define XUARTPS_CR_STARTBRK 0x00000080 /**< Set break */ +#define XUARTPS_CR_TORST 0x00000040 /**< RX timeout counter restart */ +#define XUARTPS_CR_TX_DIS 0x00000020 /**< TX disabled. */ +#define XUARTPS_CR_TX_EN 0x00000010 /**< TX enabled */ +#define XUARTPS_CR_RX_DIS 0x00000008 /**< RX disabled. */ +#define XUARTPS_CR_RX_EN 0x00000004 /**< RX enabled */ +#define XUARTPS_CR_EN_DIS_MASK 0x0000003C /**< Enable/disable Mask */ +#define XUARTPS_CR_TXRST 0x00000002 /**< TX logic reset */ +#define XUARTPS_CR_RXRST 0x00000001 /**< RX logic reset */ +/* @}*/ + + +/** @name Mode Register + * + * The mode register (MR) defines the mode of transfer as well as the data + * format. If this register is modified during transmission or reception, + * data validity cannot be guaranteed. + * + * Mode Register Bit Definition + * @{ + */ +#define XUARTPS_MR_CCLK 0x00000400 /**< Input clock selection */ +#define XUARTPS_MR_CHMODE_R_LOOP 0x00000300 /**< Remote loopback mode */ +#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200 /**< Local loopback mode */ +#define XUARTPS_MR_CHMODE_ECHO 0x00000100 /**< Auto echo mode */ +#define XUARTPS_MR_CHMODE_NORM 0x00000000 /**< Normal mode */ +#define XUARTPS_MR_CHMODE_SHIFT 8 /**< Mode shift */ +#define XUARTPS_MR_CHMODE_MASK 0x00000300 /**< Mode mask */ +#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080 /**< 2 stop bits */ +#define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040 /**< 1.5 stop bits */ +#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000 /**< 1 stop bit */ +#define XUARTPS_MR_STOPMODE_SHIFT 6 /**< Stop bits shift */ +#define XUARTPS_MR_STOPMODE_MASK 0x000000A0 /**< Stop bits mask */ +#define XUARTPS_MR_PARITY_NONE 0x00000020 /**< No parity mode */ +#define XUARTPS_MR_PARITY_MARK 0x00000018 /**< Mark parity mode */ +#define XUARTPS_MR_PARITY_SPACE 0x00000010 /**< Space parity mode */ +#define XUARTPS_MR_PARITY_ODD 0x00000008 /**< Odd parity mode */ +#define XUARTPS_MR_PARITY_EVEN 0x00000000 /**< Even parity mode */ +#define XUARTPS_MR_PARITY_SHIFT 3 /**< Parity setting shift */ +#define XUARTPS_MR_PARITY_MASK 0x00000038 /**< Parity mask */ +#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006 /**< 6 bits data */ +#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004 /**< 7 bits data */ +#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000 /**< 8 bits data */ +#define XUARTPS_MR_CHARLEN_SHIFT 1 /**< Data Length shift */ +#define XUARTPS_MR_CHARLEN_MASK 0x00000006 /**< Data length mask */ +#define XUARTPS_MR_CLKSEL 0x00000001 /**< Input clock selection */ +/* @} */ + + +/** @name Interrupt Registers + * + * Interrupt control logic uses the interrupt enable register (IER) and the + * interrupt disable register (IDR) to set the value of the bits in the + * interrupt mask register (IMR). The IMR determines whether to pass an + * interrupt to the interrupt status register (ISR). + * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an + * interrupt. IMR and ISR are read only, and IER and IDR are write only. + * Reading either IER or IDR returns 0x00. + * + * All four registers have the same bit definitions. + * + * @{ + */ +#define XUARTPS_IXR_TOVR 0x00001000 /**< Tx FIFO Overflow interrupt */ +#define XUARTPS_IXR_TNFUL 0x00000800 /**< Tx FIFO Nearly Full interrupt */ +#define XUARTPS_IXR_TTRIG 0x00000400 /**< Tx Trig interrupt */ +#define XUARTPS_IXR_DMS 0x00000200 /**< Modem status change interrupt */ +#define XUARTPS_IXR_TOUT 0x00000100 /**< Timeout error interrupt */ +#define XUARTPS_IXR_PARITY 0x00000080 /**< Parity error interrupt */ +#define XUARTPS_IXR_FRAMING 0x00000040 /**< Framing error interrupt */ +#define XUARTPS_IXR_OVER 0x00000020 /**< Overrun error interrupt */ +#define XUARTPS_IXR_TXFULL 0x00000010 /**< TX FIFO full interrupt. */ +#define XUARTPS_IXR_TXEMPTY 0x00000008 /**< TX FIFO empty interrupt. */ +#define XUARTPS_IXR_RXFULL 0x00000004 /**< RX FIFO full interrupt. */ +#define XUARTPS_IXR_RXEMPTY 0x00000002 /**< RX FIFO empty interrupt. */ +#define XUARTPS_IXR_RXOVR 0x00000001 /**< RX FIFO trigger interrupt. */ +#define XUARTPS_IXR_MASK 0x00001FFF /**< Valid bit mask */ +/* @} */ + + +/** @name Baud Rate Generator Register + * + * The baud rate generator control register (BRGR) is a 16 bit register that + * controls the receiver bit sample clock and baud rate. + * Valid values are 1 - 65535. + * + * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit + * in the MR register. + * @{ + */ +#define XUARTPS_BAUDGEN_DISABLE 0x00000000 /**< Disable clock */ +#define XUARTPS_BAUDGEN_MASK 0x0000FFFF /**< Valid bits mask */ +#define XUARTPS_BAUDGEN_RESET_VAL 0x0000028B /**< Reset value */ + +/** @name Baud Divisor Rate register + * + * The baud rate divider register (BDIV) controls how much the bit sample + * rate is divided by. It sets the baud rate. + * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored. + * + * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by + * the MR_CCLK bit in the MR register. + * @{ + */ +#define XUARTPS_BAUDDIV_MASK 0x000000FF /**< 8 bit baud divider mask */ +#define XUARTPS_BAUDDIV_RESET_VAL 0x0000000F /**< Reset value */ +/* @} */ + + +/** @name Receiver Timeout Register + * + * Use the receiver timeout register (RTR) to detect an idle condition on + * the receiver data line. + * + * @{ + */ +#define XUARTPS_RXTOUT_DISABLE 0x00000000 /**< Disable time out */ +#define XUARTPS_RXTOUT_MASK 0x000000FF /**< Valid bits mask */ + +/** @name Receiver FIFO Trigger Level Register + * + * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at + * which the RX FIFO triggers an interrupt event. + * @{ + */ + +#define XUARTPS_RXWM_DISABLE 0x00000000 /**< Disable RX trigger interrupt */ +#define XUARTPS_RXWM_MASK 0x0000003F /**< Valid bits mask */ +#define XUARTPS_RXWM_RESET_VAL 0x00000020 /**< Reset value */ +/* @} */ + +/** @name Transmit FIFO Trigger Level Register + * + * Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at + * which the TX FIFO triggers an interrupt event. + * @{ + */ + +#define XUARTPS_TXWM_MASK 0x0000003F /**< Valid bits mask */ +#define XUARTPS_TXWM_RESET_VAL 0x00000020 /**< Reset value */ +/* @} */ + +/** @name Modem Control Register + * + * This register (MODEMCR) controls the interface with the modem or data set, + * or a peripheral device emulating a modem. + * + * @{ + */ +#define XUARTPS_MODEMCR_FCM 0x00000010 /**< Flow control mode */ +#define XUARTPS_MODEMCR_RTS 0x00000002 /**< Request to send */ +#define XUARTPS_MODEMCR_DTR 0x00000001 /**< Data terminal ready */ +/* @} */ + +/** @name Modem Status Register + * + * This register (MODEMSR) indicates the current state of the control lines + * from a modem, or another peripheral device, to the CPU. In addition, four + * bits of the modem status register provide change information. These bits + * are set to a logic 1 whenever a control input from the modem changes state. + * + * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem + * status interrupt is generated and this is reflected in the modem status + * register. + * + * @{ + */ +#define XUARTPS_MODEMSR_FCMS 0x00000100 /**< Flow control mode (FCMS) */ +#define XUARTPS_MODEMSR_DCD 0x00000080 /**< Complement of DCD input */ +#define XUARTPS_MODEMSR_RI 0x00000040 /**< Complement of RI input */ +#define XUARTPS_MODEMSR_DSR 0x00000020 /**< Complement of DSR input */ +#define XUARTPS_MODEMSR_CTS 0x00000010 /**< Complement of CTS input */ +#define XUARTPS_MODEMSR_DDCD 0x00000008 /**< Delta DCD indicator */ +#define XUARTPS_MODEMSR_TERI 0x00000004 /**< Trailing Edge Ring Indicator */ +#define XUARTPS_MODEMSR_DDSR 0x00000002 /**< Change of DSR */ +#define XUARTPS_MODEMSR_DCTS 0x00000001 /**< Change of CTS */ +/* @} */ + +/** @name Channel Status Register + * + * The channel status register (CSR) is provided to enable the control logic + * to monitor the status of bits in the channel interrupt status register, + * even if these are masked out by the interrupt mask register. + * + * @{ + */ +#define XUARTPS_SR_TNFUL 0x00004000 /**< TX FIFO Nearly Full Status */ +#define XUARTPS_SR_TTRIG 0x00002000 /**< TX FIFO Trigger Status */ +#define XUARTPS_SR_FLOWDEL 0x00001000 /**< RX FIFO fill over flow delay */ +#define XUARTPS_SR_TACTIVE 0x00000800 /**< TX active */ +#define XUARTPS_SR_RACTIVE 0x00000400 /**< RX active */ +#define XUARTPS_SR_DMS 0x00000200 /**< Delta modem status change */ +#define XUARTPS_SR_TOUT 0x00000100 /**< RX timeout */ +#define XUARTPS_SR_PARITY 0x00000080 /**< RX parity error */ +#define XUARTPS_SR_FRAME 0x00000040 /**< RX frame error */ +#define XUARTPS_SR_OVER 0x00000020 /**< RX overflow error */ +#define XUARTPS_SR_TXFULL 0x00000010 /**< TX FIFO full */ +#define XUARTPS_SR_TXEMPTY 0x00000008 /**< TX FIFO empty */ +#define XUARTPS_SR_RXFULL 0x00000004 /**< RX FIFO full */ +#define XUARTPS_SR_RXEMPTY 0x00000002 /**< RX FIFO empty */ +#define XUARTPS_SR_RXOVR 0x00000001 /**< RX FIFO fill over trigger */ +/* @} */ + +/** @name Flow Delay Register + * + * Operation of the flow delay register (FLOWDEL) is very similar to the + * receive FIFO trigger register. An internal trigger signal activates when the + * FIFO is filled to the level set by this register. This trigger will not + * cause an interrupt, although it can be read through the channel status + * register. In hardware flow control mode, RTS is deactivated when the trigger + * becomes active. RTS only resets when the FIFO level is four less than the + * level of the flow delay trigger and the flow delay trigger is not activated. + * A value less than 4 disables the flow delay. + * @{ + */ +#define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /**< Valid bit mask */ +/* @} */ + + + +/* + * Defines for backwards compatabilty, will be removed + * in the next version of the driver + */ +#define XUARTPS_MEDEMSR_DCDX XUARTPS_MODEMSR_DDCD +#define XUARTPS_MEDEMSR_RIX XUARTPS_MODEMSR_TERI +#define XUARTPS_MEDEMSR_DSRX XUARTPS_MODEMSR_DDSR +#define XUARTPS_MEDEMSR_CTSX XUARTPS_MODEMSR_DCTS + + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* Read a UART register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the base address of the +* device. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset) +* +******************************************************************************/ +#define XUartPs_ReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (RegOffset)) + +/***************************************************************************/ +/** +* Write a UART register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the base address of the +* device. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XUartPs_WriteReg(u32 BaseAddress, int RegOffset, +* u16 RegisterValue) +* +******************************************************************************/ +#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ + Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue)) + +/****************************************************************************/ +/** +* Determine if there is receive data in the receiver and/or FIFO. +* +* @param BaseAddress contains the base address of the device. +* +* @return TRUE if there is receive data, FALSE otherwise. +* +* @note C-Style signature: +* u32 XUartPs_IsReceiveData(u32 BaseAddress) +* +******************************************************************************/ +#define XUartPs_IsReceiveData(BaseAddress) \ + !((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \ + XUARTPS_SR_RXEMPTY) == XUARTPS_SR_RXEMPTY) + +/****************************************************************************/ +/** +* Determine if a byte of data can be sent with the transmitter. +* +* @param BaseAddress contains the base address of the device. +* +* @return TRUE if the TX FIFO is full, FALSE if a byte can be put in the +* FIFO. +* +* @note C-Style signature: +* u32 XUartPs_IsTransmitFull(u32 BaseAddress) +* +******************************************************************************/ +#define XUartPs_IsTransmitFull(BaseAddress) \ + ((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \ + XUARTPS_SR_TXFULL) == XUARTPS_SR_TXFULL) + +/************************** Function Prototypes ******************************/ + +void XUartPs_SendByte(u32 BaseAddress, u8 Data); + +u8 XUartPs_RecvByte(u32 BaseAddress); + +void XUartPs_ResetHw(u32 BaseAddress); + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xusbps.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xusbps.h new file mode 100644 index 000000000..154b6a5cd --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xusbps.h @@ -0,0 +1,1091 @@ +/****************************************************************************** +* +* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** + * + * @file xusbps.h + * + * This file contains the implementation of the XUsbPs driver. It is the + * driver for an USB controller in DEVICE or HOST mode. + * + *

Introduction

+ * + * The Spartan-3AF Embedded Peripheral Block contains a USB controller for + * communication with serial peripherals or hosts. The USB controller supports + * Host, Device and On the Go (OTG) applications. + * + *

USB Controller Features

+ * + * - Supports Low Speed USB 1.1 (1.5Mbps), Full Speed USB 1.1 (12Mbps), and + * High Speed USB 2.0 (480Mbps) data speeds + * - Supports Device, Host and OTG operational modes + * - ULPI transceiver interface for USB 2.0 operation + * - Integrated USB Full and Low speed serial transceiver interfaces for lowest + * cost connections + * + *

Initialization & Configuration

+ * + * The configuration of the USB driver happens in multiple stages: + * + * - (a) Configuration of the basic parameters: + * In this stage the basic parameters for the driver are configured, + * including the base address and the controller ID. + * + * - (b) Configuration of the DEVICE endpoints (if applicable): + * If DEVICE mode is desired, the endpoints of the controller need to be + * configured using the XUsbPs_DeviceConfig data structure. Once the + * endpoint configuration is set up in the data structure, The user then + * needs to allocate the required amount of DMAable memory and + * finalize the configuration of the XUsbPs_DeviceConfig data structure, + * e.g. setting the DMAMemVirt and DMAMemPhys members. + * + * - (c) Configuration of the DEVICE modes: + * In the second stage the parameters for DEVICE are configured. + * The caller only needs to configure the modes that are + * actually used. Configuration is done with the: + * XUsbPs_ConfigureDevice() + * Configuration parameters are defined and passed + * into these functions using the: + * XUsbPs_DeviceConfig data structures. + * + * + *

USB Device Endpoints

+ * + * The USB core supports up to 4 endpoints. Each endpoint has two directions, + * an OUT (RX) and an IN (TX) direction. Note that the direction is viewed from + * the host's perspective. Endpoint 0 defaults to be the control endpoint and + * does not need to be set up. Other endpoints need to be configured and set up + * depending on the application. Only endpoints that are actuelly used by the + * application need to be initialized. + * See the example code (xusbps_intr_example.c) for more information. + * + * + *

Interrupt Handling

+ * + * The USB core uses one interrupt line to report interrupts to the CPU. + * Interrupts are handled by the driver's interrupt handler function + * XUsbPs_IntrHandler(). + * It has to be registered with the OS's interrupt subsystem. The driver's + * interrupt handler divides incoming interrupts into two categories: + * + * - General device interrupts + * - Endopint related interrupts + * + * The user (typically the adapter layer) can register general interrupt + * handler fucntions and endpoint specific interrupt handler functions with the + * driver to receive those interrupts by calling the + * XUsbPs_IntrSetHandler() + * and + * XUsbPs_EpSetHandler() + * functions respectively. Calling these functions with a NULL pointer as the + * argument for the function pointer will "clear" the handler function. + * + * The user can register one handler function for the generic interrupts and + * two handler functions for each endpoint, one for the RX (OUT) and one for + * the TX (IN) direction. For some applications it may be useful to register a + * single endpoint handler function for muliple endpoints/directions. + * + * When a callback function is called by the driver, parameters identifying the + * type of the interrupt will be passed into the handler functions. For general + * interrupts the interrupt mask will be passed into the handler function. For + * endpoint interrupts the parameters include the number of the endpoint, the + * direction (OUT/IN) and the type of the interrupt. + * + * + *

Data buffer handling

+ * + * Data buffers are sent to and received from endpoint using the + * XUsbPs_EpBufferSend(), XUsbPs_EpBufferSendWithZLT() + * and + * XUsbPs_EpBufferReceive() + * functions. + * + * User data buffer size is limited to 16 Kbytes. If the user wants to send a + * data buffer that is bigger than this limit it needs to break down the data + * buffer into multiple fragments and send the fragments individually. + * + * From the controller perspective Data buffers can be aligned at any boundary. + * if the buffers are from cache region then the buffer and buffer size should + * be aligned to cache line aligned + * + * + *

Zero copy

+ * + * The driver uses a zero copy mechanism which imposes certain restrictions to + * the way the user can handle the data buffers. + * + * One restriction is that the user needs to release a buffer after it is done + * processing the data in the buffer. + * + * Similarly, when the user sends a data buffer it MUST not re-use the buffer + * until it is notified by the driver that the buffer has been transmitted. The + * driver will notify the user via the registered endpoint interrupt handling + * function by sending a XUSBPS_EP_EVENT_DATA_TX event. + * + * + *

DMA

+ * + * The driver uses DMA internally to move data from/to memory. This behaviour + * is transparent to the user. Keeping the DMA handling hidden from the user + * has the advantage that the same API can be used with USB cores that do not + * support DMA. + * + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- ----------------------------------------------------------
+ * 1.00a wgr  10/10/10 First release
+ * 1.02a wgr  05/16/12 Removed comments as they are showing up in SDK
+ *		       Tabs for CR 657898
+ * 1.03a nm   09/21/12 Fixed CR#678977. Added proper sequence for setup packet
+ *                    handling.
+ * 1.04a nm   10/23/12 Fixed CR# 679106.
+ *	      11/02/12 Fixed CR# 683931. Mult bits are set properly in dQH.
+ * 2.00a kpc 04/03/14 Fixed CR#777763. Corrected the setup tripwire macro val.
+ * 2.1   kpc 04/28/14 Removed unused function prototypes
+ *
+ * + ******************************************************************************/ + +#ifndef XUSBPS_H +#define XUSBPS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xusbps_hw.h" +#include "xil_types.h" +#include "xstatus.h" + +/************************** Constant Definitions *****************************/ + +/** + * @name System hang prevention Timeout counter value. + * + * This value is used throughout the code to initialize a Timeout counter that + * is used when hard polling a register. The ides is to initialize the Timeout + * counter to a value that is longer than any expected Timeout but short enough + * so the system will continue to work and report an error while the user is + * still paying attention. A reasonable Timeout time would be about 10 seconds. + * The XUSBPS_TIMEOUT_COUNTER value should be chosen so a polling loop would + * run about 10 seconds before a Timeout is detected. For example: + * + * int Timeout = XUSBPS_TIMEOUT_COUNTER; + * while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, + * XUSBPS_CMD_OFFSET) & + * XUSBPS_CMD_RST_MASK) && --Timeout) { + * ; + * } + * if (0 == Timeout) { + * return XST_FAILURE; + * } + * + */ +#define XUSBPS_TIMEOUT_COUNTER 1000000 + + +/** + * @name Endpoint Direction (bitmask) + * Definitions to be used with Endpoint related function that require a + * 'Direction' parameter. + * + * NOTE: + * The direction is always defined from the perspective of the HOST! This + * means that an IN endpoint on the controller is used for sending data while + * the OUT endpoint on the controller is used for receiving data. + * @{ + */ +#define XUSBPS_EP_DIRECTION_IN 0x01 /**< Endpoint direction IN. */ +#define XUSBPS_EP_DIRECTION_OUT 0x02 /**< Endpoint direction OUT. */ +/* @} */ + + +/** + * @name Endpoint Type + * Definitions to be used with Endpoint related functions that require a 'Type' + * parameter. + * @{ + */ +#define XUSBPS_EP_TYPE_NONE 0 /**< Endpoint is not used. */ +#define XUSBPS_EP_TYPE_CONTROL 1 /**< Endpoint for Control Transfers */ +#define XUSBPS_EP_TYPE_ISOCHRONOUS 2 /**< Endpoint for isochronous data */ +#define XUSBPS_EP_TYPE_BULK 3 /**< Endpoint for BULK Transfers. */ +#define XUSBPS_EP_TYPE_INTERRUPT 4 /**< Endpoint for interrupt Transfers */ +/* @} */ + +/** + * Endpoint Max Packet Length in DeviceConfig is a coded value, ch9.6.6. + * + * @{ + */ +#define ENDPOINT_MAXP_LENGTH 0x400 +#define ENDPOINT_MAXP_MULT_MASK 0xC00 +#define ENDPOINT_MAXP_MULT_SHIFT 10 +/* @} */ + +/** + * @name Field names for status retrieval + * Definitions for the XUsbPs_GetStatus() function call 'StatusType' + * parameter. + * @{ + */ +#define XUSBPS_EP_STS_ADDRESS 1 /**< Address of controller. */ +#define XUSBPS_EP_STS_CONTROLLER_STATE 2 /**< Current controller state. */ +/* @} */ + + + +/** + * @name USB Default alternate setting + * + * @{ + */ +#define XUSBPS_DEFAULT_ALT_SETTING 0 /**< The default alternate setting is 0 */ +/* @} */ + +/** + * @name Endpoint event types + * Definitions that are used to identify events that occur on endpoints. Passed + * to the endpoint event handler functions registered with + * XUsbPs_EpSetHandler(). + * @{ + */ +#define XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED 0x01 + /**< Setup data has been received on the enpoint. */ +#define XUSBPS_EP_EVENT_DATA_RX 0x02 + /**< Data frame has been received on the endpoint. */ +#define XUSBPS_EP_EVENT_DATA_TX 0x03 + /**< Data frame has been sent on the endpoint. */ +/* @} */ + + +/* + * Maximum packet size for endpoint, 1024 + * @{ + */ +#define XUSBPS_MAX_PACKET_SIZE 1024 + /**< Maximum value can be put into the queue head */ +/* @} */ +/**************************** Type Definitions *******************************/ + +/****************************************************************************** + * This data type defines the callback function to be used for Endpoint + * handlers. + * + * @param CallBackRef is the Callback reference passed in by the upper + * layer when setting the handler, and is passed back to the upper + * layer when the handler is called. + * @param EpNum is the Number of the endpoint that caused the event. + * @param EventType is the type of the event that occured on the endpoint. + * @param Data is a pointer to user data pointer specified when callback + * was registered. + */ +typedef void (*XUsbPs_EpHandlerFunc)(void *CallBackRef, + u8 EpNum, u8 EventType, void *Data); + + +/****************************************************************************** + * This data type defines the callback function to be used for the general + * interrupt handler. + * + * @param CallBackRef is the Callback reference passed in by the upper + * layer when setting the handler, and is passed back to the upper + * layer when the handler is called. + * @param IrqMask is the Content of the interrupt status register. This + * value can be used by the callback function to distinguish the + * individual interrupt types. + */ +typedef void (*XUsbPs_IntrHandlerFunc)(void *CallBackRef, u32 IrqMask); + + +/******************************************************************************/ + +/* The following type definitions are used for referencing Queue Heads and + * Transfer Descriptors. The structures themselves are not used, however, the + * types are used in the API to avoid using (void *) pointers. + */ +typedef u8 XUsbPs_dQH[XUSBPS_dQH_ALIGN]; +typedef u8 XUsbPs_dTD[XUSBPS_dTD_ALIGN]; + + +/** + * The following data structures are used internally by the L0/L1 driver. + * Their contents MUST NOT be changed by the upper layers. + */ + +/** + * The following data structure represents OUT endpoint. + */ +typedef struct { + XUsbPs_dQH *dQH; + /**< Pointer to the Queue Head structure of the endpoint. */ + + XUsbPs_dTD *dTDs; + /**< Pointer to the first dTD of the dTD list for this + * endpoint. */ + + XUsbPs_dTD *dTDCurr; + /**< Buffer to the currently processed descriptor. */ + + u8 *dTDBufs; + /**< Pointer to the first buffer of the buffer list for this + * endpoint. */ + + XUsbPs_EpHandlerFunc HandlerFunc; + /**< Handler function for this endpoint. */ + void *HandlerRef; + /**< User data reference for the handler. */ +} XUsbPs_EpOut; + + +/** + * The following data structure represents IN endpoint. + */ +typedef struct { + XUsbPs_dQH *dQH; + /**< Pointer to the Queue Head structure of the endpoint. */ + + XUsbPs_dTD *dTDs; + /**< List of pointers to the Transfer Descriptors of the + * endpoint. */ + + XUsbPs_dTD *dTDHead; + /**< Buffer to the next available descriptor in the list. */ + + XUsbPs_dTD *dTDTail; + /**< Buffer to the last unsent descriptor in the list*/ + + XUsbPs_EpHandlerFunc HandlerFunc; + /**< Handler function for this endpoint. */ + void *HandlerRef; + /**< User data reference for the handler. */ +} XUsbPs_EpIn; + + +/** + * The following data structure represents an endpoint used internally + * by the L0/L1 driver. + */ +typedef struct { + /* Each endpoint has an OUT and an IN component. + */ + XUsbPs_EpOut Out; /**< OUT endpoint structure */ + XUsbPs_EpIn In; /**< IN endpoint structure */ +} XUsbPs_Endpoint; + + + +/** + * The following structure is used by the user to receive Setup Data from an + * endpoint. Using this structure simplifies the process of interpreting the + * setup data in the core's data fields. + * + * The naming scheme for the members of this structure is different from the + * naming scheme found elsewhere in the code. The members of this structure are + * defined in the Chapter 9 USB reference guide. Using this naming scheme makes + * it easier for people familiar with the standard to read the code. + */ +typedef struct { + u8 bmRequestType; /**< bmRequestType in setup data */ + u8 bRequest; /**< bRequest in setup data */ + u16 wValue; /**< wValue in setup data */ + u16 wIndex; /**< wIndex in setup data */ + u16 wLength; /**< wLength in setup data */ +} +XUsbPs_SetupData; + + +/** + * Data structures used to configure endpoints. + */ +typedef struct { + u32 Type; + /**< Endpoint type: + - XUSBPS_EP_TYPE_CONTROL + - XUSBPS_EP_TYPE_ISOCHRONOUS + - XUSBPS_EP_TYPE_BULK + - XUSBPS_EP_TYPE_INTERRUPT */ + + u32 NumBufs; + /**< Number of buffers to be handled by this endpoint. */ + u32 BufSize; + /**< Buffer size. Only relevant for OUT (receive) Endpoints. */ + + u16 MaxPacketSize; + /**< Maximum packet size for this endpoint. This number will + * define the maximum number of bytes sent on the wire per + * transaction. Range: 0..1024 */ +} XUsbPs_EpSetup; + + +/** + * Endpoint configuration structure. + */ +typedef struct { + XUsbPs_EpSetup Out; /**< OUT component of endpoint. */ + XUsbPs_EpSetup In; /**< IN component of endpoint. */ +} XUsbPs_EpConfig; + + +/** + * The XUsbPs_DeviceConfig structure contains the configuration information to + * configure the USB controller for DEVICE mode. This data structure is used + * with the XUsbPs_ConfigureDevice() function call. + */ +typedef struct { + u8 NumEndpoints; /**< Number of Endpoints for the controller. + This number depends on the runtime + configuration of driver. The driver may + configure fewer endpoints than are available + in the core. */ + + XUsbPs_EpConfig EpCfg[XUSBPS_MAX_ENDPOINTS]; + /**< List of endpoint configurations. */ + + + u32 DMAMemPhys; /**< Physical base address of DMAable memory + allocated for the driver. */ + + /* The following members are used internally by the L0/L1 driver. They + * MUST NOT be accesses and/or modified in any way by the upper layers. + * + * The reason for having these members is that we generally try to + * avoid allocating memory in the L0/L1 driver as we want to be OS + * independent. In order to avoid allocating memory for this data + * structure wihin L0/L1 we put it into the XUsbPs_DeviceConfig + * structure which is allocated by the caller. + */ + XUsbPs_Endpoint Ep[XUSBPS_MAX_ENDPOINTS]; + /**< List of endpoint metadata structures. */ + + u32 PhysAligned; /**< 64 byte aligned base address of the DMA + memory block. Will be computed and set by + the L0/L1 driver. */ +} XUsbPs_DeviceConfig; + + +/** + * The XUsbPs_Config structure contains configuration information for the USB + * controller. + * + * This structure only contains the basic configuration for the controller. The + * caller also needs to initialize the controller for the DEVICE mode + * using the XUsbPs_DeviceConfig data structures with the + * XUsbPs_ConfigureDevice() function call + */ +typedef struct { + u16 DeviceID; /**< Unique ID of controller. */ + u32 BaseAddress; /**< Core register base address. */ +} XUsbPs_Config; + + +/** + * The XUsbPs driver instance data. The user is required to allocate a + * variable of this type for every USB controller in the system. A pointer to a + * variable of this type is then passed to the driver API functions. + */ +typedef struct { + XUsbPs_Config Config; /**< Configuration structure */ + + int CurrentAltSetting; /**< Current alternative setting of interface */ + + void *UserDataPtr; /**< Data pointer to be used by upper layers to + store application dependent data structures. + The upper layers are responsible to allocated + and free the memory. The driver will not + mofidy this data pointer. */ + + /** + * The following structures hold the configuration for DEVICE mode + * of the controller. They are initialized using the + * XUsbPs_ConfigureDevice() function call. + */ + XUsbPs_DeviceConfig DeviceConfig; + /**< Configuration for the DEVICE mode. */ + + XUsbPs_IntrHandlerFunc HandlerFunc; + /**< Handler function for the controller. */ + void *HandlerRef; + /**< User data reference for the handler. */ + u32 HandlerMask; + /**< User interrupt mask. Defines which interrupts will cause + * the callback to be called. */ +} XUsbPs; + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************** + * + * USB CONTROLLER RELATED MACROS + * + ******************************************************************************/ +/*****************************************************************************/ +/** + * This macro returns the current frame number. + * + * @param InstancePtr is a pointer to the XUsbPs instance of the + * controller. + * + * @return The current frame number. + * + * @note C-style signature: + * u32 XUsbPs_GetFrameNum(const XUsbPs *InstancePtr) + * + ******************************************************************************/ +#define XUsbPs_GetFrameNum(InstancePtr) \ + XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, XUSBPS_FRAME_OFFSET) + + +/*****************************************************************************/ +/** + * This macro starts the USB engine. + * + * @param InstancePtr is a pointer to the XUsbPs instance of the + * controller. + * + * @note C-style signature: + * void XUsbPs_Start(XUsbPs *InstancePtr) + * + ******************************************************************************/ +#define XUsbPs_Start(InstancePtr) \ + XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK) + + +/*****************************************************************************/ +/** + * This macro stops the USB engine. + * + * @param InstancePtr is a pointer to the XUsbPs instance of the + * controller. + * + * @note C-style signature: + * void XUsbPs_Stop(XUsbPs *InstancePtr) + * + ******************************************************************************/ +#define XUsbPs_Stop(InstancePtr) \ + XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK) + + +/*****************************************************************************/ +/** + * This macro forces the USB engine to be in Full Speed (FS) mode. + * + * @param InstancePtr is a pointer to the XUsbPs instance of the + * controller. + * + * @note C-style signature: + * void XUsbPs_ForceFS(XUsbPs *InstancePtr) + * + ******************************************************************************/ +#define XUsbPs_ForceFS(InstancePtr) \ + XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \ + XUSBPS_PORTSCR_PFSC_MASK) + + +/*****************************************************************************/ +/** + * This macro starts the USB Timer 0, with repeat option for period of + * one second. + * + * @param InstancePtr is a pointer to XUsbPs instance of the controller. + * @param Interval is the interval for Timer0 to generate an interrupt + * + * @note C-style signature: + * void XUsbPs_StartTimer0(XUsbPs *InstancePtr, u32 Interval) + * + ******************************************************************************/ +#define XUsbPs_StartTimer0(InstancePtr, Interval) \ +{ \ + XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XUSBPS_TIMER0_LD_OFFSET, (Interval)); \ + XUsbPs_SetBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \ + XUSBPS_TIMER_RUN_MASK | \ + XUSBPS_TIMER_RESET_MASK | \ + XUSBPS_TIMER_REPEAT_MASK); \ +} \ + + +/*****************************************************************************/ +/** +* This macro stops Timer 0. +* +* @param InstancePtr is a pointer to XUsbPs instance of the controller. +* +* @note C-style signature: +* void XUsbPs_StopTimer0(XUsbPs *InstancePtr) +* +******************************************************************************/ +#define XUsbPs_StopTimer0(InstancePtr) \ + XUsbPs_ClrBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \ + XUSBPS_TIMER_RUN_MASK) + + +/*****************************************************************************/ +/** +* This macro reads Timer 0. +* +* @param InstancePtr is a pointer to XUsbPs instance of the controller. +* +* @note C-style signature: +* void XUsbPs_ReadTimer0(XUsbPs *InstancePtr) +* +******************************************************************************/ +#define XUsbPs_ReadTimer0(InstancePtr) \ + XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XUSBPS_TIMER0_CTL_OFFSET) & \ + XUSBPS_TIMER_COUNTER_MASK + + +/*****************************************************************************/ +/** +* This macro force remote wakeup on host +* +* @param InstancePtr is a pointer to XUsbPs instance of the controller. +* +* @note C-style signature: +* void XUsbPs_RemoteWakeup(XUsbPs *InstancePtr) +* +******************************************************************************/ +#define XUsbPs_RemoteWakeup(InstancePtr) \ + XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \ + XUSBPS_PORTSCR_FPR_MASK) + + +/****************************************************************************** + * + * ENDPOINT RELATED MACROS + * + ******************************************************************************/ +/*****************************************************************************/ +/** +* This macro enables the given endpoint for the given direction. +* +* @param InstancePtr is a pointer to the XUsbPs instance of the +* controller. +* @param EpNum is number of the endpoint to enable. +* @param Dir is direction of the endpoint (bitfield): +* - XUSBPS_EP_DIRECTION_OUT +* - XUSBPS_EP_DIRECTION_IN +* +* @note C-style signature: +* void XUsbPs_EpEnable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir) +* +******************************************************************************/ +#define XUsbPs_EpEnable(InstancePtr, EpNum, Dir) \ + XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \ + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \ + ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0)) + + +/*****************************************************************************/ +/** +* This macro disables the given endpoint for the given direction. +* +* @param InstancePtr is a pointer to the XUsbPs instance of the +* controller. +* @param EpNum is the number of the endpoint to disable. +* @param Dir is the direction of the endpoint (bitfield): +* - XUSBPS_EP_DIRECTION_OUT +* - XUSBPS_EP_DIRECTION_IN +* +* @note C-style signature: +* void XUsbPs_EpDisable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir) +* +******************************************************************************/ +#define XUsbPs_EpDisable(InstancePtr, EpNum, Dir) \ + XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \ + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \ + ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0)) + + +/*****************************************************************************/ +/** +* This macro stalls the given endpoint for the given direction, and flush +* the buffers. +* +* @param InstancePtr is a pointer to the XUsbPs instance of the +* controller. +* @param EpNum is number of the endpoint to stall. +* @param Dir is the direction of the endpoint (bitfield): +* - XUSBPS_EP_DIRECTION_OUT +* - XUSBPS_EP_DIRECTION_IN +* +* @note C-style signature: +* void XUsbPs_EpStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir) +* +******************************************************************************/ +#define XUsbPs_EpStall(InstancePtr, EpNum, Dir) \ + XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \ + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \ + ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0)) + + +/*****************************************************************************/ +/** +* This macro unstalls the given endpoint for the given direction. +* +* @param InstancePtr is a pointer to the XUsbPs instance of the +* controller. +* @param EpNum is the Number of the endpoint to unstall. +* @param Dir is the Direction of the endpoint (bitfield): +* - XUSBPS_EP_DIRECTION_OUT +* - XUSBPS_EP_DIRECTION_IN +* +* @note C-style signature: +* void XUsbPs_EpUnStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir) +* +******************************************************************************/ +#define XUsbPs_EpUnStall(InstancePtr, EpNum, Dir) \ + XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \ + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \ + ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0)) + + +/*****************************************************************************/ +/** +* This macro flush an endpoint upon interface disable +* +* @param InstancePtr is a pointer to the XUsbPs instance of the +* controller. +* @param EpNum is the number of the endpoint to flush. +* @param Dir is the direction of the endpoint (bitfield): +* - XUSBPS_EP_DIRECTION_OUT +* - XUSBPS_EP_DIRECTION_IN +* +* @note C-style signature: +* void XUsbPs_EpFlush(XUsbPs *InstancePtr, u8 EpNum, u8 Dir) +* +******************************************************************************/ +#define XUsbPs_EpFlush(InstancePtr, EpNum, Dir) \ + XUsbPs_SetBits(InstancePtr, XUSBPS_EPFLUSH_OFFSET, \ + EpNum << ((Dir) & XUSBPS_EP_DIRECTION_OUT ? \ + XUSBPS_EPFLUSH_RX_SHIFT:XUSBPS_EPFLUSH_TX_SHIFT)) \ + +/*****************************************************************************/ +/** +* This macro enables the interrupts defined by the bit mask. +* +* @param InstancePtr is a pointer to XUsbPs instance of the controller. +* @param IntrMask is the Bit mask of interrupts to be enabled. +* +* @note C-style signature: +* void XUsbPs_IntrEnable(XUsbPs *InstancePtr, u32 IntrMask) +* +******************************************************************************/ +#define XUsbPs_IntrEnable(InstancePtr, IntrMask) \ + XUsbPs_SetBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask) + + +/*****************************************************************************/ +/** +* This function disables the interrupts defined by the bit mask. +* +* +* @param InstancePtr is a pointer to XUsbPs instance of the controller. +* @param IntrMask is a Bit mask of interrupts to be disabled. +* +* @note C-style signature: +* void XUsbPs_IntrDisable(XUsbPs *InstancePtr, u32 IntrMask) +* +******************************************************************************/ +#define XUsbPs_IntrDisable(InstancePtr, IntrMask) \ + XUsbPs_ClrBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask) + + +/*****************************************************************************/ +/** +* This macro enables the endpoint NAK interrupts defined by the bit mask. +* +* @param InstancePtr is a pointer to XUsbPs instance of the controller. +* @param NakIntrMask is the Bit mask of endpoint NAK interrupts to be +* enabled. +* @note C-style signature: +* void XUsbPs_NakIntrEnable(XUsbPs *InstancePtr, u32 NakIntrMask) +* +******************************************************************************/ +#define XUsbPs_NakIntrEnable(InstancePtr, NakIntrMask) \ + XUsbPs_SetBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask) + + +/*****************************************************************************/ +/** +* This macro disables the endpoint NAK interrupts defined by the bit mask. +* +* @param InstancePtr is a pointer to XUsbPs instance of the controller. +* @param NakIntrMask is a Bit mask of endpoint NAK interrupts to be +* disabled. +* +* @note +* C-style signature: +* void XUsbPs_NakIntrDisable(XUsbPs *InstancePtr, u32 NakIntrMask) +* +******************************************************************************/ +#define XUsbPs_NakIntrDisable(InstancePtr, NakIntrMask) \ + XUsbPs_ClrBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask) + + +/*****************************************************************************/ +/** +* This function clears the endpoint NAK interrupts status defined by the +* bit mask. +* +* @param InstancePtr is a pointer to XUsbPs instance of the controller. +* @param NakIntrMask is the Bit mask of endpoint NAK interrupts to be cleared. +* +* @note C-style signature: +* void XUsbPs_NakIntrClear(XUsbPs *InstancePtr, u32 NakIntrMask) +* +******************************************************************************/ +#define XUsbPs_NakIntrClear(InstancePtr, NakIntrMask) \ + XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XUSBPS_EPNAKISR_OFFSET, NakIntrMask) + + + +/*****************************************************************************/ +/** +* This macro sets the Interrupt Threshold value in the control register +* +* @param InstancePtr is a pointer to XUsbPs instance of the controller. +* @param Threshold is the Interrupt threshold to be set. +* Allowed values: +* - XUSBPS_CMD_ITHRESHOLD_0 - Immediate interrupt +* - XUSBPS_CMD_ITHRESHOLD_1 - 1 Frame +* - XUSBPS_CMD_ITHRESHOLD_2 - 2 Frames +* - XUSBPS_CMD_ITHRESHOLD_4 - 4 Frames +* - XUSBPS_CMD_ITHRESHOLD_8 - 8 Frames +* - XUSBPS_CMD_ITHRESHOLD_16 - 16 Frames +* - XUSBPS_CMD_ITHRESHOLD_32 - 32 Frames +* - XUSBPS_CMD_ITHRESHOLD_64 - 64 Frames +* +* @note +* C-style signature: +* void XUsbPs_SetIntrThreshold(XUsbPs *InstancePtr, u8 Threshold) +* +******************************************************************************/ +#define XUsbPs_SetIntrThreshold(InstancePtr, Threshold) \ + XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XUSBPS_CMD_OFFSET, (Threshold))\ + + +/*****************************************************************************/ +/** +* This macro sets the Tripwire bit in the USB command register. +* +* @param InstancePtr is a pointer to XUsbPs instance of the controller. +* +* @note C-style signature: +* void XUsbPs_SetTripwire(XUsbPs *InstancePtr) +* +******************************************************************************/ +#define XUsbPs_SetSetupTripwire(InstancePtr) \ + XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, \ + XUSBPS_CMD_SUTW_MASK) + + +/*****************************************************************************/ +/** +* This macro clears the Tripwire bit in the USB command register. +* +* @param InstancePtr is a pointer to XUsbPs instance of the controller. +* +* @note C-style signature: +* void XUsbPs_ClrTripwire(XUsbPs *InstancePtr) +* +******************************************************************************/ +#define XUsbPs_ClrSetupTripwire(InstancePtr) \ + XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, \ + XUSBPS_CMD_SUTW_MASK) + + +/*****************************************************************************/ +/** +* This macro checks if the Tripwire bit in the USB command register is set. +* +* @param InstancePtr is a pointer to XUsbPs instance of the controller. +* +* @return +* - TRUE: The tripwire bit is still set. +* - FALSE: The tripwire bit has been cleared. +* +* @note C-style signature: +* int XUsbPs_TripwireIsSet(XUsbPs *InstancePtr) +* +******************************************************************************/ +#define XUsbPs_SetupTripwireIsSet(InstancePtr) \ + (XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XUSBPS_CMD_OFFSET) & \ + XUSBPS_CMD_SUTW_MASK ? TRUE : FALSE) + + +/****************************************************************************** +* +* GENERAL REGISTER / BIT MANIPULATION MACROS +* +******************************************************************************/ +/****************************************************************************/ +/** +* This macro sets the given bit mask in the register. +* +* @param InstancePtr is a pointer to XUsbPs instance of the controller. +* @param RegOffset is the register offset to be written. +* @param Bits is the Bits to be set in the register +* +* @return None. +* +* @note C-style signature: +* void XUsbPs_SetBits(u32 BaseAddress, u32 RegOffset, u32 Bits) +* +*****************************************************************************/ +#define XUsbPs_SetBits(InstancePtr, RegOffset, Bits) \ + XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \ + XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + RegOffset) | (Bits)); + + +/****************************************************************************/ +/** +* +* This macro clears the given bits in the register. +* +* @param InstancePtr is a pointer to XUsbPs instance of the controller. +* @param RegOffset is the register offset to be written. +* @param Bits are the bits to be cleared in the register +* +* @return None. +* +* @note +* C-style signature: +* void XUsbPs_ClrBits(u32 BaseAddress, u32 RegOffset, u32 Bits) +* +*****************************************************************************/ +#define XUsbPs_ClrBits(InstancePtr, RegOffset, Bits) \ + XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \ + XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + RegOffset) & ~(Bits)); + + +/************************** Function Prototypes ******************************/ + +/** + * Setup / Initialize functions. + * + * Implemented in file xusbps.c + */ +int XUsbPs_CfgInitialize(XUsbPs *InstancePtr, + const XUsbPs_Config *ConfigPtr, u32 BaseAddress); + +int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr, + const XUsbPs_DeviceConfig *CfgPtr); + +/** + * Common functions used for DEVICE/HOST mode. + */ +int XUsbPs_Reset(XUsbPs *InstancePtr); + +/** + * DEVICE mode specific functions. + */ +int XUsbPs_BusReset(XUsbPs *InstancePtr); +int XUsbPs_SetDeviceAddress(XUsbPs *InstancePtr, u8 Address); + + +/** + * Handling Suspend and Resume. + * + * Implemented in xusbps.c + */ +int XUsbPs_Suspend(const XUsbPs *InstancePtr); +int XUsbPs_Resume(const XUsbPs *InstancePtr); +int XUsbPs_RequestHostResume(const XUsbPs *InstancePtr); + + +/* + * Functions for managing Endpoints / Transfers + * + * Implemented in file xusbps_endpoint.c + */ +int XUsbPs_EpBufferSend(XUsbPs *InstancePtr, u8 EpNum, + const u8 *BufferPtr, u32 BufferLen); +int XUsbPs_EpBufferSendWithZLT(XUsbPs *InstancePtr, u8 EpNum, + const u8 *BufferPtr, u32 BufferLen); +int XUsbPs_EpBufferReceive(XUsbPs *InstancePtr, u8 EpNum, + u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle); +void XUsbPs_EpBufferRelease(u32 Handle); + +int XUsbPs_EpSetHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction, + XUsbPs_EpHandlerFunc CallBackFunc, + void *CallBackRef); +int XUsbPs_EpGetSetupData(XUsbPs *InstancePtr, int EpNum, + XUsbPs_SetupData *SetupDataPtr); + +int XUsbPs_EpPrime(XUsbPs *InstancePtr, u8 EpNum, u8 Direction); + +int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr, + int EpNum, unsigned short NewDirection, int DirectionChanged); + +/* + * Interrupt handling functions + * + * Implemented in file xusbps_intr.c + */ +void XUsbPs_IntrHandler(void *InstancePtr); + +int XUsbPs_IntrSetHandler(XUsbPs *InstancePtr, + XUsbPs_IntrHandlerFunc CallBackFunc, + void *CallBackRef, u32 Mask); +/* + * Helper functions for static configuration. + * Implemented in xusbps_sinit.c + */ +XUsbPs_Config *XUsbPs_LookupConfig(u16 DeviceId); + +#ifdef __cplusplus +} +#endif + +#endif /* XUSBPS_H */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xusbps_endpoint.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xusbps_endpoint.h new file mode 100644 index 000000000..8b6984980 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xusbps_endpoint.h @@ -0,0 +1,521 @@ +/****************************************************************************** +* +* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** + * + * @file xusbps_endpoint.h + * + * This is an internal file containung the definitions for endpoints. It is + * included by the xusbps_endpoint.c which is implementing the endpoint + * functions and by xusbps_intr.c. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- --------------------------------------------------------
+ * 1.00a wgr  10/10/10 First release
+ *
+ * + ******************************************************************************/ +#ifndef XUSBPS_ENDPOINT_H +#define XUSBPS_ENDPOINT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_cache.h" +#include "xusbps.h" +#include "xil_types.h" + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + + +/** + * Endpoint Device Transfer Descriptor + * + * The dTD describes to the device controller the location and quantity of data + * to be sent/received for given transfer. The driver does not attempt to + * modify any field in an active dTD except the Next Link Pointer. + */ +#define XUSBPS_dTDNLP 0x00 /**< Pointer to the next descriptor */ +#define XUSBPS_dTDTOKEN 0x04 /**< Descriptor Token */ +#define XUSBPS_dTDBPTR0 0x08 /**< Buffer Pointer 0 */ +#define XUSBPS_dTDBPTR1 0x0C /**< Buffer Pointer 1 */ +#define XUSBPS_dTDBPTR2 0x10 /**< Buffer Pointer 2 */ +#define XUSBPS_dTDBPTR3 0x14 /**< Buffer Pointer 3 */ +#define XUSBPS_dTDBPTR4 0x18 /**< Buffer Pointer 4 */ +#define XUSBPS_dTDBPTR(n) (XUSBPS_dTDBPTR0 + (n) * 0x04) +#define XUSBPS_dTDRSRVD 0x1C /**< Reserved field */ + +/* We use the reserved field in the dTD to store user data. */ +#define XUSBPS_dTDUSERDATA XUSBPS_dTDRSRVD /**< Reserved field */ + + +/** @name dTD Next Link Pointer (dTDNLP) bit positions. + * @{ + */ +#define XUSBPS_dTDNLP_T_MASK 0x00000001 + /**< USB dTD Next Link Pointer Terminate Bit */ +#define XUSBPS_dTDNLP_ADDR_MASK 0xFFFFFFE0 + /**< USB dTD Next Link Pointer Address [31:5] */ +/* @} */ + + +/** @name dTD Token (dTDTOKEN) bit positions. + * @{ + */ +#define XUSBPS_dTDTOKEN_XERR_MASK 0x00000008 /**< dTD Transaction Error */ +#define XUSBPS_dTDTOKEN_BUFERR_MASK 0x00000020 /**< dTD Data Buffer Error */ +#define XUSBPS_dTDTOKEN_HALT_MASK 0x00000040 /**< dTD Halted Flag */ +#define XUSBPS_dTDTOKEN_ACTIVE_MASK 0x00000080 /**< dTD Active Bit */ +#define XUSBPS_dTDTOKEN_MULTO_MASK 0x00000C00 /**< Multiplier Override Field [1:0] */ +#define XUSBPS_dTDTOKEN_IOC_MASK 0x00008000 /**< Interrupt on Complete Bit */ +#define XUSBPS_dTDTOKEN_LEN_MASK 0x7FFF0000 /**< Transfer Length Field */ +/* @} */ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** + * + * IMPORTANT NOTE: + * =============== + * + * Many of the following macros modify Device Queue Head (dQH) data structures + * and Device Transfer Descriptor (dTD) data structures. Those structures can + * potentially reside in CACHED memory. Therefore, it's the callers + * responsibility to ensure cache coherency by using provided + * + * XUsbPs_dQHInvalidateCache() + * XUsbPs_dQHFlushCache() + * XUsbPs_dTDInvalidateCache() + * XUsbPs_dTDFlushCache() + * + * function calls. + * + ******************************************************************************/ +#define XUsbPs_dTDInvalidateCache(dTDPtr) \ + Xil_DCacheInvalidateRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD)) + +#define XUsbPs_dTDFlushCache(dTDPtr) \ + Xil_DCacheFlushRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD)) + +#define XUsbPs_dQHInvalidateCache(dQHPtr) \ + Xil_DCacheInvalidateRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH)) + +#define XUsbPs_dQHFlushCache(dQHPtr) \ + Xil_DCacheFlushRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH)) + +/*****************************************************************************/ +/** + * + * This macro sets the Transfer Length for the given Transfer Descriptor. + * + * @param dTDPtr is pointer to the dTD element. + * @param Len is the length to be set. Range: 0..16384 + * + * @note C-style signature: + * void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len) + * + ******************************************************************************/ +#define XUsbPs_dTDSetTransferLen(dTDPtr, Len) \ + XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \ + (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \ + ~XUSBPS_dTDTOKEN_LEN_MASK) | ((Len) << 16)) + + +/*****************************************************************************/ +/** + * + * This macro gets the Next Link pointer of the given Transfer Descriptor. + * + * @param dTDPtr is pointer to the dTD element. + * + * @return TransferLength field of the descriptor. + * + * @note C-style signature: + * u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr) + * + ******************************************************************************/ +#define XUsbPs_dTDGetNLP(dTDPtr) \ + (XUsbPs_dTD *) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP)\ + & XUSBPS_dTDNLP_ADDR_MASK)) + + +/*****************************************************************************/ +/** + * + * This macro sets the Next Link pointer of the given Transfer Descriptor. + * + * @param dTDPtr is a pointer to the dTD element. + * @param NLP is the Next Link Pointer + * + * @note C-style signature: + * void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len) + * + ******************************************************************************/ +#define XUsbPs_dTDSetNLP(dTDPtr, NLP) \ + XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \ + (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \ + ~XUSBPS_dTDNLP_ADDR_MASK) | \ + ((NLP) & XUSBPS_dTDNLP_ADDR_MASK)) + + +/*****************************************************************************/ +/** + * + * This macro gets the Transfer Length for the given Transfer Descriptor. + * + * @param dTDPtr is a pointer to the dTD element. + * + * @return TransferLength field of the descriptor. + * + * @note C-style signature: + * u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr) + * + ******************************************************************************/ +#define XUsbPs_dTDGetTransferLen(dTDPtr) \ + (u32) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) \ + & XUSBPS_dTDTOKEN_LEN_MASK) >> 16) + + +/*****************************************************************************/ +/** + * + * This macro sets the Interrupt On Complete (IOC) bit for the given Transfer + * Descriptor. + * + * @param dTDPtr is a pointer to the dTD element. + * + * @note C-style signature: + * void XUsbPs_dTDSetIOC(u32 dTDPtr) + * + ******************************************************************************/ +#define XUsbPs_dTDSetIOC(dTDPtr) \ + XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \ + XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \ + XUSBPS_dTDTOKEN_IOC_MASK) + + +/*****************************************************************************/ +/** + * + * This macro sets the Terminate bit for the given Transfer Descriptor. + * + * @param dTDPtr is a pointer to the dTD element. + * + * @note C-style signature: + * void XUsbPs_dTDSetTerminate(u32 dTDPtr) + * + ******************************************************************************/ +#define XUsbPs_dTDSetTerminate(dTDPtr) \ + XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \ + XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) | \ + XUSBPS_dTDNLP_T_MASK) + + +/*****************************************************************************/ +/** + * + * This macro clears the Terminate bit for the given Transfer Descriptor. + * + * @param dTDPtr is a pointer to the dTD element. + * + * @note C-style signature: + * void XUsbPs_dTDClrTerminate(u32 dTDPtr) + * + ******************************************************************************/ +#define XUsbPs_dTDClrTerminate(dTDPtr) \ + XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \ + XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \ + ~XUSBPS_dTDNLP_T_MASK) + + +/*****************************************************************************/ +/** + * + * This macro checks if the given descriptor is active. + * + * @param dTDPtr is a pointer to the dTD element. + * + * @return + * - TRUE: The buffer is active. + * - FALSE: The buffer is not active. + * + * @note C-style signature: + * int XUsbPs_dTDIsActive(u32 dTDPtr) + * + ******************************************************************************/ +#define XUsbPs_dTDIsActive(dTDPtr) \ + ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \ + XUSBPS_dTDTOKEN_ACTIVE_MASK) ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * + * This macro sets the Active bit for the given Transfer Descriptor. + * + * @param dTDPtr is a pointer to the dTD element. + * + * @note C-style signature: + * void XUsbPs_dTDSetActive(u32 dTDPtr) + * + ******************************************************************************/ +#define XUsbPs_dTDSetActive(dTDPtr) \ + XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \ + XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \ + XUSBPS_dTDTOKEN_ACTIVE_MASK) + + +/*****************************************************************************/ +/** + * + * This macro reads the content of a field in a Transfer Descriptor. + * + * @param dTDPtr is a pointer to the dTD element. + * @param Id is the field ID inside the dTD element to read. + * + * @note C-style signature: + * u32 XUsbPs_ReaddTD(u32 dTDPtr, u32 Id) + * + ******************************************************************************/ +#define XUsbPs_ReaddTD(dTDPtr, Id) (*(u32 *)((u32)(dTDPtr) + (u32)(Id))) + +/*****************************************************************************/ +/** + * + * This macro writes a value to a field in a Transfer Descriptor. + * + * @param dTDPtr is pointer to the dTD element. + * @param Id is the field ID inside the dTD element to read. + * @param Val is the value to write to the field. + * + * @note C-style signature: + * u32 XUsbPs_WritedTD(u32 dTDPtr, u32 Id, u32 Val) + * + ******************************************************************************/ +#define XUsbPs_WritedTD(dTDPtr, Id, Val) \ + (*(u32 *) ((u32)(dTDPtr) + (u32)(Id)) = (u32)(Val)) + + +/******************************************************************************/ +/** + * Endpoint Device Queue Head + * + * Device queue heads are arranged in an array in a continuous area of memory + * pointed to by the ENDPOINTLISTADDR pointer. The device controller will index + * into this array based upon the endpoint number received from the USB bus. + * All information necessary to respond to transactions for all primed + * transfers is contained in this list so the Device Controller can readily + * respond to incoming requests without having to traverse a linked list. + * + * The device Endpoint Queue Head (dQH) is where all transfers are managed. The + * dQH is a 48-byte data structure, but must be aligned on a 64-byte boundary. + * During priming of an endpoint, the dTD (device transfer descriptor) is + * copied into the overlay area of the dQH, which starts at the nextTD pointer + * DWord and continues through the end of the buffer pointers DWords. After a + * transfer is complete, the dTD status DWord is updated in the dTD pointed to + * by the currentTD pointer. While a packet is in progress, the overlay area of + * the dQH is used as a staging area for the dTD so that the Device Controller + * can access needed information with little minimal latency. + * + * @note + * Software must ensure that no interface data structure reachable by the + * Device Controller spans a 4K-page boundary. The first element of the + * Endpoint Queue Head List must be aligned on a 4K boundary. + */ +#define XUSBPS_dQHCFG 0x00 /**< dQH Configuration */ +#define XUSBPS_dQHCPTR 0x04 /**< dQH Current dTD Pointer */ +#define XUSBPS_dQHdTDNLP 0x08 /**< dTD Next Link Ptr in dQH + overlay */ +#define XUSBPS_dQHdTDTOKEN 0x0C /**< dTD Token in dQH overlay */ +#define XUSBPS_dQHSUB0 0x28 /**< USB dQH Setup Buffer 0 */ +#define XUSBPS_dQHSUB1 0x2C /**< USB dQH Setup Buffer 1 */ + + +/** @name dQH Configuration (dQHCFG) bit positions. + * @{ + */ +#define XUSBPS_dQHCFG_IOS_MASK 0x00008000 + /**< USB dQH Interrupt on Setup Bit */ +#define XUSBPS_dQHCFG_MPL_MASK 0x07FF0000 + /**< USB dQH Maximum Packet Length + * Field [10:0] */ +#define XUSBPS_dQHCFG_MPL_SHIFT 16 +#define XUSBPS_dQHCFG_ZLT_MASK 0x20000000 + /**< USB dQH Zero Length Termination + * Select Bit */ +#define XUSBPS_dQHCFG_MULT_MASK 0xC0000000 + /* USB dQH Number of Transactions Field + * [1:0] */ +#define XUSBPS_dQHCFG_MULT_SHIFT 30 +/* @} */ + + +/*****************************************************************************/ +/** + * + * This macro sets the Maximum Packet Length field of the give Queue Head. + * + * @param dQHPtr is a pointer to the dQH element. + * @param Len is the length to be set. + * + * @note C-style signature: + * void XUsbPs_dQHSetMaxPacketLen(u32 dQHPtr, u32 Len) + * + ******************************************************************************/ +#define XUsbPs_dQHSetMaxPacketLen(dQHPtr, Len) \ + XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ + (XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \ + ~XUSBPS_dQHCFG_MPL_MASK) | ((Len) << 16)) + +/*****************************************************************************/ +/** + * + * This macro sets the Interrupt On Setup (IOS) bit for an endpoint. + * + * @param dQHPtr is a pointer to the dQH element. + * + * @note C-style signature: + * void XUsbPs_dQHSetIOS(u32 dQHPtr) + * + ******************************************************************************/ +#define XUsbPs_dQHSetIOS(dQHPtr) \ + XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ + XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \ + XUSBPS_dQHCFG_IOS_MASK) + +/*****************************************************************************/ +/** + * + * This macro clears the Interrupt On Setup (IOS) bit for an endpoint. + * + * @param dQHPtr is a pointer to the dQH element. + * + * @note C-style signature: + * void XUsbPs_dQHClrIOS(u32 dQHPtr) + * + ******************************************************************************/ +#define XUsbPs_dQHClrIOS(dQHPtr) \ + XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ + XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \ + ~XUSBPS_dQHCFG_IOS_MASK) + +/*****************************************************************************/ +/** + * + * This macro enables Zero Length Termination for the endpoint. + * + * @param dQHPtr is a pointer to the dQH element. + * + * @note C-style signature: + * void XUsbPs_dQHEnableZLT(u32 dQHPtr) + * + * + ******************************************************************************/ +#define XUsbPs_dQHEnableZLT(dQHPtr) \ + XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ + XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \ + ~XUSBPS_dQHCFG_ZLT_MASK) + + +/*****************************************************************************/ +/** + * + * This macro disables Zero Length Termination for the endpoint. + * + * @param dQHPtr is a pointer to the dQH element. + * + * @note C-style signature: + * void XUsbPs_dQHDisableZLT(u32 dQHPtr) + * + * + ******************************************************************************/ +#define XUsbPs_dQHDisableZLT(dQHPtr) \ + XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ + XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \ + XUSBPS_dQHCFG_ZLT_MASK) + +/*****************************************************************************/ +/** + * + * This macro reads the content of a field in a Queue Head. + * + * @param dQHPtr is a pointer to the dQH element. + * @param Id is the Field ID inside the dQH element to read. + * + * @note C-style signature: + * u32 XUsbPs_ReaddQH(u32 dQHPtr, u32 Id) + * + ******************************************************************************/ +#define XUsbPs_ReaddQH(dQHPtr, Id) (*(u32 *)((u32)(dQHPtr) + (u32) (Id))) + +/*****************************************************************************/ +/** + * + * This macro writes a value to a field in a Queue Head. + * + * @param dQHPtr is a pointer to the dQH element. + * @param Id is the Field ID inside the dQH element to read. + * @param Val is the Value to write to the field. + * + * @note C-style signature: + * u32 XUsbPs_WritedQH(u32 dQHPtr, u32 Id, u32 Val) + * + ******************************************************************************/ +#define XUsbPs_WritedQH(dQHPtr, Id, Val) \ + (*(u32 *) ((u32)(dQHPtr) + (u32)(Id)) = (u32)(Val)) + + + +#ifdef __cplusplus +} +#endif + +#endif /* XUSBPS_ENDPOINT_H */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xusbps_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xusbps_hw.h new file mode 100644 index 000000000..5bab09165 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xusbps_hw.h @@ -0,0 +1,532 @@ +/****************************************************************************** +* +* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** + * + * @file xusbps_hw.h + * + * This header file contains identifiers and low-level driver functions (or + * macros) that can be used to access the device. High-level driver functions + * are defined in xusbps.h. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.00a wgr  10/10/10 First release
+ * 1.04a nm   10/23/12 Fixed CR# 679106.
+ * 1.05a kpc  07/03/13 Added XUsbPs_ResetHw function prototype
+ * 2.00a kpc  04/03/14 Fixed CR#777764. Corrected max endpoint vale and masks 
+ *
+ * + ******************************************************************************/ +#ifndef XUSBPS_HW_H +#define XUSBPS_HW_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + + +#define XUSBPS_REG_SPACING 4 + +/** @name Timer 0 Register offsets + * + * @{ + */ +#define XUSBPS_TIMER0_LD_OFFSET 0x00000080 +#define XUSBPS_TIMER0_CTL_OFFSET 0x00000084 +/* @} */ + +/** @name Timer Control Register bit mask + * + * @{ + */ +#define XUSBPS_TIMER_RUN_MASK 0x80000000 +#define XUSBPS_TIMER_STOP_MASK 0x80000000 +#define XUSBPS_TIMER_RESET_MASK 0x40000000 +#define XUSBPS_TIMER_REPEAT_MASK 0x01000000 +/* @} */ + +/** @name Timer Control Register bit mask + * + * @{ + */ +#define XUSBPS_TIMER_COUNTER_MASK 0x00FFFFFF +/* @} */ + +/** @name Device Hardware Parameters + * + * @{ + */ +#define XUSBPS_HWDEVICE_OFFSET 0x0000000C + +#define XUSBPS_EP_NUM_MASK 0x3E +#define XUSBPS_EP_NUM_SHIFT 1 +/* @} */ + +/** @name Capability Regsiter offsets + */ +#define XUSBPS_HCSPARAMS_OFFSET 0x00000104 + +/** @name Operational Register offsets. + * Register comments are tagged with "H:" and "D:" for Host and Device modes, + * respectively. + * Tags are only present for registers that have a different meaning DEVICE and + * HOST modes. Most registers are only valid for either DEVICE or HOST mode. + * Those registers don't have tags. + * @{ + */ +#define XUSBPS_CMD_OFFSET 0x00000140 /**< Configuration */ +#define XUSBPS_ISR_OFFSET 0x00000144 /**< Interrupt Status */ +#define XUSBPS_IER_OFFSET 0x00000148 /**< Interrupt Enable */ +#define XUSBPS_FRAME_OFFSET 0x0000014C /**< USB Frame Index */ +#define XUSBPS_LISTBASE_OFFSET 0x00000154 /**< H: Periodic List Base Address */ +#define XUSBPS_DEVICEADDR_OFFSET 0x00000154 /**< D: Device Address */ +#define XUSBPS_ASYNCLISTADDR_OFFSET 0x00000158 /**< H: Async List Address */ +#define XUSBPS_EPLISTADDR_OFFSET 0x00000158 /**< D: Endpoint List Addr */ +#define XUSBPS_TTCTRL_OFFSET 0x0000015C /**< TT Control */ +#define XUSBPS_BURSTSIZE_OFFSET 0x00000160 /**< Burst Size */ +#define XUSBPS_TXFILL_OFFSET 0x00000164 /**< Tx Fill Tuning */ +#define XUSBPS_ULPIVIEW_OFFSET 0x00000170 /**< ULPI Viewport */ +#define XUSBPS_EPNAKISR_OFFSET 0x00000178 /**< Endpoint NAK IRQ Status */ +#define XUSBPS_EPNAKIER_OFFSET 0x0000017C /**< Endpoint NAK IRQ Enable */ +#define XUSBPS_PORTSCR1_OFFSET 0x00000184 /**< Port Control/Status 1 */ + +/* NOTE: The Port Control / Status Register index is 1-based. */ +#define XUSBPS_PORTSCRn_OFFSET(n) \ + (XUSBPS_PORTSCR1_OFFSET + (((n)-1) * XUSBPS_REG_SPACING)) + + +#define XUSBPS_OTGCSR_OFFSET 0x000001A4 /**< OTG Status and Control */ +#define XUSBPS_MODE_OFFSET 0x000001A8 /**< USB Mode */ +#define XUSBPS_EPSTAT_OFFSET 0x000001AC /**< Endpoint Setup Status */ +#define XUSBPS_EPPRIME_OFFSET 0x000001B0 /**< Endpoint Prime */ +#define XUSBPS_EPFLUSH_OFFSET 0x000001B4 /**< Endpoint Flush */ +#define XUSBPS_EPRDY_OFFSET 0x000001B8 /**< Endpoint Ready */ +#define XUSBPS_EPCOMPL_OFFSET 0x000001BC /**< Endpoint Complete */ +#define XUSBPS_EPCR0_OFFSET 0x000001C0 /**< Endpoint Control 0 */ +#define XUSBPS_EPCR1_OFFSET 0x000001C4 /**< Endpoint Control 1 */ +#define XUSBPS_EPCR2_OFFSET 0x000001C8 /**< Endpoint Control 2 */ +#define XUSBPS_EPCR3_OFFSET 0x000001CC /**< Endpoint Control 3 */ +#define XUSBPS_EPCR4_OFFSET 0x000001D0 /**< Endpoint Control 4 */ + +#define XUSBPS_MAX_ENDPOINTS 12 /**< Number of supported Endpoints in + * this core. */ +#define XUSBPS_EP_OUT_MASK 0x00000FFF /**< OUR (RX) endpoint mask */ +#define XUSBPS_EP_IN_MASK 0x0FFF0000 /**< IN (TX) endpoint mask */ +#define XUSBPS_EP_ALL_MASK 0x0FFF0FFF /**< Mask used for endpoint control + * registers */ +#define XUSBPS_EPCRn_OFFSET(n) \ + (XUSBPS_EPCR0_OFFSET + ((n) * XUSBPS_REG_SPACING)) + +#define XUSBPS_EPFLUSH_RX_SHIFT 0 +#define XUSBPS_EPFLUSH_TX_SHIFT 16 + +/* @} */ + + + +/** @name Endpoint Control Register (EPCR) bit positions. + * @{ + */ + +/* Definitions for TX Endpoint bits */ +#define XUSBPS_EPCR_TXT_CONTROL_MASK 0x00000000 /**< Control Endpoint - TX */ +#define XUSBPS_EPCR_TXT_ISO_MASK 0x00040000 /**< Isochronous. Endpoint */ +#define XUSBPS_EPCR_TXT_BULK_MASK 0x00080000 /**< Bulk Endpoint - TX */ +#define XUSBPS_EPCR_TXT_INTR_MASK 0x000C0000 /**< Interrupt Endpoint */ +#define XUSBPS_EPCR_TXS_MASK 0x00010000 /**< Stall TX endpoint */ +#define XUSBPS_EPCR_TXE_MASK 0x00800000 /**< Transmit enable - TX */ +#define XUSBPS_EPCR_TXR_MASK 0x00400000 /**< Data Toggle Reset Bit */ + + +/* Definitions for RX Endpoint bits */ +#define XUSBPS_EPCR_RXT_CONTROL_MASK 0x00000000 /**< Control Endpoint - RX */ +#define XUSBPS_EPCR_RXT_ISO_MASK 0x00000004 /**< Isochronous Endpoint */ +#define XUSBPS_EPCR_RXT_BULK_MASK 0x00000008 /**< Bulk Endpoint - RX */ +#define XUSBPS_EPCR_RXT_INTR_MASK 0x0000000C /**< Interrupt Endpoint */ +#define XUSBPS_EPCR_RXS_MASK 0x00000001 /**< Stall RX endpoint. */ +#define XUSBPS_EPCR_RXE_MASK 0x00000080 /**< Transmit enable. - RX */ +#define XUSBPS_EPCR_RXR_MASK 0x00000040 /**< Data Toggle Reset Bit */ +/* @} */ + + +/** @name USB Command Register (CR) bit positions. + * @{ + */ +#define XUSBPS_CMD_RS_MASK 0x00000001 /**< Run/Stop */ +#define XUSBPS_CMD_RST_MASK 0x00000002 /**< Controller RESET */ +#define XUSBPS_CMD_FS01_MASK 0x0000000C /**< Frame List Size bit 0,1 */ +#define XUSBPS_CMD_PSE_MASK 0x00000010 /**< Periodic Sched Enable */ +#define XUSBPS_CMD_ASE_MASK 0x00000020 /**< Async Sched Enable */ +#define XUSBPS_CMD_IAA_MASK 0x00000040 /**< IRQ Async Advance Doorbell */ +#define XUSBPS_CMD_ASP_MASK 0x00000300 /**< Async Sched Park Mode Cnt */ +#define XUSBPS_CMD_ASPE_MASK 0x00000800 /**< Async Sched Park Mode Enbl */ +#define XUSBPS_CMD_SUTW_MASK 0x00002000 /**< Setup TripWire */ +#define XUSBPS_CMD_ATDTW_MASK 0x00004000 /**< Add dTD TripWire */ +#define XUSBPS_CMD_FS2_MASK 0x00008000 /**< Frame List Size bit 2 */ +#define XUSBPS_CMD_ITC_MASK 0x00FF0000 /**< IRQ Threshold Control */ +/* @} */ + + +/** + * @name Interrupt Threshold + * These definitions are used by software to set the maximum rate at which the + * USB controller will generate interrupt requests. The interrupt interval is + * given in number of micro-frames. + * + * USB defines a full-speed 1 ms frame time indicated by a Start Of Frame (SOF) + * packet each and every 1ms. USB also defines a high-speed micro-frame with a + * 125us frame time. For each micro-frame a SOF (Start Of Frame) packet is + * generated. Data is sent in between the SOF packets. The interrupt threshold + * defines how many micro-frames the controller waits before issuing an + * interrupt after data has been received. + * + * For a threshold of 0 the controller will issue an interrupt immediately + * after the last byte of the data has been received. For a threshold n>0 the + * controller will wait for n micro-frames before issuing an interrupt. + * + * Therefore, a setting of 8 micro-frames (default) means that the controller + * will issue at most 1 interrupt per millisecond. + * + * @{ + */ +#define XUSBPS_CMD_ITHRESHOLD_0 0x00 /**< Immediate interrupt. */ +#define XUSBPS_CMD_ITHRESHOLD_1 0x01 /**< 1 micro-frame */ +#define XUSBPS_CMD_ITHRESHOLD_2 0x02 /**< 2 micro-frames */ +#define XUSBPS_CMD_ITHRESHOLD_4 0x04 /**< 4 micro-frames */ +#define XUSBPS_CMD_ITHRESHOLD_8 0x08 /**< 8 micro-frames */ +#define XUSBPS_CMD_ITHRESHOLD_16 0x10 /**< 16 micro-frames */ +#define XUSBPS_CMD_ITHRESHOLD_32 0x20 /**< 32 micro-frames */ +#define XUSBPS_CMD_ITHRESHOLD_64 0x40 /**< 64 micro-frames */ +#define XUSBPS_CMD_ITHRESHOLD_MAX XUSBPS_CMD_ITHRESHOLD_64 +#define XUSBPS_CMD_ITHRESHOLD_DEFAULT XUSBPS_CMD_ITHRESHOLD_8 +/* @} */ + + + +/** @name USB Interrupt Status Register (ISR) / Interrupt Enable Register (IER) + * bit positions. + * @{ + */ +#define XUSBPS_IXR_UI_MASK 0x00000001 /**< USB Transaction Complete */ +#define XUSBPS_IXR_UE_MASK 0x00000002 /**< Transaction Error */ +#define XUSBPS_IXR_PC_MASK 0x00000004 /**< Port Change Detect */ +#define XUSBPS_IXR_FRE_MASK 0x00000008 /**< Frame List Rollover */ +#define XUSBPS_IXR_AA_MASK 0x00000020 /**< Async Advance */ +#define XUSBPS_IXR_UR_MASK 0x00000040 /**< RESET Received */ +#define XUSBPS_IXR_SR_MASK 0x00000080 /**< Start of Frame */ +#define XUSBPS_IXR_SLE_MASK 0x00000100 /**< Device Controller Suspend */ +#define XUSBPS_IXR_ULPI_MASK 0x00000400 /**< ULPI IRQ */ +#define XUSBPS_IXR_HCH_MASK 0x00001000 /**< Host Controller Halted + * Read Only */ +#define XUSBPS_IXR_RCL_MASK 0x00002000 /**< USB Reclamation Read Only */ +#define XUSBPS_IXR_PS_MASK 0x00004000 /**< Periodic Sched Status + * Read Only */ +#define XUSBPS_IXR_AS_MASK 0x00008000 /**< Async Sched Status Read only */ +#define XUSBPS_IXR_NAK_MASK 0x00010000 /**< NAK IRQ */ +#define XUSBPS_IXR_UA_MASK 0x00040000 /**< USB Host Async IRQ */ +#define XUSBPS_IXR_UP_MASK 0x00080000 /**< USB Host Periodic IRQ */ +#define XUSBPS_IXR_TI0_MASK 0x01000000 /**< Timer 0 Interrupt */ +#define XUSBPS_IXR_TI1_MASK 0x02000000 /**< Timer 1 Interrupt */ + +#define XUSBPS_IXR_ALL (XUSBPS_IXR_UI_MASK | \ + XUSBPS_IXR_UE_MASK | \ + XUSBPS_IXR_PC_MASK | \ + XUSBPS_IXR_FRE_MASK | \ + XUSBPS_IXR_AA_MASK | \ + XUSBPS_IXR_UR_MASK | \ + XUSBPS_IXR_SR_MASK | \ + XUSBPS_IXR_SLE_MASK | \ + XUSBPS_IXR_ULPI_MASK | \ + XUSBPS_IXR_HCH_MASK | \ + XUSBPS_IXR_RCL_MASK | \ + XUSBPS_IXR_PS_MASK | \ + XUSBPS_IXR_AS_MASK | \ + XUSBPS_IXR_NAK_MASK | \ + XUSBPS_IXR_UA_MASK | \ + XUSBPS_IXR_UP_MASK | \ + XUSBPS_IXR_TI0_MASK | \ + XUSBPS_IXR_TI1_MASK) + /**< Mask for ALL IRQ types */ +/* @} */ + + +/** @name USB Mode Register (MODE) bit positions. + * @{ + */ +#define XUSBPS_MODE_CM_MASK 0x00000003 /**< Controller Mode Select */ +#define XUSBPS_MODE_CM_IDLE_MASK 0x00000000 +#define XUSBPS_MODE_CM_DEVICE_MASK 0x00000002 +#define XUSBPS_MODE_CM_HOST_MASK 0x00000003 +#define XUSBPS_MODE_ES_MASK 0x00000004 /**< USB Endian Select */ +#define XUSBPS_MODE_SLOM_MASK 0x00000008 /**< USB Setup Lockout Mode Disable */ +#define XUSBPS_MODE_SDIS_MASK 0x00000010 +#define XUSBPS_MODE_VALID_MASK 0x0000001F + +/* @} */ + + +/** @name USB Device Address Register (DEVICEADDR) bit positions. + * @{ + */ +#define XUSBPS_DEVICEADDR_DEVICEAADV_MASK 0x01000000 + /**< Device Addr Auto Advance */ +#define XUSBPS_DEVICEADDR_ADDR_MASK 0xFE000000 + /**< Device Address */ +#define XUSBPS_DEVICEADDR_ADDR_SHIFT 25 + /**< Address shift */ +#define XUSBPS_DEVICEADDR_MAX 127 + /**< Biggest allowed address */ +/* @} */ + +/** @name USB TT Control Register (TTCTRL) bit positions. + * @{ + */ +#define XUSBPS_TTCTRL_HUBADDR_MASK 0x7F000000 /**< TT Hub Address */ +/* @} */ + + +/** @name USB Burst Size Register (BURSTSIZE) bit posisions. + * @{ + */ +#define XUSBPS_BURSTSIZE_RX_MASK 0x000000FF /**< RX Burst Length */ +#define XUSBPS_BURSTSIZE_TX_MASK 0x0000FF00 /**< TX Burst Length */ +/* @} */ + + +/** @name USB Tx Fill Tuning Register (TXFILL) bit positions. + * @{ + */ +#define XUSBPS_TXFILL_OVERHEAD_MASK 0x000000FF + /**< Scheduler Overhead */ +#define XUSBPS_TXFILL_HEALTH_MASK 0x00001F00 + /**< Scheduler Health Cntr */ +#define XUSBPS_TXFILL_BURST_MASK 0x003F0000 + /**< FIFO Burst Threshold */ +/* @} */ + + +/** @name USB ULPI Viewport Register (ULPIVIEW) bit positions. + * @{ + */ +#define XUSBPS_ULPIVIEW_DATWR_MASK 0x000000FF /**< ULPI Data Write */ +#define XUSBPS_ULPIVIEW_DATRD_MASK 0x0000FF00 /**< ULPI Data Read */ +#define XUSBPS_ULPIVIEW_ADDR_MASK 0x00FF0000 /**< ULPI Data Address */ +#define XUSBPS_ULPIVIEW_PORT_MASK 0x07000000 /**< ULPI Port Number */ +#define XUSBPS_ULPIVIEW_SS_MASK 0x08000000 /**< ULPI Synchronous State */ +#define XUSBPS_ULPIVIEW_RW_MASK 0x20000000 /**< ULPI Read/Write Control */ +#define XUSBPS_ULPIVIEW_RUN_MASK 0x40000000 /**< ULPI Run */ +#define XUSBPS_ULPIVIEW_WU_MASK 0x80000000 /**< ULPI Wakeup */ +/* @} */ + + +/** @name Port Status Control Register bit positions. + * @{ + */ +#define XUSBPS_PORTSCR_CCS_MASK 0x00000001 /**< Current Connect Status */ +#define XUSBPS_PORTSCR_CSC_MASK 0x00000002 /**< Connect Status Change */ +#define XUSBPS_PORTSCR_PE_MASK 0x00000004 /**< Port Enable/Disable */ +#define XUSBPS_PORTSCR_PEC_MASK 0x00000008 /**< Port Enable/Disable Change */ +#define XUSBPS_PORTSCR_OCA_MASK 0x00000010 /**< Over-current Active */ +#define XUSBPS_PORTSCR_OCC_MASK 0x00000020 /**< Over-current Change */ +#define XUSBPS_PORTSCR_FPR_MASK 0x00000040 /**< Force Port Resume */ +#define XUSBPS_PORTSCR_SUSP_MASK 0x00000080 /**< Suspend */ +#define XUSBPS_PORTSCR_PR_MASK 0x00000100 /**< Port Reset */ +#define XUSBPS_PORTSCR_HSP_MASK 0x00000200 /**< High Speed Port */ +#define XUSBPS_PORTSCR_LS_MASK 0x00000C00 /**< Line Status */ +#define XUSBPS_PORTSCR_PP_MASK 0x00001000 /**< Port Power */ +#define XUSBPS_PORTSCR_PO_MASK 0x00002000 /**< Port Owner */ +#define XUSBPS_PORTSCR_PIC_MASK 0x0000C000 /**< Port Indicator Control */ +#define XUSBPS_PORTSCR_PTC_MASK 0x000F0000 /**< Port Test Control */ +#define XUSBPS_PORTSCR_WKCN_MASK 0x00100000 /**< Wake on Connect Enable */ +#define XUSBPS_PORTSCR_WKDS_MASK 0x00200000 /**< Wake on Disconnect Enable */ +#define XUSBPS_PORTSCR_WKOC_MASK 0x00400000 /**< Wake on Over-current Enable */ +#define XUSBPS_PORTSCR_PHCD_MASK 0x00800000 /**< PHY Low Power Suspend - + * Clock Disable */ +#define XUSBPS_PORTSCR_PFSC_MASK 0x01000000 /**< Port Force Full Speed + * Connect */ +#define XUSBPS_PORTSCR_PSPD_MASK 0x0C000000 /**< Port Speed */ +/* @} */ + + +/** @name On-The-Go Status Control Register (OTGCSR) bit positions. + * @{ + */ +#define XUSBPS_OTGSC_VD_MASK 0x00000001 /**< VBus Discharge Bit */ +#define XUSBPS_OTGSC_VC_MASK 0x00000002 /**< VBus Charge Bit */ +#define XUSBPS_OTGSC_HAAR_MASK 0x00000004 /**< HW Assist Auto Reset + * Enable Bit */ +#define XUSBPS_OTGSC_OT_MASK 0x00000008 /**< OTG Termination Bit */ +#define XUSBPS_OTGSC_DP_MASK 0x00000010 /**< Data Pulsing Pull-up + * Enable Bit */ +#define XUSBPS_OTGSC_IDPU_MASK 0x00000020 /**< ID Pull-up Enable Bit */ +#define XUSBPS_OTGSC_HADP_MASK 0x00000040 /**< HW Assist Data Pulse + * Enable Bit */ +#define XUSBPS_OTGSC_HABA_MASK 0x00000080 /**< USB Hardware Assist + * B Disconnect to A + * Connect Enable Bit */ +#define XUSBPS_OTGSC_ID_MASK 0x00000100 /**< ID Status Flag */ +#define XUSBPS_OTGSC_AVV_MASK 0x00000200 /**< USB A VBus Valid Interrupt Status Flag */ +#define XUSBPS_OTGSC_ASV_MASK 0x00000400 /**< USB A Session Valid Interrupt Status Flag */ +#define XUSBPS_OTGSC_BSV_MASK 0x00000800 /**< USB B Session Valid Status Flag */ +#define XUSBPS_OTGSC_BSE_MASK 0x00001000 /**< USB B Session End Status Flag */ +#define XUSBPS_OTGSC_1MST_MASK 0x00002000 /**< USB 1 Millisecond Timer Status Flag */ +#define XUSBPS_OTGSC_DPS_MASK 0x00004000 /**< Data Pulse Status Flag */ +#define XUSBPS_OTGSC_IDIS_MASK 0x00010000 /**< USB ID Interrupt Status Flag */ +#define XUSBPS_OTGSC_AVVIS_MASK 0x00020000 /**< USB A VBus Valid Interrupt Status Flag */ +#define XUSBPS_OTGSC_ASVIS_MASK 0x00040000 /**< USB A Session Valid Interrupt Status Flag */ +#define XUSBPS_OTGSC_BSVIS_MASK 0x00080000 /**< USB B Session Valid Interrupt Status Flag */ +#define XUSBPS_OTGSC_BSEIS_MASK 0x00100000 /**< USB B Session End Interrupt Status Flag */ +#define XUSBPS_OTGSC_1MSS_MASK 0x00200000 /**< 1 Millisecond Timer Interrupt Status Flag */ +#define XUSBPS_OTGSC_DPIS_MASK 0x00400000 /**< Data Pulse Interrupt Status Flag */ +#define XUSBPS_OTGSC_IDIE_MASK 0x01000000 /**< ID Interrupt Enable Bit */ +#define XUSBPS_OTGSC_AVVIE_MASK 0x02000000 /**< USB A VBus Valid Interrupt Enable Bit */ +#define XUSBPS_OTGSC_ASVIE_MASK 0x04000000 /**< USB A Session Valid Interrupt Enable Bit */ +#define XUSBPS_OTGSC_BSVIE_MASK 0x08000000 /**< USB B Session Valid Interrupt Enable Bit */ +#define XUSBPS_OTGSC_BSEE_MASK 0x10000000 /**< USB B Session End Interrupt Enable Bit */ +#define XUSBPS_OTGSC_1MSE_MASK 0x20000000 /**< 1 Millisecond Timer + * Interrupt Enable Bit */ +#define XUSBPS_OTGSC_DPIE_MASK 0x40000000 /**< Data Pulse Interrupt + * Enable Bit */ + +#define XUSBPS_OTG_ISB_ALL (XUSBPS_OTGSC_IDIS_MASK |\ + XUSBPS_OTGSC_AVVIS_MASK | \ + XUSBPS_OTGSC_ASVIS_MASK | \ + XUSBPS_OTGSC_BSVIS_MASK | \ + XUSBPS_OTGSC_BSEIS_MASK | \ + XUSBPS_OTGSC_1MSS_MASK | \ + XUSBPS_OTGSC_DPIS_MASK) + /** Mask for All IRQ status masks */ + +#define XUSBPS_OTG_IEB_ALL (XUSBPS_OTGSC_IDIE_MASK |\ + XUSBPS_OTGSC_AVVIE_MASK | \ + XUSBPS_OTGSC_ASVIE_MASK | \ + XUSBPS_OTGSC_BSVIE_MASK | \ + XUSBPS_OTGSC_BSEE_IEB_MASK | \ + XUSBPS_OTGSC_1MSE_MASK | \ + XUSBPS_OTGSC_DPIE_MASK) + /** Mask for All IRQ Enable masks */ +/* @} */ + + +/**< Alignment of the Device Queue Head List BASE. */ +#define XUSBPS_dQH_BASE_ALIGN 2048 + +/**< Alignment of a Device Queue Head structure. */ +#define XUSBPS_dQH_ALIGN 64 + +/**< Alignment of a Device Transfer Descriptor structure. */ +#define XUSBPS_dTD_ALIGN 32 + +/**< Size of one RX buffer for a OUT Transfer Descriptor. */ +#define XUSBPS_dTD_BUF_SIZE 4096 + +/**< Maximum size of one RX/TX buffer. */ +#define XUSBPS_dTD_BUF_MAX_SIZE 16*1024 + +/**< Alignment requirement for Transfer Descriptor buffers. */ +#define XUSBPS_dTD_BUF_ALIGN 4096 + + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* This macro reads the given register. +* +* @param BaseAddress is the base address for the USB registers. +* @param RegOffset is the register offset to be read. +* +* @return The 32-bit value of the register. +* +* @note C-style signature: +* u32 XUsbPs_ReadReg(u32 BaseAddress, u32 RegOffset) +* +*****************************************************************************/ +#define XUsbPs_ReadReg(BaseAddress, RegOffset) \ + Xil_In32(BaseAddress + (RegOffset)) + + +/****************************************************************************/ +/** +* +* This macro writes the given register. +* +* @param BaseAddress is the the base address for the USB registers. +* @param RegOffset is the register offset to be written. +* @param Data is the the 32-bit value to write to the register. +* +* @return None. +* +* @note C-style signature: +* void XUsbPs_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) +* + *****************************************************************************/ +#define XUsbPs_WriteReg(BaseAddress, RegOffset, Data) \ + Xil_Out32(BaseAddress + (RegOffset), (Data)) + + +/************************** Function Prototypes ******************************/ +/* + * Perform reset operation to the USB PS interface + */ +void XUsbPs_ResetHw(u32 BaseAddress); +/************************** Variable Definitions ******************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* XUSBPS_L_H */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/Makefile new file mode 100644 index 000000000..55565709b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/Makefile @@ -0,0 +1,40 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES:=*.c +INCLUDEFILES:=*.h + +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) + +libs: banner xcanps_libs clean + +%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling canps" + +xcanps_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} + +.PHONY: include +include: xcanps_includes + +xcanps_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS} diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/xcanps.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/xcanps.c new file mode 100644 index 000000000..e49b0b682 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/xcanps.c @@ -0,0 +1,1164 @@ +/****************************************************************************** +* +* (c) Copyright 2010-11 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcanps.c +* +* Functions in this file are the minimum required functions for the XCanPs +* driver. See xcanps.h for a detailed description of the driver. +* +* @note None. +* +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+* 1.01a bss    12/27/11 Added the APIs XCanPs_SetTxIntrWatermark and
+* 			XCanPs_GetTxIntrWatermark.
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xcanps.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +static void StubHandler(void); + +/*****************************************************************************/ +/* +* +* This function initializes a XCanPs instance/driver. +* +* The initialization entails: +* - Initialize all members of the XCanPs structure. +* - Reset the CAN device. The CAN device will enter Configuration Mode +* immediately after the reset is finished. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param ConfigPtr points to the XCanPs device configuration structure. +* @param EffectiveAddr is the device base address in the virtual memory +* address space. If the address translation is not used then the +* physical address is passed. +* Unexpected errors may occur if the address mapping is changed +* after this function is invoked. +* +* @return XST_SUCCESS always. +* +* @note None. +* +******************************************************************************/ +int XCanPs_CfgInitialize(XCanPs *InstancePtr, XCanPs_Config *ConfigPtr, + u32 EffectiveAddr) +{ + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(ConfigPtr != NULL); + + /* + * Set some default values for instance data, don't indicate the device + * is ready to use until everything has been initialized successfully. + */ + InstancePtr->IsReady = 0; + InstancePtr->CanConfig.BaseAddr = EffectiveAddr; + InstancePtr->CanConfig.DeviceId = ConfigPtr->DeviceId; + + /* + * Set all handlers to stub values, let user configure this data later. + */ + InstancePtr->SendHandler = (XCanPs_SendRecvHandler) StubHandler; + InstancePtr->RecvHandler = (XCanPs_SendRecvHandler) StubHandler; + InstancePtr->ErrorHandler = (XCanPs_ErrorHandler) StubHandler; + InstancePtr->EventHandler = (XCanPs_EventHandler) StubHandler; + + /* + * Indicate the component is now ready to use. + */ + InstancePtr->IsReady = XIL_COMPONENT_IS_READY; + + /* + * Reset the device to get it into its initial state. + */ + XCanPs_Reset(InstancePtr); + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This function resets the CAN device. Calling this function resets the device +* immediately, and any pending transmission or reception is terminated at once. +* Both Object Layer and Transfer Layer are reset. This function does not reset +* the Physical Layer. All registers are reset to the default values, and no +* previous status will be restored. TX FIFO, RX FIFO and TX High Priority +* Buffer are also reset. +* +* When a reset is required due to an internal error, the driver notifies the +* upper layer software of this need through the error status code or interrupts. +* The upper layer software is responsible for calling this Reset function and +* then re-configuring the device. +* +* The CAN device will be in Configuration Mode immediately after this function +* returns. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCanPs_Reset(XCanPs *InstancePtr) +{ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_SRR_OFFSET, \ + XCANPS_SRR_SRST_MASK); +} + +/****************************************************************************/ +/** +* +* This routine returns the current operation mode of the CAN device. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - XCANPS_MODE_CONFIG if the device is in Configuration Mode. +* - XCANPS_MODE_SLEEP if the device is in Sleep Mode. +* - XCANPS_MODE_NORMAL if the device is in Normal Mode. +* - XCANPS_MODE_LOOPBACK if the device is in Loop Back Mode. +* - XCANPS_MODE_SNOOP if the device is in Snoop Mode. +* +* @note None. +* +*****************************************************************************/ +u8 XCanPs_GetMode(XCanPs *InstancePtr) +{ + u32 StatusReg; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + StatusReg = XCanPs_GetStatus(InstancePtr); + + if (StatusReg & XCANPS_SR_CONFIG_MASK) { + return XCANPS_MODE_CONFIG; + + } else if (StatusReg & XCANPS_SR_SLEEP_MASK) { + return XCANPS_MODE_SLEEP; + + } else if (StatusReg & XCANPS_SR_NORMAL_MASK) { + if (StatusReg & XCANPS_SR_SNOOP_MASK) { + return XCANPS_MODE_SNOOP; + } else { + return XCANPS_MODE_NORMAL; + } + } else { + /* + * If this line is reached, the device is in Loop Back Mode. + */ + return XCANPS_MODE_LOOPBACK; + } +} + +/*****************************************************************************/ +/** +* +* This function allows the CAN device to enter one of the following operation +* modes: +* - Configuration Mode: Pass in parameter XCANPS_MODE_CONFIG +* - Sleep Mode: Pass in parameter XCANPS_MODE_SLEEP +* - Normal Mode: Pass in parameter XCANPS_MODE_NORMAL +* - Loop Back Mode: Pass in parameter XCANPS_MODE_LOOPBACK. +* - Snoop Mode: Pass in parameter XCANPS_MODE_SNOOP. +* +* Read the xcanps.h file and device specification for detailed description of +* each operation mode. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param OperationMode specify which operation mode to enter. Valid value +* is any of XCANPS_MODE_* defined in xcanps.h. Multiple modes +* can not be entered at the same time. +* +* @return None. +* +* @note +* +* This function does NOT ensure CAN device enters the specified operation mode +* before it returns the control to the caller. The caller is responsible for +* checking current operation mode using XCanPs_GetMode(). +* +******************************************************************************/ +void XCanPs_EnterMode(XCanPs *InstancePtr, u8 OperationMode) +{ + u8 CurrentMode; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid((OperationMode == XCANPS_MODE_CONFIG) || + (OperationMode == XCANPS_MODE_SLEEP) || + (OperationMode == XCANPS_MODE_NORMAL) || + (OperationMode == XCANPS_MODE_LOOPBACK) || + (OperationMode == XCANPS_MODE_SNOOP)); + + CurrentMode = XCanPs_GetMode(InstancePtr); + + /* + * If current mode is Normal Mode and the mode to enter is Sleep Mode, + * or if current mode is Sleep Mode and the mode to enter is Normal + * Mode, no transition through Configuration Mode is needed. + */ + if ((CurrentMode == XCANPS_MODE_NORMAL) && + (OperationMode == XCANPS_MODE_SLEEP)) { + /* + * Normal Mode ---> Sleep Mode + */ + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_MSR_OFFSET, XCANPS_MSR_SLEEP_MASK); + return; + + } else if ((CurrentMode == XCANPS_MODE_SLEEP) && + (OperationMode == XCANPS_MODE_NORMAL)) { + /* + * Sleep Mode ---> Normal Mode + */ + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_MSR_OFFSET, 0); + return; + } + + + /* + * If the mode transition is not any of the two cases above, CAN must + * enter Configuration Mode before switching into the target operation + * mode. + */ + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_SRR_OFFSET, 0); + + /* + * Check if the device has entered Configuration Mode, if not, return to + * the caller. + */ + if (XCanPs_GetMode(InstancePtr) != XCANPS_MODE_CONFIG) { + return; + } + + switch (OperationMode) { + case XCANPS_MODE_CONFIG: + /* + * As CAN is in Configuration Mode already. + * Nothing is needed to be done here. + */ + break; + + case XCANPS_MODE_SLEEP: + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_MSR_OFFSET, XCANPS_MSR_SLEEP_MASK); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK); + break; + + case XCANPS_MODE_NORMAL: + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_MSR_OFFSET, 0); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK); + break; + + case XCANPS_MODE_LOOPBACK: + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_MSR_OFFSET, XCANPS_MSR_LBACK_MASK); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK); + break; + + case XCANPS_MODE_SNOOP: + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_MSR_OFFSET, XCANPS_MSR_SNOOP_MASK); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK); + break; + + } +} + +/*****************************************************************************/ +/** +* +* This function returns Status value from Status Register (SR). Use the +* XCANPS_SR_* constants defined in xcanps_hw.h to interpret the returned +* value. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return The 32-bit value read from Status Register. +* +* @note None. +* +******************************************************************************/ +u32 XCanPs_GetStatus(XCanPs *InstancePtr) +{ + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_SR_OFFSET); +} + +/*****************************************************************************/ +/** +* +* This function reads Receive and Transmit error counters. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param RxErrorCount is a pointer to data in which the Receive Error +* counter value is returned. +* @param TxErrorCount is a pointer to data in which the Transmit Error +* counter value is returned. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCanPs_GetBusErrorCounter(XCanPs *InstancePtr, u8 *RxErrorCount, + u8 *TxErrorCount) +{ + u32 ErrorCount; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(RxErrorCount != NULL); + Xil_AssertVoid(TxErrorCount != NULL); + /* + * Read Error Counter Register and parse it. + */ + ErrorCount = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_ECR_OFFSET); + *RxErrorCount = (ErrorCount & XCANPS_ECR_REC_MASK) >> + XCANPS_ECR_REC_SHIFT; + *TxErrorCount = ErrorCount & XCANPS_ECR_TEC_MASK; +} + +/*****************************************************************************/ +/** +* +* This function reads Error Status value from Error Status Register (ESR). Use +* the XCANPS_ESR_* constants defined in xcanps_hw.h to interpret the +* returned value. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return The 32-bit value read from Error Status Register. +* +* @note None. +* +******************************************************************************/ +u32 XCanPs_GetBusErrorStatus(XCanPs *InstancePtr) +{ + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_ESR_OFFSET); +} + +/*****************************************************************************/ +/** +* +* This function clears Error Status bit(s) previously set in Error +* Status Register (ESR). Use the XCANPS_ESR_* constants defined in xcanps_hw.h +* to create the value to pass in. If a bit was cleared in Error Status Register +* before this function is called, it will not be modified. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @param Mask is he 32-bit mask used to clear bits in Error Status +* Register. Multiple XCANPS_ESR_* values can be 'OR'ed to clear +* multiple bits. +* +* @note None. +* +******************************************************************************/ +void XCanPs_ClearBusErrorStatus(XCanPs *InstancePtr, u32 Mask) +{ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_ESR_OFFSET, Mask); +} + +/*****************************************************************************/ +/** +* +* This function sends a CAN Frame. If the TX FIFO is not full then the given +* frame is written into the the TX FIFO otherwise, it returns an error code +* immediately. +* This function does not wait for the given frame being sent to CAN bus. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param FramePtr is a pointer to a 32-bit aligned buffer containing the +* CAN frame to be sent. +* +* @return +* - XST_SUCCESS if TX FIFO was not full and the given frame was +* written into the FIFO. +* - XST_FIFO_NO_ROOM if there is no room in the TX FIFO for the +* given frame. +* +* @note None. +* +******************************************************************************/ +int XCanPs_Send(XCanPs *InstancePtr, u32 *FramePtr) +{ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(FramePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (XCanPs_IsTxFifoFull(InstancePtr) == TRUE) { + return XST_FIFO_NO_ROOM; + } + + /* + * Write IDR, DLC, Data Word 1 and Data Word 2 to the CAN device. + */ + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_TXFIFO_ID_OFFSET, FramePtr[0]); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_TXFIFO_DLC_OFFSET, FramePtr[1]); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_TXFIFO_DW1_OFFSET, FramePtr[2]); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_TXFIFO_DW2_OFFSET, FramePtr[3]); + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This function receives a CAN Frame. This function first checks if RX FIFO is +* empty, if not, it then reads a frame from the RX FIFO into the given buffer. +* This function returns error code immediately if there is no frame in the RX +* FIFO. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param FramePtr is a pointer to a 32-bit aligned buffer where the CAN +* frame to be written. +* +* @return +* - XST_SUCCESS if RX FIFO was not empty and a frame was read from +* RX FIFO successfully and written into the given buffer. +* - XST_NO_DATA if there is no frame to be received from the FIFO. +* +* @note None. +* +******************************************************************************/ +int XCanPs_Recv(XCanPs *InstancePtr, u32 *FramePtr) +{ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(FramePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (XCanPs_IsRxEmpty(InstancePtr) == TRUE) { + return XST_NO_DATA; + } + + /* + * Read IDR, DLC, Data Word 1 and Data Word 2 from the CAN device. + */ + FramePtr[0] = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_RXFIFO_ID_OFFSET); + FramePtr[1] = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_RXFIFO_DLC_OFFSET); + FramePtr[2] = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_RXFIFO_DW1_OFFSET); + FramePtr[3] = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_RXFIFO_DW2_OFFSET); + + /* + * Clear RXNEMP bit in ISR. This allows future XCanPs_IsRxEmpty() call + * returns correct RX FIFO occupancy/empty condition. + */ + XCanPs_IntrClear(InstancePtr, XCANPS_IXR_RXNEMP_MASK); + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This routine sends a CAN High Priority frame. This function first checks if +* TX High Priority Buffer is empty. If yes, it then writes the given frame into +* the Buffer. If not, this function returns immediately. This function does not +* wait for the given frame being sent to CAN bus. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param FramePtr is a pointer to a 32-bit aligned buffer containing the +* CAN High Priority frame to be sent. +* +* @return +* - XST_SUCCESS if TX High Priority Buffer was not full and the +* given frame was written into the buffer; +* - XST_FIFO_NO_ROOM if there is no room in the TX High Priority +* Buffer for this frame. +* +* @note +* +* If the frame needs to be sent immediately and not delayed by processor's +* interrupt handling, the caller should disable interrupt at processor +* level before invoking this function. +* +******************************************************************************/ +int XCanPs_SendHighPriority(XCanPs *InstancePtr, u32 *FramePtr) +{ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(FramePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (XCanPs_IsHighPriorityBufFull(InstancePtr) == TRUE) { + return XST_FIFO_NO_ROOM; + } + + /* + * Write IDR, DLC, Data Word 1 and Data Word 2 to the CAN device. + */ + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_TXHPB_ID_OFFSET, FramePtr[0]); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_TXHPB_DLC_OFFSET, FramePtr[1]); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_TXHPB_DW1_OFFSET, FramePtr[2]); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_TXHPB_DW2_OFFSET, FramePtr[3]); + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This routine enables individual acceptance filters. Up to 4 filters could +* be enabled. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param FilterIndexes specifies which filter(s) to enable. Use +* any XCANPS_AFR_UAF*_MASK to enable one filter, and "Or" +* multiple XCANPS_AFR_UAF*_MASK values if multiple filters need +* to be enabled. Any filter not specified in this parameter will +* keep its previous enable/disable setting. +* +* @return None. +* +* @note None. +* +* +******************************************************************************/ +void XCanPs_AcceptFilterEnable(XCanPs *InstancePtr, u32 FilterIndexes) +{ + u32 EnabledFilters; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Calculate the new value and write to AFR. + */ + EnabledFilters = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFR_OFFSET); + EnabledFilters |= FilterIndexes; + EnabledFilters &= XCANPS_AFR_UAF_ALL_MASK; + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_AFR_OFFSET, + EnabledFilters); +} + +/*****************************************************************************/ +/** +* +* This routine disables individual acceptance filters. Up to 4 filters could +* be disabled. If all acceptance filters are disabled then all the received +* frames are stored in the RX FIFO. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param FilterIndexes specifies which filter(s) to disable. Use +* any XCANPS_AFR_UAF*_MASK to disable one filter, and "Or" +* multiple XCANPS_AFR_UAF*_MASK values if multiple filters need +* to be disabled. Any filter not specified in this parameter will +* keep its previous enable/disable setting. If all acceptance +* filters are disabled then all received frames are stored in the +* RX FIFO. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCanPs_AcceptFilterDisable(XCanPs *InstancePtr, u32 FilterIndexes) +{ + u32 EnabledFilters; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Calculate the new value and write to AFR. + */ + EnabledFilters = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFR_OFFSET); + EnabledFilters &= XCANPS_AFR_UAF_ALL_MASK & (~FilterIndexes); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_AFR_OFFSET, + EnabledFilters); +} + +/*****************************************************************************/ +/** +* +* This function returns enabled acceptance filters. Use XCANPS_AFR_UAF*_MASK +* defined in xcanps_hw.h to interpret the returned value. If no acceptance +* filters are enabled then all received frames are stored in the RX FIFO. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return The value stored in Acceptance Filter Register. +* +* @note None. +* +* +******************************************************************************/ +u32 XCanPs_AcceptFilterGetEnabled(XCanPs *InstancePtr) +{ + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFR_OFFSET); + +} + +/*****************************************************************************/ +/** +* +* This function sets values to the Acceptance Filter Mask Register (AFMR) and +* Acceptance Filter ID Register (AFIR) for the specified Acceptance Filter. +* Use XCANPS_IDR_* defined in xcanps_hw.h to create the values to set the +* filter. Read the xcanps.h file and device specification for details. +* +* This function should be called only after: +* - The given filter is disabled by calling XCanPs_AcceptFilterDisable(); +* - And the CAN device is ready to accept writes to AFMR and AFIR, i.e., +* XCanPs_IsAcceptFilterBusy() returns FALSE. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param FilterIndex defines which Acceptance Filter Mask and ID Register +* to set. Use any single XCANPS_AFR_UAF*_MASK value. +* @param MaskValue is the value to write to the chosen Acceptance Filter +* Mask Register. +* @param IdValue is the value to write to the chosen Acceptance Filter +* ID Register. +* +* @return +* - XST_SUCCESS if the values were set successfully. +* - XST_FAILURE if the given filter was not disabled, or the CAN +* device was not ready to accept writes to AFMR and AFIR. +* +* @note None. +* +******************************************************************************/ +int XCanPs_AcceptFilterSet(XCanPs *InstancePtr, u32 FilterIndex, + u32 MaskValue, u32 IdValue) +{ + u32 EnabledFilters; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid((FilterIndex == XCANPS_AFR_UAF4_MASK) || + (FilterIndex == XCANPS_AFR_UAF3_MASK) || + (FilterIndex == XCANPS_AFR_UAF2_MASK) || + (FilterIndex == XCANPS_AFR_UAF1_MASK)); + + /* + * Return an error if the given filter is currently enabled. + */ + EnabledFilters = XCanPs_AcceptFilterGetEnabled(InstancePtr); + if ((EnabledFilters & FilterIndex) == FilterIndex) { + return XST_FAILURE; + } + + /* + * If the CAN device is not ready to accept writes to AFMR and AFIR, + * return error code. + */ + if (XCanPs_IsAcceptFilterBusy(InstancePtr) == TRUE) { + return XST_FAILURE; + } + + /* + * Write to the AFMR and AFIR of the specified filter. + */ + switch (FilterIndex) { + case XCANPS_AFR_UAF1_MASK: /* Acceptance Filter No. 1 */ + + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFMR1_OFFSET, MaskValue); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFIR1_OFFSET, IdValue); + break; + + case XCANPS_AFR_UAF2_MASK: /* Acceptance Filter No. 2 */ + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFMR2_OFFSET, MaskValue); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFIR2_OFFSET, IdValue); + break; + + case XCANPS_AFR_UAF3_MASK: /* Acceptance Filter No. 3 */ + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFMR3_OFFSET, MaskValue); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFIR3_OFFSET, IdValue); + break; + + case XCANPS_AFR_UAF4_MASK: /* Acceptance Filter No. 4 */ + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFMR4_OFFSET, MaskValue); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFIR4_OFFSET, IdValue); + break; + } + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This function reads the values of the Acceptance Filter Mask and ID Register +* for the specified Acceptance Filter. Use XCANPS_IDR_* defined in xcanps_hw.h +* to interpret the values. Read the xcanps.h file and device specification for +* details. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param FilterIndex defines which Acceptance Filter Mask Register to get +* Mask and ID from. Use any single XCANPS_FILTER_* value. +* @param MaskValue is a pointer to the data in which the Mask value read +* from the chosen Acceptance Filter Mask Register is returned. +* @param IdValue is a pointer to the data in which the ID value read +* from the chosen Acceptance Filter ID Register is returned. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCanPs_AcceptFilterGet(XCanPs *InstancePtr, u32 FilterIndex, + u32 *MaskValue, u32 *IdValue) +{ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid((FilterIndex == XCANPS_AFR_UAF4_MASK) || + (FilterIndex == XCANPS_AFR_UAF3_MASK) || + (FilterIndex == XCANPS_AFR_UAF2_MASK) || + (FilterIndex == XCANPS_AFR_UAF1_MASK)); + Xil_AssertVoid(MaskValue != NULL); + Xil_AssertVoid(IdValue != NULL); + + /* + * Read from the AFMR and AFIR of the specified filter. + */ + switch (FilterIndex) { + case XCANPS_AFR_UAF1_MASK: /* Acceptance Filter No. 1 */ + *MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFMR1_OFFSET); + *IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFIR1_OFFSET); + break; + + case XCANPS_AFR_UAF2_MASK: /* Acceptance Filter No. 2 */ + *MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFMR2_OFFSET); + *IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFIR2_OFFSET); + break; + + case XCANPS_AFR_UAF3_MASK: /* Acceptance Filter No. 3 */ + *MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFMR3_OFFSET); + *IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFIR3_OFFSET); + break; + + case XCANPS_AFR_UAF4_MASK: /* Acceptance Filter No. 4 */ + *MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFMR4_OFFSET); + *IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFIR4_OFFSET); + break; + } +} + +/*****************************************************************************/ +/** +* +* This routine sets Baud Rate Prescaler value. The system clock for the CAN +* controller is divided by (Prescaler + 1) to generate the quantum clock +* needed for sampling and synchronization. Read the device specification +* for details. +* +* Baud Rate Prescaler can be set only if the CAN device is in Configuration +* Mode. Call XCanPs_EnterMode() to enter Configuration Mode before using this +* function. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param Prescaler is the value to set. Valid values are from 0 to 255. +* +* @return +* - XST_SUCCESS if the Baud Rate Prescaler value is set +* successfully. +* - XST_FAILURE if CAN device is not in Configuration Mode. +* +* @note None. +* +******************************************************************************/ +int XCanPs_SetBaudRatePrescaler(XCanPs *InstancePtr, u8 Prescaler) +{ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (XCanPs_GetMode(InstancePtr) != XCANPS_MODE_CONFIG) { + return XST_FAILURE; + } + + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_BRPR_OFFSET, + (u32)Prescaler); + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This routine gets Baud Rate Prescaler value. The system clock for the CAN +* controller is divided by (Prescaler + 1) to generate the quantum clock +* needed for sampling and synchronization. Read the device specification for +* details. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return Current used Baud Rate Prescaler value. The value's range is +* from 0 to 255. +* +* @note None. +* +******************************************************************************/ +u8 XCanPs_GetBaudRatePrescaler(XCanPs *InstancePtr) +{ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return (u8) XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_BRPR_OFFSET); + +} + +/*****************************************************************************/ +/** +* +* This routine sets Bit time. Time segment 1, Time segment 2 and +* Synchronization Jump Width are set in this function. Device specification +* requires the values passed into this function be one less than the actual +* values of these fields. Read the device specification for details. +* +* Bit time can be set only if the CAN device is in Configuration Mode. +* Call XCanPs_EnterMode() to enter Configuration Mode before using this +* function. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param SyncJumpWidth is the Synchronization Jump Width value to set. +* Valid values are from 0 to 3. +* @param TimeSegment2 is the Time Segment 2 value to set. Valid values +* are from 0 to 7. +* @param TimeSegment1 is the Time Segment 1 value to set. Valid values +* are from 0 to 15. +* +* @return +* - XST_SUCCESS if the Bit time is set successfully. +* - XST_FAILURE if CAN device is not in Configuration Mode. +* +* @note None. +* +******************************************************************************/ +int XCanPs_SetBitTiming(XCanPs *InstancePtr, u8 SyncJumpWidth, + u8 TimeSegment2, u8 TimeSegment1) +{ + u32 Value; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(SyncJumpWidth <= 3); + Xil_AssertNonvoid(TimeSegment2 <= 7); + Xil_AssertNonvoid(TimeSegment1 <= 15 ); + + if (XCanPs_GetMode(InstancePtr) != XCANPS_MODE_CONFIG) { + return XST_FAILURE; + } + + Value = ((u32) TimeSegment1) & XCANPS_BTR_TS1_MASK; + Value |= (((u32) TimeSegment2) << XCANPS_BTR_TS2_SHIFT) & + XCANPS_BTR_TS2_MASK; + Value |= (((u32) SyncJumpWidth) << XCANPS_BTR_SJW_SHIFT) & + XCANPS_BTR_SJW_MASK; + + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_BTR_OFFSET, Value); + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This routine gets Bit time. Time segment 1, Time segment 2 and +* Synchronization Jump Width values are read in this function. According to +* device specification, the actual value of each of these fields is one +* more than the value read. Read the device specification for details. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param SyncJumpWidth will store the Synchronization Jump Width value +* after this function returns. Its value ranges from 0 to 3. +* @param TimeSegment2 will store the Time Segment 2 value after this +* function returns. Its value ranges from 0 to 7. +* @param TimeSegment1 will store the Time Segment 1 value after this +* function returns. Its value ranges from 0 to 15. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCanPs_GetBitTiming(XCanPs *InstancePtr, u8 *SyncJumpWidth, + u8 *TimeSegment2, u8 *TimeSegment1) +{ + u32 Value; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(SyncJumpWidth != NULL); + Xil_AssertVoid(TimeSegment2 != NULL); + Xil_AssertVoid(TimeSegment1 != NULL); + + Value = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_BTR_OFFSET); + + *TimeSegment1 = (u8) (Value & XCANPS_BTR_TS1_MASK); + *TimeSegment2 = + (u8) ((Value & XCANPS_BTR_TS2_MASK) >> XCANPS_BTR_TS2_SHIFT); + *SyncJumpWidth = + (u8) ((Value & XCANPS_BTR_SJW_MASK) >> XCANPS_BTR_SJW_SHIFT); +} + + +/****************************************************************************/ +/** +* +* This routine sets the Rx Full threshold in the Watermark Interrupt Register. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param Threshold is the threshold to be set. The valid values are +* from 1 to 63. +* +* @return +* - XST_FAILURE - If the CAN device is not in Configuration Mode. +* - XST_SUCCESS - If the Rx Full threshold is set in Watermark +* Interrupt Register. +* +* @note The threshold can only be set when the CAN device is in the +* configuration mode. +* +*****************************************************************************/ +int XCanPs_SetRxIntrWatermark(XCanPs *InstancePtr, u8 Threshold) +{ + + u32 ThrReg; + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(Threshold <= 63); + + if (XCanPs_GetMode(InstancePtr) != XCANPS_MODE_CONFIG) + return XST_FAILURE; + + ThrReg = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_WIR_OFFSET); + + ThrReg &= XCANPS_WIR_EW_MASK; + ThrReg |= ((u32)Threshold & XCANPS_WIR_FW_MASK); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_WIR_OFFSET, ThrReg); + + return XST_SUCCESS; +} + +/****************************************************************************/ +/** +* +* This routine gets the Rx Full threshold from the Watermark Interrupt Register. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return The Rx FIFO full watermark threshold value. The valid values +* are 1 to 63. +* +* @note None. +* +*****************************************************************************/ +u8 XCanPs_GetRxIntrWatermark(XCanPs *InstancePtr) +{ + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + return (u8) (XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_WIR_OFFSET) & + XCANPS_WIR_FW_MASK); +} + + +/****************************************************************************/ +/** +* +* This routine sets the Tx Empty Threshold in the Watermark Interrupt Register. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param Threshold is the threshold to be set. The valid values are +* from 1 to 63. +* +* @return +* - XST_FAILURE - If the CAN device is not in Configuration Mode. +* - XST_SUCCESS - If the threshold is set in Watermark +* Interrupt Register. +* +* @note The threshold can only be set when the CAN device is in the +* configuration mode. +* +*****************************************************************************/ +int XCanPs_SetTxIntrWatermark(XCanPs *InstancePtr, u8 Threshold) +{ + u32 ThrReg; + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(Threshold <= 63); + + if (XCanPs_GetMode(InstancePtr) != XCANPS_MODE_CONFIG) + return XST_FAILURE; + + ThrReg = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_WIR_OFFSET); + + ThrReg &= XCANPS_WIR_FW_MASK; + ThrReg |= ((u32)(Threshold << XCANPS_WIR_EW_SHIFT) + & XCANPS_WIR_EW_MASK); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_WIR_OFFSET, ThrReg); + + return XST_SUCCESS; +} + +/****************************************************************************/ +/** +* +* This routine gets the Tx Empty threshold from Watermark Interrupt Register. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return The Tx Empty FIFO threshold value. The valid values are 1 to 63. +* +* @note None. +* +*****************************************************************************/ +u8 XCanPs_GetTxIntrWatermark(XCanPs *InstancePtr) +{ + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + return (u8) ((XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_WIR_OFFSET) & XCANPS_WIR_EW_MASK) >> + XCANPS_WIR_EW_SHIFT); +} + + + +/******************************************************************************/ +/* + * This routine is a stub for the asynchronous callbacks. The stub is here in + * case the upper layer forgot to set the handler(s). On initialization, all + * handlers are set to this callback. It is considered an error for this handler + * to be invoked. + * + ******************************************************************************/ +static void StubHandler(void) +{ + Xil_AssertVoidAlways(); +} + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/xcanps.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/xcanps.h new file mode 100644 index 000000000..162f3190a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/xcanps.h @@ -0,0 +1,570 @@ +/****************************************************************************** +* +* (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcanps.h +* +* The Xilinx CAN driver component. This component supports the Xilinx +* CAN Controller. +* +* The CAN Controller supports the following features: +* - Confirms to the ISO 11898-1, CAN 2.0A and CAN 2.0B standards. +* - Supports both Standard (11 bit Identifier) and Extended (29 bit +* Identifier) frames. +* - Supports Bit Rates up to 1 Mbps. +* - Transmit message object FIFO with a user configurable depth of +* up to 64 message objects. +* - Transmit prioritization through one TX High Priority Buffer. +* - Receive message object FIFO with a user configurable depth of +* up to 64 message objects. +* - Watermark interrupts for Rx FIFO with configurable Watermark. +* - Acceptance filtering with 4 acceptance filters. +* - Sleep mode with automatic wake up. +* - Loop Back mode for diagnostic applications. +* - Snoop mode for diagnostic applications. +* - Maskable Error and Status Interrupts. +* - Readable Error Counters. +* - External PHY chip required. +* - Receive Timestamp. +* +* The device driver supports all the features listed above, if applicable. +* +* Driver Description +* +* The device driver enables higher layer software (e.g., an application) to +* communicate to the CAN. The driver handles transmission and reception of +* CAN frames, as well as configuration of the controller. The driver is simply a +* pass-through mechanism between a protocol stack and the CAN. A single device +* driver can support multiple CANs. +* +* Since the driver is a simple pass-through mechanism between a protocol stack +* and the CAN, no assembly or disassembly of CAN frames is done at the +* driver-level. This assumes that the protocol stack passes a correctly +* formatted CAN frame to the driver for transmission, and that the driver +* does not validate the contents of an incoming frame +* +* Operation Modes +* +* The CAN controller supports the following modes of operation: +* - Configuration Mode: In this mode the CAN timing parameters and +* Baud Rate Pre-scalar parameters can be changed. In this mode the CAN +* controller loses synchronization with the CAN bus and drives a +* constant recessive bit on the bus line. The Error Counter Register are +* reset. The CAN controller does not receive or transmit any messages +* even if there are pending transmit requests from the TX FIFO or the TX +* High Priority Buffer. The Storage FIFOs and the CAN configuration +* registers are still accessible. +* - Normal Mode:In Normal Mode the CAN controller participates in bus +* communication, by transmitting and receiving messages. +* - Sleep Mode: In Sleep Mode the CAN Controller does not transmit any +* messages. However, if any other node transmits a message, then the CAN +* Controller receives the transmitted message and exits from Sleep Mode. +* If there are new transmission requests from either the TX FIFO or the +* TX High Priority Buffer when the CAN Controller is in Sleep Mode, these +* requests are not serviced, and the CAN Controller continues to remain +* in Sleep Mode. Interrupts are generated when the CAN controller enters +* Sleep mode or Wakes up from Sleep mode. +* - Loop Back Mode: In Loop Back mode, the CAN controller transmits a +* recessive bit stream on to the CAN Bus. Any message that is transmitted +* is looped back to the ‘Rx’ line and acknowledged. The CAN controller +* thus receives any message that it transmits. It does not participate in +* normal bus communication and does not receive any messages that are +* transmitted by other CAN nodes. This mode is used for diagnostic +* purposes. +* - Snoop Mode: In Snoop mode, the CAN controller transmits a +* recessive bit stream on to the CAN Bus and does not participate +* in normal bus communication but receives messages that are transmitted +* by other CAN nodes. This mode is used for diagnostic purposes. +* +* +* Buffer Alignment +* +* It is important to note that frame buffers passed to the driver must be +* 32-bit aligned. +* +* Receive Address Filtering +* +* The device can be set to accept frames whose Identifiers match any of the +* 4 filters set in the Acceptance Filter Mask/ID registers. +* +* The incoming Identifier is masked with the bits in the Acceptance Filter Mask +* Register. This value is compared with the result of masking the bits in the +* Acceptance Filter ID Register with the Acceptance Filter Mask Register. If +* both these values are equal, the message will be stored in the RX FIFO. +* +* Acceptance Filtering is performed by each of the defined acceptance filters. +* If the incoming identifier passes through any acceptance filter then the +* frame is stored in the RX FIFO. +* +* If the Accpetance Filters are not set up then all the received messages are +* stroed in the RX FIFO. +* +* PHY Communication +* +* This driver does not provide any mechanism for directly programming PHY. +* +* Interrupts +* +* The driver has no dependencies on the interrupt controller. The driver +* provides an interrupt handler. User of this driver needs to provide +* callback functions. An interrupt handler example is available with +* the driver. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Device Reset +* +* Bus Off interrupt that can occur in the device requires a device reset. +* The user is responsible for resetting the device and re-configuring it +* based on its needs (the driver does not save the current configuration). +* When integrating into an RTOS, these reset and re-configure obligations are +* taken care of by the OS adapter software if it exists for that RTOS. +* +* Device Configuration +* +* The device can be configured in various ways during the FPGA implementation +* process. Configuration parameters are stored in the xcanps_g.c files. +* A table is defined where each entry contains configuration information +* for a CAN device. This information includes such things as the base address +* of the memory-mapped device. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The XCanPs driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +*

+* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+* 1.01a bss    12/27/11 Added the APIs XCanPs_SetTxIntrWatermark and
+* 			XCanPs_GetTxIntrWatermark.
+*			Updated the Register/bit definitions
+*                       Changed XCANPS_RXFWIR_RXFLL_MASK to XCANPS_WIR_FW_MASK
+*                       Changed XCANPS_RXWIR_OFFSET to XCANPS_WIR_OFFSET
+*			Added XCANPS_IXR_TXFEMP_MASK for Tx Fifo Empty
+*			Changed XCANPS_IXR_RXFLL_MASK to
+*			XCANPS_IXR_RXFWMFLL_MASK
+* 			Changed
+*			XCANPS_TXBUF_ID_OFFSET to XCANPS_TXHPB_ID_OFFSET
+* 			XCANPS_TXBUF_DLC_OFFSET to XCANPS_TXHPB_DLC_OFFSET
+*			XCANPS_TXBUF_DW1_OFFSET to XCANPS_TXHPB_DW1_OFFSET
+*			XCANPS_TXBUF_DW2_OFFSET to XCANPS_TXHPB_DW2_OFFSET
+*
+* +******************************************************************************/ +#ifndef XCANPS_H /* prevent circular inclusions */ +#define XCANPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xcanps_hw.h" + +/************************** Constant Definitions *****************************/ + +/** @name CAN operation modes + * @{ + */ +#define XCANPS_MODE_CONFIG 0x00000001 /**< Configuration mode */ +#define XCANPS_MODE_NORMAL 0x00000002 /**< Normal mode */ +#define XCANPS_MODE_LOOPBACK 0x00000004 /**< Loop Back mode */ +#define XCANPS_MODE_SLEEP 0x00000008 /**< Sleep mode */ +#define XCANPS_MODE_SNOOP 0x00000010 /**< Snoop mode */ +/* @} */ + +/** @name Callback identifiers used as parameters to XCanPs_SetHandler() + * @{ + */ +#define XCANPS_HANDLER_SEND 1 /**< Handler type for frame sending interrupt */ +#define XCANPS_HANDLER_RECV 2 /**< Handler type for frame reception interrupt*/ +#define XCANPS_HANDLER_ERROR 3 /**< Handler type for error interrupt */ +#define XCANPS_HANDLER_EVENT 4 /**< Handler type for all other interrupts */ +/* @} */ + +/**************************** Type Definitions *******************************/ + +/** + * This typedef contains configuration information for a device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddr; /**< Register base address */ +} XCanPs_Config; + +/******************************************************************************/ +/** + * Callback type for frame sending and reception interrupts. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the callback functions, and passed back to the + * upper layer when the callback is invoked. +*******************************************************************************/ +typedef void (*XCanPs_SendRecvHandler) (void *CallBackRef); + +/******************************************************************************/ +/** + * Callback type for error interrupt. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the callback functions, and passed back to the + * upper layer when the callback is invoked. + * @param ErrorMask is a bit mask indicating the cause of the error. Its + * value equals 'OR'ing one or more XCANPS_ESR_* values defined in + * xcanps_hw.h +*******************************************************************************/ +typedef void (*XCanPs_ErrorHandler) (void *CallBackRef, u32 ErrorMask); + +/******************************************************************************/ +/** + * Callback type for all kinds of interrupts except sending frame interrupt, + * receiving frame interrupt, and error interrupt. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the callback functions, and passed back to the + * upper layer when the callback is invoked. + * @param Mask is a bit mask indicating the pending interrupts. Its value + * equals 'OR'ing one or more XCANPS_IXR_* defined in xcanps_hw.h +*******************************************************************************/ +typedef void (*XCanPs_EventHandler) (void *CallBackRef, u32 Mask); + +/** + * The XCanPs driver instance data. The user is required to allocate a + * variable of this type for every CAN device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XCanPs_Config CanConfig; /**< Device configuration */ + u32 IsReady; /**< Device is initialized and ready */ + + /** + * Callback and callback reference for TXOK interrupt. + */ + XCanPs_SendRecvHandler SendHandler; + void *SendRef; + + /** + * Callback and callback reference for RXOK/RXNEMP/RXFLL interrupts. + */ + XCanPs_SendRecvHandler RecvHandler; + void *RecvRef; + + /** + * Callback and callback reference for ERROR interrupt. + */ + XCanPs_ErrorHandler ErrorHandler; + void *ErrorRef; + + /** + * Callback and callback reference for RXOFLW/RXUFLW/TXBFLL/TXFLL/ + * Wakeup/Sleep/Bus off/ARBLST interrupts. + */ + XCanPs_EventHandler EventHandler; + void *EventRef; + +} XCanPs; + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* This macro checks if the transmission is complete. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if the transmission is done. +* - FALSE if the transmission is not done. +* +* @note C-Style signature: +* int XCanPs_IsTxDone(XCanPs *InstancePtr); +* +*******************************************************************************/ +#define XCanPs_IsTxDone(InstancePtr) \ + ((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_ISR_OFFSET) & XCANPS_IXR_TXOK_MASK) ? TRUE : FALSE) + + +/****************************************************************************/ +/** +* +* This macro checks if the transmission FIFO is full. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if TX FIFO is full. +* - FALSE if the TX FIFO is NOT full. +* +* @note C-Style signature: +* int XCanPs_IsTxFifoFull(XCanPs *InstancePtr); +* +*****************************************************************************/ +#define XCanPs_IsTxFifoFull(InstancePtr) \ + ((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_SR_OFFSET) & XCANPS_SR_TXFLL_MASK) ? TRUE : FALSE) + + +/****************************************************************************/ +/** +* +* This macro checks if the Transmission High Priority Buffer is full. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if the TX High Priority Buffer is full. +* - FALSE if the TX High Priority Buffer is NOT full. +* +* @note C-Style signature: +* int XCanPs_IsHighPriorityBufFull(XCanPs *InstancePtr); +* +*****************************************************************************/ +#define XCanPs_IsHighPriorityBufFull(InstancePtr) \ + ((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_SR_OFFSET) & XCANPS_SR_TXBFLL_MASK) ? TRUE : FALSE) + + +/****************************************************************************/ +/** +* +* This macro checks if the receive FIFO is empty. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if RX FIFO is empty. +* - FALSE if the RX FIFO is NOT empty. +* +* @note C-Style signature: +* int XCanPs_IsRxEmpty(XCanPs *InstancePtr); +* +*****************************************************************************/ +#define XCanPs_IsRxEmpty(InstancePtr) \ + ((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_ISR_OFFSET) & XCANPS_IXR_RXNEMP_MASK) ? FALSE : TRUE) + + +/****************************************************************************/ +/** +* +* This macro checks if the CAN device is ready for the driver to change +* Acceptance Filter Identifier Registers (AFIR) and Acceptance Filter Mask +* Registers (AFMR). +* +* AFIR and AFMR for a filter are changeable only after the filter is disabled +* and this routine returns FALSE. The filter can be disabled using the +* XCanPs_AcceptFilterDisable function. +* +* Use the XCanPs_Accept_* functions for configuring the acceptance filters. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if the device is busy and NOT ready to accept writes to +* AFIR and AFMR. +* - FALSE if the device is ready to accept writes to AFIR and +* AFMR. +* +* @note C-Style signature: +* int XCanPs_IsAcceptFilterBusy(XCanPs *InstancePtr); +* +*****************************************************************************/ +#define XCanPs_IsAcceptFilterBusy(InstancePtr) \ + ((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_SR_OFFSET) & XCANPS_SR_ACFBSY_MASK) ? TRUE : FALSE) + + +/****************************************************************************/ +/** +* +* This macro calculates CAN message identifier value given identifier field +* values. +* +* @param StandardId contains Standard Message ID value. +* @param SubRemoteTransReq contains Substitute Remote Transmission +* Request value. +* @param IdExtension contains Identifier Extension value. +* @param ExtendedId contains Extended Message ID value. +* @param RemoteTransReq contains Remote Transmission Request value. +* +* @return Message Identifier value. +* +* @note C-Style signature: +* u32 XCanPs_CreateIdValue(u32 StandardId, +* u32 SubRemoteTransReq, +* u32 IdExtension, u32 ExtendedId, +* u32 RemoteTransReq); +* +* Read the CAN specification for meaning of each parameter. +* +*****************************************************************************/ +#define XCanPs_CreateIdValue(StandardId, SubRemoteTransReq, IdExtension, \ + ExtendedId, RemoteTransReq) \ + ((((StandardId) << XCANPS_IDR_ID1_SHIFT) & XCANPS_IDR_ID1_MASK) | \ + (((SubRemoteTransReq) << XCANPS_IDR_SRR_SHIFT) & XCANPS_IDR_SRR_MASK)|\ + (((IdExtension) << XCANPS_IDR_IDE_SHIFT) & XCANPS_IDR_IDE_MASK) | \ + (((ExtendedId) << XCANPS_IDR_ID2_SHIFT) & XCANPS_IDR_ID2_MASK) | \ + ((RemoteTransReq) & XCANPS_IDR_RTR_MASK)) + + +/****************************************************************************/ +/** +* +* This macro calculates value for Data Length Code register given Data +* Length Code value. +* +* @param DataLengCode indicates Data Length Code value. +* +* @return Value that can be assigned to Data Length Code register. +* +* @note C-Style signature: +* u32 XCanPs_CreateDlcValue(u32 DataLengCode); +* +* Read the CAN specification for meaning of Data Length Code. +* +*****************************************************************************/ +#define XCanPs_CreateDlcValue(DataLengCode) \ + (((DataLengCode) << XCANPS_DLCR_DLC_SHIFT) & XCANPS_DLCR_DLC_MASK) + + +/****************************************************************************/ +/** +* +* This macro clears the timestamp in the Timestamp Control Register. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return None. +* +* @note C-Style signature: +* void XCanPs_ClearTimestamp(XCanPs *InstancePtr); +* +*****************************************************************************/ +#define XCanPs_ClearTimestamp(InstancePtr) \ + XCanPs_WriteReg((InstancePtr)->CanConfig.BaseAddr, \ + XCANPS_TCR_OFFSET, XCANPS_TCR_CTS_MASK) + +/************************** Function Prototypes ******************************/ + +/* + * Functions in xcanps.c + */ +int XCanPs_CfgInitialize(XCanPs *InstancePtr, XCanPs_Config *ConfigPtr, + u32 EffectiveAddr); + +void XCanPs_Reset(XCanPs *InstancePtr); +u8 XCanPs_GetMode(XCanPs *InstancePtr); +void XCanPs_EnterMode(XCanPs *InstancePtr, u8 OperationMode); +u32 XCanPs_GetStatus(XCanPs *InstancePtr); +void XCanPs_GetBusErrorCounter(XCanPs *InstancePtr, u8 *RxErrorCount, + u8 *TxErrorCount); +u32 XCanPs_GetBusErrorStatus(XCanPs *InstancePtr); +void XCanPs_ClearBusErrorStatus(XCanPs *InstancePtr, u32 Mask); +int XCanPs_Send(XCanPs *InstancePtr, u32 *FramePtr); +int XCanPs_Recv(XCanPs *InstancePtr, u32 *FramePtr); +int XCanPs_SendHighPriority(XCanPs *InstancePtr, u32 *FramePtr); +void XCanPs_AcceptFilterEnable(XCanPs *InstancePtr, u32 FilterIndexes); +void XCanPs_AcceptFilterDisable(XCanPs *InstancePtr, u32 FilterIndexes); +u32 XCanPs_AcceptFilterGetEnabled(XCanPs *InstancePtr); +int XCanPs_AcceptFilterSet(XCanPs *InstancePtr, u32 FilterIndex, + u32 MaskValue, u32 IdValue); +void XCanPs_AcceptFilterGet(XCanPs *InstancePtr, u32 FilterIndex, + u32 *MaskValue, u32 *IdValue); + +int XCanPs_SetBaudRatePrescaler(XCanPs *InstancePtr, u8 Prescaler); +u8 XCanPs_GetBaudRatePrescaler(XCanPs *InstancePtr); +int XCanPs_SetBitTiming(XCanPs *InstancePtr, u8 SyncJumpWidth, + u8 TimeSegment2, u8 TimeSegment1); +void XCanPs_GetBitTiming(XCanPs *InstancePtr, u8 *SyncJumpWidth, + u8 *TimeSegment2, u8 *TimeSegment1); + +int XCanPs_SetRxIntrWatermark(XCanPs *InstancePtr, u8 Threshold); +u8 XCanPs_GetRxIntrWatermark(XCanPs *InstancePtr); + +/* + * Diagnostic functions in xcanps_selftest.c + */ +int XCanPs_SelfTest(XCanPs *InstancePtr); + +/* + * Functions in xcanps_intr.c + */ +void XCanPs_IntrEnable(XCanPs *InstancePtr, u32 Mask); +void XCanPs_IntrDisable(XCanPs *InstancePtr, u32 Mask); +u32 XCanPs_IntrGetEnabled(XCanPs *InstancePtr); +u32 XCanPs_IntrGetStatus(XCanPs *InstancePtr); +void XCanPs_IntrClear(XCanPs *InstancePtr, u32 Mask); +void XCanPs_IntrHandler(void *InstancePtr); +int XCanPs_SetHandler(XCanPs *InstancePtr, u32 HandlerType, + void *CallBackFunc, void *CallBackRef); + +/* + * Functions in xcanps_sinit.c + */ +XCanPs_Config *XCanPs_LookupConfig(u16 DeviceId); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/xcanps_g.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/xcanps_g.c new file mode 100644 index 000000000..7f9c4cb7e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/xcanps_g.c @@ -0,0 +1,31 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSM. +* Version: +* DO NOT EDIT. +* +* v (64-bit) +SW Build (by ) on +Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xcanps.h" + +/* +* The configuration table for devices +*/ + +XCanPs_Config XCanPs_ConfigTable[] = +{ + { + XPAR_PS7_CAN_0_DEVICE_ID, + XPAR_PS7_CAN_0_BASEADDR + } +}; + + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/xcanps_hw.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/xcanps_hw.c new file mode 100644 index 000000000..ed6bfccaa --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/xcanps_hw.c @@ -0,0 +1,98 @@ +/****************************************************************************** +* +* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcanps_hw.c +* +* This file contains the implementation of the canps interface reset sequence +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.02a adk  08/08/13 First release
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xparameters.h" +#include "xcanps_hw.h" + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +/*****************************************************************************/ +/** +* +* This function resets the CAN device. Calling this function resets the device +* immediately, and any pending transmission or reception is terminated at once. +* Both Object Layer and Transfer Layer are reset. This function does not reset +* the Physical Layer. All registers are reset to the default values, and no +* previous status will be restored. TX FIFO, RX FIFO and TX High Priority +* Buffer are also reset. +* +* The CAN device will be in Configuration Mode immediately after this function +* returns. +* +* @param BaseAddr is the baseaddress of the interface. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCanPs_ResetHw(u32 BaseAddr) +{ + XCanPs_WriteReg(BaseAddr, XCANPS_SRR_OFFSET, \ + XCANPS_SRR_SRST_MASK); +} \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/xcanps_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/xcanps_hw.h new file mode 100644 index 000000000..22f456f86 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/xcanps_hw.h @@ -0,0 +1,375 @@ +/****************************************************************************** +* +* (c) Copyright 2010-2013 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcanps_hw.h +* +* This header file contains the identifiers and basic driver functions (or +* macros) that can be used to access the device. Other driver functions +* are defined in xcanps.h. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+* 1.01a sbs    12/27/11 Updated the Register/bit definitions
+*                       Changed XCANPS_RXFWIR_RXFLL_MASK to XCANPS_WIR_FW_MASK
+*                       Changed XCANPS_RXWIR_OFFSET to XCANPS_WIR_OFFSET
+*			Added XCANPS_IXR_TXFEMP_MASK for Tx Fifo Empty
+*			Changed XCANPS_IXR_RXFLL_MASK to
+*			XCANPS_IXR_RXFWMFLL_MASK
+* 			Changed
+*			XCANPS_TXBUF_ID_OFFSET to XCANPS_TXHPB_ID_OFFSET
+* 			XCANPS_TXBUF_DLC_OFFSET to XCANPS_TXHPB_DLC_OFFSET
+*			XCANPS_TXBUF_DW1_OFFSET  to XCANPS_TXHPB_DW1_OFFSET
+*			XCANPS_TXBUF_DW2_OFFSET  to XCANPS_TXHPB_DW2_OFFSET
+* 1.02a adk   08/08/13  Updated for inclding the function prototype
+*
+* +******************************************************************************/ + +#ifndef XCANPS_HW_H /* prevent circular inclusions */ +#define XCANPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register offsets for the CAN. Each register is 32 bits. + * @{ + */ +#define XCANPS_SRR_OFFSET 0x00 /**< Software Reset Register */ +#define XCANPS_MSR_OFFSET 0x04 /**< Mode Select Register */ +#define XCANPS_BRPR_OFFSET 0x08 /**< Baud Rate Prescaler */ +#define XCANPS_BTR_OFFSET 0x0C /**< Bit Timing Register */ +#define XCANPS_ECR_OFFSET 0x10 /**< Error Counter Register */ +#define XCANPS_ESR_OFFSET 0x14 /**< Error Status Register */ +#define XCANPS_SR_OFFSET 0x18 /**< Status Register */ + +#define XCANPS_ISR_OFFSET 0x1C /**< Interrupt Status Register */ +#define XCANPS_IER_OFFSET 0x20 /**< Interrupt Enable Register */ +#define XCANPS_ICR_OFFSET 0x24 /**< Interrupt Clear Register */ +#define XCANPS_TCR_OFFSET 0x28 /**< Timestamp Control Register */ +#define XCANPS_WIR_OFFSET 0x2C /**< Watermark Interrupt Reg */ + +#define XCANPS_TXFIFO_ID_OFFSET 0x30 /**< TX FIFO ID */ +#define XCANPS_TXFIFO_DLC_OFFSET 0x34 /**< TX FIFO DLC */ +#define XCANPS_TXFIFO_DW1_OFFSET 0x38 /**< TX FIFO Data Word 1 */ +#define XCANPS_TXFIFO_DW2_OFFSET 0x3C /**< TX FIFO Data Word 2 */ + +#define XCANPS_TXHPB_ID_OFFSET 0x40 /**< TX High Priority Buffer ID */ +#define XCANPS_TXHPB_DLC_OFFSET 0x44 /**< TX High Priority Buffer DLC */ +#define XCANPS_TXHPB_DW1_OFFSET 0x48 /**< TX High Priority Buf Data 1 */ +#define XCANPS_TXHPB_DW2_OFFSET 0x4C /**< TX High Priority Buf Data Word 2 */ + +#define XCANPS_RXFIFO_ID_OFFSET 0x50 /**< RX FIFO ID */ +#define XCANPS_RXFIFO_DLC_OFFSET 0x54 /**< RX FIFO DLC */ +#define XCANPS_RXFIFO_DW1_OFFSET 0x58 /**< RX FIFO Data Word 1 */ +#define XCANPS_RXFIFO_DW2_OFFSET 0x5C /**< RX FIFO Data Word 2 */ + +#define XCANPS_AFR_OFFSET 0x60 /**< Acceptance Filter Register */ +#define XCANPS_AFMR1_OFFSET 0x64 /**< Acceptance Filter Mask 1 */ +#define XCANPS_AFIR1_OFFSET 0x68 /**< Acceptance Filter ID 1 */ +#define XCANPS_AFMR2_OFFSET 0x6C /**< Acceptance Filter Mask 2 */ +#define XCANPS_AFIR2_OFFSET 0x70 /**< Acceptance Filter ID 2 */ +#define XCANPS_AFMR3_OFFSET 0x74 /**< Acceptance Filter Mask 3 */ +#define XCANPS_AFIR3_OFFSET 0x78 /**< Acceptance Filter ID 3 */ +#define XCANPS_AFMR4_OFFSET 0x7C /**< Acceptance Filter Mask 4 */ +#define XCANPS_AFIR4_OFFSET 0x80 /**< Acceptance Filter ID 4 */ +/* @} */ + +/** @name Software Reset Register (SRR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_SRR_CEN_MASK 0x00000002 /**< Can Enable */ +#define XCANPS_SRR_SRST_MASK 0x00000001 /**< Reset */ +/* @} */ + +/** @name Mode Select Register (MSR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_MSR_SNOOP_MASK 0x00000004 /**< Snoop Mode Select */ +#define XCANPS_MSR_LBACK_MASK 0x00000002 /**< Loop Back Mode Select */ +#define XCANPS_MSR_SLEEP_MASK 0x00000001 /**< Sleep Mode Select */ +/* @} */ + +/** @name Baud Rate Prescaler register (BRPR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_BRPR_BRP_MASK 0x000000FF /**< Baud Rate Prescaler */ +/* @} */ + +/** @name Bit Timing Register (BTR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_BTR_SJW_MASK 0x00000180 /**< Synchronization Jump Width */ +#define XCANPS_BTR_SJW_SHIFT 7 +#define XCANPS_BTR_TS2_MASK 0x00000070 /**< Time Segment 2 */ +#define XCANPS_BTR_TS2_SHIFT 4 +#define XCANPS_BTR_TS1_MASK 0x0000000F /**< Time Segment 1 */ +/* @} */ + +/** @name Error Counter Register (ECR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_ECR_REC_MASK 0x0000FF00 /**< Receive Error Counter */ +#define XCANPS_ECR_REC_SHIFT 8 +#define XCANPS_ECR_TEC_MASK 0x000000FF /**< Transmit Error Counter */ +/* @} */ + +/** @name Error Status Register (ESR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_ESR_ACKER_MASK 0x00000010 /**< ACK Error */ +#define XCANPS_ESR_BERR_MASK 0x00000008 /**< Bit Error */ +#define XCANPS_ESR_STER_MASK 0x00000004 /**< Stuff Error */ +#define XCANPS_ESR_FMER_MASK 0x00000002 /**< Form Error */ +#define XCANPS_ESR_CRCER_MASK 0x00000001 /**< CRC Error */ +/* @} */ + +/** @name Status Register (SR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_SR_SNOOP_MASK 0x00001000 /**< Snoop Mask */ +#define XCANPS_SR_ACFBSY_MASK 0x00000800 /**< Acceptance Filter busy */ +#define XCANPS_SR_TXFLL_MASK 0x00000400 /**< TX FIFO is full */ +#define XCANPS_SR_TXBFLL_MASK 0x00000200 /**< TX High Priority Buffer full */ +#define XCANPS_SR_ESTAT_MASK 0x00000180 /**< Error Status */ +#define XCANPS_SR_ESTAT_SHIFT 7 +#define XCANPS_SR_ERRWRN_MASK 0x00000040 /**< Error Warning */ +#define XCANPS_SR_BBSY_MASK 0x00000020 /**< Bus Busy */ +#define XCANPS_SR_BIDLE_MASK 0x00000010 /**< Bus Idle */ +#define XCANPS_SR_NORMAL_MASK 0x00000008 /**< Normal Mode */ +#define XCANPS_SR_SLEEP_MASK 0x00000004 /**< Sleep Mode */ +#define XCANPS_SR_LBACK_MASK 0x00000002 /**< Loop Back Mode */ +#define XCANPS_SR_CONFIG_MASK 0x00000001 /**< Configuration Mode */ +/* @} */ + +/** @name Interrupt Status/Enable/Clear Register Bit Definitions and Masks + * @{ + */ +#define XCANPS_IXR_TXFEMP_MASK 0x00004000 /**< Tx Fifo Empty Interrupt */ +#define XCANPS_IXR_TXFWMEMP_MASK 0x00002000 /**< Tx Fifo Watermark Empty */ +#define XCANPS_IXR_RXFWMFLL_MASK 0x00001000 /**< Rx FIFO Watermark Full */ +#define XCANPS_IXR_WKUP_MASK 0x00000800 /**< Wake up Interrupt */ +#define XCANPS_IXR_SLP_MASK 0x00000400 /**< Sleep Interrupt */ +#define XCANPS_IXR_BSOFF_MASK 0x00000200 /**< Bus Off Interrupt */ +#define XCANPS_IXR_ERROR_MASK 0x00000100 /**< Error Interrupt */ +#define XCANPS_IXR_RXNEMP_MASK 0x00000080 /**< RX FIFO Not Empty Interrupt */ +#define XCANPS_IXR_RXOFLW_MASK 0x00000040 /**< RX FIFO Overflow Interrupt */ +#define XCANPS_IXR_RXUFLW_MASK 0x00000020 /**< RX FIFO Underflow Interrupt */ +#define XCANPS_IXR_RXOK_MASK 0x00000010 /**< New Message Received Intr */ +#define XCANPS_IXR_TXBFLL_MASK 0x00000008 /**< TX High Priority Buf Full */ +#define XCANPS_IXR_TXFLL_MASK 0x00000004 /**< TX FIFO Full Interrupt */ +#define XCANPS_IXR_TXOK_MASK 0x00000002 /**< TX Successful Interrupt */ +#define XCANPS_IXR_ARBLST_MASK 0x00000001 /**< Arbitration Lost Interrupt */ +#define XCANPS_IXR_ALL (XCANPS_IXR_RXFWMFLL_MASK | \ + XCANPS_IXR_WKUP_MASK | \ + XCANPS_IXR_SLP_MASK | \ + XCANPS_IXR_BSOFF_MASK | \ + XCANPS_IXR_ERROR_MASK | \ + XCANPS_IXR_RXNEMP_MASK | \ + XCANPS_IXR_RXOFLW_MASK | \ + XCANPS_IXR_RXUFLW_MASK | \ + XCANPS_IXR_RXOK_MASK | \ + XCANPS_IXR_TXBFLL_MASK | \ + XCANPS_IXR_TXFLL_MASK | \ + XCANPS_IXR_TXOK_MASK | \ + XCANPS_IXR_ARBLST_MASK) +/* @} */ + +/** @name CAN Timestamp Control Register (TCR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_TCR_CTS_MASK 0x00000001 /**< Clear Timestamp counter mask */ +/* @} */ + +/** @name CAN Watermark Register (WIR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_WIR_FW_MASK 0x0000003F /**< Rx Full Threshold mask */ +#define XCANPS_WIR_EW_MASK 0x00003F00 /**< Tx Empty Threshold mask */ +#define XCANPS_WIR_EW_SHIFT 0x00000008 /**< Tx Empty Threshold shift */ + +/* @} */ + +/** @name CAN Frame Identifier (TX High Priority Buffer/TX/RX/Acceptance Filter + Mask/Acceptance Filter ID) + * @{ + */ +#define XCANPS_IDR_ID1_MASK 0xFFE00000 /**< Standard Messg Identifier */ +#define XCANPS_IDR_ID1_SHIFT 21 +#define XCANPS_IDR_SRR_MASK 0x00100000 /**< Substitute Remote TX Req */ +#define XCANPS_IDR_SRR_SHIFT 20 +#define XCANPS_IDR_IDE_MASK 0x00080000 /**< Identifier Extension */ +#define XCANPS_IDR_IDE_SHIFT 19 +#define XCANPS_IDR_ID2_MASK 0x0007FFFE /**< Extended Message Ident */ +#define XCANPS_IDR_ID2_SHIFT 1 +#define XCANPS_IDR_RTR_MASK 0x00000001 /**< Remote TX Request */ +/* @} */ + +/** @name CAN Frame Data Length Code (TX High Priority Buffer/TX/RX) + * @{ + */ +#define XCANPS_DLCR_DLC_MASK 0xF0000000 /**< Data Length Code */ +#define XCANPS_DLCR_DLC_SHIFT 28 +#define XCANPS_DLCR_TIMESTAMP_MASK 0x0000FFFF /**< Timestamp Mask (Rx only) */ + +/* @} */ + +/** @name CAN Frame Data Word 1 (TX High Priority Buffer/TX/RX) + * @{ + */ +#define XCANPS_DW1R_DB0_MASK 0xFF000000 /**< Data Byte 0 */ +#define XCANPS_DW1R_DB0_SHIFT 24 +#define XCANPS_DW1R_DB1_MASK 0x00FF0000 /**< Data Byte 1 */ +#define XCANPS_DW1R_DB1_SHIFT 16 +#define XCANPS_DW1R_DB2_MASK 0x0000FF00 /**< Data Byte 2 */ +#define XCANPS_DW1R_DB2_SHIFT 8 +#define XCANPS_DW1R_DB3_MASK 0x000000FF /**< Data Byte 3 */ +/* @} */ + +/** @name CAN Frame Data Word 2 (TX High Priority Buffer/TX/RX) + * @{ + */ +#define XCANPS_DW2R_DB4_MASK 0xFF000000 /**< Data Byte 4 */ +#define XCANPS_DW2R_DB4_SHIFT 24 +#define XCANPS_DW2R_DB5_MASK 0x00FF0000 /**< Data Byte 5 */ +#define XCANPS_DW2R_DB5_SHIFT 16 +#define XCANPS_DW2R_DB6_MASK 0x0000FF00 /**< Data Byte 6 */ +#define XCANPS_DW2R_DB6_SHIFT 8 +#define XCANPS_DW2R_DB7_MASK 0x000000FF /**< Data Byte 7 */ +/* @} */ + +/** @name Acceptance Filter Register (AFR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_AFR_UAF4_MASK 0x00000008 /**< Use Acceptance Filter No.4 */ +#define XCANPS_AFR_UAF3_MASK 0x00000004 /**< Use Acceptance Filter No.3 */ +#define XCANPS_AFR_UAF2_MASK 0x00000002 /**< Use Acceptance Filter No.2 */ +#define XCANPS_AFR_UAF1_MASK 0x00000001 /**< Use Acceptance Filter No.1 */ +#define XCANPS_AFR_UAF_ALL_MASK (XCANPS_AFR_UAF4_MASK | \ + XCANPS_AFR_UAF3_MASK | \ + XCANPS_AFR_UAF2_MASK | \ + XCANPS_AFR_UAF1_MASK) +/* @} */ + +/** @name CAN frame length constants + * @{ + */ +#define XCANPS_MAX_FRAME_SIZE 16 /**< Maximum CAN frame length in bytes */ +/* @} */ + +/* For backwards compatibilty */ +#define XCANPS_TXBUF_ID_OFFSET XCANPS_TXHPB_ID_OFFSET +#define XCANPS_TXBUF_DLC_OFFSET XCANPS_TXHPB_DLC_OFFSET +#define XCANPS_TXBUF_DW1_OFFSET XCANPS_TXHPB_DW1_OFFSET +#define XCANPS_TXBUF_DW2_OFFSET XCANPS_TXHPB_DW2_OFFSET + +#define XCANPS_RXFWIR_RXFLL_MASK XCANPS_WIR_FW_MASK +#define XCANPS_RXWIR_OFFSET XCANPS_WIR_OFFSET +#define XCANPS_IXR_RXFLL_MASK XCANPS_IXR_RXFWMFLL_MASK + + + + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* This macro reads the given register. +* +* @param BaseAddr is the base address of the device. +* @param RegOffset is the register offset to be read. +* +* @return The 32-bit value of the register +* +* @note None. +* +*****************************************************************************/ +#define XCanPs_ReadReg(BaseAddr, RegOffset) \ + Xil_In32((BaseAddr) + (RegOffset)) + + +/****************************************************************************/ +/** +* +* This macro writes the given register. +* +* @param BaseAddr is the base address of the device. +* @param RegOffset is the register offset to be written. +* @param Data is the 32-bit value to write to the register. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#define XCanPs_WriteReg(BaseAddr, RegOffset, Data) \ + Xil_Out32((BaseAddr) + (RegOffset), (Data)) + +/************************** Function Prototypes ******************************/ +/* + * Perform reset operation to the CanPs interface + */ +void XCanPs_ResetHw(u32 BaseAddr); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/xcanps_intr.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/xcanps_intr.c new file mode 100644 index 000000000..991af856d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/xcanps_intr.c @@ -0,0 +1,412 @@ +/****************************************************************************** +* +* (c) Copyright 2010-11 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcanps_intr.c +* +* This file contains functions related to CAN interrupt handling. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xcanps.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +/****************************************************************************/ +/** +* +* This routine enables interrupt(s). Use the XCANPS_IXR_* constants defined in +* xcanps_hw.h to create the bit-mask to enable interrupts. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param Mask is the mask to enable. Bit positions of 1 will be enabled. +* Bit positions of 0 will keep the previous setting. This mask is +* formed by OR'ing XCANPS_IXR_* bits defined in xcanps_hw.h. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XCanPs_IntrEnable(XCanPs *InstancePtr, u32 Mask) +{ + u32 IntrValue; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Write to the IER to enable the specified interrupts. + */ + IntrValue = XCanPs_IntrGetEnabled(InstancePtr); + IntrValue |= Mask & XCANPS_IXR_ALL; + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_IER_OFFSET, IntrValue); +} + +/****************************************************************************/ +/** +* +* This routine disables interrupt(s). Use the XCANPS_IXR_* constants defined in +* xcanps_hw.h to create the bit-mask to disable interrupt(s). +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param Mask is the mask to disable. Bit positions of 1 will be +* disabled. Bit positions of 0 will keep the previous setting. +* This mask is formed by OR'ing XCANPS_IXR_* bits defined in +* xcanps_hw.h. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XCanPs_IntrDisable(XCanPs *InstancePtr, u32 Mask) +{ + u32 IntrValue; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Write to the IER to disable the specified interrupts. + */ + IntrValue = XCanPs_IntrGetEnabled(InstancePtr); + IntrValue &= ~Mask; + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_IER_OFFSET, IntrValue); +} + +/****************************************************************************/ +/** +* +* This routine returns enabled interrupt(s). Use the XCANPS_IXR_* constants +* defined in xcanps_hw.h to interpret the returned value. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return Enabled interrupt(s) in a 32-bit format. +* +* @note None. +* +*****************************************************************************/ +u32 XCanPs_IntrGetEnabled(XCanPs *InstancePtr) +{ + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_IER_OFFSET); +} + + +/****************************************************************************/ +/** +* +* This routine returns interrupt status read from Interrupt Status Register. +* Use the XCANPS_IXR_* constants defined in xcanps_hw.h to interpret the +* returned value. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return The value stored in Interrupt Status Register. +* +* @note None. +* +*****************************************************************************/ +u32 XCanPs_IntrGetStatus(XCanPs *InstancePtr) +{ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_ISR_OFFSET); +} + +/****************************************************************************/ +/** +* +* This function clears interrupt(s). Every bit set in Interrupt Status +* Register indicates that a specific type of interrupt is occurring, and this +* function clears one or more interrupts by writing a bit mask to Interrupt +* Clear Register. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param Mask is the mask to clear. Bit positions of 1 will be cleared. +* Bit positions of 0 will not change the previous interrupt +* status. This mask is formed by OR'ing XCANPS_IXR_* bits defined +* in xcanps_hw.h. +* +* @note None. +* +*****************************************************************************/ +void XCanPs_IntrClear(XCanPs *InstancePtr, u32 Mask) +{ + u32 IntrValue; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Clear the currently pending interrupts. + */ + IntrValue = XCanPs_IntrGetStatus(InstancePtr); + IntrValue &= Mask; + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_ICR_OFFSET, + IntrValue); +} + +/*****************************************************************************/ +/** +* +* This routine is the interrupt handler for the CAN driver. +* +* This handler reads the interrupt status from the ISR, determines the source of +* the interrupts, calls according callbacks, and finally clears the interrupts. +* +* Application beyond this driver is responsible for providing callbacks to +* handle interrupts and installing the callbacks using XCanPs_SetHandler() +* during initialization phase. An example delivered with this driver +* demonstrates how this could be done. +* +* @param InstancePtr is a pointer to the XCanPs instance that just +* interrupted. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCanPs_IntrHandler(void *InstancePtr) +{ + u32 PendingIntr; + u32 EventIntr; + u32 ErrorStatus; + XCanPs *CanPtr = (XCanPs *) InstancePtr; + + Xil_AssertVoid(CanPtr != NULL); + Xil_AssertVoid(CanPtr->IsReady == XIL_COMPONENT_IS_READY); + + PendingIntr = XCanPs_IntrGetStatus(CanPtr); + PendingIntr &= XCanPs_IntrGetEnabled(CanPtr); + + /* + * Clear all pending interrupts. + * Rising Edge interrupt + */ + XCanPs_IntrClear(CanPtr, PendingIntr); + + /* + * An error interrupt is occurring. + */ + if ((PendingIntr & XCANPS_IXR_ERROR_MASK)) { + ErrorStatus = XCanPs_GetBusErrorStatus(CanPtr); + CanPtr->ErrorHandler(CanPtr->ErrorRef, ErrorStatus); + + /* + * Clear Error Status Register. + */ + XCanPs_ClearBusErrorStatus(CanPtr, ErrorStatus); + } + + /* + * Check if any following event interrupt is pending: + * - RX FIFO Overflow + * - RX FIFO Underflow + * - TX High Priority Buffer full + * - TX FIFO Full + * - Wake up from sleep mode + * - Enter sleep mode + * - Enter Bus off status + * - Arbitration is lost + * + * If so, call event callback provided by upper level. + */ + EventIntr = PendingIntr & (XCANPS_IXR_RXOFLW_MASK | + XCANPS_IXR_RXUFLW_MASK | + XCANPS_IXR_TXBFLL_MASK | + XCANPS_IXR_TXFLL_MASK | + XCANPS_IXR_WKUP_MASK | + XCANPS_IXR_SLP_MASK | + XCANPS_IXR_BSOFF_MASK | + XCANPS_IXR_ARBLST_MASK); + if (EventIntr) { + CanPtr->EventHandler(CanPtr->EventRef, EventIntr); + + if ((EventIntr & XCANPS_IXR_BSOFF_MASK)) { + /* + * Event callback should reset whole device if "Enter + * Bus Off Status" interrupt occurred. All pending + * interrupts are cleared and no further checking and + * handling of other interrupts is needed any more. + */ + return; + } + } + + + if ((PendingIntr & (XCANPS_IXR_RXFWMFLL_MASK | + XCANPS_IXR_RXNEMP_MASK))) { + + /* + * This case happens when + * A number of frames depending on the Rx FIFO Watermark + * threshold are received. + * And also when frame was received and is sitting in RX FIFO. + * + * XCANPS_IXR_RXOK_MASK is not used because the bit is set + * just once even if there are multiple frames sitting + * in the RX FIFO. + * + * XCANPS_IXR_RXNEMP_MASK is used because the bit can be + * set again and again automatically as long as there is + * at least one frame in RX FIFO. + */ + CanPtr->RecvHandler(CanPtr->RecvRef); + } + + /* + * A frame was transmitted successfully. + */ + if ((PendingIntr & XCANPS_IXR_TXOK_MASK)) { + CanPtr->SendHandler(CanPtr->SendRef); + } +} + + +/*****************************************************************************/ +/** +* +* This routine installs an asynchronous callback function for the given +* HandlerType: +* +* 
+* HandlerType			Callback Function Type
+* -----------------------	------------------------
+* XCANPS_HANDLER_SEND		XCanPs_SendRecvHandler
+* XCANPS_HANDLER_RECV		XCanPs_SendRecvHandler
+* XCANPS_HANDLER_ERROR		XCanPs_ErrorHandler
+* XCANPS_HANDLER_EVENT		XCanPs_EventHandler
+*
+* HandlerType			Invoked by this driver when:
+* -------------------------------------------------------------------------
+* XCANPS_HANDLER_SEND		A frame transmitted by a call to
+*				XCanPs_Send() has been sent successfully.
+*
+* XCANPS_HANDLER_RECV		A frame(s) has been received and is sitting in
+*				the RX FIFO.
+*
+* XCANPS_HANDLER_ERROR		An error interrupt is occurring.
+*
+* XCANPS_HANDLER_EVENT		Any other kind of interrupt is occurring.
+*
+* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param HandlerType specifies which handler is to be attached. +* @param CallBackFunc is the address of the callback function. +* @param CallBackRef is a user data item that will be passed to the +* callback function when it is invoked. +* +* @return +* - XST_SUCCESS when handler is installed. +* - XST_INVALID_PARAM when HandlerType is invalid. +* +* @note +* Invoking this function for a handler that already has been installed replaces +* it with the new handler. +* +******************************************************************************/ +int XCanPs_SetHandler(XCanPs *InstancePtr, u32 HandlerType, + void *CallBackFunc, void *CallBackRef) +{ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + switch (HandlerType) { + case XCANPS_HANDLER_SEND: + InstancePtr->SendHandler = + (XCanPs_SendRecvHandler) CallBackFunc; + InstancePtr->SendRef = CallBackRef; + break; + + case XCANPS_HANDLER_RECV: + InstancePtr->RecvHandler = + (XCanPs_SendRecvHandler) CallBackFunc; + InstancePtr->RecvRef = CallBackRef; + break; + + case XCANPS_HANDLER_ERROR: + InstancePtr->ErrorHandler = (XCanPs_ErrorHandler) CallBackFunc; + InstancePtr->ErrorRef = CallBackRef; + break; + + case XCANPS_HANDLER_EVENT: + InstancePtr->EventHandler = (XCanPs_EventHandler) CallBackFunc; + InstancePtr->EventRef = CallBackRef; + break; + + default: + return (XST_INVALID_PARAM); + + } + return (XST_SUCCESS); +} + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/xcanps_selftest.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/xcanps_selftest.c new file mode 100644 index 000000000..f4faf903a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/xcanps_selftest.c @@ -0,0 +1,216 @@ +/****************************************************************************** +* +* (c) Copyright 2010-11 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcanps_selftest.c +* +* This file contains a diagnostic self-test function for the XCanPs driver. +* +* Read xcanps.h file for more information. +* +* @note +* The Baud Rate Prescaler Register (BRPR) and Bit Timing Register(BTR) +* are setup such that CAN baud rate equals 40Kbps, given the CAN clock +* equal to 24MHz. These need to be changed based on the desired baudrate +* and CAN clock frequency. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+*
+* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xstatus.h" +#include "xcanps.h" + +/************************** Constant Definitions ****************************/ + +#define XCANPS_MAX_FRAME_SIZE_IN_WORDS (XCANPS_MAX_FRAME_SIZE / sizeof(u32)) + +#define FRAME_DATA_LENGTH 8 /* Frame Data field length */ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Variable Definitions ****************************/ + +/* + * Buffers to hold frames to send and receive. These are declared as global so + * that they are not on the stack. + */ +static u32 TxFrame[XCANPS_MAX_FRAME_SIZE_IN_WORDS]; +static u32 RxFrame[XCANPS_MAX_FRAME_SIZE_IN_WORDS]; + +/************************** Function Prototypes *****************************/ + +/*****************************************************************************/ +/** +* +* This function runs a self-test on the CAN driver/device. The test resets +* the device, sets up the Loop Back mode, sends a standard frame, receives the +* frame, verifies the contents, and resets the device again. +* +* Note that this is a destructive test in that resets of the device are +* performed. Refer the device specification for the device status after +* the reset operation. +* +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - XST_SUCCESS if the self-test passed. i.e., the frame +* received via the internal loop back has the same contents as +* the frame sent. +* - XST_FAILURE Otherwise. +* +* @note +* +* If the CAN device does not work properly, this function may enter an +* infinite loop and will never return to the caller. +*

+* If XST_FAILURE is returned, the device is not reset so that the caller could +* have a chance to check reason(s) causing the failure. +* +******************************************************************************/ +int XCanPs_SelfTest(XCanPs *InstancePtr) +{ + u8 *FramePtr; + u32 Status; + u32 Index; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XCanPs_Reset(InstancePtr); + + /* + * The device should enter Configuration Mode immediately after + * reset above is finished. Now check the mode and return error code if + * it is not Configuration Mode. + */ + if (XCanPs_GetMode(InstancePtr) != XCANPS_MODE_CONFIG) { + return XST_FAILURE; + } + + /* + * Setup Baud Rate Prescaler Register (BRPR) and Bit Timing Register + * (BTR) such that CAN baud rate equals 40Kbps, given the CAN clock + * equal to 24MHz. For more information see the CAN 2.0A, CAN 2.0B, + * ISO 11898-1 specifications. + */ + XCanPs_SetBaudRatePrescaler(InstancePtr, 1); + XCanPs_SetBitTiming(InstancePtr, 1, 3, 8); + + /* + * Enter the loop back mode. + */ + XCanPs_EnterMode(InstancePtr, XCANPS_MODE_LOOPBACK); + while (XCanPs_GetMode(InstancePtr) != XCANPS_MODE_LOOPBACK); + + /* + * Create a frame to send with known values so we can verify them + * on receive. + */ + TxFrame[0] = (u32)XCanPs_CreateIdValue((u32)2000, 0, 0, 0, 0); + TxFrame[1] = (u32)XCanPs_CreateDlcValue((u32)8); + + FramePtr = (u8 *) (&TxFrame[2]); + for (Index = 0; Index < 8; Index++) { + *FramePtr++ = (u8) Index; + } + + /* + * Send the frame. + */ + Status = XCanPs_Send(InstancePtr, TxFrame); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* + * Wait until the frame arrives RX FIFO via internal loop back. + */ + while (XCanPs_IsRxEmpty(InstancePtr) == TRUE); + + /* + * Receive the frame. + */ + Status = XCanPs_Recv(InstancePtr, RxFrame); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* + * Verify Identifier and Data Length Code. + */ + if (RxFrame[0] != + (u32)XCanPs_CreateIdValue((u32)2000, 0, 0, 0, 0)) { + return XST_FAILURE; + } + + if ((RxFrame[1] & ~XCANPS_DLCR_TIMESTAMP_MASK) != TxFrame[1]) { + return XST_FAILURE; + } + + + for (Index = 2; Index < XCANPS_MAX_FRAME_SIZE_IN_WORDS; Index++) { + if (RxFrame[Index] != TxFrame[Index]) { + return XST_FAILURE; + } + } + + /* + * Reset device again before returning to the caller. + */ + XCanPs_Reset(InstancePtr); + + return XST_SUCCESS; +} + + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/xcanps_sinit.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/xcanps_sinit.c new file mode 100644 index 000000000..472c4a4c6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v2_0/src/xcanps_sinit.c @@ -0,0 +1,108 @@ +/****************************************************************************** +* +* (c) Copyright 2010 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcanps_sinit.c +* +* This file contains the implementation of the XCanPs driver's static +* initialization functionality. +* +* @note None. +* +* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+*
+*
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xparameters.h" +#include "xcanps.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ +extern XCanPs_Config XCanPs_ConfigTable[]; + +/*****************************************************************************/ +/** +* +* This function looks for the device configuration based on the unique device +* ID. The table XCanPs_ConfigTable[] contains the configuration information for +* each device in the system. +* +* @param DeviceId is the unique device ID of the device being looked up. +* +* @return A pointer to the configuration table entry corresponding to the +* given device ID, or NULL if no match is found. +* +* @note None. +* +******************************************************************************/ +XCanPs_Config *XCanPs_LookupConfig(u16 DeviceId) +{ + XCanPs_Config *CfgPtr = NULL; + u32 Index; + + for (Index = 0; Index < XPAR_XCANPS_NUM_INSTANCES; Index++) { + if (XCanPs_ConfigTable[Index].DeviceId == DeviceId) { + CfgPtr = &XCanPs_ConfigTable[Index]; + break; + } + } + + return CfgPtr; +} diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_0/src/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_0/src/Makefile new file mode 100644 index 000000000..77363c67c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_0/src/Makefile @@ -0,0 +1,23 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES=*.c +INCLUDEFILES=*.h + +libs: + echo "Compiling cpu_cortexa9" + +.PHONY: include +include: + ${CP} $(INCLUDEFILES) $(INCLUDEDIR) + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_0/src/xcpu_cortexa9.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_0/src/xcpu_cortexa9.h new file mode 100644 index 000000000..0933143a4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_0/src/xcpu_cortexa9.h @@ -0,0 +1,49 @@ +/* $Id: xcpu_cortexa9.h,v 1.1.2.1 2011/02/11 09:30:37 kkatna Exp $ */ +/****************************************************************************** +* +* (c) Copyright 2011 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcpu_cortexa9.h +* +* dummy file +* +******************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/Makefile new file mode 100644 index 000000000..2b569563c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/Makefile @@ -0,0 +1,41 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES:=*.c +INCLUDEFILES:=*.h + +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) + +libs: banner xdevcfg_libs clean + +%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling devcfg" + +xdevcfg_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} + +.PHONY: include +include: xdevcfg_includes + +xdevcfg_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS} + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/xdevcfg.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/xdevcfg.c new file mode 100644 index 000000000..bcd58c903 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/xdevcfg.c @@ -0,0 +1,941 @@ +/****************************************************************************** +* +* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdevcfg.c +* +* This file contains the implementation of the interface functions for XDcfg +* driver. Refer to the header file xdevcfg.h for more detailed information. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.00a nm  05/31/12 Updated the driver for CR 660835 so that input length for
+*		     source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
+*		     APIs is words (32 bit) and not bytes.
+* 		     Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
+*		     to add information that 2 LSBs of the Source/Destination
+*		     address when equal to 2Â’b01 indicate the last DMA command
+*		     of an overall transfer.
+*		     Updated the XDcfg_Transfer function to use the
+*		     Destination Address passed to this API for secure transfers
+*		     instead of using 0xFFFFFFFF for CR 662197. This issue was
+*		     resulting in the failure of secure transfers of
+*		     non-bitstream images.
+* 2.01a nm  08/27/12 Updated the XDcfg_Transfer API to clear the
+*		     QUARTER_PCAP_RATE_EN bit in the control register for
+*		     non secure writes for CR 675543.
+* 2.02a nm  01/31/13 Fixed CR# 679335.
+* 		     Added Setting and Clearing the internal PCAP loopback.
+*		     Removed code for enabling/disabling AES engine as BootROM
+*		     locks down this setting.
+*		     Fixed CR# 681976.
+*		     Skip Checking the PCFG_INIT in case of non-secure DMA
+*		     loopback.
+*		     Fixed CR# 699558.
+*		     XDcfg_Transfer fails to transfer data in loopback mode.
+* 2.03a nm  04/19/13 Fixed CR# 703728.
+*		     Updated the register definitions as per the latest TRM
+*		     version UG585 (v1.4) November 16, 2012.
+* 3.0   kpc 21/02/14 Implemented new function XDcfg_ClearControlRegister
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xdevcfg.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +/****************************************************************************/ +/** +* +* Initialize the Device Config Interface driver. This function +* must be called before other functions of the driver are called. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param ConfigPtr is the config structure. +* @param EffectiveAddress is the base address for the device. It could be +* a virtual address if address translation is supported in the +* system, otherwise it is the physical address. +* +* @return +* - XST_SUCCESS if initialization was successful. +* - XST_DEVICE_IS_STARTED if the device has already been started. +* +* @note The very first APB access to the Device Configuration Interface +* block needs to be a write to the UNLOCK register with the value +* of 0x757BDF0D. This step is to be done once after reset, any +* other APB access has to come after this. The APB access is +* considered illegal if the step is not done or if it is done +* incorrectly. Furthermore, if any of efuse_sec_cfg[5:0] is high, +* the following additional actions would be carried out. +* In other words, if all bits are low, the following steps are not +* done. +* 1. AES is disabled +* 2. All APB writes disabled +* 3. SoC debug fully enabled +* +******************************************************************************/ +int XDcfg_CfgInitialize(XDcfg *InstancePtr, + XDcfg_Config *ConfigPtr, u32 EffectiveAddress) +{ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(ConfigPtr != NULL); + + /* + * If the device is started, disallow the initialize and return a + * status indicating it is started. This allows the user to stop the + * device and reinitialize, but prevents a user from inadvertently + * initializing. + */ + if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) { + return XST_DEVICE_IS_STARTED; + } + + /* + * Copy configuration into instance. + */ + InstancePtr->Config.DeviceId = ConfigPtr->DeviceId; + + /* + * Save the base address pointer such that the registers of the block + * can be accessed and indicate it has not been started yet. + */ + InstancePtr->Config.BaseAddr = EffectiveAddress; + InstancePtr->IsStarted = 0; + + + /* Unlock the Device Configuration Interface */ + XDcfg_Unlock(InstancePtr); + + /* + * Indicate the instance is ready to use, successfully initialized. + */ + InstancePtr->IsReady = XIL_COMPONENT_IS_READY; + + return XST_SUCCESS; +} + +/****************************************************************************/ +/** +* +* The functions enables the PCAP interface by setting the PCAP mode bit in the +* control register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return None. +* +* @note Enable FPGA programming from PCAP interface. Enabling this bit +* disables all the external interfaces from programming of FPGA +* except for ICAP. The user needs to ensure that the FPGA is +* programmed through either PCAP or ICAP. +* +*****************************************************************************/ +void XDcfg_EnablePCAP(XDcfg *InstancePtr) +{ + u32 CtrlReg; + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_CTRL_OFFSET); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET, + (CtrlReg | XDCFG_CTRL_PCAP_MODE_MASK)); + +} + +/****************************************************************************/ +/** +* +* The functions disables the PCAP interface by clearing the PCAP mode bit in +* the control register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_DisablePCAP(XDcfg *InstancePtr) +{ + u32 CtrlReg; + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_CTRL_OFFSET); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET, + (CtrlReg & ( ~XDCFG_CTRL_PCAP_MODE_MASK))); + +} + +/****************************************************************************/ +/** +* +* The function sets the contents of the Control Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Mask is the 32 bit mask data to be written to the Register. +* The mask definitions are defined in the xdevcfg_hw.h file. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask) +{ + u32 CtrlReg; + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_CTRL_OFFSET); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET, + (CtrlReg | Mask)); + +} + +/****************************************************************************/ +/** +* +* The function Clears the specified bit positions of the Control Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Mask is the 32 bit value which holds the bit positions to be cleared. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask) +{ + u32 CtrlReg; + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_CTRL_OFFSET); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET, + (CtrlReg & ~Mask)); + +} + +/****************************************************************************/ +/** +* +* The function reads the contents of the Control Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return A 32-bit value representing the contents of the Control +* Register. +* Use the XDCFG_CTRL_*_MASK constants defined in xdevcfg_hw.h to +* interpret the returned value. +* +* @note None. +* +*****************************************************************************/ +u32 XDcfg_GetControlRegister(XDcfg *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the Control Register and return the value. + */ + return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET); +} + +/****************************************************************************/ +/** +* +* The function sets the contents of the Lock Register. These bits +* can only be set to a 1. They will be cleared after a Power On Reset. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Data is the 32 bit data to be written to the Register. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data) +{ + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_LOCK_OFFSET, Data); + +} + +/****************************************************************************/ +/** +* +* The function reads the contents of the Lock Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return A 32-bit value representing the contents of the Lock +* Register. +* Use the XDCFG_CR_*_MASK constants defined in xdevcfg_hw.h to +* interpret the returned value. +* +* @note None. +* +*****************************************************************************/ +u32 XDcfg_GetLockRegister(XDcfg *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the Lock Register and return the value. + */ + return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_LOCK_OFFSET); +} + +/****************************************************************************/ +/** +* +* The function sets the contents of the Configuration Register with the +* given value. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Data is the 32 bit data to be written to the Register. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data) +{ + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CFG_OFFSET, Data); + +} + +/****************************************************************************/ +/** +* +* The function reads the contents of the Configuration Register with the +* given value. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return A 32-bit value representing the contents of the Config +* Register. +* Use the XDCFG_CFG_*_MASK constants defined in xdevcfg_hw.h to +* interpret the returned value. +* +* @note None. +* +*****************************************************************************/ +u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_CFG_OFFSET); + +} + +/****************************************************************************/ +/** +* +* The function sets the contents of the Status Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Data is the 32 bit data to be written to the Register. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data) +{ + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET, Data); + +} + +/****************************************************************************/ +/** +* +* The function reads the contents of the Status Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return A 32-bit value representing the contents of the Status +* Register. +* Use the XDCFG_STATUS_*_MASK constants defined in +* xdevcfg_hw.h to interpret the returned value. +* +* @note None. +* +*****************************************************************************/ +u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the Status Register and return the value. + */ + return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET); +} + +/****************************************************************************/ +/** +* +* The function sets the contents of the ROM Shadow Control Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Data is the 32 bit data to be written to the Register. +* +* @return None. +* +* @note This register is can only be written and is used to control the +* RAM shadow of 32 bit 4K page ROM pages in user mode +* +*****************************************************************************/ +void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data) +{ + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_ROM_SHADOW_OFFSET, + Data); + +} + +/****************************************************************************/ +/** +* +* The function reads the contents of the Software ID Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return 32 Bit boot software ID. +* +* @note This register is locked for write once the system enters +* usermode. Hence API for reading the register only is provided. +* +*****************************************************************************/ +u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the Software ID Register and return the value. + */ + return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_SW_ID_OFFSET); +} + +/****************************************************************************/ +/** +* +* The function sets the bit mask for the feature in Miscellaneous Control +* Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Mask is the bit-mask of the feature to be set. +* +* @return None. +* +* @note None +* +*****************************************************************************/ +void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask) +{ + u32 RegData; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_MCTRL_OFFSET, + (RegData | Mask)); +} + +/****************************************************************************/ +/** +* +* The function reads the contents of the Miscellaneous Control Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return 32 Bit boot software ID. +* +* @note This register is locked for write once the system enters +* usermode. Hence API to reading the register only is provided. +* +*****************************************************************************/ +u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the Miscellaneous Control Register and return the value. + */ + return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_MCTRL_OFFSET); +} + +/******************************************************************************/ +/** +* +* This function checks if DMA command queue is full. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return XST_SUCCESS is the DMA is busy +* XST_FAILURE if the DMA is idle +* +* @note The DMA queue has a depth of two. +* +****************************************************************************/ +u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr) +{ + + u32 RegData; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* Read the PCAP status register for DMA status */ + RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_STATUS_OFFSET); + + if ((RegData & XDCFG_STATUS_DMA_CMD_Q_F_MASK) == + XDCFG_STATUS_DMA_CMD_Q_F_MASK){ + return XST_SUCCESS; + } + + return XST_FAILURE; +} + +/******************************************************************************/ +/** +* +* This function initiates the DMA transfer. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param SourcePtr contains a pointer to the source memory where the data +* is to be transferred from. +* @param SrcWordLength is the number of words (32 bit) to be transferred +* for the source transfer. +* @param DestPtr contains a pointer to the destination memory +* where the data is to be transferred to. +* @param DestWordLength is the number of words (32 bit) to be transferred +* for the Destination transfer. +* +* @return None. +* +* @note It is the responsibility of the caller function to ensure that +* correct values are passed to this function. +* +* The 2 LSBs of the SourcePtr (Source)/ DestPtr (Destination) +* address when equal to 2Â’b01 indicates the last DMA command of +* an overall transfer. +* +****************************************************************************/ +void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr, + u32 SrcWordLength, u32 DestWordLength) +{ + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_DMA_SRC_ADDR_OFFSET, + SourcePtr); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_DMA_DEST_ADDR_OFFSET, + DestPtr); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_DMA_SRC_LEN_OFFSET, + SrcWordLength); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_DMA_DEST_LEN_OFFSET, + DestWordLength); +} + +/******************************************************************************/ +/** +* +* This function Implements the DMA Read Command. This command is used to +* transfer the image data from FPGA to the external memory. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param SourcePtr contains a pointer to the source memory where the data +* is to be transferred from. +* @param SrcWordLength is the number of words (32 bit) to be transferred +* for the source transfer. +* @param DestPtr contains a pointer to the destination memory +* where the data is to be transferred to. +* @param DestWordLength is the number of words (32 bit) to be transferred +* for the Destination transfer. +* +* @return - XST_INVALID_PARAM if source address/length is invalid. +* - XST_SUCCESS if DMA transfer initiated properly. +* +* @note None. +* +****************************************************************************/ +static u32 XDcfg_PcapReadback(XDcfg *InstancePtr, u32 SourcePtr, + u32 SrcWordLength, u32 DestPtr, + u32 DestWordLength) +{ + u32 IntrReg; + + /* + * Send READ Frame command to FPGA + */ + XDcfg_InitiateDma(InstancePtr, SourcePtr, XDCFG_DMA_INVALID_ADDRESS, + SrcWordLength, 0); + + /* + * Store the enabled interrupts to enable before the actual read + * transfer is initiated and Disable all the interrupts temporarily. + */ + IntrReg = XDcfg_IntrGetEnabled(InstancePtr); + XDcfg_IntrDisable(InstancePtr, XDCFG_IXR_ALL_MASK); + + /* + * Wait till you get the DMA done for the read command sent + */ + while ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_STS_OFFSET) & + XDCFG_IXR_D_P_DONE_MASK) == + XDCFG_IXR_D_P_DONE_MASK); + /* + * Enable the previously stored Interrupts . + */ + XDcfg_IntrEnable(InstancePtr, IntrReg); + + /* + * Initiate the DMA write command. + */ + XDcfg_InitiateDma(InstancePtr, XDCFG_DMA_INVALID_ADDRESS, (u32)DestPtr, + 0, DestWordLength); + + return XST_SUCCESS; +} + + +/****************************************************************************/ +/** +* +* This function starts the DMA transfer. This function only starts the +* operation and returns before the operation may be completed. +* If the interrupt is enabled, an interrupt will be generated when the +* operation is completed, otherwise it is necessary to poll the Status register +* to determine when it is completed. It is the responsibility of the caller to +* determine when the operation is completed by handling the generated interrupt +* or polling the Status Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param SourcePtr contains a pointer to the source memory where the data +* is to be transferred from. +* @param SrcWordLength is the number of words (32 bit) to be transferred +* for the source transfer. +* @param DestPtr contains a pointer to the destination memory +* where the data is to be transferred to. +* @param DestWordLength is the number of words (32 bit) to be transferred +* for the Destination transfer. +* @param TransferType contains the type of PCAP transfer being requested. +* The definitions can be found in the xdevcfg.h file. +* @return +* - XST_SUCCESS.if DMA transfer initiated successfully +* - XST_DEVICE_BUSY if DMA is busy +* - XST_INVALID_PARAM if invalid Source / Destination address +* is sent or an invalid Source / Destination length is +* sent +* +* @note It is the responsibility of the caller to ensure that the cache +* is flushed and invalidated both before the DMA operation is +* started and after the DMA operation completes if the memory +* pointed to is cached. The caller must also ensure that the +* pointers contain physical address rather than a virtual address +* if address translation is being used. +* +* The 2 LSBs of the SourcePtr (Source)/ DestPtr (Destination) +* address when equal to 2Â’b01 indicates the last DMA command of +* an overall transfer. +* +*****************************************************************************/ +u32 XDcfg_Transfer(XDcfg *InstancePtr, + void *SourcePtr, u32 SrcWordLength, + void *DestPtr, u32 DestWordLength, + u32 TransferType) +{ + + u32 CtrlReg; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + if (XDcfg_IsDmaBusy(InstancePtr) == XST_SUCCESS) { + return XST_DEVICE_BUSY; + } + + /* + * Check whether the fabric is in initialized state + */ + if ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET) + & XDCFG_STATUS_PCFG_INIT_MASK) == 0) { + /* + * We don't need to check PCFG_INIT to be high for + * non-encrypted loopback transfers. + */ + if (TransferType != XDCFG_CONCURRENT_NONSEC_READ_WRITE) { + return XST_FAILURE; + } + } + + if ((TransferType == XDCFG_SECURE_PCAP_WRITE) || + (TransferType == XDCFG_NON_SECURE_PCAP_WRITE)) { + + /* Check for valid source pointer and length */ + if ((!SourcePtr) || (SrcWordLength == 0)) { + return XST_INVALID_PARAM; + } + + /* Clear internal PCAP loopback */ + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET); + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET, (CtrlReg & + ~(XDCFG_MCTRL_PCAP_LPBK_MASK))); + + if (TransferType == XDCFG_NON_SECURE_PCAP_WRITE) { + /* + * Clear QUARTER_PCAP_RATE_EN bit + * so that the PCAP data is transmitted every clock + */ + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_CTRL_OFFSET); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_CTRL_OFFSET, (CtrlReg & + ~XDCFG_CTRL_PCAP_RATE_EN_MASK)); + + } + if (TransferType == XDCFG_SECURE_PCAP_WRITE) { + /* + * AES engine handles only 8 bit data every clock cycle. + * Hence, Encrypted PCAP data which is 32 bit data can + * only be sent in every 4 clock cycles. Set the control + * register QUARTER_PCAP_RATE_EN bit to achieve this + * operation. + */ + XDcfg_SetControlRegister(InstancePtr, + XDCFG_CTRL_PCAP_RATE_EN_MASK); + } + + XDcfg_InitiateDma(InstancePtr, (u32)SourcePtr, + (u32)DestPtr, SrcWordLength, DestWordLength); + + } + + if (TransferType == XDCFG_PCAP_READBACK) { + + if ((!DestPtr) || (DestWordLength == 0)) { + + return XST_INVALID_PARAM; + } + + /* Clear internal PCAP loopback */ + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET); + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET, (CtrlReg & + ~(XDCFG_MCTRL_PCAP_LPBK_MASK))); + + /* + * For PCAP readback of FPGA configuration register or memory, + * the read command is first sent (written) to the FPGA fabric + * which responds by returning the required read data. Read data + * from the FPGA is captured if pcap_radata_v is active.A DMA + * read transfer is required to obtain the readback command, + * which is then sent to the FPGA, followed by a DMA write + * transfer to support this mode of operation. + */ + return XDcfg_PcapReadback(InstancePtr, + (u32)SourcePtr, SrcWordLength, + (u32)DestPtr, DestWordLength); + } + + + if ((TransferType == XDCFG_CONCURRENT_SECURE_READ_WRITE) || + (TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE)) { + + if ((!SourcePtr) || (SrcWordLength == 0) || + (!DestPtr) || (DestWordLength == 0)) { + return XST_INVALID_PARAM; + } + + if (TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE) { + /* Enable internal PCAP loopback */ + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET); + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET, (CtrlReg | + XDCFG_MCTRL_PCAP_LPBK_MASK)); + + /* + * Clear QUARTER_PCAP_RATE_EN bit + * so that the PCAP data is transmitted every clock + */ + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_CTRL_OFFSET); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_CTRL_OFFSET, (CtrlReg & + ~XDCFG_CTRL_PCAP_RATE_EN_MASK)); + + } + if (TransferType == XDCFG_CONCURRENT_SECURE_READ_WRITE) { + /* Clear internal PCAP loopback */ + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET); + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET, (CtrlReg & + ~(XDCFG_MCTRL_PCAP_LPBK_MASK))); + + /* + * Set the QUARTER_PCAP_RATE_EN bit + * so that the PCAP data is transmitted every 4 clock + * cycles, this is required for encrypted data. + */ + XDcfg_SetControlRegister(InstancePtr, + XDCFG_CTRL_PCAP_RATE_EN_MASK); + } + + XDcfg_InitiateDma(InstancePtr, (u32)SourcePtr, + (u32)DestPtr, SrcWordLength, DestWordLength); + } + + return XST_SUCCESS; +} diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/xdevcfg.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/xdevcfg.h new file mode 100644 index 000000000..d40321251 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/xdevcfg.h @@ -0,0 +1,389 @@ +/****************************************************************************** +* +* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdevcfg.h +* +* The is the main header file for the Device Configuration Interface of the Zynq +* device. The device configuration interface has three main functionality. +* 1. AXI-PCAP +* 2. Security Policy +* 3. XADC +* This current version of the driver supports only the AXI-PCAP and Security +* Policy blocks. There is a separate driver for XADC. +* +* AXI-PCAP is used for download/upload an encrypted or decrypted bitstream. +* DMA embedded in the AXI PCAP provides the master interface to +* the Device configuration block for any DMA transfers. The data transfer can +* take place between the Tx/RxFIFOs of AXI-PCAP and memory (on chip +* RAM/DDR/peripheral memory). +* +* The current driver only supports the downloading the FPGA bitstream and +* readback of the decrypted image (sort of loopback). +* The driver does not know what information needs to be written to the FPGA to +* readback FPGA configuration register or memory data. The application above the +* driver should take care of creating the data that needs to be downloaded to +* the FPGA so that the bitstream can be readback. +* This driver also does not support the reading of the internal registers of the +* PCAP. The driver has no knowledge of the PCAP internals. +* +* Initialization and Configuration +* +* The device driver enables higher layer software (e.g., an application) to +* communicate with the Device Configuration device. +* +* XDcfg_CfgInitialize() API is used to initialize the Device Configuration +* Interface. The user needs to first call the XDcfg_LookupConfig() API which +* returns the Configuration structure pointer which is passed as a parameter to +* the XDcfg_CfgInitialize() API. +* +* Interrupts +* The Driver implements an interrupt handler to support the interrupts provided +* by this interface. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The XDcfg driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +* +*

+* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.00a nm  05/31/12 Updated the driver for CR 660835 so that input length for
+*		     source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
+*		     APIs is words (32 bit) and not bytes.
+* 		     Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
+*		     to add information that 2 LSBs of the Source/Destination
+*		     address when equal to 2Â’b01 indicate the last DMA command
+*		     of an overall transfer.
+*		     Destination Address passed to this API for secure transfers
+*		     instead of using 0xFFFFFFFF for CR 662197. This issue was
+*		     resulting in the failure of secure transfers of
+*		     non-bitstream images.
+* 2.01a nm  07/07/12 Updated the XDcfg_IntrClear function to directly
+*		     set the mask instead of oring it with the
+*		     value read from the interrupt status register
+* 		     Added defines for the PS Version bits,
+*	             removed the FIFO Flush bits from the
+*		     Miscellaneous Control Reg.
+*		     Added XDcfg_GetPsVersion, XDcfg_SelectIcapInterface
+*		     and XDcfg_SelectPcapInterface APIs for CR 643295
+*		     The user has to call the XDcfg_SelectIcapInterface API
+*		     for the PL reconfiguration using AXI HwIcap.
+*		     Updated the XDcfg_Transfer API to clear the
+*		     QUARTER_PCAP_RATE_EN bit in the control register for
+*		     non secure writes for CR 675543.
+* 2.02a nm  01/31/13 Fixed CR# 679335.
+* 		     Added Setting and Clearing the internal PCAP loopback.
+*		     Removed code for enabling/disabling AES engine as BootROM
+*		     locks down this setting.
+*		     Fixed CR# 681976.
+*		     Skip Checking the PCFG_INIT in case of non-secure DMA
+*		     loopback.
+*		     Fixed CR# 699558.
+*		     XDcfg_Transfer fails to transfer data in loopback mode.
+*		     Fixed CR# 701348.
+*                    Peripheral test fails with  Running
+* 		     DcfgSelfTestExample() in SECURE bootmode.
+* 2.03a nm  04/19/13 Fixed CR# 703728.
+*		     Updated the register definitions as per the latest TRM
+*		     version UG585 (v1.4) November 16, 2012.
+* 3.0   adk 10/12/13 Updated as per the New Tcl API's
+* 3.0   kpc 21/02/14 Added function prototype for XDcfg_ClearControlRegister
+*
+* +******************************************************************************/ +#ifndef XDCFG_H /* prevent circular inclusions */ +#define XDCFG_H /* by using protection macros */ + +/***************************** Include Files *********************************/ + +#include "xdevcfg_hw.h" +#include "xstatus.h" +#include "xil_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ + +/* Types of PCAP transfers */ + +#define XDCFG_NON_SECURE_PCAP_WRITE 1 +#define XDCFG_SECURE_PCAP_WRITE 2 +#define XDCFG_PCAP_READBACK 3 +#define XDCFG_CONCURRENT_SECURE_READ_WRITE 4 +#define XDCFG_CONCURRENT_NONSEC_READ_WRITE 5 + + +/**************************** Type Definitions *******************************/ +/** +* The handler data type allows the user to define a callback function to +* respond to interrupt events in the system. This function is executed +* in interrupt context, so amount of processing should be minimized. +* +* @param CallBackRef is the callback reference passed in by the upper +* layer when setting the callback functions, and passed back to +* the upper layer when the callback is invoked. Its type is +* unimportant to the driver component, so it is a void pointer. +* @param Status is the Interrupt status of the XDcfg device. +*/ +typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status); + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddr; /**< Base address of the device */ +} XDcfg_Config; + +/** + * The XDcfg driver instance data. + */ +typedef struct { + XDcfg_Config Config; /**< Hardware Configuration */ + u32 IsReady; /**< Device is initialized and ready */ + u32 IsStarted; /**< Device Configuration Interface + * is running + */ + XDcfg_IntrHandler StatusHandler; /* Event handler function */ + void *CallBackRef; /* Callback reference for event handler */ +} XDcfg; + +/****************************************************************************/ +/** +* +* Unlock the Device Config Interface block. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return None. +* +* @note C-style signature: +* void XDcfg_Unlock(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_Unlock(InstancePtr) \ + XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, \ + XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA) + + + +/****************************************************************************/ +/** +* +* Get the version number of the PS from the Miscellaneous Control Register. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return Version of the PS. +* +* @note C-style signature: +* void XDcfg_GetPsVersion(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_GetPsVersion(InstancePtr) \ + ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \ + XDCFG_MCTRL_OFFSET)) & \ + XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \ + XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT + + + +/****************************************************************************/ +/** +* +* Read the multiboot config register value. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return None. +* +* @note C-style signature: +* u32 XDcfg_ReadMultiBootConfig(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_ReadMultiBootConfig(InstancePtr) \ + XDcfg_ReadReg((InstancePtr)->Config.BaseAddr + \ + XDCFG_MULTIBOOT_ADDR_OFFSET) + + +/****************************************************************************/ +/** +* +* Selects ICAP interface for reconfiguration after the initial configuration +* of the PL. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return None. +* +* @note C-style signature: +* void XDcfg_SelectIcapInterface(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_SelectIcapInterface(InstancePtr) \ + XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \ + ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \ + & ( ~XDCFG_CTRL_PCAP_PR_MASK))) + +/****************************************************************************/ +/** +* +* Selects PCAP interface for reconfiguration after the initial configuration +* of the PL. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return None. +* +* @note C-style signature: +* void XDcfg_SelectPcapInterface(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_SelectPcapInterface(InstancePtr) \ + XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \ + ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \ + | XDCFG_CTRL_PCAP_PR_MASK)) + + + +/************************** Function Prototypes ******************************/ + +/* + * Lookup configuration in xdevcfg_sinit.c. + */ +XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId); + +/* + * Selftest function in xdevcfg_selftest.c + */ +int XDcfg_SelfTest(XDcfg *InstancePtr); + +/* + * Interface functions in xdevcfg.c + */ +int XDcfg_CfgInitialize(XDcfg *InstancePtr, + XDcfg_Config *ConfigPtr, u32 EffectiveAddress); + +void XDcfg_EnablePCAP(XDcfg *InstancePtr); + +void XDcfg_DisablePCAP(XDcfg *InstancePtr); + +void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask); + +void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask); + +u32 XDcfg_GetControlRegister(XDcfg *InstancePtr); + +void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data); + +u32 XDcfg_GetLockRegister(XDcfg *InstancePtr); + +void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data); + +u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr); + +void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data); + +u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr); + +void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data); + +u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr); + +void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask); + +u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr); + +u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr); + +void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr, + u32 SrcWordLength, u32 DestWordLength); + +u32 XDcfg_Transfer(XDcfg *InstancePtr, + void *SourcePtr, u32 SrcWordLength, + void *DestPtr, u32 DestWordLength, + u32 TransferType); + +/* + * Interrupt related function prototypes implemented in xdevcfg_intr.c + */ +void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask); + +void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask); + +u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr); + +u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr); + +void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask); + +void XDcfg_InterruptHandler(XDcfg *InstancePtr); + +void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc, + void *CallBackRef); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/xdevcfg_g.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/xdevcfg_g.c new file mode 100644 index 000000000..621ac3a65 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/xdevcfg_g.c @@ -0,0 +1,31 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSM. +* Version: +* DO NOT EDIT. +* +* v (64-bit) +SW Build (by ) on +Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xdevcfg.h" + +/* +* The configuration table for devices +*/ + +XDcfg_Config XDcfg_ConfigTable[] = +{ + { + XPAR_PS7_DEV_CFG_0_DEVICE_ID, + XPAR_PS7_DEV_CFG_0_BASEADDR + } +}; + + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/xdevcfg_hw.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/xdevcfg_hw.c new file mode 100644 index 000000000..94c9ccff3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/xdevcfg_hw.c @@ -0,0 +1,119 @@ +/****************************************************************************** +* +* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdevcfg_hw.c +* +* This file contains the implementation of the interface reset functionality +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 2.04a kpc 10/07/13 First release
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xdevcfg_hw.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +/*****************************************************************************/ +/** +* This function perform the reset sequence to the given devcfg interface by +* configuring the appropriate control bits in the devcfg specifc registers +* the devcfg reset squence involves the following steps +* Disable all the interuupts +* Clear the status +* Update relevant config registers with reset values +* Disbale the looopback mode and pcap rate enable +* +* @param BaseAddress of the interface +* +* @return N/A +* +* @note +* This function will not modify the slcr registers that are relavant for +* devcfg controller +******************************************************************************/ +void XDcfg_ResetHw(u32 BaseAddr) +{ + u32 Regval = 0; + + /* Mask the interrupts */ + XDcfg_WriteReg(BaseAddr, XDCFG_INT_MASK_OFFSET, + XDCFG_IXR_ALL_MASK); + /* Clear the interuupt status */ + Regval = XDcfg_ReadReg(BaseAddr, XDCFG_INT_STS_OFFSET); + XDcfg_WriteReg(BaseAddr, XDCFG_INT_STS_OFFSET, Regval); + /* Clear the source address register */ + XDcfg_WriteReg(BaseAddr, XDCFG_DMA_SRC_ADDR_OFFSET, 0x0); + /* Clear the destination address register */ + XDcfg_WriteReg(BaseAddr, XDCFG_DMA_DEST_ADDR_OFFSET, 0x0); + /* Clear the source length register */ + XDcfg_WriteReg(BaseAddr, XDCFG_DMA_SRC_LEN_OFFSET, 0x0); + /* Clear the destination length register */ + XDcfg_WriteReg(BaseAddr, XDCFG_DMA_DEST_LEN_OFFSET, 0x0); + /* Clear the loopback enable bit */ + Regval = XDcfg_ReadReg(BaseAddr, XDCFG_MCTRL_OFFSET); + Regval = Regval & ~XDCFG_MCTRL_PCAP_LPBK_MASK; + XDcfg_WriteReg(BaseAddr, XDCFG_MCTRL_OFFSET, Regval); + /*Reset the configuration register to reset value */ + XDcfg_WriteReg(BaseAddr, XDCFG_CFG_OFFSET, + XDCFG_CONFIG_RESET_VALUE); + /*Disable the PCAP rate enable bit */ + Regval = XDcfg_ReadReg(BaseAddr, XDCFG_CTRL_OFFSET); + Regval = Regval & ~XDCFG_CTRL_PCAP_RATE_EN_MASK; + XDcfg_WriteReg(BaseAddr, XDCFG_CTRL_OFFSET, Regval); + +} diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/xdevcfg_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/xdevcfg_hw.h new file mode 100644 index 000000000..3f06b5d0c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/xdevcfg_hw.h @@ -0,0 +1,401 @@ +/****************************************************************************** +* +* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdevcfg_hw.h +* +* This file contains the hardware interface to the Device Config Interface. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.01a nm  08/01/12 Added defines for the PS Version bits,
+*	             removed the FIFO Flush bits from the
+*		     Miscellaneous Control Reg
+* 2.03a nm  04/19/13 Fixed CR# 703728.
+*		     Updated the register definitions as per the latest TRM
+*		     version UG585 (v1.4) November 16, 2012.
+* 2.04a	kpc	10/07/13 Added function prototype.	
+* 3.00a	kpc	25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
+*
+* +******************************************************************************/ +#ifndef XDCFG_HW_H /* prevent circular inclusions */ +#define XDCFG_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * Offsets of registers from the start of the device + * @{ + */ + +#define XDCFG_CTRL_OFFSET 0x00 /**< Control Register */ +#define XDCFG_LOCK_OFFSET 0x04 /**< Lock Register */ +#define XDCFG_CFG_OFFSET 0x08 /**< Configuration Register */ +#define XDCFG_INT_STS_OFFSET 0x0C /**< Interrupt Status Register */ +#define XDCFG_INT_MASK_OFFSET 0x10 /**< Interrupt Mask Register */ +#define XDCFG_STATUS_OFFSET 0x14 /**< Status Register */ +#define XDCFG_DMA_SRC_ADDR_OFFSET 0x18 /**< DMA Source Address Register */ +#define XDCFG_DMA_DEST_ADDR_OFFSET 0x1C /**< DMA Destination Address Reg */ +#define XDCFG_DMA_SRC_LEN_OFFSET 0x20 /**< DMA Source Transfer Length */ +#define XDCFG_DMA_DEST_LEN_OFFSET 0x24 /**< DMA Destination Transfer */ +#define XDCFG_ROM_SHADOW_OFFSET 0x28 /**< DMA ROM Shadow Register */ +#define XDCFG_MULTIBOOT_ADDR_OFFSET 0x2C /**< Multi BootAddress Pointer */ +#define XDCFG_SW_ID_OFFSET 0x30 /**< Software ID Register */ +#define XDCFG_UNLOCK_OFFSET 0x34 /**< Unlock Register */ +#define XDCFG_MCTRL_OFFSET 0x80 /**< Miscellaneous Control Reg */ + +/* @} */ + +/** @name Control Register Bit definitions + * @{ + */ + +#define XDCFG_CTRL_FORCE_RST_MASK 0x80000000 /**< Force into + * Secure Reset + */ +#define XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000 /**< Program signal to + * Reset FPGA + */ +#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x20000000 /**< Control PL POR timer */ +#define XDCFG_CTRL_PCAP_PR_MASK 0x08000000 /**< Enable PCAP for PR */ +#define XDCFG_CTRL_PCAP_MODE_MASK 0x04000000 /**< Enable PCAP */ +#define XDCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000 /**< Enable PCAP send data + * to FPGA every 4 PCAP + * cycles + */ +#define XDCFG_CTRL_MULTIBOOT_EN_MASK 0x01000000 /**< Multiboot Enable */ +#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK 0x00800000 /**< JTAG Chain Disable */ +#define XDCFG_CTRL_USER_MODE_MASK 0x00008000 /**< User Mode Mask */ +#define XDCFG_CTRL_PCFG_AES_FUSE_MASK 0x00001000 /**< AES key source */ +#define XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 /**< AES Enable Mask */ +#define XDCFG_CTRL_SEU_EN_MASK 0x00000100 /**< SEU Enable Mask */ +#define XDCFG_CTRL_SEC_EN_MASK 0x00000080 /**< Secure/Non Secure + * Status mask + */ +#define XDCFG_CTRL_SPNIDEN_MASK 0x00000040 /**< Secure Non Invasive + * Debug Enable + */ +#define XDCFG_CTRL_SPIDEN_MASK 0x00000020 /**< Secure Invasive + * Debug Enable + */ +#define XDCFG_CTRL_NIDEN_MASK 0x00000010 /**< Non-Invasive Debug + * Enable + */ +#define XDCFG_CTRL_DBGEN_MASK 0x00000008 /**< Invasive Debug + * Enable + */ +#define XDCFG_CTRL_DAP_EN_MASK 0x00000007 /**< DAP Enable Mask */ + +/* @} */ + +/** @name Lock register bit definitions + * @{ + */ + +#define XDCFG_LOCK_AES_EFUSE_MASK 0x00000010 /**< Lock AES Efuse bit */ +#define XDCFG_LOCK_AES_EN_MASK 0x00000008 /**< Lock AES_EN update */ +#define XDCFG_LOCK_SEU_MASK 0x00000004 /**< Lock SEU_En update */ +#define XDCFG_LOCK_SEC_MASK 0x00000002 /**< Lock SEC_EN and + * USER_MODE + */ +#define XDCFG_LOCK_DBG_MASK 0x00000001 /**< This bit locks + * security config + * including: DAP_En, + * DBGEN,, + * NIDEN, SPNIEN + */ +/*@}*/ + + + +/** @name Config Register Bit definitions + * @{ + */ +#define XDCFG_CFG_RFIFO_TH_MASK 0x00000C00 /**< Read FIFO + * Threshold Mask + */ +#define XDCFG_CFG_WFIFO_TH_MASK 0x00000300 /**< Write FIFO Threshold + * Mask + */ +#define XDCFG_CFG_RCLK_EDGE_MASK 0x00000080 /**< Read data active + * clock edge + */ +#define XDCFG_CFG_WCLK_EDGE_MASK 0x00000040 /**< Write data active + * clock edge + */ +#define XDCFG_CFG_DISABLE_SRC_INC_MASK 0x00000020 /**< Disable Source address + * increment mask + */ +#define XDCFG_CFG_DISABLE_DST_INC_MASK 0x00000010 /**< Disable Destination + * address increment + * mask + */ +/* @} */ + + +/** @name Interrupt Status/Mask Register Bit definitions + * @{ + */ +#define XDCFG_IXR_PSS_GTS_USR_B_MASK 0x80000000 /**< Tri-state IO during + * HIZ + */ +#define XDCFG_IXR_PSS_FST_CFG_B_MASK 0x40000000 /**< First configuration + * done + */ +#define XDCFG_IXR_PSS_GPWRDWN_B_MASK 0x20000000 /**< Global power down */ +#define XDCFG_IXR_PSS_GTS_CFG_B_MASK 0x10000000 /**< Tri-state IO during + * configuration + */ +#define XDCFG_IXR_PSS_CFG_RESET_B_MASK 0x08000000 /**< PL configuration + * reset + */ +#define XDCFG_IXR_AXI_WTO_MASK 0x00800000 /**< AXI Write Address + * or Data or response + * timeout + */ +#define XDCFG_IXR_AXI_WERR_MASK 0x00400000 /**< AXI Write response + * error + */ +#define XDCFG_IXR_AXI_RTO_MASK 0x00200000 /**< AXI Read Address or + * response timeout + */ +#define XDCFG_IXR_AXI_RERR_MASK 0x00100000 /**< AXI Read response + * error + */ +#define XDCFG_IXR_RX_FIFO_OV_MASK 0x00040000 /**< Rx FIFO Overflow */ +#define XDCFG_IXR_WR_FIFO_LVL_MASK 0x00020000 /**< Tx FIFO less than + * threshold */ +#define XDCFG_IXR_RD_FIFO_LVL_MASK 0x00010000 /**< Rx FIFO greater than + * threshold */ +#define XDCFG_IXR_DMA_CMD_ERR_MASK 0x00008000 /**< Illegal DMA command */ +#define XDCFG_IXR_DMA_Q_OV_MASK 0x00004000 /**< DMA command queue + * overflow + */ +#define XDCFG_IXR_DMA_DONE_MASK 0x00002000 /**< DMA Command Done */ +#define XDCFG_IXR_D_P_DONE_MASK 0x00001000 /**< DMA and PCAP + * transfers Done + */ +#define XDCFG_IXR_P2D_LEN_ERR_MASK 0x00000800 /**< PCAP to DMA transfer + * length error + */ +#define XDCFG_IXR_PCFG_HMAC_ERR_MASK 0x00000040 /**< HMAC error mask */ +#define XDCFG_IXR_PCFG_SEU_ERR_MASK 0x00000020 /**< SEU Error mask */ +#define XDCFG_IXR_PCFG_POR_B_MASK 0x00000010 /**< FPGA POR mask */ +#define XDCFG_IXR_PCFG_CFG_RST_MASK 0x00000008 /**< FPGA Reset mask */ +#define XDCFG_IXR_PCFG_DONE_MASK 0x00000004 /**< Done Signal Mask */ +#define XDCFG_IXR_PCFG_INIT_PE_MASK 0x00000002 /**< Detect Positive edge + * of Init Signal + */ +#define XDCFG_IXR_PCFG_INIT_NE_MASK 0x00000001 /**< Detect Negative edge + * of Init Signal + */ +#define XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WTO_MASK | \ + XDCFG_IXR_AXI_WERR_MASK | \ + XDCFG_IXR_AXI_RTO_MASK | \ + XDCFG_IXR_AXI_RERR_MASK | \ + XDCFG_IXR_RX_FIFO_OV_MASK | \ + XDCFG_IXR_DMA_CMD_ERR_MASK |\ + XDCFG_IXR_DMA_Q_OV_MASK | \ + XDCFG_IXR_P2D_LEN_ERR_MASK |\ + XDCFG_IXR_PCFG_HMAC_ERR_MASK) + + +#define XDCFG_IXR_ALL_MASK 0x00F7F8EF + + + +/* @} */ + + +/** @name Status Register Bit definitions + * @{ + */ +#define XDCFG_STATUS_DMA_CMD_Q_F_MASK 0x80000000 /**< DMA command + * Queue full + */ +#define XDCFG_STATUS_DMA_CMD_Q_E_MASK 0x40000000 /**< DMA command + * Queue empty + */ +#define XDCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 /**< Number of + * completed DMA + * transfers + */ +#define XDCFG_STATUS_RX_FIFO_LVL_MASK 0x01F000000 /**< Rx FIFO level */ +#define XDCFG_STATUS_TX_FIFO_LVL_MASK 0x0007F000 /**< Tx FIFO level */ + +#define XDCFG_STATUS_PSS_GTS_USR_B 0x00000800 /**< Tri-state IO + * during HIZ + */ +#define XDCFG_STATUS_PSS_FST_CFG_B 0x00000400 /**< First PL config + * done + */ +#define XDCFG_STATUS_PSS_GPWRDWN_B 0x00000200 /**< Global power down */ +#define XDCFG_STATUS_PSS_GTS_CFG_B 0x00000100 /**< Tri-state IO during + * config + */ +#define XDCFG_STATUS_SECURE_RST_MASK 0x00000080 /**< Secure Reset + * POR Status + */ +#define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 0x00000040 /**< Illegal APB + * access + */ +#define XDCFG_STATUS_PSS_CFG_RESET_B 0x00000020 /**< PL config + * reset status + */ +#define XDCFG_STATUS_PCFG_INIT_MASK 0x00000010 /**< FPGA Init + * Status + */ +#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008 + /**< BBRAM key + * disable + */ +#define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004 /**< Efuse Security + * Enable Status + */ +#define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK 0x00000002 /**< EFuse JTAG + * Disable + * status + */ +/* @} */ + + +/** @name DMA Source/Destination Transfer Length Register Bit definitions + * @{ + */ +#define XDCFG_DMA_LEN_MASK 0x7FFFFFF /**< Length Mask */ +/*@}*/ + + + + +/** @name Miscellaneous Control Register Bit definitions + * @{ + */ +#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK 0xF0000000 /**< PS Version Mask */ +#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28 /**< PS Version Shift */ +#define XDCFG_MCTRL_PCAP_LPBK_MASK 0x00000010 /**< PCAP loopback mask */ +/* @} */ + +/** @name FIFO Threshold Bit definitions + * @{ + */ + +#define XDCFG_CFG_FIFO_QUARTER 0x0 /**< Quarter empty */ +#define XDCFG_CFG_FIFO_HALF 0x1 /**< Half empty */ +#define XDCFG_CFG_FIFO_3QUARTER 0x2 /**< 3/4 empty */ +#define XDCFG_CFG_FIFO_EMPTY 0x4 /**< Empty */ +/* @}*/ + + +/* Miscellaneous constant values */ +#define XDCFG_DMA_INVALID_ADDRESS 0xFFFFFFFF /**< Invalid DMA address */ +#define XDCFG_UNLOCK_DATA 0x757BDF0D /**< First APB access data*/ +#define XDCFG_BASE_ADDRESS 0xF8007000 /**< Device Config base + * address + */ +#define XDCFG_CONFIG_RESET_VALUE 0x508 /**< Config reg reset value */ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Read the given register. +* +* @param BaseAddr is the base address of the device +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note C-style signature: +* u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset) +* +*****************************************************************************/ +#define XDcfg_ReadReg(BaseAddr, RegOffset) \ + Xil_In32((BaseAddr) + (RegOffset)) + +/****************************************************************************/ +/** +* +* Write to the given register. +* +* @param BaseAddr is the base address of the device +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note C-style signature: +* void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define XDcfg_WriteReg(BaseAddr, RegOffset, Data) \ + Xil_Out32((BaseAddr) + (RegOffset), (Data)) + +/************************** Function Prototypes ******************************/ +/* + * Perform reset operation to the devcfg interface + */ +void XDcfg_ResetHw(u32 BaseAddr); +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/xdevcfg_intr.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/xdevcfg_intr.c new file mode 100644 index 000000000..8fb39d747 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/xdevcfg_intr.c @@ -0,0 +1,316 @@ +/****************************************************************************** +* +* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdevcfg_intr.c +* +* Contains the implementation of interrupt related functions of the XDcfg +* driver. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.01a nm  07/07/12 Updated the XDcfg_IntrClear function to directly
+*		     set the mask instead of oring it with the
+*		     value read from the interrupt status register
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xdevcfg.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +/****************************************************************************/ +/** +* +* This function enables the specified interrupts in the device. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Mask is the bit-mask of the interrupts to be enabled. +* Bit positions of 1 will be enabled. Bit positions of 0 will +* keep the previous setting. This mask is formed by OR'ing +* XDCFG_INT_* bits defined in xdevcfg_hw.h. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask) +{ + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Enable the specified interrupts in the Interrupt Mask Register. + */ + RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_MASK_OFFSET); + RegValue &= ~(Mask & XDCFG_IXR_ALL_MASK); + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_MASK_OFFSET, + RegValue); +} + + +/****************************************************************************/ +/** +* +* This function disables the specified interrupts in the device. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Mask is the bit-mask of the interrupts to be disabled. +* Bit positions of 1 will be disabled. Bit positions of 0 will +* keep the previous setting. This mask is formed by OR'ing +* XDCFG_INT_* bits defined in xdevcfg_hw.h. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask) +{ + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Disable the specified interrupts in the Interrupt Mask Register. + */ + RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_MASK_OFFSET); + RegValue |= (Mask & XDCFG_IXR_ALL_MASK); + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_MASK_OFFSET, + RegValue); +} +/****************************************************************************/ +/** +* +* This function returns the enabled interrupts read from the Interrupt Mask +* Register. Use the XDCFG_INT_* constants defined in xdevcfg_hw.h +* to interpret the returned value. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return A 32-bit value representing the contents of the IMR. +* +* @note None. +* +*****************************************************************************/ +u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Return the value read from the Interrupt Mask Register. + */ + return (~ XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_MASK_OFFSET)); +} + +/****************************************************************************/ +/** +* +* This function returns the interrupt status read from Interrupt Status +* Register. Use the XDCFG_INT_* constants defined in xdevcfg_hw.h +* to interpret the returned value. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return A 32-bit value representing the contents of the Interrupt +* Status register. +* +* @note None. +* +*****************************************************************************/ +u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Return the value read from the Interrupt Status register. + */ + return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_STS_OFFSET); +} + +/****************************************************************************/ +/** +* +* This function clears the specified interrupts in the Interrupt Status +* Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Mask is the bit-mask of the interrupts to be cleared. +* Bit positions of 1 will be cleared. Bit positions of 0 will not +* change the previous interrupt status. This mask is formed by +* OR'ing XDCFG_INT_* bits which are defined in xdevcfg_hw.h. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask) +{ + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_STS_OFFSET, + Mask); + +} + +/*****************************************************************************/ +/** +* The interrupt handler for the Device Config Interface. +* +* Events are signaled to upper layer for proper handling. +* +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void XDcfg_InterruptHandler(XDcfg *InstancePtr) +{ + u32 IntrStatusReg; + + /* + * Assert validates the input arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the Interrupt status register. + */ + IntrStatusReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_STS_OFFSET); + + /* + * Write the status back to clear the interrupts so that no + * subsequent interrupts are missed while processing this interrupt. + * This also does the DMA acknowledgment automatically. + */ + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_STS_OFFSET, IntrStatusReg); + + /* + * Signal application that there are events to handle. + */ + InstancePtr->StatusHandler(InstancePtr->CallBackRef, + IntrStatusReg); + +} + +/****************************************************************************/ +/** +* +* This function sets the handler that will be called when an event (interrupt) +* occurs that needs application's attention. +* +* @param InstancePtr is a pointer to the XDcfg instance +* @param CallBackFunc is the address of the callback function. +* @param CallBackRef is a user data item that will be passed to the +* callback function when it is invoked. +* +* @return None. +* +* @note None. +* +* +*****************************************************************************/ +void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc, + void *CallBackRef) +{ + /* + * Asserts validate the input arguments + * CallBackRef not checked, no way to know what is valid + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(CallBackFunc != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + InstancePtr->StatusHandler = (XDcfg_IntrHandler) CallBackFunc; + InstancePtr->CallBackRef = CallBackRef; +} diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/xdevcfg_selftest.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/xdevcfg_selftest.c new file mode 100644 index 000000000..dc1f9f202 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/xdevcfg_selftest.c @@ -0,0 +1,120 @@ +/****************************************************************************** +* +* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license1and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdevcfg_selftest.c +* +* Contains diagnostic self-test functions for the XDcfg driver. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.02a nm  02/27/13 Fixed CR# 701348.
+*                    Peripheral test fails with  Running
+* 		     DcfgSelfTestExample() in SECURE bootmode.
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xdevcfg.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +/****************************************************************************/ +/** +* +* Run a self-test on the Device Configuration Interface. This test does a +* control register write and reads back the same value. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return +* - XST_SUCCESS if self-test was successful. +* - XST_FAILURE if fails. +* +* @note None. +* +******************************************************************************/ +int XDcfg_SelfTest(XDcfg *InstancePtr) +{ + u32 OldCfgReg; + u32 CfgReg; + int Status = XST_SUCCESS; + + /* + * Assert to ensure the inputs are valid and the instance has been + * initialized. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + OldCfgReg = XDcfg_GetControlRegister(InstancePtr); + + XDcfg_SetControlRegister(InstancePtr, XDCFG_CTRL_NIDEN_MASK); + + CfgReg = XDcfg_GetControlRegister(InstancePtr); + + if ((CfgReg & XDCFG_CTRL_NIDEN_MASK) != XDCFG_CTRL_NIDEN_MASK) { + + Status = XST_FAILURE; + } + + /* + * Restore the original values of the register + */ + XDcfg_SetControlRegister(InstancePtr, OldCfgReg); + + return Status; +} diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/xdevcfg_sinit.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/xdevcfg_sinit.c new file mode 100644 index 000000000..93b3ed9b0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_1/src/xdevcfg_sinit.c @@ -0,0 +1,99 @@ +/****************************************************************************** +* +* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xdevcfg_sinit.c +* +* This file contains method for static initialization (compile-time) of the +* driver. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xdevcfg.h" +#include "xparameters.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/*****************************************************************************/ +/** +* Lookup the device configuration based on the unique device ID. The table +* contains the configuration info for each device in the system. +* +* @param DeviceId is the unique device ID of the device being looked up. +* +* @return A pointer to the configuration table entry corresponding to the +* given device ID, or NULL if no match is found. +* +* @note None. +* +******************************************************************************/ +XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId) +{ + extern XDcfg_Config XDcfg_ConfigTable[]; + XDcfg_Config *CfgPtr = NULL; + int Index; + + for (Index = 0; Index < XPAR_XDCFG_NUM_INSTANCES; Index++) { + if (XDcfg_ConfigTable[Index].DeviceId == DeviceId) { + CfgPtr = &XDcfg_ConfigTable[Index]; + break; + } + } + + return (CfgPtr); +} diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_0/src/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_0/src/Makefile new file mode 100644 index 000000000..d1240c586 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_0/src/Makefile @@ -0,0 +1,41 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES:=*.c +INCLUDEFILES:=*.h + +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) + +libs: banner xdmaps_libs clean + +%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling dmaps" + +xdmaps_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} + +.PHONY: include +include: xdmaps_includes + +xdmaps_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS} + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_0/src/xdmaps.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_0/src/xdmaps.c new file mode 100644 index 000000000..4b489c0ef --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_0/src/xdmaps.c @@ -0,0 +1,1989 @@ +/***************************************************************************** +* +* (c) Copyright 2009-2013 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +*****************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdmaps.c +* +* This file contains the implementation of the interface functions for XDmaPs +* driver. Refer to the header file xdmaps.h for more detailed information. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  	Date     Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	hbm    08/19/2010 First Release
+* 1.00  nm     05/25/2011 Updated for minor doxygen corrections
+* 1.02a sg     05/16/2012 Made changes for doxygen and moved some function
+*			  header from the xdmaps.h file to xdmaps.c file
+*			  Other cleanup for coding guidelines and CR 657109
+*			  and CR 657898
+* 1.03a sg     07/16/2012 changed inline to __inline for CR665681
+* 1.04a nm     10/22/2012 Fixed CR# 681671.
+* 1.05a nm     04/15/2013 Fixed CR# 704396. Removed warnings when compiled
+*			  with -Wall and -Wextra option in bsp.
+*	       05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
+*			  function description.
+*			  Fixed CR# 704396. Removed unused variables
+*			  UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
+*			  function.
+* 1.07a asa    11/02/13. Made changes to fix compilation issues for iarcc.
+*			   Removed the PDBG prints. By default they were always
+*			   defined out and never used. The PDBG is non-standard for
+*			   Xilinx drivers and no other driver does something similar.
+*			   Since there is no easy way to fix compilation issues with
+*			   the IARCC compiler around PDBG, it is better to remove it.
+*			   Users can always use xil_printfs if they want to debug.
+*
+* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include + +#include "xstatus.h" +#include "xdmaps.h" +#include "xil_io.h" +#include "xil_cache.h" + +#include "xil_printf.h" + + +/************************** Constant Definitions ****************************/ + +/* The following constant defines the amount of error that is allowed for + * a specified baud rate. This error is the difference between the actual + * baud rate that will be generated using the specified clock and the + * desired baud rate. + */ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + + +/************************** Function Prototypes *****************************/ +static int XDmaPs_Exec_DMAKILL(u32 BaseAddr, + unsigned int Channel, + unsigned int Thread); + +static void XDmaPs_BufPool_Free(XDmaPs_ProgBuf *Pool, void *Buf); + +static int XDmaPs_Exec_DMAGO(u32 BaseAddr, unsigned int Channel, u32 DmaProg); + +static void XDmaPs_DoneISR_n(XDmaPs *InstPtr, unsigned Channel); +static void *XDmaPs_BufPool_Allocate(XDmaPs_ProgBuf *Pool); +static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd, + unsigned CacheLength); + +static void XDmaPs_Print_DmaProgBuf(char *Buf, int Length); + + + +/************************** Variable Definitions ****************************/ + +/****************************************************************************/ +/** +* +* Initializes a specific XDmaPs instance such that it is ready to be used. +* The data format of the device is setup for 8 data bits, 1 stop bit, and no +* parity by default. The baud rate is set to a default value specified by +* Config->DefaultBaudRate if set, otherwise it is set to 19.2K baud. The +* receive FIFO threshold is set for 8 bytes. The default operating mode of the +* driver is polled mode. +* +* @param InstPtr is a pointer to the XDmaPs instance. +* @param Config is a reference to a structure containing information +* about a specific XDmaPs driver. +* @param EffectiveAddr is the device base address in the virtual memory +* address space. The caller is responsible for keeping the +* address mapping from EffectiveAddr to the device physical base +* address unchanged once this function is invoked. Unexpected +* errors may occur if the address mapping changes after this +* function is called. If address translation is not used, pass in +* the physical address instead. +* +* @return +* +* - XST_SUCCESS on initialization completion +* +* @note None. +* +*****************************************************************************/ +int XDmaPs_CfgInitialize(XDmaPs *InstPtr, + XDmaPs_Config *Config, + u32 EffectiveAddr) +{ + int Status = XST_SUCCESS; + unsigned int CacheLength = 0; + u32 CfgReg; + unsigned Channel; + XDmaPs_ChannelData *ChanData; + + /* + * Assert validates the input arguments + */ + Xil_AssertNonvoid(InstPtr != NULL); + Xil_AssertNonvoid(Config != NULL); + + /* + * Setup the driver instance using passed in parameters + */ + InstPtr->Config.DeviceId = Config->DeviceId; + InstPtr->Config.BaseAddress = EffectiveAddr; + + CfgReg = XDmaPs_ReadReg(EffectiveAddr, XDMAPS_CR1_OFFSET); + CacheLength = CfgReg & XDMAPS_CR1_I_CACHE_LEN_MASK; + if (CacheLength < 2 || CacheLength > 5) + CacheLength = 0; + else + CacheLength = 1 << CacheLength; + + InstPtr->CacheLength = CacheLength; + + memset(InstPtr->Chans, 0, + sizeof(XDmaPs_ChannelData[XDMAPS_CHANNELS_PER_DEV])); + + for (Channel = 0; Channel < XDMAPS_CHANNELS_PER_DEV; Channel++) { + ChanData = InstPtr->Chans + Channel; + ChanData->ChanId = Channel; + ChanData->DevId = Config->DeviceId; + } + + InstPtr->IsReady = 1; + + return Status; +} + +/****************************************************************************/ +/** +* +* Reset the DMA Manager. +* +* @param InstPtr is the DMA instance. +* +* @return 0 on success, -1 on time out +* +* @note None. +* +*****************************************************************************/ +int XDmaPs_ResetManager(XDmaPs *InstPtr) +{ + int Status; + Status = XDmaPs_Exec_DMAKILL(InstPtr->Config.BaseAddress, + 0, 0); + + return Status; +} + +/****************************************************************************/ +/** +* +* Reset the specified DMA Channel. +* +* @param InstPtr is the DMA instance. +* @param Channel is the channel to be reset. +* +* @return 0 on success, -1 on time out +* +* @note None. +* +*****************************************************************************/ +int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel) +{ + int Status; + Status = XDmaPs_Exec_DMAKILL(InstPtr->Config.BaseAddress, + Channel, 1); + + return Status; + +} + +/*****************************************************************************/ +/** +* +* Driver fault interrupt service routine +* This is the one that connects the GIC +* +* @param InstPtr is the DMA instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XDmaPs_FaultISR(XDmaPs *InstPtr) +{ + + void *DmaProgBuf; + u32 Fsm; /* Fault status DMA manager register value */ + u32 Fsc; /* Fault status DMA channel register value */ + u32 FaultType; /* Fault type DMA manager register value */ + + u32 BaseAddr = InstPtr->Config.BaseAddress; + + u32 Pc; /* DMA Pc or channel Pc */ + XDmaPs_ChannelData *ChanData; + + unsigned Chan; + unsigned DevId; + + XDmaPs_Cmd *DmaCmd; + + Fsm = XDmaPs_ReadReg(BaseAddr, XDMAPS_FSM_OFFSET) & 0x01; + Fsc = XDmaPs_ReadReg(BaseAddr, XDMAPS_FSC_OFFSET) & 0xFF; + + + DevId = InstPtr->Config.DeviceId; + + if (Fsm) { + /* + * if DMA manager is fault + */ + FaultType = XDmaPs_ReadReg(BaseAddr, XDMAPS_FTM_OFFSET); + Pc = XDmaPs_ReadReg(BaseAddr, XDMAPS_DPC_OFFSET); + + xil_printf("PL330 device %d fault with type: %x at Pc %x\n", + DevId, + FaultType, Pc); + + /* kill the DMA manager thread */ + /* Should we disable interrupt?*/ + XDmaPs_Exec_DMAKILL(BaseAddr, 0, 0); + } + + /* + * check which channel faults and kill the channel thread + */ + for (Chan = 0; + Chan < XDMAPS_CHANNELS_PER_DEV; + Chan++) { + if (Fsc & (0x01 << Chan)) { + FaultType = + XDmaPs_ReadReg(BaseAddr, + XDmaPs_FTCn_OFFSET(Chan)); + Pc = XDmaPs_ReadReg(BaseAddr, + XDmaPs_CPCn_OFFSET(Chan)); + + /* kill the channel thread */ + /* Should we disable interrupt? */ + XDmaPs_Exec_DMAKILL(BaseAddr, Chan, 1); + + /* + * get the fault type and fault Pc and invoke the + * fault callback. + */ + ChanData = InstPtr->Chans + Chan; + + DmaCmd = ChanData->DmaCmdToHw; + + /* Should we check DmaCmd is not null */ + DmaCmd->DmaStatus = -1; + DmaCmd->ChanFaultType = FaultType; + DmaCmd->ChanFaultPCAddr = Pc; + ChanData->DmaCmdFromHw = DmaCmd; + ChanData->DmaCmdToHw = NULL; + + if (!ChanData->HoldDmaProg) { + DmaProgBuf = (void *)DmaCmd->GeneratedDmaProg; + if (DmaProgBuf) + XDmaPs_BufPool_Free(ChanData->ProgBufPool, + DmaProgBuf); + DmaCmd->GeneratedDmaProg = NULL; + } + + if (InstPtr->FaultHandler) + InstPtr->FaultHandler(Chan, + DmaCmd, + InstPtr->FaultRef); + + } + } + +} + +/*****************************************************************************/ +/** +* +* Set the done handler for a channel. +* +* @param InstPtr is the DMA instance. +* @param Channel is the channel number. +* @param DoneHandler is the done interrupt handler. +* @param CallbackRef is the callback reference data. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +int XDmaPs_SetDoneHandler(XDmaPs *InstPtr, + unsigned Channel, + XDmaPsDoneHandler DoneHandler, + void *CallbackRef) +{ + XDmaPs_ChannelData *ChanData; + + Xil_AssertNonvoid(InstPtr != NULL); + + if (Channel >= XDMAPS_CHANNELS_PER_DEV) + return XST_FAILURE; + + + ChanData = InstPtr->Chans + Channel; + + ChanData->DoneHandler = DoneHandler; + ChanData->DoneRef = CallbackRef; + + return 0; +} + +/*****************************************************************************/ +/** +* +* Set the fault handler for a channel. +* +* @param InstPtr is the DMA instance. +* @param FaultHandler is the fault interrupt handler. +* @param CallbackRef is the callback reference data. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +int XDmaPs_SetFaultHandler(XDmaPs *InstPtr, + XDmaPsFaultHandler FaultHandler, + void *CallbackRef) +{ + Xil_AssertNonvoid(InstPtr != NULL); + + InstPtr->FaultHandler = FaultHandler; + InstPtr->FaultRef = CallbackRef; + + return XST_SUCCESS; +} + + + +/****************************************************************************/ +/** +* Construction function for DMAEND instruction. This function fills the program +* buffer with the constructed instruction. +* +* @param DmaProg the DMA program buffer, it's the starting address for +* the instruction being constructed +* +* @return The number of bytes for this instruction which is 1. +* +* @note None. +* +*****************************************************************************/ +__inline int XDmaPs_Instr_DMAEND(char *DmaProg) +{ + /* + * DMAEND encoding: + * 7 6 5 4 3 2 1 0 + * 0 0 0 0 0 0 0 0 + */ + *DmaProg = 0x0; + + return 1; +} + +__inline void XDmaPs_Memcpy4(char *Dst, char *Src) +{ + *Dst = *Src; + *(Dst + 1) = *(Src + 1); + *(Dst + 2) = *(Src + 2); + *(Dst + 3) = *(Src + 3); +} + +/****************************************************************************/ +/** +* +* Construction function for DMAGO instruction. This function fills the program +* buffer with the constructed instruction. +* +* @param DmaProg is the DMA program buffer, it's the starting address +* for the instruction being constructed +* @param Cn is the Channel number, 0 - 7 +* @param Imm is 32-bit immediate number written to the Channel Program +* Counter. +* @param Ns is Non-secure flag. If Ns is 1, the DMA channel operates in +* the Non-secure state. If Ns is 0, the execution depends on the +* security state of the DMA manager: +* DMA manager is in the Secure state, DMA channel operates in the +* Secure state. +* DMA manager is in the Non-secure state, DMAC aborts. +* +* @return The number of bytes for this instruction which is 6. +* +* @note None +* +*****************************************************************************/ +__inline int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn, + u32 Imm, unsigned int Ns) +{ + /* + * DMAGO encoding: + * 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 + * 0 0 0 0 0 |cn[2:0]| 1 0 1 0 0 0 ns 0 + * + * 47 ... 16 + * imm[32:0] + */ + *DmaProg = 0xA0 | ((Ns << 1) & 0x02); + + *(DmaProg + 1) = (u8)(Cn & 0x07); + + // *((u32 *)(DmaProg + 2)) = Imm; + XDmaPs_Memcpy4(DmaProg + 2, (char *)&Imm); + + /* success */ + return 6; +} + +/****************************************************************************/ +/** +* +* Construction function for DMALD instruction. This function fills the program +* buffer with the constructed instruction. +* +* @param DmaProg the DMA program buffer, it's the starting address for the +* instruction being constructed +* +* @return The number of bytes for this instruction which is 1. +* +* @note None. +* +*****************************************************************************/ +__inline int XDmaPs_Instr_DMALD(char *DmaProg) +{ + /* + * DMALD encoding + * 7 6 5 4 3 2 1 0 + * 0 0 0 0 0 1 bs x + * + * Note: this driver doesn't support conditional load or store, + * so the bs bit is 0 and x bit is 0. + */ + *DmaProg = 0x04; + return 1; +} + +/****************************************************************************/ +/** +* +* Construction function for DMALP instruction. This function fills the program +* buffer with the constructed instruction. +* +* @param DmaProg is the DMA program buffer, it's the starting address +* for the instruction being constructed +* @param Lc is the Loop counter register, can either be 0 or 1. +* @param LoopIterations: the number of interations, LoopInterations - 1 +* will be encoded in the DMALP instruction. +* +* @return The number of bytes for this instruction which is 2. +* +* @note None. +* +*****************************************************************************/ +__inline int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc, + unsigned LoopIterations) +{ + /* + * DMALP encoding + * 15 ... 8 7 6 5 4 3 2 1 0 + * | iter[7:0] |0 0 1 0 0 0 lc 0 + */ + *DmaProg = (u8)(0x20 | ((Lc & 1) << 1)); + *(DmaProg + 1) = (u8)(LoopIterations - 1); + return 2; +} + +/****************************************************************************/ +/** +* +* Construction function for DMALPEND instruction. This function fills the +* program buffer with the constructed instruction. +* +* @param DmaProg is the DMA program buffer, it's the starting address +* for the instruction being constructed +* @param BodyStart is the starting address of the loop body. It is used +* to calculate the bytes of backward jump. +* @param Lc is the Loop counter register, can either be 0 or 1. +* +* @return The number of bytes for this instruction which is 2. +* +* @note None. +* +*****************************************************************************/ +__inline int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc) +{ + /* + * DMALPEND encoding + * 15 ... 8 7 6 5 4 3 2 1 0 + * | backward_jump[7:0] |0 0 1 nf 1 lc bs x + * + * lc: loop counter + * nf is for loop forever. The driver does not support loop forever, + * so nf is 1. + * The driver does not support conditional LPEND, so bs is 0, x is 0. + */ + *DmaProg = 0x38 | ((Lc & 1) << 2); + *(DmaProg + 1) = (u8)(DmaProg - BodyStart); + + return 2; +} + +/* + * Register number for the DMAMOV instruction + */ +#define XDMAPS_MOV_SAR 0x0 +#define XDMAPS_MOV_CCR 0x1 +#define XDMAPS_MOV_DAR 0x2 + +/****************************************************************************/ +/** +* +* Construction function for DMAMOV instruction. This function fills the +* program buffer with the constructed instruction. +* +* @param DmaProg is the DMA program buffer, it's the starting address +* for the instruction being constructed +* @param Rd is the register id, 0 for SAR, 1 for CCR, and 2 for DAR +* @param Imm is the 32-bit immediate number +* +* @return The number of bytes for this instruction which is 6. +* +* @note None. +* +*****************************************************************************/ +__inline int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm) +{ + /* + * DMAMOV encoding + * 15 4 3 2 1 10 ... 8 7 6 5 4 3 2 1 0 + * 0 0 0 0 0 |rd[2:0]|1 0 1 1 1 1 0 0 + * + * 47 ... 16 + * imm[32:0] + * + * rd: b000 for SAR, b001 CCR, b010 DAR + */ + *DmaProg = 0xBC; + *(DmaProg + 1) = Rd & 0x7; + // *((u32 *)(DmaProg + 2)) = Imm; + XDmaPs_Memcpy4(DmaProg + 2, (char *)&Imm); + + return 6; +} + +/****************************************************************************/ +/** +* +* Construction function for DMANOP instruction. This function fills the +* program buffer with the constructed instruction. +* +* @param DmaProg is the DMA program buffer, it's the starting address +* for the instruction being constructed +* @return The number of bytes for this instruction which is 1. +* +* @note None. +* +*****************************************************************************/ +__inline int XDmaPs_Instr_DMANOP(char *DmaProg) +{ + /* + * DMANOP encoding + * 7 6 5 4 3 2 1 0 + * 0 0 0 1 1 0 0 0 + */ + *DmaProg = 0x18; + return 1; +} + +/****************************************************************************/ +/** +* +* Construction function for DMARMB instruction. This function fills the +* program buffer with the constructed instruction. +* +* @param DmaProg is the DMA program buffer, it's the starting address +* for the instruction being constructed +* +* @return The number of bytes for this instruction which is 1. +* +* @note None. +* +*****************************************************************************/ +__inline int XDmaPs_Instr_DMARMB(char *DmaProg) +{ + /* + * DMARMB encoding + * 7 6 5 4 3 2 1 0 + * 0 0 0 1 0 0 1 0 + */ + *DmaProg = 0x12; + return 1; +} + +/****************************************************************************/ +/** +* +* Construction function for DMASEV instruction. This function fills the +* program buffer with the constructed instruction. +* +* @param DmaProg is the DMA program buffer, it's the starting address +* for the instruction being constructed +* @param EventNumber is the Event number to signal. +* +* @return The number of bytes for this instruction which is 2. +* +* @note None. +* +*****************************************************************************/ +__inline int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber) +{ + /* + * DMASEV encoding + * 15 4 3 2 1 10 9 8 7 6 5 4 3 2 1 0 + * |event[4:0]| 0 0 0 0 0 1 1 0 1 0 0 + */ + *DmaProg = 0x34; + *(DmaProg + 1) = (u8)(EventNumber << 3); + + return 2; +} + + +/****************************************************************************/ +/** +* +* Construction function for DMAST instruction. This function fills the +* program buffer with the constructed instruction. +* +* @param DmaProg is the DMA program buffer, it's the starting address +* for the instruction being constructed +* +* @return The number of bytes for this instruction which is 1. +* +* @note None. +* +*****************************************************************************/ +__inline int XDmaPs_Instr_DMAST(char *DmaProg) +{ + /* + * DMAST encoding + * 7 6 5 4 3 2 1 0 + * 0 0 0 0 1 0 bs x + * + * Note: this driver doesn't support conditional load or store, + * so the bs bit is 0 and x bit is 0. + */ + *DmaProg = 0x08; + return 1; +} + + +/****************************************************************************/ +/** +* +* Construction function for DMAWMB instruction. This function fills the +* program buffer with the constructed instruction. +* +* @param DmaProg is the DMA program buffer, it's the starting address +* for the instruction being constructed +* +* @return The number of bytes for this instruction which is 1. +* +* @note None. +* +*****************************************************************************/ +__inline int XDmaPs_Instr_DMAWMB(char *DmaProg) +{ + /* + * DMAWMB encoding + * 7 6 5 4 3 2 1 0 + * 0 0 0 1 0 0 1 0 + */ + *DmaProg = 0x13; + return 1; +} + +/****************************************************************************/ +/** +* +* Conversion function from the endian swap size to the bit encoding of the CCR +* +* @param EndianSwapSize is the endian swap size, in terms of bits, it +* could be 8, 16, 32, 64, or 128(We are using DMA assembly syntax) +* +* @return The endian swap size bit encoding for the CCR. +* +* @note None. +* +*****************************************************************************/ +__inline unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize) +{ + switch (EndianSwapSize) { + case 0: + case 8: + return 0; + case 16: + return 1; + case 32: + return 2; + case 64: + return 3; + case 128: + return 4; + default: + return 0; + } + +} + +/****************************************************************************/ +/** +* +* Conversion function from the burst size to the bit encoding of the CCR +* +* @param BurstSize is the burst size. It's the data width. +* In terms of bytes, it could be 1, 2, 4, 8, 16, 32, 64, or 128. +* It must be no larger than the bus width. +* (We are using DMA assembly syntax.) +* +* @note None. +* +*****************************************************************************/ +__inline unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize) +{ + switch (BurstSize) { + case 1: + return 0; + case 2: + return 1; + case 4: + return 2; + case 8: + return 3; + case 16: + return 4; + case 32: + return 5; + case 64: + return 6; + case 128: + return 7; + default: + return 0; + } +} + + +/****************************************************************************/ +/** +* +* Conversion function from PL330 bus transfer descriptors to CCR value. All the +* values passed to the functions are in terms of assembly languages, not in +* terms of the register bit encoding. +* +* @param ChanCtrl is the Instance of XDmaPs_ChanCtrl. +* +* @return The 32-bit CCR value. +* +* @note None. +* +*****************************************************************************/ +u32 XDmaPs_ToCCRValue(XDmaPs_ChanCtrl *ChanCtrl) +{ + /* + * Channel Control Register encoding + * [31:28] - endian_swap_size + * [27:25] - dst_cache_ctrl + * [24:22] - dst_prot_ctrl + * [21:18] - dst_burst_len + * [17:15] - dst_burst_size + * [14] - dst_inc + * [13:11] - src_cache_ctrl + * [10:8] - src_prot_ctrl + * [7:4] - src_burst_len + * [3:1] - src_burst_size + * [0] - src_inc + */ + + unsigned es = + XDmaPs_ToEndianSwapSizeBits(ChanCtrl->EndianSwapSize); + + unsigned dst_burst_size = + XDmaPs_ToBurstSizeBits(ChanCtrl->DstBurstSize); + unsigned dst_burst_len = (ChanCtrl->DstBurstLen - 1) & 0x0F; + unsigned dst_cache_ctrl = (ChanCtrl->DstCacheCtrl & 0x03) + | ((ChanCtrl->DstCacheCtrl & 0x08) >> 1); + unsigned dst_prot_ctrl = ChanCtrl->DstProtCtrl & 0x07; + unsigned dst_inc_bit = ChanCtrl->DstInc & 1; + + unsigned src_burst_size = + XDmaPs_ToBurstSizeBits(ChanCtrl->SrcBurstSize); + unsigned src_burst_len = (ChanCtrl->SrcBurstLen - 1) & 0x0F; + unsigned src_cache_ctrl = (ChanCtrl->SrcCacheCtrl & 0x03) + | ((ChanCtrl->SrcCacheCtrl & 0x08) >> 1); + unsigned src_prot_ctrl = ChanCtrl->SrcProtCtrl & 0x07; + unsigned src_inc_bit = ChanCtrl->SrcInc & 1; + + u32 ccr_value = (es << 28) + | (dst_cache_ctrl << 25) + | (dst_prot_ctrl << 22) + | (dst_burst_len << 18) + | (dst_burst_size << 15) + | (dst_inc_bit << 14) + | (src_cache_ctrl << 11) + | (src_prot_ctrl << 8) + | (src_burst_len << 4) + | (src_burst_size << 1) + | (src_inc_bit); + + return ccr_value; +} + +/****************************************************************************/ +/** +* Construct a loop with only DMALD and DMAST as the body using loop counter 0. +* The function also makes sure the loop body and the lpend is in the same +* cache line. +* +* @param DmaProgStart is the very start address of the DMA program. +* This is used to calculate whether the loop is in a cache line. +* @param CacheLength is the icache line length, in terms of bytes. +* If it's zero, the performance enhancement feature will be +* turned off. +* @param DmaProgLoopStart The starting address of the loop (DMALP). +* @param LoopCount The inner loop count. Loop count - 1 will be used to +* initialize the loop counter. +* +* @return The number of bytes the loop has. +* +* @note None. +* +*****************************************************************************/ +int XDmaPs_ConstructSingleLoop(char *DmaProgStart, + int CacheLength, + char *DmaProgLoopStart, + int LoopCount) +{ + int CacheStartOffset; + int CacheEndOffset; + int NumNops; + char *DmaProgBuf = DmaProgLoopStart; + + DmaProgBuf += XDmaPs_Instr_DMALP(DmaProgBuf, 0, LoopCount); + + if (CacheLength > 0) { + /* + * the CacheLength > 0 switch is ued to turn on/off nop + * insertion + */ + CacheStartOffset = DmaProgBuf - DmaProgStart; + CacheEndOffset = CacheStartOffset + 3; + + /* + * check whether the body and lpend fit in one cache line + */ + if (CacheStartOffset / CacheLength + != CacheEndOffset / CacheLength) { + /* insert the nops */ + NumNops = CacheLength + - CacheStartOffset % CacheLength; + while (NumNops--) { + DmaProgBuf += + XDmaPs_Instr_DMANOP(DmaProgBuf); + } + } + } + + DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf); + DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf); + DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf, + DmaProgBuf - 2, 0); + + return DmaProgBuf - DmaProgLoopStart; +} + +/****************************************************************************/ +/** +* Construct a nested loop with only DMALD and DMAST in the inner loop body. +* It uses loop counter 1 for the outer loop and loop counter 0 for the +* inner loop. +* +* @param DmaProgStart is the very start address of the DMA program. +* This is used to calculate whether the loop is in a cache line. +* @param CacheLength is the icache line length, in terms of bytes. +* If it's zero, the performance enhancement feature will be +* turned off. +* @param DmaProgLoopStart The starting address of the loop (DMALP). +* @param LoopCountOuter The outer loop count. Loop count - 1 will be +* used to initialize the loop counter. +* @param LoopCountInner The inner loop count. Loop count - 1 will be +* used to initialize the loop counter. +* +* @return The number byes the nested loop program has. +* +* @note None. +* +*****************************************************************************/ +int XDmaPs_ConstructNestedLoop(char *DmaProgStart, + int CacheLength, + char *DmaProgLoopStart, + unsigned int LoopCountOuter, + unsigned int LoopCountInner) +{ + int CacheStartOffset; + int CacheEndOffset; + int NumNops; + char *InnerLoopStart; + char *DmaProgBuf = DmaProgLoopStart; + + DmaProgBuf += XDmaPs_Instr_DMALP(DmaProgBuf, 1, LoopCountOuter); + InnerLoopStart = DmaProgBuf; + + if (CacheLength > 0) { + /* + * the CacheLength > 0 switch is ued to turn on/off nop + * insertion + */ + if (CacheLength < 8) { + /* + * if the cache line is too small to fit both loops + * just align the inner loop + */ + DmaProgBuf += + XDmaPs_ConstructSingleLoop(DmaProgStart, + CacheLength, + DmaProgBuf, + LoopCountInner); + /* outer loop end */ + DmaProgBuf += + XDmaPs_Instr_DMALPEND(DmaProgBuf, + InnerLoopStart, + 1); + + /* + * the nested loop is constructed for + * smaller cache line + */ + return DmaProgBuf - DmaProgLoopStart; + } + + /* + * Now let's handle the case where a cache line can + * fit the nested loops. + */ + CacheStartOffset = DmaProgBuf - DmaProgStart; + CacheEndOffset = CacheStartOffset + 7; + + /* + * check whether the body and lpend fit in one cache line + */ + if (CacheStartOffset / CacheLength + != CacheEndOffset / CacheLength) { + /* insert the nops */ + NumNops = CacheLength + - CacheStartOffset % CacheLength; + while (NumNops--) { + DmaProgBuf += + XDmaPs_Instr_DMANOP(DmaProgBuf); + } + } + } + + /* insert the inner DMALP */ + DmaProgBuf += XDmaPs_Instr_DMALP(DmaProgBuf, 0, LoopCountInner); + + /* DMALD and DMAST instructions */ + DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf); + DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf); + + /* inner DMALPEND */ + DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf, + DmaProgBuf - 2, 0); + /* outer DMALPEND */ + DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf, + InnerLoopStart, 1); + + /* return the number of bytes */ + return DmaProgBuf - DmaProgLoopStart; +} + +/* + * [31:28] endian_swap_size b0000 + * [27:25] dst_cache_ctrl b000 + * [24:22] dst_prot_ctrl b000 + * [21:18] dst_burst_len b0000 + * [17:15] dst_burst_size b000 + * [14] dst_inc b0 + * [27:25] src_cache_ctrl b000 + * [24:22] src_prot_ctrl b000 + * [21:18] src_burst_len b0000 + * [17:15] src_burst_size b000 + * [14] src_inc b0 + */ +#define XDMAPS_CCR_SINGLE_BYTE (0x0) +#define XDMAPS_CCR_M2M_SINGLE_BYTE ((0x1 << 14) | 0x1) + + +/****************************************************************************/ +/** +* +* Construct the DMA program based on the descriptions of the DMA transfer. +* The function handles memory to memory DMA transfers. +* It also handles unalgined head and small amount of residue tail. +* +* @param Channel DMA channel number +* @param Cmd is the DMA command. +* @param CacheLength is the icache line length, in terms of bytes. +* If it's zero, the performance enhancement feature will be +* turned off. +* +* @returns The number of bytes for the program. +* +* @note None. +* +*****************************************************************************/ +static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd, + unsigned CacheLength) +{ + /* + * unpack arguments + */ + char *DmaProgBuf = (char *)Cmd->GeneratedDmaProg; + unsigned DevChan = Channel; + unsigned long DmaLength = Cmd->BD.Length; + u32 SrcAddr = Cmd->BD.SrcAddr; + + unsigned SrcInc = Cmd->ChanCtrl.SrcInc; + u32 DstAddr = Cmd->BD.DstAddr; + unsigned DstInc = Cmd->ChanCtrl.DstInc; + + char *DmaProgStart = DmaProgBuf; + + unsigned int BurstBytes; + unsigned int LoopCount; + unsigned int LoopCount1 = 0; + unsigned int LoopResidue = 0; + unsigned int TailBytes; + unsigned int TailWords; + int DmaProgBytes; + u32 CCRValue; + unsigned int Unaligned; + unsigned int UnalignedCount; + unsigned int MemBurstSize = 1; + u32 MemAddr = 0; + unsigned int Index; + unsigned int SrcUnaligned = 0; + unsigned int DstUnaligned = 0; + + XDmaPs_ChanCtrl *ChanCtrl; + XDmaPs_ChanCtrl WordChanCtrl; + static XDmaPs_ChanCtrl Mem2MemByteCC; + + Mem2MemByteCC.EndianSwapSize = 0; + Mem2MemByteCC.DstCacheCtrl = 0; + Mem2MemByteCC.DstProtCtrl = 0; + Mem2MemByteCC.DstBurstLen = 1; + Mem2MemByteCC.DstBurstSize = 1; + Mem2MemByteCC.DstInc = 1; + Mem2MemByteCC.SrcCacheCtrl = 0; + Mem2MemByteCC.SrcProtCtrl = 0; + Mem2MemByteCC.SrcBurstLen = 1; + Mem2MemByteCC.SrcBurstSize = 1; + Mem2MemByteCC.SrcInc = 1; + + ChanCtrl = &Cmd->ChanCtrl; + + /* insert DMAMOV for SAR and DAR */ + DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf, + XDMAPS_MOV_SAR, + SrcAddr); + DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf, + XDMAPS_MOV_DAR, + DstAddr); + + + if (ChanCtrl->SrcInc) + SrcUnaligned = SrcAddr % ChanCtrl->SrcBurstSize; + + if (ChanCtrl->DstInc) + DstUnaligned = DstAddr % ChanCtrl->DstBurstSize; + + if ((SrcUnaligned && DstInc) || (DstUnaligned && SrcInc)) { + ChanCtrl = &Mem2MemByteCC; + } + + if (ChanCtrl->SrcInc) { + MemBurstSize = ChanCtrl->SrcBurstSize; + MemAddr = SrcAddr; + + } else if (ChanCtrl->DstInc) { + MemBurstSize = ChanCtrl->DstBurstSize; + MemAddr = DstAddr; + } + + /* check whether the head is aligned or not */ + Unaligned = MemAddr % MemBurstSize; + + if (Unaligned) { + /* if head is unaligned, transfer head in bytes */ + UnalignedCount = MemBurstSize - Unaligned; + CCRValue = XDMAPS_CCR_SINGLE_BYTE + | (SrcInc & 1) + | ((DstInc & 1) << 14); + + DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf, + XDMAPS_MOV_CCR, + CCRValue); + + for (Index = 0; Index < UnalignedCount; Index++) { + DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf); + DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf); + } + + DmaLength -= UnalignedCount; + } + + /* now the burst transfer part */ + CCRValue = XDmaPs_ToCCRValue(ChanCtrl); + DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf, + XDMAPS_MOV_CCR, + CCRValue); + + BurstBytes = ChanCtrl->SrcBurstSize * ChanCtrl->SrcBurstLen; + + LoopCount = DmaLength / BurstBytes; + TailBytes = DmaLength % BurstBytes; + + /* + * the loop count register is 8-bit wide, so if we need + * a larger loop, we need to have nested loops + */ + if (LoopCount > 256) { + LoopCount1 = LoopCount / 256; + if (LoopCount1 > 256) { + xil_printf("DMA operation cannot fit in a 2-level " + "loop for channel %d, please reduce the " + "DMA length or increase the burst size or " + "length", + Channel); + return 0; + } + LoopResidue = LoopCount % 256; + + if (LoopCount1 > 1) + DmaProgBuf += + XDmaPs_ConstructNestedLoop(DmaProgStart, + CacheLength, + DmaProgBuf, + LoopCount1, + 256); + else + DmaProgBuf += + XDmaPs_ConstructSingleLoop(DmaProgStart, + CacheLength, + DmaProgBuf, + 256); + + /* there will be some that cannot be covered by + * nested loops + */ + LoopCount = LoopResidue; + } + + if (LoopCount > 0) { + DmaProgBuf += XDmaPs_ConstructSingleLoop(DmaProgStart, + CacheLength, + DmaProgBuf, + LoopCount); + } + + if (TailBytes) { + /* handle the tail */ + TailWords = TailBytes / MemBurstSize; + TailBytes = TailBytes % MemBurstSize; + + if (TailWords) { + WordChanCtrl = *ChanCtrl; + /* + * if we can transfer the tail in words, we will + * transfer words as much as possible + */ + WordChanCtrl.SrcBurstSize = MemBurstSize; + WordChanCtrl.SrcBurstLen = 1; + WordChanCtrl.DstBurstSize = MemBurstSize; + WordChanCtrl.DstBurstLen = 1; + + + /* + * the burst length is 1 + */ + CCRValue = XDmaPs_ToCCRValue(&WordChanCtrl); + + DmaProgBuf += + XDmaPs_Instr_DMAMOV(DmaProgBuf, + XDMAPS_MOV_CCR, + CCRValue); + DmaProgBuf += + XDmaPs_ConstructSingleLoop(DmaProgStart, + CacheLength, + DmaProgBuf, + TailWords); + + } + + if (TailBytes) { + /* + * for the rest, we'll tranfer in bytes + */ + /* + * So far just to be safe, the tail bytes + * are transfered in a loop. We can optimize a little + * to perform a burst. + */ + CCRValue = XDMAPS_CCR_SINGLE_BYTE + | (SrcInc & 1) + | ((DstInc & 1) << 14); + + DmaProgBuf += + XDmaPs_Instr_DMAMOV(DmaProgBuf, + XDMAPS_MOV_CCR, + CCRValue); + + DmaProgBuf += + XDmaPs_ConstructSingleLoop(DmaProgStart, + CacheLength, + DmaProgBuf, + TailBytes); + + } + } + + DmaProgBuf += XDmaPs_Instr_DMASEV(DmaProgBuf, DevChan); + DmaProgBuf += XDmaPs_Instr_DMAEND(DmaProgBuf); + + DmaProgBytes = DmaProgBuf - DmaProgStart; + + Xil_DCacheFlushRange((u32)DmaProgStart, DmaProgBytes); + + return DmaProgBytes; + +} + + +/****************************************************************************/ +/** +* +* Generate a DMA program based for the DMA command, the buffer will be pointed +* by the GeneratedDmaProg field of the command. +* +* @param InstPtr is then DMA instance. +* @param Channel is the DMA channel number. +* @param Cmd is the DMA command. +* +* @return - XST_SUCCESS on success. +* - XST_FAILURE if it fails +* +* @note None. +* +*****************************************************************************/ +int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel, XDmaPs_Cmd *Cmd) +{ + void *Buf; + int ProgLen; + XDmaPs_ChannelData *ChanData; + XDmaPs_ChanCtrl *ChanCtrl; + + Xil_AssertNonvoid(InstPtr != NULL); + Xil_AssertNonvoid(Cmd != NULL); + + + if (Channel > XDMAPS_CHANNELS_PER_DEV) + return XST_FAILURE; + + ChanData = InstPtr->Chans + Channel; + ChanCtrl = &Cmd->ChanCtrl; + + if (ChanCtrl->SrcBurstSize * ChanCtrl->SrcBurstLen + != ChanCtrl->DstBurstSize * ChanCtrl->DstBurstLen) { + xil_printf("source burst_size * burst_len does not match " + "that of destination\r\n"); + return XST_FAILURE; + } + + + /* + * unaligned fixed address is not supported + */ + if (!ChanCtrl->SrcInc && Cmd->BD.SrcAddr % ChanCtrl->SrcBurstSize) { + xil_printf("source address is fixed but is unaligned\r\n"); + return XST_FAILURE; + } + + if (!ChanCtrl->DstInc && Cmd->BD.DstAddr % ChanCtrl->DstBurstSize) { + xil_printf("destination address is fixed but is " + "unaligned\r\n"); + return XST_FAILURE; + } + + Buf = XDmaPs_BufPool_Allocate(ChanData->ProgBufPool); + if (Buf == NULL) { + xil_printf("failed to allocate program buffer\r\n"); + return XST_FAILURE; + } + + Cmd->GeneratedDmaProg = Buf; + ProgLen = XDmaPs_BuildDmaProg(Channel, Cmd, + InstPtr->CacheLength); + Cmd->GeneratedDmaProgLength = ProgLen; + + +#ifdef XDMAPS_DEBUG + XDmaPs_Print_DmaProg(Cmd); +#endif + + if (ProgLen <= 0) { + /* something wrong, release the buffer */ + XDmaPs_BufPool_Free(ChanData->ProgBufPool, Buf); + Cmd->GeneratedDmaProgLength = 0; + Cmd->GeneratedDmaProg = NULL; + return XST_FAILURE; + } + + return XST_SUCCESS; +} + + +/****************************************************************************/ +/** + * Free the DMA program buffer that is pointed by the GeneratedDmaProg field + * of the command. + * + * @param InstPtr is then DMA instance. + * @param Channel is the DMA channel number. + * @param Cmd is the DMA command. + * + * @return XST_SUCCESS on success. + * XST_FAILURE if there is any error. + * + * @note None. + * + ****************************************************************************/ +int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel, XDmaPs_Cmd *Cmd) +{ + + void *Buf; + XDmaPs_ChannelData *ChanData; + + Xil_AssertNonvoid(InstPtr != NULL); + Xil_AssertNonvoid(Cmd != NULL); + + if (Channel > XDMAPS_CHANNELS_PER_DEV) + return XST_FAILURE; + + Buf = (void *)Cmd->GeneratedDmaProg; + ChanData = InstPtr->Chans + Channel; + + if (Buf) { + XDmaPs_BufPool_Free(ChanData->ProgBufPool, Buf); + Cmd->GeneratedDmaProg = 0; + Cmd->GeneratedDmaProgLength = 0; + } + + return XST_SUCCESS; +} + + +/****************************************************************************/ +/** +* +* Start a DMA command. The command can only be invoked when the channel +* is idle. The driver takes the command, generates DMA program if needed, +* then pass the program to DMAC to execute. +* +* @param InstPtr is then DMA instance. +* @param Channel is the DMA channel number. +* @param Cmd is the DMA command. +* @param HoldDmaProg is tag indicating whether the driver can release +* the allocated DMA buffer or not. If a user wants to examine the +* generated DMA program, the flag should be set to 1. After the +* DMA program is finished, a user needs to explicity free the +* buffer. +* +* @return +* - XST_SUCCESS on success +* - XST_DEVICE_BUSY if DMA is busy +* - XST_FAILURE on other failures +* +* @note None. +* +****************************************************************************/ +int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel, + XDmaPs_Cmd *Cmd, + int HoldDmaProg) +{ + int Status; + u32 DmaProg = 0; + u32 Inten; + + Xil_AssertNonvoid(InstPtr != NULL); + Xil_AssertNonvoid(Cmd != NULL); + + + Cmd->DmaStatus = XST_FAILURE; + + if (XDmaPs_IsActive(InstPtr, Channel)) + return XST_DEVICE_BUSY; + + if (!Cmd->UserDmaProg && !Cmd->GeneratedDmaProg) { + Status = XDmaPs_GenDmaProg(InstPtr, Channel, Cmd); + if (Status) + return XST_FAILURE; + } + + InstPtr->Chans[Channel].HoldDmaProg = HoldDmaProg; + + if (Cmd->UserDmaProg) + DmaProg = (u32)Cmd->UserDmaProg; + else if (Cmd->GeneratedDmaProg) + DmaProg = (u32)Cmd->GeneratedDmaProg; + + if (DmaProg) { + /* enable the interrupt */ + Inten = XDmaPs_ReadReg(InstPtr->Config.BaseAddress, + XDMAPS_INTEN_OFFSET); + Inten |= 0x01 << Channel; /* set the correpsonding bit */ + XDmaPs_WriteReg(InstPtr->Config.BaseAddress, + XDMAPS_INTEN_OFFSET, + Inten); + Inten = XDmaPs_ReadReg(InstPtr->Config.BaseAddress, + XDMAPS_INTEN_OFFSET); + + InstPtr->Chans[Channel].DmaCmdToHw = Cmd; + + if (Cmd->ChanCtrl.SrcInc) { + Xil_DCacheFlushRange(Cmd->BD.SrcAddr, Cmd->BD.Length); + } + if (Cmd->ChanCtrl.DstInc) { + Xil_DCacheInvalidateRange(Cmd->BD.DstAddr, + Cmd->BD.Length); + } + + Status = XDmaPs_Exec_DMAGO(InstPtr->Config.BaseAddress, + Channel, DmaProg); + } + else { + InstPtr->Chans[Channel].DmaCmdToHw = NULL; + Status = XST_FAILURE; + } + + return Status; +} + +/****************************************************************************/ +/** +* +* Checks whether the DMA channel is active or idle. +* +* @param InstPtr is the DMA instance. +* @param Channel is the DMA channel number. +* +* @return 0: if the channel is idle +* 1: otherwise +* +* @note None. +* +*****************************************************************************/ +int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel) +{ + Xil_AssertNonvoid(InstPtr != NULL); + + /* Need to assert Channel is in range */ + if (Channel > XDMAPS_CHANNELS_PER_DEV) + return 0; + + return InstPtr->Chans[Channel].DmaCmdToHw != NULL; +} + + + +/****************************************************************************/ +/** +* +* Allocate a buffer of the DMA program buffer from the pool. +* +* @param Pool the DMA program pool. +* +* @return The allocated buffer, NULL if there is any error. +* +* @note None. +* +*****************************************************************************/ +static void *XDmaPs_BufPool_Allocate(XDmaPs_ProgBuf *Pool) +{ + int Index; + + Xil_AssertNonvoid(Pool != NULL); + + for (Index = 0; Index < XDMAPS_MAX_CHAN_BUFS; Index++) { + if (!Pool[Index].Allocated) { + Pool[Index].Allocated = 1; + return Pool[Index].Buf; + } + } + + return NULL; + +} + +/*****************************************************************************/ +/** +* +* Driver done interrupt service routine for channel 0. We need this done ISR +* mainly because the driver needs to release the DMA program buffer. +* This is the one that connects the GIC +* +* @param InstPtr is the DMA instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XDmaPs_DoneISR_0(XDmaPs *InstPtr) +{ + XDmaPs_DoneISR_n(InstPtr, 0); +} + +/*****************************************************************************/ +/** +* +* Driver done interrupt service routine for channel 1. We need this done ISR +* mainly because the driver needs to release the DMA program buffer. +* This is the one that connects the GIC +* +* @param InstPtr is the DMA instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XDmaPs_DoneISR_1(XDmaPs *InstPtr) +{ + XDmaPs_DoneISR_n(InstPtr, 1); +} + +/*****************************************************************************/ +/** +* +* Driver done interrupt service routine for channel 2. We need this done ISR +* mainly because the driver needs to release the DMA program buffer. +* This is the one that connects the GIC +* +* @param InstPtr is the DMA instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XDmaPs_DoneISR_2(XDmaPs *InstPtr) +{ + XDmaPs_DoneISR_n(InstPtr, 2); +} + +/*****************************************************************************/ +/** +* +* Driver done interrupt service routine for channel 3. We need this done ISR +* mainly because the driver needs to release the DMA program buffer. +* This is the one that connects the GIC +* +* @param InstPtr is the DMA instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XDmaPs_DoneISR_3(XDmaPs *InstPtr) +{ + XDmaPs_DoneISR_n(InstPtr, 3); +} + +/*****************************************************************************/ +/** +* +* Driver done interrupt service routine for channel 4. We need this done ISR +* mainly because the driver needs to release the DMA program buffer. +* This is the one that connects the GIC +* +* @param InstPtr is the DMA instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XDmaPs_DoneISR_4(XDmaPs *InstPtr) +{ + XDmaPs_DoneISR_n(InstPtr, 4); +} + +/*****************************************************************************/ +/** +* +* Driver done interrupt service routine for channel 5. We need this done ISR +* mainly because the driver needs to release the DMA program buffer. +* This is the one that connects the GIC +* +* @param InstPtr is the DMA instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XDmaPs_DoneISR_5(XDmaPs *InstPtr) +{ + XDmaPs_DoneISR_n(InstPtr, 5); +} + +/*****************************************************************************/ +/** +* +* Driver done interrupt service routine for channel 6. We need this done ISR +* mainly because the driver needs to release the DMA program buffer. +* This is the one that connects the GIC +* +* @param InstPtr is the DMA instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XDmaPs_DoneISR_6(XDmaPs *InstPtr) +{ + XDmaPs_DoneISR_n(InstPtr, 6); +} + +/*****************************************************************************/ +/** +* +* Driver done interrupt service routine for channel 7. We need this done ISR +* mainly because the driver needs to release the DMA program buffer. +* This is the one that connects the GIC +* +* @param InstPtr is the DMA instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XDmaPs_DoneISR_7(XDmaPs *InstPtr) +{ + XDmaPs_DoneISR_n(InstPtr, 7); +} + +#ifndef XDMAPS_MAX_WAIT +#define XDMAPS_MAX_WAIT 4000 +#endif + +/****************************************************************************/ +/** +* Use the debug registers to kill the DMA thread. +* +* @param BaseAddr is DMA device base address. +* @param Channel is the DMA channel number. +* @param Thread is Debug thread encoding. +* 0: DMA manager thread, 1: DMA channel. +* +* @return 0 on success, -1 on time out +* +* @note None. +* +*****************************************************************************/ +static int XDmaPs_Exec_DMAKILL(u32 BaseAddr, + unsigned int Channel, + unsigned int Thread) +{ + u32 DbgInst0; + int WaitCount; + + DbgInst0 = XDmaPs_DBGINST0(0, 0x01, Channel, Thread); + + /* wait while debug status is busy */ + WaitCount = 0; + while ((XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET) + & XDMAPS_DBGSTATUS_BUSY) + && (WaitCount < XDMAPS_MAX_WAIT)) + WaitCount++; + + if (WaitCount >= XDMAPS_MAX_WAIT) { + /* wait time out */ + xil_printf("PL330 device at %x debug status busy time out\n", + BaseAddr); + + return -1; + } + + /* write debug instruction 0 */ + XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST0_OFFSET, DbgInst0); + + XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST1_OFFSET, 0); + + + /* run the command in DbgInst0 and DbgInst1 */ + XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGCMD_OFFSET, 0); + + return 0; +} + +/****************************************************************************/ +/** +* +* +* Free a buffer of the DMA program buffer. +* @param Pool the DMA program pool. +* @param Buf the DMA program buffer to be release. +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void XDmaPs_BufPool_Free(XDmaPs_ProgBuf *Pool, void *Buf) +{ + int Index; + Xil_AssertVoid(Pool != NULL); + + for (Index = 0; Index < XDMAPS_MAX_CHAN_BUFS; Index++) { + if (Pool[Index].Buf == Buf) { + if (Pool[Index].Allocated) { + Pool[Index].Allocated = 0; + } + } + } +} + +/*****************************************************************************/ +/** +* XDmaPs_Exec_DMAGO - Execute the DMAGO to start a channel. +* +* @param BaseAddr PL330 device base address +* @param Channel Channel number for the device +* @param DmaProg DMA program starting address, this should be DMA address +* +* @return 0 on success, -1 on time out +* +* @note None. +* +****************************************************************************/ +static int XDmaPs_Exec_DMAGO(u32 BaseAddr, unsigned int Channel, u32 DmaProg) +{ + char DmaGoProg[8]; + u32 DbgInst0; + u32 DbgInst1; + + int WaitCount; + + XDmaPs_Instr_DMAGO(DmaGoProg, Channel, DmaProg, 0); + + DbgInst0 = XDmaPs_DBGINST0(*(DmaGoProg + 1), *DmaGoProg, 0, 0); + DbgInst1 = (u32)DmaProg; + + /* wait while debug status is busy */ + WaitCount = 0; + while ((XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET) + & XDMAPS_DBGSTATUS_BUSY) + && (WaitCount < XDMAPS_MAX_WAIT)) { + + WaitCount++; + } + + if (WaitCount >= XDMAPS_MAX_WAIT) { + xil_printf("PL330 device at %x debug status busy time out\r\n", + BaseAddr); + return -1; + } + + /* write debug instruction 0 */ + XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST0_OFFSET, DbgInst0); + /* write debug instruction 1 */ + XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST1_OFFSET, DbgInst1); + + + /* wait while the DMA Manager is busy */ + WaitCount = 0; + while ((XDmaPs_ReadReg(BaseAddr, + XDMAPS_DS_OFFSET) & XDMAPS_DS_DMA_STATUS) + != XDMAPS_DS_DMA_STATUS_STOPPED + && WaitCount <= XDMAPS_MAX_WAIT) { + WaitCount++; + } + + if (WaitCount >= XDMAPS_MAX_WAIT) { + xil_printf("PL330 device at %x debug status busy time out\r\n", + BaseAddr); + return -1; + } + + /* run the command in DbgInst0 and DbgInst1 */ + XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGCMD_OFFSET, 0); + + return 0; +} + + +/****************************************************************************/ +/** +* +* It's the generic Done ISR. +* @param InstPtr is the DMA instance. +* @param Channel is the DMA channel numer. +* +* @return None.* +* +* @note None. +* +*****************************************************************************/ +static void XDmaPs_DoneISR_n(XDmaPs *InstPtr, unsigned Channel) +{ + + void *DmaProgBuf; + XDmaPs_ChannelData *ChanData; + XDmaPs_Cmd *DmaCmd; + //u32 Value; + + ChanData = InstPtr->Chans + Channel; + + /*Value = XDmaPs_ReadReg(InstPtr->Config.BaseAddress, + XDMAPS_INTSTATUS_OFFSET);*/ + + /* clear the interrupt status */ + XDmaPs_WriteReg(InstPtr->Config.BaseAddress, + XDMAPS_INTCLR_OFFSET, + 1 << ChanData->ChanId); + + /*Value = XDmaPs_ReadReg(InstPtr->Config.BaseAddress, + XDMAPS_INTSTATUS_OFFSET);*/ + + + if ((DmaCmd = ChanData->DmaCmdToHw)) { + if (!ChanData->HoldDmaProg) { + DmaProgBuf = (void *)DmaCmd->GeneratedDmaProg; + if (DmaProgBuf) + XDmaPs_BufPool_Free(ChanData->ProgBufPool, + DmaProgBuf); + DmaCmd->GeneratedDmaProg = NULL; + } + + DmaCmd->DmaStatus = 0; + ChanData->DmaCmdToHw = NULL; + ChanData->DmaCmdFromHw = DmaCmd; + + if (ChanData->DoneHandler) + ChanData->DoneHandler(Channel, DmaCmd, + ChanData->DoneRef); + } + +} + + +/****************************************************************************/ +/** +* Prints the content of the buffer in bytes +* @param Buf is the buffer. +* @param Length is the length of the DMA program. +* +* @return None. +* +* @note None. +****************************************************************************/ +static void XDmaPs_Print_DmaProgBuf(char *Buf, int Length) +{ + int Index; + for (Index = 0; Index < Length; Index++) + xil_printf("[%x] %x\r\n", Index, Buf[Index]); + +} +/****************************************************************************/ +/** +* Print the Dma Prog Contents. +* +* @param Cmd is the command buffer. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ + void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd) +{ + if (Cmd->GeneratedDmaProg && Cmd->GeneratedDmaProgLength) { + xil_printf("Generated DMA program (%d):\r\n", + Cmd->GeneratedDmaProgLength); + XDmaPs_Print_DmaProgBuf((char *)Cmd->GeneratedDmaProg, + Cmd->GeneratedDmaProgLength); + } + + if (Cmd->UserDmaProg && Cmd->UserDmaProgLength) { + xil_printf("User defined DMA program (%d):\r\n", + Cmd->UserDmaProgLength); + XDmaPs_Print_DmaProgBuf((char *)Cmd->UserDmaProg, + Cmd->UserDmaProgLength); + } +} + + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_0/src/xdmaps.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_0/src/xdmaps.h new file mode 100644 index 000000000..02de2a5ec --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_0/src/xdmaps.h @@ -0,0 +1,325 @@ +/***************************************************************************** +* +* (c) Copyright 2009-2013 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +*****************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdmaps.h +* +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  	Date     Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	hbm    08/19/10 First Release
+* 1.01a nm     12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
+*		        the maximum number of channels.
+*		        Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
+*                       with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h.
+*			Added the tcl file to automatically generate the
+*			xparameters.h
+* 1.02a sg     05/16/12 Made changes for doxygen and moved some function
+*			header from the xdmaps.h file to xdmaps.c file
+*			Other cleanup for coding guidelines and CR 657109
+*			and CR 657898
+*			The xdmaps_example_no_intr.c example is removed
+*			as it is using interrupts  and is similar to
+*			the interrupt example - CR 652477
+* 1.03a sg     07/16/2012 changed inline to __inline for CR665681
+* 1.04a nm     10/22/2012 Fixed CR# 681671.
+* 1.05a nm     04/15/2013 Fixed CR# 704396. Removed warnings when compiled
+*			  with -Wall and -Wextra option in bsp.
+*	       05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
+*			  function description.
+*			  Fixed CR# 704396. Removed unused variables
+*			  UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
+*			  function.
+* 1.07a asa    11/02/13. Made changes to fix compilation issues for iarcc.
+*			   Removed the PDBG prints. By default they were always
+*			   defined out and never used. The PDBG is non-standard for
+*			   Xilinx drivers and no other driver does something similar.
+*			   Since there is no easy way to fix compilation issues with
+*			   the IARCC compiler around PDBG, it is better to remove it.
+*			   Users can always use xil_printfs if they want to debug.
+* 2.0   adk    10/12/13  Updated as per the New Tcl API's
+*
+* +*****************************************************************************/ + +#ifndef XDMAPS_H /* prevent circular inclusions */ +#define XDMAPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xparameters.h" +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" + +#include "xdmaps_hw.h" + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Base address of device (IPIF) */ +} XDmaPs_Config; + + +/** DMA channle control structure. It's for AXI bus transaction. + * This struct will be translated into a 32-bit channel control register value. + */ +typedef struct { + unsigned int EndianSwapSize; /**< Endian swap size. */ + unsigned int DstCacheCtrl; /**< Destination cache control */ + unsigned int DstProtCtrl; /**< Destination protection control */ + unsigned int DstBurstLen; /**< Destination burst length */ + unsigned int DstBurstSize; /**< Destination burst size */ + unsigned int DstInc; /**< Destination incrementing or fixed + * address */ + unsigned int SrcCacheCtrl; /**< Source cache control */ + unsigned int SrcProtCtrl; /**< Source protection control */ + unsigned int SrcBurstLen; /**< Source burst length */ + unsigned int SrcBurstSize; /**< Source burst size */ + unsigned int SrcInc; /**< Source incrementing or fixed + * address */ +} XDmaPs_ChanCtrl; + +/** DMA block descriptor stucture. + */ +typedef struct { + u32 SrcAddr; /**< Source starting address */ + u32 DstAddr; /**< Destination starting address */ + unsigned int Length; /**< Number of bytes for the block */ +} XDmaPs_BD; + +/** + * A DMA command consisits of a channel control struct, a block descriptor, + * a user defined program, a pointer pointing to generated DMA program, and + * execution result. + * + */ +typedef struct { + XDmaPs_ChanCtrl ChanCtrl; /**< Channel Control Struct */ + XDmaPs_BD BD; /**< Together with SgLength field, + * it's a scatter-gather list. + */ + void *UserDmaProg; /**< If user wants the driver to + * execute their own DMA program, + * this field points to the DMA + * program. + */ + int UserDmaProgLength; /**< The length of user defined + * DMA program. + */ + + void *GeneratedDmaProg; /**< The DMA program genreated + * by the driver. This field will be + * set if a user invokes the DMA + * program generation function. Or + * the DMA command is finished and + * a user informs the driver not to + * release the program buffer. + * This field has two purposes, one + * is to ask the driver to generate + * a DMA program while the DMAC is + * performaning DMA transactions. The + * other purpose is to debug the + * driver. + */ + int GeneratedDmaProgLength; /**< The length of the DMA program + * generated by the driver + */ + int DmaStatus; /**< 0 on success, otherwise error code + */ + u32 ChanFaultType; /**< Channel fault type in case of fault + */ + u32 ChanFaultPCAddr; /**< Channel fault PC address + */ +} XDmaPs_Cmd; + +/** + * It's the done handler a user can set for a channel + */ +typedef void (*XDmaPsDoneHandler) (unsigned int Channel, + XDmaPs_Cmd *DmaCmd, + void *CallbackRef); + +/** + * It's the fault handler a user can set for a channel + */ +typedef void (*XDmaPsFaultHandler) (unsigned int Channel, + XDmaPs_Cmd *DmaCmd, + void *CallbackRef); + +#define XDMAPS_MAX_CHAN_BUFS 2 +#define XDMAPS_CHAN_BUF_LEN 128 + +/** + * The XDmaPs_ProgBuf is the struct for a DMA program buffer. + */ +typedef struct { + char Buf[XDMAPS_CHAN_BUF_LEN]; /**< The actual buffer the holds the + * content */ + unsigned Len; /**< The actual length of the DMA + * program in bytes. */ + int Allocated; /**< A tag indicating whether the + * buffer is allocated or not */ +} XDmaPs_ProgBuf; + +/** + * The XDmaPs_ChannelData is a struct to book keep individual channel of + * the DMAC. + */ +typedef struct { + unsigned DevId; /**< Device id indicating which DMAC */ + unsigned ChanId; /**< Channel number of the DMAC */ + XDmaPs_ProgBuf ProgBufPool[XDMAPS_MAX_CHAN_BUFS]; /**< A pool of + program buffers*/ + XDmaPsDoneHandler DoneHandler; /**< Done interrupt handler */ + void *DoneRef; /**< Done interrupt callback data */ + XDmaPs_Cmd *DmaCmdToHw; /**< DMA command being executed */ + XDmaPs_Cmd *DmaCmdFromHw; /**< DMA command that is finished. + * This field is for debugging purpose + */ + int HoldDmaProg; /**< A tag indicating whether to hold the + * DMA program after the DMA is done. + */ + +} XDmaPs_ChannelData; + +/** + * The XDmaPs driver instance data structure. A pointer to an instance data + * structure is passed around by functions to refer to a specific driver + * instance. + */ +typedef struct { + XDmaPs_Config Config; /**< Configuration data structure */ + int IsReady; /**< Device is Ready */ + int CacheLength; /**< icache length */ + XDmaPsFaultHandler FaultHandler; /**< fault interrupt handler */ + void *FaultRef; /**< fault call back data */ + XDmaPs_ChannelData Chans[XDMAPS_CHANNELS_PER_DEV]; + /**< + * channel data + */ +} XDmaPs; + +/* + * Functions implemented in xdmaps.c + */ +int XDmaPs_CfgInitialize(XDmaPs *InstPtr, + XDmaPs_Config *Config, + u32 EffectiveAddr); + +int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel, + XDmaPs_Cmd *Cmd, + int HoldDmaProg); + +int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel); +int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel, + XDmaPs_Cmd *Cmd); +int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel, + XDmaPs_Cmd *Cmd); +void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd); + + +int XDmaPs_ResetManager(XDmaPs *InstPtr); +int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel); + + +int XDmaPs_SetDoneHandler(XDmaPs *InstPtr, + unsigned Channel, + XDmaPsDoneHandler DoneHandler, + void *CallbackRef); + +int XDmaPs_SetFaultHandler(XDmaPs *InstPtr, + XDmaPsFaultHandler FaultHandler, + void *CallbackRef); + +void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd); + +/** + * Driver done interrupt service routines for the channels. + * We need this done ISR mainly because the driver needs to release the + * DMA program buffer. This is the one that connects the GIC + */ +void XDmaPs_DoneISR_0(XDmaPs *InstPtr); +void XDmaPs_DoneISR_1(XDmaPs *InstPtr); +void XDmaPs_DoneISR_2(XDmaPs *InstPtr); +void XDmaPs_DoneISR_3(XDmaPs *InstPtr); +void XDmaPs_DoneISR_4(XDmaPs *InstPtr); +void XDmaPs_DoneISR_5(XDmaPs *InstPtr); +void XDmaPs_DoneISR_6(XDmaPs *InstPtr); +void XDmaPs_DoneISR_7(XDmaPs *InstPtr); + +/** + * Driver fault interrupt service routine + */ +void XDmaPs_FaultISR(XDmaPs *InstPtr); + + +/* + * Static loopup function implemented in xdmaps_sinit.c + */ +XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId); + + +/* + * self-test functions in xdmaps_selftest.c + */ +int XDmaPs_SelfTest(XDmaPs *InstPtr); + + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_0/src/xdmaps_g.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_0/src/xdmaps_g.c new file mode 100644 index 000000000..79eabf157 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_0/src/xdmaps_g.c @@ -0,0 +1,35 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSM. +* Version: +* DO NOT EDIT. +* +* v (64-bit) +SW Build (by ) on +Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xdmaps.h" + +/* +* The configuration table for devices +*/ + +XDmaPs_Config XDmaPs_ConfigTable[] = +{ + { + XPAR_PS7_DMA_NS_DEVICE_ID, + XPAR_PS7_DMA_NS_BASEADDR + }, + { + XPAR_PS7_DMA_S_DEVICE_ID, + XPAR_PS7_DMA_S_BASEADDR + } +}; + + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_0/src/xdmaps_hw.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_0/src/xdmaps_hw.c new file mode 100644 index 000000000..98fbabd8c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_0/src/xdmaps_hw.c @@ -0,0 +1,122 @@ +/***************************************************************************** +* +* (c) Copyright 2009-2013 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +*****************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdmaps_hw.c +* +* This file contains the implementation of the interface reset functionality +* for XDmaPs driver. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  	Date     Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.06a kpc 10/07/13 First release
+*
+* +*****************************************************************************/ + +/***************************** Include Files ********************************/ +#include "xdmaps_hw.h" + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ +#ifndef XDMAPS_MAX_WAIT +#define XDMAPS_MAX_WAIT 4000 +#endif +/************************** Function Prototypes *****************************/ + +/************************** Variable Definitions ****************************/ + +/*****************************************************************************/ +/** +* This function perform the reset sequence to the given dmaps interface by +* configuring the appropriate control bits in the dmaps specifc registers +* the dmaps reset squence involves the following steps +* Disable all the interuupts +* Clear the pending interrupts +* Kill all the active channel threads +* Kill the manager thread +* +* @param BaseAddress of the interface +* +* @return N/A +* +* @note +* This function will not modify the slcr registers that are relavant for +* dmaps controller +******************************************************************************/ +void XDmaPs_ResetHw(u32 BaseAddress) +{ + u32 DbgInst; + u32 WaitCount = 0; + u32 ChanIndex; + + /* Disable all the interrupts */ + XDmaPs_WriteReg(BaseAddress, XDMAPS_INTEN_OFFSET, 0x00); + /* Clear the interrupts */ + XDmaPs_WriteReg(BaseAddress, XDMAPS_INTCLR_OFFSET, XDMAPS_INTCLR_ALL_MASK); + /* Kill the dma channel threads */ + for (ChanIndex=0; ChanIndex < XDMAPS_CHANNELS_PER_DEV; ChanIndex++) { + while ((XDmaPs_ReadReg(BaseAddress, XDMAPS_DBGSTATUS_OFFSET) + & XDMAPS_DBGSTATUS_BUSY) + && (WaitCount < XDMAPS_MAX_WAIT)) + WaitCount++; + + DbgInst = XDmaPs_DBGINST0(0, 0x01, ChanIndex, 1); + XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST0_OFFSET, DbgInst); + XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0); + XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0); + } + /* Kill the manager thread */ + DbgInst = XDmaPs_DBGINST0(0, 0x01, 0, 0); + XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST0_OFFSET, DbgInst); + XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0); + XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0); +} + + + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_0/src/xdmaps_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_0/src/xdmaps_hw.h new file mode 100644 index 000000000..1fc33e547 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_0/src/xdmaps_hw.h @@ -0,0 +1,299 @@ +/****************************************************************************** +* +* (c) Copyright 2009-2013 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xdmaps_hw.h +* +* This header file contains the hardware interface of an XDmaPs device. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who   Date     Changes
+* ----- ----  -------- ----------------------------------------------
+* 1.00a	hbm   08/18/10 First Release
+* 1.01a nm    12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
+*		       the maximum number of channels.
+*		       Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
+*                      with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h
+* 1.02a sg    05/16/12 Made changes for doxygen
+* 1.06a kpc   07/10/13 Added function prototype
+*
+* +******************************************************************************/ + +#ifndef XDMAPS_HW_H /* prevent circular inclusions */ +#define XDMAPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * + * Register offsets for the DMAC. + * @{ + */ + +#define XDMAPS_DS_OFFSET 0x000 /* DMA Status Register */ +#define XDMAPS_DPC_OFFSET 0x004 /* DMA Program Counter Rregister */ +#define XDMAPS_INTEN_OFFSET 0X020 /* DMA Interrupt Enable Register */ +#define XDMAPS_ES_OFFSET 0x024 /* DMA Event Status Register */ +#define XDMAPS_INTSTATUS_OFFSET 0x028 /* DMA Interrupt Status Register + */ +#define XDMAPS_INTCLR_OFFSET 0x02c /* DMA Interrupt Clear Register */ +#define XDMAPS_FSM_OFFSET 0x030 /* DMA Fault Status DMA Manager + * Register + */ +#define XDMAPS_FSC_OFFSET 0x034 /* DMA Fault Status DMA Chanel Register + */ +#define XDMAPS_FTM_OFFSET 0x038 /* DMA Fault Type DMA Manager Register */ + +#define XDMAPS_FTC0_OFFSET 0x040 /* DMA Fault Type for DMA Channel 0 */ +/* + * The offset for the rest of the FTC registers is calculated as + * FTC0 + dev_chan_num * 4 + */ +#define XDmaPs_FTCn_OFFSET(ch) (XDMAPS_FTC0_OFFSET + (ch) * 4) + +#define XDMAPS_CS0_OFFSET 0x100 /* Channel Status for DMA Channel 0 */ +/* + * The offset for the rest of the CS registers is calculated as + * CS0 + * dev_chan_num * 0x08 + */ +#define XDmaPs_CSn_OFFSET(ch) (XDMAPS_CS0_OFFSET + (ch) * 8) + +#define XDMAPS_CPC0_OFFSET 0x104 /* Channel Program Counter for DMA + * Channel 0 + */ +/* + * The offset for the rest of the CPC registers is calculated as + * CPC0 + dev_chan_num * 0x08 + */ +#define XDmaPs_CPCn_OFFSET(ch) (XDMAPS_CPC0_OFFSET + (ch) * 8) + +#define XDMAPS_SA_0_OFFSET 0x400 /* Source Address Register for DMA + * Channel 0 + */ +/* The offset for the rest of the SA registers is calculated as + * SA_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_SA_n_OFFSET(ch) (XDMAPS_SA_0_OFFSET + (ch) * 0x20) + +#define XDMAPS_DA_0_OFFSET 0x404 /* Destination Address Register for + * DMA Channel 0 + */ +/* The offset for the rest of the DA registers is calculated as + * DA_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_DA_n_OFFSET(ch) (XDMAPS_DA_0_OFFSET + (ch) * 0x20) + +#define XDMAPS_CC_0_OFFSET 0x408 /* Channel Control Register for + * DMA Channel 0 + */ +/* + * The offset for the rest of the CC registers is calculated as + * CC_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_CC_n_OFFSET(ch) (XDMAPS_CC_0_OFFSET + (ch) * 0x20) + +#define XDMAPS_LC0_0_OFFSET 0x40C /* Loop Counter 0 for DMA Channel 0 */ +/* + * The offset for the rest of the LC0 registers is calculated as + * LC_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_LC0_n_OFFSET(ch) (XDMAPS_LC0_0_OFFSET + (ch) * 0x20) +#define XDMAPS_LC1_0_OFFSET 0x410 /* Loop Counter 1 for DMA Channel 0 */ +/* + * The offset for the rest of the LC1 registers is calculated as + * LC_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_LC1_n_OFFSET(ch) (XDMAPS_LC1_0_OFFSET + (ch) * 0x20) + +#define XDMAPS_DBGSTATUS_OFFSET 0xD00 /* Debug Status Register */ +#define XDMAPS_DBGCMD_OFFSET 0xD04 /* Debug Command Register */ +#define XDMAPS_DBGINST0_OFFSET 0xD08 /* Debug Instruction 0 Register */ +#define XDMAPS_DBGINST1_OFFSET 0xD0C /* Debug Instruction 1 Register */ + +#define XDMAPS_CR0_OFFSET 0xE00 /* Configuration Register 0 */ +#define XDMAPS_CR1_OFFSET 0xE04 /* Configuration Register 1 */ +#define XDMAPS_CR2_OFFSET 0xE08 /* Configuration Register 2 */ +#define XDMAPS_CR3_OFFSET 0xE0C /* Configuration Register 3 */ +#define XDMAPS_CR4_OFFSET 0xE10 /* Configuration Register 4 */ +#define XDMAPS_CRDN_OFFSET 0xE14 /* Configuration Register Dn */ + +#define XDMAPS_PERIPH_ID_0_OFFSET 0xFE0 /* Peripheral Identification + * Register 0 + */ +#define XDMAPS_PERIPH_ID_1_OFFSET 0xFE4 /* Peripheral Identification + * Register 1 + */ +#define XDMAPS_PERIPH_ID_2_OFFSET 0xFE8 /* Peripheral Identification + * Register 2 + */ +#define XDMAPS_PERIPH_ID_3_OFFSET 0xFEC /* Peripheral Identification + * Register 3 + */ +#define XDMAPS_PCELL_ID_0_OFFSET 0xFF0 /* PrimeCell Identification + * Register 0 + */ +#define XDMAPS_PCELL_ID_1_OFFSET 0xFF4 /* PrimeCell Identification + * Register 1 + */ +#define XDMAPS_PCELL_ID_2_OFFSET 0xFF8 /* PrimeCell Identification + * Register 2 + */ +#define XDMAPS_PCELL_ID_3_OFFSET 0xFFC /* PrimeCell Identification + * Register 3 + */ + +/* + * Some useful register masks + */ +#define XDMAPS_DS_DMA_STATUS 0x0F /* DMA status mask */ +#define XDMAPS_DS_DMA_STATUS_STOPPED 0x00 /* debug status busy mask */ + +#define XDMAPS_DBGSTATUS_BUSY 0x01 /* debug status busy mask */ + +#define XDMAPS_CS_ACTIVE_MASK 0x07 /* channel status active mask, + * llast 3 bits of CS register + */ + +#define XDMAPS_CR1_I_CACHE_LEN_MASK 0x07 /* i_cache_len mask */ + + +/* + * XDMAPS_DBGINST0 - constructs the word for the Debug Instruction-0 Register. + * @b1: Instruction byte 1 + * @b0: Instruction byte 0 + * @ch: Channel number + * @dbg_th: Debug thread encoding: 0 = DMA manager thread, 1 = DMA channel + */ +#define XDmaPs_DBGINST0(b1, b0, ch, dbg_th) \ + (((b1) << 24) | ((b0) << 16) | (((ch) & 0x7) << 8) | ((dbg_th & 0x1))) + +/* @} */ + +/** @name Control Register + * + * The Control register (CR) controls the major functions of the device. + * + * Control Register Bit Definition + */ + +/* @}*/ + + +#define XDMAPS_CHANNELS_PER_DEV 8 + + +/** @name Mode Register + * + * The mode register (MR) defines the mode of transfer as well as the data + * format. If this register is modified during transmission or reception, + * data validity cannot be guaranteed. + * + * Mode Register Bit Definition + * @{ + */ + +/* @} */ + + +/** @name Interrupt Registers + * + * Interrupt control logic uses the interrupt enable register (IER) and the + * interrupt disable register (IDR) to set the value of the bits in the + * interrupt mask register (IMR). The IMR determines whether to pass an + * interrupt to the interrupt status register (ISR). + * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an + * interrupt. IMR and ISR are read only, and IER and IDR are write only. + * Reading either IER or IDR returns 0x00. + * + * All four registers have the same bit definitions. + * + * @{ + */ + +/* @} */ +#define XDMAPS_INTCLR_ALL_MASK 0xFF + +#define XDmaPs_ReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (RegOffset)) + +/***************************************************************************/ +/** +* Write a DMAC register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the base address of the device. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note +* C-Style signature: +* void XDmaPs_WriteReg(u32 BaseAddress, int RegOffset, +* u32 RegisterValue) +******************************************************************************/ +#define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ + Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue)) +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes *****************************/ +/* + * Perform reset operation to the dmaps interface + */ +void XDmaPs_ResetHw(u32 BaseAddr); +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_0/src/xdmaps_selftest.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_0/src/xdmaps_selftest.c new file mode 100644 index 000000000..cafbd7dfb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_0/src/xdmaps_selftest.c @@ -0,0 +1,116 @@ +/***************************************************************************** +* +* (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +*****************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdmaps_selftest.c +* +* This file contains the self-test functions for the XDmaPs driver. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00	hbm 	03/29/2010 First Release
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xdmaps.h" + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Variable Definitions *****************************/ + + +/************************** Function Prototypes ******************************/ + + +/****************************************************************************/ +/** +* +* This function runs a self-test on the driver and hardware device. This self +* test performs a local loopback and verifies data can be sent and received. +* +* The time for this test is proportional to the baud rate that has been set +* prior to calling this function. +* +* The mode and control registers are restored before return. +* +* @param InstPtr is a pointer to the XDmaPs instance +* +* @return +* +* - XST_SUCCESS if the test was successful +* - XST_FAILURE if the test failed +* +* @note +* +* This function can hang if the hardware is not functioning properly. +* +******************************************************************************/ +int XDmaPs_SelfTest(XDmaPs *InstPtr) +{ + u32 BaseAddr = InstPtr->Config.BaseAddress; + int i; + + if (XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET) + & XDMAPS_DBGSTATUS_BUSY) + return XST_FAILURE; + + for (i = 0; i < XDMAPS_CHANNELS_PER_DEV; i++) { + if (XDmaPs_ReadReg(BaseAddr, + XDmaPs_CSn_OFFSET(i))) + return XST_FAILURE; + } + return XST_SUCCESS; +} diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_0/src/xdmaps_sinit.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_0/src/xdmaps_sinit.c new file mode 100644 index 000000000..447624e36 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_0/src/xdmaps_sinit.c @@ -0,0 +1,110 @@ +/***************************************************************************** +* +* (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +*****************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdmaps_sinit.c +* +* The implementation of the XDmaPs driver's static initialzation +* functionality. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00  hbm  08/13/10 First Release
+*
+* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xstatus.h" +#include "xparameters.h" +#include "xdmaps.h" + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + + +/***************** Macros (Inline Functions) Definitions ********************/ + + +/************************** Variable Definitions ****************************/ +extern XDmaPs_Config XDmaPs_ConfigTable[]; + +/************************** Function Prototypes *****************************/ + +/****************************************************************************/ +/** +* +* Looks up the device configuration based on the unique device ID. The table +* contains the configuration info for each device in the system. +* +* @param DeviceId contains the ID of the device +* +* @return +* +* A pointer to the configuration structure or NULL if the specified device +* is not in the system. +* +* @note +* +* None. +* +******************************************************************************/ +XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId) +{ + XDmaPs_Config *CfgPtr = NULL; + + int i; + + for (i = 0; i < XPAR_XDMAPS_NUM_INSTANCES; i++) { + if (XDmaPs_ConfigTable[i].DeviceId == DeviceId) { + CfgPtr = &XDmaPs_ConfigTable[i]; + break; + } + } + + return CfgPtr; +} diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/Makefile new file mode 100644 index 000000000..ba187001d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/Makefile @@ -0,0 +1,41 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES:=*.c +INCLUDEFILES:=*.h + +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) + +libs: banner xemacps_libs clean + +%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling emacps" + +xemacps_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} + +.PHONY: include +include: xemacps_includes + +xemacps_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS} + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps.c new file mode 100644 index 000000000..8064f7aef --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps.c @@ -0,0 +1,401 @@ +/* $Id: xemacps.c,v 1.1.2.3 2011/05/17 12:00:33 anirudh Exp $ */ +/****************************************************************************** +* +* (c) Copyright 2010 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xemacps.c +* +* The XEmacPs driver. Functions in this file are the minimum required functions +* for this driver. See xemacps.h for a detailed description of the driver. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release
+*
+******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xemacps.h" + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +void XEmacPs_StubHandler(void); /* Default handler routine */ + +/************************** Variable Definitions *****************************/ + + +/*****************************************************************************/ +/** +* Initialize a specific XEmacPs instance/driver. The initialization entails: +* - Initialize fields of the XEmacPs instance structure +* - Reset hardware and apply default options +* - Configure the DMA channels +* +* The PHY is setup independently from the device. Use the MII or whatever other +* interface may be present for setup. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param CfgPtr is the device configuration structure containing required +* hardware build data. +* @param EffectiveAddress is the base address of the device. If address +* translation is not utilized, this parameter can be passed in using +* CfgPtr->Config.BaseAddress to specify the physical base address. +* +* @return +* - XST_SUCCESS if initialization was successful +* +******************************************************************************/ +int XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr, + u32 EffectiveAddress) +{ + /* Verify arguments */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(CfgPtr != NULL); + + /* Set device base address and ID */ + InstancePtr->Config.DeviceId = CfgPtr->DeviceId; + InstancePtr->Config.BaseAddress = EffectiveAddress; + + /* Set callbacks to an initial stub routine */ + InstancePtr->SendHandler = (XEmacPs_Handler) XEmacPs_StubHandler; + InstancePtr->RecvHandler = (XEmacPs_Handler) XEmacPs_StubHandler; + InstancePtr->ErrorHandler = (XEmacPs_ErrHandler) XEmacPs_StubHandler; + + /* Reset the hardware and set default options */ + InstancePtr->IsReady = XIL_COMPONENT_IS_READY; + XEmacPs_Reset(InstancePtr); + + return (XST_SUCCESS); +} + + +/*****************************************************************************/ +/** +* Start the Ethernet controller as follows: +* - Enable transmitter if XTE_TRANSMIT_ENABLE_OPTION is set +* - Enable receiver if XTE_RECEIVER_ENABLE_OPTION is set +* - Start the SG DMA send and receive channels and enable the device +* interrupt +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return N/A +* +* @note +* Hardware is configured with scatter-gather DMA, the driver expects to start +* the scatter-gather channels and expects that the user has previously set up +* the buffer descriptor lists. +* +* This function makes use of internal resources that are shared between the +* Start, Stop, and Set/ClearOptions functions. So if one task might be setting +* device options while another is trying to start the device, the user is +* required to provide protection of this shared data (typically using a +* semaphore). +* +* This function must not be preempted by an interrupt that may service the +* device. +* +******************************************************************************/ +void XEmacPs_Start(XEmacPs *InstancePtr) +{ + u32 Reg; + + /* Assert bad arguments and conditions */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(InstancePtr->RxBdRing.BaseBdAddr != 0); + Xil_AssertVoid(InstancePtr->TxBdRing.BaseBdAddr != 0); + + /* If already started, then there is nothing to do */ + if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) { + return; + } + + /* Start DMA */ + /* When starting the DMA channels, both transmit and receive sides + * need an initialized BD list. + */ + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_RXQBASE_OFFSET, + InstancePtr->RxBdRing.BaseBdAddr); + + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_TXQBASE_OFFSET, + InstancePtr->TxBdRing.BaseBdAddr); + + /* clear any existed int status */ + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET, + XEMACPS_IXR_ALL_MASK); + + /* Enable transmitter if not already enabled */ + if (InstancePtr->Options & XEMACPS_TRANSMITTER_ENABLE_OPTION) { + Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET); + if (!(Reg & XEMACPS_NWCTRL_TXEN_MASK)) { + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET, + Reg | XEMACPS_NWCTRL_TXEN_MASK); + } + } + + /* Enable receiver if not already enabled */ + if (InstancePtr->Options & XEMACPS_RECEIVER_ENABLE_OPTION) { + Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET); + if (!(Reg & XEMACPS_NWCTRL_RXEN_MASK)) { + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET, + Reg | XEMACPS_NWCTRL_RXEN_MASK); + } + } + + /* Enable TX and RX interrupts */ + XEmacPs_IntEnable(InstancePtr, (XEMACPS_IXR_TX_ERR_MASK | + XEMACPS_IXR_RX_ERR_MASK | XEMACPS_IXR_FRAMERX_MASK | + XEMACPS_IXR_TXCOMPL_MASK)); + + /* Mark as started */ + InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED; + + return; +} + + +/*****************************************************************************/ +/** +* Gracefully stop the Ethernet MAC as follows: +* - Disable all interrupts from this device +* - Stop DMA channels +* - Disable the tansmitter and receiver +* +* Device options currently in effect are not changed. +* +* This function will disable all interrupts. Default interrupts settings that +* had been enabled will be restored when XEmacPs_Start() is called. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @note +* This function makes use of internal resources that are shared between the +* Start, Stop, SetOptions, and ClearOptions functions. So if one task might be +* setting device options while another is trying to start the device, the user +* is required to provide protection of this shared data (typically using a +* semaphore). +* +* Stopping the DMA channels causes this function to block until the DMA +* operation is complete. +* +******************************************************************************/ +void XEmacPs_Stop(XEmacPs *InstancePtr) +{ + u32 Reg; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* Disable all interrupts */ + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET, + XEMACPS_IXR_ALL_MASK); + + /* Disable the receiver & transmitter */ + Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET); + Reg &= ~XEMACPS_NWCTRL_RXEN_MASK; + Reg &= ~XEMACPS_NWCTRL_TXEN_MASK; + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET, Reg); + + /* Mark as stopped */ + InstancePtr->IsStarted = 0; +} + + +/*****************************************************************************/ +/** +* Perform a graceful reset of the Ethernet MAC. Resets the DMA channels, the +* transmitter, and the receiver. +* +* Steps to reset +* - Stops transmit and receive channels +* - Stops DMA +* - Configure transmit and receive buffer size to default +* - Clear transmit and receive status register and counters +* - Clear all interrupt sources +* - Clear phy (if there is any previously detected) address +* - Clear MAC addresses (1-4) as well as Type IDs and hash value +* +* All options are placed in their default state. Any frames in the +* descriptor lists will remain in the lists. The side effect of doing +* this is that after a reset and following a restart of the device, frames +* were in the list before the reset may be transmitted or received. +* +* The upper layer software is responsible for re-configuring (if necessary) +* and restarting the MAC after the reset. Note also that driver statistics +* are not cleared on reset. It is up to the upper layer software to clear the +* statistics if needed. +* +* When a reset is required, the driver notifies the upper layer software of +* this need through the ErrorHandler callback and specific status codes. +* The upper layer software is responsible for calling this Reset function +* and then re-configuring the device. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +******************************************************************************/ +void XEmacPs_Reset(XEmacPs *InstancePtr) +{ + u32 Reg; + u8 i; + char EmacPs_zero_MAC[6] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* Stop the device and reset hardware */ + XEmacPs_Stop(InstancePtr); + InstancePtr->Options = XEMACPS_DEFAULT_OPTIONS; + + /* Setup hardware with default values */ + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET, + (XEMACPS_NWCTRL_STATCLR_MASK | + XEMACPS_NWCTRL_MDEN_MASK) & + ~XEMACPS_NWCTRL_LOOPEN_MASK); + + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCFG_OFFSET, + XEMACPS_NWCFG_100_MASK | + XEMACPS_NWCFG_FDEN_MASK | + XEMACPS_NWCFG_UCASTHASHEN_MASK); + + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_DMACR_OFFSET, + ((((XEMACPS_RX_BUF_SIZE / XEMACPS_RX_BUF_UNIT) + + ((XEMACPS_RX_BUF_SIZE % + XEMACPS_RX_BUF_UNIT) ? 1 : 0)) << + XEMACPS_DMACR_RXBUF_SHIFT) & + XEMACPS_DMACR_RXBUF_MASK) | + XEMACPS_DMACR_RXSIZE_MASK | + XEMACPS_DMACR_TXSIZE_MASK); + + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_TXSR_OFFSET, 0x0); + + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_RXQBASE_OFFSET, 0x0); + + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_TXQBASE_OFFSET, 0x0); + + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_RXSR_OFFSET, 0x0); + + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET, + XEMACPS_IXR_ALL_MASK); + + Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, + XEMACPS_ISR_OFFSET); + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET, + Reg); + + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_PHYMNTNC_OFFSET, 0x0); + + XEmacPs_ClearHash(InstancePtr); + + for (i = 1; i < 5; i++) { + XEmacPs_SetMacAddress(InstancePtr, EmacPs_zero_MAC, i); + XEmacPs_SetTypeIdCheck(InstancePtr, 0x0, i); + } + + /* clear all counters */ + for (i = 0; i < (XEMACPS_LAST_OFFSET - XEMACPS_OCTTXL_OFFSET) / 4; + i++) { + XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, + XEMACPS_OCTTXL_OFFSET + i * 4); + } + + /* Disable the receiver */ + Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET); + Reg &= ~XEMACPS_NWCTRL_RXEN_MASK; + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET, Reg); + + /* Sync default options with hardware but leave receiver and + * transmitter disabled. They get enabled with XEmacPs_Start() if + * XEMACPS_TRANSMITTER_ENABLE_OPTION and + * XEMACPS_RECEIVER_ENABLE_OPTION are set. + */ + XEmacPs_SetOptions(InstancePtr, InstancePtr->Options & + ~(XEMACPS_TRANSMITTER_ENABLE_OPTION | + XEMACPS_RECEIVER_ENABLE_OPTION)); + + XEmacPs_ClearOptions(InstancePtr, ~InstancePtr->Options); +} + + +/******************************************************************************/ +/** + * This is a stub for the asynchronous callbacks. The stub is here in case the + * upper layer forgot to set the handler(s). On initialization, all handlers are + * set to this callback. It is considered an error for this handler to be + * invoked. + * + ******************************************************************************/ +void XEmacPs_StubHandler(void) +{ + Xil_AssertVoidAlways(); +} diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps.h new file mode 100644 index 000000000..643ba2cf6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps.h @@ -0,0 +1,721 @@ +/***************************************************************************** +* +* (c) Copyright 2010-11 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +*****************************************************************************/ +/****************************************************************************/ +/** + * + * @file xemacps.h + * + * The Xilinx Embedded Processor Block Ethernet driver. + * + * For a full description of XEMACPS features, please see the hardware spec. + * This driver supports the following features: + * - Memory mapped access to host interface registers + * - Statistics counter registers for RMON/MIB + * - API for interrupt driven frame transfers for hardware configured DMA + * - Virtual memory support + * - Unicast, broadcast, and multicast receive address filtering + * - Full and half duplex operation + * - Automatic PAD & FCS insertion and stripping + * - Flow control + * - Support up to four 48bit addresses + * - Address checking for four specific 48bit addresses + * - VLAN frame support + * - Pause frame support + * - Large frame support up to 1536 bytes + * - Checksum offload + * + * Driver Description + * + * The device driver enables higher layer software (e.g., an application) to + * communicate to the XEmacPs. The driver handles transmission and reception + * of Ethernet frames, as well as configuration and control. No pre or post + * processing of frame data is performed. The driver does not validate the + * contents of an incoming frame in addition to what has already occurred in + * hardware. + * A single device driver can support multiple devices even when those devices + * have significantly different configurations. + * + * Initialization & Configuration + * + * The XEmacPs_Config structure is used by the driver to configure itself. + * This configuration structure is typically created by the tool-chain based + * on hardware build properties. + * + * The driver instance can be initialized in + * + * - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a + * configuration structure provided by the caller. If running in a system + * with address translation, the provided virtual memory base address + * replaces the physical address present in the configuration structure. + * + * The device supports DMA only as current development plan. No FIFO mode is + * supported. The driver expects to start the DMA channels and expects that + * the user has set up the buffer descriptor lists. + * + * Interrupts and Asynchronous Callbacks + * + * The driver has no dependencies on the interrupt controller. When an + * interrupt occurs, the handler will perform a small amount of + * housekeeping work, determine the source of the interrupt, and call the + * appropriate callback function. All callbacks are registered by the user + * level application. + * + * Virtual Memory + * + * All virtual to physical memory mappings must occur prior to accessing the + * driver API. + * + * For DMA transactions, user buffers supplied to the driver must be in terms + * of their physical address. + * + * DMA + * + * The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames. + * These BDs are typically chained together into a list the hardware follows + * when transferring data in and out of the packet buffers. Each BD describes + * a memory region containing either a full or partial Ethernet packet. + * + * Interrupt coalescing is not suppoted from this built-in DMA engine. + * + * This API requires the user to understand how the DMA operates. The + * following paragraphs provide some explanation, but the user is encouraged + * to read documentation in xemacps_bdring.h as well as study example code + * that accompanies this driver. + * + * The API is designed to get BDs to and from the DMA engine in the most + * efficient means possible. The first step is to establish a memory region + * to contain all BDs for a specific channel. This is done with + * XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will + * follow as BDs are processed. The ring will consist of a user defined number + * of BDs which will all be partially initialized. For example on the transmit + * channel, the driver will initialize all BDs' so that they are configured + * for transmit. The more fields that can be permanently setup at + * initialization, then the fewer accesses will be needed to each BD while + * the DMA engine is in operation resulting in better throughput and CPU + * utilization. The best case initialization would require the user to set + * only a frame buffer address and length prior to submitting the BD to the + * engine. + * + * BDs move through the engine with the help of functions + * XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(), + * and XEmacPs_BdRingFree(). + * All these functions handle BDs that are in place. That is, there are no + * copies of BDs kept anywhere and any BD the user interacts with is an actual + * BD from the same ring hardware accesses. + * + * BDs in the ring go through a series of states as follows: + * 1. Idle. The driver controls BDs in this state. + * 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to + * reserve BD(s). Once allocated, the user may setup the BD(s) with + * frame buffer address, length, and other attributes. The user controls + * BDs in this state. + * 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs + * in this state are either waiting to be processed by hardware, are in + * process, or have been processed. The DMA engine controls BDs in this + * state. + * 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the + * user. Once retrieved, the user can examine each BD for the outcome of + * the DMA transfer. The user controls BDs in this state. After examining + * the BDs the user calls XEmacPs_BdRingFree() which places the BDs back + * into state 1. + * + * Each of the four BD accessor functions operate on a set of BDs. A set is + * defined as a segment of the BD ring consisting of one or more BDs. The user + * views the set as a pointer to the first BD along with the number of BDs for + * that set. The set can be navigated by using macros XEmacPs_BdNext(). The + * user must exercise extreme caution when changing BDs in a set as there is + * nothing to prevent doing a mBdNext past the end of the set and modifying a + * BD out of bounds. + * + * XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as + * XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in + * tandem. The same BD set retrieved with BdRingAlloc should be the same one + * provided to hardware with BdRingToHw. Same goes with BdRingFromHw and + * BdRIngFree. + * + * Alignment & Data Cache Restrictions + * + * Due to the design of the hardware, all RX buffers, BDs need to be 4-byte + * aligned. Please reference xemacps_bd.h for cache related macros. + * + * DMA Tx: + * + * - If frame buffers exist in cached memory, then they must be flushed + * prior to committing them to hardware. + * + * DMA Rx: + * + * - If frame buffers exist in cached memory, then the cache must be + * invalidated for the memory region containing the frame prior to data + * access + * + * Both cache invalidate/flush are taken care of in driver code. + * + * Buffer Copying + * + * The driver is designed for a zero-copy buffer scheme. That is, the driver + * will not copy buffers. This avoids potential throughput bottlenecks within + * the driver. If byte copying is required, then the transfer will take longer + * to complete. + * + * Checksum Offloading + * + * The Embedded Processor Block Ethernet can be configured to perform IP, TCP + * and UDP checksum offloading in both receive and transmit directions. + * + * IP packets contain a 16-bit checksum field, which is the 16-bit 1s + * complement of the 1s complement sum of all 16-bit words in the header. + * TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit + * 1s complement of the 1s complement sum of all 16-bit words in the header, + * the data and a conceptual pseudo header. + * + * To calculate these checksums in software requires each byte of the packet + * to be read. For TCP and UDP this can use a large amount of processing power. + * Offloading the checksum calculation to hardware can result in significant + * performance improvements. + * + * The transmit checksum offload is only available to use DMA in packet buffer + * mode. This is because the complete frame to be transmitted must be read + * into the packet buffer memory before the checksum can be calculated and + * written to the header at the beginning of the frame. + * + * For IP, TCP or UDP receive checksum offload to be useful, the operating + * system containing the protocol stack must be aware that this offload is + * available so that it can make use of the fact that the hardware has verified + * the checksum. + * + * When receive checksum offloading is enabled in the hardware, the IP header + * checksum is checked, where the packet meets the following criteria: + * + * 1. If present, the VLAN header must be four octets long and the CFI bit + * must not be set. + * 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP + * encoding. + * 3. IP v4 packet. + * 4. IP header is of a valid length. + * 5. Good IP header checksum. + * 6. No IP fragmentation. + * 7. TCP or UDP packet. + * + * When an IP, TCP or UDP frame is received, the receive buffer descriptor + * gives an indication if the hardware was able to verify the checksums. + * There is also an indication if the frame had SNAP encapsulation. These + * indication bits will replace the type ID match indication bits when the + * receive checksum offload is enabled. + * + * If any of the checksums are verified incorrect by the hardware, the packet + * is discarded and the appropriate statistics counter incremented. + * + * PHY Interfaces + * + * RGMII 1.3 is the only interface supported. + * + * Asserts + * + * Asserts are used within all Xilinx drivers to enforce constraints on + * parameters. Asserts can be turned off on a system-wide basis by defining, + * at compile time, the NDEBUG identifier. By default, asserts are turned on + * and it is recommended that users leave asserts on during development. For + * deployment use -DNDEBUG compiler switch to remove assert code. + * + * @note + * + * Xilinx drivers are typically composed of two parts, one is the driver + * and the other is the adapter. The driver is independent of OS and processor + * and is intended to be highly portable. The adapter is OS-specific and + * facilitates communication between the driver and an OS. + * This driver is intended to be RTOS and processor independent. Any needs for + * dynamic memory management, threads or thread mutual exclusion, or cache + * control must be satisfied bythe layer above this driver. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy  01/10/10 First release
+ * 1.00a asa  11/21/11 The function XEmacPs_BdRingFromHwTx in file
+ *		       xemacps_bdring.c is modified. Earlier it was checking for
+ *		       "BdLimit"(passed argument) number of BDs for finding out
+ *		       which BDs are successfully processed. Now one more check
+ *		       is added. It looks for BDs till the current BD pointer
+ *		       reaches HwTail. By doing this processing time is saved.
+ * 1.00a asa  01/24/12 The function XEmacPs_BdRingFromHwTx in file
+ *		       xemacps_bdring.c is modified. Now start of packet is
+ *		       searched for returning the number of BDs processed.
+ * 1.02a asa  11/05/12 Added a new API for deleting an entry from the HASH
+ *		       registers. Added a new API to set the bust length.
+ *		       Added some new hash-defines.
+ * 1.03a asa  01/23/12 Fix for CR #692702 which updates error handling for
+ *		       Rx errors. Under heavy Rx traffic, there will be a large
+ *		       number of errors related to receive buffer not available.
+ *		       Because of a HW bug (SI #692601), under such heavy errors,
+ *		       the Rx data path can become unresponsive. To reduce the
+ *		       probabilities for hitting this HW bug, the SW writes to
+ *		       bit 18 to flush a packet from Rx DPRAM immediately. The
+ *		       changes for it are done in the function
+ *		       XEmacPs_IntrHandler.
+ * 1.05a asa  09/23/13 Cache operations on BDs are not required and hence
+ *		       removed. It is expected that all BDs are allocated in
+ *		       from uncached area.
+ * 1.06a asa  11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+ *				to 0x1fff. This fixes the CR#744902.
+ *			  Made changes in example file xemacps_example.h to fix compilation
+ *			  issues with iarcc compiler.
+ * 2.0   adk  10/12/13 Updated as per the New Tcl API's
+ *
+ * + ****************************************************************************/ + +#ifndef XEMACPS_H /* prevent circular inclusions */ +#define XEMACPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xemacps_hw.h" +#include "xemacps_bd.h" +#include "xemacps_bdring.h" + +/************************** Constant Definitions ****************************/ + +/* + * Device information + */ +#define XEMACPS_DEVICE_NAME "xemacps" +#define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC" + + +/** @name Configuration options + * + * Device configuration options. See the XEmacPs_SetOptions(), + * XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to + * use options. + * + * The default state of the options are noted and are what the device and + * driver will be set to after calling XEmacPs_Reset() or + * XEmacPs_Initialize(). + * + * @{ + */ + +#define XEMACPS_PROMISC_OPTION 0x00000001 +/**< Accept all incoming packets. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_FRAME1536_OPTION 0x00000002 +/**< Frame larger than 1516 support for Tx & Rx. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_VLAN_OPTION 0x00000004 +/**< VLAN Rx & Tx frame support. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010 +/**< Enable recognition of flow control frames on Rx + * This option defaults to enabled (set) */ + +#define XEMACPS_FCS_STRIP_OPTION 0x00000020 +/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not + * stripped. + * This option defaults to enabled (set) */ + +#define XEMACPS_FCS_INSERT_OPTION 0x00000040 +/**< Generate FCS field and add PAD automatically for outgoing frames. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080 +/**< Enable Length/Type error checking for incoming frames. When this option is + * set, the MAC will filter frames that have a mismatched type/length field + * and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these + * types of frames are encountered. When this option is cleared, the MAC will + * allow these types of frames to be received. + * + * This option defaults to disabled (cleared) */ + +#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100 +/**< Enable the transmitter. + * This option defaults to enabled (set) */ + +#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200 +/**< Enable the receiver + * This option defaults to enabled (set) */ + +#define XEMACPS_BROADCAST_OPTION 0x00000400 +/**< Allow reception of the broadcast address + * This option defaults to enabled (set) */ + +#define XEMACPS_MULTICAST_OPTION 0x00000800 +/**< Allows reception of multicast addresses programmed into hash + * This option defaults to disabled (clear) */ + +#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000 +/**< Enable the RX checksum offload + * This option defaults to enabled (set) */ + +#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000 +/**< Enable the TX checksum offload + * This option defaults to enabled (set) */ + + +#define XEMACPS_DEFAULT_OPTIONS \ + (XEMACPS_FLOW_CONTROL_OPTION | \ + XEMACPS_FCS_INSERT_OPTION | \ + XEMACPS_FCS_STRIP_OPTION | \ + XEMACPS_BROADCAST_OPTION | \ + XEMACPS_LENTYPE_ERR_OPTION | \ + XEMACPS_TRANSMITTER_ENABLE_OPTION | \ + XEMACPS_RECEIVER_ENABLE_OPTION | \ + XEMACPS_RX_CHKSUM_ENABLE_OPTION | \ + XEMACPS_TX_CHKSUM_ENABLE_OPTION) + +/**< Default options set when device is initialized or reset */ +/*@}*/ + +/** @name Callback identifiers + * + * These constants are used as parameters to XEmacPs_SetHandler() + * @{ + */ +#define XEMACPS_HANDLER_DMASEND 1 +#define XEMACPS_HANDLER_DMARECV 2 +#define XEMACPS_HANDLER_ERROR 3 +/*@}*/ + +/* Constants to determine the configuration of the hardware device. They are + * used to allow the driver to verify it can operate with the hardware. + */ +#define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */ + +/* The next few constants help upper layers determine the size of memory + * pools used for Ethernet buffers and descriptor lists. + */ +#define XEMACPS_MAC_ADDR_SIZE 6 /* size of Ethernet header */ + +#define XEMACPS_MTU 1500 /* max MTU size of Ethernet frame */ +#define XEMACPS_HDR_SIZE 14 /* size of Ethernet header */ +#define XEMACPS_HDR_VLAN_SIZE 18 /* size of Ethernet header with VLAN */ +#define XEMACPS_TRL_SIZE 4 /* size of Ethernet trailer (FCS) */ +#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \ + XEMACPS_TRL_SIZE) +#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \ + XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE) + +/* DMACR Bust length hash defines */ + +#define XEMACPS_SINGLE_BURST 1 +#define XEMACPS_4BYTE_BURST 4 +#define XEMACPS_8BYTE_BURST 8 +#define XEMACPS_16BYTE_BURST 16 + + +/**************************** Type Definitions ******************************/ +/** @name Typedefs for callback functions + * + * These callbacks are invoked in interrupt context. + * @{ + */ +/** + * Callback invoked when frame(s) have been sent or received in interrupt + * driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler(). + * + * @param CallBackRef is user data assigned when the callback was set. + * + * @note + * See xemacps_hw.h for bitmasks definitions and the device hardware spec for + * further information on their meaning. + * + */ +typedef void (*XEmacPs_Handler) (void *CallBackRef); + +/** + * Callback when an asynchronous error occurs. To set this callback, invoke + * XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType + * paramter. + * + * @param CallBackRef is user data assigned when the callback was set. + * @param Direction defines either receive or transmit error(s) has occurred. + * @param ErrorWord definition varies with Direction + * + */ +typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction, + u32 ErrorWord); + +/*@}*/ + +/** + * This typedef contains configuration information for a device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress;/**< Physical base address of IPIF registers */ +} XEmacPs_Config; + + +/** + * The XEmacPs driver instance data. The user is required to allocate a + * structure of this type for every XEmacPs device in the system. A pointer + * to a structure of this type is then passed to the driver API functions. + */ +typedef struct XEmacPs { + XEmacPs_Config Config; /* Hardware configuration */ + u32 IsStarted; /* Device is currently started */ + u32 IsReady; /* Device is initialized and ready */ + u32 Options; /* Current options word */ + + XEmacPs_BdRing TxBdRing; /* Transmit BD ring */ + XEmacPs_BdRing RxBdRing; /* Receive BD ring */ + + XEmacPs_Handler SendHandler; + XEmacPs_Handler RecvHandler; + void *SendRef; + void *RecvRef; + + XEmacPs_ErrHandler ErrorHandler; + void *ErrorRef; + +} XEmacPs; + + +/***************** Macros (Inline Functions) Definitions ********************/ + +/****************************************************************************/ +/** +* Retrieve the Tx ring object. This object can be used in the various Ring +* API functions. +* +* @param InstancePtr is the DMA channel to operate on. +* +* @return TxBdRing attribute +* +* @note +* C-style signature: +* XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing) + +/****************************************************************************/ +/** +* Retrieve the Rx ring object. This object can be used in the various Ring +* API functions. +* +* @param InstancePtr is the DMA channel to operate on. +* +* @return RxBdRing attribute +* +* @note +* C-style signature: +* XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing) + +/****************************************************************************/ +/** +* +* Enable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to enable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntEnable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_IER_OFFSET, \ + (Mask & XEMACPS_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* Disable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to disable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntDisable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_IDR_OFFSET, \ + (Mask & XEMACPS_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* This macro triggers trasmit circuit to send data currently in TX buffer(s). +* +* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. +* +* @return +* +* @note +* +* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_Transmit(InstancePtr) \ + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, \ + XEMACPS_NWCTRL_OFFSET, \ + (XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, \ + XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK)) + +/****************************************************************************/ +/** +* +* This macro determines if the device is configured with checksum offloading +* on the receive channel +* +* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. +* +* @return +* +* Boolean TRUE if the device is configured with checksum offloading, or +* FALSE otherwise. +* +* @note +* +* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_IsRxCsum(InstancePtr) \ + ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) \ + ? TRUE : FALSE) + +/****************************************************************************/ +/** +* +* This macro determines if the device is configured with checksum offloading +* on the transmit channel +* +* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. +* +* @return +* +* Boolean TRUE if the device is configured with checksum offloading, or +* FALSE otherwise. +* +* @note +* +* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_IsTxCsum(InstancePtr) \ + ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) \ + ? TRUE : FALSE) + +/************************** Function Prototypes *****************************/ + +/* + * Initialization functions in xemacps.c + */ +int XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr, + u32 EffectiveAddress); +void XEmacPs_Start(XEmacPs *InstancePtr); +void XEmacPs_Stop(XEmacPs *InstancePtr); +void XEmacPs_Reset(XEmacPs *InstancePtr); + +/* + * Lookup configuration in xemacps_sinit.c + */ +XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId); + +/* + * Interrupt-related functions in xemacps_intr.c + * DMA only and FIFO is not supported. This DMA does not support coalescing. + */ +int XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType, + void *FuncPtr, void *CallBackRef); +void XEmacPs_IntrHandler(void *InstancePtr); + +/* + * MAC configuration/control functions in XEmacPs_control.c + */ +int XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options); +int XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options); +u32 XEmacPs_GetOptions(XEmacPs *InstancePtr); + +int XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index); +void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index); + +int XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr); +void XEmacPs_ClearHash(XEmacPs *InstancePtr); +void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr); + +void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, + XEmacPs_MdcDiv Divisor); +void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed); +u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr); +int XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress, + u32 RegisterNum, u16 *PhyDataPtr); +int XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress, + u32 RegisterNum, u16 PhyData); +int XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index); + +int XEmacPs_SendPausePacket(XEmacPs *InstancePtr); +void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, int BLength); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_bd.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_bd.h new file mode 100644 index 000000000..8bf33cfa5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_bd.h @@ -0,0 +1,737 @@ +/* $Id: xemacps_bd.h,v 1.1.2.1 2011/01/20 03:39:02 sadanan Exp $ */ +/****************************************************************************** +* +* (c) Copyright 2010 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** + * + * @file xemacps_bd.h + * + * This header provides operations to manage buffer descriptors in support + * of scatter-gather DMA. + * + * The API exported by this header defines abstracted macros that allow the + * user to read/write specific BD fields. + * + * Buffer Descriptors + * + * A buffer descriptor (BD) defines a DMA transaction. The macros defined by + * this header file allow access to most fields within a BD to tailor a DMA + * transaction according to user and hardware requirements. See the hardware + * IP DMA spec for more information on BD fields and how they affect transfers. + * + * The XEmacPs_Bd structure defines a BD. The organization of this structure + * is driven mainly by the hardware for use in scatter-gather DMA transfers. + * + * Performance + * + * Limiting I/O to BDs can improve overall performance of the DMA channel. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy  01/10/10 First release
+ *
+ * + * *************************************************************************** + */ + +#ifndef XEMACPS_BD_H /* prevent circular inclusions */ +#define XEMACPS_BD_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include +#include "xil_types.h" +#include "xil_assert.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/* Minimum BD alignment */ +#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4 + +/** + * The XEmacPs_Bd is the type for buffer descriptors (BDs). + */ +#define XEMACPS_BD_NUM_WORDS 2 +typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS]; + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** + * Zero out BD fields + * + * @param BdPtr is the BD pointer to operate on + * + * @return Nothing + * + * @note + * C-style signature: + * void XEmacPs_BdClear(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClear(BdPtr) \ + memset((BdPtr), 0, sizeof(XEmacPs_Bd)) + +/****************************************************************************/ +/** +* +* Read the given Buffer Descriptor word. +* +* @param BaseAddress is the base address of the BD to read +* @param Offset is the word offset to be read +* +* @return The 32-bit value of the field +* +* @note +* C-style signature: +* u32 XEmacPs_BdRead(u32 BaseAddress, u32 Offset) +* +*****************************************************************************/ +#define XEmacPs_BdRead(BaseAddress, Offset) \ + (*(u32*)((u32)(BaseAddress) + (u32)(Offset))) + +/****************************************************************************/ +/** +* +* Write the given Buffer Descriptor word. +* +* @param BaseAddress is the base address of the BD to write +* @param Offset is the word offset to be written +* @param Data is the 32-bit value to write to the field +* +* @return None. +* +* @note +* C-style signature: +* void XEmacPs_BdWrite(u32 BaseAddress, u32 Offset, u32 Data) +* +*****************************************************************************/ +#define XEmacPs_BdWrite(BaseAddress, Offset, Data) \ + (*(u32*)((u32)(BaseAddress) + (u32)(Offset)) = (Data)) + +/*****************************************************************************/ +/** + * Set the BD's Address field (word 0). + * + * @param BdPtr is the BD pointer to operate on + * @param Addr is the value to write to BD's status field. + * + * @note : + * + * C-style signature: + * void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, u32 Addr) + * + *****************************************************************************/ +#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr))) + + +/*****************************************************************************/ +/** + * Set the BD's Address field (word 0). + * + * @param BdPtr is the BD pointer to operate on + * @param Addr is the value to write to BD's status field. + * + * @note : Due to some bits are mixed within recevie BD's address field, + * read-modify-write is performed. + * + * C-style signature: + * void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, u32 Addr) + * + *****************************************************************************/ +#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + ~XEMACPS_RXBUF_ADD_MASK) | (u32)(Addr))) + + +/*****************************************************************************/ +/** + * Set the BD's Status field (word 1). + * + * @param BdPtr is the BD pointer to operate on + * @param Data is the value to write to BD's status field. + * + * @note + * C-style signature: + * void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, u32 Data) + * + *****************************************************************************/ +#define XEmacPs_BdSetStatus(BdPtr, Data) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | Data) + + +/*****************************************************************************/ +/** + * Retrieve the BD's Packet DMA transfer status word (word 1). + * + * @param BdPtr is the BD pointer to operate on + * + * @return Status word + * + * @note + * C-style signature: + * u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr) + * + * Due to the BD bit layout differences in transmit and receive. User's + * caution is required. + *****************************************************************************/ +#define XEmacPs_BdGetStatus(BdPtr) \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) + + +/*****************************************************************************/ +/** + * Get the address (bits 0..31) of the BD's buffer address (word 0) + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u32 XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdGetBufAddr(BdPtr) \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET)) + + +/*****************************************************************************/ +/** + * Set transfer length in bytes for the given BD. The length must be set each + * time a BD is submitted to hardware. + * + * @param BdPtr is the BD pointer to operate on + * @param LenBytes is the number of bytes to transfer. + * + * @note + * C-style signature: + * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes) + * + *****************************************************************************/ +#define XEmacPs_BdSetLength(BdPtr, LenBytes) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes))) + + +/*****************************************************************************/ +/** + * Retrieve the BD length field. + * + * For Tx channels, the returned value is the same as that written with + * XEmacPs_BdSetLength(). + * + * For Rx channels, the returned value is the size of the received packet. + * + * @param BdPtr is the BD pointer to operate on + * + * @return Length field processed by hardware or set by + * XEmacPs_BdSetLength(). + * + * @note + * C-style signature: + * u32 XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr) + * XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK. + * + *****************************************************************************/ +#define XEmacPs_BdGetLength(BdPtr) \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_LEN_MASK) + + +/*****************************************************************************/ +/** + * Test whether the given BD has been marked as the last BD of a packet. + * + * @param BdPtr is the BD pointer to operate on + * + * @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise + * + * @note + * C-style signature: + * u32 XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsLast(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_EOF_MASK) ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Tell the DMA engine that the given transmit BD marks the end of the current + * packet to be processed. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdSetLast(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_LAST_MASK)) + + +/*****************************************************************************/ +/** + * Tell the DMA engine that the current packet does not end with the given + * BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearLast(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_LAST_MASK)) + + +/*****************************************************************************/ +/** + * Set this bit to mark the last descriptor in the receive buffer descriptor + * list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdSetRxWrap(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \ + XEMACPS_RXBUF_WRAP_MASK)) + + +/*****************************************************************************/ +/** + * Determine the wrap bit of the receive BD which indicates end of the + * BD list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u32 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxWrap(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + XEMACPS_RXBUF_WRAP_MASK) ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Sets this bit to mark the last descriptor in the transmit buffer + * descriptor list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdSetTxWrap(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_WRAP_MASK)) + + +/*****************************************************************************/ +/** + * Determine the wrap bit of the transmit BD which indicates end of the + * BD list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u32 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxWrap(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_WRAP_MASK) ? TRUE : FALSE) + + +/*****************************************************************************/ +/* + * Must clear this bit to enable the MAC to write data to the receive + * buffer. Hardware sets this bit once it has successfully written a frame to + * memory. Once set, software has to clear the bit before the buffer can be + * used again. This macro clear the new bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearRxNew(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + ~XEMACPS_RXBUF_NEW_MASK)) + + +/*****************************************************************************/ +/** + * Determine the new bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u32 XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxNew(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + XEMACPS_RXBUF_NEW_MASK) ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Software sets this bit to disable the buffer to be read by the hardware. + * Hardware sets this bit for the first buffer of a frame once it has been + * successfully transmitted. This macro sets this bit of transmit BD to avoid + * confusion. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdSetTxUsed(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_USED_MASK)) + + +/*****************************************************************************/ +/** + * Software clears this bit to enable the buffer to be read by the hardware. + * Hardware sets this bit for the first buffer of a frame once it has been + * successfully transmitted. This macro clears this bit of transmit BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearTxUsed(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_USED_MASK)) + + +/*****************************************************************************/ +/** + * Determine the used bit of the transmit BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u32 XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxUsed(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_USED_MASK) ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if a frame fails to be transmitted due to too many retries. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u32 XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxRetry(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_RETRY_MASK) ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if a frame fails to be transmitted due to data can not be + * feteched in time or buffers are exhausted. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u32 XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxUrun(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_URUN_MASK) ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if a frame fails to be transmitted due to buffer is exhausted + * mid-frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u32 XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxExh(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_EXH_MASK) ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Sets this bit, no CRC will be appended to the current frame. This control + * bit must be set for the first buffer in a frame and will be ignored for + * the subsequent buffers of a frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * This bit must be clear when using the transmit checksum generation offload, + * otherwise checksum generation and substitution will not occur. + * + * C-style signature: + * u32 XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdSetTxNoCRC(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_NOCRC_MASK)) + + +/*****************************************************************************/ +/** + * Clear this bit, CRC will be appended to the current frame. This control + * bit must be set for the first buffer in a frame and will be ignored for + * the subsequent buffers of a frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * This bit must be clear when using the transmit checksum generation offload, + * otherwise checksum generation and substitution will not occur. + * + * C-style signature: + * u32 XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearTxNoCRC(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_NOCRC_MASK)) + + +/*****************************************************************************/ +/** + * Determine the broadcast bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u32 XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxBcast(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_BCAST_MASK) ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the multicast hash bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u32 XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxMultiHash(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_MULTIHASH_MASK) ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the unicast hash bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u32 XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxUniHash(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_UNIHASH_MASK) ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if the received frame is a VLAN Tagged frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u32 XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxVlan(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_VLAN_MASK) ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if the received frame has Type ID of 8100h and null VLAN + * identifier(Priority tag). + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u32 XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxPri(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_PRI_MASK) ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if the received frame's Concatenation Format Indicator (CFI) of + * the frames VLANTCI field was set. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u32 XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxCFI(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_CFI_MASK) ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the End Of Frame (EOF) bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u32 XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxEOF(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_EOF_MASK) ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the Start Of Frame (SOF) bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u32 XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxSOF(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_SOF_MASK) ? TRUE : FALSE) + + +/************************** Function Prototypes ******************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_bdring.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_bdring.c new file mode 100644 index 000000000..40c1e35dc --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_bdring.c @@ -0,0 +1,1010 @@ +/* $Id: xemacps_bdring.c,v 1.1.2.1 2011/01/20 03:39:02 sadanan Exp $ */ +/****************************************************************************** +* +* (c) Copyright 2010 Xilinx, Inc. All rights reserved. +* +* This file contains confidential and proprietary information of Xilinx, Inc. +* and is protected under U.S. and international copyright and other +* intellectual property laws. +* +* DISCLAIMER +* This disclaimer is not a license and does not grant any rights to the +* materials distributed herewith. Except as otherwise provided in a valid +* license issued to you by Xilinx, and to the maximum extent permitted by +* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL +* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, +* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; +* and (2) Xilinx shall not be liable (whether in contract or tort, including +* negligence, or under any other theory of liability) for any loss or damage +* of any kind or nature related to, arising under or in connection with these +* materials, including for any direct, or any indirect, special, incidental, +* or consequential loss or damage (including loss of data, profits, goodwill, +* or any type of loss or damage suffered as a result of any action brought by +* a third party) even if such damage or loss was reasonably foreseeable or +* Xilinx had been advised of the possibility of the same. +* +* CRITICAL APPLICATIONS +* Xilinx products are not designed or intended to be fail-safe, or for use in +* any application requiring fail-safe performance, such as life-support or +* safety devices or systems, Class III medical devices, nuclear facilities, +* applications related to the deployment of airbags, or any other applications +* that could lead to death, personal injury, or severe property or +* environmental damage (individually and collectively, "Critical +* Applications"). Customer assumes the sole risk and liability of any use of +* Xilinx products in Critical Applications, subject only to applicable laws +* and regulations governing limitations on product liability. +* +* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE +* AT ALL TIMES. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xemacps_bdring.c +* +* This file implements buffer descriptor ring related functions. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release
+* 1.00a asa  11/21/11 The function XEmacPs_BdRingFromHwTx is modified.
+*		      Earlier it used to search in "BdLimit" number of BDs to
+*		      know which BDs are processed. Now one more check is
+*		      added. It looks for BDs till the current BD pointer
+*		      reaches HwTail. By doing this processing time is saved.
+* 1.00a asa  01/24/12 The function XEmacPs_BdRingFromHwTx in file
+*		      xemacps_bdring.c is modified. Now start of packet is
+*		      searched for returning the number of BDs processed.
+* 1.05a asa  09/23/13 Cache operations on BDs are not required and hence
+*		      removed. It is expected that all BDs are allocated in
+*		      from uncached area. Fix for CR #663885.
+*
+******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xil_cache.h" +#include "xemacps_hw.h" +#include "xemacps_bd.h" +#include "xemacps_bdring.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************************************************************** + * Compute the virtual address of a descriptor from its physical address + * + * @param BdPtr is the physical address of the BD + * + * @returns Virtual address of BdPtr + * + * @note Assume BdPtr is always a valid BD in the ring + ****************************************************************************/ +#define XEMACPS_PHYS_TO_VIRT(BdPtr) \ + ((u32)BdPtr + (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr)) + +/**************************************************************************** + * Compute the physical address of a descriptor from its virtual address + * + * @param BdPtr is the physical address of the BD + * + * @returns Physical address of BdPtr + * + * @note Assume BdPtr is always a valid BD in the ring + ****************************************************************************/ +#define XEMACPS_VIRT_TO_PHYS(BdPtr) \ + ((u32)BdPtr - (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr)) + +/**************************************************************************** + * Move the BdPtr argument ahead an arbitrary number of BDs wrapping around + * to the beginning of the ring if needed. + * + * We know if a wrapaound should occur if the new BdPtr is greater than + * the high address in the ring OR if the new BdPtr crosses over the + * 0xFFFFFFFF to 0 boundary. The latter test is a valid one since we do not + * allow a BD space to span this boundary. + * + * @param RingPtr is the ring BdPtr appears in + * @param BdPtr on input is the starting BD position and on output is the + * final BD position + * @param NumBd is the number of BD spaces to increment + * + ****************************************************************************/ +#define XEMACPS_RING_SEEKAHEAD(RingPtr, BdPtr, NumBd) \ + { \ + u32 Addr = (u32)BdPtr; \ + \ + Addr += ((RingPtr)->Separation * NumBd); \ + if ((Addr > (RingPtr)->HighBdAddr) || ((u32)BdPtr > Addr)) \ + { \ + Addr -= (RingPtr)->Length; \ + } \ + \ + BdPtr = (XEmacPs_Bd*)Addr; \ + } + +/**************************************************************************** + * Move the BdPtr argument backwards an arbitrary number of BDs wrapping + * around to the end of the ring if needed. + * + * We know if a wrapaound should occur if the new BdPtr is less than + * the base address in the ring OR if the new BdPtr crosses over the + * 0xFFFFFFFF to 0 boundary. The latter test is a valid one since we do not + * allow a BD space to span this boundary. + * + * @param RingPtr is the ring BdPtr appears in + * @param BdPtr on input is the starting BD position and on output is the + * final BD position + * @param NumBd is the number of BD spaces to increment + * + ****************************************************************************/ +#define XEMACPS_RING_SEEKBACK(RingPtr, BdPtr, NumBd) \ + { \ + u32 Addr = (u32)BdPtr; \ + \ + Addr -= ((RingPtr)->Separation * NumBd); \ + if ((Addr < (RingPtr)->BaseBdAddr) || ((u32)BdPtr < Addr)) \ + { \ + Addr += (RingPtr)->Length; \ + } \ + \ + BdPtr = (XEmacPs_Bd*)Addr; \ + } + + +/************************** Function Prototypes ******************************/ + + +/************************** Variable Definitions *****************************/ + +/*****************************************************************************/ +/** + * Using a memory segment allocated by the caller, create and setup the BD list + * for the given DMA channel. + * + * @param RingPtr is the instance to be worked on. + * @param PhysAddr is the physical base address of user memory region. + * @param VirtAddr is the virtual base address of the user memory region. If + * address translation is not being utilized, then VirtAddr should be + * equivalent to PhysAddr. + * @param Alignment governs the byte alignment of individual BDs. This function + * will enforce a minimum alignment of 4 bytes with no maximum as long + * as it is specified as a power of 2. + * @param BdCount is the number of BDs to setup in the user memory region. It + * is assumed the region is large enough to contain the BDs. + * + * @return + * + * - XST_SUCCESS if initialization was successful + * - XST_NO_FEATURE if the provided instance is a non DMA type + * channel. + * - XST_INVALID_PARAM under any of the following conditions: + * 1) PhysAddr and/or VirtAddr are not aligned to the given Alignment + * parameter; + * 2) Alignment parameter does not meet minimum requirements or is not a + * power of 2 value; + * 3) BdCount is 0. + * - XST_DMA_SG_LIST_ERROR if the memory segment containing the list spans + * over address 0x00000000 in virtual address space. + * + * @note + * Make sure to pass in the right alignment value. + *****************************************************************************/ +int XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, u32 PhysAddr, + u32 VirtAddr, u32 Alignment, unsigned BdCount) +{ + unsigned i; + u32 BdVirtAddr; + u32 BdPhyAddr; + + /* In case there is a failure prior to creating list, make sure the + * following attributes are 0 to prevent calls to other functions + * from doing anything. + */ + RingPtr->AllCnt = 0; + RingPtr->FreeCnt = 0; + RingPtr->HwCnt = 0; + RingPtr->PreCnt = 0; + RingPtr->PostCnt = 0; + + /* Make sure Alignment parameter meets minimum requirements */ + if (Alignment < XEMACPS_DMABD_MINIMUM_ALIGNMENT) { + return (XST_INVALID_PARAM); + } + + /* Make sure Alignment is a power of 2 */ + if ((Alignment - 1) & Alignment) { + return (XST_INVALID_PARAM); + } + + /* Make sure PhysAddr and VirtAddr are on same Alignment */ + if ((PhysAddr % Alignment) || (VirtAddr % Alignment)) { + return (XST_INVALID_PARAM); + } + + /* Is BdCount reasonable? */ + if (BdCount == 0) { + return (XST_INVALID_PARAM); + } + + /* Figure out how many bytes will be between the start of adjacent BDs */ + RingPtr->Separation = + (sizeof(XEmacPs_Bd) + (Alignment - 1)) & ~(Alignment - 1); + + /* Must make sure the ring doesn't span address 0x00000000. If it does, + * then the next/prev BD traversal macros will fail. + */ + if (VirtAddr > (VirtAddr + (RingPtr->Separation * BdCount) - 1)) { + return (XST_DMA_SG_LIST_ERROR); + } + + /* Initial ring setup: + * - Clear the entire space + * - Setup each BD's BDA field with the physical address of the next BD + */ + memset((void *) VirtAddr, 0, (RingPtr->Separation * BdCount)); + + BdVirtAddr = VirtAddr; + BdPhyAddr = PhysAddr + RingPtr->Separation; + for (i = 1; i < BdCount; i++) { + BdVirtAddr += RingPtr->Separation; + BdPhyAddr += RingPtr->Separation; + } + + /* Setup and initialize pointers and counters */ + RingPtr->RunState = XST_DMA_SG_IS_STOPPED; + RingPtr->BaseBdAddr = VirtAddr; + RingPtr->PhysBaseAddr = PhysAddr; + RingPtr->HighBdAddr = BdVirtAddr; + RingPtr->Length = + RingPtr->HighBdAddr - RingPtr->BaseBdAddr + RingPtr->Separation; + RingPtr->AllCnt = BdCount; + RingPtr->FreeCnt = BdCount; + RingPtr->FreeHead = (XEmacPs_Bd *) VirtAddr; + RingPtr->PreHead = (XEmacPs_Bd *) VirtAddr; + RingPtr->HwHead = (XEmacPs_Bd *) VirtAddr; + RingPtr->HwTail = (XEmacPs_Bd *) VirtAddr; + RingPtr->PostHead = (XEmacPs_Bd *) VirtAddr; + RingPtr->BdaRestart = (XEmacPs_Bd *) PhysAddr; + + return (XST_SUCCESS); +} + + +/*****************************************************************************/ +/** + * Clone the given BD into every BD in the list. + * every field of the source BD is replicated in every BD of the list. + * + * This function can be called only when all BDs are in the free group such as + * they are immediately after initialization with XEmacPs_BdRingCreate(). + * This prevents modification of BDs while they are in use by hardware or the + * user. + * + * @param RingPtr is the pointer of BD ring instance to be worked on. + * @param SrcBdPtr is the source BD template to be cloned into the list. This + * BD will be modified. + * @param Direction is either XEMACPS_SEND or XEMACPS_RECV that indicates + * which direction. + * + * @return + * - XST_SUCCESS if the list was modified. + * - XST_DMA_SG_NO_LIST if a list has not been created. + * - XST_DMA_SG_LIST_ERROR if some of the BDs in this channel are under + * hardware or user control. + * - XST_DEVICE_IS_STARTED if the DMA channel has not been stopped. + * + *****************************************************************************/ +int XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr, + u8 Direction) +{ + unsigned i; + u32 CurBd; + + /* Can't do this function if there isn't a ring */ + if (RingPtr->AllCnt == 0) { + return (XST_DMA_SG_NO_LIST); + } + + /* Can't do this function with the channel running */ + if (RingPtr->RunState == XST_DMA_SG_IS_STARTED) { + return (XST_DEVICE_IS_STARTED); + } + + /* Can't do this function with some of the BDs in use */ + if (RingPtr->FreeCnt != RingPtr->AllCnt) { + return (XST_DMA_SG_LIST_ERROR); + } + + if ((Direction != XEMACPS_SEND) && (Direction != XEMACPS_RECV)) { + return (XST_INVALID_PARAM); + } + + /* Starting from the top of the ring, save BD.Next, overwrite the entire + * BD with the template, then restore BD.Next + */ + for (i = 0, CurBd = (u32) RingPtr->BaseBdAddr; + i < RingPtr->AllCnt; i++, CurBd += RingPtr->Separation) { + memcpy((void *)CurBd, SrcBdPtr, sizeof(XEmacPs_Bd)); + } + + CurBd -= RingPtr->Separation; + + if (Direction == XEMACPS_RECV) { + XEmacPs_BdSetRxWrap(CurBd); + } + else { + XEmacPs_BdSetTxWrap(CurBd); + } + + return (XST_SUCCESS); +} + + +/*****************************************************************************/ +/** + * Reserve locations in the BD list. The set of returned BDs may be modified + * in preparation for future DMA transaction(s). Once the BDs are ready to be + * submitted to hardware, the user must call XEmacPs_BdRingToHw() in the same + * order which they were allocated here. Example: + * + * 
+ *        NumBd = 2;
+ *        Status = XEmacPs_BdRingAlloc(MyRingPtr, NumBd, &MyBdSet);
+ *
+ *        if (Status != XST_SUCCESS)
+ *        {
+ *            // Not enough BDs available for the request
+ *        }
+ *
+ *        CurBd = MyBdSet;
+ *        for (i=0; i
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be allocated and given to hardware in the correct sequence:
+ * 
+ *        // Legal
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1);
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1);
+ *
+ *        // Legal
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1);
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd2, &MySet2);
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1);
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd2, MySet2);
+ *
+ *        // Not legal
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1);
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd2, &MySet2);
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd2, MySet2);
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1);
+ * 

+ *
+ * Use the API defined in xemacps_bd.h to modify individual BDs. Traversal
+ * of the BD set can be done using XEmacPs_BdRingNext() and
+ * XEmacPs_BdRingPrev().
+ *
+ * @param RingPtr is a pointer to the BD ring instance to be worked on.
+ * @param NumBd is the number of BDs to allocate
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ *        for modification.
+ *
+ * @return
+ *   - XST_SUCCESS if the requested number of BDs was returned in the BdSetPtr
+ *     parameter.
+ *   - XST_FAILURE if there were not enough free BDs to satisfy the request.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ * @note Do not modify more BDs than the number requested with the NumBd
+ *       parameter. Doing so will lead to data corruption and system
+ *       instability.
+ *
+ *****************************************************************************/
+int XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, unsigned NumBd,
+			 XEmacPs_Bd ** BdSetPtr)
+{
+	/* Enough free BDs available for the request? */
+	if (RingPtr->FreeCnt < NumBd) {
+		return (XST_FAILURE);
+	}
+
+	/* Set the return argument and move FreeHead forward */
+	*BdSetPtr = RingPtr->FreeHead;
+	XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->FreeHead, NumBd);
+	RingPtr->FreeCnt -= NumBd;
+	RingPtr->PreCnt += NumBd;
+	return (XST_SUCCESS);
+}
+
+/*****************************************************************************/
+/**
+ * Fully or partially undo an XEmacPs_BdRingAlloc() operation. Use this
+ * function if all the BDs allocated by XEmacPs_BdRingAlloc() could not be
+ * transferred to hardware with XEmacPs_BdRingToHw().
+ *
+ * This function helps out in situations when an unrelated error occurs after
+ * BDs have been allocated but before they have been given to hardware.
+ * An example of this type of error would be an OS running out of resources.
+ *
+ * This function is not the same as XEmacPs_BdRingFree(). The Free function
+ * returns BDs to the free list after they have been processed by hardware,
+ * while UnAlloc returns them before being processed by hardware.
+ *
+ * There are two scenarios where this function can be used. Full UnAlloc or
+ * Partial UnAlloc. A Full UnAlloc means all the BDs Alloc'd will be returned:
+ *
+ * 
+ *    Status = XEmacPs_BdRingAlloc(MyRingPtr, 10, &BdPtr);
+ *        ...
+ *    if (Error)
+ *    {
+ *        Status = XEmacPs_BdRingUnAlloc(MyRingPtr, 10, &BdPtr);
+ *    }
+ * 

+ *
+ * A partial UnAlloc means some of the BDs Alloc'd will be returned:
+ *
+ * 
+ *    Status = XEmacPs_BdRingAlloc(MyRingPtr, 10, &BdPtr);
+ *    BdsLeft = 10;
+ *    CurBdPtr = BdPtr;
+ *
+ *    while (BdsLeft)
+ *    {
+ *       if (Error)
+ *       {
+ *          Status = XEmacPs_BdRingUnAlloc(MyRingPtr, BdsLeft, CurBdPtr);
+ *       }
+ *
+ *       CurBdPtr = XEmacPs_BdRingNext(MyRingPtr, CurBdPtr);
+ *       BdsLeft--;
+ *    }
+ * 

+ *
+ * A partial UnAlloc must include the last BD in the list that was Alloc'd.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param NumBd is the number of BDs to allocate
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ *        for modification.
+ *
+ * @return
+ *   - XST_SUCCESS if the BDs were unallocated.
+ *   - XST_FAILURE if NumBd parameter was greater that the number of BDs in
+ *     the preprocessing state.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+int XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, unsigned NumBd,
+			   XEmacPs_Bd * BdSetPtr)
+{
+	(void)BdSetPtr;
+
+	/* Enough BDs in the free state for the request? */
+	if (RingPtr->PreCnt < NumBd) {
+		return (XST_FAILURE);
+	}
+
+	/* Set the return argument and move FreeHead backward */
+	XEMACPS_RING_SEEKBACK(RingPtr, RingPtr->FreeHead, NumBd);
+	RingPtr->FreeCnt += NumBd;
+	RingPtr->PreCnt -= NumBd;
+	return (XST_SUCCESS);
+}
+
+
+/*****************************************************************************/
+/**
+ * Enqueue a set of BDs to hardware that were previously allocated by
+ * XEmacPs_BdRingAlloc(). Once this function returns, the argument BD set goes
+ * under hardware control. Any changes made to these BDs after this point will
+ * corrupt the BD list leading to data corruption and system instability.
+ *
+ * The set will be rejected if the last BD of the set does not mark the end of
+ * a packet (see XEmacPs_BdSetLast()).
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param NumBd is the number of BDs in the set.
+ * @param BdSetPtr is the first BD of the set to commit to hardware.
+ *
+ * @return
+ *   - XST_SUCCESS if the set of BDs was accepted and enqueued to hardware.
+ *   - XST_FAILURE if the set of BDs was rejected because the last BD of the set
+ *     did not have its "last" bit set.
+ *   - XST_DMA_SG_LIST_ERROR if this function was called out of sequence with
+ *     XEmacPs_BdRingAlloc().
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+int XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, unsigned NumBd,
+			XEmacPs_Bd * BdSetPtr)
+{
+	XEmacPs_Bd *CurBdPtr;
+	unsigned i;
+
+	/* if no bds to process, simply return. */
+	if (0 == NumBd)
+		return (XST_SUCCESS);
+
+	/* Make sure we are in sync with XEmacPs_BdRingAlloc() */
+	if ((RingPtr->PreCnt < NumBd) || (RingPtr->PreHead != BdSetPtr)) {
+		return (XST_DMA_SG_LIST_ERROR);
+	}
+
+	CurBdPtr = BdSetPtr;
+	for (i = 0; i < NumBd; i++) {
+		CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
+	}
+
+	/* Adjust ring pointers & counters */
+	XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PreHead, NumBd);
+	RingPtr->PreCnt -= NumBd;
+
+	RingPtr->HwTail = CurBdPtr;
+	RingPtr->HwCnt += NumBd;
+
+	return (XST_SUCCESS);
+}
+
+
+/*****************************************************************************/
+/**
+ * Returns a set of BD(s) that have been processed by hardware. The returned
+ * BDs may be examined to determine the outcome of the DMA transaction(s).
+ * Once the BDs have been examined, the user must call XEmacPs_BdRingFree()
+ * in the same order which they were retrieved here. Example:
+ *
+ * 
+ *        NumBd = XEmacPs_BdRingFromHwTx(MyRingPtr, MaxBd, &MyBdSet);
+ *
+ *        if (NumBd == 0)
+ *        {
+ *           // hardware has nothing ready for us yet
+ *        }
+ *
+ *        CurBd = MyBdSet;
+ *        for (i=0; i
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be retrieved from hardware and freed in the correct sequence:
+ * 
+ *        // Legal
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1);
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1);
+ *
+ *        // Legal
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1);
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd2, &MySet2);
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1);
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2);
+ *
+ *        // Not legal
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1);
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd2, &MySet2);
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2);
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1);
+ * 

+ *
+ * If hardware has only partially completed a packet spanning multiple BDs,
+ * then none of the BDs for that packet will be included in the results.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param BdLimit is the maximum number of BDs to return in the set.
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ *        for examination.
+ *
+ * @return
+ *   The number of BDs processed by hardware. A value of 0 indicates that no
+ *   data is available. No more than BdLimit BDs will be returned.
+ *
+ * @note Treat BDs returned by this function as read-only.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+unsigned XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, unsigned BdLimit,
+				 XEmacPs_Bd ** BdSetPtr)
+{
+	XEmacPs_Bd *CurBdPtr;
+	u32 BdStr = 0;
+	unsigned BdCount;
+	unsigned BdPartialCount;
+	unsigned int Sop = 0;
+
+
+	CurBdPtr = RingPtr->HwHead;
+	BdCount = 0;
+	BdPartialCount = 0;
+
+	/* If no BDs in work group, then there's nothing to search */
+	if (RingPtr->HwCnt == 0) {
+		*BdSetPtr = NULL;
+		return (0);
+	}
+
+	if (BdLimit > RingPtr->HwCnt)
+		BdLimit = RingPtr->HwCnt;
+
+	/* Starting at HwHead, keep moving forward in the list until:
+	 *  - A BD is encountered with its new/used bit set which means
+	 *    hardware has not completed processing of that BD.
+	 *  - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
+	 *  - The number of requested BDs has been processed
+	 */
+	while (BdCount < BdLimit) {
+		/* Read the status */
+		BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
+
+		if ((Sop == 0) && (BdStr & XEMACPS_TXBUF_USED_MASK))
+			Sop = 1;
+
+		if (Sop == 1) {
+			BdCount++;
+			BdPartialCount++;
+		}
+
+		/* hardware has processed this BD so check the "last" bit.
+		 * If it is clear, then there are more BDs for the current
+		 * packet. Keep a count of these partial packet BDs.
+		 */
+		if ((Sop == 1) && (BdStr & XEMACPS_TXBUF_LAST_MASK)) {
+			Sop = 0;
+			BdPartialCount = 0;
+		}
+
+		/* Move on to next BD in work group */
+		CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
+	}
+
+	/* Subtract off any partial packet BDs found */
+        BdCount -= BdPartialCount;
+
+	/* If BdCount is non-zero then BDs were found to return. Set return
+	 * parameters, update pointers and counters, return success
+	 */
+	if (BdCount > 0) {
+		*BdSetPtr = RingPtr->HwHead;
+		RingPtr->HwCnt -= BdCount;
+		RingPtr->PostCnt += BdCount;
+		XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
+		return (BdCount);
+	}
+	else {
+		*BdSetPtr = NULL;
+		return (0);
+	}
+}
+
+
+/*****************************************************************************/
+/**
+ * Returns a set of BD(s) that have been processed by hardware. The returned
+ * BDs may be examined to determine the outcome of the DMA transaction(s).
+ * Once the BDs have been examined, the user must call XEmacPs_BdRingFree()
+ * in the same order which they were retrieved here. Example:
+ *
+ * 
+ *        NumBd = XEmacPs_BdRingFromHwRx(MyRingPtr, MaxBd, &MyBdSet);
+ *
+ *        if (NumBd == 0)
+ *        {
+ *           // hardware has nothing ready for us yet
+ *        }
+ *
+ *        CurBd = MyBdSet;
+ *        for (i=0; i
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be retrieved from hardware and freed in the correct sequence:
+ * 
+ *        // Legal
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1);
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1);
+ *
+ *        // Legal
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1);
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd2, &MySet2);
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1);
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2);
+ *
+ *        // Not legal
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1);
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd2, &MySet2);
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2);
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1);
+ * 

+ *
+ * If hardware has only partially completed a packet spanning multiple BDs,
+ * then none of the BDs for that packet will be included in the results.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param BdLimit is the maximum number of BDs to return in the set.
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ *        for examination.
+ *
+ * @return
+ *   The number of BDs processed by hardware. A value of 0 indicates that no
+ *   data is available. No more than BdLimit BDs will be returned.
+ *
+ * @note Treat BDs returned by this function as read-only.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+unsigned XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, unsigned BdLimit,
+				 XEmacPs_Bd ** BdSetPtr)
+{
+	XEmacPs_Bd *CurBdPtr;
+	u32 BdStr = 0;
+	unsigned BdCount;
+	unsigned BdPartialCount;
+
+	CurBdPtr = RingPtr->HwHead;
+	BdCount = 0;
+	BdPartialCount = 0;
+
+	/* If no BDs in work group, then there's nothing to search */
+	if (RingPtr->HwCnt == 0) {
+		*BdSetPtr = NULL;
+		return (0);
+	}
+
+	/* Starting at HwHead, keep moving forward in the list until:
+	 *  - A BD is encountered with its new/used bit set which means
+	 *    hardware has completed processing of that BD.
+	 *  - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
+	 *  - The number of requested BDs has been processed
+	 */
+	while (BdCount < BdLimit) {
+
+		/* Read the status */
+		BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
+
+		if (!(XEmacPs_BdIsRxNew(CurBdPtr))) {
+			break;
+		}
+
+		BdCount++;
+
+		/* hardware has processed this BD so check the "last" bit. If
+                 * it is clear, then there are more BDs for the current packet.
+                 * Keep a count of these partial packet BDs.
+		 */
+		if (BdStr & XEMACPS_RXBUF_EOF_MASK) {
+			BdPartialCount = 0;
+		}
+		else {
+			BdPartialCount++;
+		}
+
+		/* Move on to next BD in work group */
+		CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
+	}
+
+	/* Subtract off any partial packet BDs found */
+	BdCount -= BdPartialCount;
+
+	/* If BdCount is non-zero then BDs were found to return. Set return
+	 * parameters, update pointers and counters, return success
+	 */
+	if (BdCount > 0) {
+		*BdSetPtr = RingPtr->HwHead;
+		RingPtr->HwCnt -= BdCount;
+		RingPtr->PostCnt += BdCount;
+		XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
+		return (BdCount);
+	}
+	else {
+		*BdSetPtr = NULL;
+		return (0);
+	}
+}
+
+
+/*****************************************************************************/
+/**
+ * Frees a set of BDs that had been previously retrieved with
+ * XEmacPs_BdRingFromHw().
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param NumBd is the number of BDs to free.
+ * @param BdSetPtr is the head of a list of BDs returned by
+ * XEmacPs_BdRingFromHw().
+ *
+ * @return
+ *   - XST_SUCCESS if the set of BDs was freed.
+ *   - XST_DMA_SG_LIST_ERROR if this function was called out of sequence with
+ *     XEmacPs_BdRingFromHw().
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+int XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, unsigned NumBd,
+			XEmacPs_Bd * BdSetPtr)
+{
+	/* if no bds to process, simply return. */
+	if (0 == NumBd)
+		return (XST_SUCCESS);
+
+	/* Make sure we are in sync with XEmacPs_BdRingFromHw() */
+	if ((RingPtr->PostCnt < NumBd) || (RingPtr->PostHead != BdSetPtr)) {
+		return (XST_DMA_SG_LIST_ERROR);
+	}
+
+	/* Update pointers and counters */
+	RingPtr->FreeCnt += NumBd;
+	RingPtr->PostCnt -= NumBd;
+	XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PostHead, NumBd);
+	return (XST_SUCCESS);
+}
+
+
+/*****************************************************************************/
+/**
+ * Check the internal data structures of the BD ring for the provided channel.
+ * The following checks are made:
+ *
+ *   - Is the BD ring linked correctly in physical address space.
+ *   - Do the internal pointers point to BDs in the ring.
+ *   - Do the internal counters add up.
+ *
+ * The channel should be stopped prior to calling this function.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param Direction is either XEMACPS_SEND or XEMACPS_RECV that indicates
+ *        which direction.
+ *
+ * @return
+ *   - XST_SUCCESS if the set of BDs was freed.
+ *   - XST_DMA_SG_NO_LIST if the list has not been created.
+ *   - XST_IS_STARTED if the channel is not stopped.
+ *   - XST_DMA_SG_LIST_ERROR if a problem is found with the internal data
+ *     structures. If this value is returned, the channel should be reset to
+ *     avoid data corruption or system instability.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+int XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction)
+{
+	u32 AddrV, AddrP;
+	unsigned i;
+
+	if ((Direction != XEMACPS_SEND) && (Direction != XEMACPS_RECV)) {
+		return (XST_INVALID_PARAM);
+	}
+
+	/* Is the list created */
+	if (RingPtr->AllCnt == 0) {
+		return (XST_DMA_SG_NO_LIST);
+	}
+
+	/* Can't check if channel is running */
+	if (RingPtr->RunState == XST_DMA_SG_IS_STARTED) {
+		return (XST_IS_STARTED);
+	}
+
+	/* RunState doesn't make sense */
+	else if (RingPtr->RunState != XST_DMA_SG_IS_STOPPED) {
+		return (XST_DMA_SG_LIST_ERROR);
+	}
+
+	/* Verify internal pointers point to correct memory space */
+	AddrV = (u32) RingPtr->FreeHead;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (XST_DMA_SG_LIST_ERROR);
+	}
+
+	AddrV = (u32) RingPtr->PreHead;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (XST_DMA_SG_LIST_ERROR);
+	}
+
+	AddrV = (u32) RingPtr->HwHead;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (XST_DMA_SG_LIST_ERROR);
+	}
+
+	AddrV = (u32) RingPtr->HwTail;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (XST_DMA_SG_LIST_ERROR);
+	}
+
+	AddrV = (u32) RingPtr->PostHead;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (XST_DMA_SG_LIST_ERROR);
+	}
+
+	/* Verify internal counters add up */
+	if ((RingPtr->HwCnt + RingPtr->PreCnt + RingPtr->FreeCnt +
+	     RingPtr->PostCnt) != RingPtr->AllCnt) {
+		return (XST_DMA_SG_LIST_ERROR);
+	}
+
+	/* Verify BDs are linked correctly */
+	AddrV = RingPtr->BaseBdAddr;
+	AddrP = RingPtr->PhysBaseAddr + RingPtr->Separation;
+
+	for (i = 1; i < RingPtr->AllCnt; i++) {
+		/* Check BDA for this BD. It should point to next physical addr */
+		if (XEmacPs_BdRead(AddrV, XEMACPS_BD_ADDR_OFFSET) != AddrP) {
+			return (XST_DMA_SG_LIST_ERROR);
+		}
+
+		/* Move on to next BD */
+		AddrV += RingPtr->Separation;
+		AddrP += RingPtr->Separation;
+	}
+
+	/* Last BD should have wrap bit set */
+	if (XEMACPS_SEND == Direction) {
+		if (!XEmacPs_BdIsTxWrap(AddrV)) {
+			return (XST_DMA_SG_LIST_ERROR);
+		}
+	}
+	else {			/* XEMACPS_RECV */
+		if (!XEmacPs_BdIsRxWrap(AddrV)) {
+			return (XST_DMA_SG_LIST_ERROR);
+		}
+	}
+
+	/* No problems found */
+	return (XST_SUCCESS);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_bdring.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_bdring.h
new file mode 100644
index 000000000..9c50d618e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_bdring.h
@@ -0,0 +1,242 @@
+/* $Id: xemacps_bdring.h,v 1.1.2.1 2011/01/20 03:39:02 sadanan Exp $ */
+/******************************************************************************
+*
+* (c) Copyright 2010 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_bdring.h
+*
+* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
+* DMA functionalities.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release
+* 

+*
+******************************************************************************/
+
+#ifndef XEMACPS_BDRING_H	/* prevent curcular inclusions */
+#define XEMACPS_BDRING_H	/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**************************** Type Definitions *******************************/
+
+/** This is an internal structure used to maintain the DMA list */
+typedef struct {
+	u32 PhysBaseAddr;/**< Physical address of 1st BD in list */
+	u32 BaseBdAddr;	 /**< Virtual address of 1st BD in list */
+	u32 HighBdAddr;	 /**< Virtual address of last BD in the list */
+	u32 Length;	 /**< Total size of ring in bytes */
+	u32 RunState;	 /**< Flag to indicate DMA is started */
+	u32 Separation;	 /**< Number of bytes between the starting address
+                                  of adjacent BDs */
+	XEmacPs_Bd *FreeHead;
+			     /**< First BD in the free group */
+	XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */
+	XEmacPs_Bd *HwHead; /**< First BD in the work group */
+	XEmacPs_Bd *HwTail; /**< Last BD in the work group */
+	XEmacPs_Bd *PostHead;
+			     /**< First BD in the post-work group */
+	XEmacPs_Bd *BdaRestart;
+			     /**< BDA to load when channel is started */
+	unsigned HwCnt;	     /**< Number of BDs in work group */
+	unsigned PreCnt;     /**< Number of BDs in pre-work group */
+	unsigned FreeCnt;    /**< Number of allocatable BDs in the free group */
+	unsigned PostCnt;    /**< Number of BDs in post-work group */
+	unsigned AllCnt;     /**< Total Number of BDs for channel */
+} XEmacPs_BdRing;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many BDs will fit
+* in a BD list within the given memory constraints.
+*
+* The results of this macro can be provided to XEmacPs_BdRingCreate().
+*
+* @param Alignment specifies what byte alignment the BDs must fall on and
+*        must be a power of 2 to get an accurate calculation (32, 64, 128,...)
+* @param Bytes is the number of bytes to be used to store BDs.
+*
+* @return Number of BDs that can fit in the given memory area
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes)
+*
+******************************************************************************/
+#define XEmacPs_BdRingCntCalc(Alignment, Bytes)                    \
+    (u32)((Bytes) / ((sizeof(XEmacPs_Bd) + ((Alignment)-1)) &   \
+    ~((Alignment)-1)))
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many bytes of memory
+* is required to contain a given number of BDs at a given alignment.
+*
+* @param Alignment specifies what byte alignment the BDs must fall on. This
+*        parameter must be a power of 2 to get an accurate calculation (32, 64,
+*        128,...)
+* @param NumBd is the number of BDs to calculate memory size requirements for
+*
+* @return The number of bytes of memory required to create a BD list with the
+*         given memory constraints.
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd)
+*
+******************************************************************************/
+#define XEmacPs_BdRingMemCalc(Alignment, NumBd)                    \
+    (u32)((sizeof(XEmacPs_Bd) + ((Alignment)-1)) &              \
+    ~((Alignment)-1)) * (NumBd)
+
+/****************************************************************************/
+/**
+* Return the total number of BDs allocated by this channel with
+* XEmacPs_BdRingCreate().
+*
+* @param  RingPtr is the DMA channel to operate on.
+*
+* @return The total number of BDs allocated for this channel.
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
+
+/****************************************************************************/
+/**
+* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre-
+* processing.
+*
+* @param  RingPtr is the DMA channel to operate on.
+*
+* @return The number of BDs currently allocatable.
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingGetFreeCnt(RingPtr)   ((RingPtr)->FreeCnt)
+
+/****************************************************************************/
+/**
+* Return the next BD from BdPtr in a list.
+*
+* @param  RingPtr is the DMA channel to operate on.
+* @param  BdPtr is the BD to operate on.
+*
+* @return The next BD in the list relative to the BdPtr parameter.
+*
+* @note
+* C-style signature:
+*    XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr,
+*                                      XEmacPs_Bd *BdPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingNext(RingPtr, BdPtr)                           \
+    (((u32)(BdPtr) >= (RingPtr)->HighBdAddr) ?                     \
+    (XEmacPs_Bd*)(RingPtr)->BaseBdAddr :                              \
+    (XEmacPs_Bd*)((u32)(BdPtr) + (RingPtr)->Separation))
+
+/****************************************************************************/
+/**
+* Return the previous BD from BdPtr in the list.
+*
+* @param  RingPtr is the DMA channel to operate on.
+* @param  BdPtr is the BD to operate on
+*
+* @return The previous BD in the list relative to the BdPtr parameter.
+*
+* @note
+* C-style signature:
+*    XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr,
+*                                      XEmacPs_Bd *BdPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingPrev(RingPtr, BdPtr)                           \
+    (((u32)(BdPtr) <= (RingPtr)->BaseBdAddr) ?                     \
+    (XEmacPs_Bd*)(RingPtr)->HighBdAddr :                              \
+    (XEmacPs_Bd*)((u32)(BdPtr) - (RingPtr)->Separation))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Scatter gather DMA related functions in xemacps_bdring.c
+ */
+int XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, u32 PhysAddr,
+			  u32 VirtAddr, u32 Alignment, unsigned BdCount);
+int XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
+			 u8 Direction);
+int XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, unsigned NumBd,
+			 XEmacPs_Bd ** BdSetPtr);
+int XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, unsigned NumBd,
+			   XEmacPs_Bd * BdSetPtr);
+int XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, unsigned NumBd,
+			XEmacPs_Bd * BdSetPtr);
+int XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, unsigned NumBd,
+			XEmacPs_Bd * BdSetPtr);
+unsigned XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, unsigned BdLimit,
+				 XEmacPs_Bd ** BdSetPtr);
+unsigned XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, unsigned BdLimit,
+				 XEmacPs_Bd ** BdSetPtr);
+int XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* end of protection macros */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_control.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_control.c
new file mode 100644
index 000000000..2daf8adc3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_control.c
@@ -0,0 +1,1084 @@
+/* $Id: xemacps_control.c,v 1.1.2.1 2011/01/20 03:39:02 sadanan Exp $ */
+/******************************************************************************
+*
+* (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xemacps_control.c
+ *
+ * Functions in this file implement general purpose command and control related
+ * functionality. See xemacps.h for a detailed description of the driver.
+ *
+ * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy  01/10/10 First release
+ * 1.02a asa  11/05/12 Added a new API for deleting an entry from the HASH
+ *					   register. Added a new API for setting the BURST length
+ *					   in DMACR register.
+ * 

+ *****************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+ * Set the MAC address for this driver/device.  The address is a 48-bit value.
+ * The device must be stopped before calling this function.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is a pointer to a 6-byte MAC address.
+ * @param Index is a index to which MAC (1-4) address.
+ *
+ * @return
+ * - XST_SUCCESS if the MAC address was set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ *****************************************************************************/
+int XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
+{
+	u32 MacAddr;
+	u8 *Aptr = (u8 *) AddressPtr;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(AddressPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((Index <= XEMACPS_MAX_MAC_ADDR) && (Index > 0));
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
+		return (XST_DEVICE_IS_STARTED);
+	}
+
+	/* Index ranges 1 to 4, for offset calculation is 0 to 3. */
+	Index--;
+
+	/* Set the MAC bits [31:0] in BOT */
+	MacAddr = Aptr[0];
+	MacAddr |= Aptr[1] << 8;
+	MacAddr |= Aptr[2] << 16;
+	MacAddr |= Aptr[3] << 24;
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			(XEMACPS_LADDR1L_OFFSET + Index * 8), MacAddr);
+
+	/* There are reserved bits in TOP so don't affect them */
+	MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				(XEMACPS_LADDR1H_OFFSET + (Index * 8)));
+
+	MacAddr &= ~XEMACPS_LADDR_MACH_MASK;
+
+	/* Set MAC bits [47:32] in TOP */
+	MacAddr |= Aptr[4];
+	MacAddr |= Aptr[5] << 8;
+
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			(XEMACPS_LADDR1H_OFFSET + (Index * 8)), MacAddr);
+
+	return (XST_SUCCESS);
+}
+
+
+/*****************************************************************************/
+/**
+ * Get the MAC address for this driver/device.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is an output parameter, and is a pointer to a buffer into
+ *        which the current MAC address will be copied.
+ * @param Index is a index to which MAC (1-4) address.
+ *
+ *****************************************************************************/
+void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
+{
+	u32 MacAddr;
+	u8 *Aptr = (u8 *) AddressPtr;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(AddressPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((Index <= XEMACPS_MAX_MAC_ADDR) && (Index > 0));
+
+	/* Index ranges 1 to 4, for offset calculation is 0 to 3. */
+	Index--;
+
+	MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    (XEMACPS_LADDR1L_OFFSET + (Index * 8)));
+	Aptr[0] = (u8) MacAddr;
+	Aptr[1] = (u8) (MacAddr >> 8);
+	Aptr[2] = (u8) (MacAddr >> 16);
+	Aptr[3] = (u8) (MacAddr >> 24);
+
+	/* Read MAC bits [47:32] in TOP */
+	MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    (XEMACPS_LADDR1H_OFFSET + (Index * 8)));
+	Aptr[4] = (u8) MacAddr;
+	Aptr[5] = (u8) (MacAddr >> 8);
+}
+
+
+/*****************************************************************************/
+/**
+ * Set 48-bit MAC addresses in hash table.
+ * The device must be stopped before calling this function.
+ *
+ * The hash address register is 64 bits long and takes up two locations in
+ * the memory map. The least significant bits are stored in hash register
+ * bottom and the most significant bits in hash register top.
+ *
+ * The unicast hash enable and the multicast hash enable bits in the network
+ * configuration register enable the reception of hash matched frames. The
+ * destination address is reduced to a 6 bit index into the 64 bit hash
+ * register using the following hash function. The hash function is an XOR
+ * of every sixth bit of the destination address.
+ *
+ * 
+ * hash_index[05] = da[05]^da[11]^da[17]^da[23]^da[29]^da[35]^da[41]^da[47]
+ * hash_index[04] = da[04]^da[10]^da[16]^da[22]^da[28]^da[34]^da[40]^da[46]
+ * hash_index[03] = da[03]^da[09]^da[15]^da[21]^da[27]^da[33]^da[39]^da[45]
+ * hash_index[02] = da[02]^da[08]^da[14]^da[20]^da[26]^da[32]^da[38]^da[44]
+ * hash_index[01] = da[01]^da[07]^da[13]^da[19]^da[25]^da[31]^da[37]^da[43]
+ * hash_index[00] = da[00]^da[06]^da[12]^da[18]^da[24]^da[30]^da[36]^da[42]
+ * 

+ *
+ * da[0] represents the least significant bit of the first byte received,
+ * that is, the multicast/unicast indicator, and da[47] represents the most
+ * significant bit of the last byte received.
+ *
+ * If the hash index points to a bit that is set in the hash register then
+ * the frame will be matched according to whether the frame is multicast
+ * or unicast.
+ *
+ * A multicast match will be signaled if the multicast hash enable bit is
+ * set, da[0] is logic 1 and the hash index points to a bit set in the hash
+ * register.
+ *
+ * A unicast match will be signaled if the unicast hash enable bit is set,
+ * da[0] is logic 0 and the hash index points to a bit set in the hash
+ * register.
+ *
+ * To receive all multicast frames, the hash register should be set with
+ * all ones and the multicast hash enable bit should be set in the network
+ * configuration register.
+ *
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is a pointer to a 6-byte MAC address.
+ *
+ * @return
+ * - XST_SUCCESS if the HASH MAC address was set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ * - XST_INVALID_PARAM if the HASH MAC address passed in does not meet
+ *   requirement after calculation
+ *
+ * @note
+ * Having Aptr be unsigned type prevents the following operations from sign
+ * extending.
+ *****************************************************************************/
+int XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr)
+{
+	u32 HashAddr;
+	u8 *Aptr = (u8 *) AddressPtr;
+	u8 Temp1, Temp2, Temp3, Temp4, Temp5, Temp6, Temp7, Temp8;
+	int Result;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(AddressPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
+		return (XST_DEVICE_IS_STARTED);
+	}
+	Temp1 = Aptr[0] & 0x3F;
+	Temp2 = ((Aptr[0] >> 6) & 0x3) | ((Aptr[1] & 0xF) << 2);
+	Temp3 = ((Aptr[1] >> 4) & 0xF) | ((Aptr[2] & 0x3) << 4);
+	Temp4 = ((Aptr[2] >> 2) & 0x3F);
+	Temp5 =   Aptr[3] & 0x3F;
+	Temp6 = ((Aptr[3] >> 6) & 0x3) | ((Aptr[4] & 0xF) << 2);
+	Temp7 = ((Aptr[4] >> 4) & 0xF) | ((Aptr[5] & 0x3) << 4);
+	Temp8 = ((Aptr[5] >> 2) & 0x3F);
+
+	Result = Temp1 ^ Temp2 ^ Temp3 ^ Temp4 ^ Temp5 ^ Temp6 ^ Temp7 ^ Temp8;
+
+	if (Result >= XEMACPS_MAX_HASH_BITS) {
+		return (XST_INVALID_PARAM);
+	}
+
+	if (Result < 32) {
+		HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHL_OFFSET);
+		HashAddr |= (1 << Result);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_HASHL_OFFSET, HashAddr);
+	} else {
+		HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHH_OFFSET);
+		HashAddr |= (1 << (Result - 32));
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_HASHH_OFFSET, HashAddr);
+	}
+
+	return (XST_SUCCESS);
+}
+
+/*****************************************************************************/
+/**
+ * Delete 48-bit MAC addresses in hash table.
+ * The device must be stopped before calling this function.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is a pointer to a 6-byte MAC address.
+ *
+ * @return
+ * - XST_SUCCESS if the HASH MAC address was deleted successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ * - XST_INVALID_PARAM if the HASH MAC address passed in does not meet
+ *   requirement after calculation
+ *
+ * @note
+ * Having Aptr be unsigned type prevents the following operations from sign
+ * extending.
+ *****************************************************************************/
+int XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr)
+{
+	u32 HashAddr;
+	u8 *Aptr = (u8 *) AddressPtr;
+	u8 Temp1, Temp2, Temp3, Temp4, Temp5, Temp6, Temp7, Temp8;
+	int Result;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(AddressPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
+		return (XST_DEVICE_IS_STARTED);
+	}
+	Temp1 = Aptr[0] & 0x3F;
+	Temp2 = ((Aptr[0] >> 6) & 0x3) | ((Aptr[1] & 0xF) << 2);
+	Temp3 = ((Aptr[1] >> 4) & 0xF) | ((Aptr[2] & 0x3) << 4);
+	Temp4 = ((Aptr[2] >> 2) & 0x3F);
+	Temp5 =   Aptr[3] & 0x3F;
+	Temp6 = ((Aptr[3] >> 6) & 0x3) | ((Aptr[4] & 0xF) << 2);
+	Temp7 = ((Aptr[4] >> 4) & 0xF) | ((Aptr[5] & 0x3) << 4);
+	Temp8 = ((Aptr[5] >> 2) & 0x3F);
+
+	Result = Temp1 ^ Temp2 ^ Temp3 ^ Temp4 ^ Temp5 ^ Temp6 ^ Temp7 ^ Temp8;
+
+	if (Result >= XEMACPS_MAX_HASH_BITS) {
+		return (XST_INVALID_PARAM);
+	}
+
+	if (Result < 32) {
+		HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHL_OFFSET);
+		HashAddr &= (~(1 << Result));
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHL_OFFSET, HashAddr);
+	} else {
+		HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHH_OFFSET);
+		HashAddr &= (~(1 << (Result - 32)));
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_HASHH_OFFSET, HashAddr);
+	}
+
+	return (XST_SUCCESS);
+}
+
+
+/*****************************************************************************/
+/**
+ * Clear the Hash registers for the mac address pointed by AddressPtr.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ *
+ *****************************************************************************/
+void XEmacPs_ClearHash(XEmacPs *InstancePtr)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				    XEMACPS_HASHL_OFFSET, 0x0);
+
+	/* write bits [63:32] in TOP */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				    XEMACPS_HASHH_OFFSET, 0x0);
+}
+
+
+/*****************************************************************************/
+/**
+ * Get the Hash address for this driver/device.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is an output parameter, and is a pointer to a buffer into
+ *        which the current HASH MAC address will be copied.
+ *
+ *****************************************************************************/
+void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr)
+{
+	u32 *Aptr = (u32 *) AddressPtr;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(AddressPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	Aptr[0] = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XEMACPS_HASHL_OFFSET);
+
+	/* Read Hash bits [63:32] in TOP */
+	Aptr[1] = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XEMACPS_HASHH_OFFSET);
+}
+
+
+/*****************************************************************************/
+/**
+ * Set the Type ID match for this driver/device.  The register is a 32-bit
+ * value. The device must be stopped before calling this function.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Id_Check is type ID to be configured.
+ * @param Index is a index to which Type ID (1-4).
+ *
+ * @return
+ * - XST_SUCCESS if the MAC address was set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ *****************************************************************************/
+int XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((Index <= XEMACPS_MAX_TYPE_ID) && (Index > 0));
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
+		return (XST_DEVICE_IS_STARTED);
+	}
+
+	/* Index ranges 1 to 4, for offset calculation is 0 to 3. */
+	Index--;
+
+	/* Set the ID bits in MATCHx register */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   (XEMACPS_MATCH1_OFFSET + (Index * 4)), Id_Check);
+
+	return (XST_SUCCESS);
+}
+
+/*****************************************************************************/
+/**
+ * Set options for the driver/device. The driver should be stopped with
+ * XEmacPs_Stop() before changing options.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Options are the options to set. Multiple options can be set by OR'ing
+ *        XTE_*_OPTIONS constants together. Options not specified are not
+ *        affected.
+ *
+ * @return
+ * - XST_SUCCESS if the options were set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ * @note
+ * See xemacps.h for a description of the available options.
+ *
+ *****************************************************************************/
+int XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options)
+{
+	u32 Reg;		/* Generic register contents */
+	u32 RegNetCfg;		/* Reflects original contents of NET_CONFIG */
+	u32 RegNewNetCfg;	/* Reflects new contents of NET_CONFIG */
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
+		return (XST_DEVICE_IS_STARTED);
+	}
+
+	/* Many of these options will change the NET_CONFIG registers.
+	 * To reduce the amount of IO to the device, group these options here
+	 * and change them all at once.
+	 */
+
+	/* Grab current register contents */
+	RegNetCfg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XEMACPS_NWCFG_OFFSET);
+	RegNewNetCfg = RegNetCfg;
+
+	/*
+	 * It is configured to max 1536.
+	 */
+	if (Options & XEMACPS_FRAME1536_OPTION) {
+		RegNewNetCfg |= (XEMACPS_NWCFG_1536RXEN_MASK);
+	}
+
+	/* Turn on VLAN packet only, only VLAN tagged will be accepted */
+	if (Options & XEMACPS_VLAN_OPTION) {
+		RegNewNetCfg |= XEMACPS_NWCFG_NVLANDISC_MASK;
+	}
+
+	/* Turn on FCS stripping on receive packets */
+	if (Options & XEMACPS_FCS_STRIP_OPTION) {
+		RegNewNetCfg |= XEMACPS_NWCFG_FCSREM_MASK;
+	}
+
+	/* Turn on length/type field checking on receive packets */
+	if (Options & XEMACPS_LENTYPE_ERR_OPTION) {
+		RegNewNetCfg |= XEMACPS_NWCFG_LENGTHERRDSCRD_MASK;
+	}
+
+	/* Turn on flow control */
+	if (Options & XEMACPS_FLOW_CONTROL_OPTION) {
+		RegNewNetCfg |= XEMACPS_NWCFG_PAUSEEN_MASK;
+	}
+
+	/* Turn on promiscuous frame filtering (all frames are received) */
+	if (Options & XEMACPS_PROMISC_OPTION) {
+		RegNewNetCfg |= XEMACPS_NWCFG_COPYALLEN_MASK;
+	}
+
+	/* Allow broadcast address reception */
+	if (Options & XEMACPS_BROADCAST_OPTION) {
+		RegNewNetCfg &= ~XEMACPS_NWCFG_BCASTDI_MASK;
+	}
+
+	/* Allow multicast address filtering */
+	if (Options & XEMACPS_MULTICAST_OPTION) {
+		RegNewNetCfg |= XEMACPS_NWCFG_MCASTHASHEN_MASK;
+	}
+
+	/* enable RX checksum offload */
+	if (Options & XEMACPS_RX_CHKSUM_ENABLE_OPTION) {
+		RegNewNetCfg |= XEMACPS_NWCFG_RXCHKSUMEN_MASK;
+	}
+
+	/* Officially change the NET_CONFIG registers if it needs to be
+	 * modified.
+	 */
+	if (RegNetCfg != RegNewNetCfg) {
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCFG_OFFSET, RegNewNetCfg);
+	}
+
+	/* Enable TX checksum offload */
+	if (Options & XEMACPS_TX_CHKSUM_ENABLE_OPTION) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_DMACR_OFFSET);
+		Reg |= XEMACPS_DMACR_TCPCKSUM_MASK;
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+					 XEMACPS_DMACR_OFFSET, Reg);
+	}
+
+	/* Enable transmitter */
+	if (Options & XEMACPS_TRANSMITTER_ENABLE_OPTION) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET);
+		Reg |= XEMACPS_NWCTRL_TXEN_MASK;
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCTRL_OFFSET, Reg);
+	}
+
+	/* Enable receiver */
+	if (Options & XEMACPS_RECEIVER_ENABLE_OPTION) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET);
+		Reg |= XEMACPS_NWCTRL_RXEN_MASK;
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCTRL_OFFSET, Reg);
+	}
+
+	/* The remaining options not handled here are managed elsewhere in the
+	 * driver. No register modifications are needed at this time. Reflecting
+	 * the option in InstancePtr->Options is good enough for now.
+	 */
+
+	/* Set options word to its new value */
+	InstancePtr->Options |= Options;
+
+	return (XST_SUCCESS);
+}
+
+
+/*****************************************************************************/
+/**
+ * Clear options for the driver/device
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Options are the options to clear. Multiple options can be cleared by
+ *        OR'ing XEMACPS_*_OPTIONS constants together. Options not specified
+ *        are not affected.
+ *
+ * @return
+ * - XST_SUCCESS if the options were set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ * @note
+ * See xemacps.h for a description of the available options.
+ *
+ *****************************************************************************/
+int XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options)
+{
+	u32 Reg;		/* Generic */
+	u32 RegNetCfg;		/* Reflects original contents of NET_CONFIG */
+	u32 RegNewNetCfg;	/* Reflects new contents of NET_CONFIG */
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
+		return (XST_DEVICE_IS_STARTED);
+	}
+
+	/* Many of these options will change the NET_CONFIG registers.
+	 * To reduce the amount of IO to the device, group these options here
+	 * and change them all at once.
+	 */
+
+	/* Grab current register contents */
+	RegNetCfg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XEMACPS_NWCFG_OFFSET);
+	RegNewNetCfg = RegNetCfg;
+
+	/* There is only RX configuration!?
+	 * It is configured in two different length, upto 1536 and 10240 bytes
+	 */
+	if (Options & XEMACPS_FRAME1536_OPTION) {
+		RegNewNetCfg &= ~XEMACPS_NWCFG_1536RXEN_MASK;
+	}
+
+	/* Turn off VLAN packet only */
+	if (Options & XEMACPS_VLAN_OPTION) {
+		RegNewNetCfg &= ~XEMACPS_NWCFG_NVLANDISC_MASK;
+	}
+
+	/* Turn off FCS stripping on receive packets */
+	if (Options & XEMACPS_FCS_STRIP_OPTION) {
+		RegNewNetCfg &= ~XEMACPS_NWCFG_FCSREM_MASK;
+	}
+
+	/* Turn off length/type field checking on receive packets */
+	if (Options & XEMACPS_LENTYPE_ERR_OPTION) {
+		RegNewNetCfg &= ~XEMACPS_NWCFG_LENGTHERRDSCRD_MASK;
+	}
+
+	/* Turn off flow control */
+	if (Options & XEMACPS_FLOW_CONTROL_OPTION) {
+		RegNewNetCfg &= ~XEMACPS_NWCFG_PAUSEEN_MASK;
+	}
+
+	/* Turn off promiscuous frame filtering (all frames are received) */
+	if (Options & XEMACPS_PROMISC_OPTION) {
+		RegNewNetCfg &= ~XEMACPS_NWCFG_COPYALLEN_MASK;
+	}
+
+	/* Disallow broadcast address filtering => broadcast reception */
+	if (Options & XEMACPS_BROADCAST_OPTION) {
+		RegNewNetCfg |= XEMACPS_NWCFG_BCASTDI_MASK;
+	}
+
+	/* Disallow multicast address filtering */
+	if (Options & XEMACPS_MULTICAST_OPTION) {
+		RegNewNetCfg &= ~XEMACPS_NWCFG_MCASTHASHEN_MASK;
+	}
+
+	/* Disable RX checksum offload */
+	if (Options & XEMACPS_RX_CHKSUM_ENABLE_OPTION) {
+		RegNewNetCfg &= ~XEMACPS_NWCFG_RXCHKSUMEN_MASK;
+	}
+
+	/* Officially change the NET_CONFIG registers if it needs to be
+	 * modified.
+	 */
+	if (RegNetCfg != RegNewNetCfg) {
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCFG_OFFSET, RegNewNetCfg);
+	}
+
+	/* Disable TX checksum offload */
+	if (Options & XEMACPS_TX_CHKSUM_ENABLE_OPTION) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_DMACR_OFFSET);
+		Reg &= ~XEMACPS_DMACR_TCPCKSUM_MASK;
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+					 XEMACPS_DMACR_OFFSET, Reg);
+	}
+
+	/* Disable transmitter */
+	if (Options & XEMACPS_TRANSMITTER_ENABLE_OPTION) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET);
+		Reg &= ~XEMACPS_NWCTRL_TXEN_MASK;
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCTRL_OFFSET, Reg);
+	}
+
+	/* Disable receiver */
+	if (Options & XEMACPS_RECEIVER_ENABLE_OPTION) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET);
+		Reg &= ~XEMACPS_NWCTRL_RXEN_MASK;
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCTRL_OFFSET, Reg);
+	}
+
+	/* The remaining options not handled here are managed elsewhere in the
+	 * driver. No register modifications are needed at this time. Reflecting
+	 * option in InstancePtr->Options is good enough for now.
+	 */
+
+	/* Set options word to its new value */
+	InstancePtr->Options &= ~Options;
+
+	return (XST_SUCCESS);
+}
+
+
+/*****************************************************************************/
+/**
+ * Get current option settings
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ *
+ * @return
+ * A bitmask of XTE_*_OPTION constants. Any bit set to 1 is to be interpreted
+ * as a set opion.
+ *
+ * @note
+ * See xemacps.h for a description of the available options.
+ *
+ *****************************************************************************/
+u32 XEmacPs_GetOptions(XEmacPs *InstancePtr)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	return (InstancePtr->Options);
+}
+
+
+/*****************************************************************************/
+/**
+ * Send a pause packet
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ *
+ * @return
+ * - XST_SUCCESS if pause frame transmission was initiated
+ * - XST_DEVICE_IS_STOPPED if the device has not been started.
+ *
+ *****************************************************************************/
+int XEmacPs_SendPausePacket(XEmacPs *InstancePtr)
+{
+	u32 Reg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Make sure device is ready for this operation */
+	if (InstancePtr->IsStarted != XIL_COMPONENT_IS_STARTED) {
+		return (XST_DEVICE_IS_STOPPED);
+	}
+
+	/* Send flow control frame */
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_NWCTRL_OFFSET);
+	Reg |= XEMACPS_NWCTRL_PAUSETX_MASK;
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_NWCTRL_OFFSET, Reg);
+	return (XST_SUCCESS);
+}
+
+/*****************************************************************************/
+/**
+ * XEmacPs_GetOperatingSpeed gets the current operating link speed. This may
+ * be the value set by XEmacPs_SetOperatingSpeed() or a hardware default.
+ *
+ * @param InstancePtr references the TEMAC channel on which to operate.
+ *
+ * @return XEmacPs_GetOperatingSpeed returns the link speed in units of
+ *         megabits per second.
+ *
+ * @note
+ *
+ *****************************************************************************/
+u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr)
+{
+	u32 Reg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_NWCFG_OFFSET);
+
+	if (Reg & XEMACPS_NWCFG_1000_MASK) {
+		return (1000);
+	} else {
+		if (Reg & XEMACPS_NWCFG_100_MASK) {
+			return (100);
+		} else {
+			return (10);
+		}
+	}
+}
+
+
+/*****************************************************************************/
+/**
+ * XEmacPs_SetOperatingSpeed sets the current operating link speed. For any
+ * traffic to be passed, this speed must match the current MII/GMII/SGMII/RGMII
+ * link speed.
+ *
+ * @param InstancePtr references the TEMAC channel on which to operate.
+ * @param Speed is the speed to set in units of Mbps. Valid values are 10, 100,
+ *        or 1000. XEmacPs_SetOperatingSpeed ignores invalid values.
+ *
+ * @note
+ *
+ *****************************************************************************/
+void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed)
+{
+        u32 Reg;
+
+        Xil_AssertVoid(InstancePtr != NULL);
+        Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+        Xil_AssertVoid((Speed == 10) || (Speed == 100) || (Speed == 1000));
+
+        Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_NWCFG_OFFSET);
+	Reg &= ~(XEMACPS_NWCFG_1000_MASK | XEMACPS_NWCFG_100_MASK);
+
+	switch (Speed) {
+	case 10:
+                break;
+
+        case 100:
+                Reg |= XEMACPS_NWCFG_100_MASK;
+                break;
+
+        case 1000:
+                Reg |= XEMACPS_NWCFG_1000_MASK;
+                break;
+
+        default:
+                return;
+        }
+
+        /* Set register and return */
+        XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+                XEMACPS_NWCFG_OFFSET, Reg);
+}
+
+
+/*****************************************************************************/
+/**
+ * Set the MDIO clock divisor.
+ *
+ * Calculating the divisor:
+ *
+ * 
+ *              f[HOSTCLK]
+ *   f[MDC] = -----------------
+ *            (1 + Divisor) * 2
+ * 

+ *
+ * where f[HOSTCLK] is the bus clock frequency in MHz, and f[MDC] is the
+ * MDIO clock frequency in MHz to the PHY. Typically, f[MDC] should not
+ * exceed 2.5 MHz. Some PHYs can tolerate faster speeds which means faster
+ * access. Here is the table to show values to generate MDC,
+ *
+ * 
+ * 000 : divide pclk by   8 (pclk up to  20 MHz)
+ * 001 : divide pclk by  16 (pclk up to  40 MHz)
+ * 010 : divide pclk by  32 (pclk up to  80 MHz)
+ * 011 : divide pclk by  48 (pclk up to 120 MHz)
+ * 100 : divide pclk by  64 (pclk up to 160 MHz)
+ * 101 : divide pclk by  96 (pclk up to 240 MHz)
+ * 110 : divide pclk by 128 (pclk up to 320 MHz)
+ * 111 : divide pclk by 224 (pclk up to 540 MHz)
+ * 

+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Divisor is the divisor to set. Range is 0b000 to 0b111.
+ *
+ *****************************************************************************/
+void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, XEmacPs_MdcDiv Divisor)
+{
+	u32 Reg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Divisor <= 0x7); /* only last three bits are valid */
+
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_NWCFG_OFFSET);
+	/* clear these three bits, could be done with mask */
+	Reg &= ~XEMACPS_NWCFG_MDCCLKDIV_MASK;
+
+	Reg |= (Divisor << XEMACPS_NWCFG_MDC_SHIFT_MASK);
+
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_NWCFG_OFFSET, Reg);
+
+}
+
+
+/*****************************************************************************/
+/**
+* Read the current value of the PHY register indicated by the PhyAddress and
+* the RegisterNum parameters. The MAC provides the driver with the ability to
+* talk to a PHY that adheres to the Media Independent Interface (MII) as
+* defined in the IEEE 802.3 standard.
+*
+* Prior to PHY access with this function, the user should have setup the MDIO
+* clock with XEmacPs_SetMdioDivisor().
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param PhyAddress is the address of the PHY to be read (supports multiple
+*        PHYs)
+* @param RegisterNum is the register number, 0-31, of the specific PHY register
+*        to read
+* @param PhyDataPtr is an output parameter, and points to a 16-bit buffer into
+*        which the current value of the register will be copied.
+*
+* @return
+*
+* - XST_SUCCESS if the PHY was read from successfully
+* - XST_EMAC_MII_BUSY if there is another PHY operation in progress
+*
+* @note
+*
+* This function is not thread-safe. The user must provide mutually exclusive
+* access to this function if there are to be multiple threads that can call it.
+*
+* There is the possibility that this function will not return if the hardware
+* is broken (i.e., it never sets the status bit indicating that the read is
+* done). If this is of concern to the user, the user should provide a mechanism
+* suitable to their needs for recovery.
+*
+* For the duration of this function, all host interface reads and writes are
+* blocked to the current XEmacPs instance.
+*
+******************************************************************************/
+int XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
+		     u32 RegisterNum, u16 *PhyDataPtr)
+{
+	u32 Mgtcr;
+	volatile u32 Ipisr;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	/* Make sure no other PHY operation is currently in progress */
+	if (!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_NWSR_OFFSET) &
+	      XEMACPS_NWSR_MDIOIDLE_MASK)) {
+		return (XST_EMAC_MII_BUSY);
+	}
+
+	/* Construct Mgtcr mask for the operation */
+	Mgtcr = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_R_MASK |
+		(PhyAddress << XEMACPS_PHYMNTNC_PHYAD_SHIFT_MASK) |
+		(RegisterNum << XEMACPS_PHYMNTNC_PHREG_SHIFT_MASK);
+
+	/* Write Mgtcr and wait for completion */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_PHYMNTNC_OFFSET, Mgtcr);
+
+	do {
+		Ipisr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XEMACPS_NWSR_OFFSET);
+	} while ((Ipisr & XEMACPS_NWSR_MDIOIDLE_MASK) == 0);
+
+	/* Read data */
+	*PhyDataPtr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_PHYMNTNC_OFFSET);
+
+	return (XST_SUCCESS);
+}
+
+
+/*****************************************************************************/
+/**
+* Write data to the specified PHY register. The Ethernet driver does not
+* require the device to be stopped before writing to the PHY.  Although it is
+* probably a good idea to stop the device, it is the responsibility of the
+* application to deem this necessary. The MAC provides the driver with the
+* ability to talk to a PHY that adheres to the Media Independent Interface
+* (MII) as defined in the IEEE 802.3 standard.
+*
+* Prior to PHY access with this function, the user should have setup the MDIO
+* clock with XEmacPs_SetMdioDivisor().
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param PhyAddress is the address of the PHY to be written (supports multiple
+*        PHYs)
+* @param RegisterNum is the register number, 0-31, of the specific PHY register
+*        to write
+* @param PhyData is the 16-bit value that will be written to the register
+*
+* @return
+*
+* - XST_SUCCESS if the PHY was written to successfully. Since there is no error
+*   status from the MAC on a write, the user should read the PHY to verify the
+*   write was successful.
+* - XST_EMAC_MII_BUSY if there is another PHY operation in progress
+*
+* @note
+*
+* This function is not thread-safe. The user must provide mutually exclusive
+* access to this function if there are to be multiple threads that can call it.
+*
+* There is the possibility that this function will not return if the hardware
+* is broken (i.e., it never sets the status bit indicating that the write is
+* done). If this is of concern to the user, the user should provide a mechanism
+* suitable to their needs for recovery.
+*
+* For the duration of this function, all host interface reads and writes are
+* blocked to the current XEmacPs instance.
+*
+******************************************************************************/
+int XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
+		      u32 RegisterNum, u16 PhyData)
+{
+	u32 Mgtcr;
+	volatile u32 Ipisr;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	/* Make sure no other PHY operation is currently in progress */
+	if (!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_NWSR_OFFSET) &
+	      XEMACPS_NWSR_MDIOIDLE_MASK)) {
+		return (XST_EMAC_MII_BUSY);
+	}
+
+	/* Construct Mgtcr mask for the operation */
+	Mgtcr = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_W_MASK |
+		(PhyAddress << XEMACPS_PHYMNTNC_PHYAD_SHIFT_MASK) |
+		(RegisterNum << XEMACPS_PHYMNTNC_PHREG_SHIFT_MASK) | PhyData;
+
+	/* Write Mgtcr and wait for completion */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_PHYMNTNC_OFFSET, Mgtcr);
+
+	do {
+		Ipisr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XEMACPS_NWSR_OFFSET);
+	} while ((Ipisr & XEMACPS_NWSR_MDIOIDLE_MASK) == 0);
+
+	return (XST_SUCCESS);
+}
+
+/*****************************************************************************/
+/**
+* API to update the Burst length in the DMACR register.
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param BLength is the length in bytes for the dma burst.
+*
+* @return None
+*
+******************************************************************************/
+void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, int BLength)
+{
+	u32 Reg;
+	u32 RegUpdateVal = 0;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid((BLength == XEMACPS_SINGLE_BURST) ||
+					(BLength == XEMACPS_4BYTE_BURST) ||
+					(BLength == XEMACPS_8BYTE_BURST) ||
+					(BLength == XEMACPS_16BYTE_BURST));
+
+	switch (BLength) {
+		case XEMACPS_SINGLE_BURST:
+			RegUpdateVal = XEMACPS_DMACR_SINGLE_AHB_BURST;
+			break;
+
+		case XEMACPS_4BYTE_BURST:
+			RegUpdateVal = XEMACPS_DMACR_INCR4_AHB_BURST;
+			break;
+
+		case XEMACPS_8BYTE_BURST:
+			RegUpdateVal = XEMACPS_DMACR_INCR8_AHB_BURST;
+			break;
+
+		case XEMACPS_16BYTE_BURST:
+			RegUpdateVal = XEMACPS_DMACR_INCR16_AHB_BURST;
+			break;
+
+		default:
+			break;
+	}
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XEMACPS_DMACR_OFFSET);
+
+	Reg &= (~XEMACPS_DMACR_BLENGTH_MASK);
+	Reg |= RegUpdateVal;
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
+																	Reg);
+}
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_g.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_g.c
new file mode 100644
index 000000000..f485ae6e2
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_g.c
@@ -0,0 +1,31 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSM.
+* Version: 
+* DO NOT EDIT.
+*
+*  v (64-bit)
+SW Build (by ) on 
+Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xemacps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XEmacPs_Config XEmacPs_ConfigTable[] =
+{
+	{
+		XPAR_PS7_ETHERNET_0_DEVICE_ID,
+		XPAR_PS7_ETHERNET_0_BASEADDR
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_hw.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_hw.c
new file mode 100644
index 000000000..0b6f47154
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_hw.c
@@ -0,0 +1,132 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_hw.c
+*
+* This file contains the implementation of the ethernet interface reset sequence
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.05a kpc  28/06/13 First release
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xemacps_hw.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* This function perform the reset sequence to the given emacps interface by 
+* configuring the appropriate control bits in the emacps specifc registers.
+* the emacps reset squence involves the following steps
+*	Disable all the interuupts 
+*	Clear the status registers
+*	Disable Rx and Tx engines
+*	Update the Tx and Rx descriptor queue registers with reset values
+*	Update the other relevant control registers with reset value
+*
+* @param   BaseAddress of the interface
+*
+* @return N/A
+*
+* @note 
+* This function will not modify the slcr registers that are relavant for 
+* emacps controller
+******************************************************************************/
+void XEmacPs_ResetHw(u32 BaseAddr)
+{
+	u32 RegVal = 0;
+
+	/* Disable the interrupts  */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_IDR_OFFSET,0x0);
+
+	/* Stop transmission,disable loopback and Stop tx and Rx engines */
+	RegVal = XEmacPs_ReadReg(BaseAddr,XEMACPS_NWCTRL_OFFSET);
+	RegVal &= ~(XEMACPS_NWCTRL_TXEN_MASK|
+				XEMACPS_NWCTRL_RXEN_MASK|
+				XEMACPS_NWCTRL_HALTTX_MASK|
+				XEMACPS_NWCTRL_LOOPEN_MASK);
+	/* Clear the statistic registers, flush the packets in DPRAM*/				
+	RegVal |= (XEMACPS_NWCTRL_STATCLR_MASK|
+				XEMACPS_NWCTRL_FLUSH_DPRAM_MASK);
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCTRL_OFFSET,RegVal);
+	/* Clear the interrupt status */					
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_ISR_OFFSET,XEMACPS_IXR_ALL_MASK);
+	/* Clear the tx status */						
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_TXSR_OFFSET,XEMACPS_TXSR_ERROR_MASK|
+									XEMACPS_TXSR_TXCOMPL_MASK|
+									XEMACPS_TXSR_TXGO_MASK);
+	/* Clear the rx status */							
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_RXSR_OFFSET,
+								XEMACPS_RXSR_FRAMERX_MASK);	
+	/* Clear the tx base address */							
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_TXQBASE_OFFSET,0x0);		
+	/* Clear the rx base address */						
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_RXQBASE_OFFSET,0x0);	
+	/* Update the network config register with reset value */						
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCFG_OFFSET,XEMACPS_NWCFG_RESET_MASK);
+	/* Update the hash address registers with reset value */	
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHL_OFFSET,0x0);			
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHH_OFFSET,0x0);
+}
+
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_hw.h
new file mode 100644
index 000000000..4ae27afd8
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_hw.h
@@ -0,0 +1,605 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_hw.h
+*
+* This header file contains identifiers and low-level driver functions (or
+* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device.
+* High-level driver functions are defined in xemacps.h.
+*
+* @note
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release.
+* 1.02a asa  11/05/12 Added hash defines for DMACR burst length configuration.
+* 1.05a kpc  28/06/13 Added XEmacPs_ResetHw function prototype
+* 1.06a asa  11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+*					  to 0x1fff. This fixes the CR#744902.
+* 

+*
+******************************************************************************/
+
+#ifndef XEMACPS_HW_H		/* prevent circular inclusions */
+#define XEMACPS_HW_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+#define XEMACPS_MAX_MAC_ADDR     4   /**< Maxmum number of mac address
+                                           supported */
+#define XEMACPS_MAX_TYPE_ID      4   /**< Maxmum number of type id supported */
+#define XEMACPS_BD_ALIGNMENT     4   /**< Minimum buffer descriptor alignment
+                                           on the local bus */
+#define XEMACPS_RX_BUF_ALIGNMENT 4   /**< Minimum buffer alignment when using
+                                           options that impose alignment
+                                           restrictions on the buffer data on
+                                           the local bus */
+
+/** @name Direction identifiers
+ *
+ *  These are used by several functions and callbacks that need
+ *  to specify whether an operation specifies a send or receive channel.
+ * @{
+ */
+#define XEMACPS_SEND        1	      /**< send direction */
+#define XEMACPS_RECV        2	      /**< receive direction */
+/*@}*/
+
+/**  @name MDC clock division
+ *  currently supporting 8, 16, 32, 48, 64, 96, 128, 224.
+ * @{
+ */
+typedef enum { MDC_DIV_8 = 0, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
+	MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
+} XEmacPs_MdcDiv;
+
+/*@}*/
+
+#define XEMACPS_RX_BUF_SIZE 1536 /**< Specify the receive buffer size in
+                                       bytes, 64, 128, ... 10240 */
+#define XEMACPS_RX_BUF_UNIT   64 /**< Number of receive buffer bytes as a
+                                       unit, this is HW setup */
+
+#define XEMACPS_MAX_RXBD     128 /**< Size of RX buffer descriptor queues */
+#define XEMACPS_MAX_TXBD     128 /**< Size of TX buffer descriptor queues */
+
+#define XEMACPS_MAX_HASH_BITS 64 /**< Maximum value for hash bits. 2**6 */
+
+/* Register offset definitions. Unless otherwise noted, register access is
+ * 32 bit. Names are self explained here.
+ */
+
+#define XEMACPS_NWCTRL_OFFSET        0x00000000 /**< Network Control reg */
+#define XEMACPS_NWCFG_OFFSET         0x00000004 /**< Network Config reg */
+#define XEMACPS_NWSR_OFFSET          0x00000008 /**< Network Status reg */
+
+#define XEMACPS_DMACR_OFFSET         0x00000010 /**< DMA Control reg */
+#define XEMACPS_TXSR_OFFSET          0x00000014 /**< TX Status reg */
+#define XEMACPS_RXQBASE_OFFSET       0x00000018 /**< RX Q Base address reg */
+#define XEMACPS_TXQBASE_OFFSET       0x0000001C /**< TX Q Base address reg */
+#define XEMACPS_RXSR_OFFSET          0x00000020 /**< RX Status reg */
+
+#define XEMACPS_ISR_OFFSET           0x00000024 /**< Interrupt Status reg */
+#define XEMACPS_IER_OFFSET           0x00000028 /**< Interrupt Enable reg */
+#define XEMACPS_IDR_OFFSET           0x0000002C /**< Interrupt Disable reg */
+#define XEMACPS_IMR_OFFSET           0x00000030 /**< Interrupt Mask reg */
+
+#define XEMACPS_PHYMNTNC_OFFSET      0x00000034 /**< Phy Maintaince reg */
+#define XEMACPS_RXPAUSE_OFFSET       0x00000038 /**< RX Pause Time reg */
+#define XEMACPS_TXPAUSE_OFFSET       0x0000003C /**< TX Pause Time reg */
+
+#define XEMACPS_HASHL_OFFSET         0x00000080 /**< Hash Low address reg */
+#define XEMACPS_HASHH_OFFSET         0x00000084 /**< Hash High address reg */
+
+#define XEMACPS_LADDR1L_OFFSET       0x00000088 /**< Specific1 addr low reg */
+#define XEMACPS_LADDR1H_OFFSET       0x0000008C /**< Specific1 addr high reg */
+#define XEMACPS_LADDR2L_OFFSET       0x00000090 /**< Specific2 addr low reg */
+#define XEMACPS_LADDR2H_OFFSET       0x00000094 /**< Specific2 addr high reg */
+#define XEMACPS_LADDR3L_OFFSET       0x00000098 /**< Specific3 addr low reg */
+#define XEMACPS_LADDR3H_OFFSET       0x0000009C /**< Specific3 addr high reg */
+#define XEMACPS_LADDR4L_OFFSET       0x000000A0 /**< Specific4 addr low reg */
+#define XEMACPS_LADDR4H_OFFSET       0x000000A4 /**< Specific4 addr high reg */
+
+#define XEMACPS_MATCH1_OFFSET        0x000000A8 /**< Type ID1 Match reg */
+#define XEMACPS_MATCH2_OFFSET        0x000000AC /**< Type ID2 Match reg */
+#define XEMACPS_MATCH3_OFFSET        0x000000B0 /**< Type ID3 Match reg */
+#define XEMACPS_MATCH4_OFFSET        0x000000B4 /**< Type ID4 Match reg */
+
+#define XEMACPS_STRETCH_OFFSET       0x000000BC /**< IPG Stretch reg */
+
+#define XEMACPS_OCTTXL_OFFSET        0x00000100 /**< Octects transmitted Low
+                                                      reg */
+#define XEMACPS_OCTTXH_OFFSET        0x00000104 /**< Octects transmitted High
+                                                      reg */
+
+#define XEMACPS_TXCNT_OFFSET         0x00000108 /**< Error-free Frmaes
+                                                      transmitted counter */
+#define XEMACPS_TXBCCNT_OFFSET       0x0000010C /**< Error-free Broadcast
+                                                      Frames counter*/
+#define XEMACPS_TXMCCNT_OFFSET       0x00000110 /**< Error-free Multicast
+                                                      Frame counter */
+#define XEMACPS_TXPAUSECNT_OFFSET    0x00000114 /**< Pause Frames Transmitted
+                                                      Counter */
+#define XEMACPS_TX64CNT_OFFSET       0x00000118 /**< Error-free 64 byte Frames
+                                                      Transmitted counter */
+#define XEMACPS_TX65CNT_OFFSET       0x0000011C /**< Error-free 65-127 byte
+                                                      Frames Transmitted
+                                                      counter */
+#define XEMACPS_TX128CNT_OFFSET      0x00000120 /**< Error-free 128-255 byte
+                                                      Frames Transmitted
+                                                      counter*/
+#define XEMACPS_TX256CNT_OFFSET      0x00000124 /**< Error-free 256-511 byte
+                                                      Frames transmitted
+                                                      counter */
+#define XEMACPS_TX512CNT_OFFSET      0x00000128 /**< Error-free 512-1023 byte
+                                                      Frames transmitted
+                                                      counter */
+#define XEMACPS_TX1024CNT_OFFSET     0x0000012C /**< Error-free 1024-1518 byte
+                                                      Frames transmitted
+                                                      counter */
+#define XEMACPS_TX1519CNT_OFFSET     0x00000130 /**< Error-free larger than
+                                                      1519 byte Frames
+                                                      transmitted counter */
+#define XEMACPS_TXURUNCNT_OFFSET     0x00000134 /**< TX under run error
+                                                      counter */
+
+#define XEMACPS_SNGLCOLLCNT_OFFSET   0x00000138 /**< Single Collision Frame
+                                                      Counter */
+#define XEMACPS_MULTICOLLCNT_OFFSET  0x0000013C /**< Multiple Collision Frame
+                                                      Counter */
+#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140 /**< Excessive Collision Frame
+                                                      Counter */
+#define XEMACPS_LATECOLLCNT_OFFSET   0x00000144 /**< Late Collision Frame
+                                                      Counter */
+#define XEMACPS_TXDEFERCNT_OFFSET    0x00000148 /**< Deferred Transmission
+                                                      Frame Counter */
+#define XEMACPS_TXCSENSECNT_OFFSET   0x0000014C /**< Transmit Carrier Sense
+                                                      Error Counter */
+
+#define XEMACPS_OCTRXL_OFFSET        0x00000150 /**< Octects Received register
+                                                      Low */
+#define XEMACPS_OCTRXH_OFFSET        0x00000154 /**< Octects Received register
+                                                      High */
+
+#define XEMACPS_RXCNT_OFFSET         0x00000158 /**< Error-free Frames
+                                                      Received Counter */
+#define XEMACPS_RXBROADCNT_OFFSET    0x0000015C /**< Error-free Broadcast
+                                                      Frames Received Counter */
+#define XEMACPS_RXMULTICNT_OFFSET    0x00000160 /**< Error-free Multicast
+                                                      Frames Received Counter */
+#define XEMACPS_RXPAUSECNT_OFFSET    0x00000164 /**< Pause Frames
+                                                      Received Counter */
+#define XEMACPS_RX64CNT_OFFSET       0x00000168 /**< Error-free 64 byte Frames
+                                                      Received Counter */
+#define XEMACPS_RX65CNT_OFFSET       0x0000016C /**< Error-free 65-127 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX128CNT_OFFSET      0x00000170 /**< Error-free 128-255 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX256CNT_OFFSET      0x00000174 /**< Error-free 256-512 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX512CNT_OFFSET      0x00000178 /**< Error-free 512-1023 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX1024CNT_OFFSET     0x0000017C /**< Error-free 1024-1518 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX1519CNT_OFFSET     0x00000180 /**< Error-free 1519-max byte
+                                                      Frames Received Counter */
+#define XEMACPS_RXUNDRCNT_OFFSET     0x00000184 /**< Undersize Frames Received
+                                                      Counter */
+#define XEMACPS_RXOVRCNT_OFFSET      0x00000188 /**< Oversize Frames Received
+                                                      Counter */
+#define XEMACPS_RXJABCNT_OFFSET      0x0000018C /**< Jabbers Received
+                                                      Counter */
+#define XEMACPS_RXFCSCNT_OFFSET      0x00000190 /**< Frame Check Sequence
+                                                      Error Counter */
+#define XEMACPS_RXLENGTHCNT_OFFSET   0x00000194 /**< Length Field Error
+                                                      Counter */
+#define XEMACPS_RXSYMBCNT_OFFSET     0x00000198 /**< Symbol Error Counter */
+#define XEMACPS_RXALIGNCNT_OFFSET    0x0000019C /**< Alignment Error Counter */
+#define XEMACPS_RXRESERRCNT_OFFSET   0x000001A0 /**< Receive Resource Error
+                                                      Counter */
+#define XEMACPS_RXORCNT_OFFSET       0x000001A4 /**< Receive Overrun Counter */
+#define XEMACPS_RXIPCCNT_OFFSET      0x000001A8 /**< IP header Checksum Error
+                                                      Counter */
+#define XEMACPS_RXTCPCCNT_OFFSET     0x000001AC /**< TCP Checksum Error
+                                                      Counter */
+#define XEMACPS_RXUDPCCNT_OFFSET     0x000001B0 /**< UDP Checksum Error
+                                                      Counter */
+#define XEMACPS_LAST_OFFSET          0x000001B4 /**< Last statistic counter
+						      offset, for clearing */
+
+#define XEMACPS_1588_SEC_OFFSET      0x000001D0 /**< 1588 second counter */
+#define XEMACPS_1588_NANOSEC_OFFSET  0x000001D4 /**< 1588 nanosecond counter */
+#define XEMACPS_1588_ADJ_OFFSET      0x000001D8 /**< 1588 nanosecond
+						      adjustment counter */
+#define XEMACPS_1588_INC_OFFSET      0x000001DC /**< 1588 nanosecond
+						      increment counter */
+#define XEMACPS_PTP_TXSEC_OFFSET     0x000001E0 /**< 1588 PTP transmit second
+						      counter */
+#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4 /**< 1588 PTP transmit
+						      nanosecond counter */
+#define XEMACPS_PTP_RXSEC_OFFSET     0x000001E8 /**< 1588 PTP receive second
+						      counter */
+#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001EC /**< 1588 PTP receive
+						      nanosecond counter */
+#define XEMACPS_PTPP_TXSEC_OFFSET    0x000001F0 /**< 1588 PTP peer transmit
+						      second counter */
+#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4 /**< 1588 PTP peer transmit
+						      nanosecond counter */
+#define XEMACPS_PTPP_RXSEC_OFFSET    0x000001F8 /**< 1588 PTP peer receive
+						      second counter */
+#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FC /**< 1588 PTP peer receive
+						      nanosecond counter */
+
+/* Define some bit positions for registers. */
+
+/** @name network control register bit definitions
+ * @{
+ */
+#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK	0x00040000 /**< Flush a packet from
+							Rx SRAM */
+#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800 /**< Transmit zero quantum
+                                                         pause frame */
+#define XEMACPS_NWCTRL_PAUSETX_MASK     0x00000800 /**< Transmit pause frame */
+#define XEMACPS_NWCTRL_HALTTX_MASK      0x00000400 /**< Halt transmission
+                                                         after current frame */
+#define XEMACPS_NWCTRL_STARTTX_MASK     0x00000200 /**< Start tx (tx_go) */
+
+#define XEMACPS_NWCTRL_STATWEN_MASK     0x00000080 /**< Enable writing to
+                                                         stat counters */
+#define XEMACPS_NWCTRL_STATINC_MASK     0x00000040 /**< Increment statistic
+                                                         registers */
+#define XEMACPS_NWCTRL_STATCLR_MASK     0x00000020 /**< Clear statistic
+                                                         registers */
+#define XEMACPS_NWCTRL_MDEN_MASK        0x00000010 /**< Enable MDIO port */
+#define XEMACPS_NWCTRL_TXEN_MASK        0x00000008 /**< Enable transmit */
+#define XEMACPS_NWCTRL_RXEN_MASK        0x00000004 /**< Enable receive */
+#define XEMACPS_NWCTRL_LOOPEN_MASK      0x00000002 /**< local loopback */
+/*@}*/
+
+/** @name network configuration register bit definitions
+ * @{
+ */
+#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000 /**< disable rejection of
+                                                        non-standard preamble */
+#define XEMACPS_NWCFG_IPDSTRETCH_MASK  0x10000000 /**< enable transmit IPG */
+#define XEMACPS_NWCFG_FCSIGNORE_MASK   0x04000000 /**< disable rejection of
+                                                        FCS error */
+#define XEMACPS_NWCFG_HDRXEN_MASK      0x02000000 /**< RX half duplex */
+#define XEMACPS_NWCFG_RXCHKSUMEN_MASK  0x01000000 /**< enable RX checksum
+                                                        offload */
+#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000 /**< Do not copy pause
+                                                        Frames to memory */
+#define XEMACPS_NWCFG_MDC_SHIFT_MASK   18	   /**< shift bits for MDC */
+#define XEMACPS_NWCFG_MDCCLKDIV_MASK   0x001C0000 /**< MDC Mask PCLK divisor */
+#define XEMACPS_NWCFG_FCSREM_MASK      0x00020000 /**< Discard FCS from
+                                                        received frames */
+#define XEMACPS_NWCFG_LENGTHERRDSCRD_MASK 0x00010000
+/**< RX length error discard */
+#define XEMACPS_NWCFG_RXOFFS_MASK      0x0000C000 /**< RX buffer offset */
+#define XEMACPS_NWCFG_PAUSEEN_MASK     0x00002000 /**< Enable pause RX */
+#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000 /**< Retry test */
+#define XEMACPS_NWCFG_EXTADDRMATCHEN_MASK 0x00000200
+/**< External address match enable */
+#define XEMACPS_NWCFG_1000_MASK        0x00000400 /**< 1000 Mbps */
+#define XEMACPS_NWCFG_1536RXEN_MASK    0x00000100 /**< Enable 1536 byte
+                                                        frames reception */
+#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080 /**< Receive unicast hash
+                                                        frames */
+#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040 /**< Receive multicast hash
+                                                        frames */
+#define XEMACPS_NWCFG_BCASTDI_MASK     0x00000020 /**< Do not receive
+                                                        broadcast frames */
+#define XEMACPS_NWCFG_COPYALLEN_MASK   0x00000010 /**< Copy all frames */
+#define XEMACPS_NWCFG_JUMBO_MASK       0x00000008 /**< Jumbo frames */
+#define XEMACPS_NWCFG_NVLANDISC_MASK   0x00000004 /**< Receive only VLAN
+                                                        frames */
+#define XEMACPS_NWCFG_FDEN_MASK        0x00000002 /**< full duplex */
+#define XEMACPS_NWCFG_100_MASK         0x00000001 /**< 100 Mbps */
+#define XEMACPS_NWCFG_RESET_MASK       0x00080000 /**< reset value */
+/*@}*/
+
+/** @name network status register bit definitaions
+ * @{
+ */
+#define XEMACPS_NWSR_MDIOIDLE_MASK     0x00000004 /**< PHY management idle */
+#define XEMACPS_NWSR_MDIO_MASK         0x00000002 /**< Status of mdio_in */
+/*@}*/
+
+
+/** @name MAC address register word 1 mask
+ * @{
+ */
+#define XEMACPS_LADDR_MACH_MASK        0x0000FFFF /**< Address bits[47:32]
+                                                      bit[31:0] are in BOTTOM */
+/*@}*/
+
+
+/** @name DMA control register bit definitions
+ * @{
+ */
+#define XEMACPS_DMACR_RXBUF_MASK		0x00FF0000 /**< Mask bit for RX buffer
+													size */
+#define XEMACPS_DMACR_RXBUF_SHIFT 		16	/**< Shift bit for RX buffer
+												size */
+#define XEMACPS_DMACR_TCPCKSUM_MASK		0x00000800 /**< enable/disable TX
+													    checksum offload */
+#define XEMACPS_DMACR_TXSIZE_MASK		0x00000400 /**< TX buffer memory size */
+#define XEMACPS_DMACR_RXSIZE_MASK		0x00000300 /**< RX buffer memory size */
+#define XEMACPS_DMACR_ENDIAN_MASK		0x00000080 /**< endian configuration */
+#define XEMACPS_DMACR_BLENGTH_MASK		0x0000001F /**< buffer burst length */
+#define XEMACPS_DMACR_SINGLE_AHB_BURST	0x00000001 /**< single AHB bursts */
+#define XEMACPS_DMACR_INCR4_AHB_BURST	0x00000004 /**< 4 bytes AHB bursts */
+#define XEMACPS_DMACR_INCR8_AHB_BURST	0x00000008 /**< 8 bytes AHB bursts */
+#define XEMACPS_DMACR_INCR16_AHB_BURST	0x00000010 /**< 16 bytes AHB bursts */
+/*@}*/
+
+/** @name transmit status register bit definitions
+ * @{
+ */
+#define XEMACPS_TXSR_HRESPNOK_MASK    0x00000100 /**< Transmit hresp not OK */
+#define XEMACPS_TXSR_URUN_MASK        0x00000040 /**< Transmit underrun */
+#define XEMACPS_TXSR_TXCOMPL_MASK     0x00000020 /**< Transmit completed OK */
+#define XEMACPS_TXSR_BUFEXH_MASK      0x00000010 /**< Transmit buffs exhausted
+                                                       mid frame */
+#define XEMACPS_TXSR_TXGO_MASK        0x00000008 /**< Status of go flag */
+#define XEMACPS_TXSR_RXOVR_MASK       0x00000004 /**< Retry limit exceeded */
+#define XEMACPS_TXSR_FRAMERX_MASK     0x00000002 /**< Collision tx frame */
+#define XEMACPS_TXSR_USEDREAD_MASK    0x00000001 /**< TX buffer used bit set */
+
+#define XEMACPS_TXSR_ERROR_MASK      (XEMACPS_TXSR_HRESPNOK_MASK | \
+                                       XEMACPS_TXSR_URUN_MASK | \
+                                       XEMACPS_TXSR_BUFEXH_MASK | \
+                                       XEMACPS_TXSR_RXOVR_MASK | \
+                                       XEMACPS_TXSR_FRAMERX_MASK | \
+                                       XEMACPS_TXSR_USEDREAD_MASK)
+/*@}*/
+
+/**
+ * @name receive status register bit definitions
+ * @{
+ */
+#define XEMACPS_RXSR_HRESPNOK_MASK    0x00000008 /**< Receive hresp not OK */
+#define XEMACPS_RXSR_RXOVR_MASK       0x00000004 /**< Receive overrun */
+#define XEMACPS_RXSR_FRAMERX_MASK     0x00000002 /**< Frame received OK */
+#define XEMACPS_RXSR_BUFFNA_MASK      0x00000001 /**< RX buffer used bit set */
+
+#define XEMACPS_RXSR_ERROR_MASK      (XEMACPS_RXSR_HRESPNOK_MASK | \
+                                       XEMACPS_RXSR_RXOVR_MASK | \
+                                       XEMACPS_RXSR_BUFFNA_MASK)
+/*@}*/
+
+/**
+ * @name interrupts bit definitions
+ * Bits definitions are same in XEMACPS_ISR_OFFSET,
+ * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
+ * @{
+ */
+#define XEMACPS_IXR_PTPPSTX_MASK    0x02000000 /**< PTP Psync transmitted */
+#define XEMACPS_IXR_PTPPDRTX_MASK   0x01000000 /**< PTP Pdelay_req
+						     transmitted */
+#define XEMACPS_IXR_PTPSTX_MASK     0x00800000 /**< PTP Sync transmitted */
+#define XEMACPS_IXR_PTPDRTX_MASK    0x00400000 /**< PTP Delay_req transmitted
+						*/
+#define XEMACPS_IXR_PTPPSRX_MASK    0x00200000 /**< PTP Psync received */
+#define XEMACPS_IXR_PTPPDRRX_MASK   0x00100000 /**< PTP Pdelay_req received */
+#define XEMACPS_IXR_PTPSRX_MASK     0x00080000 /**< PTP Sync received */
+#define XEMACPS_IXR_PTPDRRX_MASK    0x00040000 /**< PTP Delay_req received */
+#define XEMACPS_IXR_PAUSETX_MASK    0x00004000	/**< Pause frame transmitted */
+#define XEMACPS_IXR_PAUSEZERO_MASK  0x00002000	/**< Pause time has reached
+                                                     zero */
+#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000	/**< Pause frame received */
+#define XEMACPS_IXR_HRESPNOK_MASK   0x00000800	/**< hresp not ok */
+#define XEMACPS_IXR_RXOVR_MASK      0x00000400	/**< Receive overrun occurred */
+#define XEMACPS_IXR_TXCOMPL_MASK    0x00000080	/**< Frame transmitted ok */
+#define XEMACPS_IXR_TXEXH_MASK      0x00000040	/**< Transmit err occurred or
+                                                     no buffers*/
+#define XEMACPS_IXR_RETRY_MASK      0x00000020	/**< Retry limit exceeded */
+#define XEMACPS_IXR_URUN_MASK       0x00000010	/**< Transmit underrun */
+#define XEMACPS_IXR_TXUSED_MASK     0x00000008	/**< Tx buffer used bit read */
+#define XEMACPS_IXR_RXUSED_MASK     0x00000004	/**< Rx buffer used bit read */
+#define XEMACPS_IXR_FRAMERX_MASK    0x00000002	/**< Frame received ok */
+#define XEMACPS_IXR_MGMNT_MASK      0x00000001	/**< PHY management complete */
+#define XEMACPS_IXR_ALL_MASK        0x00007FFF	/**< Everything! */
+
+#define XEMACPS_IXR_TX_ERR_MASK    (XEMACPS_IXR_TXEXH_MASK |         \
+                                     XEMACPS_IXR_RETRY_MASK |         \
+                                     XEMACPS_IXR_URUN_MASK  |         \
+                                     XEMACPS_IXR_TXUSED_MASK)
+
+
+#define XEMACPS_IXR_RX_ERR_MASK    (XEMACPS_IXR_HRESPNOK_MASK |      \
+                                     XEMACPS_IXR_RXUSED_MASK |        \
+                                     XEMACPS_IXR_RXOVR_MASK)
+
+/*@}*/
+
+/** @name PHY Maintenance bit definitions
+ * @{
+ */
+#define XEMACPS_PHYMNTNC_OP_MASK    0x40020000	/**< operation mask bits */
+#define XEMACPS_PHYMNTNC_OP_R_MASK  0x20000000	/**< read operation */
+#define XEMACPS_PHYMNTNC_OP_W_MASK  0x10000000	/**< write operation */
+#define XEMACPS_PHYMNTNC_ADDR_MASK  0x0F800000	/**< Address bits */
+#define XEMACPS_PHYMNTNC_REG_MASK   0x007C0000	/**< register bits */
+#define XEMACPS_PHYMNTNC_DATA_MASK  0x00000FFF	/**< data bits */
+#define XEMACPS_PHYMNTNC_PHYAD_SHIFT_MASK   23	/**< Shift bits for PHYAD */
+#define XEMACPS_PHYMNTNC_PHREG_SHIFT_MASK   18	/**< Shift bits for PHREG */
+/*@}*/
+
+/* Transmit buffer descriptor status words offset
+ * @{
+ */
+#define XEMACPS_BD_ADDR_OFFSET  0x00000000 /**< word 0/addr of BDs */
+#define XEMACPS_BD_STAT_OFFSET  0x00000004 /**< word 1/status of BDs */
+/*
+ * @}
+ */
+
+/* Transmit buffer descriptor status words bit positions.
+ * Transmit buffer descriptor consists of two 32-bit registers,
+ * the first - word0 contains a 32-bit address pointing to the location of
+ * the transmit data.
+ * The following register - word1, consists of various information to control
+ * the XEmacPs transmit process.  After transmit, this is updated with status
+ * information, whether the frame was transmitted OK or why it had failed.
+ * @{
+ */
+#define XEMACPS_TXBUF_USED_MASK  0x80000000 /**< Used bit. */
+#define XEMACPS_TXBUF_WRAP_MASK  0x40000000 /**< Wrap bit, last descriptor */
+#define XEMACPS_TXBUF_RETRY_MASK 0x20000000 /**< Retry limit exceeded */
+#define XEMACPS_TXBUF_URUN_MASK  0x10000000 /**< Transmit underrun occurred */
+#define XEMACPS_TXBUF_EXH_MASK   0x08000000 /**< Buffers exhausted */
+#define XEMACPS_TXBUF_TCP_MASK   0x04000000 /**< Late collision. */
+#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000 /**< No CRC */
+#define XEMACPS_TXBUF_LAST_MASK  0x00008000 /**< Last buffer */
+#define XEMACPS_TXBUF_LEN_MASK   0x00003FFF /**< Mask for length field */
+/*
+ * @}
+ */
+
+/* Receive buffer descriptor status words bit positions.
+ * Receive buffer descriptor consists of two 32-bit registers,
+ * the first - word0 contains a 32-bit word aligned address pointing to the
+ * address of the buffer. The lower two bits make up the wrap bit indicating
+ * the last descriptor and the ownership bit to indicate it has been used by
+ * the XEmacPs.
+ * The following register - word1, contains status information regarding why
+ * the frame was received (the filter match condition) as well as other
+ * useful info.
+ * @{
+ */
+#define XEMACPS_RXBUF_BCAST_MASK     0x80000000 /**< Broadcast frame */
+#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000 /**< Multicast hashed frame */
+#define XEMACPS_RXBUF_UNIHASH_MASK   0x20000000 /**< Unicast hashed frame */
+#define XEMACPS_RXBUF_EXH_MASK       0x08000000 /**< buffer exhausted */
+#define XEMACPS_RXBUF_AMATCH_MASK    0x06000000 /**< Specific address
+                                                      matched */
+#define XEMACPS_RXBUF_IDFOUND_MASK   0x01000000 /**< Type ID matched */
+#define XEMACPS_RXBUF_IDMATCH_MASK   0x00C00000 /**< ID matched mask */
+#define XEMACPS_RXBUF_VLAN_MASK      0x00200000 /**< VLAN tagged */
+#define XEMACPS_RXBUF_PRI_MASK       0x00100000 /**< Priority tagged */
+#define XEMACPS_RXBUF_VPRI_MASK      0x000E0000 /**< Vlan priority */
+#define XEMACPS_RXBUF_CFI_MASK       0x00010000 /**< CFI frame */
+#define XEMACPS_RXBUF_EOF_MASK       0x00008000 /**< End of frame. */
+#define XEMACPS_RXBUF_SOF_MASK       0x00004000 /**< Start of frame. */
+#define XEMACPS_RXBUF_LEN_MASK       0x00001FFF /**< Mask for length field */
+
+#define XEMACPS_RXBUF_WRAP_MASK      0x00000002 /**< Wrap bit, last BD */
+#define XEMACPS_RXBUF_NEW_MASK       0x00000001 /**< Used bit.. */
+#define XEMACPS_RXBUF_ADD_MASK       0xFFFFFFFC /**< Mask for address */
+/*
+ * @}
+ */
+
+/*
+ * Define appropriate I/O access method to mempry mapped I/O or other
+ * intarfce if necessary.
+ */
+
+#define XEmacPs_In32  Xil_In32
+#define XEmacPs_Out32 Xil_Out32
+
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param    BaseAddress is the base address of the device
+* @param    RegOffset is the register offset to be read
+*
+* @return   The 32-bit value of the register
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XEmacPs_ReadReg(BaseAddress, RegOffset) \
+    XEmacPs_In32((BaseAddress) + (RegOffset))
+
+
+/****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param    BaseAddress is the base address of the device
+* @param    RegOffset is the register offset to be written
+* @param    Data is the 32-bit value to write to the register
+*
+* @return   None.
+*
+* @note
+* C-style signature:
+*    void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset,
+*         u32 Data)
+*
+*****************************************************************************/
+#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \
+    XEmacPs_Out32((BaseAddress) + (RegOffset), (Data))
+
+/************************** Function Prototypes *****************************/
+/*
+ * Perform reset operation to the emacps interface
+ */
+void XEmacPs_ResetHw(u32 BaseAddr);
+
+#ifdef __cplusplus
+  }
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_intr.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_intr.c
new file mode 100644
index 000000000..a3b920848
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_intr.c
@@ -0,0 +1,229 @@
+/* $Id: xemacps_intr.c,v 1.1.2.1 2011/01/20 03:39:02 sadanan Exp $ */
+/******************************************************************************
+*
+* (c) Copyright 2010 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_intr.c
+*
+* Functions in this file implement general purpose interrupt processing related
+* functionality. See xemacps.h for a detailed description of the driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release
+* 1.03a asa  01/24/13 Fix for CR #692702 which updates error handling for
+*		      Rx errors. Under heavy Rx traffic, there will be a large
+*		      number of errors related to receive buffer not available.
+*		      Because of a HW bug (SI #692601), under such heavy errors,
+*		      the Rx data path can become unresponsive. To reduce the
+*		      probabilities for hitting this HW bug, the SW writes to
+*		      bit 18 to flush a packet from Rx DPRAM immediately. The
+*		      changes for it are done in the function
+*		      XEmacPs_IntrHandler.
+* 

+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+ * Install an asynchronious handler function for the given HandlerType:
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param HandlerType indicates what interrupt handler type is.
+ *        XEMACPS_HANDLER_DMASEND, XEMACPS_HANDLER_DMARECV and
+ *        XEMACPS_HANDLER_ERROR.
+ * @param FuncPtr is the pointer to the callback function
+ * @param CallBackRef is the upper layer callback reference passed back when
+ *        when the callback function is invoked.
+ *
+ * @return
+ *
+ * None.
+ *
+ * @note
+ * There is no assert on the CallBackRef since the driver doesn't know what
+ * it is.
+ *
+ *****************************************************************************/
+int XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
+			void *FuncPtr, void *CallBackRef)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(FuncPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	switch (HandlerType) {
+	case XEMACPS_HANDLER_DMASEND:
+		InstancePtr->SendHandler = (XEmacPs_Handler) FuncPtr;
+		InstancePtr->SendRef = CallBackRef;
+		break;
+	case XEMACPS_HANDLER_DMARECV:
+		InstancePtr->RecvHandler = (XEmacPs_Handler) FuncPtr;
+		InstancePtr->RecvRef = CallBackRef;
+		break;
+	case XEMACPS_HANDLER_ERROR:
+		InstancePtr->ErrorHandler = (XEmacPs_ErrHandler) FuncPtr;
+		InstancePtr->ErrorRef = CallBackRef;
+		break;
+	default:
+		return (XST_INVALID_PARAM);
+	}
+	return (XST_SUCCESS);
+}
+
+/*****************************************************************************/
+/**
+* Master interrupt handler for EMAC driver. This routine will query the
+* status of the device, bump statistics, and invoke user callbacks.
+*
+* This routine must be connected to an interrupt controller using OS/BSP
+* specific methods.
+*
+* @param XEmacPsPtr is a pointer to the XEMACPS instance that has caused the
+*        interrupt.
+*
+******************************************************************************/
+void XEmacPs_IntrHandler(void *XEmacPsPtr)
+{
+	u32 RegISR;
+	u32 RegSR;
+	u32 RegCtrl;
+	XEmacPs *InstancePtr = (XEmacPs *) XEmacPsPtr;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* This ISR will try to handle as many interrupts as it can in a single
+	 * call. However, in most of the places where the user's error handler
+         * is called, this ISR exits because it is expected that the user will
+         * reset the device in nearly all instances.
+	 */
+	RegISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_ISR_OFFSET);
+
+	/* Clear the interrupt status register */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
+			   RegISR);
+
+	/* Receive complete interrupt */
+	if (RegISR & (XEMACPS_IXR_FRAMERX_MASK)) {
+		/* Clear RX status register RX complete indication but preserve
+		 * error bits if there is any */
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_RXSR_OFFSET,
+				   XEMACPS_RXSR_FRAMERX_MASK |
+				   XEMACPS_RXSR_BUFFNA_MASK);
+		InstancePtr->RecvHandler(InstancePtr->RecvRef);
+	}
+
+	/* Transmit complete interrupt */
+	if (RegISR & (XEMACPS_IXR_TXCOMPL_MASK)) {
+		/* Clear TX status register TX complete indication but preserve
+		 * error bits if there is any */
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_TXSR_OFFSET,
+				   XEMACPS_TXSR_TXCOMPL_MASK |
+				   XEMACPS_TXSR_USEDREAD_MASK);
+		InstancePtr->SendHandler(InstancePtr->SendRef);
+	}
+
+	/* Receive error conditions interrupt */
+	if (RegISR & (XEMACPS_IXR_RX_ERR_MASK)) {
+		/* Clear RX status register */
+		RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XEMACPS_RXSR_OFFSET);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_RXSR_OFFSET, RegSR);
+
+		/* Fix for CR # 692702. Write to bit 18 of net_ctrl
+		 * register to flush a packet out of Rx SRAM upon
+		 * an error for receive buffer not available. */
+		if (RegISR & XEMACPS_IXR_RXUSED_MASK) {
+			RegCtrl =
+			XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XEMACPS_NWCTRL_OFFSET);
+			RegCtrl |= XEMACPS_NWCTRL_FLUSH_DPRAM_MASK;
+			XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET, RegCtrl);
+		}
+		InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_RECV,
+					  RegSR);
+	}
+
+        /* When XEMACPS_IXR_TXCOMPL_MASK is flaged, XEMACPS_IXR_TXUSED_MASK
+         * will be asserted the same time.
+         * Have to distinguish this bit to handle the real error condition.
+         */
+	/* Transmit error conditions interrupt */
+        if (RegISR & (XEMACPS_IXR_TX_ERR_MASK) &&
+            !(RegISR & (XEMACPS_IXR_TXCOMPL_MASK))) {
+		/* Clear TX status register */
+		RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XEMACPS_TXSR_OFFSET);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_TXSR_OFFSET, RegSR);
+		InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
+					  RegSR);
+	}
+
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_sinit.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_sinit.c
new file mode 100644
index 000000000..6472342eb
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v2_0/src/xemacps_sinit.c
@@ -0,0 +1,102 @@
+/* $Id: xemacps_sinit.c,v 1.1.2.1 2011/01/20 03:39:02 sadanan Exp $ */
+/******************************************************************************
+*
+* (c) Copyright 2010 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_sinit.c
+*
+* This file contains lookup method by device ID when success, it returns
+* pointer to config table to be used to initialize the device.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 New
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xemacps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID.  The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return
+* A pointer to the configuration table entry corresponding to the given
+* device ID, or NULL if no match is found.
+*
+******************************************************************************/
+XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId)
+{
+	extern XEmacPs_Config XEmacPs_ConfigTable[];
+	XEmacPs_Config *CfgPtr = NULL;
+	int i;
+
+	for (i = 0; i < XPAR_XEMACPS_NUM_INSTANCES; i++) {
+		if (XEmacPs_ConfigTable[i].DeviceId == DeviceId) {
+			CfgPtr = &XEmacPs_ConfigTable[i];
+			break;
+		}
+	}
+
+	return (CfgPtr);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/Makefile
new file mode 100644
index 000000000..f7eb27bf1
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/Makefile
@@ -0,0 +1,41 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xgpiops_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling gpiops"
+
+xgpiops_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xgpiops_includes
+
+xgpiops_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/xgpiops.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/xgpiops.c
new file mode 100644
index 000000000..9c7789297
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/xgpiops.c
@@ -0,0 +1,606 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops.c
+*
+* The XGpioPs driver. Functions in this file are the minimum required functions
+* for this driver. See xgpiops.h for a detailed description of the driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 1.01a sv   04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
+*                     XGpioPs_GetMode, XGpioPs_GetModePin as they are not
+*		      relevant to Zynq device. The interrupts are disabled
+*		      for output pins on all banks during initialization.
+* 2.1   hk   04/29/14 Use Input data register DATA_RO for read. CR# 771667.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/*
+ * This structure defines the mapping of the pin numbers to the banks when
+ * the driver APIs are used for working on the individual pins.
+ */
+unsigned int XGpioPsPinTable[] = {
+	31, /* 0 - 31, Bank 0 */
+	53, /* 32 - 53, Bank 1 */
+	85, /* 54 - 85, Bank 2 */
+	117 /* 86 - 117 Bank 3 */
+};
+
+/************************** Function Prototypes ******************************/
+
+extern void StubHandler(void *CallBackRef, int Bank, u32 Status);
+
+/*****************************************************************************/
+/*
+*
+* This function initializes a XGpioPs instance/driver.
+* All members of the XGpioPs instance structure are initialized and
+* StubHandlers are assigned to the Bank Status Handlers.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	ConfigPtr points to the XGpioPs device configuration structure.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. If the address translation is not used then the
+*		physical address should be passed.
+*		Unexpected errors may occur if the address mapping is changed
+*		after this function is invoked.
+*
+* @return	XST_SUCCESS always.
+*
+* @note		None.
+*
+******************************************************************************/
+int XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * Set some default values for instance data, don't indicate the device
+	 * is ready to use until everything has been initialized successfully.
+	 */
+	InstancePtr->IsReady = 0;
+	InstancePtr->GpioConfig.BaseAddr = EffectiveAddr;
+	InstancePtr->GpioConfig.DeviceId = ConfigPtr->DeviceId;
+	InstancePtr->Handler = StubHandler;
+
+	/*
+	 * By default, interrupts are not masked in GPIO. Disable
+	 * interrupts for all pins in all the 4 banks.
+	 */
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFF);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((1) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFF);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((2) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFF);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((3) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFF);
+
+	/*
+	 * Indicate the component is now ready to use.
+	 */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* Read the Data register of the specified GPIO bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+*
+* @return	Current value of the Data register.
+*
+* @note		This function is used for reading the state of all the GPIO pins
+*		of specified bank.
+*
+*****************************************************************************/
+u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS);
+
+	return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				 ((Bank) * XGPIOPS_DATA_BANK_OFFSET) +
+				 XGPIOPS_DATA_RO_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* Read Data from the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the data has to be read.
+*		Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
+*		See xgpiops.h for the mapping of the pin numbers in the banks.
+*
+* @return	Current value of the Pin (0 or 1).
+*
+* @note		This function is used for reading the state of the specified
+*		GPIO pin.
+*
+*****************************************************************************/
+int XGpioPs_ReadPin(XGpioPs *InstancePtr, int Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
+
+	/*
+	 * Get the Bank number and Pin number within the bank.
+	 */
+	XGpioPs_GetBankPin(Pin, &Bank, &PinNumber);
+
+	return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				 ((Bank) * XGPIOPS_DATA_BANK_OFFSET) +
+				 XGPIOPS_DATA_RO_OFFSET) >> PinNumber) & 1;
+
+}
+
+/****************************************************************************/
+/**
+*
+* Write to the Data register of the specified GPIO bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+* @param	Data is the value to be written to the Data register.
+*
+* @return	None.
+*
+* @note		This function is used for writing to all the GPIO pins of
+*		the bank. The previous state of the pins is not maintained.
+*
+*****************************************************************************/
+void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((Bank) * XGPIOPS_DATA_BANK_OFFSET) +
+			  XGPIOPS_DATA_OFFSET, Data);
+}
+
+/****************************************************************************/
+/**
+*
+* Write data to the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number to which the Data is to be written.
+*		Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
+* @param	Data is the data to be written to the specified pin (0 or 1).
+*
+* @return	None.
+*
+* @note		This function does a masked write to the specified pin of
+*		the specified GPIO bank. The previous state of other pins
+*		is maintained.
+*
+*****************************************************************************/
+void XGpioPs_WritePin(XGpioPs *InstancePtr, int Pin, int Data)
+{
+	u32 RegOffset;
+	u32 Value;
+	u8 Bank;
+	u8 PinNumber;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
+
+	/*
+	 * Get the Bank number and Pin number within the bank.
+	 */
+	XGpioPs_GetBankPin(Pin, &Bank, &PinNumber);
+
+	if (PinNumber > 15) {
+		/*
+		 * There are only 16 data bits in bit maskable register.
+		 */
+		PinNumber -= 16;
+		RegOffset = XGPIOPS_DATA_MSW_OFFSET;
+	} else {
+		RegOffset = XGPIOPS_DATA_LSW_OFFSET;
+	}
+
+	/*
+	 * Get the 32 bit value to be written to the Mask/Data register where
+	 * the upper 16 bits is the mask and lower 16 bits is the data.
+	 */
+	Data &= 0x01;
+	Value = ~(1 << (PinNumber + 16)) & ((Data << PinNumber) | 0xFFFF0000);
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((Bank) * XGPIOPS_DATA_MASK_OFFSET) +
+			  RegOffset, Value);
+}
+
+
+
+/****************************************************************************/
+/**
+*
+* Set the Direction of the pins of the specified GPIO Bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+* @param	Direction is the 32 bit mask of the Pin direction to be set for
+*		all the pins in the Bank. Bits with 0 are set to Input mode,
+*		bits with 1 are	set to Output Mode.
+*
+* @return	None.
+*
+* @note		This function is used for setting the direction of all the pins
+*		in the specified bank. The previous state of the pins is
+*		not maintained.
+*
+*****************************************************************************/
+void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_DIRM_OFFSET, Direction);
+}
+
+/****************************************************************************/
+/**
+*
+* Set the Direction of the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number to which the Data is to be written.
+*		Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
+* @param	Direction is the direction to be set for the specified pin.
+*		Valid values are 0 for Input Direction, 1 for Output Direction.
+*
+* @return	None.
+*
+*****************************************************************************/
+void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, int Pin, int Direction)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 DirModeReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
+	Xil_AssertVoid((Direction == 0) || (Direction == 1));
+
+	/*
+	 * Get the Bank number and Pin number within the bank.
+	 */
+	XGpioPs_GetBankPin(Pin, &Bank, &PinNumber);
+
+	DirModeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				      ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				      XGPIOPS_DIRM_OFFSET);
+
+	if (Direction) { /*  Output Direction */
+		DirModeReg |= (1 << PinNumber);
+	} else { /* Input Direction */
+		DirModeReg &= ~ (1 << PinNumber);
+	}
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			 ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			 XGPIOPS_DIRM_OFFSET, DirModeReg);
+}
+
+/****************************************************************************/
+/**
+*
+* Get the Direction of the pins of the specified GPIO Bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+*
+* return	Returns a 32 bit mask of the Direction register. Bits with 0 are
+*		in Input mode, bits with 1 are in Output Mode.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS);
+
+	return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				XGPIOPS_DIRM_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* Get the Direction of the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the Direction is to be
+*		retrieved.
+*		Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
+*
+* @return	Direction of the specified pin.
+*		- 0 for Input Direction
+*		- 1 for Output Direction
+*
+* @note		None.
+*
+*****************************************************************************/
+int XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, int Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
+
+	/*
+	 * Get the Bank number and Pin number within the bank.
+	 */
+	XGpioPs_GetBankPin(Pin, &Bank, &PinNumber);
+
+	return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				 ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_DIRM_OFFSET) >> PinNumber) & 1;
+}
+
+/****************************************************************************/
+/**
+*
+* Set the Output Enable of the pins of the specified GPIO Bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+* @param	OpEnable is the 32 bit mask of the Output Enables to be set for
+*		all the pins in the Bank. The Output Enable of bits with 0 are
+*		disabled, the Output Enable of bits with 1 are enabled.
+*
+* @return	None.
+*
+* @note		This function is used for setting the Output Enables of all the
+*		pins in the specified bank. The previous state of the Output
+*		Enables is not maintained.
+*
+*****************************************************************************/
+void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_OUTEN_OFFSET, OpEnable);
+}
+
+/****************************************************************************/
+/**
+*
+* Set the Output Enable of the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number to which the Data is to be written.
+*		Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
+* @param	OpEnable specifies whether the Output Enable for the specified
+*		pin should be enabled.
+*		Valid values are 0 for Disabling Output Enable,
+*		1 for Enabling Output Enable.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, int Pin, int OpEnable)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 OpEnableReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
+	Xil_AssertVoid((OpEnable == 0) || (OpEnable == 1));
+
+	/*
+	 * Get the Bank number and Pin number within the bank.
+	 */
+	XGpioPs_GetBankPin(Pin, &Bank, &PinNumber);
+
+	OpEnableReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				       ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				       XGPIOPS_OUTEN_OFFSET);
+
+	if (OpEnable) { /*  Enable Output Enable */
+		OpEnableReg |= (1 << PinNumber);
+	} else { /* Disable Output Enable */
+		OpEnableReg &= ~ (1 << PinNumber);
+	}
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_OUTEN_OFFSET, OpEnableReg);
+}
+/****************************************************************************/
+/**
+*
+* Get the Output Enable status of the pins of the specified GPIO Bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+*
+* return	Returns a a 32 bit mask of the Output Enable register.
+*		Bits with 0 are in Disabled state, bits with 1 are in
+*		Enabled State.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS);
+
+	return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				XGPIOPS_OUTEN_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* Get the Output Enable status of the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the Output Enable status is to
+*		be retrieved.
+*		Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
+*
+* @return	Output Enable of the specified pin.
+*		- 0 if Output Enable is disabled for this pin
+*		- 1 if Output Enable is enabled for this pin
+*
+* @note		None.
+*
+*****************************************************************************/
+int XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, int Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
+
+	/*
+	 * Get the Bank number and Pin number within the bank.
+	 */
+	XGpioPs_GetBankPin(Pin, &Bank, &PinNumber);
+
+	return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				 ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_OUTEN_OFFSET) >> PinNumber) & 1;
+}
+
+/****************************************************************************/
+/*
+*
+* Get the Bank number and the Pin number in the Bank, for the given PinNumber
+* in the GPIO device.
+*
+* @param	PinNumber is the Pin number in the GPIO device.
+* @param	BankNumber returns the Bank in which this GPIO pin is present.
+*		Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+* @param	PinNumberInBank returns the Pin Number within the Bank.
+*
+* return	None;
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_GetBankPin(u8 PinNumber,	u8 *BankNumber, u8 *PinNumberInBank)
+{
+	for (*BankNumber = 0; *BankNumber < 4; (*BankNumber)++)
+		if (PinNumber <= XGpioPsPinTable[*BankNumber])
+			break;
+
+	if (*BankNumber == 0) {
+		*PinNumberInBank = PinNumber;
+	} else {
+		*PinNumberInBank = PinNumber %
+					(XGpioPsPinTable[*BankNumber - 1] + 1);
+	}
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/xgpiops.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/xgpiops.h
new file mode 100644
index 000000000..f04e62da3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/xgpiops.h
@@ -0,0 +1,264 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops.h
+*
+* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
+* Controller.
+*
+* The GPIO Controller supports the following features:
+*	- 4 banks
+*	- Masked writes (There are no masked reads)
+*	- Bypass mode
+*	- Configurable Interrupts (Level/Edge)
+*
+* This driver is intended to be RTOS and processor independent. Any needs for
+* dynamic memory management, threads or thread mutual exclusion, virtual
+* memory, or cache control must be satisfied by the layer above this driver.
+
+* This driver supports all the features listed above, if applicable.
+*
+* Driver Description
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the GPIO.
+*
+* Interrupts
+*
+* The driver provides interrupt management functions and an interrupt handler.
+* Users of this driver need to provide callback functions. An interrupt handler
+* example is available with the driver.
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* Building the driver
+*
+* The XGpioPs driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+* 


+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 1.01a sv   04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
+*                     XGpioPs_GetMode, XGpioPs_GetModePin as they are not
+*		      relevant to Zynq device.The interrupts are disabled
+*		      for output pins on all banks during initialization.
+* 1.02a hk   08/22/13 Added low level reset API
+* 2.1   hk   04/29/14 Use Input data register DATA_RO for read. CR# 771667.
+*
+* 

+*
+******************************************************************************/
+#ifndef XGPIOPS_H		/* prevent circular inclusions */
+#define XGPIOPS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xgpiops_hw.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Interrupt types
+ *  @{
+ * The following constants define the interrupt types that can be set for each
+ * GPIO pin.
+ */
+#define XGPIOPS_IRQ_TYPE_EDGE_RISING	0  /**< Interrupt on Rising edge */
+#define XGPIOPS_IRQ_TYPE_EDGE_FALLING	1  /**< Interrupt Falling edge */
+#define XGPIOPS_IRQ_TYPE_EDGE_BOTH	2  /**< Interrupt on both edges */
+#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH	3  /**< Interrupt on high level */
+#define XGPIOPS_IRQ_TYPE_LEVEL_LOW	4  /**< Interrupt on low level */
+/*@}*/
+
+#define XGPIOPS_BANK0			0  /**< GPIO Bank 0 */
+#define XGPIOPS_BANK1			1  /**< GPIO Bank 1 */
+#define XGPIOPS_BANK2			2  /**< GPIO Bank 2 */
+#define XGPIOPS_BANK3			3  /**< GPIO Bank 3 */
+
+#define XGPIOPS_MAX_BANKS		4  /**< Max banks in a GPIO device */
+#define XGPIOPS_BANK_MAX_PINS		32 /**< Max pins in a GPIO bank */
+
+#define XGPIOPS_DEVICE_MAX_PIN_NUM	118 /*< Max pins in the GPIO device
+					      * 0 - 31,  Bank 0
+					      * 32 - 53, Bank 1
+					      *	54 - 85, Bank 2
+					      *	86 - 117, Bank 3
+					      */
+
+/**************************** Type Definitions *******************************/
+
+/****************************************************************************/
+/**
+ * This handler data type allows the user to define a callback function to
+ * handle the interrupts for the GPIO device. The application using this
+ * driver is expected to define a handler of this type, to support interrupt
+ * driven mode. The handler executes in an interrupt context such that minimal
+ * processing should be performed.
+ *
+ * @param	CallBackRef is a callback reference passed in by the upper layer
+ *		when setting the callback functions for a GPIO bank. It is
+ *		passed back to the upper layer when the callback is invoked. Its
+ *		type is not important to the driver component, so it is a void
+ *		pointer.
+ * @param	Bank is the bank for which the interrupt status has changed.
+ * @param	Status is the Interrupt status of the GPIO bank.
+ *
+ *****************************************************************************/
+typedef void (*XGpioPs_Handler) (void *CallBackRef, int Bank, u32 Status);
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID of device */
+	u32 BaseAddr;		/**< Register base address */
+} XGpioPs_Config;
+
+/**
+ * The XGpioPs driver instance data. The user is required to allocate a
+ * variable of this type for the GPIO device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XGpioPs_Config GpioConfig;	/**< Device configuration */
+	u32 IsReady;			/**< Device is initialized and ready */
+	XGpioPs_Handler Handler;	/**< Status handlers for all banks */
+	void *CallBackRef; 		/**< Callback ref for bank handlers */
+} XGpioPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Functions in xgpiops.c
+ */
+int XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
+			   u32 EffectiveAddr);
+
+/*
+ * Bank APIs in xgpiops.c
+ */
+u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data);
+void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction);
+u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 Enable);
+u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_GetBankPin(u8 PinNumber,	u8 *BankNumber, u8 *PinNumberInBank);
+
+/*
+ * Pin APIs in xgpiops.c
+ */
+int XGpioPs_ReadPin(XGpioPs *InstancePtr, int Pin);
+void XGpioPs_WritePin(XGpioPs *InstancePtr, int Pin, int Data);
+void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, int Pin, int Direction);
+int XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, int Pin);
+void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, int Pin, int Enable);
+int XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, int Pin);
+
+/*
+ * Diagnostic functions in xgpiops_selftest.c
+ */
+int XGpioPs_SelfTest(XGpioPs *InstancePtr);
+
+/*
+ * Functions in xgpiops_intr.c
+ */
+/*
+ * Bank APIs in xgpiops_intr.c
+ */
+void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank);
+u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
+			  u32 IntrPolarity, u32 IntrOnAny);
+void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
+			  u32 *IntrPolarity, u32 *IntrOnAny);
+void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
+			     XGpioPs_Handler FuncPtr);
+void XGpioPs_IntrHandler(XGpioPs *InstancePtr);
+
+/*
+ * Pin APIs in xgpiops_intr.c
+ */
+void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, int Pin, u8 IrqType);
+u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, int Pin);
+
+void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, int Pin);
+void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, int Pin);
+int XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, int Pin);
+int XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, int Pin);
+void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, int Pin);
+
+/*
+ * Functions in xgpiops_sinit.c
+ */
+XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/xgpiops_g.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/xgpiops_g.c
new file mode 100644
index 000000000..a724d46a5
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/xgpiops_g.c
@@ -0,0 +1,31 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSM.
+* Version: 
+* DO NOT EDIT.
+*
+*  v (64-bit)
+SW Build (by ) on 
+Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xgpiops.h"
+
+/*
+* The configuration table for devices
+*/
+
+XGpioPs_Config XGpioPs_ConfigTable[] =
+{
+	{
+		XPAR_PS7_GPIO_0_DEVICE_ID,
+		XPAR_PS7_GPIO_0_BASEADDR
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/xgpiops_hw.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/xgpiops_hw.c
new file mode 100644
index 000000000..59c924db5
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/xgpiops_hw.c
@@ -0,0 +1,171 @@
+/******************************************************************************
+*
+* (c) Copyright 2013-14 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_hw.c
+*
+* This file contains low level GPIO functions.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.02a hk   08/22/13 First Release
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops_hw.h"
+#include "xgpiops.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+
+/*****************************************************************************/
+/*
+*
+* This function resets the GPIO module by writing reset values to
+* all registers
+*
+* @param	Base address of GPIO module
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XGpioPs_ResetHw(u32 BaseAddress)
+{
+	u32 BankCount;
+
+	/*
+	 * Write reset values to all mask data registers
+	 */
+	for(BankCount = 2; BankCount < XGPIOPS_MAX_BANKS; BankCount++) {
+
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
+				 XGPIOPS_DATA_LSW_OFFSET), 0x0);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
+				 XGPIOPS_DATA_MSW_OFFSET), 0x0);
+	}
+	/*
+	 * Write reset values to all output data registers
+	 */
+	for(BankCount = 2; BankCount < XGPIOPS_MAX_BANKS; BankCount++) {
+
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_DATA_BANK_OFFSET) +
+				 XGPIOPS_DATA_OFFSET), 0x0);
+	}
+
+	/*
+	 * Reset all registers of all 4 banks
+	 */
+	for(BankCount = 0; BankCount < XGPIOPS_MAX_BANKS; BankCount++) {
+
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_DIRM_OFFSET), 0x0);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_OUTEN_OFFSET), 0x0);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTMASK_OFFSET), 0x0);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTEN_OFFSET), 0x0);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTDIS_OFFSET), 0x0);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTSTS_OFFSET), 0x0);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTPOL_OFFSET), 0x0);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTANY_OFFSET), 0x0);
+	}
+
+	/*
+	 * Bank 0 Int type
+	 */
+	XGpioPs_WriteReg(BaseAddress, XGPIOPS_INTTYPE_OFFSET,
+			XGPIOPS_INTTYPE_BANK0_RESET);
+	/*
+	 * Bank 1 Int type
+	 */
+	XGpioPs_WriteReg(BaseAddress,
+			(XGPIOPS_REG_MASK_OFFSET + XGPIOPS_INTTYPE_OFFSET),
+			XGPIOPS_INTTYPE_BANK1_RESET);
+	/*
+	 * Bank 2 Int type
+	 */
+	XGpioPs_WriteReg(BaseAddress,
+			((2*XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+			XGPIOPS_INTTYPE_BANK2_RESET);
+	/*
+	 * Bank 3 Int type
+	 */
+	XGpioPs_WriteReg(BaseAddress,
+			((3*XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+			XGPIOPS_INTTYPE_BANK3_RESET);
+
+}
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/xgpiops_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/xgpiops_hw.h
new file mode 100644
index 000000000..6c9ef5e0e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/xgpiops_hw.h
@@ -0,0 +1,159 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_hw.h
+*
+* This header file contains the identifiers and basic driver functions (or
+* macros) that can be used to access the device. Other driver functions
+* are defined in xgpiops.h.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 1.02a hk   08/22/13 Added low level reset API function prototype and
+*                     related constant definitions
+* 

+*
+******************************************************************************/
+#ifndef XGPIOPS_HW_H		/* prevent circular inclusions */
+#define XGPIOPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register offsets for the GPIO. Each register is 32 bits.
+ *  @{
+ */
+#define XGPIOPS_DATA_LSW_OFFSET  0x000  /* Mask and Data Register LSW, WO */
+#define XGPIOPS_DATA_MSW_OFFSET  0x004  /* Mask and Data Register MSW, WO */
+#define XGPIOPS_DATA_OFFSET	 0x040  /* Data Register, RW */
+#define XGPIOPS_DATA_RO_OFFSET	 0x060  /* Data Register - Input, RO */
+#define XGPIOPS_DIRM_OFFSET	 0x204  /* Direction Mode Register, RW */
+#define XGPIOPS_OUTEN_OFFSET	 0x208  /* Output Enable Register, RW */
+#define XGPIOPS_INTMASK_OFFSET	 0x20C  /* Interrupt Mask Register, RO */
+#define XGPIOPS_INTEN_OFFSET	 0x210  /* Interrupt Enable Register, WO */
+#define XGPIOPS_INTDIS_OFFSET	 0x214  /* Interrupt Disable Register, WO*/
+#define XGPIOPS_INTSTS_OFFSET	 0x218  /* Interrupt Status Register, RO */
+#define XGPIOPS_INTTYPE_OFFSET	 0x21C  /* Interrupt Type Register, RW */
+#define XGPIOPS_INTPOL_OFFSET	 0x220  /* Interrupt Polarity Register, RW */
+#define XGPIOPS_INTANY_OFFSET	 0x224  /* Interrupt On Any Register, RW */
+/* @} */
+
+/** @name Register offsets for each Bank.
+ *  @{
+ */
+#define XGPIOPS_DATA_MASK_OFFSET 0x8  /* Data/Mask Registers offset */
+#define XGPIOPS_DATA_BANK_OFFSET 0x4  /* Data Registers offset */
+#define XGPIOPS_REG_MASK_OFFSET 0x40  /* Registers offset */
+/* @} */
+
+/* For backwards compatibility */
+#define XGPIOPS_BYPM_MASK_OFFSET	XGPIOPS_REG_MASK_OFFSET
+
+/** @name Interrupt type reset values for each bank
+ *  @{
+ */
+#define XGPIOPS_INTTYPE_BANK0_RESET  0xFFFFFFFF
+#define XGPIOPS_INTTYPE_BANK1_RESET  0x3FFFFFFF
+#define XGPIOPS_INTTYPE_BANK2_RESET  0xFFFFFFFF
+#define XGPIOPS_INTTYPE_BANK3_RESET  0xFFFFFFFF
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param	BaseAddr is the base address of the device.
+* @param	RegOffset is the register offset to be read.
+*
+* @return	The 32-bit value of the register
+*
+* @note		None.
+*
+*****************************************************************************/
+#define XGpioPs_ReadReg(BaseAddr, RegOffset)		\
+		Xil_In32((BaseAddr) + (RegOffset))
+
+/****************************************************************************/
+/**
+*
+* This macro writes to the given register.
+*
+* @param	BaseAddr is the base address of the device.
+* @param	RegOffset is the offset of the register to be written.
+* @param	Data is the 32-bit value to write to the register.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data)	\
+		Xil_Out32((BaseAddr) + (RegOffset), (Data))
+
+/************************** Function Prototypes ******************************/
+
+void XGpioPs_ResetHw(u32 BaseAddress);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XGPIOPS_HW_H */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/xgpiops_intr.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/xgpiops_intr.c
new file mode 100644
index 000000000..fce9c7d8a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/xgpiops_intr.c
@@ -0,0 +1,741 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_intr.c
+*
+* This file contains functions related to GPIO interrupt handling.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/18/10 First Release
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void StubHandler(void *CallBackRef, int Bank, u32 Status);
+
+/****************************************************************************/
+/**
+*
+* This function enables the interrupts for the specified pins in the specified
+* bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+* @param	Mask is the bit mask of the pins for which interrupts are to
+*		be enabled. Bit positions of 1 will be enabled. Bit positions
+*		of 0 will keep the previous setting.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTEN_OFFSET, Mask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the interrupt for the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the interrupt is to be enabled.
+*		Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, int Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 IntrReg = 0;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
+
+	/*
+	 * Get the Bank number and Pin number within the bank.
+	 */
+	XGpioPs_GetBankPin(Pin, &Bank, &PinNumber);
+
+	IntrReg = 1 << PinNumber;
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTEN_OFFSET, IntrReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables the interrupts for the specified pins in the specified
+* bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+* @param	Mask is the bit mask of the pins for which interrupts are
+*		to be disabled. Bit positions of 1 will be disabled. Bit
+*		positions of 0 will keep the previous setting.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTDIS_OFFSET, Mask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables the interrupts for the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the interrupt is to be disabled.
+*		Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, int Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 IntrReg = 0;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
+
+	/*
+	 * Get the Bank number and Pin number within the bank.
+	 */
+	XGpioPs_GetBankPin(Pin, &Bank, &PinNumber);
+
+	IntrReg =  1 << PinNumber;
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTDIS_OFFSET, IntrReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the interrupt enable status for a bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+*
+* @return	Enabled interrupt(s) in a 32-bit format. Bit positions with 1
+*		indicate that the interrupt for that pin is enabled, bit
+*		positions with 0 indicate that the interrupt for that pin is
+*		disabled.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank)
+{
+	u32 IntrMask;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS);
+
+	IntrMask = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				    ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				    XGPIOPS_INTMASK_OFFSET);
+	return ~IntrMask;
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns whether interrupts are enabled for the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the interrupt enable status
+*		is to be known.
+*		Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
+*
+* @return
+*		- TRUE if the interrupt is enabled.
+*		- FALSE if the interrupt is disabled.
+*
+* @note		None.
+*
+*****************************************************************************/
+int XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, int Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 IntrReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
+
+	/*
+	 * Get the Bank number and Pin number within the bank.
+	 */
+	XGpioPs_GetBankPin(Pin, &Bank, &PinNumber);
+
+	IntrReg  = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				    ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				    XGPIOPS_INTMASK_OFFSET);
+
+	return (IntrReg & (1 << Pin)) ? TRUE : FALSE;
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns interrupt status read from Interrupt Status Register.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+*
+* @return	The value read from Interrupt Status Register.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS);
+
+	return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				XGPIOPS_INTSTS_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns interrupt enable status of the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the interrupt enable status
+*		is to be known.
+*		Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
+*
+* @return
+*		- TRUE if the interrupt has occurred.
+*		- FALSE if the interrupt has not occurred.
+*
+* @note		None.
+*
+*****************************************************************************/
+int XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, int Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 IntrReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
+
+	/*
+	 * Get the Bank number and Pin number within the bank.
+	 */
+	XGpioPs_GetBankPin(Pin, &Bank, &PinNumber);
+
+	IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				   ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				   XGPIOPS_INTSTS_OFFSET);
+
+	return (IntrReg & (1 << Pin)) ? TRUE : FALSE;
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears pending interrupt(s) with the provided mask. This
+* function should be called after the software has serviced the interrupts
+* that are pending.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+* @param	Mask is the mask of the interrupts to be cleared. Bit positions
+*		of 1 will be cleared. Bit positions of 0 will not change the
+*		previous interrupt status.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS);
+
+	/*
+	 * Clear the currently pending interrupts.
+	 */
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTSTS_OFFSET, Mask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears the specified pending interrupt. This function should be
+* called after the software has serviced the interrupts that are pending.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the interrupt status is to be
+*		cleared. Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, int Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 IntrReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
+
+	/*
+	 * Get the Bank number and Pin number within the bank.
+	 */
+	XGpioPs_GetBankPin(Pin, &Bank, &PinNumber);
+
+	/*
+	 * Clear the specified pending interrupts.
+	 */
+	IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				   ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				   XGPIOPS_INTSTS_OFFSET);
+
+	IntrReg &= (1 << Pin);
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTSTS_OFFSET, IntrReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for setting the Interrupt Type, Interrupt Polarity and
+* Interrupt On Any for the specified GPIO Bank pins.
+*
+* @param	InstancePtr is a pointer to an XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+* @param	IntrType is the 32 bit mask of the interrupt type.
+*		0 means Level Sensitive and 1 means Edge Sensitive.
+* @param	IntrPolarity is the 32 bit mask of the interrupt polarity.
+*		0 means Active Low or Falling Edge and 1 means Active High or
+*		Rising Edge.
+* @param	IntrOnAny is the 32 bit mask of the interrupt trigger for
+*		edge triggered interrupts. 0 means trigger on single edge using
+*		the configured interrupt polarity and 1 means  trigger on both
+*		edges.
+*
+* @return	None.
+*
+* @note		This function is used for setting the interrupt related
+*		properties of all the pins in the specified bank. The previous
+*		state of the pins is not maintained.
+*		To change the Interrupt properties of a single GPIO pin, use the
+*		function XGpioPs_SetPinIntrType().
+*
+*****************************************************************************/
+void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
+			  u32 IntrPolarity, u32 IntrOnAny)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTTYPE_OFFSET, IntrType);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTPOL_OFFSET, IntrPolarity);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTANY_OFFSET, IntrOnAny);
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for getting the Interrupt Type, Interrupt Polarity and
+* Interrupt On Any for the specified GPIO Bank pins.
+*
+* @param	InstancePtr is a pointer to an XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+* @param	IntrType returns the 32 bit mask of the interrupt type.
+*		0 means Level Sensitive and 1 means Edge Sensitive.
+* @param	IntrPolarity returns the 32 bit mask of the interrupt
+*		polarity. 0 means Active Low or Falling Edge and 1 means
+*		Active High or Rising Edge.
+* @param	IntrOnAny returns the 32 bit mask of the interrupt trigger for
+*		edge triggered interrupts. 0 means trigger on single edge using
+*		the configured interrupt polarity and 1 means trigger on both
+*		edges.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
+			  u32 *IntrPolarity, u32 *IntrOnAny)
+
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS);
+
+	*IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				     ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				     XGPIOPS_INTTYPE_OFFSET);
+
+	*IntrPolarity = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+					 ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+					 XGPIOPS_INTPOL_OFFSET);
+
+	*IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				      ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				      XGPIOPS_INTANY_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for setting the IRQ Type of a single GPIO pin.
+*
+* @param	InstancePtr is a pointer to an XGpioPs instance.
+* @param	Pin is the pin number whose IRQ type is to be set.
+*		Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
+* @param	IrqType is the IRQ type for GPIO Pin. Use XGPIOPS_IRQ_TYPE_*
+*		defined in xgpiops.h to specify the IRQ type.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, int Pin, u8 IrqType)
+{
+	u32 IntrTypeReg;
+	u32 IntrPolReg;
+	u32 IntrOnAnyReg;
+	u8 Bank;
+	u8 PinNumber;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
+	Xil_AssertVoid(IrqType <= XGPIOPS_IRQ_TYPE_LEVEL_LOW);
+
+	/*
+	 * Get the Bank number and Pin number within the bank.
+	 */
+	XGpioPs_GetBankPin(Pin, &Bank, &PinNumber);
+
+	IntrTypeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				       ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				       XGPIOPS_INTTYPE_OFFSET);
+
+	IntrPolReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				      ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				      XGPIOPS_INTPOL_OFFSET);
+
+	IntrOnAnyReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+					((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+					XGPIOPS_INTANY_OFFSET);
+
+	switch (IrqType) {
+		case XGPIOPS_IRQ_TYPE_EDGE_RISING:
+			IntrTypeReg |= (1 << PinNumber);
+			IntrPolReg |= (1 << PinNumber);
+			IntrOnAnyReg &= ~(1 << PinNumber);
+			break;
+		case XGPIOPS_IRQ_TYPE_EDGE_FALLING:
+			IntrTypeReg |= (1 << PinNumber);
+			IntrPolReg &= ~(1 << PinNumber);
+			IntrOnAnyReg &= ~(1 << PinNumber);
+			break;
+		case XGPIOPS_IRQ_TYPE_EDGE_BOTH:
+			IntrTypeReg |= (1 << PinNumber);
+			IntrOnAnyReg |= (1 << PinNumber);
+			break;
+		case XGPIOPS_IRQ_TYPE_LEVEL_HIGH:
+			IntrTypeReg &= ~(1 << PinNumber);
+			IntrPolReg |= (1 << PinNumber);
+			break;
+		case XGPIOPS_IRQ_TYPE_LEVEL_LOW:
+			IntrTypeReg &= ~(1 << PinNumber);
+			IntrPolReg &= ~(1 << PinNumber);
+			break;
+	}
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTTYPE_OFFSET, IntrTypeReg);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTPOL_OFFSET, IntrPolReg);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTANY_OFFSET, IntrOnAnyReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the IRQ Type of a given GPIO pin.
+*
+* @param	InstancePtr is a pointer to an XGpioPs instance.
+* @param	Pin is the pin number whose IRQ type is to be obtained.
+*		Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
+*
+* @return	None.
+*
+* @note		Use XGPIOPS_IRQ_TYPE_* defined in xgpiops.h for the IRQ type
+*		returned by this function.
+*
+*****************************************************************************/
+u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, int Pin)
+{
+	u32 IntrType;
+	u32 IntrPol;
+	u32 IntrOnAny;
+	u8 Bank;
+	u8 PinNumber;
+	u8 IrqType;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
+
+	/*
+	 * Get the Bank number and Pin number within the bank.
+	 */
+	XGpioPs_GetBankPin(Pin, &Bank, &PinNumber);
+
+	IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				    ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				    XGPIOPS_INTTYPE_OFFSET) & PinNumber;
+
+	IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				   ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				   XGPIOPS_INTPOL_OFFSET) & PinNumber;
+
+	IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				     ((Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				     XGPIOPS_INTANY_OFFSET) & PinNumber;
+
+	if (IntrType == 1) {
+		if (IntrOnAny == 1) {
+			IrqType = XGPIOPS_IRQ_TYPE_EDGE_BOTH;
+		} else if (IntrPol == 1) {
+			IrqType = XGPIOPS_IRQ_TYPE_EDGE_RISING;
+		} else {
+			IrqType = XGPIOPS_IRQ_TYPE_EDGE_FALLING;
+		}
+	} else {
+		if (IntrPol == 1) {
+			IrqType = XGPIOPS_IRQ_TYPE_LEVEL_HIGH;
+		} else {
+			IrqType = XGPIOPS_IRQ_TYPE_LEVEL_LOW;
+		}
+	}
+
+	return IrqType;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the status callback function. The callback function is
+* called by the  XGpioPs_IntrHandler when an interrupt occurs.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	CallBackRef is the upper layer callback reference passed back
+*		when the callback function is invoked.
+* @param	FuncPtr is the pointer to the callback function.
+*
+*
+* @return	None.
+*
+* @note		The handler is called within interrupt context, so it should do
+*		its work quickly and queue potentially time-consuming work to a
+*		task-level thread.
+*
+******************************************************************************/
+void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
+				 XGpioPs_Handler FuncPtr)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FuncPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	InstancePtr->Handler = FuncPtr;
+	InstancePtr->CallBackRef = CallBackRef;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function is the interrupt handler for GPIO interrupts.It checks the
+* interrupt status registers of all the banks to determine the actual bank in
+* which an interrupt has been triggered. It then calls the upper layer callback
+* handler set by the function XGpioPs_SetBankHandler(). The callback is called
+* when an interrupt
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+*
+* @return	None.
+*
+* @note		This function does not save and restore the processor context
+*		such that the user must provide this processing.
+*
+******************************************************************************/
+void XGpioPs_IntrHandler(XGpioPs *InstancePtr)
+{
+	u8 Bank;
+	u32 IntrStatus;
+	u32 IntrEnabled;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	for (Bank = 0; Bank < XGPIOPS_MAX_BANKS; Bank++) {
+		IntrStatus = XGpioPs_IntrGetStatus(InstancePtr, Bank);
+		if (IntrStatus != 0) {
+			IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr,
+							      Bank);
+			XGpioPs_IntrClear(InstancePtr, Bank,
+					   IntrStatus & IntrEnabled);
+			InstancePtr->Handler((void *)InstancePtr->
+					     CallBackRef, Bank,
+					     (IntrStatus & IntrEnabled));
+		}
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* This is a stub for the status callback. The stub is here in case the upper
+* layers do not set the handler.
+*
+* @param	CallBackRef is a pointer to the upper layer callback reference
+* @param	Bank is the GPIO Bank in which an interrupt occurred.
+* @param	Status is the Interrupt status of the GPIO bank.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void StubHandler(void *CallBackRef, int Bank, u32 Status)
+{
+	(void) CallBackRef;
+	(void) Bank;
+	(void) Status;
+
+	Xil_AssertVoidAlways();
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/xgpiops_selftest.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/xgpiops_selftest.c
new file mode 100644
index 000000000..f39a32af2
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/xgpiops_selftest.c
@@ -0,0 +1,140 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_selftest.c
+*
+* This file contains a diagnostic self-test function for the XGpioPs driver.
+*
+* Read xgpiops.h file for more information.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/18/10 First Release
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xgpiops.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function runs a self-test on the GPIO driver/device. This function
+* does a register read/write test on some of the Interrupt Registers.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+*
+* @return
+*		- XST_SUCCESS if the self-test passed.
+* 		- XST_FAILURE otherwise.
+*
+*
+******************************************************************************/
+int XGpioPs_SelfTest(XGpioPs *InstancePtr)
+{
+	int Status = XST_SUCCESS;
+	u32 IntrEnabled;
+	u32 CurrentIntrType;
+	u32 CurrentIntrPolarity;
+	u32 CurrentIntrOnAny;
+	u32 IntrType;
+	u32 IntrPolarity;
+	u32 IntrOnAny;
+	u32 IntrTestValue = 0x22;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Disable the Interrupts for Bank 0 .
+	 */
+	IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr, XGPIOPS_BANK0);
+	XGpioPs_IntrDisable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
+
+	/*
+	 * Get the Current Interrupt properties for Bank 0.
+	 * Set them to a known value, read it back and compare.
+	 */
+	XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &CurrentIntrType,
+			     &CurrentIntrPolarity, &CurrentIntrOnAny);
+
+	XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, IntrTestValue,
+			     IntrTestValue, IntrTestValue);
+
+	XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &IntrType,
+			     &IntrPolarity, &IntrOnAny);
+
+	if ((IntrType != IntrTestValue) && (IntrPolarity != IntrTestValue) &&
+	    (IntrOnAny != IntrTestValue)) {
+
+		Status = XST_FAILURE;
+	}
+
+	/*
+	 * Restore the contents of all the interrupt registers modified in this
+	 * test.
+	 */
+	XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, CurrentIntrType,
+			     CurrentIntrPolarity, CurrentIntrOnAny);
+
+	XGpioPs_IntrEnable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
+
+	return Status;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/xgpiops_sinit.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/xgpiops_sinit.c
new file mode 100644
index 000000000..dc2526f2c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v2_1/src/xgpiops_sinit.c
@@ -0,0 +1,106 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_sinit.c
+*
+* This file contains the implementation of the XGpioPs driver's static
+* initialization functionality.
+*
+* @note		None.
+*
+* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xgpiops.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XGpioPs_Config XGpioPs_ConfigTable[];
+
+/*****************************************************************************/
+/**
+*
+* This function looks for the device configuration based on the unique device
+* ID. The table XGpioPs_ConfigTable[] contains the configuration information
+* for each device in the system.
+*
+* @param	DeviceId is the unique device ID of the device being looked up.
+*
+* @return	A pointer to the configuration table entry corresponding to the
+*		given device ID, or NULL if no match is found.
+*
+* @note		None.
+*
+******************************************************************************/
+XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId)
+{
+	XGpioPs_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0; Index < XPAR_XGPIOPS_NUM_INSTANCES; Index++) {
+		if (XGpioPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XGpioPs_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return CfgPtr;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/Makefile
new file mode 100644
index 000000000..c506c25d5
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/Makefile
@@ -0,0 +1,41 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xiicps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling iicps"
+
+xiicps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xiicps_includes
+
+xiicps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps.c
new file mode 100644
index 000000000..82b1c94ac
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps.c
@@ -0,0 +1,331 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps.c
+*
+* Contains implementation of required functions for the XIicPs driver.
+* See xiicps.h for detailed description of the device and driver.
+*
+* 
 MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- --------------------------------------------
+* 1.00a drg/jz  01/30/10 First release
+* 1.00a sdm     09/21/11 Updated the InstancePtr->Options in the
+*			 XIicPs_CfgInitialize by calling XIicPs_GetOptions.
+* 2.1   hk      04/25/14 Explicitly reset CR and clear FIFO in Abort function
+*                        and state the same in the comments. CR# 784254.
+*                        Fix for CR# 761060 - provision for repeated start.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+static void StubHandler(void *CallBackRef, u32 StatusEvent);
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XIicPs instance such that the driver is ready to use.
+*
+* The state of the device after initialization is:
+*   - Device is disabled
+*   - Slave mode
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	ConfigPtr is a reference to a structure containing information
+*		about a specific IIC device. This function initializes an
+*		InstancePtr object for a specific device specified by the
+*		contents of Config.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, use
+*		ConfigPtr->BaseAddress for this parameter, passing the physical
+*		address instead.
+*
+* @return	The return value is XST_SUCCESS if successful.
+*
+* @note		None.
+*
+******************************************************************************/
+int XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config *ConfigPtr,
+				  u32 EffectiveAddr)
+{
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * Set some default values.
+	 */
+	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+	InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
+	InstancePtr->StatusHandler = StubHandler;
+	InstancePtr->CallBackRef = NULL;
+
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	/*
+	 * Reset the IIC device to get it into its initial state. It is expected
+	 * that device configuration will take place after this initialization
+	 * is done, but before the device is started.
+	 */
+	XIicPs_Reset(InstancePtr);
+
+	/*
+	 * Keep a copy of what options this instance has.
+	 */
+	InstancePtr->Options = XIicPs_GetOptions(InstancePtr);
+
+	/* Initialize repeated start flag to 0 */
+	InstancePtr->IsRepeatedStart = 0;
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* Check whether the I2C bus is busy
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return
+* 		- TRUE if the bus is busy.
+*		- FALSE if the bus is not busy.
+*
+* @note		None.
+*
+******************************************************************************/
+int XIicPs_BusIsBusy(XIicPs *InstancePtr)
+{
+	u32 StatusReg;
+
+	StatusReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					   XIICPS_SR_OFFSET);
+	if (StatusReg & XIICPS_SR_BA_MASK) {
+		return TRUE;
+	}else {
+		return FALSE;
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* This is a stub for the status callback. The stub is here in case the upper
+* layers forget to set the handler.
+*
+* @param	CallBackRef is a pointer to the upper layer callback reference.
+* @param	StatusEvent is the event that just occurred.
+* @param	ByteCount is the number of bytes transferred up until the event
+*		occurred.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void StubHandler(void *CallBackRef, u32 StatusEvent)
+{
+	(void) CallBackRef;
+	(void) StatusEvent;
+	Xil_AssertVoidAlways();
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Aborts a transfer in progress by resetting the FIFOs. The byte counts are
+* cleared.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XIicPs_Abort(XIicPs *InstancePtr)
+{
+	u32 IntrMaskReg;
+	u32 IntrStatusReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Enter a critical section, so disable the interrupts while we clear
+	 * the FIFO and the status register.
+	 */
+	IntrMaskReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					   XIICPS_IMR_OFFSET);
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_IDR_OFFSET, XIICPS_IXR_ALL_INTR_MASK);
+
+	/*
+	 * Reset the settings in config register and clear the FIFOs.
+	 */
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
+			  XIICPS_CR_RESET_VALUE | XIICPS_CR_CLR_FIFO_MASK);
+
+	/*
+	 * Read, then write the interrupt status to make sure there are no
+	 * pending interrupts.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					 XIICPS_ISR_OFFSET);
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	/*
+	 * Restore the interrupt state.
+	 */
+	IntrMaskReg = XIICPS_IXR_ALL_INTR_MASK & (~IntrMaskReg);
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_IER_OFFSET, IntrMaskReg);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Resets the IIC device. Reset must only be called after the driver has been
+* initialized. The configuration of the device after reset is the same as its
+* configuration after initialization.  Any data transfer that is in progress is
+* aborted.
+*
+* The upper layer software is responsible for re-configuring (if necessary)
+* and reenabling interrupts for the IIC device after the reset.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XIicPs_Reset(XIicPs *InstancePtr)
+{
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Abort any transfer that is in progress.
+	 */
+	XIicPs_Abort(InstancePtr);
+
+	/*
+	 * Reset any values so the software state matches the hardware device.
+	 */
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
+			  XIICPS_CR_RESET_VALUE);
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_TIME_OUT_OFFSET, XIICPS_TO_RESET_VALUE);
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_IDR_OFFSET,
+			  XIICPS_IXR_ALL_INTR_MASK);
+
+}
+/*****************************************************************************/
+/**
+* Put more data into the transmit FIFO, number of bytes is ether expected
+* number of bytes for this transfer or available space in FIFO, which ever
+* is less.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	Number of bytes left for this instance.
+*
+* @note		This is function is shared by master and slave.
+*
+******************************************************************************/
+int TransmitFifoFill(XIicPs *InstancePtr)
+{
+	u8 AvailBytes;
+	int LoopCnt;
+	int NumBytesToSend;
+
+	/*
+	 * Determine number of bytes to write to FIFO.
+	 */
+	AvailBytes = XIICPS_FIFO_DEPTH -
+		XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					   XIICPS_TRANS_SIZE_OFFSET);
+
+	if (InstancePtr->SendByteCount > AvailBytes) {
+		NumBytesToSend = AvailBytes;
+	} else {
+		NumBytesToSend = InstancePtr->SendByteCount;
+	}
+
+	/*
+	 * Fill FIFO with amount determined above.
+	 */
+	for (LoopCnt = 0; LoopCnt < NumBytesToSend; LoopCnt++) {
+		XIicPs_SendByte(InstancePtr);
+	}
+
+	return InstancePtr->SendByteCount;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps.h
new file mode 100644
index 000000000..92afb51a0
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps.h
@@ -0,0 +1,410 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps.h
+*
+* This is an implementation of IIC driver in the PS block. The device can
+* be either a master or a slave on the IIC bus. This implementation supports
+* both interrupt mode transfer and polled mode transfer. Only 7-bit address
+* is used in the driver, although the hardware also supports 10-bit address.
+*
+* IIC is a 2-wire serial interface.  The master controls the clock, so it can
+* regulate when it wants to send or receive data. The slave is under control of
+* the master, it must respond quickly since it has no control of the clock and
+* must send/receive data as fast or as slow as the master does.
+*
+* The higher level software must implement a higher layer protocol to inform
+* the slave what to send to the master.
+*
+* Initialization & Configuration
+*
+* The XIicPs_Config structure is used by the driver to configure itself. This
+* configuration structure is typically created by the tool-chain based on HW
+* build properties.
+*
+* To support multiple runtime loading and initialization strategies employed by
+* various operating systems, the driver instance can be initialized in the
+* following way:
+*
+*    - XIicPs_LookupConfig(DeviceId) - Use the device identifier to find
+*      the static configuration structure defined in xiicps_g.c. This is
+*      setup by the tools. For some operating systems the config structure
+*      will be initialized by the software and this call is not needed.
+*
+*   - XIicPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+*     configuration structure provided by the caller. If running in a
+*     system with address translation, the provided virtual memory base
+*     address replaces the physical address in the configuration
+*     structure.
+*
+* Multiple Masters
+*
+* More than one master can exist, bus arbitration is defined in the IIC
+* standard. Lost of arbitration causes arbitration loss interrupt on the device.
+*
+* Multiple Slaves
+*
+* Multiple slaves are supported by selecting them with unique addresses. It is
+* up to the system designer to be sure all devices on the IIC bus have
+* unique addresses.
+*
+* Addressing
+*
+* The IIC hardware can use 7 or 10 bit addresses.  The driver provides the
+* ability to control which address size is sent in messages as a master to a
+* slave device.
+*
+* FIFO Size 
+* The hardware FIFO is 32 bytes deep. The user must know the limitations of
+* other IIC devices on the bus. Some are only able to receive a limited number
+* of bytes in a single transfer.
+*
+* Data Rates
+*
+* The data rate is set by values in the control register. The formula for
+* determining the correct register values is:
+* Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
+*
+* When the device is configured as a slave, the slck setting controls the
+* sample rate and so must be set to be at least as fast as the fastest scl
+* expected to be seen in the system.
+*
+* Polled Mode Operation
+*
+* This driver supports polled mode transfers.
+*
+* Interrupts
+*
+* The user must connect the interrupt handler of the driver,
+* XIicPs_InterruptHandler to an interrupt system such that it will be called
+* when an interrupt occurs. This function does not save and restore the
+* processor context such that the user must provide this processing.
+*
+* The driver handles the following interrupts:
+* - Transfer complete
+* - More Data
+* - Transfer not Acknowledged
+* - Transfer Time out
+* - Monitored slave ready - master mode only
+* - Receive Overflow
+* - Transmit FIFO overflow
+* - Receive FIFO underflow
+* - Arbitration lost
+*
+* Bus Busy
+*
+* Bus busy is checked before the setup of a master mode device, to avoid
+* unnecessary arbitration loss interrupt.
+*
+* RTOS Independence
+*
+* This driver is intended to be RTOS and processor independent.  It works with
+* physical addresses only.  Any needs for dynamic memory management, threads or
+* thread mutual exclusion, virtual memory, or cache control must be satisfied by
+* the layer above this driver.
+*
+* @note
+* . Less than FIFO size transfers work for both 100 KHz and 400 KHz.
+* . Larger than FIFO size interrupt-driven transfers are not reliable on
+*    busy systems where interrupt latency is high.
+* . Larger than FIFO size interrupt-driven transfers are not reliable for
+*    data rate of 400 KHz.
+* . Larger than FIFO size polled mode transfers work reliably.
+*
+* 
 MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- -----------------------------------------------
+* 1.00a drg/jz  01/30/08 First release
+* 1.00a sdm     09/21/11 Fixed an issue in the XIicPs_SetOptions and
+*			 XIicPs_ClearOptions where the InstancePtr->Options
+*			 was not updated correctly.
+* 			 Updated the InstancePtr->Options in the
+*			 XIicPs_CfgInitialize by calling XIicPs_GetOptions.
+*			 Updated the XIicPs_SetupMaster to not check for
+*			 Bus Busy condition when the Hold Bit is set.
+*			 Removed some unused variables.
+* 1.01a sg      03/30/12 Fixed an issue in XIicPs_MasterSendPolled where a
+*			 check for transfer completion is added, which indicates
+*			 the completion of current transfer.
+* 1.02a sg	08/29/12 Updated the logic to arrive at the best divisors
+*			 to achieve I2C clock with minimum error for
+*			 CR #674195
+* 1.03a hk  05/04/13 Initialized BestDivA and BestDivB to 0.
+*			 This is fix for CR#704398 to remove warning.
+* 2.0   hk  03/07/14 Added check for error status in the while loop that
+*                    checks for completion.
+*                    (XIicPs_MasterSendPolled function). CR# 762244, 764875.
+*                    Limited frequency set when 100KHz or 400KHz is
+*                    selected. This is a hardware limitation. CR#779290.
+* 2.1   hk  04/24/14 Fix for CR# 789821 to handle >14 byte transfers.
+*                    Explicitly reset CR and clear FIFO in Abort function
+*                    and state the same in the comments. CR# 784254.
+*                    Fix for CR# 761060 - provision for repeated start.
+*
+* 

+*
+******************************************************************************/
+
+#ifndef XIICPS_H       /* prevent circular inclusions */
+#define XIICPS_H       /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xiicps_hw.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Configuration options
+ *
+ * The following options may be specified or retrieved for the device and
+ * enable/disable additional features of the IIC.  Each of the options
+ * are bit fields, so more than one may be specified.
+ *
+ * @{
+ */
+#define XIICPS_7_BIT_ADDR_OPTION	0x01  /**< 7-bit address mode */
+#define XIICPS_10_BIT_ADDR_OPTION	0x02  /**< 10-bit address mode */
+#define XIICPS_SLAVE_MON_OPTION		0x04  /**< Slave monitor mode */
+#define XIICPS_REP_START_OPTION		0x08  /**< Repeated Start */
+/*@}*/
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that are passed to an application
+ * event handler from the driver.  These constants are bit masks such that
+ * more than one event can be passed to the handler.
+ *
+ * @{
+ */
+#define XIICPS_EVENT_COMPLETE_SEND	0x0001  /**< Transmit Complete Event*/
+#define XIICPS_EVENT_COMPLETE_RECV	0x0002  /**< Receive Complete Event*/
+#define XIICPS_EVENT_TIME_OUT		0x0004  /**< Transfer timed out */
+#define XIICPS_EVENT_ERROR		0x0008  /**< Receive error */
+#define XIICPS_EVENT_ARB_LOST		0x0010  /**< Arbitration lost */
+#define XIICPS_EVENT_NACK		0x0020  /**< NACK Received */
+#define XIICPS_EVENT_SLAVE_RDY		0x0040  /**< Slave ready */
+#define XIICPS_EVENT_RX_OVR		0x0080  /**< RX overflow */
+#define XIICPS_EVENT_TX_OVR		0x0100  /**< TX overflow */
+#define XIICPS_EVENT_RX_UNF		0x0200  /**< RX underflow */
+/*@}*/
+
+/** @name Role constants
+ *
+ * These constants are used to pass into the device setup routines to
+ * set up the device according to transfer direction.
+ */
+#define SENDING_ROLE		1  /**< Transfer direction is sending */
+#define RECVING_ROLE		0  /**< Transfer direction is receiving */
+
+/* Maximum transfer size */
+#define XIICPS_MAX_TRANSFER_SIZE	(255 - 3)
+
+/**************************** Type Definitions *******************************/
+
+/**
+* The handler data type allows the user to define a callback function to
+* respond to interrupt events in the system. This function is executed
+* in interrupt context, so amount of processing should be minimized.
+*
+* @param	CallBackRef is the callback reference passed in by the upper
+*		layer when setting the callback functions, and passed back to
+*		the upper layer when the callback is invoked. Its type is
+*		not important to the driver, so it is a void pointer.
+* @param	StatusEvent indicates one or more status events that occurred.
+*/
+typedef void (*XIicPs_IntrHandler) (void *CallBackRef, u32 StatusEvent);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;     /**< Unique ID  of device */
+	u32 BaseAddress;  /**< Base address of the device */
+	u32 InputClockHz; /**< Input clock frequency */
+} XIicPs_Config;
+
+/**
+ * The XIicPs driver instance data. The user is required to allocate a
+ * variable of this type for each IIC device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XIicPs_Config Config;	/* Configuration structure */
+	u32 IsReady;		/* Device is initialized and ready */
+	u32 Options;		/* Options set in the device */
+
+	u8 *SendBufferPtr;	/* Pointer to send buffer */
+	u8 *RecvBufferPtr;	/* Pointer to recv buffer */
+	int SendByteCount;	/* Number of bytes still expected to send */
+	int RecvByteCount;	/* Number of bytes still expected to receive */
+	int CurrByteCount;	/* No. of bytes expected in current transfer */
+
+	int UpdateTxSize;	/* If tx size register has to be updated */
+	int IsSend;		/* Whether master is sending or receiving */
+	int IsRepeatedStart;	/* Indicates if user set repeated start */
+
+	XIicPs_IntrHandler StatusHandler;  /* Event handler function */
+	void *CallBackRef;	/* Callback reference for event handler */
+} XIicPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+/****************************************************************************/
+/*
+*
+* Place one byte into the transmit FIFO.
+*
+* @param	InstancePtr is the instance of IIC
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XIicPs_SendByte(XIicPs *InstancePtr)
+*
+*****************************************************************************/
+#define XIicPs_SendByte(InstancePtr)					\
+{									\
+	 XIicPs_Out32((InstancePtr)->Config.BaseAddress			\
+			 + XIICPS_DATA_OFFSET, 				\
+	*(InstancePtr)->SendBufferPtr ++);				\
+	 (InstancePtr)->SendByteCount --;				\
+}
+
+/****************************************************************************/
+/*
+*
+* Receive one byte from FIFO.
+*
+* @param	InstancePtr is the instance of IIC
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		u8 XIicPs_RecvByte(XIicPs *InstancePtr)
+*
+*****************************************************************************/
+#define XIicPs_RecvByte(InstancePtr)					\
+{									\
+	*(InstancePtr)->RecvBufferPtr ++ =				\
+	 (u8)XIicPs_In32((InstancePtr)->Config.BaseAddress		\
+		  + XIICPS_DATA_OFFSET); 				\
+	 (InstancePtr)->RecvByteCount --; 				\
+}
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Function for configuration lookup, in xiicps_sinit.c
+ */
+XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Functions for general setup, in xiicps.c
+ */
+int XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config * Config,
+				  u32 EffectiveAddr);
+
+void XIicPs_Abort(XIicPs *InstancePtr);
+void XIicPs_Reset(XIicPs *InstancePtr);
+
+int XIicPs_BusIsBusy(XIicPs *InstancePtr);
+
+/*
+ * Functions for interrupts, in xiicps_intr.c
+ */
+void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef,
+				  XIicPs_IntrHandler FuncPtr);
+
+/*
+ * Functions for device as master, in xiicps_master.c
+ */
+void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount,
+		u16 SlaveAddr);
+void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount,
+		u16 SlaveAddr);
+int XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount,
+		u16 SlaveAddr);
+int XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount,
+		u16 SlaveAddr);
+void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr);
+void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr);
+void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr);
+
+/*
+ * Functions for device as slave, in xiicps_slave.c
+ */
+void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr);
+void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount);
+void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount);
+int XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount);
+int XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount);
+void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr);
+
+/*
+ * Functions for selftest, in xiicps_selftest.c
+ */
+int XIicPs_SelfTest(XIicPs *InstancePtr);
+
+/*
+ * Functions for setting and getting data rate, in xiicps_options.c
+ */
+int XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options);
+int XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options);
+u32 XIicPs_GetOptions(XIicPs *InstancePtr);
+
+int XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz);
+u32 XIicPs_GetSClk(XIicPs *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_g.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_g.c
new file mode 100644
index 000000000..df49cbb5b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_g.c
@@ -0,0 +1,32 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSM.
+* Version: 
+* DO NOT EDIT.
+*
+*  v (64-bit)
+SW Build (by ) on 
+Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xiicps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XIicPs_Config XIicPs_ConfigTable[] =
+{
+	{
+		XPAR_PS7_I2C_0_DEVICE_ID,
+		XPAR_PS7_I2C_0_BASEADDR,
+		XPAR_PS7_I2C_0_I2C_CLK_FREQ_HZ
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_hw.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_hw.c
new file mode 100644
index 000000000..bdb1a354f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_hw.c
@@ -0,0 +1,116 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_hw.c
+*
+* Contains implementation of required functions for providing the reset sequence
+* to the i2c interface
+*
+* 
 MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- --------------------------------------------
+* 1.04a kpc     11/07/13 First release
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps_hw.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+/*****************************************************************************/
+/**
+* This function perform the reset sequence to the given I2c interface by 
+* configuring the appropriate control bits in the I2c specifc registers
+* the i2cps reset squence involves the following steps
+*	Disable all the interuupts 
+*	Clear the status
+*	Clear FIFO's and disable hold bit
+*	Clear the line status
+*	Update relevant config registers with reset values
+*
+* @param   BaseAddress of the interface
+*
+* @return N/A
+*
+* @note 
+* This function will not modify the slcr registers that are relavant for 
+* I2c controller
+******************************************************************************/
+void XIicPs_ResetHw(u32 BaseAddress)
+{
+	u32 RegVal;
+	
+	/* Disable all the interrupts */
+	XIicPs_WriteReg(BaseAddress, XIICPS_IDR_OFFSET, XIICPS_IXR_ALL_INTR_MASK);
+	/* Clear the interrupt status */	
+	RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_ISR_OFFSET);
+	XIicPs_WriteReg(BaseAddress, XIICPS_ISR_OFFSET, RegVal);	
+	/* Clear the hold bit,master enable bit and ack bit */		
+	RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_CR_OFFSET);
+	RegVal &= ~(XIICPS_CR_HOLD_MASK|XIICPS_CR_MS_MASK|XIICPS_CR_ACKEN_MASK);
+	/* Clear the fifos */			
+	RegVal |= XIICPS_CR_CLR_FIFO_MASK;	
+	XIicPs_WriteReg(BaseAddress, XIICPS_CR_OFFSET, RegVal);	
+	/* Clear the timeout register */
+	XIicPs_WriteReg(BaseAddress, XIICPS_TIME_OUT_OFFSET, 0x0);	
+	/* Clear the transfer size register */	
+	XIicPs_WriteReg(BaseAddress, XIICPS_TRANS_SIZE_OFFSET, 0x0);
+	/* Clear the status register */	
+	RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_SR_OFFSET);
+	XIicPs_WriteReg(BaseAddress, XIICPS_SR_OFFSET, RegVal);	
+	/* Update the configuraqtion register with reset value */		
+	XIicPs_WriteReg(BaseAddress, XIICPS_CR_OFFSET, 0x0);		
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_hw.h
new file mode 100644
index 000000000..406892c7c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_hw.h
@@ -0,0 +1,388 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_hw.h
+*
+* This header file contains the hardware definition for an IIC device.
+* It includes register definitions and interface functions to read/write
+* the registers.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who 	Date     Changes
+* ----- ------  -------- -----------------------------------------------
+* 1.00a drg/jz  01/30/10 First release
+* 1.04a kpc		11/07/13 Added function prototype. 
+* 

+*
+******************************************************************************/
+#ifndef XIICPS_HW_H		/* prevent circular inclusions */
+#define XIICPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the IIC.
+ * @{
+ */
+#define XIICPS_CR_OFFSET		0x00  /**< 32-bit Control */
+#define XIICPS_SR_OFFSET		0x04  /**< Status */
+#define XIICPS_ADDR_OFFSET		0x08  /**< IIC Address */
+#define XIICPS_DATA_OFFSET		0x0C  /**< IIC FIFO Data */
+#define XIICPS_ISR_OFFSET		0x10  /**< Interrupt Status */
+#define XIICPS_TRANS_SIZE_OFFSET	0x14  /**< Transfer Size */
+#define XIICPS_SLV_PAUSE_OFFSET		0x18  /**< Slave monitor pause */
+#define XIICPS_TIME_OUT_OFFSET		0x1C  /**< Time Out */
+#define XIICPS_IMR_OFFSET		0x20  /**< Interrupt Enabled Mask */
+#define XIICPS_IER_OFFSET		0x24  /**< Interrupt Enable */
+#define XIICPS_IDR_OFFSET		0x28  /**< Interrupt Disable */
+/* @} */
+
+/** @name Control Register
+ *
+ * This register contains various control bits that
+ * affects the operation of the IIC controller. Read/Write.
+ * @{
+ */
+
+#define XIICPS_CR_DIV_A_MASK	0x0000C000 /**< Clock Divisor A */
+#define XIICPS_CR_DIV_A_SHIFT		14 /**< Clock Divisor A shift */
+#define XIICPS_DIV_A_MAX		4  /**< Maximum value of Divisor A */
+#define XIICPS_CR_DIV_B_MASK	0x00003F00 /**< Clock Divisor B */
+#define XIICPS_CR_DIV_B_SHIFT		8  /**< Clock Divisor B shift */
+#define XIICPS_CR_CLR_FIFO_MASK	0x00000040 /**< Clear FIFO, auto clears*/
+#define XIICPS_CR_SLVMON_MASK	0x00000020 /**< Slave monitor mode */
+#define XIICPS_CR_HOLD_MASK	0x00000010 /**<  Hold bus 1=Hold scl,
+						0=terminate transfer */
+#define XIICPS_CR_ACKEN_MASK	0x00000008  /**< Enable TX of ACK when
+						 Master receiver*/
+#define XIICPS_CR_NEA_MASK	0x00000004  /**< Addressing Mode 1=7 bit,
+						 0=10 bit */
+#define XIICPS_CR_MS_MASK	0x00000002  /**< Master mode bit 1=Master,
+						 0=Slave */
+#define XIICPS_CR_RD_WR_MASK	0x00000001  /**< Read or Write Master
+						 transfer  0=Transmitter,
+						 1=Receiver*/
+#define XIICPS_CR_RESET_VALUE		0   /**< Reset value of the Control
+						 register */
+/* @} */
+
+/** @name IIC Status Register
+ *
+ * This register is used to indicate status of the IIC controller. Read only
+ * @{
+ */
+#define XIICPS_SR_BA_MASK	0x00000100  /**< Bus Active Mask */
+#define XIICPS_SR_RXOVF_MASK	0x00000080  /**< Receiver Overflow Mask */
+#define XIICPS_SR_TXDV_MASK	0x00000040  /**< Transmit Data Valid Mask */
+#define XIICPS_SR_RXDV_MASK	0x00000020  /**< Receiver Data Valid Mask */
+#define XIICPS_SR_RXRW_MASK	0x00000008  /**< Receive read/write Mask */
+/* @} */
+
+/** @name IIC Address Register
+ *
+ * Normal addressing mode uses add[6:0]. Extended addressing mode uses add[9:0].
+ * A write access to this register always initiates a transfer if the IIC is in
+ * master mode. Read/Write
+ * @{
+ */
+#define XIICPS_ADDR_MASK	0x000003FF  /**< IIC Address Mask */
+/* @} */
+
+/** @name IIC Data Register
+ *
+ * When written to, the data register sets data to transmit. When read from, the
+ * data register reads the last received byte of data. Read/Write
+ * @{
+ */
+#define XIICPS_DATA_MASK	0x000000FF  /**< IIC Data Mask */
+/* @} */
+
+/** @name IIC Interrupt Registers
+ *
+ * IIC Interrupt Status Register
+ *
+ * This register holds the interrupt status flags for the IIC controller. Some
+ * of the flags are level triggered
+ * - i.e. are set as long as the interrupt condition exists.  Other flags are
+ *   edge triggered, which means they are set one the interrupt condition occurs
+ *   then remain set until they are cleared by software.
+ *   The interrupts are cleared by writing a one to the interrupt bit position
+ *   in the Interrupt Status Register. Read/Write.
+ *
+ * IIC Interrupt Enable Register
+ *
+ * This register is used to enable interrupt sources for the IIC controller.
+ * Writing a '1' to a bit in this register clears the corresponding bit in the
+ * IIC Interrupt Mask register.  Write only.
+ *
+ * IIC Interrupt Disable Register 
+ *
+ * This register is used to disable interrupt sources for the IIC controller.
+ * Writing a '1' to a bit in this register sets the corresponding bit in the
+ * IIC Interrupt Mask register. Write only.
+ *
+ * IIC Interrupt Mask Register
+ *
+ * This register shows the enabled/disabled status of each IIC controller
+ * interrupt source. A bit set to 1 will ignore the corresponding interrupt in
+ * the status register. A bit set to 0 means the interrupt is enabled.
+ * All mask bits are set and all interrupts are disabled after reset. Read only.
+ *
+ * All four registers have the same bit definitions. They are only defined once
+ * for each of the Interrupt Enable Register, Interrupt Disable Register,
+ * Interrupt Mask Register, and Interrupt Status Register
+ * @{
+ */
+
+#define XIICPS_IXR_ARB_LOST_MASK  0x00000200	 /**< Arbitration Lost Interrupt
+						   mask */
+#define XIICPS_IXR_RX_UNF_MASK    0x00000080	 /**< FIFO Recieve Underflow
+						   Interrupt mask */
+#define XIICPS_IXR_TX_OVR_MASK    0x00000040	 /**< Transmit Overflow
+						   Interrupt mask */
+#define XIICPS_IXR_RX_OVR_MASK    0x00000020	 /**< Receive Overflow Interrupt
+						   mask */
+#define XIICPS_IXR_SLV_RDY_MASK   0x00000010	 /**< Monitored Slave Ready
+						   Interrupt mask */
+#define XIICPS_IXR_TO_MASK        0x00000008	 /**< Transfer Time Out
+						   Interrupt mask */
+#define XIICPS_IXR_NACK_MASK      0x00000004	 /**< NACK Interrupt mask */
+#define XIICPS_IXR_DATA_MASK      0x00000002	 /**< Data Interrupt mask */
+#define XIICPS_IXR_COMP_MASK      0x00000001	 /**< Transfer Complete
+						   Interrupt mask */
+#define XIICPS_IXR_DEFAULT_MASK   0x000002FF	 /**< Default ISR Mask */
+#define XIICPS_IXR_ALL_INTR_MASK  0x000002FF	 /**< All ISR Mask */
+/* @} */
+
+
+/** @name IIC Transfer Size Register
+*
+* The register's meaning varies according to the operating mode as follows:
+*   - Master transmitter mode: number of data bytes still not transmitted minus
+*     one
+*   - Master receiver mode: number of data bytes that are still expected to be
+*     received
+*   - Slave transmitter mode: number of bytes remaining in the FIFO after the
+*     master terminates the transfer
+*   - Slave receiver mode: number of valid data bytes in the FIFO
+*
+* This register is cleared if CLR_FIFO bit in the control register is set.
+* Read/Write
+* @{
+*/
+#define XIICPS_TRANS_SIZE_MASK  0x0000003F /**< IIC Transfer Size Mask */
+#define XIICPS_FIFO_DEPTH          16	  /**< Number of bytes in the FIFO */
+#define XIICPS_DATA_INTR_DEPTH     14    /**< Number of bytes at DATA intr */
+/* @} */
+
+
+/** @name IIC Slave Monitor Pause Register
+*
+* This register is associated with the slave monitor mode of the I2C interface.
+* It is meaningful only when the module is in master mode and bit SLVMON in the
+* control register is set.
+*
+* This register defines the pause interval between consecutive attempts to
+* address the slave once a write to an I2C address register is done by the
+* host. It represents the number of sclk cycles minus one between two attempts.
+*
+* The reset value of the register is 0, which results in the master repeatedly
+* trying to access the slave immediately after unsuccessful attempt.
+* Read/Write
+* @{
+*/
+#define XIICPS_SLV_PAUSE_MASK    0x0000000F  /**< Slave monitor pause mask */
+/* @} */
+
+
+/** @name IIC Time Out Register
+*
+* The value of time out register represents the time out interval in number of
+* sclk cycles minus one.
+*
+* When the accessed slave holds the sclk line low for longer than the time out
+* period, thus prohibiting the I2C interface in master mode to complete the
+* current transfer, an interrupt is generated and TO interrupt flag is set.
+*
+* The reset value of the register is 0x1f.
+* Read/Write
+* @{
+ */
+#define XIICPS_TIME_OUT_MASK    0x000000FF    /**< IIC Time Out mask */
+#define XIICPS_TO_RESET_VALUE   0x0000001F    /**< IIC Time Out reset value */
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XIicPs_In32 Xil_In32
+#define XIicPs_Out32 Xil_Out32
+
+/****************************************************************************/
+/**
+* Read an IIC register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to select the specific register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XIicPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XIicPs_ReadReg(BaseAddress, RegOffset) \
+	XIicPs_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write an IIC register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to select the specific register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note	C-Style signature:
+*	void XIicPs_WriteReg(u32 BaseAddress, int RegOffset, u32 RegisterValue)
+*
+******************************************************************************/
+#define XIicPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+	XIicPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+/***************************************************************************/
+/**
+* Read the interrupt enable register.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	Current bit mask that represents currently enabled interrupts.
+*
+* @note		C-Style signature:
+*		u32 XIicPs_ReadIER(u32 BaseAddress)
+*
+******************************************************************************/
+#define XIicPs_ReadIER(BaseAddress) \
+	XIicPs_ReadReg((BaseAddress),  XIICPS_IER_OFFSET)
+
+/***************************************************************************/
+/**
+* Write to the interrupt enable register.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @param	IntrMask is the interrupts to be enabled.
+*
+* @return	None.
+*
+* @note	C-Style signature:
+*	void XIicPs_EnabledInterrupts(u32 BaseAddress, u32 IntrMask)
+*
+******************************************************************************/
+#define XIicPs_EnableInterrupts(BaseAddress, IntrMask) \
+	XIicPs_WriteReg((BaseAddress), XIICPS_IER_OFFSET, (IntrMask))
+
+/***************************************************************************/
+/**
+* Disable all interrupts.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XIicPs_DisableAllInterrupts(u32 BaseAddress)
+*
+******************************************************************************/
+#define XIicPs_DisableAllInterrupts(BaseAddress) \
+	XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
+		XIICPS_IXR_ALL_INTR_MASK)
+
+/***************************************************************************/
+/**
+* Disable selected interrupts.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @param	IntrMask is the interrupts to be disabled.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XIicPs_DisableInterrupts(u32 BaseAddress, u32 IntrMask)
+*
+******************************************************************************/
+#define XIicPs_DisableInterrupts(BaseAddress, IntrMask) \
+	XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
+		(IntrMask))
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+/*
+ * Perform reset operation to the I2c interface
+ */
+void XIicPs_ResetHw(u32 BaseAddr);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_intr.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_intr.c
new file mode 100644
index 000000000..092e0fa98
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_intr.c
@@ -0,0 +1,106 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_intr.c
+*
+* Contains functions of the XIicPs driver for interrupt-driven transfers.
+* See xiicps.h for a detailed description of the device and driver.
+*
+* 
 MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- -----------------------------------------------
+* 1.00a drg/jz  01/30/10 First release
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************* Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function sets the status callback function, the status handler, which the
+* driver calls when it encounters conditions that should be reported to the
+* higher layer software. The handler executes in an interrupt context, so
+* the amount of processing should be minimized
+*
+* Refer to the xiicps.h file for a list of the Callback events. The events are
+* defined to start with XIICPS_EVENT_*.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	CallBackRef is the upper layer callback reference passed back
+*		when the callback function is invoked.
+* @param	FuncPtr is the pointer to the callback function.
+*
+* @return	None.
+*
+* @note
+*
+* The handler is called within interrupt context, so it should finish its
+* work quickly.
+*
+******************************************************************************/
+void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef,
+				  XIicPs_IntrHandler FuncPtr)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FuncPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	InstancePtr->StatusHandler = FuncPtr;
+	InstancePtr->CallBackRef = CallBackRef;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_master.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_master.c
new file mode 100644
index 000000000..752c43253
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_master.c
@@ -0,0 +1,885 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_master.c
+*
+* Handles master mode transfers.
+*
+* 
 MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---  -------- ---------------------------------------------
+* 1.00a jz   01/30/10 First release
+* 1.00a sdm  09/21/11 Updated the XIicPs_SetupMaster to not check for
+*		      Bus Busy condition when the Hold Bit is set.
+* 1.01a sg   03/30/12 Fixed an issue in XIicPs_MasterSendPolled where a
+*		      check for transfer completion is added, which indicates
+*			 the completion of current transfer.
+* 2.0   hk   03/07/14 Added check for error status in the while loop that
+*                     checks for completion. CR# 762244, 764875.
+* 2.1   hk   04/24/14 Fix for CR# 789821 to handle >14 byte transfers.
+*                     Fix for CR# 761060 - provision for repeated start.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+int TransmitFifoFill(XIicPs *InstancePtr);
+
+static int XIicPs_SetupMaster(XIicPs *InstancePtr, int Role);
+static void MasterSendData(XIicPs *InstancePtr);
+
+/************************* Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* This function initiates an interrupt-driven send in master mode.
+*
+* It tries to send the first FIFO-full of data, then lets the interrupt
+* handler to handle the rest of the data if there is any.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the send buffer.
+* @param	ByteCount is the number of bytes to be sent.
+* @param	SlaveAddr is the address of the slave we are sending to.
+*
+* @return	None.
+*
+* @note		This send routine is for interrupt-driven transfer only.
+*
+ ****************************************************************************/
+void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount,
+		 u16 SlaveAddr)
+{
+	u32 BaseAddr;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(MsgPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr);
+
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->SendBufferPtr = MsgPtr;
+	InstancePtr->SendByteCount = ByteCount;
+	InstancePtr->RecvBufferPtr = NULL;
+	InstancePtr->IsSend = 1;
+
+	/*
+	 * Set repeated start if sending more than FIFO of data.
+	 */
+	if ((InstancePtr->IsRepeatedStart) ||
+		(ByteCount > XIICPS_FIFO_DEPTH)) {
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+			XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) |
+				XIICPS_CR_HOLD_MASK);
+	}
+
+	/*
+	 * Setup as a master sending role.
+	 */
+	XIicPs_SetupMaster(InstancePtr, SENDING_ROLE);
+
+	/*
+	 * Do the address transfer to notify the slave.
+	 */
+	XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
+
+	TransmitFifoFill(InstancePtr);
+
+	XIicPs_EnableInterrupts(BaseAddr,
+		XIICPS_IXR_NACK_MASK | XIICPS_IXR_COMP_MASK |
+		XIICPS_IXR_ARB_LOST_MASK);
+}
+
+/*****************************************************************************/
+/**
+* This function initiates an interrupt-driven receive in master mode.
+*
+* It sets the transfer size register so the slave can send data to us.
+* The rest of the work is managed by interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the receive buffer.
+* @param	ByteCount is the number of bytes to be received.
+* @param	SlaveAddr is the address of the slave we are receiving from.
+*
+* @return	None.
+*
+* @note		This receive routine is for interrupt-driven transfer only.
+*
+****************************************************************************/
+void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount,
+		 u16 SlaveAddr)
+{
+	u32 BaseAddr;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(MsgPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->RecvBufferPtr = MsgPtr;
+	InstancePtr->RecvByteCount = ByteCount;
+	InstancePtr->CurrByteCount = ByteCount;
+	InstancePtr->SendBufferPtr = NULL;
+	InstancePtr->IsSend = 0;
+	InstancePtr->UpdateTxSize = 0;
+
+	if ((ByteCount > XIICPS_DATA_INTR_DEPTH) ||
+		(InstancePtr->IsRepeatedStart))
+	{
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) |
+						XIICPS_CR_HOLD_MASK);
+	}
+
+	/*
+	 * Initialize for a master receiving role.
+	 */
+	XIicPs_SetupMaster(InstancePtr, RECVING_ROLE);
+
+	/*
+	 * Do the address transfer to signal the slave.
+	 */
+	XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
+
+	/*
+	 * Setup the transfer size register so the slave knows how much
+	 * to send to us.
+	 */
+	if (ByteCount > XIICPS_MAX_TRANSFER_SIZE) {
+		XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
+				XIICPS_MAX_TRANSFER_SIZE);
+		InstancePtr->CurrByteCount = XIICPS_MAX_TRANSFER_SIZE;
+		InstancePtr->UpdateTxSize = 1;
+	}else {
+		XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
+			 ByteCount);
+	}
+
+	XIicPs_EnableInterrupts(BaseAddr,
+		XIICPS_IXR_NACK_MASK | XIICPS_IXR_DATA_MASK |
+		XIICPS_IXR_RX_OVR_MASK | XIICPS_IXR_COMP_MASK |
+		XIICPS_IXR_ARB_LOST_MASK);
+}
+
+/*****************************************************************************/
+/**
+* This function initiates a polled mode send in master mode.
+*
+* It sends data to the FIFO and waits for the slave to pick them up.
+* If slave fails to remove data from FIFO, the send fails with
+* time out.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the send buffer.
+* @param	ByteCount is the number of bytes to be sent.
+* @param	SlaveAddr is the address of the slave we are sending to.
+*
+* @return
+*		- XST_SUCCESS if everything went well.
+*		- XST_FAILURE if timed out.
+*
+* @note		This send routine is for polled mode transfer only.
+*
+****************************************************************************/
+int XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr,
+		 int ByteCount, u16 SlaveAddr)
+{
+	u32 IntrStatusReg;
+	u32 StatusReg;
+	u32 BaseAddr;
+	u32 Intrs;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(MsgPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(XIICPS_ADDR_MASK >= SlaveAddr);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->SendBufferPtr = MsgPtr;
+	InstancePtr->SendByteCount = ByteCount;
+
+	if ((InstancePtr->IsRepeatedStart) ||
+		(ByteCount > XIICPS_FIFO_DEPTH)) {
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) |
+						XIICPS_CR_HOLD_MASK);
+	}
+
+	XIicPs_SetupMaster(InstancePtr, SENDING_ROLE);
+
+	XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
+
+	/*
+	 * Intrs keeps all the error-related interrupts.
+	 */
+	Intrs = XIICPS_IXR_ARB_LOST_MASK | XIICPS_IXR_TX_OVR_MASK |
+		XIICPS_IXR_NACK_MASK;
+
+	/*
+	 * Clear the interrupt status register before use it to monitor.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	/*
+	 * Transmit first FIFO full of data.
+	 */
+	TransmitFifoFill(InstancePtr);
+
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+
+	/*
+	 * Continue sending as long as there is more data and
+	 * there are no errors.
+	 */
+	while ((InstancePtr->SendByteCount > 0) &&
+		((IntrStatusReg & Intrs) == 0)) {
+		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+		/*
+		 * Wait until transmit FIFO is empty.
+		 */
+		if ((StatusReg & XIICPS_SR_TXDV_MASK) != 0) {
+			IntrStatusReg = XIicPs_ReadReg(BaseAddr,
+					XIICPS_ISR_OFFSET);
+			continue;
+		}
+
+		/*
+		 * Send more data out through transmit FIFO.
+		 */
+		TransmitFifoFill(InstancePtr);
+	}
+
+	/*
+	 * Check for completion of transfer.
+	 */
+	while ((IntrStatusReg & XIICPS_IXR_COMP_MASK) != XIICPS_IXR_COMP_MASK){
+
+		IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+		/*
+		 * If there is an error, tell the caller.
+		 */
+		if ((IntrStatusReg & Intrs) != 0) {
+			return XST_FAILURE;
+		}
+	}
+
+	if (!(InstancePtr->IsRepeatedStart)) {
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr,XIICPS_CR_OFFSET) &
+						(~XIICPS_CR_HOLD_MASK));
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* This function initiates a polled mode receive in master mode.
+*
+* It repeatedly sets the transfer size register so the slave can
+* send data to us. It polls the data register for data to come in.
+* If slave fails to send us data, it fails with time out.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the receive buffer.
+* @param	ByteCount is the number of bytes to be received.
+* @param	SlaveAddr is the address of the slave we are receiving from.
+*
+* @return
+*		- XST_SUCCESS if everything went well.
+*		- XST_FAILURE if timed out.
+*
+* @note		This receive routine is for polled mode transfer only.
+*
+****************************************************************************/
+int XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
+				int ByteCount, u16 SlaveAddr)
+{
+	u32 IntrStatusReg;
+	u32 Intrs;
+	u32 StatusReg;
+	u32 BaseAddr;
+	int IsHold = 0;
+	int UpdateTxSize = 0;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(MsgPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(XIICPS_ADDR_MASK >= SlaveAddr);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->RecvBufferPtr = MsgPtr;
+	InstancePtr->RecvByteCount = ByteCount;
+
+	if((ByteCount > XIICPS_DATA_INTR_DEPTH) ||
+		(InstancePtr->IsRepeatedStart))
+	{
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) |
+						XIICPS_CR_HOLD_MASK);
+		IsHold = 1;
+	}
+
+	XIicPs_SetupMaster(InstancePtr, RECVING_ROLE);
+
+	/*
+	 * Clear the interrupt status register before use it to monitor.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
+
+	/*
+	 * Set up the transfer size register so the slave knows how much
+	 * to send to us.
+	 */
+	if (ByteCount > XIICPS_MAX_TRANSFER_SIZE) {
+		XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
+				XIICPS_MAX_TRANSFER_SIZE);
+		ByteCount = XIICPS_MAX_TRANSFER_SIZE;
+		UpdateTxSize = 1;
+	}else {
+		XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
+			 ByteCount);
+	}
+
+	/*
+	 * Intrs keeps all the error-related interrupts.
+	 */
+	Intrs = XIICPS_IXR_ARB_LOST_MASK | XIICPS_IXR_RX_OVR_MASK |
+			XIICPS_IXR_RX_UNF_MASK | XIICPS_IXR_NACK_MASK;
+
+	/*
+	 * Poll the interrupt status register to find the errors.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	while ((InstancePtr->RecvByteCount > 0) &&
+			((IntrStatusReg & Intrs) == 0)) {
+		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+		while (StatusReg & XIICPS_SR_RXDV_MASK) {
+			if ((InstancePtr->RecvByteCount <
+				XIICPS_DATA_INTR_DEPTH) && IsHold &&
+				(!(InstancePtr->IsRepeatedStart))) {
+				IsHold = 0;
+				XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+						XIicPs_ReadReg(BaseAddr,
+						XIICPS_CR_OFFSET) &
+						(~XIICPS_CR_HOLD_MASK));
+			}
+			XIicPs_RecvByte(InstancePtr);
+			ByteCount --;
+
+			if (UpdateTxSize &&
+				(ByteCount == XIICPS_FIFO_DEPTH + 1))
+				break;
+
+			StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+		}
+
+		if (UpdateTxSize && (ByteCount == XIICPS_FIFO_DEPTH + 1)) {
+			/*
+			 * wait while fifo is full
+			 */
+			while(XIicPs_ReadReg(BaseAddr,
+				XIICPS_TRANS_SIZE_OFFSET) !=
+				(ByteCount - XIICPS_FIFO_DEPTH));
+
+			if ((InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH) >
+				XIICPS_MAX_TRANSFER_SIZE) {
+
+				XIicPs_WriteReg(BaseAddr,
+					XIICPS_TRANS_SIZE_OFFSET,
+					XIICPS_MAX_TRANSFER_SIZE);
+				ByteCount = XIICPS_MAX_TRANSFER_SIZE +
+						XIICPS_FIFO_DEPTH;
+			}else {
+				XIicPs_WriteReg(BaseAddr,
+					XIICPS_TRANS_SIZE_OFFSET,
+					InstancePtr->RecvByteCount -
+					XIICPS_FIFO_DEPTH);
+				UpdateTxSize = 0;
+				ByteCount = InstancePtr->RecvByteCount;
+			}
+		}
+
+		IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	}
+
+	if (!(InstancePtr->IsRepeatedStart)) {
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr,XIICPS_CR_OFFSET) &
+						(~XIICPS_CR_HOLD_MASK));
+	}
+
+	if (IntrStatusReg & Intrs) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* This function enables the slave monitor mode.
+*
+* It enables slave monitor in the control register and enables
+* slave ready interrupt. It then does an address transfer to slave.
+* Interrupt handler will signal the caller if slave responds to
+* the address transfer.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	SlaveAddr is the address of the slave we want to contact.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr)
+{
+	u32 BaseAddr;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	/*
+	 * Enable slave monitor mode in control register.
+	 */
+	XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+	XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) |
+				XIICPS_CR_MS_MASK |
+				XIICPS_CR_NEA_MASK |
+				XIICPS_CR_SLVMON_MASK );
+
+	/*
+	 * Set up interrupt flag for slave monitor interrupt.
+	 */
+	XIicPs_EnableInterrupts(BaseAddr, XIICPS_IXR_NACK_MASK |
+				XIICPS_IXR_SLV_RDY_MASK);
+
+	/*
+	 * Initialize the slave monitor register.
+	 */
+	XIicPs_WriteReg(BaseAddr, XIICPS_SLV_PAUSE_OFFSET, 0xF);
+
+	/*
+	 * Set the slave address to start the slave address transmission.
+	 */
+	XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
+
+	return;
+}
+
+/*****************************************************************************/
+/**
+* This function disables slave monitor mode.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr)
+{
+	u32 BaseAddr;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	/*
+	 * Clear slave monitor control bit.
+	 */
+	XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+		XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET)
+			& (~XIICPS_CR_SLVMON_MASK));
+
+	/*
+	 * Clear interrupt flag for slave monitor interrupt.
+	 */
+	XIicPs_DisableInterrupts(BaseAddr, XIICPS_IXR_SLV_RDY_MASK);
+
+	return;
+}
+
+/*****************************************************************************/
+/**
+* The interrupt handler for the master mode. It does the protocol handling for
+* the interrupt-driven transfers.
+*
+* Completion events and errors are signaled to upper layer for proper handling.
+*
+* 
+* The interrupts that are handled are:
+* - DATA
+*	This case is handled only for master receive data.
+*	The master has to request for more data (if there is more data to
+*	receive) and read the data from the FIFO .
+*
+* - COMP
+*	If the Master is transmitting data and there is more data to be
+*	sent then the data is written to the FIFO. If there is no more data to
+*	be transmitted then a completion event is signalled to the upper layer
+*	by calling the callback handler.
+*
+*	If the Master is receiving data then the data is read from the FIFO and
+*	the Master has to request for more data (if there is more data to
+*	receive). If all the data has been received then a completion event
+*	is signalled to the upper layer by calling the callback handler.
+*	It is an error if the amount of received data is more than expected.
+*
+* - NAK and SLAVE_RDY
+*	This is signalled to the upper layer by calling the callback handler.
+*
+* - All Other interrupts
+*	These interrupts are marked as error. This is signalled to the upper
+*	layer by calling the callback handler.
+*
+* 

+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note 	None.
+*
+****************************************************************************/
+void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr)
+{
+	u32 IntrStatusReg;
+	u32 StatusEvent = 0;
+	u32 BaseAddr;
+	int ByteCnt;
+	int IsHold;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	/*
+	 * Read the Interrupt status register.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr,
+					 XIICPS_ISR_OFFSET);
+
+	/*
+	 * Write the status back to clear the interrupts so no events are
+	 * missed while processing this interrupt.
+	 */
+	XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	/*
+	 * Use the Mask register AND with the Interrupt Status register so
+	 * disabled interrupts are not processed.
+	 */
+	IntrStatusReg &= ~(XIicPs_ReadReg(BaseAddr, XIICPS_IMR_OFFSET));
+
+	ByteCnt = InstancePtr->CurrByteCount;
+
+	IsHold = 0;
+	if (XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) & XIICPS_CR_HOLD_MASK) {
+		IsHold = 1;
+	}
+
+	/*
+	 * Send
+	 */
+	if ((InstancePtr->IsSend) &&
+		(0 != (IntrStatusReg & XIICPS_IXR_COMP_MASK))) {
+		if (InstancePtr->SendByteCount > 0) {
+			MasterSendData(InstancePtr);
+		} else {
+			StatusEvent |= XIICPS_EVENT_COMPLETE_SEND;
+		}
+	}
+
+
+	/*
+	 * Receive
+	 */
+	if ((!(InstancePtr->IsSend)) &&
+		((0 != (IntrStatusReg & XIICPS_IXR_DATA_MASK)) ||
+		(0 != (IntrStatusReg & XIICPS_IXR_COMP_MASK)))){
+
+		while (XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET) &
+				XIICPS_SR_RXDV_MASK) {
+			if ((InstancePtr->RecvByteCount <
+				XIICPS_DATA_INTR_DEPTH) && IsHold &&
+				(!(InstancePtr->IsRepeatedStart))) {
+				IsHold = 0;
+				XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+						XIicPs_ReadReg(BaseAddr,
+						XIICPS_CR_OFFSET) &
+						(~XIICPS_CR_HOLD_MASK));
+			}
+			XIicPs_RecvByte(InstancePtr);
+			ByteCnt--;
+
+			if (InstancePtr->UpdateTxSize &&
+				(ByteCnt == XIICPS_FIFO_DEPTH + 1))
+				break;
+		}
+
+		if (InstancePtr->UpdateTxSize &&
+			(ByteCnt == XIICPS_FIFO_DEPTH + 1)) {
+			/*
+			 * wait while fifo is full
+			 */
+			while(XIicPs_ReadReg(BaseAddr,
+				XIICPS_TRANS_SIZE_OFFSET) !=
+				(ByteCnt - XIICPS_FIFO_DEPTH));
+
+			if ((InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH) >
+				XIICPS_MAX_TRANSFER_SIZE) {
+
+				XIicPs_WriteReg(BaseAddr,
+					XIICPS_TRANS_SIZE_OFFSET,
+					XIICPS_MAX_TRANSFER_SIZE);
+				ByteCnt = XIICPS_MAX_TRANSFER_SIZE +
+						XIICPS_FIFO_DEPTH;
+			}else {
+				XIicPs_WriteReg(BaseAddr,
+					XIICPS_TRANS_SIZE_OFFSET,
+					InstancePtr->RecvByteCount -
+					XIICPS_FIFO_DEPTH);
+				InstancePtr->UpdateTxSize = 0;
+				ByteCnt = InstancePtr->RecvByteCount;
+			}
+		}
+		InstancePtr->CurrByteCount = ByteCnt;
+	}
+
+	if ((!(InstancePtr->IsSend)) &&
+		(0 != (IntrStatusReg & XIICPS_IXR_COMP_MASK))) {
+		/*
+		 * If all done, tell the application.
+		 */
+		if (InstancePtr->RecvByteCount == 0){
+			if (!(InstancePtr->IsRepeatedStart)) {
+				XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+						XIicPs_ReadReg(BaseAddr,
+						XIICPS_CR_OFFSET) &
+						(~XIICPS_CR_HOLD_MASK));
+			}
+			StatusEvent |= XIICPS_EVENT_COMPLETE_RECV;
+		}
+	}
+
+
+	/*
+	 * Slave ready interrupt, it is only meaningful for master mode.
+	 */
+	if (0 != (IntrStatusReg & XIICPS_IXR_SLV_RDY_MASK)) {
+		StatusEvent |= XIICPS_EVENT_SLAVE_RDY;
+	}
+
+	if (0 != (IntrStatusReg & XIICPS_IXR_NACK_MASK)) {
+		if (!(InstancePtr->IsRepeatedStart)) {
+			XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+					XIicPs_ReadReg(BaseAddr,
+					XIICPS_CR_OFFSET) &
+					(~XIICPS_CR_HOLD_MASK));
+		}
+		StatusEvent |= XIICPS_EVENT_NACK;
+	}
+
+	/*
+	 * All other interrupts are treated as error.
+	 */
+	if (0 != (IntrStatusReg & (XIICPS_IXR_NACK_MASK |
+			XIICPS_IXR_ARB_LOST_MASK | XIICPS_IXR_RX_UNF_MASK |
+			XIICPS_IXR_TX_OVR_MASK | XIICPS_IXR_RX_OVR_MASK))) {
+		if (!(InstancePtr->IsRepeatedStart)) {
+			XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+					XIicPs_ReadReg(BaseAddr,
+					XIICPS_CR_OFFSET) &
+					(~XIICPS_CR_HOLD_MASK));
+		}
+		StatusEvent |= XIICPS_EVENT_ERROR;
+	}
+
+	/*
+	 * Signal application if there are any events.
+	 */
+	if (0 != StatusEvent) {
+		InstancePtr->StatusHandler(InstancePtr->CallBackRef,
+					   StatusEvent);
+	}
+
+}
+
+/*****************************************************************************/
+/*
+* This function prepares a device to transfers as a master.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @param	Role specifies whether the device is sending or receiving.
+*
+* @return
+*		- XST_SUCCESS if everything went well.
+*		- XST_FAILURE if bus is busy.
+*
+* @note		Interrupts are always disabled, device which needs to use
+*		interrupts needs to setup interrupts after this call.
+*
+****************************************************************************/
+static int XIicPs_SetupMaster(XIicPs *InstancePtr, int Role)
+{
+	u32 ControlReg;
+	u32 BaseAddr;
+	u32 EnabledIntr = 0x0;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	ControlReg = XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET);
+
+
+	/*
+	 * Only check if bus is busy when repeated start option is not set.
+	 */
+	if ((ControlReg & XIICPS_CR_HOLD_MASK) == 0) {
+		if (XIicPs_BusIsBusy(InstancePtr)) {
+			return XST_FAILURE;
+		}
+	}
+
+	/*
+	 * Set up master, AckEn, nea and also clear fifo.
+	 */
+	ControlReg |= XIICPS_CR_ACKEN_MASK | XIICPS_CR_CLR_FIFO_MASK |
+		 	XIICPS_CR_NEA_MASK | XIICPS_CR_MS_MASK;
+
+	if (Role == RECVING_ROLE) {
+		ControlReg |= XIICPS_CR_RD_WR_MASK;
+		EnabledIntr = XIICPS_IXR_DATA_MASK |XIICPS_IXR_RX_OVR_MASK;
+	}else {
+		ControlReg &= ~XIICPS_CR_RD_WR_MASK;
+	}
+	EnabledIntr |= XIICPS_IXR_COMP_MASK | XIICPS_IXR_ARB_LOST_MASK;
+
+	XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, ControlReg);
+
+	XIicPs_DisableAllInterrupts(BaseAddr);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/*
+* This function handles continuation of sending data. It is invoked
+* from interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+static void MasterSendData(XIicPs *InstancePtr)
+{
+	TransmitFifoFill(InstancePtr);
+
+	/*
+	 * Clear hold bit if done, so stop can be sent out.
+	 */
+	if (InstancePtr->SendByteCount == 0) {
+
+		/*
+		 * If user has enabled repeated start as an option,
+		 * do not disable it.
+		 */
+		if (!(InstancePtr->IsRepeatedStart)) {
+
+			XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XIICPS_CR_OFFSET) & ~ XIICPS_CR_HOLD_MASK);
+		}
+	}
+
+	return;
+}
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_options.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_options.c
new file mode 100644
index 000000000..0a3bed959
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_options.c
@@ -0,0 +1,495 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_options.c
+*
+* Contains functions for the configuration of the XIccPs driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- -----------------------------------------------
+* 1.00a drg/jz  01/30/10 First release
+* 1.02a sg	08/29/12 Updated the logic to arrive at the best divisors
+*			 to achieve I2C clock with minimum error.
+*			 This is a fix for CR #674195
+* 1.03a hk  05/04/13 Initialized BestDivA and BestDivB to 0.
+*			 This is fix for CR#704398 to remove warning.
+* 2.0   hk  03/07/14 Limited frequency set when 100KHz or 400KHz is
+*                    selected. This is a hardware limitation. CR#779290.
+* 2.1   hk  04/24/14 Fix for CR# 761060 - provision for repeated start.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+/*
+ * Create the table of options which are processed to get/set the device
+ * options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+typedef struct {
+		u32 Option;
+		u32 Mask;
+} OptionsMap;
+
+static OptionsMap OptionsTable[] = {
+		{XIICPS_7_BIT_ADDR_OPTION, XIICPS_CR_NEA_MASK},
+		{XIICPS_10_BIT_ADDR_OPTION, XIICPS_CR_NEA_MASK},
+		{XIICPS_SLAVE_MON_OPTION, XIICPS_CR_SLVMON_MASK},
+		{XIICPS_REP_START_OPTION, XIICPS_CR_HOLD_MASK},
+};
+
+#define XIICPS_NUM_OPTIONS      (sizeof(OptionsTable) / sizeof(OptionsMap))
+
+/*****************************************************************************/
+/**
+*
+* This function sets the options for the IIC device driver. The options control
+* how the device behaves relative to the IIC bus. The device must be idle
+* rather than busy transferring data before setting these device options.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	Options contains the specified options to be set. This is a bit
+*		mask where a 1 means to turn the option on. One or more bit
+*		values may be contained in the mask. See the bit definitions
+*		named XIICPS_*_OPTION in xiicps.h.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_IS_STARTED if the device is currently transferring
+*		data. The transfer must complete or be aborted before setting
+*		options.
+*
+* @note		None.
+*
+******************************************************************************/
+int XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options)
+{
+	u32 ControlReg;
+	unsigned int Index;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XIICPS_CR_OFFSET);
+
+	/*
+	 * If repeated start option is requested, set the flag.
+	 * The hold bit in CR will be written by driver when the next transfer
+	 * is initiated.
+	 */
+	if (Options & XIICPS_REP_START_OPTION) {
+		InstancePtr->IsRepeatedStart = 1;
+		Options = Options & (~XIICPS_REP_START_OPTION);
+	}
+
+	/*
+	 * Loop through the options table, turning the option on.
+	 */
+	for (Index = 0; Index < XIICPS_NUM_OPTIONS; Index++) {
+ 		if (Options & OptionsTable[Index].Option) {
+			/*
+			 * 10-bit option is specially treated, because it is
+			 * using the 7-bit option, so turning it on means
+			 * turning 7-bit option off.
+			 */
+			if (OptionsTable[Index].Option &
+				XIICPS_10_BIT_ADDR_OPTION) {
+				/* Turn 7-bit off */
+				ControlReg &= ~OptionsTable[Index].Mask;
+ 			} else {
+				/* Turn 7-bit on */
+				ControlReg |= OptionsTable[Index].Mask;
+			}
+		}
+	}
+
+	/*
+	 * Now write to the control register. Leave it to the upper layers
+	 * to restart the device.
+	 */
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
+			  ControlReg);
+
+	/*
+	 * Keep a copy of what options this instance has.
+	 */
+	InstancePtr->Options = XIicPs_GetOptions(InstancePtr);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function clears the options for the IIC device driver. The options
+* control how the device behaves relative to the IIC bus. The device must be
+* idle rather than busy transferring data before setting these device options.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	Options contains the specified options to be cleared. This is a
+*		bit mask where a 1 means to turn the option off. One or more bit
+*		values may be contained in the mask. See the bit definitions
+*		named XIICPS_*_OPTION in xiicps.h.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_IS_STARTED if the device is currently transferring
+*		data. The transfer must complete or be aborted before setting
+*		options.
+*
+* @note		None
+*
+******************************************************************************/
+int XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options)
+{
+	u32 ControlReg;
+	unsigned int Index;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XIICPS_CR_OFFSET);
+
+	/*
+	 * If repeated start option is cleared, set the flag.
+	 * The hold bit in CR will be cleared by driver when the
+	 * following transfer ends.
+	 */
+	if (Options & XIICPS_REP_START_OPTION) {
+		InstancePtr->IsRepeatedStart = 0;
+		Options = Options & (~XIICPS_REP_START_OPTION);
+	}
+
+	/*
+	 * Loop through the options table and clear the specified options.
+	 */
+	for (Index = 0; Index < XIICPS_NUM_OPTIONS; Index++) {
+ 		if (Options & OptionsTable[Index].Option) {
+
+			/*
+			 * 10-bit option is specially treated, because it is
+			 * using the 7-bit option, so clearing it means turning
+			 * 7-bit option on.
+			 */
+			if (OptionsTable[Index].Option &
+						XIICPS_10_BIT_ADDR_OPTION) {
+
+				/* Turn 7-bit on */
+				ControlReg |= OptionsTable[Index].Mask;
+ 			} else {
+
+				/* Turn 7-bit off */
+				ControlReg &= ~OptionsTable[Index].Mask;
+			}
+		}
+	}
+
+
+	/*
+	 * Now write the control register. Leave it to the upper layers
+	 * to restart the device.
+	 */
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
+			  ControlReg);
+
+	/*
+	 * Keep a copy of what options this instance has.
+	 */
+	InstancePtr->Options = XIicPs_GetOptions(InstancePtr);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the options for the IIC device. The options control how
+* the device behaves relative to the IIC bus.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	32 bit mask of the options, where a 1 means the option is on,
+*		and a 0 means to the option is off. One or more bit values may
+*		be contained in the mask. See the bit definitions named
+* 		XIICPS_*_OPTION in the file xiicps.h.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XIicPs_GetOptions(XIicPs *InstancePtr)
+{
+	u32 OptionsFlag = 0;
+	u32 ControlReg;
+	unsigned int Index;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read control register to find which options are currently set.
+	 */
+	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XIICPS_CR_OFFSET);
+
+	/*
+	 * Loop through the options table to determine which options are set.
+	 */
+	for (Index = 0; Index < XIICPS_NUM_OPTIONS; Index++) {
+		if (ControlReg & OptionsTable[Index].Mask) {
+			OptionsFlag |= OptionsTable[Index].Option;
+		}
+		if ((ControlReg & XIICPS_CR_NEA_MASK) == 0) {
+			OptionsFlag |= XIICPS_10_BIT_ADDR_OPTION;
+		}
+	}
+
+	if (InstancePtr->IsRepeatedStart) {
+		OptionsFlag |= XIICPS_REP_START_OPTION;
+	}
+	return OptionsFlag;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the serial clock rate for the IIC device. The device
+* must be idle rather than busy transferring data before setting these device
+* options.
+*
+* The data rate is set by values in the control register. The formula for
+* determining the correct register values is:
+* Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
+* See the hardware data sheet for a full explanation of setting the serial
+* clock rate.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	FsclHz is the clock frequency in Hz. The two most common clock
+*		rates are 100KHz and 400KHz.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_IS_STARTED if the device is currently transferring
+*		data. The transfer must complete or be aborted before setting
+*		options.
+*		- XST_FAILURE if the Fscl frequency can not be set.
+*
+* @note		The clock can not be faster than the input clock divide by 22.
+*
+******************************************************************************/
+int XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz)
+{
+	u32 Div_a;
+	u32 Div_b;
+	u32 ActualFscl;
+	u32 Temp;
+	u32 TempLimit;
+	u32 LastError;
+	u32 BestError;
+	u32 CurrentError;
+	u32 ControlReg;
+	u32 CalcDivA;
+	u32 CalcDivB;
+	u32 BestDivA = 0;
+	u32 BestDivB = 0;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(FsclHz > 0);
+
+	if (0 != XIicPs_In32((InstancePtr->Config.BaseAddress) +
+					XIICPS_TRANS_SIZE_OFFSET)) {
+		return XST_DEVICE_IS_STARTED;
+	}
+
+	/*
+	 * Assume Div_a is 0 and calculate (divisor_a+1) x (divisor_b+1).
+	 */
+	Temp = (InstancePtr->Config.InputClockHz) / (22 * FsclHz);
+
+	/*
+	 * If the answer is negative or 0, the Fscl input is out of range.
+	 */
+	if (0 == Temp) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * If frequency 400KHz is selected, 384.6KHz should be set.
+	 * If frequency 100KHz is selected, 90KHz should be set.
+	 * This is due to a hardware limitation.
+	 */
+	if(FsclHz > 384600) {
+		FsclHz = 384600;
+	}
+
+	if((FsclHz <= 100000) && (FsclHz > 90000)) {
+		FsclHz = 90000;
+	}
+
+	/*
+	 * TempLimit helps in iterating over the consecutive value of Temp to
+	 * find the closest clock rate achievable with divisors.
+	 * Iterate over the next value only if fractional part is involved.
+	 */
+	TempLimit = ((InstancePtr->Config.InputClockHz) % (22 * FsclHz)) ?
+							Temp + 1 : Temp;
+	BestError = FsclHz;
+
+	for ( ; Temp <= TempLimit ; Temp++)
+	{
+		LastError = FsclHz;
+		CalcDivA = 0;
+		CalcDivB = 0;
+		CurrentError = 0;
+
+		for (Div_b = 0; Div_b < 64; Div_b++) {
+
+			Div_a = Temp / (Div_b + 1);
+
+			if (Div_a != 0)
+				Div_a = Div_a - 1;
+
+			if (Div_a > 3)
+				continue;
+
+			ActualFscl = (InstancePtr->Config.InputClockHz) /
+						(22 * (Div_a + 1) * (Div_b + 1));
+
+			if (ActualFscl > FsclHz)
+				CurrentError = (ActualFscl - FsclHz);
+			else
+				CurrentError = (FsclHz - ActualFscl);
+
+			if (LastError > CurrentError) {
+				CalcDivA = Div_a;
+				CalcDivB = Div_b;
+				LastError = CurrentError;
+			}
+		}
+
+		/*
+		 * Used to capture the best divisors.
+		 */
+		if (LastError < BestError) {
+			BestError = LastError;
+			BestDivA = CalcDivA;
+			BestDivB = CalcDivB;
+		}
+	}
+
+
+	/*
+	 * Read the control register and mask the Divisors.
+	 */
+	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XIICPS_CR_OFFSET);
+	ControlReg &= ~(XIICPS_CR_DIV_A_MASK | XIICPS_CR_DIV_B_MASK);
+	ControlReg |= (BestDivA << XIICPS_CR_DIV_A_SHIFT) |
+		(BestDivB << XIICPS_CR_DIV_B_SHIFT);
+
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
+			  ControlReg);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the serial clock rate for the IIC device. The device
+* must be idle rather than busy transferring data before setting these device
+* options.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	The value of the IIC clock to the nearest Hz based on the
+*		control register settings. The actual value may not be exact to
+*		to integer math rounding errors.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XIicPs_GetSClk(XIicPs *InstancePtr)
+{
+	u32 ControlReg;
+	u32 ActualFscl;
+	u32 Div_a;
+	u32 Div_b;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XIICPS_CR_OFFSET);
+
+	Div_a = (ControlReg & XIICPS_CR_DIV_A_MASK) >> XIICPS_CR_DIV_A_SHIFT;
+	Div_b = (ControlReg & XIICPS_CR_DIV_B_MASK) >> XIICPS_CR_DIV_B_SHIFT;
+
+	ActualFscl = (InstancePtr->Config.InputClockHz) /
+		(22 * (Div_a + 1) * (Div_b + 1));
+
+	return ActualFscl;
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_selftest.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_selftest.c
new file mode 100644
index 000000000..a378b2e33
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_selftest.c
@@ -0,0 +1,140 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_selftest.c
+*
+* This component contains the implementation of selftest functions for the
+* XIicPs driver component.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a drg/jz 01/30/10 First release
+* 1.00a sdm    09/22/11 Removed unused code
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+#define REG_TEST_VALUE    0x00000005
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Runs a self-test on the driver/device. The self-test is destructive in that
+* a reset of the device is performed in order to check the reset values of
+* the registers and to get the device into a known state.
+*
+* Upon successful return from the self-test, the device is reset.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_REGISTER_ERROR indicates a register did not read or write
+*		correctly
+*
+* @note		None.
+*
+******************************************************************************/
+int XIicPs_SelfTest(XIicPs *InstancePtr)
+{
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * All the IIC registers should be in their default state right now.
+	 */
+	if ((XIICPS_CR_RESET_VALUE !=
+		 XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XIICPS_CR_OFFSET)) ||
+		(XIICPS_TO_RESET_VALUE !=
+		 XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XIICPS_TIME_OUT_OFFSET)) ||
+		(XIICPS_IXR_ALL_INTR_MASK !=
+		 XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XIICPS_IMR_OFFSET))) {
+		return XST_FAILURE;
+	}
+
+	XIicPs_Reset(InstancePtr);
+
+	/*
+	 * Write, Read then write a register
+	 */
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_SLV_PAUSE_OFFSET, REG_TEST_VALUE);
+
+	if (REG_TEST_VALUE != XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+						   XIICPS_SLV_PAUSE_OFFSET)) {
+		return XST_FAILURE;
+	}
+
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_SLV_PAUSE_OFFSET, 0);
+
+	XIicPs_Reset(InstancePtr);
+
+	return XST_SUCCESS;
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_sinit.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_sinit.c
new file mode 100644
index 000000000..fcaaedb90
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_sinit.c
@@ -0,0 +1,107 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_sinit.c
+*
+* The implementation of the XIicPs component's static initialization
+* functionality.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- --------------------------------------------
+* 1.00a drg/jz 01/30/10 First release
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XIicPs_Config XIicPs_ConfigTable[];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the ID of the device to look up the
+*		configuration for.
+*
+* @return	A pointer to the configuration found or NULL if the specified
+*		device ID was not found. See xiicps.h for the definition of
+*		XIicPs_Config.
+*
+* @note		None.
+*
+******************************************************************************/
+XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId)
+{
+	XIicPs_Config *CfgPtr = NULL;
+	int Index;
+
+	for (Index = 0; Index < XPAR_XIICPS_NUM_INSTANCES; Index++) {
+		if (XIicPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XIicPs_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return CfgPtr;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_slave.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_slave.c
new file mode 100644
index 000000000..a4d5f03f6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v2_1/src/xiicps_slave.c
@@ -0,0 +1,585 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xiicps_slave.c
+*
+* Handles slave transfers
+*
+* 
 MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --  -------- ---------------------------------------------
+* 1.00a jz  01/30/10 First release
+* 1.04a kpc 08/30/13 Avoid buffer overwrite in SlaveRecvData function
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+extern int TransmitFifoFill(XIicPs *InstancePtr);
+
+static int SlaveRecvData(XIicPs *InstancePtr);
+
+/************************* Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* This function sets up the device to be a slave.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	SlaveAddr is the address of the slave we are receiving from.
+*
+* @return	None.
+*
+* @note
+*	Interrupt is always enabled no matter the tranfer is interrupt-
+*	driven or polled mode. Whether device will be interrupted or not
+*	depends on whether the device is connected to an interrupt
+*	controller and interrupt for the device is enabled.
+*
+****************************************************************************/
+void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr)
+{
+	volatile u32 ControlReg;
+	u32 BaseAddr;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	ControlReg = XIicPs_In32(BaseAddr + XIICPS_CR_OFFSET);
+
+	/*
+	 * Set up master, AckEn, nea and also clear fifo.
+	 */
+	ControlReg |= XIICPS_CR_ACKEN_MASK | XIICPS_CR_CLR_FIFO_MASK;
+	ControlReg |= XIICPS_CR_NEA_MASK;
+	ControlReg &= ~XIICPS_CR_MS_MASK;
+
+	XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+			  ControlReg);
+
+	XIicPs_DisableAllInterrupts(BaseAddr);
+
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_ADDR_OFFSET, SlaveAddr);
+
+	return;
+}
+
+/*****************************************************************************/
+/**
+* This function setup a slave interrupt-driven send. It set the repeated
+* start for the device is the tranfer size is larger than FIFO depth.
+* Data processing for the send is initiated by the interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the send buffer.
+* @param	ByteCount is the number of bytes to be sent.
+*
+* @return	None.
+*
+* @note		This send routine is for interrupt-driven transfer only.
+*
+****************************************************************************/
+void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount)
+{
+	u32 BaseAddr;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(MsgPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->SendBufferPtr = MsgPtr;
+	InstancePtr->SendByteCount = ByteCount;
+	InstancePtr->RecvBufferPtr = NULL;
+
+	XIicPs_EnableInterrupts(BaseAddr,
+			XIICPS_IXR_DATA_MASK | XIICPS_IXR_COMP_MASK |
+			XIICPS_IXR_TO_MASK | XIICPS_IXR_NACK_MASK |
+			XIICPS_IXR_TX_OVR_MASK);
+}
+
+/*****************************************************************************/
+/**
+* This function setup a slave interrupt-driven receive.
+* Data processing for the receive is handled by the interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the receive buffer.
+* @param	ByteCount is the number of bytes to be received.
+*
+* @return	None.
+*
+* @note		This routine is for interrupt-driven transfer only.
+*
+****************************************************************************/
+void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount)
+{
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(MsgPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+	InstancePtr->RecvBufferPtr = MsgPtr;
+	InstancePtr->RecvByteCount = ByteCount;
+	InstancePtr->SendBufferPtr = NULL;
+
+	XIicPs_EnableInterrupts(InstancePtr->Config.BaseAddress,
+			XIICPS_IXR_DATA_MASK | XIICPS_IXR_COMP_MASK |
+			XIICPS_IXR_NACK_MASK | XIICPS_IXR_TO_MASK |
+			XIICPS_IXR_RX_OVR_MASK | XIICPS_IXR_RX_UNF_MASK);
+
+}
+
+/*****************************************************************************/
+/**
+* This function sends  a buffer in polled mode as a slave.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the send buffer.
+* @param	ByteCount is the number of bytes to be sent.
+*
+* @return
+*		- XST_SUCCESS if everything went well.
+*		- XST_FAILURE if master sends us data or master terminates the
+*		transfer before all data has sent out.
+*
+* @note		This send routine is for polled mode transfer only.
+*
+****************************************************************************/
+int XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount)
+{
+	volatile u32 IntrStatusReg;
+	volatile u32 StatusReg;
+	u32 BaseAddr;
+	int Tmp;
+	int BytesToSend;
+	int Error = 0;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(MsgPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->SendBufferPtr = MsgPtr;
+	InstancePtr->SendByteCount = ByteCount;
+
+	/*
+	 * Use RXRW bit in status register to wait master to start a read.
+	 */
+	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+	while (((StatusReg & XIICPS_SR_RXRW_MASK) == 0) && (!Error)) {
+
+		/*
+		 * If master tries to send us data, it is an error.
+		 */
+		if (StatusReg & XIICPS_SR_RXDV_MASK) {
+			Error = 1;
+		}
+
+		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+	}
+
+	if (Error) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Clear the interrupt status register.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	/*
+	 * Send data as long as there is more data to send and
+	 * there are no errors.
+	 */
+	while ((InstancePtr->SendByteCount > 0) && (!Error)){
+
+		/*
+		 * Find out how many can be sent.
+		 */
+		BytesToSend = InstancePtr->SendByteCount;
+		if (BytesToSend > XIICPS_FIFO_DEPTH) {
+			BytesToSend = XIICPS_FIFO_DEPTH;
+		}
+
+		for(Tmp = 0; Tmp < BytesToSend; Tmp ++) {
+			XIicPs_SendByte(InstancePtr);
+		}
+
+		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+		/*
+		 * Wait for master to read the data out of fifo.
+		 */
+		while (((StatusReg & XIICPS_SR_TXDV_MASK) != 0) && (!Error)) {
+
+			/*
+			 * If master terminates the transfer before all data is
+			 * sent, it is an error.
+			 */
+			IntrStatusReg = XIicPs_ReadReg(BaseAddr,
+			XIICPS_ISR_OFFSET);
+			if (IntrStatusReg & XIICPS_IXR_NACK_MASK) {
+				Error = 1;
+			}
+
+			/* Clear ISR.
+			 */
+			XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET,
+						IntrStatusReg);
+
+			StatusReg = XIicPs_ReadReg(BaseAddr,
+					XIICPS_SR_OFFSET);
+		}
+	}
+
+	if (Error) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+/*****************************************************************************/
+/**
+* This function receives a buffer in polled mode as a slave.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the receive buffer.
+* @param	ByteCount is the number of bytes to be received.
+*
+* @return
+*		- XST_SUCCESS if everything went well.
+*		- XST_FAILURE if timed out.
+*
+* @note		This receive routine is for polled mode transfer only.
+*
+****************************************************************************/
+int XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, int ByteCount)
+{
+	volatile u32 IntrStatusReg;
+	volatile u32 StatusReg;
+	u32 BaseAddr;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(MsgPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->RecvBufferPtr = MsgPtr;
+	InstancePtr->RecvByteCount = ByteCount;
+
+	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+	/*
+	 * Clear the interrupt status register.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	/*
+	 * Clear the status register.
+	 */
+	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+	XIicPs_WriteReg(BaseAddr, XIICPS_SR_OFFSET, StatusReg);
+
+	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+	while (InstancePtr->RecvByteCount > 0) {
+
+		/* Wait for master to put data */
+		while ((StatusReg & XIICPS_SR_RXDV_MASK) == 0) {
+		    StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+			/*
+			 * If master terminates the transfer before we get all
+			 * the data or the master tries to read from us,
+		 	 * it is an error.
+		 	 */
+			IntrStatusReg = XIicPs_ReadReg(BaseAddr,
+						XIICPS_ISR_OFFSET);
+			if ((IntrStatusReg & (XIICPS_IXR_DATA_MASK |
+					XIICPS_IXR_COMP_MASK)) &&
+				((StatusReg & XIICPS_SR_RXDV_MASK) == 0) &&
+				(InstancePtr->RecvByteCount > 0)) {
+
+				return XST_FAILURE;
+			}
+
+			/*
+			 * Clear the interrupt status register.
+			 */
+			XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET,
+			IntrStatusReg);
+		}
+
+		/*
+		 * Read all data from FIFO.
+		 */
+		while ((StatusReg & XIICPS_SR_RXDV_MASK) &&
+			 (InstancePtr->RecvByteCount > 0)){
+
+			XIicPs_RecvByte(InstancePtr);
+
+			StatusReg = XIicPs_ReadReg(BaseAddr,
+				XIICPS_SR_OFFSET);
+		}
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* The interrupt handler for slave mode. It does the protocol handling for
+* the interrupt-driven transfers.
+*
+* Completion events and errors are signaled to upper layer for proper
+* handling.
+*
+* 
+*
+* The interrupts that are handled are:
+* - DATA
+*	If the instance is sending, it means that the master wants to read more
+*	data from us. Send more data, and check whether we are done with this
+*	send.
+*
+*	If the instance is receiving, it means that the master has writen
+* 	more data to us. Receive more data, and check whether we are done with
+*	with this receive.
+*
+* - COMP
+*	This marks that stop sequence has been sent from the master, transfer
+*	is about to terminate. However, for receiving, the master may have
+*	written us some data, so receive that first.
+*
+*	It is an error if the amount of transfered data is less than expected.
+*
+* - NAK
+*	This marks that master does not want our data. It is for send only.
+*
+* - Other interrupts
+*	These interrupts are marked as error.
+*
+* 

+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note 	None.
+*
+****************************************************************************/
+void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr)
+{
+	volatile u32 IntrStatusReg;
+	u32 IsSend = 0;
+	u32 StatusEvent = 0;
+	int LeftOver;
+	u32 BaseAddr;
+
+	/*
+ 	 * Assert validates the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	/*
+	 * Read the Interrupt status register.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+
+	/*
+	 * Write the status back to clear the interrupts so no events are missed
+	 * while processing this interrupt.
+	 */
+	XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	/*
+	 * Use the Mask register AND with the Interrupt Status register so
+	 * disabled interrupts are not processed.
+	 */
+	IntrStatusReg &= ~(XIicPs_ReadReg(BaseAddr, XIICPS_IMR_OFFSET));
+
+	/*
+	 * Determine whether the device is sending.
+	 */
+	if (InstancePtr->RecvBufferPtr == NULL) {
+		IsSend = 1;
+	}
+
+	/* Data interrupt
+	 *
+	 * This means master wants to do more data transfers.
+	 * Also check for completion of transfer, signal upper layer if done.
+	 */
+	if (0 != (IntrStatusReg & XIICPS_IXR_DATA_MASK)) {
+		if (IsSend) {
+			LeftOver = TransmitFifoFill(InstancePtr);
+				/*
+				 * We may finish send here
+				 */
+				if (LeftOver == 0) {
+					StatusEvent |=
+						XIICPS_EVENT_COMPLETE_SEND;
+				}
+		} else {
+			LeftOver = SlaveRecvData(InstancePtr);
+
+			/* We may finish the receive here */
+			if (LeftOver == 0) {
+				StatusEvent |= XIICPS_EVENT_COMPLETE_RECV;
+			}
+		}
+	}
+
+	/*
+	 * Complete interrupt.
+	 *
+	 * In slave mode, it means the master has done with this transfer, so
+	 * we signal the application using completion event.
+	 */
+	if (0 != (IntrStatusReg & XIICPS_IXR_COMP_MASK)) {
+		if (IsSend) {
+			if (InstancePtr->SendByteCount > 0) {
+				StatusEvent |= XIICPS_EVENT_ERROR;
+			}else {
+				StatusEvent |= XIICPS_EVENT_COMPLETE_SEND;
+			}
+		} else {
+			LeftOver = SlaveRecvData(InstancePtr);
+			if (LeftOver > 0) {
+				StatusEvent |= XIICPS_EVENT_ERROR;
+			} else {
+				StatusEvent |= XIICPS_EVENT_COMPLETE_RECV;
+			}
+		}
+	}
+
+	/*
+	 * Nack interrupt, pass this information to application.
+	 */
+	if (0 != (IntrStatusReg & XIICPS_IXR_NACK_MASK)) {
+		StatusEvent |= XIICPS_EVENT_NACK;
+	}
+
+	/*
+	 * All other interrupts are treated as error.
+	 */
+	if (0 != (IntrStatusReg & (XIICPS_IXR_TO_MASK |
+			  	XIICPS_IXR_RX_UNF_MASK |
+				XIICPS_IXR_TX_OVR_MASK |
+				XIICPS_IXR_RX_OVR_MASK))){
+
+		StatusEvent |= XIICPS_EVENT_ERROR;
+	}
+
+	/*
+	 * Signal application if there are any events.
+	 */
+	if (0 != StatusEvent) {
+		InstancePtr->StatusHandler(InstancePtr->CallBackRef,
+					   StatusEvent);
+	}
+}
+
+/*****************************************************************************/
+/*
+*
+* This function handles continuation of receiving data. It is invoked
+* from interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	Number of bytes still expected by the instance.
+*
+* @note		None.
+*
+****************************************************************************/
+static int SlaveRecvData(XIicPs *InstancePtr)
+{
+	volatile u32 StatusReg;
+	u32 BaseAddr;
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+	while ((StatusReg & XIICPS_SR_RXDV_MASK) && 
+			(InstancePtr->RecvByteCount > 0)) {
+		XIicPs_RecvByte(InstancePtr);
+		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+	}
+
+	return InstancePtr->RecvByteCount;
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/Makefile
new file mode 100644
index 000000000..c05a30d97
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/Makefile
@@ -0,0 +1,41 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xqspips_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling qspips"
+
+xqspips_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xqspips_includes
+
+xqspips_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/xqspips.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/xqspips.c
new file mode 100644
index 000000000..a017dbcd0
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/xqspips.c
@@ -0,0 +1,1558 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips.c
+*
+* Contains implements the interface functions of the XQspiPs driver.
+* See xqspips.h for a detailed description of the device and driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00  sdm 11/25/10 First release
+* 2.00a kka 07/25/12 Removed XQspiPs_GetWriteData API.
+*		     The XQspiPs_SetSlaveSelect has been modified to remove
+*		     the argument of the slave select as the QSPI controller
+*		     only supports one slave.
+* 		     XQspiPs_GetSlaveSelect API has been removed
+* 		     Added logic to XQspiPs_GetReadData to handle data
+*		     shift for normal data reads and instruction/status
+*		     reads differently based on the ShiftReadData flag.
+* 		     Removed the selection for the following options:
+*		     Master mode (XQSPIPS_MASTER_OPTION) and
+*		     Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
+*		     as the QSPI driver supports the Master mode
+*		     and Flash Interface mode and doesnot support
+*		     Slave mode or the legacy mode.
+*		     Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
+*		     APIs so that the last argument (IsInst) specifying whether
+*		     it is instruction or data has been removed. The first byte
+*		     in the SendBufPtr argument of these APIs specify the
+*		     instruction to be sent to the Flash Device.
+*		     The XQspiPs_PolledTransfer function has been updated
+*		     to fill the data to fifo depth.
+*		     This version of the driver fixes CRs 670197/663787.
+* 2.01a sg  02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
+*		     Created macros XQspiPs_IsManualStart and
+*		     XQspiPs_IsManualChipSelect.
+*		     Changed QSPI transfer logic for polled and interrupt
+*		     modes to be based on filled tx fifo count and receive
+*		     based on it. RXNEMPTY interrupt is not used.
+*		     Added assertions to XQspiPs_LqspiRead function.
+*
+* 2.02a hk  05/14/13 Added enable and disable to the XQspiPs_LqspiRead()
+*			 function
+*            Added instructions for bank selection, die erase and
+*            flag status register to the flash instruction table
+*            Handling for instructions not in flash instruction
+*			 table added. Checking for Tx FIFO empty when switching from
+*			 TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
+*            byte count 3 (spansion), instruction size and TXD register
+*			 changed accordingly. CR# 712502 and 703869.
+*            Added (#ifdef linear base address) in the Linear read function.
+*            Changed  XPAR_XQSPIPS_0_LINEAR_BASEADDR to
+*            XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
+*            XQspiPs_LqspiRead function. Fix for CR#718141
+*
+* 2.03a hk  09/05/13 Modified polled and interrupt transfers to make use of
+*                    thresholds. This is to improve performance.
+*                    Added RX and TX threshold reset to one in XQspiPs_Abort.
+*                    Added RX threshold reset(1) after transfer in polled and
+*                    interrupt transfers. Made changes to make sure threshold
+*                    change is done only when no transfer is in progress.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xqspips.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef defines qspi flash instruction format
+ */
+typedef struct {
+	u8 OpCode;	/**< Operational code of the instruction */
+	u8 InstSize;	/**< Size of the instruction including address bytes */
+	u8 TxOffset;	/**< Register address where instruction has to be
+			     written */
+} XQspiPsInstFormat;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define ARRAY_SIZE(Array)		(sizeof(Array) / sizeof((Array)[0]))
+
+/************************** Function Prototypes ******************************/
+static void XQspiPs_GetReadData(XQspiPs *InstancePtr, u32 Data, u8 Size);
+static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
+				unsigned ByteCount);
+
+/************************** Variable Definitions *****************************/
+
+/*
+ * List of all the QSPI instructions and its format
+ */
+static XQspiPsInstFormat FlashInst[] = {
+	{ XQSPIPS_FLASH_OPCODE_WREN, 1, XQSPIPS_TXD_01_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_WRDS, 1, XQSPIPS_TXD_01_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_RDSR1, 2, XQSPIPS_TXD_10_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_RDSR2, 2, XQSPIPS_TXD_10_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_WRSR, 2, XQSPIPS_TXD_10_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_PP, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_SE, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_BE_32K, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_BE_4K, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_BE, 1, XQSPIPS_TXD_01_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_ERASE_SUS, 1, XQSPIPS_TXD_01_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_ERASE_RES, 1, XQSPIPS_TXD_01_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_RDID, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_NORM_READ, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_FAST_READ, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_DUAL_READ, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_QUAD_READ, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_DUAL_IO_READ, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_QUAD_IO_READ, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_BRWR, 2, XQSPIPS_TXD_10_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_BRRD, 2, XQSPIPS_TXD_10_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_EARWR, 2, XQSPIPS_TXD_10_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_EARRD, 2, XQSPIPS_TXD_10_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_DIE_ERASE, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_READ_FLAG_SR, 2, XQSPIPS_TXD_10_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR, 1, XQSPIPS_TXD_01_OFFSET },
+	/* Add all the instructions supported by the flash device */
+};
+
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XQspiPs instance such that the driver is ready to use.
+*
+* The state of the device after initialization is:
+*   - Master mode
+*   - Active high clock polarity
+*   - Clock phase 0
+*   - Baud rate divisor 2
+*   - Transfer width 32
+*   - Master reference clock = pclk
+*   - No chip select active
+*   - Manual CS and Manual Start disabled
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	ConfigPtr is a reference to a structure containing information
+*		about a specific QSPI device. This function initializes an
+*		InstancePtr object for a specific device specified by the
+*		contents of Config.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, use
+*		ConfigPtr->Config.BaseAddress for this device.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_DEVICE_IS_STARTED if the device is already started.
+*		It must be stopped to re-initialize.
+*
+* @note		None.
+*
+******************************************************************************/
+int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * If the device is busy, disallow the initialize and return a status
+	 * indicating it is already started. This allows the user to stop the
+	 * device and re-initialize, but prevents a user from inadvertently
+	 * initializing. This assumes the busy flag is cleared at startup.
+	 */
+	if (InstancePtr->IsBusy == TRUE) {
+		return XST_DEVICE_IS_STARTED;
+	}
+
+	/*
+	 * Set some default values.
+	 */
+	InstancePtr->IsBusy = FALSE;
+
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+	InstancePtr->StatusHandler = StubStatusHandler;
+
+	InstancePtr->SendBufferPtr = NULL;
+	InstancePtr->RecvBufferPtr = NULL;
+	InstancePtr->RequestedBytes = 0;
+	InstancePtr->RemainingBytes = 0;
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	InstancePtr->Config.ConnectionMode = ConfigPtr->ConnectionMode;
+
+	/*
+	 * Reset the QSPI device to get it into its initial state. It is
+	 * expected that device configuration will take place after this
+	 * initialization is done, but before the device is started.
+	 */
+	XQspiPs_Reset(InstancePtr);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Resets the QSPI device. Reset must only be called after the driver has been
+* initialized. Any data transfer that is in progress is aborted.
+*
+* The upper layer software is responsible for re-configuring (if necessary)
+* and restarting the QSPI device after the reset.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XQspiPs_Reset(XQspiPs *InstancePtr)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Abort any transfer that is in progress
+	 */
+	XQspiPs_Abort(InstancePtr);
+
+	/*
+	 * Reset any values that are not reset by the hardware reset such that
+	 * the software state matches the hardware device
+	 */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET,
+			  XQSPIPS_CR_RESET_STATE);
+}
+
+/*****************************************************************************/
+/**
+*
+* Aborts a transfer in progress by disabling the device and flush the RxFIFO.
+* The byte counts are cleared, the busy flag is cleared.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	None.
+*
+* @note
+*
+* This function does a read/modify/write of the config register. The user of
+* this function needs to take care of critical sections.
+*
+******************************************************************************/
+void XQspiPs_Abort(XQspiPs *InstancePtr)
+{
+	u32 ConfigReg;
+
+	XQspiPs_Disable(InstancePtr);
+
+	/*
+	 * De-assert slave select lines.
+	 */
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+			 XQSPIPS_CR_OFFSET);
+	ConfigReg |= (XQSPIPS_CR_SSCTRL_MASK | XQSPIPS_CR_SSFORCE_MASK);
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			 XQSPIPS_CR_OFFSET, ConfigReg);
+
+	/*
+	 * Set the RX and TX FIFO threshold to reset value (one)
+	 */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPS_TXWR_OFFSET, XQSPIPS_TXWR_RESET_VALUE);
+
+	/*
+	 * Clear the RX FIFO and drop any data.
+	 */
+	while ((XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+		 XQSPIPS_SR_OFFSET) & XQSPIPS_IXR_RXNEMPTY_MASK) != 0) {
+		XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				 XQSPIPS_RXD_OFFSET);
+	}
+
+	InstancePtr->RemainingBytes = 0;
+	InstancePtr->RequestedBytes = 0;
+	InstancePtr->IsBusy = FALSE;
+}
+
+/*****************************************************************************/
+/**
+*
+* Transfers specified data on the QSPI bus. Initiates bus communication and
+* sends/receives data to/from the selected QSPI slave. For every byte sent,
+* a byte is received.
+*
+* The caller has the option of providing two different buffers for send and
+* receive, or one buffer for both send and receive, or no buffer for receive.
+* The receive buffer must be at least as big as the send buffer to prevent
+* unwanted memory writes. This implies that the byte count passed in as an
+* argument must be the smaller of the two buffers if they differ in size.
+* Here are some sample usages:
+* 
+*   XQspiPs_Transfer(InstancePtr, SendBuf, RecvBuf, ByteCount)
+*	The caller wishes to send and receive, and provides two different
+*	buffers for send and receive.
+*
+*   XQspiPs_Transfer(InstancePtr, SendBuf, NULL, ByteCount)
+*	The caller wishes only to send and does not care about the received
+*	data. The driver ignores the received data in this case.
+*
+*   XQspiPs_Transfer(InstancePtr, SendBuf, SendBuf, ByteCount)
+*	The caller wishes to send and receive, but provides the same buffer
+*	for doing both. The driver sends the data and overwrites the send
+*	buffer with received data as it transfers the data.
+*
+*   XQspiPs_Transfer(InstancePtr, RecvBuf, RecvBuf, ByteCount)
+*	The caller wishes to only receive and does not care about sending
+*	data.  In this case, the caller must still provide a send buffer, but
+*	it can be the same as the receive buffer if the caller does not care
+*	what it sends.  The device must send N bytes of data if it wishes to
+*	receive N bytes of data.
+* 

+* Although this function takes entire buffers as arguments, the driver can only
+* transfer a limited number of bytes at a time, limited by the size of the
+* FIFO. A call to this function only starts the transfer, then subsequent
+* transfers of the data is performed by the interrupt service routine until
+* the entire buffer has been transferred. The status callback function is
+* called when the entire buffer has been sent/received.
+*
+* This function is non-blocking. The SetSlaveSelect function must be called
+* prior to this function.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	SendBufPtr is a pointer to a data buffer that needs to be
+*		transmitted. This buffer must not be NULL.
+* @param	RecvBufPtr is a pointer to a buffer for received data.
+*		This argument can be NULL if do not care about receiving.
+* @param	ByteCount contains the number of bytes to send/receive.
+*		The number of bytes received always equals the number of bytes
+*		sent.
+*
+* @return
+*		- XST_SUCCESS if the buffers are successfully handed off to the
+*		  device for transfer.
+*		- XST_DEVICE_BUSY indicates that a data transfer is already in
+*		  progress. This is determined by the driver.
+*
+* @note
+*
+* This function is not thread-safe.  The higher layer software must ensure that
+* no two threads are transferring data on the QSPI bus at the same time.
+*
+******************************************************************************/
+int XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
+			unsigned ByteCount)
+{
+	u32 StatusReg;
+	u32 ConfigReg;
+	u8 Instruction;
+	u32 Data;
+	unsigned int Index;
+	u8 TransCount = 0;
+	XQspiPsInstFormat *CurrInst;
+	XQspiPsInstFormat NewInst[2];
+	u8 SwitchFlag  = 0;
+
+	CurrInst = &NewInst[0];
+
+	/*
+	 * The RecvBufPtr argument can be null
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(SendBufPtr != NULL);
+	Xil_AssertNonvoid(ByteCount > 0);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Check whether there is another transfer in progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy) {
+		return XST_DEVICE_BUSY;
+	}
+
+	/*
+	 * Set the busy flag, which will be cleared in the ISR when the
+	 * transfer is entirely done.
+	 */
+	InstancePtr->IsBusy = TRUE;
+
+	/*
+	 * Set up buffer pointers.
+	 */
+	InstancePtr->SendBufferPtr = SendBufPtr;
+	InstancePtr->RecvBufferPtr = RecvBufPtr;
+
+	InstancePtr->RequestedBytes = ByteCount;
+	InstancePtr->RemainingBytes = ByteCount;
+
+	/*
+	 * The first byte with every chip-select assertion is always
+	 * expected to be an instruction for flash interface mode
+	 */
+	Instruction = *InstancePtr->SendBufferPtr;
+
+	for (Index = 0 ; Index < ARRAY_SIZE(FlashInst); Index++) {
+		if (Instruction == FlashInst[Index].OpCode) {
+			break;
+		}
+	}
+
+	/*
+	 * Set the RX FIFO threshold
+	 */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPS_RXWR_OFFSET, XQSPIPS_RXFIFO_THRESHOLD_OPT);
+
+	/*
+	 * If the slave select is "Forced" or under manual control,
+	 * set the slave select now, before beginning the transfer.
+	 */
+	if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+		ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				 XQSPIPS_CR_OFFSET);
+		ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK;
+		XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XQSPIPS_CR_OFFSET,
+				  ConfigReg);
+	}
+
+	/*
+	 * Enable the device.
+	 */
+	XQspiPs_Enable(InstancePtr);
+
+	/*
+	 * Clear all the interrrupts.
+	 */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_SR_OFFSET,
+			XQSPIPS_IXR_WR_TO_CLR_MASK);
+
+	if (Index < ARRAY_SIZE(FlashInst)) {
+		CurrInst = &FlashInst[Index];
+		/*
+		 * Check for WRSR instruction which has different size for
+		 * Spansion (3 bytes) and Micron (2 bytes)
+		 */
+		if( (CurrInst->OpCode == XQSPIPS_FLASH_OPCODE_WRSR) &&
+			(ByteCount == 3) ) {
+			CurrInst->InstSize = 3;
+			CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
+		}
+	}
+
+	/*
+	 * If instruction not present in table
+	 */
+	if (Index == ARRAY_SIZE(FlashInst)) {
+		/*
+		 * Assign current instruction, size and TXD register to be used
+		 * The InstSize mentioned in case of instructions greater than
+		 * 4 bytes is not the actual size, but is indicative of
+		 * the TXD register used.
+		 * The remaining bytes of the instruction will be transmitted
+		 * through TXD0 below.
+		 */
+		switch(ByteCount%4)
+		{
+			case XQSPIPS_SIZE_ONE:
+				CurrInst->OpCode = Instruction;
+				CurrInst->InstSize = XQSPIPS_SIZE_ONE;
+				CurrInst->TxOffset = XQSPIPS_TXD_01_OFFSET;
+				if(ByteCount > 4) {
+					SwitchFlag = 1;
+				}
+				break;
+			case XQSPIPS_SIZE_TWO:
+				CurrInst->OpCode = Instruction;
+				CurrInst->InstSize = XQSPIPS_SIZE_TWO;
+				CurrInst->TxOffset = XQSPIPS_TXD_10_OFFSET;
+				if(ByteCount > 4) {
+					SwitchFlag = 1;
+				}
+				break;
+			case XQSPIPS_SIZE_THREE:
+				CurrInst->OpCode = Instruction;
+				CurrInst->InstSize = XQSPIPS_SIZE_THREE;
+				CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
+				if(ByteCount > 4) {
+					SwitchFlag = 1;
+				}
+				break;
+			default:
+				CurrInst->OpCode = Instruction;
+				CurrInst->InstSize = XQSPIPS_SIZE_FOUR;
+				CurrInst->TxOffset = XQSPIPS_TXD_00_OFFSET;
+				break;
+		}
+	}
+
+	/*
+	 * If the instruction size in not 4 bytes then the data received needs
+	 * to be shifted
+	 */
+	if( CurrInst->InstSize != 4 ) {
+		InstancePtr->ShiftReadData = 1;
+	} else {
+		InstancePtr->ShiftReadData = 0;
+	}
+
+	/* Get the complete command (flash inst + address/data) */
+	Data = *((u32 *)InstancePtr->SendBufferPtr);
+	InstancePtr->SendBufferPtr += CurrInst->InstSize;
+	InstancePtr->RemainingBytes -= CurrInst->InstSize;
+	if (InstancePtr->RemainingBytes < 0) {
+		InstancePtr->RemainingBytes = 0;
+	}
+
+	/* Write the command to the FIFO */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			 CurrInst->TxOffset, Data);
+	TransCount++;
+
+	/*
+	 * If switching from TXD1/2/3 to TXD0, then start transfer and
+	 * check for FIFO empty
+	 */
+	if(SwitchFlag == 1) {
+		SwitchFlag = 0;
+		/*
+		 * If, in Manual Start mode, start the transfer.
+		 */
+		if (XQspiPs_IsManualStart(InstancePtr)) {
+			ConfigReg = XQspiPs_ReadReg(
+					InstancePtr->Config.BaseAddress,
+					 XQSPIPS_CR_OFFSET);
+			ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+			XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+					 XQSPIPS_CR_OFFSET, ConfigReg);
+		}
+		/*
+		 * Wait for the transfer to finish by polling Tx fifo status.
+		 */
+		do {
+			StatusReg = XQspiPs_ReadReg(
+					InstancePtr->Config.BaseAddress,
+					XQSPIPS_SR_OFFSET);
+		} while ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0);
+
+	}
+
+	/*
+	 * Fill the Tx FIFO with as many bytes as it takes (or as many as
+	 * we have to send).
+	 */
+	while ((InstancePtr->RemainingBytes > 0) &&
+		(TransCount < XQSPIPS_FIFO_DEPTH)) {
+		XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XQSPIPS_TXD_00_OFFSET,
+				  *((u32 *)InstancePtr->SendBufferPtr));
+		InstancePtr->SendBufferPtr += 4;
+		InstancePtr->RemainingBytes -= 4;
+		if (InstancePtr->RemainingBytes < 0) {
+			InstancePtr->RemainingBytes = 0;
+		}
+		TransCount++;
+	}
+
+	/*
+	 * Enable QSPI interrupts (connecting to the interrupt controller and
+	 * enabling interrupts should have been done by the caller).
+	 */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XQSPIPS_IER_OFFSET, XQSPIPS_IXR_RXNEMPTY_MASK |
+			  XQSPIPS_IXR_TXOW_MASK | XQSPIPS_IXR_RXOVR_MASK |
+			  XQSPIPS_IXR_TXUF_MASK);
+
+	/*
+	 * If, in Manual Start mode, Start the transfer.
+	 */
+	if (XQspiPs_IsManualStart(InstancePtr)) {
+		ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XQSPIPS_CR_OFFSET);
+		ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+		XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XQSPIPS_CR_OFFSET, ConfigReg);
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* Transfers specified data on the QSPI bus in polled mode.
+*
+* The caller has the option of providing two different buffers for send and
+* receive, or one buffer for both send and receive, or no buffer for receive.
+* The receive buffer must be at least as big as the send buffer to prevent
+* unwanted memory writes. This implies that the byte count passed in as an
+* argument must be the smaller of the two buffers if they differ in size.
+* Here are some sample usages:
+* 
+*   XQspiPs_PolledTransfer(InstancePtr, SendBuf, RecvBuf, ByteCount)
+*	The caller wishes to send and receive, and provides two different
+*	buffers for send and receive.
+*
+*   XQspiPs_PolledTransfer(InstancePtr, SendBuf, NULL, ByteCount)
+*	The caller wishes only to send and does not care about the received
+*	data. The driver ignores the received data in this case.
+*
+*   XQspiPs_PolledTransfer(InstancePtr, SendBuf, SendBuf, ByteCount)
+*	The caller wishes to send and receive, but provides the same buffer
+*	for doing both. The driver sends the data and overwrites the send
+*	buffer with received data as it transfers the data.
+*
+*   XQspiPs_PolledTransfer(InstancePtr, RecvBuf, RecvBuf, ByteCount)
+*	The caller wishes to only receive and does not care about sending
+*	data.  In this case, the caller must still provide a send buffer, but
+*	it can be the same as the receive buffer if the caller does not care
+*	what it sends.  The device must send N bytes of data if it wishes to
+*	receive N bytes of data.
+*
+* 

+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	SendBufPtr is a pointer to a data buffer that needs to be
+*		transmitted. This buffer must not be NULL.
+* @param	RecvBufPtr is a pointer to a buffer for received data.
+*		This argument can be NULL if do not care about receiving.
+* @param	ByteCount contains the number of bytes to send/receive.
+*		The number of bytes received always equals the number of bytes
+*		sent.
+* @return
+*		- XST_SUCCESS if the buffers are successfully handed off to the
+*		  device for transfer.
+*		- XST_DEVICE_BUSY indicates that a data transfer is already in
+*		  progress. This is determined by the driver.
+*
+* @note
+*
+* This function is not thread-safe.  The higher layer software must ensure that
+* no two threads are transferring data on the QSPI bus at the same time.
+*
+******************************************************************************/
+int XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
+			    u8 *RecvBufPtr, unsigned ByteCount)
+{
+	u32 StatusReg;
+	u32 ConfigReg;
+	u8 Instruction;
+	u32 Data;
+	u8 TransCount;
+	unsigned int Index;
+	XQspiPsInstFormat *CurrInst;
+	XQspiPsInstFormat NewInst[2];
+	u8 SwitchFlag  = 0;
+	u8 IsManualStart = FALSE;
+	u32 RxCount = 0;
+
+	CurrInst = &NewInst[0];
+	/*
+	 * The RecvBufPtr argument can be NULL.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(SendBufPtr != NULL);
+	Xil_AssertNonvoid(ByteCount > 0);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Check whether there is another transfer in progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy) {
+		return XST_DEVICE_BUSY;
+	}
+
+	/*
+	 * Set the busy flag, which will be cleared when the transfer is
+	 * entirely done.
+	 */
+	InstancePtr->IsBusy = TRUE;
+
+	/*
+	 * Set up buffer pointers.
+	 */
+	InstancePtr->SendBufferPtr = SendBufPtr;
+	InstancePtr->RecvBufferPtr = RecvBufPtr;
+
+	InstancePtr->RequestedBytes = ByteCount;
+	InstancePtr->RemainingBytes = ByteCount;
+
+	/*
+	 * The first byte with every chip-select assertion is always
+	 * expected to be an instruction for flash interface mode
+	 */
+	Instruction = *InstancePtr->SendBufferPtr;
+
+	for (Index = 0 ; Index < ARRAY_SIZE(FlashInst); Index++) {
+		if (Instruction == FlashInst[Index].OpCode) {
+			break;
+		}
+	}
+
+	/*
+	 * Set the RX FIFO threshold
+	 */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPS_RXWR_OFFSET, XQSPIPS_RXFIFO_THRESHOLD_OPT);
+
+	/*
+	 * If the slave select is "Forced" or under manual control,
+	 * set the slave select now, before beginning the transfer.
+	 */
+	if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+		ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				 XQSPIPS_CR_OFFSET);
+		ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK;
+		XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XQSPIPS_CR_OFFSET,
+				  ConfigReg);
+	}
+
+	/*
+	 * Enable the device.
+	 */
+	XQspiPs_Enable(InstancePtr);
+
+	if (Index < ARRAY_SIZE(FlashInst)) {
+
+		CurrInst = &FlashInst[Index];
+		/*
+		 * Check for WRSR instruction which has different size for
+		 * Spansion (3 bytes) and Micron (2 bytes)
+		 */
+		if( (CurrInst->OpCode == XQSPIPS_FLASH_OPCODE_WRSR) &&
+			(ByteCount == 3) ) {
+			CurrInst->InstSize = 3;
+			CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
+		}
+	}
+
+	/*
+	 * If instruction not present in table
+	 */
+	if (Index == ARRAY_SIZE(FlashInst)) {
+		/*
+		 * Assign current instruction, size and TXD register to be used.
+		 * The InstSize mentioned in case of instructions greater than 4 bytes
+		 * is not the actual size, but is indicative of the TXD register used.
+		 * The remaining bytes of the instruction will be transmitted
+		 * through TXD0 below.
+		 */
+		switch(ByteCount%4)
+		{
+			case XQSPIPS_SIZE_ONE:
+				CurrInst->OpCode = Instruction;
+				CurrInst->InstSize = XQSPIPS_SIZE_ONE;
+				CurrInst->TxOffset = XQSPIPS_TXD_01_OFFSET;
+				if(ByteCount > 4) {
+					SwitchFlag = 1;
+				}
+				break;
+			case XQSPIPS_SIZE_TWO:
+				CurrInst->OpCode = Instruction;
+				CurrInst->InstSize = XQSPIPS_SIZE_TWO;
+				CurrInst->TxOffset = XQSPIPS_TXD_10_OFFSET;
+				if(ByteCount > 4) {
+					SwitchFlag = 1;
+				}
+				break;
+			case XQSPIPS_SIZE_THREE:
+				CurrInst->OpCode = Instruction;
+				CurrInst->InstSize = XQSPIPS_SIZE_THREE;
+				CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
+				if(ByteCount > 4) {
+					SwitchFlag = 1;
+				}
+				break;
+			default:
+				CurrInst->OpCode = Instruction;
+				CurrInst->InstSize = XQSPIPS_SIZE_FOUR;
+				CurrInst->TxOffset = XQSPIPS_TXD_00_OFFSET;
+				break;
+		}
+	}
+
+	/*
+	 * If the instruction size in not 4 bytes then the data received needs
+	 * to be shifted
+	 */
+	if( CurrInst->InstSize != 4 ) {
+		InstancePtr->ShiftReadData = 1;
+	} else {
+		InstancePtr->ShiftReadData = 0;
+	}
+	TransCount = 0;
+	/* Get the complete command (flash inst + address/data) */
+	Data = *((u32 *)InstancePtr->SendBufferPtr);
+	InstancePtr->SendBufferPtr += CurrInst->InstSize;
+	InstancePtr->RemainingBytes -= CurrInst->InstSize;
+	if (InstancePtr->RemainingBytes < 0) {
+		InstancePtr->RemainingBytes = 0;
+	}
+
+	/* Write the command to the FIFO */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+					CurrInst->TxOffset, Data);
+	++TransCount;
+
+	/*
+	 * If switching from TXD1/2/3 to TXD0, then start transfer and
+	 * check for FIFO empty
+	 */
+	if(SwitchFlag == 1) {
+		SwitchFlag = 0;
+		/*
+		 * If, in Manual Start mode, start the transfer.
+		 */
+		if (XQspiPs_IsManualStart(InstancePtr)) {
+			ConfigReg = XQspiPs_ReadReg(
+					InstancePtr->Config.BaseAddress,
+					 XQSPIPS_CR_OFFSET);
+			ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+			XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+					 XQSPIPS_CR_OFFSET, ConfigReg);
+		}
+		/*
+		 * Wait for the transfer to finish by polling Tx fifo status.
+		 */
+		do {
+			StatusReg = XQspiPs_ReadReg(
+					InstancePtr->Config.BaseAddress,
+					XQSPIPS_SR_OFFSET);
+		} while ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0);
+
+	}
+
+	/*
+	 * Check if manual start is selected and store it in a
+	 * local varibale for reference. This is to avoid reading
+	 * the config register everytime.
+	 */
+	IsManualStart = XQspiPs_IsManualStart(InstancePtr);
+
+	/*
+	 * Fill the DTR/FIFO with as many bytes as it will take (or as
+	 * many as we have to send).
+	 */
+	while ((InstancePtr->RemainingBytes > 0) &&
+		(TransCount < XQSPIPS_FIFO_DEPTH)) {
+		XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				 XQSPIPS_TXD_00_OFFSET,
+				 *((u32 *)InstancePtr->SendBufferPtr));
+		InstancePtr->SendBufferPtr += 4;
+		InstancePtr->RemainingBytes -= 4;
+		if (InstancePtr->RemainingBytes < 0) {
+			InstancePtr->RemainingBytes = 0;
+		}
+		++TransCount;
+	}
+
+	while((InstancePtr->RemainingBytes > 0) ||
+	      (InstancePtr->RequestedBytes > 0)) {
+
+		/*
+		 * Fill the TX FIFO with RX threshold no. of entries (or as
+		 * many as we have to send, in case that's less).
+		 */
+		while ((InstancePtr->RemainingBytes > 0) &&
+			(TransCount < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
+			XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+					 XQSPIPS_TXD_00_OFFSET,
+					 *((u32 *)InstancePtr->SendBufferPtr));
+			InstancePtr->SendBufferPtr += 4;
+			InstancePtr->RemainingBytes -= 4;
+			if (InstancePtr->RemainingBytes < 0) {
+				InstancePtr->RemainingBytes = 0;
+			}
+			++TransCount;
+		}
+
+		/*
+		 * If, in Manual Start mode, start the transfer.
+		 */
+		if (IsManualStart == TRUE) {
+			ConfigReg = XQspiPs_ReadReg(
+					InstancePtr->Config.BaseAddress,
+					 XQSPIPS_CR_OFFSET);
+			ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+			XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+					 XQSPIPS_CR_OFFSET, ConfigReg);
+		}
+
+		/*
+		 * Reset TransCount - this is only used to fill TX FIFO
+		 * in the above loop;
+		 * RxCount is used to keep track of data received
+		 */
+		TransCount = 0;
+
+		/*
+		 * Wait for RX FIFO to reach threshold (or)
+		 * TX FIFO to become empty.
+		 * The latter check is required for
+		 * small transfers (<32 words) and
+		 * when the last chunk in a large data transfer is < 32 words.
+		 */
+
+		do {
+			StatusReg = XQspiPs_ReadReg(
+					InstancePtr->Config.BaseAddress,
+					XQSPIPS_SR_OFFSET);
+		} while ( ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0) &&
+			((StatusReg & XQSPIPS_IXR_RXNEMPTY_MASK) == 0) );
+
+		/*
+		 * A transmit has just completed. Process received data
+		 * and check for more data to transmit.
+		 * First get the data received as a result of the
+		 * transmit that just completed. Receive data based on the
+		 * count obtained while filling tx fifo. Always get
+		 * the received data, but only fill the receive
+		 * buffer if it points to something (the upper layer
+		 * software may not care to receive data).
+		 */
+		while ((InstancePtr->RequestedBytes > 0) &&
+			(RxCount < XQSPIPS_RXFIFO_THRESHOLD_OPT )) {
+			u32 Data;
+
+			RxCount++;
+
+			if (InstancePtr->RecvBufferPtr != NULL) {
+				if (InstancePtr->RequestedBytes < 4) {
+					Data = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XQSPIPS_RXD_OFFSET);
+					XQspiPs_GetReadData(InstancePtr, Data,
+						InstancePtr->RequestedBytes);
+				} else {
+					(*(u32 *)InstancePtr->RecvBufferPtr) =
+						XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XQSPIPS_RXD_OFFSET);
+					InstancePtr->RecvBufferPtr += 4;
+					InstancePtr->RequestedBytes -= 4;
+					if (InstancePtr->RequestedBytes < 0) {
+						InstancePtr->RequestedBytes = 0;
+					}
+				}
+			} else {
+				Data = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XQSPIPS_RXD_OFFSET);
+				InstancePtr->RequestedBytes -= 4;
+			}
+		}
+		RxCount = 0;
+	}
+
+	/*
+	 * If the Slave select lines are being manually controlled, disable
+	 * them because the transfer is complete.
+	 */
+	if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+		ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				 XQSPIPS_CR_OFFSET);
+		ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
+		XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XQSPIPS_CR_OFFSET, ConfigReg);
+	}
+
+	/*
+	 * Clear the busy flag.
+	 */
+	InstancePtr->IsBusy = FALSE;
+
+	/*
+	 * Disable the device.
+	 */
+	XQspiPs_Disable(InstancePtr);
+
+	/*
+	 * Reset the RX FIFO threshold to one
+	 */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Read the flash in Linear QSPI mode.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	RecvBufPtr is a pointer to a buffer for received data.
+* @param	Address is the starting address within the flash from
+*		from where data needs to be read.
+* @param	ByteCount contains the number of bytes to receive.
+*
+* @return
+*		- XST_SUCCESS if read is performed
+*		- XST_FAILURE if Linear mode is not set
+*
+* @note		None.
+*
+*
+******************************************************************************/
+int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
+			u32 Address, unsigned ByteCount)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(RecvBufPtr != NULL);
+	Xil_AssertNonvoid(ByteCount > 0);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+#ifdef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR
+	/*
+	 * Enable the controller
+	 */
+	XQspiPs_Enable(InstancePtr);
+
+	if (XQspiPs_GetLqspiConfigReg(InstancePtr) &
+		XQSPIPS_LQSPI_CR_LINEAR_MASK) {
+		memcpy((void*)RecvBufPtr,
+		      (const void*)(XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR +
+		       Address),
+		      (size_t)ByteCount);
+		return XST_SUCCESS;
+	} else {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Disable the controller
+	 */
+	XQspiPs_Disable(InstancePtr);
+
+#else
+	return XST_FAILURE;
+#endif
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Selects the slave with which the master communicates.
+*
+* The user is not allowed to select the slave while a transfer is in progress.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return
+*		- XST_SUCCESS if the slave is selected or deselected
+*		  successfully.
+*		- XST_DEVICE_BUSY if a transfer is in progress, slave cannot be
+*		  changed.
+*
+* @note
+*
+* This function only sets the slave which will be selected when a transfer
+* occurs. The slave is not selected when the QSPI is idle.
+*
+******************************************************************************/
+int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr)
+{
+	u32 ConfigReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Do not allow the slave select to change while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy) {
+		return XST_DEVICE_BUSY;
+	}
+
+	/*
+	 * Select the slave
+	 */
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPS_CR_OFFSET);
+	ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK;
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XQSPIPS_CR_OFFSET, ConfigReg);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Sets the status callback function, the status handler, which the driver
+* calls when it encounters conditions that should be reported to upper
+* layer software. The handler executes in an interrupt context, so it must
+* minimize the amount of processing performed. One of the following status
+* events is passed to the status handler.
+*
+* 
+*
+* XST_SPI_TRANSFER_DONE		The requested data transfer is done
+*
+* XST_SPI_TRANSMIT_UNDERRUN	As a slave device, the master clocked data
+*				but there were none available in the transmit
+*				register/FIFO. This typically means the slave
+*				application did not issue a transfer request
+*				fast enough, or the processor/driver could not
+*				fill the transmit register/FIFO fast enough.
+*
+* XST_SPI_RECEIVE_OVERRUN	The QSPI device lost data. Data was received
+*				but the receive data register/FIFO was full.
+*
+* 

+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	CallBackRef is the upper layer callback reference passed back
+*		when the callback function is invoked.
+* @param	FuncPtr is the pointer to the callback function.
+*
+* @return	None.
+*
+* @note
+*
+* The handler is called within interrupt context, so it should do its work
+* quickly and queue potentially time-consuming work to a task-level thread.
+*
+******************************************************************************/
+void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
+				XQspiPs_StatusHandler FuncPtr)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FuncPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	InstancePtr->StatusHandler = FuncPtr;
+	InstancePtr->StatusRef = CallBackRef;
+}
+
+/*****************************************************************************/
+/**
+*
+* This is a stub for the status callback. The stub is here in case the upper
+* layers forget to set the handler.
+*
+* @param	CallBackRef is a pointer to the upper layer callback reference
+* @param	StatusEvent is the event that just occurred.
+* @param	ByteCount is the number of bytes transferred up until the event
+*		occurred.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
+				unsigned ByteCount)
+{
+	(void) CallBackRef;
+	(void) StatusEvent;
+	(void) ByteCount;
+
+	Xil_AssertVoidAlways();
+}
+
+/*****************************************************************************/
+/**
+*
+* The interrupt handler for QSPI interrupts. This function must be connected
+* by the user to an interrupt controller.
+*
+* The interrupts that are handled are:
+*
+*
+* - Data Transmit Register (FIFO) Empty. This interrupt is generated when the
+*   transmit register or FIFO is empty. The driver uses this interrupt during a
+*   transmission to continually send/receive data until the transfer is done.
+*
+* - Data Transmit Register (FIFO) Underflow. This interrupt is generated when
+*   the QSPI device, when configured as a slave, attempts to read an empty
+*   DTR/FIFO.  An empty DTR/FIFO usually means that software is not giving the
+*   device data in a timely manner. No action is taken by the driver other than
+*   to inform the upper layer software of the error.
+*
+* - Data Receive Register (FIFO) Overflow. This interrupt is generated when the
+*   QSPI device attempts to write a received byte to an already full DRR/FIFO.
+*   A full DRR/FIFO usually means software is not emptying the data in a timely
+*   manner.  No action is taken by the driver other than to inform the upper
+*   layer software of the error.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	None.
+*
+* @note
+*
+* The slave select register is being set to deselect the slave when a transfer
+* is complete.
+*
+******************************************************************************/
+void XQspiPs_InterruptHandler(void *InstancePtr)
+{
+	XQspiPs *QspiPtr = (XQspiPs *)InstancePtr;
+	u32 IntrStatus;
+	u32 ConfigReg;
+	u32 Data;
+	u32 TransCount;
+	u32 Count = 0;
+	unsigned BytesDone; /* Number of bytes done so far. */
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(QspiPtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Immediately clear the interrupts in case the ISR causes another
+	 * interrupt to be generated. If we clear at the end of the ISR,
+	 * we may miss newly generated interrupts. This occurs because we
+	 * transmit from within the ISR, which could potentially cause another
+	 * TX_EMPTY interrupt.
+	 */
+	IntrStatus = XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
+				      XQSPIPS_SR_OFFSET);
+	XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_SR_OFFSET,
+			  (IntrStatus & XQSPIPS_IXR_WR_TO_CLR_MASK));
+	XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_IDR_OFFSET,
+			XQSPIPS_IXR_TXOW_MASK | XQSPIPS_IXR_RXNEMPTY_MASK |
+			XQSPIPS_IXR_RXOVR_MASK | XQSPIPS_IXR_TXUF_MASK);
+
+	if ((IntrStatus & XQSPIPS_IXR_TXOW_MASK) ||
+		(IntrStatus & XQSPIPS_IXR_RXNEMPTY_MASK)) {
+
+		/*
+		 * Rx FIFO has just reached threshold no. of entries.
+		 * Read threshold no. of entries from RX FIFO
+		 * Another possiblity of entering this loop is when
+		 * the last byte has been transmitted and TX FIFO is empty,
+		 * in which case, read all the data from RX FIFO.
+		 * Always get the received data, but only fill the
+		 * receive buffer if it is not null (it can be null when
+		 * the device does not care to receive data).
+		 */
+		TransCount = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes;
+		if (TransCount % 4) {
+			TransCount = TransCount/4 + 1;
+		} else {
+			TransCount = TransCount/4;
+		}
+
+		while ((Count < TransCount) &&
+			(Count < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
+
+			if (QspiPtr->RecvBufferPtr != NULL) {
+				if (QspiPtr->RequestedBytes < 4) {
+					Data = XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
+						XQSPIPS_RXD_OFFSET);
+					XQspiPs_GetReadData(QspiPtr, Data,
+						QspiPtr->RequestedBytes);
+				} else {
+					(*(u32 *)QspiPtr->RecvBufferPtr) =
+						XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
+						XQSPIPS_RXD_OFFSET);
+					QspiPtr->RecvBufferPtr += 4;
+					QspiPtr->RequestedBytes -= 4;
+					if (QspiPtr->RequestedBytes < 0) {
+						QspiPtr->RequestedBytes = 0;
+					}
+				}
+			} else {
+				XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
+						XQSPIPS_RXD_OFFSET);
+				QspiPtr->RequestedBytes -= 4;
+				if (QspiPtr->RequestedBytes < 0) {
+					QspiPtr->RequestedBytes = 0;
+				}
+
+			}
+			Count++;
+		}
+		Count = 0;
+		/*
+		 * Interrupt asserted as TX_OW got asserted
+		 * See if there is more data to send.
+		 * Fill TX FIFO with RX threshold no. of entries or
+		 * remaining entries (in case that is less than threshold)
+		 */
+		while ((QspiPtr->RemainingBytes > 0) &&
+			(Count < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
+			/*
+			 * Send more data.
+			 */
+			XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+				XQSPIPS_TXD_00_OFFSET,
+				*((u32 *)QspiPtr->SendBufferPtr));
+			QspiPtr->SendBufferPtr += 4;
+			QspiPtr->RemainingBytes -= 4;
+			if (QspiPtr->RemainingBytes < 0) {
+				QspiPtr->RemainingBytes = 0;
+			}
+
+			Count++;
+		}
+
+		if ((QspiPtr->RemainingBytes == 0) &&
+			(QspiPtr->RequestedBytes == 0)) {
+			/*
+			 * No more data to send.  Disable the interrupt
+			 * and inform the upper layer software that the
+			 * transfer is done. The interrupt will be re-enabled
+			 * when another transfer is initiated.
+			 */
+			XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+					  XQSPIPS_IDR_OFFSET,
+					  XQSPIPS_IXR_RXNEMPTY_MASK |
+					  XQSPIPS_IXR_TXOW_MASK |
+					  XQSPIPS_IXR_RXOVR_MASK |
+					  XQSPIPS_IXR_TXUF_MASK);
+
+			/*
+			 * If the Slave select is being manually controlled,
+			 * disable it because the transfer is complete.
+			 */
+			if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+				ConfigReg = XQspiPs_ReadReg(
+						QspiPtr->Config.BaseAddress,
+				 		XQSPIPS_CR_OFFSET);
+				ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
+				XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+						  XQSPIPS_CR_OFFSET,
+						   ConfigReg);
+			}
+
+			/*
+			 * Clear the busy flag.
+			 */
+			QspiPtr->IsBusy = FALSE;
+
+			/*
+			 * Disable the device.
+			 */
+			XQspiPs_Disable(QspiPtr);
+
+			/*
+			 * Reset the RX FIFO threshold to one
+			 */
+			XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+				XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+			QspiPtr->StatusHandler(QspiPtr->StatusRef,
+						XST_SPI_TRANSFER_DONE,
+						QspiPtr->RequestedBytes);
+		} else {
+			/*
+			 * Enable the TXOW interrupt.
+			 */
+			XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+					 XQSPIPS_IER_OFFSET,
+					 XQSPIPS_IXR_RXNEMPTY_MASK |
+					 XQSPIPS_IXR_TXOW_MASK |
+					 XQSPIPS_IXR_RXOVR_MASK |
+					 XQSPIPS_IXR_TXUF_MASK);
+			/*
+			 * If, in Manual Start mode, start the transfer.
+			 */
+			if (XQspiPs_IsManualStart(QspiPtr)) {
+				ConfigReg = XQspiPs_ReadReg(
+					QspiPtr->Config.BaseAddress,
+				 	 XQSPIPS_CR_OFFSET);
+				ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+				XQspiPs_WriteReg(
+					QspiPtr->Config.BaseAddress,
+					 XQSPIPS_CR_OFFSET, ConfigReg);
+			}
+		}
+	}
+
+	/*
+	 * Check for overflow and underflow errors.
+	 */
+	if (IntrStatus & XQSPIPS_IXR_RXOVR_MASK) {
+		BytesDone = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes;
+		QspiPtr->IsBusy = FALSE;
+
+		/*
+		 * If the Slave select lines is being manually controlled,
+		 * disable it because the transfer is complete.
+		 */
+		if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+			ConfigReg = XQspiPs_ReadReg(
+					QspiPtr->Config.BaseAddress,
+					XQSPIPS_CR_OFFSET);
+			ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
+			XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+				XQSPIPS_CR_OFFSET, ConfigReg);
+		}
+
+		/*
+		 * Disable the device.
+		 */
+		XQspiPs_Disable(QspiPtr);
+
+		/*
+		 * Reset the RX FIFO threshold to one
+		 */
+		XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+			XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+		QspiPtr->StatusHandler(QspiPtr->StatusRef,
+			XST_SPI_RECEIVE_OVERRUN, BytesDone);
+	}
+
+	if (IntrStatus & XQSPIPS_IXR_TXUF_MASK) {
+		BytesDone = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes;
+
+		QspiPtr->IsBusy = FALSE;
+		/*
+		 * If the Slave select lines is being manually controlled,
+		 * disable it because the transfer is complete.
+		 */
+		if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+			ConfigReg = XQspiPs_ReadReg(
+					QspiPtr->Config.BaseAddress,
+					XQSPIPS_CR_OFFSET);
+			ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
+			XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+					  XQSPIPS_CR_OFFSET, ConfigReg);
+		}
+
+		/*
+		 * Disable the device.
+		 */
+		XQspiPs_Disable(QspiPtr);
+
+		/*
+		 * Reset the RX FIFO threshold to one
+		 */
+		XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+			XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+		QspiPtr->StatusHandler(QspiPtr->StatusRef,
+				      XST_SPI_TRANSMIT_UNDERRUN, BytesDone);
+	}
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Copies data from Data to the Receive buffer.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	Data is the data which needs to be copied to the Rx buffer.
+* @param	Size is the number of bytes to be copied to the Receive buffer.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void XQspiPs_GetReadData(XQspiPs *InstancePtr, u32 Data, u8 Size)
+{
+	u8 DataByte3;
+
+	if (InstancePtr->RecvBufferPtr) {
+		switch (Size) {
+		case 1:
+			if (InstancePtr->ShiftReadData == 1) {
+				*((u8 *)InstancePtr->RecvBufferPtr) =
+					((Data & 0xFF000000) >> 24);
+			} else {
+				*((u8 *)InstancePtr->RecvBufferPtr) =
+					(Data & 0xFF);
+			}
+			InstancePtr->RecvBufferPtr += 1;
+			break;
+		case 2:
+			if (InstancePtr->ShiftReadData == 1) {
+				*((u16 *)InstancePtr->RecvBufferPtr) =
+					((Data & 0xFFFF0000) >> 16);
+			} else 	{
+				*((u16 *)InstancePtr->RecvBufferPtr) =
+					(Data & 0xFFFF);
+			}
+			InstancePtr->RecvBufferPtr += 2;
+			break;
+		case 3:
+			if (InstancePtr->ShiftReadData == 1) {
+				*((u16 *)InstancePtr->RecvBufferPtr) =
+					((Data & 0x00FFFF00) >> 8);
+				InstancePtr->RecvBufferPtr += 2;
+				DataByte3 = ((Data & 0xFF000000) >> 24);
+				*((u8 *)InstancePtr->RecvBufferPtr) = DataByte3;
+			} else {
+				*((u16 *)InstancePtr->RecvBufferPtr) =
+					(Data & 0xFFFF);
+				InstancePtr->RecvBufferPtr += 2;
+				DataByte3 = ((Data & 0x00FF0000) >> 16);
+				*((u8 *)InstancePtr->RecvBufferPtr) = DataByte3;
+			}
+			InstancePtr->RecvBufferPtr += 1;
+			break;
+		default:
+			/* This will never execute */
+			break;
+		}
+	}
+	InstancePtr->ShiftReadData  = 0;
+	InstancePtr->RequestedBytes -= Size;
+	if (InstancePtr->RequestedBytes < 0) {
+		InstancePtr->RequestedBytes = 0;
+	}
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/xqspips.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/xqspips.h
new file mode 100644
index 000000000..6a9e7f8b1
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/xqspips.h
@@ -0,0 +1,790 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips.h
+*
+* This file contains the implementation of the XQspiPs driver. It supports only
+* master mode. User documentation for the driver functions is contained in this
+* file in the form of comment blocks at the front of each function.
+*
+* A QSPI device connects to an QSPI bus through a 4-wire serial interface.
+* The QSPI bus is a full-duplex, synchronous bus that facilitates communication
+* between one master and one slave. The device is always full-duplex,
+* which means that for every byte sent, one is received, and vice-versa.
+* The master controls the clock, so it can regulate when it wants to
+* send or receive data. The slave is under control of the master, it must
+* respond quickly since it has no control of the clock and must send/receive
+* data as fast or as slow as the master does.
+*
+*  Linear Mode 
+* The Linear Quad-SPI Controller extends the existing Quad-SPI ControllerÂ’s
+* functionality by adding a linear addressing scheme that allows the SPI flash
+* memory subsystem to behave like a typical ROM device.  The new feature hides
+* the normal SPI protocol from a master reading from the SPI flash memory. The
+* feature improves both the user friendliness and the overall read memory
+* throughput over that of the current Quad-SPI Controller by lessening the
+* amount of software overheads required and by the use of the faster AXI
+* interface.
+*
+* Initialization & Configuration
+*
+* The XQspiPs_Config structure is used by the driver to configure itself. This
+* configuration structure is typically created by the tool-chain based on HW
+* build properties.
+*
+* To support multiple runtime loading and initialization strategies employed by
+* various operating systems, the driver instance can be initialized in the
+* following way:
+*	- XQspiPs_LookupConfig(DeviceId) - Use the device identifier to find
+*	  static configuration structure defined in xqspips_g.c. This is setup
+*	  by the tools. For some operating systems the config structure will be
+*	  initialized by the software and this call is not needed.
+*	- XQspiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+*	  configuration structure provided by the caller. If running in a system
+*	  with address translation, the provided virtual memory base address
+*	  replaces the physical address present in the configuration structure.
+*
+* Multiple Masters
+*
+* More than one master can exist, but arbitration is the responsibility of
+* the higher layer software. The device driver does not perform any type of
+* arbitration.
+*
+* Modes of Operation
+*
+* There are four modes to perform a data transfer and the selection of a mode
+* is based on Chip Select(CS) and Start. These two options individually, can
+* be controlled either by software(Manual) or hardware(Auto).
+* - Auto CS: Chip select is automatically asserted as soon as the first word
+*	     is written into the TXFIFO and de asserted when the TXFIFO becomes
+*	     empty
+* - Manual CS: Software must assert and de assert CS.
+* - Auto Start: Data transmission starts as soon as there is data in the
+*		TXFIFO and stalls when the TXFIFO is empty
+* - Manual Start: Software must start data transmission at the beginning of
+*		  the transaction or whenever the TXFIFO has become empty
+*
+* The preferred combination is Manual CS and Auto Start.
+* In this combination, the software asserts CS before loading any data into
+* TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it
+* out until TXFIFO becomes empty. The software reads the RXFIFO whenever the
+* data is available. If no further data, software disables CS.
+*
+* Risks/challenges of other combinations:
+* - Manual CS and Manual Start: Manual Start bit should be set after each
+*   TXFIFO write otherwise there could be a race condition where the TXFIFO
+*   becomes empty before the new word is written. In that case the
+*   transmission stops.
+* - Auto CS with Manual or Auto Start: It is very difficult for software to
+*   keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is de asserted.
+*   This results in a single transaction to be split into multiple pieces each
+*   with its own chip select. This will result in garbage data to be sent.
+*
+* Interrupts
+*
+* The user must connect the interrupt handler of the driver,
+* XQspiPs_InterruptHandler, to an interrupt system such that it will be
+* called when an interrupt occurs. This function does not save and restore
+* the processor context such that the user must provide this processing.
+*
+* The driver handles the following interrupts:
+* - Data Transmit Register/FIFO Underflow
+* - Data Receive Register/FIFO Not Empty
+* - Data Transmit Register/FIFO Overwater
+* - Data Receive Register/FIFO Overrun
+*
+* The Data Transmit Register/FIFO Overwater interrupt -- indicates that the
+* QSPI device has transmitted the data available to transmit, and now its data
+* register and FIFO is ready to accept more data. The driver uses this
+* interrupt to indicate progress while sending data.  The driver may have
+* more data to send, in which case the data transmit register and FIFO is
+* filled for subsequent transmission. When this interrupt arrives and all
+* the data has been sent, the driver invokes the status callback with a
+* value of XST_SPI_TRANSFER_DONE to inform the upper layer software that
+* all data has been sent.
+*
+* The Data Transmit Register/FIFO Underflow interrupt -- indicates that,
+* as slave, the QSPI device was required to transmit but there was no data
+* available to transmit in the transmit register (or FIFO). This may not
+* be an error if the master is not expecting data. But in the case where
+* the master is expecting data, this serves as a notification of such a
+* condition. The driver reports this condition to the upper layer
+* software through the status handler.
+*
+* The Data Receive Register/FIFO Overrun interrupt -- indicates that the QSPI
+* device received data and subsequently dropped the data because the data
+* receive register and FIFO was full. The driver reports this condition to the
+* upper layer software through the status handler. This likely indicates a
+* problem with the higher layer protocol, or a problem with the slave
+* performance.
+*
+*
+* Polled Operation
+*
+* Transfer in polled mode is supported through a separate interface function
+* XQspiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode,
+* this function blocks until all data has been sent/received.
+*
+* Device Busy
+*
+* Some operations are disallowed when the device is busy. The driver tracks
+* whether a device is busy. The device is considered busy when a data transfer
+* request is outstanding, and is considered not busy only when that transfer
+* completes (or is aborted with a mode fault error).
+*
+* Device Configuration
+*
+* The device can be configured in various ways during the FPGA implementation
+* process. Configuration parameters are stored in the xqspips_g.c file or
+* passed in via XQspiPs_CfgInitialize(). A table is defined where each entry
+* contains configuration information for an QSPI device, including the base
+* address for the device.
+*
+* RTOS Independence
+*
+* This driver is intended to be RTOS and processor independent.  It works with
+* physical addresses only.  Any needs for dynamic memory management, threads or
+* thread mutual exclusion, virtual memory, or cache control must be satisfied
+* by the layer above this driver.
+*
+* NOTE: This driver was always tested with endianess set to little-endian.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a sdm 11/25/10 First release, based on the PS SPI driver...
+* 1.01a sdm 11/22/11 Added TCL file for generating QSPI parameters
+*		     in xparameters.h
+* 2.00a kka 07/25/12 Added a few register defines for CR 670297
+* 		     Removed code related to mode fault for CR 671468
+*		     The XQspiPs_SetSlaveSelect has been modified to remove
+*		     the argument of the slave select as the QSPI controller
+*		     only supports one slave.
+* 		     XQspiPs_GetSlaveSelect API has been removed
+* 		     Added a flag ShiftReadData to the instance structure
+*.		     and is used in the XQspiPs_GetReadData API.
+*		     The ShiftReadData Flag indicates whether the data
+*		     read from the Rx FIFO needs to be shifted
+*		     in cases where the data is less than 4  bytes
+* 		     Removed the selection for the following options:
+*		     Master mode (XQSPIPS_MASTER_OPTION) and
+*		     Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
+*		     as the QSPI driver supports the Master mode
+*		     and Flash Interface mode and doesnot support
+*		     Slave mode or the legacy mode.
+*		     Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
+*		     APIs so that the last argument (IsInst) specifying whether
+*		     it is instruction or data has been removed. The first byte
+*		     in the SendBufPtr argument of these APIs specify the
+*		     instruction to be sent to the Flash Device.
+*		     This version of the driver fixes CRs 670197/663787/
+*		     670297/671468.
+* 		     Added the option for setting the Holdb_dr bit in the
+*		     configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
+*		     is the option to be used for setting this bit in the
+*		     configuration register.
+*		     The XQspiPs_PolledTransfer function has been updated
+*		     to fill the data to fifo depth.
+* 2.01a sg  02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
+*		     Added macros for Set/Get Rx Watermark. Changed QSPI
+*		     Enable/Disable macro argument from BaseAddress to
+*		     Instance Pointer. Added DelayNss argument to SetDelays
+*		     and GetDelays API's.
+*		     Created macros XQspiPs_IsManualStart and
+*		     XQspiPs_IsManualChipSelect.
+*		     Changed QSPI transfer logic for polled and interrupt
+*		     modes to be based on filled tx fifo count and receive
+*		     based on it. RXNEMPTY interrupt is not used.
+*		     Added assertions to XQspiPs_LqspiRead function.
+*		     SetDelays and GetDelays API's include DelayNss parameter.
+*		     Added defines for DelayNss,Rx Watermark,Interrupts
+*		     which need write to clear. Removed Read zeros mask from
+*		     LQSPI Config register. Renamed Fixed burst error to
+*		     data FSM error in  LQSPI Status register.
+*
+* 2.02a hk  05/07/13 Added ConnectionMode to config structure.
+*			 Corresponds to C_QSPI_MODE - 0:Single, 1:Stacked, 2:Parallel
+*			 Added enable and disable to the XQspiPs_LqspiRead() function
+*			 Removed XQspi_Reset() in Set_Options() function when
+*			 LQSPI_MODE_OPTION is set.
+*            Added instructions for bank selection, die erase and
+*            flag status register to the flash instruction table
+*            Handling for instructions not in flash instruction
+*			 table added. Checking for Tx FIFO empty when switching from
+*			 TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
+*            byte count 3 (spansion), instruction size and TXD register
+*			 changed accordingly. CR# 712502 and 703869.
+*            Added prefix to constant definitions for ConnectionMode
+*            Added (#ifdef linear base address) in the Linear read function.
+*            Changed  XPAR_XQSPIPS_0_LINEAR_BASEADDR to
+*            XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
+*            XQspiPs_LqspiRead function. Fix for CR#718141.
+*
+* 2.03a hk  09/17/13 Modified polled and interrupt transfers to make use of
+*                    thresholds. This is to improve performance.
+*                    Added API's for QSPI reset and
+*                    linear mode initialization for boot.
+*                    Added RX and TX threshold reset to one in XQspiPs_Abort.
+*                    Added RX threshold reset(1) after transfer in polled and
+*                    interrupt transfers. Made changes to make sure threshold
+*                    change is done only when no transfer is in progress.
+*                    Updated linear init API for parallel and stacked modes.
+*                    CR#737760.
+*
+* 

+*
+******************************************************************************/
+#ifndef XQSPIPS_H		/* prevent circular inclusions */
+#define XQSPIPS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xqspips_hw.h"
+#include 
+
+/************************** Constant Definitions *****************************/
+
+/** @name Configuration options
+ *
+ * The following options are supported to enable/disable certain features of
+ * an QSPI device.  Each of the options is a bit mask, so more than one may be
+ * specified.
+ *
+ *
+ * The Active Low Clock option configures the device's clock polarity.
+ * Setting this option means the clock is active low and the SCK signal idles
+ * high. By default, the clock is active high and SCK idles low.
+ *
+ * The Clock Phase option configures the QSPI device for one of two
+ * transfer formats.  A clock phase of 0, the default, means data is valid on
+ * the first SCK edge (rising or falling) after the slave select (SS) signal
+ * has been asserted. A clock phase of 1 means data is valid on the second SCK
+ * edge (rising or falling) after SS has been asserted.
+ *
+ *
+ * The QSPI Force Slave Select option is used to enable manual control of
+ * the slave select signal.
+ * 0: The SPI_SS signal is controlled by the QSPI controller during
+ * transfers. (Default)
+ * 1: The SPI_SS signal is forced active (driven low) regardless of any
+ * transfers in progress.
+ *
+ * NOTE: The driver will handle setting and clearing the Slave Select when
+ * the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the
+ * QSPI clock to be set to a faster speed. If the QSPI clock is too fast, the
+ * processor cannot empty and refill the FIFOs before the TX FIFO is empty
+ * When the QSPI hardware is controlling the Slave Select signals, this
+ * will cause slave to be de-selected and terminate the transfer.
+ *
+ * The Manual Start option is used to enable manual control of
+ * the Start command to perform data transfer.
+ * 0: The Start command is controlled by the QSPI controller during
+ * transfers(Default). Data transmission starts as soon as there is data in
+ * the TXFIFO and stalls when the TXFIFO is empty
+ * 1: The Start command must be issued by software to perform data transfer.
+ * Bit 15 of Configuration register is used to issue Start command. This bit
+ * must be set whenever TXFIFO is filled with new data.
+ *
+ * NOTE: The driver will set the Manual Start Enable bit in Configuration
+ * Register, if Manual Start option is selected. Software will issue
+ * Manual Start command whenever TXFIFO is filled with data. When there is
+ * no further data, driver will clear the Manual Start Enable bit.
+ *
+ * @{
+ */
+#define XQSPIPS_CLK_ACTIVE_LOW_OPTION	0x2  /**< Active Low Clock option */
+#define XQSPIPS_CLK_PHASE_1_OPTION	0x4  /**< Clock Phase one option */
+#define XQSPIPS_FORCE_SSELECT_OPTION	0x10 /**< Force Slave Select */
+#define XQSPIPS_MANUAL_START_OPTION	0x20 /**< Manual Start enable */
+#define XQSPIPS_LQSPI_MODE_OPTION	0x80 /**< Linear QPSI mode */
+#define XQSPIPS_HOLD_B_DRIVE_OPTION	0x100 /**< Drive HOLD_B Pin */
+/*@}*/
+
+
+/** @name QSPI Clock Prescaler options
+ * The QSPI Clock Prescaler Configuration bits are used to program master mode
+ * bit rate. The bit rate can be programmed in divide-by-two decrements from
+ * pclk/2 to pclk/256.
+ *
+ * @{
+ */
+#define XQSPIPS_CLK_PRESCALE_2		0x00 /**< PCLK/2 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_4		0x01 /**< PCLK/4 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_8		0x02 /**< PCLK/8 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_16		0x03 /**< PCLK/16 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_32		0x04 /**< PCLK/32 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_64		0x05 /**< PCLK/64 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_128	0x06 /**< PCLK/128 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_256	0x07 /**< PCLK/256 Prescaler */
+
+/*@}*/
+
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that are passed to
+ * a handler from the driver.  These constants are not bit masks such that
+ * only one will be passed at a time to the handler.
+ *
+ * @{
+ */
+#define XQSPIPS_EVENT_TRANSFER_DONE	2 /**< Transfer done */
+#define XQSPIPS_EVENT_TRANSMIT_UNDERRUN 3 /**< TX FIFO empty */
+#define XQSPIPS_EVENT_RECEIVE_OVERRUN	4 /**< Receive data loss because
+						RX FIFO full */
+/*@}*/
+
+/** @name Flash commands
+ *
+ * The following constants define most of the commands supported by flash
+ * devices. Users can add more commands supported by the flash devices
+ *
+ * @{
+ */
+#define	XQSPIPS_FLASH_OPCODE_WRSR	0x01 /* Write status register */
+#define	XQSPIPS_FLASH_OPCODE_PP		0x02 /* Page program */
+#define	XQSPIPS_FLASH_OPCODE_NORM_READ	0x03 /* Normal read data bytes */
+#define	XQSPIPS_FLASH_OPCODE_WRDS	0x04 /* Write disable */
+#define	XQSPIPS_FLASH_OPCODE_RDSR1	0x05 /* Read status register 1 */
+#define	XQSPIPS_FLASH_OPCODE_WREN	0x06 /* Write enable */
+#define	XQSPIPS_FLASH_OPCODE_FAST_READ	0x0B /* Fast read data bytes */
+#define	XQSPIPS_FLASH_OPCODE_BE_4K	0x20 /* Erase 4KiB block */
+#define	XQSPIPS_FLASH_OPCODE_RDSR2	0x35 /* Read status register 2 */
+#define	XQSPIPS_FLASH_OPCODE_DUAL_READ	0x3B /* Dual read data bytes */
+#define	XQSPIPS_FLASH_OPCODE_BE_32K	0x52 /* Erase 32KiB block */
+#define	XQSPIPS_FLASH_OPCODE_QUAD_READ	0x6B /* Quad read data bytes */
+#define	XQSPIPS_FLASH_OPCODE_ERASE_SUS	0x75 /* Erase suspend */
+#define	XQSPIPS_FLASH_OPCODE_ERASE_RES	0x7A /* Erase resume */
+#define	XQSPIPS_FLASH_OPCODE_RDID	0x9F /* Read JEDEC ID */
+#define	XQSPIPS_FLASH_OPCODE_BE		0xC7 /* Erase whole flash block */
+#define	XQSPIPS_FLASH_OPCODE_SE		0xD8 /* Sector erase (usually 64KB)*/
+#define XQSPIPS_FLASH_OPCODE_DUAL_IO_READ 0xBB /* Read data using Dual I/O */
+#define XQSPIPS_FLASH_OPCODE_QUAD_IO_READ 0xEB /* Read data using Quad I/O */
+#define XQSPIPS_FLASH_OPCODE_BRWR	0x17 /* Bank Register Write */
+#define XQSPIPS_FLASH_OPCODE_BRRD	0x16 /* Bank Register Read */
+/* Extende Address Register Write - Micron's equivalent of Bank Register */
+#define XQSPIPS_FLASH_OPCODE_EARWR	0xC5
+/* Extende Address Register Read - Micron's equivalent of Bank Register */
+#define XQSPIPS_FLASH_OPCODE_EARRD	0xC8
+#define XQSPIPS_FLASH_OPCODE_DIE_ERASE	0xC4
+#define XQSPIPS_FLASH_OPCODE_READ_FLAG_SR	0x70
+#define XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR	0x50
+#define XQSPIPS_FLASH_OPCODE_READ_LOCK_REG	0xE8	/* Lock register Read */
+#define XQSPIPS_FLASH_OPCODE_WRITE_LOCK_REG	0xE5	/* Lock Register Write */
+
+/*@}*/
+
+/** @name Instruction size
+ *
+ * The following constants define numbers 1 to 4.
+ * Used to identify whether TXD0,1,2 or 3 is to be used.
+ *
+ * @{
+ */
+#define XQSPIPS_SIZE_ONE 	1
+#define XQSPIPS_SIZE_TWO 	2
+#define XQSPIPS_SIZE_THREE 	3
+#define XQSPIPS_SIZE_FOUR 	4
+
+/*@}*/
+
+/** @name ConnectionMode
+ *
+ * The following constants are the possible values of ConnectionMode in
+ * Config structure.
+ *
+ * @{
+ */
+#define XQSPIPS_CONNECTION_MODE_SINGLE		0
+#define XQSPIPS_CONNECTION_MODE_STACKED		1
+#define XQSPIPS_CONNECTION_MODE_PARALLEL	2
+
+/*@}*/
+
+/** @name FIFO threshold value
+ *
+ * This is the Rx FIFO threshold (in words) that was found to be most
+ * optimal in terms of performance
+ *
+ * @{
+ */
+#define XQSPIPS_RXFIFO_THRESHOLD_OPT		32
+
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+/**
+ * The handler data type allows the user to define a callback function to
+ * handle the asynchronous processing for the QSPI device.  The application
+ * using this driver is expected to define a handler of this type to support
+ * interrupt driven mode.  The handler executes in an interrupt context, so
+ * only minimal processing should be performed.
+ *
+ * @param	CallBackRef is the callback reference passed in by the upper
+ *		layer when setting the callback functions, and passed back to
+ *		the upper layer when the callback is invoked. Its type is
+ *		not important to the driver, so it is a void pointer.
+ * @param 	StatusEvent holds one or more status events that have occurred.
+ *		See the XQspiPs_SetStatusHandler() for details on the status
+ *		events that can be passed in the callback.
+ * @param	ByteCount indicates how many bytes of data were successfully
+ *		transferred.  This may be less than the number of bytes
+ *		requested if the status event indicates an error.
+ */
+typedef void (*XQspiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent,
+					unsigned ByteCount);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID  of device */
+	u32 BaseAddress;	/**< Base address of the device */
+	u32 InputClockHz;	/**< Input clock frequency */
+	u8  ConnectionMode; /**< Single, Stacked and Parallel mode */
+} XQspiPs_Config;
+
+/**
+ * The XQspiPs driver instance data. The user is required to allocate a
+ * variable of this type for every QSPI device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XQspiPs_Config Config;	 /**< Configuration structure */
+	u32 IsReady;		 /**< Device is initialized and ready */
+
+	u8 *SendBufferPtr;	 /**< Buffer to send (state) */
+	u8 *RecvBufferPtr;	 /**< Buffer to receive (state) */
+	int RequestedBytes;	 /**< Number of bytes to transfer (state) */
+	int RemainingBytes;	 /**< Number of bytes left to transfer(state) */
+	u32 IsBusy;		 /**< A transfer is in progress (state) */
+	XQspiPs_StatusHandler StatusHandler;
+	void *StatusRef;  	 /**< Callback reference for status handler */
+	u32 ShiftReadData;	 /**<  Flag to indicate whether the data
+				   *   read from the Rx FIFO needs to be shifted
+				   *   in cases where the data is less than 4
+				   *   bytes
+				   */
+} XQspiPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/*
+*
+* Check in OptionsTable if Manual Start Option is enabled or disabled.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return
+*		- TRUE if option is set
+*		- FALSE if option is not set
+*
+* @note		C-Style signature:
+*		u8 XQspiPs_IsManualStart(XQspiPs *InstancePtr);
+*
+*****************************************************************************/
+#define XQspiPs_IsManualStart(InstancePtr) \
+	((XQspiPs_GetOptions(InstancePtr) & \
+	  XQSPIPS_MANUAL_START_OPTION) ? TRUE : FALSE)
+
+/****************************************************************************/
+/*
+*
+* Check in OptionsTable if Manual Chip Select Option is enabled or disabled.
+*
+* @param	InstancePtr is a pointer to the XSpiPs instance.
+*
+* @return
+*		- TRUE if option is set
+*		- FALSE if option is not set
+*
+* @note		C-Style signature:
+*		u8 XQspiPs_IsManualChipSelect(XQspiPs *InstancePtr);
+*
+*****************************************************************************/
+#define XQspiPs_IsManualChipSelect(InstancePtr) \
+	((XQspiPs_GetOptions(InstancePtr) & \
+	  XQSPIPS_FORCE_SSELECT_OPTION) ? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the slave idle count register.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	RegisterValue is the value to be written, valid values are
+*		0-255.
+*
+* @return	None
+*
+* @note
+* C-Style signature:
+*	void XQspiPs_SetSlaveIdle(XQspiPs *InstancePtr, u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetSlaveIdle(InstancePtr, RegisterValue)	\
+	XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + 	\
+			XQSPIPS_SICR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the slave idle count register. Use the XQSPIPS_SICR_*
+* constants defined in xqspips_hw.h to interpret the bit-mask returned.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	An 8-bit value representing Slave Idle Count.
+*
+* @note		C-Style signature:
+*		u32 XQspiPs_GetSlaveIdle(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetSlaveIdle(InstancePtr)				\
+	XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + 		\
+	XQSPIPS_SICR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the transmit FIFO watermark register.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	RegisterValue is the value to be written, valid values are 1-63.
+*
+* @return	None.
+*
+* @note
+* C-Style signature:
+*	void XQspiPs_SetTXWatermark(XQspiPs *InstancePtr, u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetTXWatermark(InstancePtr, RegisterValue)		\
+	XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + 		\
+			XQSPIPS_TXWR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the transmit FIFO watermark register.
+* Valid values are in the range 1-63.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	A 6-bit value representing Tx Watermark level.
+*
+* @note		C-Style signature:
+*		u32 XQspiPs_GetTXWatermark(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetTXWatermark(InstancePtr)				\
+	XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the receive FIFO watermark register.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	RegisterValue is the value to be written, valid values are 1-63.
+*
+* @return	None.
+*
+* @note
+* C-Style signature:
+*	void XQspiPs_SetRXWatermark(XQspiPs *InstancePtr, u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetRXWatermark(InstancePtr, RegisterValue)		\
+	XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + 		\
+			XQSPIPS_RXWR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the receive FIFO watermark register.
+* Valid values are in the range 1-63.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	A 6-bit value representing Rx Watermark level.
+*
+* @note		C-Style signature:
+*		u32 XQspiPs_GetRXWatermark(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetRXWatermark(InstancePtr)				\
+	XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Enable the device and uninhibit master transactions.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XQspiPs_Enable(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_Enable(InstancePtr)					\
+	XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \
+			XQSPIPS_ER_ENABLE_MASK)
+
+/****************************************************************************/
+/**
+*
+* Disable the device.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XQspiPs_Disable(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_Disable(InstancePtr)					\
+	XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the Linear QSPI Configuration register.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	RegisterValue is the value to be written to the Linear QSPI
+*		configuration register.
+*
+* @return	None.
+*
+* @note
+* C-Style signature:
+*	void XQspiPs_SetLqspiConfigReg(XQspiPs *InstancePtr,
+*					u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetLqspiConfigReg(InstancePtr, RegisterValue)		\
+	XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) +		\
+			XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the Linear QSPI Configuration register.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	A 32-bit value representing the contents of the LQSPI Config
+*		register.
+*
+* @note		C-Style signature:
+*		u32 XQspiPs_GetLqspiConfigReg(u32 *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetLqspiConfigReg(InstancePtr)				\
+	XQspiPs_In32((InstancePtr->Config.BaseAddress) +		\
+			XQSPIPS_LQSPI_CR_OFFSET)
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Initialization function, implemented in xqspips_sinit.c
+ */
+XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Functions implemented in xqspips.c
+ */
+int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config * Config,
+			   u32 EffectiveAddr);
+void XQspiPs_Reset(XQspiPs *InstancePtr);
+void XQspiPs_Abort(XQspiPs *InstancePtr);
+
+int XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
+		      unsigned ByteCount);
+int XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
+			    u8 *RecvBufPtr, unsigned ByteCount);
+int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
+			u32 Address, unsigned ByteCount);
+
+int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr);
+
+void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
+				XQspiPs_StatusHandler FuncPtr);
+void XQspiPs_InterruptHandler(void *InstancePtr);
+
+/*
+ * Functions for selftest, in xqspips_selftest.c
+ */
+int XQspiPs_SelfTest(XQspiPs *InstancePtr);
+
+/*
+ * Functions for options, in xqspips_options.c
+ */
+int XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options);
+u32 XQspiPs_GetOptions(XQspiPs *InstancePtr);
+
+int XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler);
+u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr);
+
+int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
+			 u8 DelayAfter, u8 DelayInit);
+void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
+			 u8 *DelayAfter, u8 *DelayInit);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/xqspips_g.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/xqspips_g.c
new file mode 100644
index 000000000..815886466
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/xqspips_g.c
@@ -0,0 +1,33 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSM.
+* Version: 
+* DO NOT EDIT.
+*
+*  v (64-bit)
+SW Build (by ) on 
+Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xqspips.h"
+
+/*
+* The configuration table for devices
+*/
+
+XQspiPs_Config XQspiPs_ConfigTable[] =
+{
+	{
+		XPAR_PS7_QSPI_0_DEVICE_ID,
+		XPAR_PS7_QSPI_0_BASEADDR,
+		XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ,
+		XPAR_PS7_QSPI_0_QSPI_MODE
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/xqspips_hw.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/xqspips_hw.c
new file mode 100644
index 000000000..db8657053
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/xqspips_hw.c
@@ -0,0 +1,228 @@
+/******************************************************************************
+*
+* (c) Copyright 2013 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_hw.c
+*
+* Contains low level functions, primarily reset related.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 2.03a hk  09/17/13 First release
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xqspips_hw.h"
+#include "xqspips.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Pre-scaler value for divided by 4
+ *
+ * Pre-scaler value for divided by 4
+ *
+ * @{
+ */
+#define XQSPIPS_CR_PRESC_DIV_BY_4	0x01
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Resets QSPI by disabling the device and bringing it to reset state through
+* register writes.
+*
+* @param	None
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XQspiPs_ResetHw(u32 BaseAddress)
+{
+	u32 ConfigReg;
+
+	/*
+	 * Disable interrupts
+	 */
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_IDR_OFFSET,
+				XQSPIPS_IXR_DISABLE_ALL);
+
+	/*
+	 * Disable device
+	 */
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET,
+				0);
+
+	/*
+	 * De-assert slave select lines.
+	 */
+	ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
+	ConfigReg |= (XQSPIPS_CR_SSCTRL_MASK | XQSPIPS_CR_SSFORCE_MASK);
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
+
+	/*
+	 * Write default value to RX and TX threshold registers
+	 * RX threshold should be set to 1 here because the corresponding
+	 * status bit is used next to clear the RXFIFO
+	 */
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_TXWR_OFFSET,
+			(XQSPIPS_TXWR_RESET_VALUE & XQSPIPS_TXWR_MASK));
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_RXWR_OFFSET,
+			(XQSPIPS_RXWR_RESET_VALUE & XQSPIPS_RXWR_MASK));
+
+	/*
+	 * Clear RXFIFO
+	 */
+	while ((XQspiPs_ReadReg(BaseAddress,XQSPIPS_SR_OFFSET) &
+		XQSPIPS_IXR_RXNEMPTY_MASK) != 0) {
+		XQspiPs_ReadReg(BaseAddress, XQSPIPS_RXD_OFFSET);
+	}
+
+	/*
+	 * Clear status register by reading register and
+	 * writing 1 to clear the write to clear bits
+	 */
+	XQspiPs_ReadReg(BaseAddress, XQSPIPS_SR_OFFSET);
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_SR_OFFSET,
+				XQSPIPS_IXR_WR_TO_CLR_MASK);
+
+	/*
+	 * Write default value to configuration register
+	 */
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET,
+				XQSPIPS_CR_RESET_STATE);
+
+
+	/*
+	 * De-select linear mode
+	 */
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET,
+				0x0);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Initializes QSPI to Linear mode with default QSPI boot settings.
+*
+* @param	None
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XQspiPs_LinearInit(u32 BaseAddress)
+{
+	u32 BaudRateDiv;
+	u32 LinearCfg;
+
+	/*
+	 * Baud rate divisor for dividing by 4. Value of CR bits [5:3]
+	 * should be set to 0x001; hence shift the value and use the mask.
+	 */
+	BaudRateDiv = ( (XQSPIPS_CR_PRESC_DIV_BY_4) <<
+			XQSPIPS_CR_PRESC_SHIFT) & XQSPIPS_CR_PRESC_MASK;
+	/*
+	 * Write configuration register with default values, slave selected &
+	 * pre-scaler value for divide by 4
+	 */
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET,
+				((XQSPIPS_CR_RESET_STATE |
+				XQSPIPS_CR_HOLD_B_MASK | BaudRateDiv) &
+				(~XQSPIPS_CR_SSCTRL_MASK) ));
+
+	/*
+	 * Write linear configuration register with default value -
+	 * enable linear mode and use fast read.
+	 */
+
+	if(XPAR_PS7_QSPI_0_QSPI_MODE == XQSPIPS_CONNECTION_MODE_SINGLE){
+
+		LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE;
+
+	}else if(XPAR_PS7_QSPI_0_QSPI_MODE ==
+			XQSPIPS_CONNECTION_MODE_STACKED){
+
+		LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE |
+				XQSPIPS_LQSPI_CR_TWO_MEM_MASK;
+
+	}else if(XPAR_PS7_QSPI_0_QSPI_MODE ==
+	 		XQSPIPS_CONNECTION_MODE_PARALLEL){
+
+		LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE |
+				XQSPIPS_LQSPI_CR_TWO_MEM_MASK |
+		 		XQSPIPS_LQSPI_CR_SEP_BUS_MASK;
+
+	}
+
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET,
+				LinearCfg);
+
+	/*
+	 * Enable device
+	 */
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET,
+				XQSPIPS_ER_ENABLE_MASK);
+
+}
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/xqspips_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/xqspips_hw.h
new file mode 100644
index 000000000..8e77c75ab
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/xqspips_hw.h
@@ -0,0 +1,381 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_hw.h
+*
+* This header file contains the identifiers and basic HW access driver
+* functions (or  macros) that can be used to access the device. Other driver
+* functions are defined in xqspips.h.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00  sdm 11/25/10 First release
+* 2.00a ka  07/25/12 Added a few register defines for CR 670297
+*		     and removed some defines of reserved fields for
+*		     CR 671468
+*		     Added define XQSPIPS_CR_HOLD_B_MASK for Holdb_dr
+*		     bit in Configuration register.
+* 2.01a sg  02/03/13 Added defines for DelayNss,Rx Watermark,Interrupts
+*		     which need write to clear. Removed Read zeros mask from
+*		     LQSPI Config register.
+* 2.03a hk  08/22/13 Added prototypes of API's for QSPI reset and
+*                    linear mode initialization for boot. Added related
+*                    constant definitions.
+*
+* 

+*
+******************************************************************************/
+#ifndef XQSPIPS_HW_H		/* prevent circular inclusions */
+#define XQSPIPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of an QSPI device.
+ * @{
+ */
+#define XQSPIPS_CR_OFFSET	 	0x00 /**< Configuration Register */
+#define XQSPIPS_SR_OFFSET	 	0x04 /**< Interrupt Status */
+#define XQSPIPS_IER_OFFSET	 	0x08 /**< Interrupt Enable */
+#define XQSPIPS_IDR_OFFSET	 	0x0c /**< Interrupt Disable */
+#define XQSPIPS_IMR_OFFSET	 	0x10 /**< Interrupt Enabled Mask */
+#define XQSPIPS_ER_OFFSET	 	0x14 /**< Enable/Disable Register */
+#define XQSPIPS_DR_OFFSET	 	0x18 /**< Delay Register */
+#define XQSPIPS_TXD_00_OFFSET	 	0x1C /**< Transmit 4-byte inst/data */
+#define XQSPIPS_RXD_OFFSET	 	0x20 /**< Data Receive Register */
+#define XQSPIPS_SICR_OFFSET	 	0x24 /**< Slave Idle Count */
+#define XQSPIPS_TXWR_OFFSET	 	0x28 /**< Transmit FIFO Watermark */
+#define XQSPIPS_RXWR_OFFSET	 	0x2C /**< Receive FIFO Watermark */
+#define XQSPIPS_GPIO_OFFSET	 	0x30 /**< GPIO Register */
+#define XQSPIPS_LPBK_DLY_ADJ_OFFSET	0x38 /**< Loopback Delay Adjust Reg */
+#define XQSPIPS_TXD_01_OFFSET	 	0x80 /**< Transmit 1-byte inst */
+#define XQSPIPS_TXD_10_OFFSET	 	0x84 /**< Transmit 2-byte inst */
+#define XQSPIPS_TXD_11_OFFSET	 	0x88 /**< Transmit 3-byte inst */
+#define XQSPIPS_LQSPI_CR_OFFSET  	0xA0 /**< Linear QSPI config register */
+#define XQSPIPS_LQSPI_SR_OFFSET  	0xA4 /**< Linear QSPI status register */
+#define XQSPIPS_MOD_ID_OFFSET  		0xFC /**< Module ID register */
+
+/* @} */
+
+/** @name Configuration Register
+ *
+ * This register contains various control bits that
+ * affect the operation of the QSPI device. Read/Write.
+ * @{
+ */
+
+#define XQSPIPS_CR_IFMODE_MASK    0x80000000 /**< Flash mem interface mode */
+#define XQSPIPS_CR_ENDIAN_MASK    0x04000000 /**< Tx/Rx FIFO endianness */
+#define XQSPIPS_CR_MANSTRT_MASK   0x00010000 /**< Manual Transmission Start */
+#define XQSPIPS_CR_MANSTRTEN_MASK 0x00008000 /**< Manual Transmission Start
+						   Enable */
+#define XQSPIPS_CR_SSFORCE_MASK   0x00004000 /**< Force Slave Select */
+#define XQSPIPS_CR_SSCTRL_MASK    0x00000400 /**< Slave Select Decode */
+#define XQSPIPS_CR_SSCTRL_SHIFT   10	      /**< Slave Select Decode shift */
+#define XQSPIPS_CR_DATA_SZ_MASK   0x000000C0 /**< Size of word to be
+						   transferred */
+#define XQSPIPS_CR_PRESC_MASK     0x00000038 /**< Prescaler Setting */
+#define XQSPIPS_CR_PRESC_SHIFT    3	      /**< Prescaler shift */
+#define XQSPIPS_CR_PRESC_MAXIMUM  0x07	      /**< Prescaler maximum value */
+
+#define XQSPIPS_CR_CPHA_MASK      0x00000004 /**< Phase Configuration */
+#define XQSPIPS_CR_CPOL_MASK      0x00000002 /**< Polarity Configuration */
+
+#define XQSPIPS_CR_MSTREN_MASK    0x00000001 /**< Master Mode Enable */
+
+#define XQSPIPS_CR_HOLD_B_MASK    0x00080000 /**< HOLD_B Pin Drive Enable */
+
+/* Deselect the Slave select line and set the transfer size to 32 at reset */
+#define XQSPIPS_CR_RESET_STATE    (XQSPIPS_CR_IFMODE_MASK | \
+				   XQSPIPS_CR_SSCTRL_MASK | \
+				   XQSPIPS_CR_DATA_SZ_MASK | \
+				   XQSPIPS_CR_MSTREN_MASK)
+/* @} */
+
+
+/** @name QSPI Interrupt Registers
+ *
+ * QSPI Status Register
+ *
+ * This register holds the interrupt status flags for an QSPI device. Some
+ * of the flags are level triggered, which means that they are set as long
+ * as the interrupt condition exists. Other flags are edge triggered,
+ * which means they are set once the interrupt condition occurs and remain
+ * set until they are cleared by software. The interrupts are cleared by
+ * writing a '1' to the interrupt bit position in the Status Register.
+ * Read/Write.
+ *
+ * QSPI Interrupt Enable Register
+ *
+ * This register is used to enable chosen interrupts for an QSPI device.
+ * Writing a '1' to a bit in this register sets the corresponding bit in the
+ * QSPI Interrupt Mask register.  Write only.
+ *
+ * QSPI Interrupt Disable Register 
+ *
+ * This register is used to disable chosen interrupts for an QSPI device.
+ * Writing a '1' to a bit in this register clears the corresponding bit in the
+ * QSPI Interrupt Mask register. Write only.
+ *
+ * QSPI Interrupt Mask Register
+ *
+ * This register shows the enabled/disabled interrupts of an QSPI device.
+ * Read only.
+ *
+ * All four registers have the same bit definitions. They are only defined once
+ * for each of the Interrupt Enable Register, Interrupt Disable Register,
+ * Interrupt Mask Register, and Channel Interrupt Status Register
+ * @{
+ */
+
+#define XQSPIPS_IXR_TXUF_MASK	   0x00000040  /**< QSPI Tx FIFO Underflow */
+#define XQSPIPS_IXR_RXFULL_MASK    0x00000020  /**< QSPI Rx FIFO Full */
+#define XQSPIPS_IXR_RXNEMPTY_MASK  0x00000010  /**< QSPI Rx FIFO Not Empty */
+#define XQSPIPS_IXR_TXFULL_MASK    0x00000008  /**< QSPI Tx FIFO Full */
+#define XQSPIPS_IXR_TXOW_MASK	   0x00000004  /**< QSPI Tx FIFO Overwater */
+#define XQSPIPS_IXR_RXOVR_MASK	   0x00000001  /**< QSPI Rx FIFO Overrun */
+#define XQSPIPS_IXR_DFLT_MASK	   0x00000025  /**< QSPI default interrupts
+						    mask */
+#define XQSPIPS_IXR_WR_TO_CLR_MASK 0x00000041  /**< Interrupts which
+						    need write to clear */
+#define XQSPIPS_ISR_RESET_STATE    0x00000004  /**< Default to tx/rx empty */
+#define XQSPIPS_IXR_DISABLE_ALL    0x0000007D  /**< Disable all interrupts */
+/* @} */
+
+
+/** @name Enable Register
+ *
+ * This register is used to enable or disable an QSPI device.
+ * Read/Write
+ * @{
+ */
+#define XQSPIPS_ER_ENABLE_MASK    0x00000001 /**< QSPI Enable Bit Mask */
+/* @} */
+
+
+/** @name Delay Register
+ *
+ * This register is used to program timing delays in
+ * slave mode. Read/Write
+ * @{
+ */
+#define XQSPIPS_DR_NSS_MASK	0xFF000000 /**< Delay to de-assert slave select
+						between two words mask */
+#define XQSPIPS_DR_NSS_SHIFT	24	   /**< Delay to de-assert slave select
+						between two words shift */
+#define XQSPIPS_DR_BTWN_MASK	0x00FF0000 /**< Delay Between Transfers
+						mask */
+#define XQSPIPS_DR_BTWN_SHIFT	16	   /**< Delay Between Transfers shift */
+#define XQSPIPS_DR_AFTER_MASK	0x0000FF00 /**< Delay After Transfers mask */
+#define XQSPIPS_DR_AFTER_SHIFT	8 	   /**< Delay After Transfers shift */
+#define XQSPIPS_DR_INIT_MASK	0x000000FF /**< Delay Initially mask */
+/* @} */
+
+/** @name Slave Idle Count Registers
+ *
+ * This register defines the number of pclk cycles the slave waits for a the
+ * QSPI clock to become stable in quiescent state before it can detect the start
+ * of the next transfer in CPHA = 1 mode.
+ * Read/Write
+ *
+ * @{
+ */
+#define XQSPIPS_SICR_MASK	0x000000FF /**< Slave Idle Count Mask */
+/* @} */
+
+
+/** @name Transmit FIFO Watermark Register
+ *
+ * This register defines the watermark setting for the Transmit FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_TXWR_MASK           0x0000003F /**< Transmit Watermark Mask */
+#define XQSPIPS_TXWR_RESET_VALUE    0x00000001 /**< Transmit Watermark
+						  * register reset value */
+
+/* @} */
+
+/** @name Receive FIFO Watermark Register
+ *
+ * This register defines the watermark setting for the Receive FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_RXWR_MASK	    0x0000003F /**< Receive Watermark Mask */
+#define XQSPIPS_RXWR_RESET_VALUE    0x00000001 /**< Receive Watermark
+						  * register reset value */
+
+/* @} */
+
+/** @name FIFO Depth
+ *
+ * This macro provides the depth of transmit FIFO and receive FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_FIFO_DEPTH	63	/**< FIFO depth (words) */
+/* @} */
+
+
+/** @name Linear QSPI Configuration Register
+ *
+ * This register contains various control bits that
+ * affect the operation of the Linear QSPI controller. Read/Write.
+ *
+ * @{
+ */
+#define XQSPIPS_LQSPI_CR_LINEAR_MASK	 0x80000000 /**< LQSPI mode enable */
+#define XQSPIPS_LQSPI_CR_TWO_MEM_MASK	 0x40000000 /**< Both memories or one */
+#define XQSPIPS_LQSPI_CR_SEP_BUS_MASK	 0x20000000 /**< Seperate memory bus */
+#define XQSPIPS_LQSPI_CR_U_PAGE_MASK	 0x10000000 /**< Upper memory page */
+#define XQSPIPS_LQSPI_CR_MODE_EN_MASK	 0x02000000 /**< Enable mode bits */
+#define XQSPIPS_LQSPI_CR_MODE_ON_MASK	 0x01000000 /**< Mode on */
+#define XQSPIPS_LQSPI_CR_MODE_BITS_MASK  0x00FF0000 /**< Mode value for dual I/O
+							 or quad I/O */
+#define XQSPIPS_LQSPI_CR_DUMMY_MASK	 0x00000700 /**< Number of dummy bytes
+							 between addr and return
+							 read data */
+#define XQSPIPS_LQSPI_CR_INST_MASK	 0x000000FF /**< Read instr code */
+#define XQSPIPS_LQSPI_CR_RST_STATE	 0x8000016B /**< Default CR value */
+/* @} */
+
+/** @name Linear QSPI Status Register
+ *
+ * This register contains various status bits of the Linear QSPI controller.
+ * Read/Write.
+ *
+ * @{
+ */
+#define XQSPIPS_LQSPI_SR_D_FSM_ERR_MASK	  0x00000004 /**< AXI Data FSM Error
+							  received */
+#define XQSPIPS_LQSPI_SR_WR_RECVD_MASK	  0x00000002 /**< AXI write command
+							  received */
+/* @} */
+
+
+/** @name Loopback Delay Adjust Register
+ *
+ * This register contains various bit masks of Loopback Delay Adjust Register.
+ *
+ * @{
+ */
+
+#define XQSPIPS_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020 /**< Loopback Bit */
+
+/* @} */
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XQspiPs_In32 Xil_In32
+#define XQspiPs_Out32 Xil_Out32
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XQspiPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XQspiPs_ReadReg(BaseAddress, RegOffset) \
+	XQspiPs_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XQspiPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u32 RegisterValue)
+*
+******************************************************************************/
+#define XQspiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+	XQspiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Functions implemented in xqspips_hw.c
+ */
+void XQspiPs_ResetHw(u32 BaseAddress);
+void XQspiPs_LinearInit(u32 BaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/xqspips_options.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/xqspips_options.c
new file mode 100644
index 000000000..f3cbe8b48
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/xqspips_options.c
@@ -0,0 +1,434 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_options.c
+*
+* Contains functions for the configuration of the XQspiPs driver component.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00  sdm 11/25/10 First release
+* 2.00a kka 07/25/12 Removed the selection for the following options:
+*		     Master mode (XQSPIPS_MASTER_OPTION) and
+*		     Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
+*		     as the QSPI driver supports the Master mode
+*		     and Flash Interface mode. The driver doesnot support
+*		     Slave mode or the legacy mode.
+* 		     Added the option for setting the Holdb_dr bit in the
+*		     configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
+*		     is the option to be used for setting this bit in the
+*		     configuration register.
+* 2.01a sg  02/03/13 SetDelays and GetDelays API's include DelayNss parameter.
+*
+* 2.02a hk  26/03/13 Removed XQspi_Reset() in Set_Options() function when
+*			 LQSPI_MODE_OPTION is set. Moved Enable() to XQpsiPs_LqspiRead().
+*

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xqspips.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*
+ * Create the table of options which are processed to get/set the device
+ * options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+typedef struct {
+	u32 Option;
+	u32 Mask;
+} OptionsMap;
+
+static OptionsMap OptionsTable[] = {
+	{XQSPIPS_CLK_ACTIVE_LOW_OPTION, XQSPIPS_CR_CPOL_MASK},
+	{XQSPIPS_CLK_PHASE_1_OPTION, XQSPIPS_CR_CPHA_MASK},
+	{XQSPIPS_FORCE_SSELECT_OPTION, XQSPIPS_CR_SSFORCE_MASK},
+	{XQSPIPS_MANUAL_START_OPTION, XQSPIPS_CR_MANSTRTEN_MASK},
+	{XQSPIPS_HOLD_B_DRIVE_OPTION, XQSPIPS_CR_HOLD_B_MASK},
+};
+
+#define XQSPIPS_NUM_OPTIONS	(sizeof(OptionsTable) / sizeof(OptionsMap))
+
+/*****************************************************************************/
+/**
+*
+* This function sets the options for the QSPI device driver. The options control
+* how the device behaves relative to the QSPI bus. The device must be idle
+* rather than busy transferring data before setting these device options.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	Options contains the specified options to be set. This is a bit
+*		mask where a 1 means to turn the option on, and a 0 means to
+*		turn the option off. One or more bit values may be contained in
+*		the mask. See the bit definitions named XQSPIPS_*_OPTIONS in
+*		the file xqspips.h.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_BUSY if the device is currently transferring data.
+*		The transfer must complete or be aborted before setting options.
+*
+* @note
+* This function is not thread-safe.
+*
+******************************************************************************/
+int XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options)
+{
+	u32 ConfigReg;
+	unsigned int Index;
+	u32 QspiOptions;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Do not allow to modify the Control Register while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy) {
+		return XST_DEVICE_BUSY;
+	}
+
+	QspiOptions = Options & XQSPIPS_LQSPI_MODE_OPTION;
+	Options &= ~XQSPIPS_LQSPI_MODE_OPTION;
+
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPS_CR_OFFSET);
+
+	/*
+	 * Loop through the options table, turning the option on or off
+	 * depending on whether the bit is set in the incoming options flag.
+	 */
+	for (Index = 0; Index < XQSPIPS_NUM_OPTIONS; Index++) {
+		if (Options & OptionsTable[Index].Option) {
+			/* Turn it on */
+			ConfigReg |= OptionsTable[Index].Mask;
+		} else {
+			/* Turn it off */
+			ConfigReg &= ~(OptionsTable[Index].Mask);
+		}
+	}
+
+	/*
+	 * Now write the control register. Leave it to the upper layers
+	 * to restart the device.
+	 */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET,
+			 ConfigReg);
+
+	/*
+	 * Check for the LQSPI configuration options.
+	 */
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPS_LQSPI_CR_OFFSET);
+
+
+	if (QspiOptions & XQSPIPS_LQSPI_MODE_OPTION) {
+		XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XQSPIPS_LQSPI_CR_OFFSET,
+				  XQSPIPS_LQSPI_CR_RST_STATE);
+		XQspiPs_SetSlaveSelect(InstancePtr);
+	} else {
+		ConfigReg &= ~XQSPIPS_LQSPI_CR_LINEAR_MASK;
+		XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XQSPIPS_LQSPI_CR_OFFSET, ConfigReg);
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the options for the QSPI device. The options control how
+* the device behaves relative to the QSPI bus.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return
+*
+* Options contains the specified options currently set. This is a bit value
+* where a 1 means the option is on, and a 0 means the option is off.
+* See the bit definitions named XQSPIPS_*_OPTIONS in file xqspips.h.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XQspiPs_GetOptions(XQspiPs *InstancePtr)
+{
+	u32 OptionsFlag = 0;
+	u32 ConfigReg;
+	unsigned int Index;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Get the current options from QSPI configuration register.
+	 */
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPS_CR_OFFSET);
+
+	/*
+	 * Loop through the options table to grab options
+	 */
+	for (Index = 0; Index < XQSPIPS_NUM_OPTIONS; Index++) {
+		if (ConfigReg & OptionsTable[Index].Mask) {
+			OptionsFlag |= OptionsTable[Index].Option;
+		}
+	}
+
+	/*
+	 * Check for the LQSPI configuration options.
+	 */
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPS_LQSPI_CR_OFFSET);
+
+	if ((ConfigReg & XQSPIPS_LQSPI_CR_LINEAR_MASK) != 0) {
+		OptionsFlag |= XQSPIPS_LQSPI_MODE_OPTION;
+	}
+
+	return OptionsFlag;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the clock prescaler for an QSPI device. The device
+* must be idle rather than busy transferring data before setting these device
+* options.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	Prescaler is the value that determine how much the clock should
+*		be divided by. Use the XQSPIPS_CLK_PRESCALE_* constants defined
+*		in xqspips.h for this setting.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_BUSY if the device is currently transferring data.
+*		The transfer must complete or be aborted before setting options.
+*
+* @note
+* This function is not thread-safe.
+*
+******************************************************************************/
+int XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler)
+{
+	u32 ConfigReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Prescaler <= XQSPIPS_CR_PRESC_MAXIMUM);
+
+	/*
+	 * Do not allow the slave select to change while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy) {
+		return XST_DEVICE_BUSY;
+	}
+
+	/*
+	 * Read the configuration register, mask out the interesting bits, and set
+	 * them with the shifted value passed into the function. Write the
+	 * results back to the configuration register.
+	 */
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPS_CR_OFFSET);
+
+	ConfigReg &= ~XQSPIPS_CR_PRESC_MASK;
+	ConfigReg |= (u32) (Prescaler & XQSPIPS_CR_PRESC_MAXIMUM) <<
+			    XQSPIPS_CR_PRESC_SHIFT;
+
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XQSPIPS_CR_OFFSET,
+			  ConfigReg);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the clock prescaler of an QSPI device.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	The prescaler value.
+*
+* @note		None.
+*
+*
+******************************************************************************/
+u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr)
+{
+	u32 ConfigReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPS_CR_OFFSET);
+
+	ConfigReg &= XQSPIPS_CR_PRESC_MASK;
+
+	return (u8)(ConfigReg >> XQSPIPS_CR_PRESC_SHIFT);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the delay register for the QSPI device driver.
+* The delay register controls the Delay Between Transfers, Delay After
+* Transfers, and the Delay Initially. The default value is 0x0. The range of
+* each delay value is 0-255.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	DelayNss is the delay to de-assert slave select between
+*		two word transfers.
+* @param	DelayBtwn is the delay between one Slave Select being
+*		de-activated and the activation of another slave. The delay is
+*		the number of master clock periods given by DelayBtwn + 2.
+* @param	DelayAfter define the delay between the last bit of the current
+*		byte transfer and the first bit of the next byte transfer.
+*		The delay in number of master clock periods is given as:
+*		CHPA=0:DelayInit+DelayAfter+3
+*		CHPA=1:DelayAfter+1
+* @param	DelayInit is the delay between asserting the slave select signal
+*		and the first bit transfer. The delay int number of master clock
+*		periods is DelayInit+1.
+*
+* @return
+*		- XST_SUCCESS if delays are successfully set.
+*		- XST_DEVICE_BUSY if the device is currently transferring data.
+*		The transfer must complete or be aborted before setting options.
+*
+* @note		None.
+*
+******************************************************************************/
+int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
+			 u8 DelayAfter, u8 DelayInit)
+{
+	u32 DelayRegister;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Do not allow the delays to change while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy) {
+		return XST_DEVICE_BUSY;
+	}
+
+	/* Shift, Mask and OR the values to build the register settings */
+	DelayRegister = (u32) DelayNss << XQSPIPS_DR_NSS_SHIFT;
+	DelayRegister |= (u32) DelayBtwn << XQSPIPS_DR_BTWN_SHIFT;
+	DelayRegister |= (u32) DelayAfter << XQSPIPS_DR_AFTER_SHIFT;
+	DelayRegister |= (u32) DelayInit;
+
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XQSPIPS_DR_OFFSET, DelayRegister);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the delay settings for an QSPI device.
+* The delay register controls the Delay Between Transfers, Delay After
+* Transfers, and the Delay Initially. The default value is 0x0.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	DelayNss is a pointer to the Delay to de-assert slave select
+*		between two word transfers.
+* @param	DelayBtwn is a pointer to the Delay Between transfers value.
+*		This is a return parameter.
+* @param	DelayAfter is a pointer to the Delay After transfer value.
+*		This is a return parameter.
+* @param	DelayInit is a pointer to the Delay Initially value. This is
+*		a return parameter.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
+			 u8 *DelayAfter, u8 *DelayInit)
+{
+	u32 DelayRegister;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	DelayRegister = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+					 XQSPIPS_DR_OFFSET);
+
+	*DelayInit = (u8)(DelayRegister & XQSPIPS_DR_INIT_MASK);
+
+	*DelayAfter = (u8)((DelayRegister & XQSPIPS_DR_AFTER_MASK) >>
+			   XQSPIPS_DR_AFTER_SHIFT);
+
+	*DelayBtwn = (u8)((DelayRegister & XQSPIPS_DR_BTWN_MASK) >>
+			  XQSPIPS_DR_BTWN_SHIFT);
+
+	*DelayNss = (u8)((DelayRegister & XQSPIPS_DR_NSS_MASK) >>
+			  XQSPIPS_DR_NSS_SHIFT);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/xqspips_selftest.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/xqspips_selftest.c
new file mode 100644
index 000000000..9ad32eaa2
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/xqspips_selftest.c
@@ -0,0 +1,159 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_selftest.c
+*
+* This file contains the implementation of selftest function for the QSPI
+* device.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00  sdm 11/25/10 First release
+* 2.01a sg  02/03/13 Delay Register test is added with DelayNss parameter.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xqspips.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Runs a self-test on the driver/device. The self-test is destructive in that
+* a reset of the device is performed in order to check the reset values of
+* the registers and to get the device into a known state.
+*
+* Upon successful return from the self-test, the device is reset.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return
+* 		- XST_SUCCESS if successful
+*		- XST_REGISTER_ERROR indicates a register did not read or write
+*		correctly.
+*
+* @note		None.
+*
+******************************************************************************/
+int XQspiPs_SelfTest(XQspiPs *InstancePtr)
+{
+	int Status;
+	u32 Register;
+	u8 DelayTestNss;
+	u8 DelayTestBtwn;
+	u8 DelayTestAfter;
+	u8 DelayTestInit;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Reset the QSPI device to leave it in a known good state
+	 */
+	XQspiPs_Reset(InstancePtr);
+
+	/*
+	 * All the QSPI registers should be in their default state right now.
+	 */
+	Register = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XQSPIPS_CR_OFFSET);
+	if (Register != XQSPIPS_CR_RESET_STATE) {
+		return XST_REGISTER_ERROR;
+	}
+
+	Register = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XQSPIPS_SR_OFFSET);
+	if (Register != XQSPIPS_ISR_RESET_STATE) {
+		return XST_REGISTER_ERROR;
+	}
+
+	DelayTestNss = 0x5A;
+	DelayTestBtwn = 0xA5;
+	DelayTestAfter = 0xAA;
+	DelayTestInit = 0x55;
+
+	/*
+	 * Write and read the delay register, just to be sure there is some
+	 * hardware out there.
+	 */
+	Status = XQspiPs_SetDelays(InstancePtr, DelayTestNss, DelayTestBtwn,
+				DelayTestAfter, DelayTestInit);
+	if (Status != XST_SUCCESS) {
+		return Status;
+	}
+
+	XQspiPs_GetDelays(InstancePtr, &DelayTestNss, &DelayTestBtwn,
+				&DelayTestAfter, &DelayTestInit);
+	if ((0x5A != DelayTestNss) || (0xA5 != DelayTestBtwn) ||
+		(0xAA != DelayTestAfter) || (0x55 != DelayTestInit)) {
+		return XST_REGISTER_ERROR;
+	}
+
+	Status = XQspiPs_SetDelays(InstancePtr, 0, 0, 0, 0);
+	if (Status != XST_SUCCESS) {
+		return Status;
+	}
+
+	/*
+	 * Reset the QSPI device to leave it in a known good state
+	 */
+	XQspiPs_Reset(InstancePtr);
+
+	return XST_SUCCESS;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/xqspips_sinit.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/xqspips_sinit.c
new file mode 100644
index 000000000..27ba3750b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_0/src/xqspips_sinit.c
@@ -0,0 +1,106 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_sinit.c
+*
+* The implementation of the XQspiPs component's static initialization
+* functionality.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00  sdm 11/25/10 First release
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xqspips.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+extern XQspiPs_Config XQspiPs_ConfigTable[];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the ID of the device to look up the
+*		configuration for.
+*
+* @return
+*
+* A pointer to the configuration found or NULL if the specified device ID was
+* not found. See xqspips.h for the definition of XQspiPs_Config.
+*
+* @note		None.
+*
+******************************************************************************/
+XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId)
+{
+	XQspiPs_Config *CfgPtr = NULL;
+	int Index;
+
+	for (Index = 0; Index < XPAR_XQSPIPS_NUM_INSTANCES; Index++) {
+		if (XQspiPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XQspiPs_ConfigTable[Index];
+			break;
+		}
+	}
+	return CfgPtr;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/Makefile
new file mode 100644
index 000000000..f32ad9b52
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/Makefile
@@ -0,0 +1,41 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner scugic_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling scugic"
+
+scugic_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: scugic_includes
+
+scugic_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/xscugic.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/xscugic.c
new file mode 100644
index 000000000..c9fd7e9c0
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/xscugic.c
@@ -0,0 +1,719 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic.c
+*
+* Contains required functions for the XScuGic driver for the Interrupt
+* Controller. See xscugic.h for a detailed description of the driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- --------------------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 1.01a sdm  11/09/11 Changes are made in function XScuGic_CfgInitialize. Since
+*		      "Config" entry is now made as pointer in the XScuGic
+*		      structure, necessary changes are made.
+*		      The HandlerTable can now be populated through the low
+*		      level routine XScuGic_RegisterHandler added in this
+*		      release. Hence necessary checks are added not to
+*		      overwrite the HandlerTable entriesin function
+*		      XScuGic_CfgInitialize.
+* 1.03a srt  02/27/13 Added APIs
+*			- XScuGic_SetPriTrigTypeByDistAddr()
+*			- XScuGic_GetPriTrigTypeByDistAddr()
+* 		      Removed Offset calculation macros, defined in _hw.h
+*		      (CR 702687)
+*			  Added support to direct interrupts to the appropriate CPU. Earlier
+*			  interrupts were directed to CPU1 (hard coded). Now depending
+*			  upon the CPU selected by the user (xparameters.h), interrupts
+*			  will be directed to the relevant CPU. This fixes CR 699688.
+*
+* 1.04a hk   05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
+*			  XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
+*			  Moved functions XScuGic_SetPriTrigTypeByDistAddr and
+*             XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
+*			  This is fix for CR#705621.
+* 1.06a asa  16/11/13 Fix for CR#749178. Assignment for EffectiveAddr
+*			  in function XScuGic_CfgInitialize is removed as it was
+*		      a bug.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xparameters.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+static void StubHandler(void *CallBackRef);
+
+/*****************************************************************************/
+/**
+*
+* DistInit initializes the distributor of the GIC. The
+* initialization entails:
+*
+* - Write the trigger mode, priority and target CPU
+* - All interrupt sources are disabled
+* - Enable the distributor
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	CpuID is the Cpu ID to be initialized.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void DistInit(XScuGic *InstancePtr, u32 CpuID)
+{
+	u32 Int_Id;
+
+#if USE_AMP==1
+	#warning "Building GIC for AMP"
+
+	/*
+	 * The distrubutor should not be initialized by FreeRTOS in the case of
+	 * AMP -- it is assumed that Linux is the master of this device in that
+	 * case.
+	 */
+	return;
+#endif
+
+	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, 0UL);
+
+	/*
+	 * Set the security domains in the int_security registers for
+	 * non-secure interrupts
+	 * All are secure, so leave at the default. Set to 1 for non-secure
+	 * interrupts.
+	 */
+
+	/*
+	 * For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
+	 */
+
+	/*
+	 * 1. The trigger mode in the int_config register
+	 * Only write to the SPI interrupts, so start at 32
+	 */
+	for (Int_Id = 32; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id+=16) {
+		/*
+		 * Each INT_ID uses two bits, or 16 INT_ID per register
+		 * Set them all to be level sensitive, active HIGH.
+		 */
+		XScuGic_DistWriteReg(InstancePtr,
+					XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
+					0UL);
+	}
+
+
+#define DEFAULT_PRIORITY    0xa0a0a0a0UL
+	for (Int_Id = 0; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id+=4) {
+		/*
+		 * 2. The priority using int the priority_level register
+		 * The priority_level and spi_target registers use one byte per
+		 * INT_ID.
+		 * Write a default value that can be changed elsewhere.
+		 */
+		XScuGic_DistWriteReg(InstancePtr,
+					XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+					DEFAULT_PRIORITY);
+	}
+
+	for (Int_Id = 32; Int_IdBaseAddress for this parameters, passing the physical
+*		address instead.
+*
+* @return
+*		- XST_SUCCESS if initialization was successful
+*
+* @note		None.
+*
+******************************************************************************/
+int  XScuGic_CfgInitialize(XScuGic *InstancePtr,
+				XScuGic_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+	u32 Int_Id;
+	u8 Cpu_Id = XPAR_CPU_ID + 1;
+	(void) EffectiveAddr;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	if(InstancePtr->IsReady != XIL_COMPONENT_IS_READY) {
+	
+		InstancePtr->IsReady = 0;
+		InstancePtr->Config = ConfigPtr;
+
+
+		for (Int_Id = 0; Int_IdConfig->HandlerTable[Int_Id].Handler == 0)) {
+				InstancePtr->Config->HandlerTable[Int_Id].Handler =
+									StubHandler;
+			}
+			InstancePtr->Config->HandlerTable[Int_Id].CallBackRef =
+								InstancePtr;
+		}	
+
+		DistInit(InstancePtr, Cpu_Id);
+		CPUInit(InstancePtr);
+
+		InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Makes the connection between the Int_Id of the interrupt source and the
+* associated handler that is to run when the interrupt is recognized. The
+* argument provided in this call as the Callbackref is used as the argument
+* for the handler when it is called.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	Int_Id contains the ID of the interrupt source and should be
+*		in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+* @param	Handler to the handler for that interrupt.
+* @param	CallBackRef is the callback reference, usually the instance
+*		pointer of the connecting driver.
+*
+* @return
+*
+*		- XST_SUCCESS if the handler was connected correctly.
+*
+* @note
+*
+* WARNING: The handler provided as an argument will overwrite any handler
+* that was previously connected.
+*
+****************************************************************************/
+int  XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
+                      Xil_InterruptHandler Handler, void *CallBackRef)
+{
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertNonvoid(Handler != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The Int_Id is used as an index into the table to select the proper
+	 * handler
+	 */
+	InstancePtr->Config->HandlerTable[Int_Id].Handler = Handler;
+	InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = CallBackRef;
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Updates the interrupt table with the Null Handler and NULL arguments at the
+* location pointed at by the Int_Id. This effectively disconnects that interrupt
+* source from any handler. The interrupt is disabled also.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance to be worked on.
+* @param	Int_Id contains the ID of the interrupt source and should
+*		be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id)
+{
+	u32 Mask;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The Int_Id is used to create the appropriate mask for the
+	 * desired bit position. Int_Id currently limited to 0 - 31
+	 */
+	Mask = 0x00000001 << (Int_Id % 32);
+
+	/*
+	 * Disable the interrupt such that it won't occur while disconnecting
+	 * the handler, only disable the specified interrupt id without modifying
+	 * the other interrupt ids
+	 */
+	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DISABLE_OFFSET +
+						((Int_Id / 32) * 4), Mask);
+
+	/*
+	 * Disconnect the handler and connect a stub, the callback reference
+	 * must be set to this instance to allow unhandled interrupts to be
+	 * tracked
+	 */
+	InstancePtr->Config->HandlerTable[Int_Id].Handler = StubHandler;
+	InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = InstancePtr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Enables the interrupt source provided as the argument Int_Id. Any pending
+* interrupt condition for the specified Int_Id will occur after this function is
+* called.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	Int_Id contains the ID of the interrupt source and should be
+*		in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id)
+{
+	u32 Mask;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The Int_Id is used to create the appropriate mask for the
+	 * desired bit position. Int_Id currently limited to 0 - 31
+	 */
+	Mask = 0x00000001 << (Int_Id % 32);
+
+	/*
+	 * Enable the selected interrupt source by setting the
+	 * corresponding bit in the Enable Set register.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_ENABLE_SET_OFFSET +
+						((Int_Id / 32) * 4), Mask);
+}
+
+/*****************************************************************************/
+/**
+*
+* Disables the interrupt source provided as the argument Int_Id such that the
+* interrupt controller will not cause interrupts for the specified Int_Id. The
+* interrupt controller will continue to hold an interrupt condition for the
+* Int_Id, but will not cause an interrupt.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	Int_Id contains the ID of the interrupt source and should be
+*		in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id)
+{
+	u32 Mask;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The Int_Id is used to create the appropriate mask for the
+	 * desired bit position. Int_Id currently limited to 0 - 31
+	 */
+	Mask = 0x00000001 << (Int_Id % 32);
+
+	/*
+	 * Disable the selected interrupt source by setting the
+	 * corresponding bit in the IDR.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DISABLE_OFFSET +
+						((Int_Id / 32) * 4), Mask);
+}
+
+/*****************************************************************************/
+/**
+*
+* Allows software to simulate an interrupt in the interrupt controller.  This
+* function will only be successful when the interrupt controller has been
+* started in simulation mode.  A simulated interrupt allows the interrupt
+* controller to be tested without any device to drive an interrupt input
+* signal into it.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	Int_Id is the software interrupt ID to simulate an interrupt.
+* @param	Cpu_Id is the list of CPUs to send the interrupt.
+*
+* @return
+*
+* XST_SUCCESS if successful, or XST_FAILURE if the interrupt could not be
+* simulated
+*
+* @note		None.
+*
+******************************************************************************/
+int  XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id)
+{
+	u32 Mask;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Int_Id <= 15) ;
+	Xil_AssertNonvoid(Cpu_Id <= 255) ;
+
+
+	/*
+	 * The Int_Id is used to create the appropriate mask for the
+	 * desired interrupt. Int_Id currently limited to 0 - 15
+	 * Use the target list for the Cpu ID.
+	 */
+	Mask = ((Cpu_Id << 16) | Int_Id) &
+		(XSCUGIC_SFI_TRIG_CPU_MASK | XSCUGIC_SFI_TRIG_INTID_MASK);
+
+	/*
+	 * Write to the Software interrupt trigger register. Use the appropriate
+	 * CPU Int_Id.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_SFI_TRIG_OFFSET, Mask);
+
+	/* Indicate the interrupt was successfully simulated */
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* A stub for the asynchronous callback. The stub is here in case the upper
+* layers forget to set the handler.
+*
+* @param	CallBackRef is a pointer to the upper layer callback reference
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void StubHandler(void *CallBackRef) {
+	/*
+	 * verify that the inputs are valid
+	 */
+	Xil_AssertVoid(CallBackRef != NULL);
+
+	/*
+	 * Indicate another unhandled interrupt for stats
+	 */
+	((XScuGic *)CallBackRef)->UnhandledInterrupts++;
+}
+
+/****************************************************************************/
+/**
+* Sets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Int_Id is the IRQ source number to modify
+* @param	Priority is the new priority for the IRQ source. 0 is highest
+* 			priority, 0xF8 (248) is lowest. There are 32 priority levels
+*			supported with a step of 8. Hence the supported priorities are
+*			0, 8, 16, 32, 40 ..., 248.
+* @param	Trigger is the new trigger type for the IRQ source.
+* Each bit pair describes the configuration for an INT_ID.
+* SFI    Read Only    b10 always
+* PPI    Read Only    depending on how the PPIs are configured.
+*                    b01    Active HIGH level sensitive
+*                    b11 Rising edge sensitive
+* SPI                LSB is read only.
+*                    b01    Active HIGH level sensitive
+*                    b11 Rising edge sensitive/
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+					u8 Priority, u8 Trigger)
+{
+	u32 RegValue;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(Trigger <= XSCUGIC_INT_CFG_MASK);
+	Xil_AssertVoid(Priority <= XSCUGIC_MAX_INTR_PRIO_VAL);
+
+	/*
+	 * Determine the register to write to using the Int_Id.
+	 */
+	RegValue = XScuGic_DistReadReg(InstancePtr,
+			XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+	/*
+	 * The priority bits are Bits 7 to 3 in GIC Priority Register. This
+	 * means the number of priority levels supported are 32 and they are
+	 * in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc.
+	 * The lower order 3 bits are masked before putting it in the register.
+	 */
+	Priority = Priority & XSCUGIC_INTR_PRIO_MASK;
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id%4)*8));
+	RegValue |= Priority << ((Int_Id%4)*8);
+
+	/*
+	 * Write the value back to the register.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+				RegValue);
+
+	/*
+	 * Determine the register to write to using the Int_Id.
+	 */
+	RegValue = XScuGic_DistReadReg(InstancePtr,
+			XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id%16)*2));
+	RegValue |= Trigger << ((Int_Id%16)*2);
+
+	/*
+	 * Write the value back to the register.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
+				RegValue);
+
+}
+
+/****************************************************************************/
+/**
+* Gets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Int_Id is the IRQ source number to modify
+* @param	Priority is a pointer to the value of the priority of the IRQ
+*		source. This is a return value.
+* @param	Trigger is pointer to the value of the trigger of the IRQ
+*		source. This is a return value.
+*
+* @return	None.
+*
+* @note		None
+*
+*****************************************************************************/
+void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+					u8 *Priority, u8 *Trigger)
+{
+	u32 RegValue;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(Priority != NULL);
+	Xil_AssertVoid(Trigger != NULL);
+
+	/*
+	 * Determine the register to read to using the Int_Id.
+	 */
+	RegValue = XScuGic_DistReadReg(InstancePtr,
+	    XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue = RegValue >> ((Int_Id%4)*8);
+	*Priority = RegValue & XSCUGIC_PRIORITY_MASK;
+
+	/*
+	 * Determine the register to read to using the Int_Id.
+	 */
+	RegValue = XScuGic_DistReadReg(InstancePtr,
+	XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue = RegValue >> ((Int_Id%16)*2);
+
+	*Trigger = RegValue & XSCUGIC_INT_CFG_MASK;
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/xscugic.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/xscugic.h
new file mode 100644
index 000000000..9a43efbb3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/xscugic.h
@@ -0,0 +1,324 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic.h
+*
+* The generic interrupt controller driver component.
+*
+* The interrupt controller driver uses the idea of priority for the various
+* handlers. Priority is an integer within the range of 1 and 31 inclusive with
+* default of 1 being the highest priority interrupt source. The priorities
+* of the various sources can be dynamically altered as needed through
+* hardware configuration.
+*
+* The generic interrupt controller supports the following
+* features:
+*
+*   - specific individual interrupt enabling/disabling
+*   - specific individual interrupt acknowledging
+*   - attaching specific callback function to handle interrupt source
+*   - assigning desired priority to interrupt source if default is not
+*     acceptable.
+*
+* Details about connecting the interrupt handler of the driver are contained
+* in the source file specific to interrupt processing, xscugic_intr.c.
+*
+* This driver is intended to be RTOS and processor independent.  It works with
+* physical addresses only.  Any needs for dynamic memory management, threads
+* or thread mutual exclusion, virtual memory, or cache control must be
+* satisfied by the layer above this driver.
+*
+* Interrupt Vector Tables
+*
+* The device ID of the interrupt controller device is used by the driver as a
+* direct index into the configuration data table. The user should populate the
+* vector table with handlers and callbacks at run-time using the
+* XScuGic_Connect() and XScuGic_Disconnect() functions.
+*
+* Each vector table entry corresponds to a device that can generate an
+* interrupt. Each entry contains an interrupt handler function and an
+* argument to be passed to the handler when an interrupt occurs.  The
+* user must use XScuGic_Connect() when the interrupt handler takes an
+* argument other than the base address.
+*
+* Nested Interrupts Processing
+*
+* Nested interrupts are not supported by this driver.
+*
+* NOTE:
+* The generic interrupt controller is not a part of the snoop control unit
+* as indicated by the prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00a drg  01/19/00 First release
+* 1.01a sdm  11/09/11 The XScuGic and XScuGic_Config structures have changed.
+*		      The HandlerTable (of type XScuGic_VectorTableEntry) is
+*		      moved to XScuGic_Config structure from XScuGic structure.
+*
+*		      The "Config" entry in XScuGic structure is made as
+*		      pointer for better efficiency.
+*
+*		      A new file named as xscugic_hw.c is now added. It is
+*		      to implement low level driver routines without using
+*		      any xscugic instance pointer. They are useful when the
+*		      user wants to use xscugic through device id or
+*		      base address. The driver routines provided are explained
+*		      below.
+*		      XScuGic_DeviceInitialize that takes device id as
+*		      argument and initializes the device (without calling
+*		      XScuGic_CfgInitialize).
+*		      XScuGic_DeviceInterruptHandler that takes device id
+*		      as argument and calls appropriate handlers from the
+*		      HandlerTable.
+*		      XScuGic_RegisterHandler that registers a new handler
+*		      by taking xscugic hardware base address as argument.
+*		      LookupConfigByBaseAddress is used to return the
+*		      corresponding config structure from XScuGic_ConfigTable
+*		      based on the scugic base address passed.
+* 1.02a sdm  12/20/11 Removed AckBeforeService from the XScuGic_Config
+*		      structure.
+* 1.03a srt  02/27/13 Moved Offset calculation macros from *.c and *_hw.c to
+*		      *_hw.h
+*		      Added APIs
+*			- XScuGic_SetPriTrigTypeByDistAddr()
+*			- XScuGic_GetPriTrigTypeByDistAddr()
+*		      (CR 702687)
+*			Added support to direct interrupts to the appropriate CPU. Earlier
+*			  interrupts were directed to CPU1 (hard coded). Now depending
+*			  upon the CPU selected by the user (xparameters.h), interrupts
+*			  will be directed to the relevant CPU. This fixes CR 699688.
+* 1.04a hk   05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
+*			  XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
+*			  Moved functions XScuGic_SetPriTrigTypeByDistAddr and
+*             XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
+*			  This is fix for CR#705621.
+* 1.05a hk   06/26/13 Modified tcl to export external interrupts correctly to
+*                     xparameters.h. Fix for CR's 690505, 708928 & 719359.
+* 2.0   adk  12/10/13 Updated as per the New Tcl API's
+* 2.1   adk  25/04/14 Fixed the CR:789373 changes are made in the driver tcl file.
+*
+* 

+*
+******************************************************************************/
+
+#ifndef XSCUGIC_H /* prevent circular inclusions */
+#define XSCUGIC_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xil_io.h"
+#include "xscugic_hw.h"
+#include "xil_exception.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/* The following data type defines each entry in an interrupt vector table.
+ * The callback reference is the base address of the interrupting device
+ * for the low level driver and an instance pointer for the high level driver.
+ */
+typedef struct
+{
+	Xil_InterruptHandler Handler;
+	void *CallBackRef;
+} XScuGic_VectorTableEntry;
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct
+{
+	u16 DeviceId;		/**< Unique ID  of device */
+	u32 CpuBaseAddress;	/**< CPU Interface Register base address */
+	u32 DistBaseAddress;	/**< Distributor Register base address */
+	XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**<
+				 Vector table of interrupt handlers */
+} XScuGic_Config;
+
+/**
+ * The XScuGic driver instance data. The user is required to allocate a
+ * variable of this type for every intc device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct
+{
+	XScuGic_Config *Config;  /**< Configuration table entry */
+	u32 IsReady;		 /**< Device is initialized and ready */
+	u32 UnhandledInterrupts; /**< Intc Statistics */
+} XScuGic;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Write the given CPU Interface register
+*
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    RegOffset is the register offset to be written
+* @param    Data is the 32-bit value to write to the register
+*
+* @return   None.
+*
+* @note
+* C-style signature:
+*    void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \
+(XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \
+					((u32)Data)))
+
+/****************************************************************************/
+/**
+*
+* Read the given CPU Interface register
+*
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    RegOffset is the register offset to be read
+*
+* @return   The 32-bit value of the register
+*
+* @note
+* C-style signature:
+*    u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \
+	(XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Distributor Interface register
+*
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    RegOffset is the register offset to be written
+* @param    Data is the 32-bit value to write to the register
+*
+* @return   None.
+*
+* @note
+* C-style signature:
+*    void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \
+(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \
+					((u32)Data)))
+
+/****************************************************************************/
+/**
+*
+* Read the given Distributor Interface register
+*
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    RegOffset is the register offset to be read
+*
+* @return   The 32-bit value of the register
+*
+* @note
+* C-style signature:
+*    u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_DistReadReg(InstancePtr, RegOffset) \
+(XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset)))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Required functions in xscugic.c
+ */
+
+int  XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
+			Xil_InterruptHandler Handler, void *CallBackRef);
+void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id);
+
+void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id);
+void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id);
+
+int  XScuGic_CfgInitialize(XScuGic *InstancePtr, XScuGic_Config *ConfigPtr,
+							u32 EffectiveAddr);
+
+int  XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id);
+
+void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+					u8 *Priority, u8 *Trigger);
+void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+					u8 Priority, u8 Trigger);
+
+/*
+ * Initialization functions in xscugic_sinit.c
+ */
+XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId);
+
+/*
+ * Interrupt functions in xscugic_intr.c
+ */
+void XScuGic_InterruptHandler(XScuGic *InstancePtr);
+
+/*
+ * Self-test functions in xscugic_selftest.c
+ */
+int  XScuGic_SelfTest(XScuGic *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif            /* end of protection macro */
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/xscugic_g.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/xscugic_g.c
new file mode 100644
index 000000000..55a837264
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/xscugic_g.c
@@ -0,0 +1,32 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSM.
+* Version: 
+* DO NOT EDIT.
+*
+*  v (64-bit)
+SW Build (by ) on 
+Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xscugic.h"
+
+/*
+* The configuration table for devices
+*/
+
+XScuGic_Config XScuGic_ConfigTable[] =
+{
+	{
+		XPAR_PS7_SCUGIC_0_DEVICE_ID,
+		XPAR_PS7_SCUGIC_0_BASEADDR,
+		XPAR_PS7_SCUGIC_0_DIST_BASEADDR
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/xscugic_hw.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/xscugic_hw.c
new file mode 100644
index 000000000..0634a6f08
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/xscugic_hw.c
@@ -0,0 +1,567 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_hw.c
+*
+* This file contains low-level driver functions that can be used to access the
+* device.  The user should refer to the hardware device specification for more
+* details of the device operation.
+* These routines are used when the user does not want to create an instance of
+* XScuGic structure but still wants to use the ScuGic device. Hence the
+* routines provided here take device id or scugic base address as arguments.
+* Separate static versions of DistInit and CPUInit are provided to implement
+* the low level driver routines.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.01a sdm  07/18/11 First release
+* 1.03a srt  02/27/13 Moved Offset calculation macros from *_hw.c (CR
+*		      702687).
+*					  Added support to direct interrupts to the appropriate CPU.
+*			  Earlier interrupts were directed to CPU1 (hard coded). Now
+*			  depending upon the CPU selected by the user (xparameters.h),
+*			  interrupts will be directed to the relevant CPU.
+*			  This fixes CR 699688.
+* 1.04a hk   05/04/13 Fix for CR#705621. Moved functions
+*			  XScuGic_SetPriTrigTypeByDistAddr and
+*             XScuGic_GetPriTrigTypeByDistAddr here from xscugic.c
+*
+* 

+*
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+static void DistInit(XScuGic_Config *Config, u32 CpuID);
+static void CPUInit(XScuGic_Config *Config);
+static XScuGic_Config *LookupConfigByBaseAddress(u32 BaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+extern XScuGic_Config XScuGic_ConfigTable[];
+
+/*****************************************************************************/
+/**
+*
+* DistInit initializes the distributor of the GIC. The
+* initialization entails:
+*
+* - Write the trigger mode, priority and target CPU
+* - All interrupt sources are disabled
+* - Enable the distributor
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	CpuID is the Cpu ID to be initialized.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void DistInit(XScuGic_Config *Config, u32 CpuID)
+{
+	u32 Int_Id;
+
+#if USE_AMP==1
+	#warning "Building GIC for AMP"
+
+	/*
+	 * The distrubutor should not be initialized by FreeRTOS in the case of
+	 * AMP -- it is assumed that Linux is the master of this device in that
+	 * case.
+	 */
+	return;
+#endif
+
+	XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET, 0UL);
+
+	/*
+	 * Set the security domains in the int_security registers for non-secure
+	 * interrupts. All are secure, so leave at the default. Set to 1 for
+	 * non-secure interrupts.
+	 */
+
+
+	/*
+	 * For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
+	 */
+
+	/*
+	 * 1. The trigger mode in the int_config register
+	 * Only write to the SPI interrupts, so start at 32
+	 */
+	for (Int_Id = 32; Int_IdDistBaseAddress,
+			XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id), 0UL);
+	}
+
+
+#define DEFAULT_PRIORITY	0xa0a0a0a0UL
+	for (Int_Id = 0; Int_IdDistBaseAddress,
+				XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+				DEFAULT_PRIORITY);
+	}
+
+	for (Int_Id = 32; Int_IdDistBaseAddress,
+ 				XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), CpuID);
+	}
+
+	for (Int_Id = 0; Int_IdDistBaseAddress,
+		XSCUGIC_ENABLE_DISABLE_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET,
+		Int_Id),
+		0xFFFFFFFFUL);
+
+	}
+
+	XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET,
+						XSCUGIC_EN_INT_MASK);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* CPUInit initializes the CPU Interface of the GIC. The initialization entails:
+*
+* - Set the priority of the CPU.
+* - Enable the CPU interface
+*
+* @param	ConfigPtr is a pointer to a config table for the particular
+*		device this driver is associated with.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void CPUInit(XScuGic_Config *Config)
+{
+	/*
+	 * Program the priority mask of the CPU using the Priority mask
+	 * register
+	 */
+	XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CPU_PRIOR_OFFSET,
+									0xF0);
+
+	/*
+	 * If the CPU operates in both security domains, set parameters in the
+	 * control_s register.
+	 * 1. Set FIQen=1 to use FIQ for secure interrupts,
+	 * 2. Program the AckCtl bit
+	 * 3. Program the SBPR bit to select the binary pointer behavior
+	 * 4. Set EnableS = 1 to enable secure interrupts
+	 * 5. Set EnbleNS = 1 to enable non secure interrupts
+	 */
+
+	/*
+	 * If the CPU operates only in the secure domain, setup the
+	 * control_s register.
+	 * 1. Set FIQen=1,
+	 * 2. Set EnableS=1, to enable the CPU interface to signal secure .
+	 * interrupts Only enable the IRQ output unless secure interrupts
+	 * are needed.
+	 */
+	XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CONTROL_OFFSET, 0x07);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* CfgInitialize a specific interrupt controller instance/driver. The
+* initialization entails:
+*
+* - Initialize fields of the XScuGic structure
+* - Initial vector table with stub function calls
+* - All interrupt sources are disabled
+*
+* @param InstancePtr is a pointer to the XScuGic instance to be worked on.
+* @param ConfigPtr is a pointer to a config table for the particular device
+*        this driver is associated with.
+* @param EffectiveAddr is the device base address in the virtual memory address
+*        space. The caller is responsible for keeping the address mapping
+*        from EffectiveAddr to the device physical base address unchanged
+*        once this function is invoked. Unexpected errors may occur if the
+*        address mapping changes after this function is called. If address
+*        translation is not used, use Config->BaseAddress for this parameters,
+*        passing the physical address instead.
+*
+* @return
+*
+* - XST_SUCCESS if initialization was successful
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+int XScuGic_DeviceInitialize(u32 DeviceId)
+{
+	XScuGic_Config *Config;
+	u8 Cpu_Id = XPAR_CPU_ID + 1;
+
+	Config = &XScuGic_ConfigTable[(u32 )DeviceId];
+
+	DistInit(Config, Cpu_Id);
+
+	CPUInit(Config);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* This function is the primary interrupt handler for the driver.  It must be
+* connected to the interrupt source such that it is called when an interrupt of
+* the interrupt controller is active. It will resolve which interrupts are
+* active and enabled and call the appropriate interrupt handler. It uses
+* the Interrupt Type information to determine when to acknowledge the
+* interrupt.Highest priority interrupts are serviced first.
+*
+* This function assumes that an interrupt vector table has been previously
+* initialized.  It does not verify that entries in the table are valid before
+* calling an interrupt handler.
+*
+* @param	DeviceId is the unique identifier for the ScuGic device.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XScuGic_DeviceInterruptHandler(void *DeviceId)
+{
+
+	u32 IntID;
+	XScuGic_VectorTableEntry *TablePtr;
+	XScuGic_Config *CfgPtr;
+
+	CfgPtr = &XScuGic_ConfigTable[(u32 )DeviceId];
+
+	/*
+	 * Read the int_ack register to identify the highest priority
+	 * interrupt ID and make sure it is valid. Reading Int_Ack will
+	 * clear the interrupt in the GIC.
+	 */
+	IntID = XScuGic_ReadReg(CfgPtr->CpuBaseAddress, XSCUGIC_INT_ACK_OFFSET)
+					& XSCUGIC_ACK_INTID_MASK;
+	if(XSCUGIC_MAX_NUM_INTR_INPUTS < IntID){
+		goto IntrExit;
+	}
+
+	/*
+	 * If the interrupt is shared, do some locking here if there are
+	 * multiple processors.
+	 */
+	/*
+	 * If pre-eption is required:
+	 * Re-enable pre-emption by setting the CPSR I bit for non-secure ,
+	 * interrupts or the F bit for secure interrupts
+	 */
+
+	/*
+	 * If we need to change security domains, issue a SMC instruction here.
+	 */
+
+	/*
+	 * Execute the ISR. Jump into the Interrupt service routine based on
+	 * the IRQSource. A software trigger is cleared by the ACK.
+	 */
+	TablePtr = &(CfgPtr->HandlerTable[IntID]);
+	TablePtr->Handler(TablePtr->CallBackRef);
+
+IntrExit:
+	/*
+	 * Write to the EOI register, we are all done here.
+	 * Let this function return, the boot code will restore the stack.
+	 */
+	XScuGic_WriteReg(CfgPtr->CpuBaseAddress, XSCUGIC_EOI_OFFSET, IntID);
+
+	/*
+	 * Return from the interrupt. Change security domains could happen
+	 * here.
+	 */
+}
+
+/*****************************************************************************/
+/**
+*
+* Register a handler function for a specific interrupt ID.  The vector table
+* of the interrupt controller is updated, overwriting any previous handler.
+* The handler function will be called when an interrupt occurs for the given
+* interrupt ID.
+*
+* @param	BaseAddress is the CPU Interface Register base address of the
+*		interrupt controller whose vector table will be modified.
+* @param	InterruptId is the interrupt ID to be associated with the input
+*		handler.
+* @param	Handler is the function pointer that will be added to
+*		the vector table for the given interrupt ID.
+* @param	CallBackRef is the argument that will be passed to the new
+*		handler function when it is called. This is user-specific.
+*
+* @return	None.
+*
+* @note
+*
+* Note that this function has no effect if the input base address is invalid.
+*
+******************************************************************************/
+void XScuGic_RegisterHandler(u32 BaseAddress, int InterruptId,
+			     Xil_InterruptHandler Handler, void *CallBackRef)
+{
+	XScuGic_Config *CfgPtr;
+
+	CfgPtr = LookupConfigByBaseAddress(BaseAddress);
+	if (CfgPtr != NULL) {
+		CfgPtr->HandlerTable[InterruptId].Handler = Handler;
+		CfgPtr->HandlerTable[InterruptId].CallBackRef = CallBackRef;
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the CPU interface base address of
+* the device. A table contains the configuration info for each device in the
+* system.
+*
+* @param	CpuBaseAddress is the CPU Interface Register base address.
+*
+* @return 	A pointer to the configuration structure for the specified
+*		device, or NULL if the device was not found.
+*
+* @note		None.
+*
+******************************************************************************/
+static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress)
+{
+	XScuGic_Config *CfgPtr = NULL;
+	int Index;
+
+	for (Index = 0; Index < XPAR_SCUGIC_NUM_INSTANCES; Index++) {
+		if (XScuGic_ConfigTable[Index].CpuBaseAddress ==
+				CpuBaseAddress) {
+			CfgPtr = &XScuGic_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return CfgPtr;
+}
+
+/****************************************************************************/
+/**
+* Sets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param	BaseAddr is the device base address
+* @param	Int_Id is the IRQ source number to modify
+* @param	Priority is the new priority for the IRQ source. 0 is highest
+* 			priority, 0xF8 (248) is lowest. There are 32 priority levels
+*			supported with a step of 8. Hence the supported priorities are
+*			0, 8, 16, 32, 40 ..., 248.
+* @param	Trigger is the new trigger type for the IRQ source.
+* Each bit pair describes the configuration for an INT_ID.
+* SFI    Read Only    b10 always
+* PPI    Read Only    depending on how the PPIs are configured.
+*                    b01    Active HIGH level sensitive
+*                    b11 Rising edge sensitive
+* SPI                LSB is read only.
+*                    b01    Active HIGH level sensitive
+*                    b11 Rising edge sensitive/
+*
+* @return	None.
+*
+* @note		This API has the similar functionality of XScuGic_SetPriority
+*	        TriggerType() and should be used when there is no InstancePtr.
+*
+*****************************************************************************/
+void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+					u8 Priority, u8 Trigger)
+{
+	u32 RegValue;
+
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(Trigger <= XSCUGIC_INT_CFG_MASK);
+	Xil_AssertVoid(Priority <= XSCUGIC_MAX_INTR_PRIO_VAL);
+
+	/*
+	 * Determine the register to write to using the Int_Id.
+	 */
+	RegValue = XScuGic_ReadReg(DistBaseAddress,
+			XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+	/*
+	 * The priority bits are Bits 7 to 3 in GIC Priority Register. This
+	 * means the number of priority levels supported are 32 and they are
+	 * in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc.
+	 * The lower order 3 bits are masked before putting it in the register.
+	 */
+	Priority = Priority & XSCUGIC_INTR_PRIO_MASK;
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id%4)*8));
+	RegValue |= Priority << ((Int_Id%4)*8);
+
+	/*
+	 * Write the value back to the register.
+	 */
+	XScuGic_WriteReg(DistBaseAddress, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+					RegValue);
+	/*
+	 * Determine the register to write to using the Int_Id.
+	 */
+	RegValue = XScuGic_ReadReg(DistBaseAddress,
+			XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id%16)*2));
+	RegValue |= Trigger << ((Int_Id%16)*2);
+
+	/*
+	 * Write the value back to the register.
+	 */
+	XScuGic_WriteReg(DistBaseAddress, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
+				RegValue);
+}
+
+/****************************************************************************/
+/**
+* Gets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param	BaseAddr is the device base address
+* @param	Int_Id is the IRQ source number to modify
+* @param	Priority is a pointer to the value of the priority of the IRQ
+*		source. This is a return value.
+* @param	Trigger is pointer to the value of the trigger of the IRQ
+*		source. This is a return value.
+*
+* @return	None.
+*
+* @note		This API has the similar functionality of XScuGic_GetPriority
+*	        TriggerType() and should be used when there is no InstancePtr.
+*
+*****************************************************************************/
+void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+					u8 *Priority, u8 *Trigger)
+{
+	u32 RegValue;
+
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(Priority != NULL);
+	Xil_AssertVoid(Trigger != NULL);
+
+	/*
+	 * Determine the register to read to using the Int_Id.
+	 */
+	RegValue = XScuGic_ReadReg(DistBaseAddress,
+	    XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue = RegValue >> ((Int_Id%4)*8);
+	*Priority = RegValue & XSCUGIC_PRIORITY_MASK;
+
+	/*
+	 * Determine the register to read to using the Int_Id.
+	 */
+	RegValue = XScuGic_ReadReg(DistBaseAddress,
+	    XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue = RegValue >> ((Int_Id%16)*2);
+
+	*Trigger = RegValue & XSCUGIC_INT_CFG_MASK;
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/xscugic_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/xscugic_hw.h
new file mode 100644
index 000000000..0530ee8c0
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/xscugic_hw.h
@@ -0,0 +1,641 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_hw.h
+*
+* This header file contains identifiers and HW access functions (or
+* macros) that can be used to access the device.  The user should refer to the
+* hardware device specification for more details of the device operation.
+* The driver functions/APIs are defined in xscugic.h.
+*
+* This GIC device has two parts, a distributor and CPU interface(s). Each part
+* has separate register definition sections.
+*
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 1.01a sdm  11/09/11 "xil_exception.h" added as include.
+*		      Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
+*		      added to enable or disable interrupts based on
+*		      Distributor Register base address. Normally users use
+*		      XScuGic instance and call XScuGic_Enable or
+*		      XScuGic_Disable to enable/disable interrupts. These
+*		      new macros are provided when user does not want to
+*		      use an instance pointer but still wants to enable or
+*		      disable interrupts.
+*		      Function prototypes for functions (present in newly
+*		      added file xscugic_hw.c) are added.
+* 1.03a srt  02/27/13 Moved Offset calculation macros from *_hw.c (CR
+*		      702687).
+* 1.04a hk   05/04/13 Fix for CR#705621. Moved function prototypes
+*			  XScuGic_SetPriTrigTypeByDistAddr and
+*             XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
+*
+* 

+*
+******************************************************************************/
+
+#ifndef XSCUGIC_HW_H /* prevent circular inclusions */
+#define XSCUGIC_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xil_exception.h"
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * The maximum number of interrupts supported by the hardware.
+ */
+#define XSCUGIC_MAX_NUM_INTR_INPUTS    	95
+
+/*
+ * The maximum priority value that can be used in the GIC.
+ */
+#define XSCUGIC_MAX_INTR_PRIO_VAL    	248
+#define XSCUGIC_INTR_PRIO_MASK			0xF8
+
+/** @name Distributor Interface Register Map
+ *
+ * Define the offsets from the base address for all Distributor registers of
+ * the interrupt controller, some registers may be reserved in the hardware
+ * device.
+ * @{
+ */
+#define XSCUGIC_DIST_EN_OFFSET		0x00000000 /**< Distributor Enable
+						 	Register */
+#define XSCUGIC_IC_TYPE_OFFSET		0x00000004 /**< Interrupt Controller
+						 	Type Register */
+#define XSCUGIC_DIST_IDENT_OFFSET	0x00000008 /**< Implementor ID
+							Register */
+#define XSCUGIC_SECURITY_OFFSET		0x00000080 /**< Interrupt Security
+						 	Register */
+#define XSCUGIC_ENABLE_SET_OFFSET	0x00000100 /**< Enable Set
+							Register */
+#define XSCUGIC_DISABLE_OFFSET		0x00000180 /**< Enable Clear Register */
+#define XSCUGIC_PENDING_SET_OFFSET	0x00000200 /**< Pending Set
+							Register */
+#define XSCUGIC_PENDING_CLR_OFFSET	0x00000280 /**< Pending Clear
+							Register */
+#define XSCUGIC_ACTIVE_OFFSET		0x00000300 /**< Active Status Register */
+#define XSCUGIC_PRIORITY_OFFSET		0x00000400 /**< Priority Level Register */
+#define XSCUGIC_SPI_TARGET_OFFSET	0x00000800 /**< SPI Target
+							Register 0x800-0x8FB */
+#define XSCUGIC_INT_CFG_OFFSET		0x00000C00 /**< Interrupt Configuration
+						 	Register 0xC00-0xCFC */
+#define XSCUGIC_PPI_STAT_OFFSET		0x00000D00 /**< PPI Status Register */
+#define XSCUGIC_SPI_STAT_OFFSET		0x00000D04 /**< SPI Status Register
+							0xd04-0xd7C */
+#define XSCUGIC_AHB_CONFIG_OFFSET	0x00000D80 /**< AHB Configuration
+							Register */
+#define XSCUGIC_SFI_TRIG_OFFSET		0x00000F00 /**< Software Triggered
+							Interrupt Register */
+#define XSCUGIC_PERPHID_OFFSET		0x00000FD0 /**< Peripheral ID Reg */
+#define XSCUGIC_PCELLID_OFFSET		0x00000FF0 /**< Pcell ID Register */
+/* @} */
+
+/** @name  Distributor Enable Register
+ * Controls if the distributor response to external interrupt inputs.
+ * @{
+ */
+#define XSCUGIC_EN_INT_MASK		0x00000001 /**< Interrupt In Enable */
+/* @} */
+
+/** @name  Interrupt Controller Type Register
+ * @{
+ */
+#define XSCUGIC_LSPI_MASK	0x0000F800 /**< Number of Lockable
+						Shared Peripheral
+						Interrupts*/
+#define XSCUGIC_DOMAIN_MASK	0x00000400 /**< Number os Security domains*/
+#define XSCUGIC_CPU_NUM_MASK	0x000000E0 /**< Number of CPU Interfaces */
+#define XSCUGIC_NUM_INT_MASK	0x0000001F /**< Number of Interrupt IDs */
+/* @} */
+
+/** @name  Implementor ID Register
+ * Implementor and revision information.
+ * @{
+ */
+#define XSCUGIC_REV_MASK	0x00FFF000 /**< Revision Number */
+#define XSCUGIC_IMPL_MASK	0x00000FFF /**< Implementor */
+/* @} */
+
+/** @name  Interrupt Security Registers
+ * Each bit controls the security level of an interrupt, either secure or non
+ * secure. These registers can only be accessed using secure read and write.
+ * There are registers for each of the CPU interfaces at offset 0x080.  A
+ * register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x084.
+ * @{
+ */
+#define XSCUGIC_INT_NS_MASK	0x00000001 /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Enable Set Register
+ * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is
+ * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a
+ * bit to 0.
+ * There are registers for each of the CPU interfaces at offset 0x100. With up
+ * to 8 registers aliased to the same address. A register set for the SPI
+ * interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x104.
+ * @{
+ */
+#define XSCUGIC_INT_EN_MASK	0x00000001 /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Enable Clear Register
+ * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is
+ * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and
+ * sets the corresponding bit to 0.
+ * There are registers for each of the CPU interfaces at offset 0x180. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x184.
+ * @{
+ */
+#define XSCUGIC_INT_CLR_MASK	0x00000001 /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Pending Set Register
+ * Each bit controls the Pending or Active and Pending state of an interrupt, a
+ * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets
+ * an interrupt to the pending state.
+ * There are registers for each of the CPU interfaces at offset 0x200. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x204.
+ * @{
+ */
+#define XSCUGIC_PEND_SET_MASK	0x00000001 /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Pending Clear Register
+ * Each bit can clear the Pending or Active and Pending state of an interrupt, a
+ * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1
+ * clears the pending state of an interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x280. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x284.
+ * @{
+ */
+#define XSCUGIC_PEND_CLR_MASK	0x00000001 /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Active Status Register
+ * Each bit provides the Active status of an interrupt, a
+ * 0 is not Active, a 1 is Active. This is a read only register.
+ * There are registers for each of the CPU interfaces at offset 0x300. With up
+ * to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x380.
+ * @{
+ */
+#define XSCUGIC_ACTIVE_MASK	0x00000001 /**< Each bit corresponds to an
+					      INT_ID */
+/* @} */
+
+/** @name  Priority Level Register
+ * Each byte in a Priority Level Register sets the priority level of an
+ * interrupt. Reading the register provides the priority level of an interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x400 through
+ * 0x41C. With up to 8 registers aliased to each address.
+ * 0 is highest priority, 0xFF is lowest.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0x420.
+ * @{
+ */
+#define XSCUGIC_PRIORITY_MASK	0x000000FF /**< Each Byte corresponds to an
+						INT_ID */
+#define XSCUGIC_PRIORITY_MAX	0x000000FF /**< Highest value of a priority
+						actually the lowest priority*/
+/* @} */
+
+/** @name  SPI Target Register 0x800-0x8FB
+ * Each byte references a separate SPI and programs which of the up to 8 CPU
+ * interfaces are sent a Pending interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x800 through
+ * 0x81C. With up to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0x820.
+ *
+ * This driver does not support multiple CPU interfaces. These are included
+ * for complete documentation.
+ * @{
+ */
+#define XSCUGIC_SPI_CPU7_MASK	0x00000080 /**< CPU 7 Mask*/
+#define XSCUGIC_SPI_CPU6_MASK	0x00000040 /**< CPU 6 Mask*/
+#define XSCUGIC_SPI_CPU5_MASK	0x00000020 /**< CPU 5 Mask*/
+#define XSCUGIC_SPI_CPU4_MASK	0x00000010 /**< CPU 4 Mask*/
+#define XSCUGIC_SPI_CPU3_MASK	0x00000008 /**< CPU 3 Mask*/
+#define XSCUGIC_SPI_CPU2_MASK	0x00000003 /**< CPU 2 Mask*/
+#define XSCUGIC_SPI_CPU1_MASK	0x00000002 /**< CPU 1 Mask*/
+#define XSCUGIC_SPI_CPU0_MASK	0x00000001 /**< CPU 0 Mask*/
+/* @} */
+
+/** @name  Interrupt Configuration Register 0xC00-0xCFC
+ * The interrupt configuration registers program an SFI to be active HIGH level
+ * sensitive or rising edge sensitive.
+ * Each bit pair describes the configuration for an INT_ID.
+ * SFI    Read Only    b10 always
+ * PPI    Read Only    depending on how the PPIs are configured.
+ *                    b01    Active HIGH level sensitive
+ *                    b11 Rising edge sensitive
+ * SPI                LSB is read only.
+ *                    b01    Active HIGH level sensitive
+ *                    b11 Rising edge sensitive/
+ * There are registers for each of the CPU interfaces at offset 0xC00 through
+ * 0xC04. With up to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0xC08.
+ * @{
+ */
+#define XSCUGIC_INT_CFG_MASK    0x00000003    /**< */
+/* @} */
+
+/** @name  PPI Status Register
+ * Enables an external AMBA master to access the status of the PPI inputs.
+ * A CPU can only read the status of its local PPI signals and cannot read the
+ * status for other CPUs.
+ * This register is aliased for each CPU interface.
+ * @{
+ */
+#define XSCUGIC_PPI_C15_MASK	0x00008000    /**< PPI Status */
+#define XSCUGIC_PPI_C14_MASK	0x00004000    /**< PPI Status */
+#define XSCUGIC_PPI_C13_MASK	0x00002000    /**< PPI Status */
+#define XSCUGIC_PPI_C12_MASK	0x00001000    /**< PPI Status */
+#define XSCUGIC_PPI_C11_MASK	0x00000800    /**< PPI Status */
+#define XSCUGIC_PPI_C10_MASK	0x00000400    /**< PPI Status */
+#define XSCUGIC_PPI_C09_MASK	0x00000200    /**< PPI Status */
+#define XSCUGIC_PPI_C08_MASK	0x00000100    /**< PPI Status */
+#define XSCUGIC_PPI_C07_MASK	0x00000080    /**< PPI Status */
+#define XSCUGIC_PPI_C06_MASK	0x00000040    /**< PPI Status */
+#define XSCUGIC_PPI_C05_MASK	0x00000020    /**< PPI Status */
+#define XSCUGIC_PPI_C04_MASK	0x00000010    /**< PPI Status */
+#define XSCUGIC_PPI_C03_MASK	0x00000008    /**< PPI Status */
+#define XSCUGIC_PPI_C02_MASK	0x00000004    /**< PPI Status */
+#define XSCUGIC_PPI_C01_MASK	0x00000002    /**< PPI Status */
+#define XSCUGIC_PPI_C00_MASK	0x00000001    /**< PPI Status */
+/* @} */
+
+/** @name  SPI Status Register 0xd04-0xd7C
+ * Enables an external AMBA master to access the status of the SPI inputs.
+ * There are up to 63 registers if the maximum number of SPI inputs are
+ * configured.
+ * @{
+ */
+#define XSCUGIC_SPI_N_MASK    0x00000001    /**< Each bit corresponds to an SPI
+					     input */
+/* @} */
+
+/** @name  AHB Configuration Register
+ * Provides the status of the CFGBIGEND input signal and allows the endianess
+ * of the GIC to be set.
+ * @{
+ */
+#define XSCUGIC_AHB_END_MASK       0x00000004    /**< 0-GIC uses little Endian,
+                                                  1-GIC uses Big Endian */
+#define XSCUGIC_AHB_ENDOVR_MASK    0x00000002    /**< 0-Uses CFGBIGEND control,
+                                                  1-use the AHB_END bit */
+#define XSCUGIC_AHB_TIE_OFF_MASK   0x00000001    /**< State of CFGBIGEND */
+
+/* @} */
+
+/** @name  Software Triggered Interrupt Register
+ * Controls issueing of software interrupts.
+ * @{
+ */
+#define XSCUGIC_SFI_SELFTRIG_MASK	0x02010000
+#define XSCUGIC_SFI_TRIG_TRGFILT_MASK    0x03000000    /**< Target List filter
+                                                            b00-Use the target List
+                                                            b01-All CPUs except requester
+                                                            b10-To Requester
+                                                            b11-reserved */
+#define XSCUGIC_SFI_TRIG_CPU_MASK	0x00FF0000    /**< CPU Target list */
+#define XSCUGIC_SFI_TRIG_SATT_MASK	0x00008000    /**< 0= Use a secure interrupt */
+#define XSCUGIC_SFI_TRIG_INTID_MASK	0x0000000F    /**< Set to the INTID
+                                                        signaled to the CPU*/
+/* @} */
+
+/** @name CPU Interface Register Map
+ *
+ * Define the offsets from the base address for all CPU registers of the
+ * interrupt controller, some registers may be reserved in the hardware device.
+ * @{
+ */
+#define XSCUGIC_CONTROL_OFFSET		0x00000000 /**< CPU Interface Control
+						 	Register */
+#define XSCUGIC_CPU_PRIOR_OFFSET	0x00000004 /**< Priority Mask Reg */
+#define XSCUGIC_BIN_PT_OFFSET		0x00000008 /**< Binary Point Register */
+#define XSCUGIC_INT_ACK_OFFSET		0x0000000C /**< Interrupt ACK Reg */
+#define XSCUGIC_EOI_OFFSET		0x00000010 /**< End of Interrupt Reg */
+#define XSCUGIC_RUN_PRIOR_OFFSET	0x00000014 /**< Running Priority Reg */
+#define XSCUGIC_HI_PEND_OFFSET		0x00000018 /**< Highest Pending Interrupt
+							Register */
+#define XSCUGIC_ALIAS_BIN_PT_OFFSET	0x0000001C /**< Aliased non-Secure
+						        Binary Point Register */
+
+/**<  0x00000020 to 0x00000FBC are reserved and should not be read or written
+ * to. */
+/* @} */
+
+
+/** @name Control Register
+ * CPU Interface Control register definitions
+ * All bits are defined here although some are not available in the non-secure
+ * mode.
+ * @{
+ */
+#define XSCUGIC_CNTR_SBPR_MASK	0x00000010    /**< Secure Binary Pointer,
+                                                 0=separate registers,
+                                                 1=both use bin_pt_s */
+#define XSCUGIC_CNTR_FIQEN_MASK	0x00000008    /**< Use nFIQ_C for secure
+                                                  interrupts,
+                                                  0= use IRQ for both,
+                                                  1=Use FIQ for secure, IRQ for non*/
+#define XSCUGIC_CNTR_ACKCTL_MASK	0x00000004    /**< Ack control for secure or non secure */
+#define XSCUGIC_CNTR_EN_NS_MASK		0x00000002    /**< Non Secure enable */
+#define XSCUGIC_CNTR_EN_S_MASK		0x00000001    /**< Secure enable, 0=Disabled, 1=Enabled */
+/* @} */
+
+/** @name Priority Mask Register
+ * Priority Mask register definitions
+ * The CPU interface does not send interrupt if the level of the interrupt is
+ * lower than the level of the register.
+ * @{
+ */
+#define XSCUGIC_PRIORITY_MASK		0x000000FF    /**< All interrupts */
+/* @} */
+
+/** @name Binary Point Register
+ * Binary Point register definitions
+ * @{
+ */
+
+#define XSCUGIC_BIN_PT_MASK	0x00000007  /**< Binary point mask value
+						Value  Secure  Non-secure
+						b000    0xFE    0xFF
+						b001    0xFC    0xFE
+						b010    0xF8    0xFC
+						b011    0xF0    0xF8
+						b100    0xE0    0xF0
+						b101    0xC0    0xE0
+						b110    0x80    0xC0
+						b111    0x00    0x80
+						*/
+/*@}*/
+
+/** @name Interrupt Acknowledge Register
+ * Interrupt Acknowledge register definitions
+ * Identifies the current Pending interrupt, and the CPU ID for software
+ * interrupts.
+ */
+#define XSCUGIC_ACK_INTID_MASK		0x000003FF /**< Interrupt ID */
+#define XSCUGIC_CPUID_MASK		0x00000C00 /**< CPU ID */
+/* @} */
+
+/** @name End of Interrupt Register
+ * End of Interrupt register definitions
+ * Allows the CPU to signal the GIC when it completes an interrupt service
+ * routine.
+ */
+#define XSCUGIC_EOI_INTID_MASK		0x000003FF /**< Interrupt ID */
+
+/* @} */
+
+/** @name Running Priority Register
+ * Running Priority register definitions
+ * Identifies the interrupt priority level of the highest priority active
+ * interrupt.
+ */
+#define XSCUGIC_RUN_PRIORITY_MASK	0x00000FF    /**< Interrupt Priority */
+/* @} */
+
+/*
+ * Highest Pending Interrupt register definitions
+ * Identifies the interrupt priority of the highest priority pending interupt
+ */
+#define XSCUGIC_PEND_INTID_MASK		0x000003FF /**< Pending Interrupt ID */
+#define XSCUGIC_CPUID_MASK		0x00000C00 /**< CPU ID */
+/* @} */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Configuration Register offset for an interrupt id.
+*
+* @param	InterruptID is the interrupt number.
+*
+* @return	The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \
+	(XSCUGIC_INT_CFG_OFFSET + ((InterruptID/16) * 4))
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Priority Register offset for an interrupt id.
+*
+* @param	InterruptID is the interrupt number.
+*
+* @return	The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \
+	(XSCUGIC_PRIORITY_OFFSET + ((InterruptID/4) * 4))
+
+/****************************************************************************/
+/**
+*
+* Read the SPI Target Register offset for an interrupt id.
+*
+* @param	InterruptID is the interrupt number.
+*
+* @return	The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \
+	(XSCUGIC_SPI_TARGET_OFFSET + ((InterruptID/4) * 4))
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Clear-Enable Register offset for an interrupt ID
+*
+* @param	Register is the register offset for the clear/enable bank.
+* @param	InterruptID is the interrupt number.
+*
+* @return	The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_ENABLE_DISABLE_OFFSET_CALC(Register, InterruptID) \
+	(Register + ((InterruptID/32) * 4))
+
+/****************************************************************************/
+/**
+*
+* Read the given Intc register.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	RegOffset is the register offset to be read
+*
+* @return	The 32-bit value of the register
+*
+* @note
+* C-style signature:
+*    u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_ReadReg(BaseAddress, RegOffset) \
+	(Xil_In32((BaseAddress) + (RegOffset)))
+
+
+/****************************************************************************/
+/**
+*
+* Write the given Intc register.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	RegOffset is the register offset to be written
+* @param	Data is the 32-bit value to write to the register
+*
+* @return	None.
+*
+* @note
+* C-style signature:
+*    void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \
+	(Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)Data)))
+
+
+/****************************************************************************/
+/**
+*
+* Enable specific interrupt(s) in the interrupt controller.
+*
+* @param	DistBaseAddress is the Distributor Register base address of the
+*		device
+* @param	Int_Id is the ID of the interrupt source and should be in the
+*		range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuGic_EnableIntr(u32 DistBaseAddress, u32 Int_Id);
+*
+*****************************************************************************/
+#define XScuGic_EnableIntr(DistBaseAddress, Int_Id) \
+	XScuGic_WriteReg((DistBaseAddress), \
+			 XSCUGIC_ENABLE_SET_OFFSET + ((Int_Id / 32) * 4), \
+			 (1 << (Int_Id % 32)))
+
+/****************************************************************************/
+/**
+*
+* Disable specific interrupt(s) in the interrupt controller.
+*
+* @param	DistBaseAddress is the Distributor Register base address of the
+*		device
+* @param	Int_Id is the ID of the interrupt source and should be in the
+*		range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuGic_DisableIntr(u32 DistBaseAddress, u32 Int_Id);
+*
+*****************************************************************************/
+#define XScuGic_DisableIntr(DistBaseAddress, Int_Id) \
+	XScuGic_WriteReg((DistBaseAddress), \
+			 XSCUGIC_DISABLE_OFFSET + ((Int_Id / 32) * 4), \
+			 (1 << (Int_Id % 32)))
+
+
+/************************** Function Prototypes ******************************/
+
+void XScuGic_DeviceInterruptHandler(void *DeviceId);
+int  XScuGic_DeviceInitialize(u32 DeviceId);
+void XScuGic_RegisterHandler(u32 BaseAddress, int InterruptId,
+			     Xil_InterruptHandler Handler, void *CallBackRef);
+void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+                                        u8 Priority, u8 Trigger);
+void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+					u8 *Priority, u8 *Trigger);
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+
+#endif            /* end of protection macro */
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/xscugic_intr.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/xscugic_intr.c
new file mode 100644
index 000000000..e839695fd
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/xscugic_intr.c
@@ -0,0 +1,176 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_intr.c
+*
+* This file contains the interrupt processing for the driver for the Xilinx
+* Interrupt Controller.  The interrupt processing is partitioned separately such
+* that users are not required to use the provided interrupt processing.  This
+* file requires other files of the driver to be linked in also.
+*
+* The interrupt handler, XScuGic_InterruptHandler, uses an input argument which
+* is an instance pointer to an interrupt controller driver such that multiple
+* interrupt controllers can be supported.  This handler requires the calling
+* function to pass it the appropriate argument, so another level of indirection
+* may be required.
+*
+* The interrupt processing may be used by connecting the interrupt handler to
+* the interrupt system.  The handler does not save and restore the processor
+* context but only handles the processing of the Interrupt Controller. The user
+* is encouraged to supply their own interrupt handler when performance tuning is
+* deemed necessary.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 1.01a sdm  11/09/11 XScuGic_InterruptHandler has changed correspondingly
+*		      since the HandlerTable has now moved to XScuGic_Config.
+*
+* 

+*
+* @internal
+*
+* This driver assumes that the context of the processor has been saved prior to
+* the calling of the Interrupt Controller interrupt handler and then restored
+* after the handler returns. This requires either the running RTOS to save the
+* state of the machine or that a wrapper be used as the destination of the
+* interrupt vector to save the state of the processor and restore the state
+* after the interrupt handler returns.
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* This function is the primary interrupt handler for the driver.  It must be
+* connected to the interrupt source such that it is called when an interrupt of
+* the interrupt controller is active. It will resolve which interrupts are
+* active and enabled and call the appropriate interrupt handler. It uses
+* the Interrupt Type information to determine when to acknowledge the interrupt.
+* Highest priority interrupts are serviced first.
+*
+* This function assumes that an interrupt vector table has been previously
+* initialized.  It does not verify that entries in the table are valid before
+* calling an interrupt handler.
+*
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XScuGic_InterruptHandler(XScuGic *InstancePtr)
+{
+
+    u32 IntID;
+	    u32 IntIDFull;
+	    XScuGic_VectorTableEntry *TablePtr;
+
+	    /* Assert that the pointer to the instance is valid
+	     */
+	    Xil_AssertVoid(InstancePtr != NULL);
+
+	    /*
+	     * Read the int_ack register to identify the highest priority interrupt ID
+	     * and make sure it is valid. Reading Int_Ack will clear the interrupt
+	     * in the GIC.
+	     */
+	    IntIDFull = XScuGic_CPUReadReg(InstancePtr, XSCUGIC_INT_ACK_OFFSET);
+	    IntID = IntIDFull & XSCUGIC_ACK_INTID_MASK;
+
+	    if(XSCUGIC_MAX_NUM_INTR_INPUTS < IntID){
+		goto IntrExit;
+	    }
+
+	    /*
+	     * If the interrupt is shared, do some locking here if there are multiple
+	     * processors.
+	     */
+	    /*
+	     * If pre-eption is required:
+	     * Re-enable pre-emption by setting the CPSR I bit for non-secure ,
+	     * interrupts or the F bit for secure interrupts
+	     */
+
+	    /*
+	     * If we need to change security domains, issue a SMC instruction here.
+	     */
+
+	    /*
+	     * Execute the ISR. Jump into the Interrupt service routine based on the
+	     * IRQSource. A software trigger is cleared by the ACK.
+	     */
+	        TablePtr = &(InstancePtr->Config->HandlerTable[IntID]);
+	        TablePtr->Handler(TablePtr->CallBackRef);
+
+	IntrExit:
+	    /*
+	     * Write to the EOI register, we are all done here.
+	     * Let this function return, the boot code will restore the stack.
+	     */
+	    XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_EOI_OFFSET, IntIDFull);
+
+	    /*
+	     * Return from the interrupt. Change security domains could happen here.
+     */
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/xscugic_selftest.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/xscugic_selftest.c
new file mode 100644
index 000000000..569cb54de
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/xscugic_selftest.c
@@ -0,0 +1,119 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_selftest.c
+*
+* Contains diagnostic self-test functions for the XScuGic driver.
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a drg  01/19/10 First release
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+#define	XSCUGIC_PCELL_ID	0xB105F00D
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Run a self-test on the driver/device. This test reads the ID registers and
+* compares them.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+*
+* @return
+*
+* 		- XST_SUCCESS if self-test is successful.
+* 		- XST_FAILURE if the self-test is not successful.
+*
+* @note		None.
+*
+******************************************************************************/
+int  XScuGic_SelfTest(XScuGic *InstancePtr)
+{
+	u32 RegValue1 =0;
+	int Index;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the ID registers.
+	 */
+	for(Index=0; Index<=3; Index++) {
+		RegValue1 |= XScuGic_DistReadReg(InstancePtr,
+			(XSCUGIC_PCELLID_OFFSET + (Index * 4))) << (Index * 8);
+	}
+
+	if(XSCUGIC_PCELL_ID != RegValue1){
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/xscugic_sinit.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/xscugic_sinit.c
new file mode 100644
index 000000000..a4cb7d3c2
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v2_1/src/xscugic_sinit.c
@@ -0,0 +1,109 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_sinit.c
+*
+* Contains static init functions for the XScuGic driver for the Interrupt
+* Controller. See xscugic.h for a detailed description of the driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- --------------------------------------------------------
+* 1.00a drg  01/19/10 First release
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xparameters.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+extern XScuGic_Config XScuGic_ConfigTable[];
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId is the unique identifier for a device.
+*
+* @return	A pointer to the XScuGic configuration structure for the
+*		specified device, or NULL if the device was not found.
+*
+* @note		None.
+*
+******************************************************************************/
+XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId)
+{
+	XScuGic_Config *CfgPtr = NULL;
+	int Index;
+
+	for (Index=0; Index < XPAR_SCUGIC_NUM_INSTANCES; Index++) {
+		if (XScuGic_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XScuGic_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return CfgPtr;
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_0/src/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_0/src/Makefile
new file mode 100644
index 000000000..f50acb48d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_0/src/Makefile
@@ -0,0 +1,41 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner scutimer_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling scutimer"
+
+scutimer_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: scutimer_includes
+
+scutimer_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_0/src/xscutimer.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_0/src/xscutimer.c
new file mode 100644
index 000000000..c3b4b72eb
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_0/src/xscutimer.c
@@ -0,0 +1,289 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* @file xscutimer.c
+*
+* Contains the implementation of interface functions of the SCU Timer driver.
+* See xscutimer.h for a description of the driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm  03/10/10 First release
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscutimer.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Initialize a specific timer instance/driver. This function  must be called
+* before other functions of the driver are called.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+* @param	ConfigPtr points to the XScuTimer configuration structure.
+* @param	EffectiveAddress is the base address for the device. It could be
+*		a virtual address if address translation is supported in the
+*		system, otherwise it is the physical address.
+*
+* @return
+*		- XST_SUCCESS if initialization was successful.
+*		- XST_DEVICE_IS_STARTED if the device has already been started.
+*
+* @note		None.
+*
+******************************************************************************/
+int XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
+			 XScuTimer_Config *ConfigPtr, u32 EffectiveAddress)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * If the device is started, disallow the initialize and return a
+	 * status indicating it is started. This allows the user to stop the
+	 * device and reinitialize, but prevents a user from inadvertently
+	 * initializing.
+	 */
+	if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
+		return XST_DEVICE_IS_STARTED;
+	}
+
+	/*
+	 * Copy configuration into the instance structure.
+	 */
+	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+
+	/*
+	 * Save the base address pointer such that the registers of the block
+	 * can be accessed and indicate it has not been started yet.
+	 */
+	InstancePtr->Config.BaseAddr = EffectiveAddress;
+
+	InstancePtr->IsStarted = 0;
+
+	/*
+	 * Indicate the instance is ready to use, successfully initialized.
+	 */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* Start the timer.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XScuTimer_Start(XScuTimer *InstancePtr)
+{
+	u32 Register;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the contents of the Control register.
+	 */
+	Register = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+				  XSCUTIMER_CONTROL_OFFSET);
+
+	/*
+	 * Set the 'timer enable' bit in the register.
+	 */
+	Register |= XSCUTIMER_CONTROL_ENABLE_MASK;
+
+	/*
+	 * Update the Control register with the new value.
+	 */
+	XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+			XSCUTIMER_CONTROL_OFFSET, Register);
+
+	/*
+	 * Indicate that the device is started.
+	 */
+	InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
+}
+
+/****************************************************************************/
+/**
+*
+* Stop the timer.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XScuTimer_Stop(XScuTimer *InstancePtr)
+{
+	u32 Register;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the contents of the Control register.
+	 */
+	Register = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+				  XSCUTIMER_CONTROL_OFFSET);
+
+	/*
+	 * Clear the 'timer enable' bit in the register.
+	 */
+	Register &= ~XSCUTIMER_CONTROL_ENABLE_MASK;
+
+	/*
+	 * Update the Control register with the new value.
+	 */
+	XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+			XSCUTIMER_CONTROL_OFFSET, Register);
+
+	/*
+	 * Indicate that the device is stopped.
+	 */
+	InstancePtr->IsStarted = 0;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the prescaler bits in the timer control register.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+* @param	PrescalerValue is a 8 bit value that sets the prescaler to use.
+*
+* @return	None
+*
+* @note		None
+*
+****************************************************************************/
+void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue)
+{
+	u32 ControlReg;
+
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	/*
+	 * Read the Timer control register.
+	 */
+	ControlReg = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+					XSCUTIMER_CONTROL_OFFSET);
+
+	/*
+	 * Clear all of the prescaler control bits in the register.
+	 */
+	ControlReg &= ~XSCUTIMER_CONTROL_PRESCALER_MASK;
+
+	/*
+	 * Set the prescaler value.
+	 */
+	ControlReg |= (PrescalerValue << XSCUTIMER_CONTROL_PRESCALER_SHIFT);
+
+	/*
+	 * Write the register with the new values.
+	 */
+	XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+			  XSCUTIMER_CONTROL_OFFSET, ControlReg);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function returns the current prescaler value.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	The prescaler value.
+*
+* @note		None.
+*
+****************************************************************************/
+u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr)
+{
+	u32 ControlReg;
+
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Timer control register.
+	 */
+	ControlReg = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+				    XSCUTIMER_CONTROL_OFFSET);
+	ControlReg &= XSCUTIMER_CONTROL_PRESCALER_MASK;
+
+	return (ControlReg >> XSCUTIMER_CONTROL_PRESCALER_SHIFT);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_0/src/xscutimer.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_0/src/xscutimer.h
new file mode 100644
index 000000000..1912b1061
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_0/src/xscutimer.h
@@ -0,0 +1,370 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer.h
+*
+* The timer driver supports the Cortex A9 private timer.
+*
+* The timer driver supports the following features:
+* - Normal mode and Auto reload mode
+* - Interrupts (Interrupt handler is not provided in this driver. Application
+* 		has to register it's own handler)
+*
+*  Initialization and Configuration 
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Timer.
+*
+* XScuTimer_CfgInitialize() API is used to initialize the Timer. The
+* user needs to first call the XScuTimer_LookupConfig() API which returns
+* the Configuration structure pointer which is passed as a parameter to
+* the XScuTimer_CfgInitialize() API.
+*
+*  Interrupts 
+*
+* The Timer hardware supports interrupts.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* Timer in interrupt mode.
+*
+*  Virtual Memory 
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+*  Threads 
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+*  Asserts 
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+*  Building the driver 
+*
+* The XScuTimer driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+* 


+*
+* NOTE:
+* The timer is not a part of the snoop control unit as indicated by the
+* prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm  03/10/10 First release
+* 1.02a sg  07/17/12 Included xil_assert.h for CR 667947. This is an issue
+*		     when the xstatus.h in the common driver overwrites
+*		     the xstatus.h of the standalone BSP during the
+*		     libgen.
+* 

+*
+******************************************************************************/
+#ifndef XSCUTIMER_H		/* prevent circular inclusions */
+#define XSCUTIMER_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xscutimer_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;	/**< Unique ID of device */
+	u32 BaseAddr;	/**< Base address of the device */
+} XScuTimer_Config;
+
+/**
+ * The XScuTimer driver instance data. The user is required to allocate a
+ * variable of this type for every timer device in the system.
+ * A pointer to a variable of this type is then passed to the driver API
+ * functions.
+ */
+typedef struct {
+	XScuTimer_Config Config; /**< Hardware Configuration */
+	u32 IsReady;		/**< Device is initialized and ready */
+	u32 IsStarted;		/**< Device timer is running */
+} XScuTimer;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Check if the timer has expired.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return
+*		- TRUE if the timer has expired.
+*		- FALSE if the timer has not expired.
+*
+* @note		C-style signature:
+*		int XScuTimer_IsExpired(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_IsExpired(InstancePtr) \
+	((XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+				XSCUTIMER_ISR_OFFSET) & \
+				XSCUTIMER_ISR_EVENT_FLAG_MASK) == \
+				XSCUTIMER_ISR_EVENT_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* Re-start the timer. This macro will read the timer load register
+* and writes the same value to load register to update the counter register.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_RestartTimer(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_RestartTimer(InstancePtr)				\
+	XScuTimer_LoadTimer(InstancePtr,				\
+		XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+					XSCUTIMER_LOAD_OFFSET))
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+* @param	Value is the count to be loaded in to the load register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_LoadTimer(XScuTimer *InstancePtr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_LoadTimer(InstancePtr, Value)				\
+	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUTIMER_LOAD_OFFSET, Value)
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value. It can be called at any
+* time.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	Contents of the timer counter register.
+*
+* @note		C-style signature:
+		u32 XScuTimer_GetCounterValue(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_GetCounterValue(InstancePtr)				\
+	XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,		\
+				XSCUTIMER_COUNTER_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Enable auto-reload mode.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_EnableAutoReload(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_EnableAutoReload(InstancePtr)				\
+	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUTIMER_CONTROL_OFFSET,			\
+			(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+				XSCUTIMER_CONTROL_OFFSET) |		 \
+				XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))
+
+/****************************************************************************/
+/**
+*
+* Disable auto-reload mode.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_DisableAutoReload(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_DisableAutoReload(InstancePtr)			\
+	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUTIMER_CONTROL_OFFSET,			\
+			(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+				XSCUTIMER_CONTROL_OFFSET) &		\
+				~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)))
+
+/****************************************************************************/
+/**
+*
+* Enable the Timer interrupt.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_EnableInterrupt(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_EnableInterrupt(InstancePtr)				\
+	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUTIMER_CONTROL_OFFSET,			\
+			(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+					XSCUTIMER_CONTROL_OFFSET) |	\
+					XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))
+
+/****************************************************************************/
+/**
+*
+* Disable the Timer interrupt.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_DisableInterrupt(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_DisableInterrupt(InstancePtr)				\
+	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUTIMER_CONTROL_OFFSET,			\
+			(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+				XSCUTIMER_CONTROL_OFFSET) &		\
+				~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)))
+
+/*****************************************************************************/
+/**
+*
+* This function reads the interrupt status.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_GetInterruptStatus(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_GetInterruptStatus(InstancePtr)			\
+	XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUTIMER_ISR_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function clears the interrupt status.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_ClearInterruptStatus(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_ClearInterruptStatus(InstancePtr)			\
+	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
+		XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK)
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xscutimer_sinit.c
+ */
+XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xscutimer_selftest.c
+ */
+int XScuTimer_SelfTest(XScuTimer *InstancePtr);
+
+/*
+ * Interface functions in xscutimer.c
+ */
+int XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
+			    XScuTimer_Config *ConfigPtr, u32 EffectiveAddress);
+void XScuTimer_Start(XScuTimer *InstancePtr);
+void XScuTimer_Stop(XScuTimer *InstancePtr);
+void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue);
+u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_0/src/xscutimer_g.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_0/src/xscutimer_g.c
new file mode 100644
index 000000000..7aa141ea7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_0/src/xscutimer_g.c
@@ -0,0 +1,31 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSM.
+* Version: 
+* DO NOT EDIT.
+*
+*  v (64-bit)
+SW Build (by ) on 
+Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xscutimer.h"
+
+/*
+* The configuration table for devices
+*/
+
+XScuTimer_Config XScuTimer_ConfigTable[] =
+{
+	{
+		XPAR_PS7_SCUTIMER_0_DEVICE_ID,
+		XPAR_PS7_SCUTIMER_0_BASEADDR
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_0/src/xscutimer_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_0/src/xscutimer_hw.h
new file mode 100644
index 000000000..d18cf6366
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_0/src/xscutimer_hw.h
@@ -0,0 +1,292 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer_hw.h
+*
+* This file contains the hardware interface to the Timer.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm  03/10/10 First release
+* 1.01a sdm 02/02/12 Added low level macros to read/write load, counter, control
+*		     and interrupt registers
+* 1.02a  sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+*		     when the xstatus.h in the common driver overwrites
+*		     the xstatus.h of the standalone BSP during the
+*		     libgen.
+* 

+*
+******************************************************************************/
+#ifndef XSCUTIMER_HW_H		/* prevent circular inclusions */
+#define XSCUTIMER_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device
+ * @{
+ */
+
+#define XSCUTIMER_LOAD_OFFSET		0x00 /**< Timer Load Register */
+#define XSCUTIMER_COUNTER_OFFSET	0x04 /**< Timer Counter Register */
+#define XSCUTIMER_CONTROL_OFFSET	0x08 /**< Timer Control Register */
+#define XSCUTIMER_ISR_OFFSET		0x0C /**< Timer Interrupt
+						  Status Register */
+/* @} */
+
+/** @name Timer Control register
+ * This register bits control the prescaler, Intr enable,
+ * auto-reload and timer enable.
+ * @{
+ */
+
+#define XSCUTIMER_CONTROL_PRESCALER_MASK	0x0000FF00 /**< Prescaler */
+#define XSCUTIMER_CONTROL_PRESCALER_SHIFT	8
+#define XSCUTIMER_CONTROL_IRQ_ENABLE_MASK	0x00000004 /**< Intr enable */
+#define XSCUTIMER_CONTROL_AUTO_RELOAD_MASK	0x00000002 /**< Auto-reload */
+#define XSCUTIMER_CONTROL_ENABLE_MASK		0x00000001 /**< Timer enable */
+/* @} */
+
+/** @name Interrupt Status register
+ * This register indicates the Timer counter register has reached zero.
+ * @{
+ */
+
+#define XSCUTIMER_ISR_EVENT_FLAG_MASK		0x00000001 /**< Event flag */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param	BaseAddr is the base address of the scu timer.
+* @param	Value is the count to be loaded in to the load register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_SetLoadReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetLoadReg(BaseAddr, Value)				\
+	XScuTimer_WriteReg(BaseAddr, XSCUTIMER_LOAD_OFFSET, Value)
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer load register value.
+*
+* @param	BaseAddr is the base address of the scu timer.
+*
+* @return	Contents of the timer load register.
+*
+* @note		C-style signature:
+*		u32 XScuTimer_GetLoadReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetLoadReg(BaseAddr)					\
+	XScuTimer_ReadReg(BaseAddr, XSCUTIMER_LOAD_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer counter register.
+*
+* @param	BaseAddr is the base address of the scu timer.
+* @param	Value is the count to be loaded in to the counter register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_SetCounterReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetCounterReg(BaseAddr, Value)			\
+	XScuTimer_WriteReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET, Value)
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value.
+*
+* @param	BaseAddr is the base address of the scu timer.
+*
+* @return	Contents of the timer counter register.
+*
+* @note		C-style signature:
+		u32 XScuTimer_GetCounterReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetCounterReg(BaseAddr)				\
+	XScuTimer_ReadReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param	BaseAddr is the base address of the scu timer.
+* @param	Value is the count to be loaded in to the load register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_SetControlReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetControlReg(BaseAddr, Value)			\
+	XScuTimer_WriteReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET, Value)
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer load register value.
+*
+* @param	BaseAddr is the base address of the scu timer.
+*
+* @return	Contents of the timer load register.
+*
+* @note		C-style signature:
+		u32 XScuTimer_GetControlReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetControlReg(BaseAddr)				\
+	XScuTimer_ReadReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer counter register.
+*
+* @param	BaseAddr is the base address of the scu timer.
+* @param	Value is the count to be loaded in to the counter register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_SetIntrReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetIntrReg(BaseAddr, Value)				\
+	XScuTimer_WriteReg(BaseAddr, XSCUTIMER_ISR_OFFSET, Value)
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value.
+*
+* @param	BaseAddr is the base address of the scu timer.
+*
+* @return	Contents of the timer counter register.
+*
+* @note		C-style signature:
+		u32 XScuTimer_GetIntrReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetIntrReg(BaseAddr)					\
+	XScuTimer_ReadReg(BaseAddr, XSCUTIMER_ISR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Read from the given Timer register.
+*
+* @param	BaseAddr is the base address of the device
+* @param	RegOffset is the register offset to be read
+*
+* @return	The 32-bit value of the register
+*
+* @note		C-style signature:
+*		u32 XScuTimer_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuTimer_ReadReg(BaseAddr, RegOffset)		\
+	Xil_In32((BaseAddr) + (RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write to the given Timer register.
+*
+* @param	BaseAddr is the base address of the device
+* @param	RegOffset is the register offset to be written
+* @param	Data is the 32-bit value to write to the register
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuTimer_WriteReg(BaseAddr, RegOffset, Data)	\
+	Xil_Out32((BaseAddr) + (RegOffset), (Data))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_0/src/xscutimer_selftest.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_0/src/xscutimer_selftest.c
new file mode 100644
index 000000000..8aedc2295
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_0/src/xscutimer_selftest.c
@@ -0,0 +1,140 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer_selftest.c
+*
+* Contains diagnostic self-test functions for the XScuTimer driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm  03/10/10 First release
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscutimer.h"
+
+/************************** Constant Definitions *****************************/
+
+#define XSCUTIMER_SELFTEST_VALUE	0xA55AF00F
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Run a self-test on the timer. This test clears the timer enable bit in
+* the control register, writes to the timer load register and verifies the
+* value read back matches the value written and restores the control register
+* and the timer load register.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return
+*		- XST_SUCCESS if self-test was successful.
+*		- XST_FAILURE if self test was not successful.
+*
+* @note		None.
+*
+******************************************************************************/
+int XScuTimer_SelfTest(XScuTimer *InstancePtr)
+{
+	u32 Register;
+	u32 CtrlOrig;
+	u32 LoadOrig;
+
+	/*
+	 * Assert to ensure the inputs are valid and the instance has been
+	 * initialized.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Save the contents of the Control Register and stop the timer.
+	 */
+	CtrlOrig = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+				  XSCUTIMER_CONTROL_OFFSET);
+	Register = CtrlOrig & ~XSCUTIMER_CONTROL_ENABLE_MASK;
+	XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+			XSCUTIMER_CONTROL_OFFSET, Register);
+
+	/*
+	 * Save the contents of the Load Register.
+	 * Load a new test value in the Load Register, read it back and
+	 * compare it with the written value.
+	 */
+	LoadOrig = XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,
+				  XSCUTIMER_LOAD_OFFSET);
+	XScuTimer_LoadTimer(InstancePtr, XSCUTIMER_SELFTEST_VALUE);
+	Register = XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,
+				  XSCUTIMER_LOAD_OFFSET);
+
+	/*
+	 * Restore the contents of the Load Register and Control Register.
+	 */
+	XScuTimer_LoadTimer(InstancePtr, LoadOrig);
+	XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+			XSCUTIMER_CONTROL_OFFSET, CtrlOrig);
+
+	/*
+	 * Return a Failure if the contents of the Load Register do not
+	 * match with the value written to it.
+	 */
+	if (Register != XSCUTIMER_SELFTEST_VALUE) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_0/src/xscutimer_sinit.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_0/src/xscutimer_sinit.c
new file mode 100644
index 000000000..65652897e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_0/src/xscutimer_sinit.c
@@ -0,0 +1,99 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscutimer_sinit.c
+*
+* This file contains method for static initialization (compile-time) of the
+* driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm  03/10/10 First release
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscutimer.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId is the unique device ID of the device being looked up.
+*
+* @return	A pointer to the configuration table entry corresponding to the
+*		given device ID, or NULL if no match is found.
+*
+* @note		None.
+*
+******************************************************************************/
+XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId)
+{
+	extern XScuTimer_Config XScuTimer_ConfigTable[];
+	XScuTimer_Config *CfgPtr = NULL;
+	int Index;
+
+	for (Index = 0; Index < XPAR_XSCUTIMER_NUM_INSTANCES; Index++) {
+		if (XScuTimer_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XScuTimer_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (CfgPtr);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_0/src/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_0/src/Makefile
new file mode 100644
index 000000000..2c783d4a7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_0/src/Makefile
@@ -0,0 +1,41 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner scuwdt_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling scuwdt"
+
+scuwdt_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: scuwdt_includes
+
+scuwdt_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_0/src/xscuwdt.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_0/src/xscuwdt.c
new file mode 100644
index 000000000..f561d8d7f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_0/src/xscuwdt.c
@@ -0,0 +1,219 @@
+/* $Id: xscuwdt.c,v 1.1.2.1 2011/01/20 04:04:40 sadanan Exp $ */
+/******************************************************************************
+*
+* (c) Copyright 2010 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt.c
+*
+* Contains the implementation of interface functions of the XScuWdt driver.
+* See xscuwdt.h for a description of the driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscuwdt.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Initialize a specific watchdog timer instance/driver. This function
+* must be called before other functions of the driver are called.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+* @param	ConfigPtr is the config structure.
+* @param	EffectiveAddress is the base address for the device. It could be
+*		a virtual address if address translation is supported in the
+*		system, otherwise it is the physical address.
+*
+* @return
+*		- XST_SUCCESS if initialization was successful.
+*		- XST_DEVICE_IS_STARTED if the device has already been started.
+*
+* @note		This function enables the watchdog mode.
+*
+******************************************************************************/
+int XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
+			 XScuWdt_Config *ConfigPtr, u32 EffectiveAddress)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * If the device is started, disallow the initialize and return a
+	 * status indicating it is started. This allows the user to stop the
+	 * device and reinitialize, but prevents a user from inadvertently
+	 * initializing.
+	 */
+	if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
+		return XST_DEVICE_IS_STARTED;
+	}
+
+	/*
+	 * Copy configuration into instance.
+	 */
+	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+
+	/*
+	 * Save the base address pointer such that the registers of the block
+	 * can be accessed and indicate it has not been started yet.
+	 */
+	InstancePtr->Config.BaseAddr = EffectiveAddress;
+	InstancePtr->IsStarted = 0;
+
+	/*
+	 * Put the watchdog timer in Watchdog mode.
+	 */
+	XScuWdt_SetWdMode(InstancePtr);
+
+	/*
+	 * Indicate the instance is ready to use, successfully initialized.
+	 */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* Start the watchdog counter of the device.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return	None.
+*
+* @note		User needs to select the appropriate mode (watchdog/timer)
+*		before using this API.
+*		See XScuWdt_SetWdMode/XScuWdt_SetTimerMode macros in
+*		xscuwdt.h.
+*
+******************************************************************************/
+void XScuWdt_Start(XScuWdt *InstancePtr)
+{
+	u32 Register;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the contents of the Control register.
+	 */
+	Register = XScuWdt_ReadReg(InstancePtr->Config.BaseAddr,
+				  XSCUWDT_CONTROL_OFFSET);
+
+	/*
+	 * Set the 'watchdog enable' bit in the register.
+	 */
+	Register |= XSCUWDT_CONTROL_WD_ENABLE_MASK;
+
+	/*
+	 * Update the Control register with the new value.
+	 */
+	XScuWdt_WriteReg(InstancePtr->Config.BaseAddr,
+			XSCUWDT_CONTROL_OFFSET, Register);
+
+	/*
+	 * Indicate that the device is started.
+	 */
+	InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
+}
+
+/****************************************************************************/
+/**
+*
+* Stop the watchdog timer.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XScuWdt_Stop(XScuWdt *InstancePtr)
+{
+	u32 Register;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the contents of the Control register.
+	 */
+	Register = XScuWdt_ReadReg(InstancePtr->Config.BaseAddr,
+				  XSCUWDT_CONTROL_OFFSET);
+
+	/*
+	 * Clear the 'watchdog enable' bit in the register.
+	 */
+	Register &= ~XSCUWDT_CONTROL_WD_ENABLE_MASK;
+
+	/*
+	 * Update the Control register with the new value.
+	 */
+	XScuWdt_WriteReg(InstancePtr->Config.BaseAddr,
+			XSCUWDT_CONTROL_OFFSET, Register);
+
+	/*
+	 * Indicate that the device is stopped.
+	 */
+	InstancePtr->IsStarted = 0;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_0/src/xscuwdt.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_0/src/xscuwdt.h
new file mode 100644
index 000000000..6ed40d0df
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_0/src/xscuwdt.h
@@ -0,0 +1,389 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt.h
+*
+* The Xilinx SCU watchdog timer driver (XScuWdt) supports the Xilinx SCU private
+* watchdog timer hardware.
+*
+* The XScuWdt driver supports the following features:
+* - Watchdog mode
+* - Timer mode
+* - Auto reload (timer mode only)
+*
+* The watchdog counter register is a down counter and starts decrementing when
+* the watchdog is started.
+* In watchdog mode, when the counter reaches 0, the Reset flag is set in the
+* Reset status register and the WDRESETREQ pin is asserted, causing a system
+* reset. The Reset flag is not reset by normal processor reset and is cleared
+* when written with a value of 1. This enables the user to differentiate a
+* normal reset and a reset caused by watchdog time-out. The user needs to call
+* XScuWdt_RestartWdt() periodically, to avoid the watchdog from being timed-out.
+*
+* The IsWdtExpired function can be used to check if the watchdog was the cause
+* of the last reset. In this situation, call Initialize then call IsWdtExpired.
+* If the result is true, watchdog timeout caused the last system reset. The
+* application then needs to clear the Reset flag.
+*
+* In timer mode, when the counter reaches 0, the Event flag is set in the
+* Interrupt status register and if interrupts are enabled, interrupt ID 30 is
+* set as pending in the interrupt distributor. The IsTimerExpired function
+* is used to check if the watchdog counter has decremented to 0 in timer mode.
+* If auto-reload mode is enabled, the Counter register is automatically reloaded
+* from the Load register.
+*
+*  Initialization and Configuration 
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Watchdog Timer.
+*
+* XScuWdt_CfgInitialize() API is used to initialize the Watchdog Timer. The
+* user needs to first call the XScuWdt_LookupConfig() API which returns
+* the Configuration structure pointer which is passed as a parameter to
+* the XScuWdt_CfgInitialize() API.
+*
+* Interrupts
+*
+* The SCU Watchdog Timer supports interrupts in Timer mode.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* Timer in interrupt mode.
+*
+*  Virtual Memory 
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+*  Threads 
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+*  Asserts 
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+*  Building the driver 
+*
+* The XScuWdt driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+* 


+*
+* NOTE:
+* The watchdog timer is not a part of the snoop control unit as indicated
+* by the prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 1.02a  sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+*		     when the xstatus.h in the common driver overwrites
+*		     the xstatus.h of the standalone BSP during the
+*		     libgen.
+* 

+*
+******************************************************************************/
+#ifndef XSCUWDT_H		/* prevent circular inclusions */
+#define XSCUWDT_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xscuwdt_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID of device */
+	u32 BaseAddr;		/**< Base address of the device */
+} XScuWdt_Config;
+
+/**
+ * The XScuWdt driver instance data. The user is required to allocate a
+ * variable of this type for every watchdog/timer device in the system.
+ * A pointer to a variable of this type is then passed to the driver API
+ * functions.
+ */
+typedef struct {
+	XScuWdt_Config Config;/**< Hardware Configuration */
+	u32 IsReady;		/**< Device is initialized and ready */
+	u32 IsStarted;		/**< Device watchdog timer is running */
+} XScuWdt;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+/****************************************************************************/
+/**
+*
+* This function is used to check if the watchdog has timed-out and the last
+* reset was caused by the watchdog reset.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return
+*		- TRUE if the watchdog has expired.
+*		- FALSE if the watchdog has not expired.
+*
+* @note		C-style signature:
+*		int XScuWdt_IsWdtExpired(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_IsWdtExpired(InstancePtr)				\
+	((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,		\
+			  XSCUWDT_RST_STS_OFFSET) &			\
+	 XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* This function is used to check if the watchdog counter has reached 0 in timer
+* mode.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return
+*		- TRUE if the watchdog has expired.
+*		- FALSE if the watchdog has not expired.
+*
+* @note		C-style signature:
+*		int XScuWdt_IsTimerExpired(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_IsTimerExpired(InstancePtr)				\
+	((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,		\
+			  XSCUWDT_ISR_OFFSET) &				\
+	 XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* Re-start the watchdog timer. This macro will read the watchdog load register
+* and write the same value to load register to update the counter register.
+* An application needs to call this function periodically to keep the watchdog
+* from asserting the WDRESETREQ reset request output pin.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuWdt_RestartWdt(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_RestartWdt(InstancePtr)					 \
+	XScuWdt_LoadWdt(InstancePtr,					 \
+			(XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+					 XSCUWDT_LOAD_OFFSET)))
+
+/****************************************************************************/
+/**
+*
+* Write to the watchdog timer load register. This will also update the
+* watchdog counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+* @param	Value is the value to be written to the Watchdog Load register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuWdt_LoadWdt(XScuWdt *InstancePtr, u32 Value)
+*
+******************************************************************************/
+#define XScuWdt_LoadWdt(InstancePtr, Value)				\
+	XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUWDT_LOAD_OFFSET, Value)
+
+/****************************************************************************/
+/**
+*
+* Put the watchdog timer in Watchdog mode by setting the WD mode bit of the
+* Watchdog control register.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuWdt_SetWdMode(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_SetWdMode(InstancePtr)					  \
+	XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr,		  \
+			 XSCUWDT_CONTROL_OFFSET,			  \
+			 (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+			  XSCUWDT_CONTROL_OFFSET) |			  \
+			  XSCUWDT_CONTROL_WD_MODE_MASK))
+
+/****************************************************************************/
+/**
+*
+* Put the watchdog timer in Timer mode by writing 0x12345678 and 0x87654321
+* successively to the Watchdog Disable Register.
+* The software must write 0x12345678 and 0x87654321 successively to the
+* Watchdog Disable Register so that the watchdog mode bit in the Watchdog
+* Control Register is set to zero.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuWdt_SetTimerMode(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_SetTimerMode(InstancePtr)				\
+{									\
+	XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUWDT_DISABLE_OFFSET,				\
+			XSCUWDT_DISABLE_VALUE1);			\
+	XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUWDT_DISABLE_OFFSET,				\
+			XSCUWDT_DISABLE_VALUE2);			\
+}
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the watchdog control register.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return	Contents of the watchdog control register.
+*
+* @note		C-style signature:
+		u32 XScuWdt_GetControlReg(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_GetControlReg(InstancePtr)				\
+	XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,			\
+			XSCUWDT_CONTROL_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the watchdog control register.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+* @param	ControlReg is the value to be written to the watchdog control
+*		register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+		void XScuWdt_SetControlReg(XScuWdt *InstancePtr, u32 ControlReg)
+*
+******************************************************************************/
+#define XScuWdt_SetControlReg(InstancePtr, ControlReg)			\
+	XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			 XSCUWDT_CONTROL_OFFSET, ControlReg)
+
+/****************************************************************************/
+/**
+*
+* Enable auto-reload mode.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuWdt_EnableAutoReload(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_EnableAutoReload(InstancePtr)				\
+	XScuWdt_SetControlReg((InstancePtr),				\
+			      (XScuWdt_GetControlReg(InstancePtr) |	\
+			      XSCUWDT_CONTROL_AUTO_RELOAD_MASK))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xscuwdt_sinit.c.
+ */
+XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xscuwdt_selftest.c
+ */
+int XScuWdt_SelfTest(XScuWdt *InstancePtr);
+
+/*
+ * Interface functions in xscuwdt.c
+ */
+int XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
+			  XScuWdt_Config *ConfigPtr, u32 EffectiveAddress);
+
+void XScuWdt_Start(XScuWdt *InstancePtr);
+
+void XScuWdt_Stop(XScuWdt *InstancePtr);
+
+/*
+ * Self-test function in xwdttb_selftest.c.
+ */
+int XScuWdt_SelfTest(XScuWdt *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_0/src/xscuwdt_g.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_0/src/xscuwdt_g.c
new file mode 100644
index 000000000..8d376f56a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_0/src/xscuwdt_g.c
@@ -0,0 +1,31 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSM.
+* Version: 
+* DO NOT EDIT.
+*
+*  v (64-bit)
+SW Build (by ) on 
+Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xscuwdt.h"
+
+/*
+* The configuration table for devices
+*/
+
+XScuWdt_Config XScuWdt_ConfigTable[] =
+{
+	{
+		XPAR_PS7_SCUWDT_0_DEVICE_ID,
+		XPAR_PS7_SCUWDT_0_BASEADDR
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_0/src/xscuwdt_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_0/src/xscuwdt_hw.h
new file mode 100644
index 000000000..9bf23046d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_0/src/xscuwdt_hw.h
@@ -0,0 +1,187 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt_hw.h
+*
+* This file contains the hardware interface to the Xilinx SCU private Watch Dog
+* Timer (XSCUWDT).
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 1.01a bss 02/27/12 Updated the register offsets to start at 0x0 instead
+*                    of 0x20 as the base address obtained from the tools
+*		     starts at 0x20.
+* 1.02a  sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+*		     when the xstatus.h in the common driver overwrites
+*		     the xstatus.h of the standalone BSP during the
+*		     libgen.
+* 

+*
+******************************************************************************/
+#ifndef XSCUWDT_HW_H		/* prevent circular inclusions */
+#define XSCUWDT_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device. The WDT registers start at
+ * an offset 0x20
+ * @{
+ */
+
+#define XSCUWDT_LOAD_OFFSET	0x00 /**< Watchdog Load Register */
+#define XSCUWDT_COUNTER_OFFSET	0x04 /**< Watchdog Counter Register */
+#define XSCUWDT_CONTROL_OFFSET	0x08 /**< Watchdog Control Register */
+#define XSCUWDT_ISR_OFFSET	0x0C /**< Watchdog Interrupt Status Register */
+#define XSCUWDT_RST_STS_OFFSET	0x10 /**< Watchdog Reset Status Register */
+#define XSCUWDT_DISABLE_OFFSET	0x14 /**< Watchdog Disable Register */
+/* @} */
+
+/** @name Watchdog Control register
+ * This register bits control the prescaler, WD/Timer mode, Intr enable,
+ * auto-reload, watchdog enable.
+ * @{
+ */
+
+#define XSCUWDT_CONTROL_PRESCALER_MASK	 0x0000FF00 /**< Prescaler */
+#define XSCUWDT_CONTROL_PRESCALER_SHIFT	 8
+#define XSCUWDT_CONTROL_WD_MODE_MASK	 0x00000008 /**< Watchdog/Timer mode */
+#define XSCUWDT_CONTROL_IT_ENABLE_MASK	 0x00000004 /**< Intr enable (in
+							 timer mode) */
+#define XSCUWDT_CONTROL_AUTO_RELOAD_MASK 0x00000002 /**< Auto-reload (in
+							 timer mode) */
+#define XSCUWDT_CONTROL_WD_ENABLE_MASK	 0x00000001 /**< Watchdog enable */
+/* @} */
+
+/** @name Interrupt Status register
+ * This register indicates the Counter register has reached zero in Counter
+ * mode.
+ * @{
+ */
+
+#define XSCUWDT_ISR_EVENT_FLAG_MASK	0x00000001 /**< Event flag */
+/*@}*/
+
+/** @name Reset Status register
+ * This register indicates the Counter register has reached zero in Watchdog
+ * mode and a reset request is sent.
+ * @{
+ */
+
+#define XSCUWDT_RST_STS_RESET_FLAG_MASK	0x00000001 /**< Time out occured */
+/*@}*/
+
+/** @name Disable register
+ * This register is used to switch from watchdog mode to timer mode.
+ * The software must write 0x12345678 and 0x87654321 successively to the
+ * Watchdog Disable Register so that the watchdog mode bit in the Watchdog
+ * Control Register is set to zero.
+ * @{
+ */
+#define XSCUWDT_DISABLE_VALUE1		0x12345678 /**< Watchdog mode disable
+							value 1 */
+#define XSCUWDT_DISABLE_VALUE2		0x87654321 /**< Watchdog mode disable
+							value 2 */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param	BaseAddr is the base address of the device
+* @param	RegOffset is the register offset to be read
+*
+* @return	The 32-bit value of the register
+*
+* @note		C-style signature:
+*		u32 XScuWdt_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuWdt_ReadReg(BaseAddr, RegOffset)		\
+	Xil_In32((BaseAddr) + (RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param	BaseAddr is the base address of the device
+* @param	RegOffset is the register offset to be written
+* @param	Data is the 32-bit value to write to the register
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuWdt_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuWdt_WriteReg(BaseAddr, RegOffset, Data)	\
+	Xil_Out32((BaseAddr) + (RegOffset), (Data))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_0/src/xscuwdt_selftest.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_0/src/xscuwdt_selftest.c
new file mode 100644
index 000000000..8afd5a975
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_0/src/xscuwdt_selftest.c
@@ -0,0 +1,132 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt_selftest.c
+*
+* Contains diagnostic self-test functions for the XScuWdt driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscuwdt.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Run a self-test on the WDT. This test stops the watchdog, writes a value to
+* the watchdog load register, starts the watchdog and verifies that the value
+* read from the counter register is less that the value written to the load
+* register. It then restores the control register and the watchdog load
+* register.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return
+*		- XST_SUCCESS if self-test was successful.
+*		- XST_FAILURE if the WDT is not decrementing.
+*
+* @note		None.
+*
+******************************************************************************/
+int XScuWdt_SelfTest(XScuWdt *InstancePtr)
+{
+	u32 Register;
+	u32 CtrlOrig;
+	u32 LoadOrig;
+
+	/*
+	 * Assert to ensure the inputs are valid and the instance has been
+	 * initialized.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Stop the watchdog timer.
+	 */
+	CtrlOrig = XScuWdt_GetControlReg(InstancePtr);
+	XScuWdt_SetControlReg(InstancePtr,
+			      CtrlOrig & ~XSCUWDT_CONTROL_WD_ENABLE_MASK);
+
+	LoadOrig = XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,
+				   XSCUWDT_LOAD_OFFSET);
+	XScuWdt_LoadWdt(InstancePtr, 0xFFFFFFFF);
+
+	/*
+	 * Start the watchdog timer and check if the watchdog counter is
+	 * decrementing.
+	 */
+	XScuWdt_SetControlReg(InstancePtr,
+			      CtrlOrig | XSCUWDT_CONTROL_WD_ENABLE_MASK);
+
+	Register = XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,
+				   XSCUWDT_COUNTER_OFFSET);
+
+	XScuWdt_LoadWdt(InstancePtr, LoadOrig);
+	XScuWdt_SetControlReg(InstancePtr, CtrlOrig);
+
+	if (Register == 0xFFFFFFFF) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_0/src/xscuwdt_sinit.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_0/src/xscuwdt_sinit.c
new file mode 100644
index 000000000..c286994cd
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_0/src/xscuwdt_sinit.c
@@ -0,0 +1,99 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscuwdt_sinit.c
+*
+* This file contains method for static initialization (compile-time) of the
+* driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscuwdt.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId is the unique device ID of the device being looked up.
+*
+* @return	A pointer to the configuration table entry corresponding to the
+*		given device ID, or NULL if no match is found.
+*
+* @note		None.
+*
+******************************************************************************/
+XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId)
+{
+	extern XScuWdt_Config XScuWdt_ConfigTable[];
+	XScuWdt_Config *CfgPtr = NULL;
+	int Index;
+
+	for (Index = 0; Index < XPAR_XSCUWDT_NUM_INSTANCES; Index++) {
+		if (XScuWdt_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XScuWdt_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (CfgPtr);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_1/src/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_1/src/Makefile
new file mode 100644
index 000000000..0191c3b88
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_1/src/Makefile
@@ -0,0 +1,41 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xsdps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling sdps"
+
+xsdps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xsdps_includes
+
+xsdps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_1/src/xsdps.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_1/src/xsdps.c
new file mode 100644
index 000000000..34c5c08a2
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_1/src/xsdps.c
@@ -0,0 +1,1109 @@
+/******************************************************************************
+*
+* (c) Copyright 2013-2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps.c
+*
+* Contains the interface functions of the XSdPs driver.
+* See xsdps.h for a detailed description of the device and driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.0   hk     12/13/13 Added check for arm to use sleep.h and its API's
+* 2.1   hk     04/18/14 Add sleep for microblaze designs. CR# 781117.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xsdps.h"
+/*
+ * The header sleep.h and API usleep() can only be used with an arm design.
+ * MB_Sleep() is used for microblaze design.
+ */
+#ifdef __arm__
+
+#include "sleep.h"
+
+#endif
+
+#ifdef __MICROBLAZE__
+
+#include "microblaze_sleep.h"
+
+#endif
+
+/************************** Constant Definitions *****************************/
+#define XSDPS_CMD8_VOL_PATTERN	0x1AA
+#define XSDPS_RESPOCR_READY	0x80000000
+#define XSDPS_ACMD41_HCS	0x40000000
+#define XSDPS_ACMD41_3V3	0x00300000
+#define XSDPS_CMD1_HIGH_VOL	0x00FF8000
+#define XSDPS_CMD1_DUAL_VOL	0x00FF8010
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XSDPS_INIT_DELAY	2000
+
+/************************** Function Prototypes ******************************/
+u32 XSdPs_FrameCmd(u32 Cmd);
+int XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
+void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
+
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XSdPs instance such that the driver is ready to use.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	ConfigPtr is a reference to a structure containing information
+*		about a specific SD device. This function initializes an
+*		InstancePtr object for a specific device specified by the
+*		contents of Config.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, use
+*		ConfigPtr->Config.BaseAddress for this device.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_DEVICE_IS_STARTED if the device is already started.
+*		It must be stopped to re-initialize.
+*
+* @note		This function initializes the host controller.
+*		Initial clock of 400KHz is set.
+*		Voltage of 3.3V is selected as that is supported by host.
+*		Interrupts status is enabled and signal disabled by default.
+*		Default data direction is card to host and
+*		32 bit ADMA2 is selected. Defualt Block size is 512 bytes.
+*
+******************************************************************************/
+int XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+	u32 ClockReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * Set some default values.
+	 */
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+	InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	/*
+	 * "Software reset for all" is initiated
+	 */
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
+			XSDPS_SWRST_ALL_MASK);
+
+	/*
+	 * Proceed with initialization only after reset is complete
+	 */
+	while (XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_SW_RST_OFFSET) & XSDPS_SWRST_ALL_MASK);
+
+	/*
+	 * Read capabilities register and update it in Instance pointer.
+	 * It is sufficient to read this once on power on.
+	 */
+	InstancePtr->Host_Caps = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XSDPS_CAPS_OFFSET);
+
+	/*
+	 * SD clock frequency divider 128
+	 * Enable the internal clock
+	 */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+		XSDPS_CLK_CTRL_OFFSET,
+		XSDPS_CC_SDCLK_FREQ_D128_MASK | XSDPS_CC_INT_CLK_EN_MASK);
+
+	/*
+	 * Wait for internal clock to stabilize
+	 */
+	while ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+		XSDPS_CLK_CTRL_OFFSET) & XSDPS_CC_INT_CLK_STABLE_MASK) == 0);
+
+	/*
+	 * Enable SD clock
+	 */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+		XSDPS_CLK_CTRL_OFFSET, ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
+
+	/*
+	 * Select voltage and enable bus power.
+	 */
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_POWER_CTRL_OFFSET,
+			XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK);
+
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL1_OFFSET,
+			XSDPS_HC_DMA_ADMA2_32_MASK);
+
+	/*
+	 * Enable all interrupt status except card interrupt initially
+	 */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_EN_OFFSET,
+			XSDPS_NORM_INTR_ALL_MASK & (~XSDPS_INTR_CARD_MASK));
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_ERR_INTR_STS_EN_OFFSET,
+			XSDPS_ERROR_INTR_ALL_MASK);
+
+	/*
+	 * Disable all interrupt signals by default.
+	 */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_SIG_EN_OFFSET, 0x0);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_ERR_INTR_SIG_EN_OFFSET, 0x0);
+
+	/*
+	 * Transfer mode register - default value
+	 * DMA enabled, block count enabled, data direction card to host(read)
+	 */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_DMA_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK |
+			XSDPS_TM_DAT_DIR_SEL_MASK);
+
+	/*
+	 * Set block size to 512 by default
+	 */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET, XSDPS_BLK_SIZE_512_MASK);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* SD initialization is done in this function
+*
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because
+* 			a) SD is already initialized
+* 			b) There is no card inserted
+* 			c) One of the steps (commands) in the
+			   initialization cycle failed
+*
+* @note		This function initializes the SD card by following its
+*		initialization and identification state diagram.
+*		CMD0 is sent to reset card.
+*		CMD8 and ACDM41 are sent to identify voltage and
+*		high capacity support
+*		CMD2 and CMD3 are sent to obtain Card ID and
+*		Relative card address respectively.
+*		CMD9 is sent to read the card specific data.
+*
+******************************************************************************/
+int XSdPs_SdCardInitialize(XSdPs *InstancePtr)
+{
+	u32 PresentStateReg;
+	u32 Status;
+	u32 RespOCR = 0x0;
+	u32 CSD[4];
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Check the present state register to make sure
+	 * card is inserted and detected by host controller
+	 */
+	PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_PRES_STATE_OFFSET);
+	if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0)	{
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * 74 CLK delay after card is powered up, before the first command.
+	 */
+
+#ifdef __arm__
+
+	usleep(XSDPS_INIT_DELAY);
+
+#endif
+
+#ifdef __MICROBLAZE__
+
+	/* 2 msec delay */
+	MB_Sleep(2);
+
+#endif
+
+	/*
+	 * CMD0 no response expected
+	 */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0, 0);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * CMD8; response expected
+	 * 0x1AA - Supply Voltage 2.7 - 3.6V and AA is pattern
+	 */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD8,
+			XSDPS_CMD8_VOL_PATTERN, 0);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XSDPS_RESP0_OFFSET);
+	if (RespOCR != XSDPS_CMD8_VOL_PATTERN) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	RespOCR = 0;
+	/*
+	 * Send ACMD41 while card is still busy with power up
+	 */
+	while ((RespOCR & XSDPS_RESPOCR_READY) == 0) {
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD55, 0, 0);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/*
+		 * 0x40300000 - Host High Capacity support & 3.3V window
+		 */
+		Status = XSdPs_CmdTransfer(InstancePtr, ACMD41,
+				(XSDPS_ACMD41_HCS | XSDPS_ACMD41_3V3), 0);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/*
+		 * Response with card capacity
+		 */
+		RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_RESP0_OFFSET);
+
+	}
+
+	/*
+	 * Update HCS support flag based on card capacity response
+	 */
+	if (RespOCR & XSDPS_ACMD41_HCS)
+		InstancePtr->HCS = 1;
+
+	/*
+	 * CMD2 for Card ID
+	 */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0, 0);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	InstancePtr->CardID[0] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+	InstancePtr->CardID[1] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP1_OFFSET);
+	InstancePtr->CardID[2] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP2_OFFSET);
+	InstancePtr->CardID[3] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP3_OFFSET);
+
+	while (InstancePtr->RelCardAddr == 0) {
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD3, 0, 0);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/*
+		 * Relative card address is stored as the upper 16 bits
+		 * This is to avoid shifting when sending commands
+		 */
+		InstancePtr->RelCardAddr =
+				XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_RESP0_OFFSET) & 0xFFFF0000;
+	}
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Card specific data is read.
+	 * Currently not used for any operation.
+	 */
+	CSD[0] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+	CSD[1] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP1_OFFSET);
+	CSD[2] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP2_OFFSET);
+	CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP3_OFFSET);
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+	return Status;
+
+}
+
+/*****************************************************************************/
+/**
+* This function does SD command generation.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Cmd is the command to be sent.
+* @param	Arg is the argument to be sent along with the command.
+* 		This could be address or any other information
+* @param	BlkCnt - Block count passed by the user.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because another transfer
+* 			is in progress or command or data inhibit is set
+*
+******************************************************************************/
+int XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt)
+{
+	u32 PresentStateReg;
+	u32 CommandReg;
+	u32 StatusReg;
+	u32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Check the command inhibit to make sure no other
+	 * command transfer is in progress
+	 */
+	PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_PRES_STATE_OFFSET);
+	if (PresentStateReg & XSDPS_PSR_INHIBIT_CMD_MASK) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Write block count register
+	 */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_CNT_OFFSET, BlkCnt);
+
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_TIMEOUT_CTRL_OFFSET, 0xE);
+
+	/*
+	 * Write argument register
+	 */
+	XSdPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XSDPS_ARGMT_OFFSET, Arg);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
+	/*
+	 * Command register is set to trigger transfer of command
+	 */
+	CommandReg = XSdPs_FrameCmd(Cmd);
+
+	/*
+	 * Mask to avoid writing to reserved bits 31-30
+	 * This is necessary because 0x80000000 is used  by this software to
+	 * distinguish between ACMD and CMD of same number
+	 */
+	CommandReg = CommandReg & 0x3FFF;
+
+	/*
+	 * Check for data inhibit in case of command using DAT lines
+	 */
+	PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_PRES_STATE_OFFSET);
+	if ((PresentStateReg & XSDPS_PSR_INHIBIT_CMD_MASK) &&
+			(CommandReg & XSDPS_DAT_PRESENT_SEL_MASK)) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CMD_OFFSET,
+			CommandReg);
+
+	/*
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+
+		if (StatusReg & XSDPS_INTR_ERR_MASK) {
+
+			/*
+			 * Write to clear error bits
+			 */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while((StatusReg & XSDPS_INTR_CC_MASK) == 0);
+	/*
+	 * Write to clear bit
+	 */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET,
+			XSDPS_INTR_CC_MASK);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+* This function frames the Command register for a particular command.
+* Note that this generates only the command register value i.e.
+* the upper 16 bits of the transfer mode and command register.
+* This value is already shifted to be upper 16 bits and can be directly
+* OR'ed with transfer mode register value.
+*
+* @param	Command to be sent.
+*
+* @return	Command register value complete with response type and
+* 		data, CRC and index related flags.
+*
+******************************************************************************/
+u32 XSdPs_FrameCmd(u32 Cmd)
+{
+		u32 RetVal;
+
+		RetVal = Cmd;
+
+		switch(Cmd) {
+		case CMD0:
+			RetVal |= RESP_NONE;
+		break;
+		case CMD1:
+			RetVal |= RESP_R3;
+		break;
+		case CMD2:
+			RetVal |= RESP_R2;
+		break;
+		case CMD3:
+			RetVal |= RESP_R6;
+		break;
+		case CMD4:
+			RetVal |= RESP_NONE;
+			break;
+		case CMD5:
+			RetVal |= RESP_R1B;
+		break;
+
+#ifndef MMC_CARD
+		case CMD6:
+			RetVal |= RESP_R1 | XSDPS_DAT_PRESENT_SEL_MASK;
+			break;
+#else
+		case CMD6:
+			RetVal |= RESP_R1B;
+			break;
+#endif
+
+		case ACMD6:
+			RetVal |= RESP_R1;
+		break;
+		case CMD7:
+			RetVal |= RESP_R1;
+		break;
+
+#ifndef MMC_CARD
+		case CMD8:
+			RetVal |= RESP_R1;
+			break;
+#else
+		case CMD8:
+			RetVal |= RESP_R1 | XSDPS_DAT_PRESENT_SEL_MASK;
+			break;
+#endif
+
+		case CMD9:
+			RetVal |= RESP_R2;
+		break;
+		case CMD10:
+		case CMD12:
+		case ACMD13:
+		case CMD16:
+			RetVal |= RESP_R1;
+		break;
+		case CMD17:
+		case CMD18:
+			RetVal |= RESP_R1 | XSDPS_DAT_PRESENT_SEL_MASK;
+		break;
+		case CMD23:
+		case ACMD23:
+		case CMD24:
+		case CMD25:
+			RetVal |= RESP_R1 | XSDPS_DAT_PRESENT_SEL_MASK;
+		case ACMD41:
+			RetVal |= RESP_R3;
+		break;
+		case ACMD42:
+			RetVal |= RESP_R1;
+		break;
+		case ACMD51:
+			RetVal |= RESP_R1 | XSDPS_DAT_PRESENT_SEL_MASK;
+		break;
+		case CMD52:
+		case CMD55:
+			RetVal |= RESP_R1;
+		break;
+		case CMD58:
+		break;
+		}
+
+		return RetVal;
+}
+
+/*****************************************************************************/
+/**
+* This function performs SD read in polled mode.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Arg is the address passed by the user that is to be sent as
+* 		argument along with the command.
+* @param	BlkCnt - Block count passed by the user.
+* @param	Buff - Pointer to the data buffer for a DMA transfer.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because another transfer
+* 		is in progress or command or data inhibit is set
+*
+******************************************************************************/
+int XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff)
+{
+	u32 Status;
+	u32 PresentStateReg;
+	u32 StatusReg;
+
+	/*
+	 * Check status to ensure card is initialized
+	 */
+	PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_PRES_STATE_OFFSET);
+	if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Set block size to 512 if not already set
+	 */
+	if( XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) {
+		Status = XSdPs_SetBlkSize(InstancePtr,
+			XSDPS_BLK_SIZE_512_MASK);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	}
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_AUTO_CMD12_EN_MASK |
+			XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DAT_DIR_SEL_MASK |
+			XSDPS_TM_DMA_EN_MASK | XSDPS_TM_MUL_SIN_BLK_SEL_MASK);
+
+	/*
+	 * Send block read command
+	 */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD18, Arg, BlkCnt);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if (StatusReg & XSDPS_INTR_ERR_MASK) {
+			/*
+			 * Write to clear error bits
+			 */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while((StatusReg & XSDPS_INTR_TC_MASK) == 0);
+
+	/*
+	 * Write to clear bit
+	 */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+	Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+}
+
+/*****************************************************************************/
+/**
+* This function performs SD write in polled mode.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Arg is the address passed by the user that is to be sent as
+* 		argument along with the command.
+* @param	BlkCnt - Block count passed by the user.
+* @param	Buff - Pointer to the data buffer for a DMA transfer.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because another transfer
+* 		is in progress or command or data inhibit is set
+*
+******************************************************************************/
+int XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff)
+{
+	u32 Status;
+	u32 PresentStateReg;
+	u32 StatusReg;
+
+	/*
+	 * Check status to ensure card is initialized
+	 */
+	PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_PRES_STATE_OFFSET);
+	if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Set block size to 512 if not already set
+	 */
+	if( XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) {
+		Status = XSdPs_SetBlkSize(InstancePtr,
+			XSDPS_BLK_SIZE_512_MASK);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+	}
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_AUTO_CMD12_EN_MASK |
+			XSDPS_TM_BLK_CNT_EN_MASK |
+			XSDPS_TM_MUL_SIN_BLK_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
+
+	/*
+	 * Send block write command
+	 */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD25, Arg, BlkCnt);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if (StatusReg & XSDPS_INTR_ERR_MASK) {
+			/*
+			 * Write to clear error bits
+			 */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while((StatusReg & XSDPS_INTR_TC_MASK) == 0);
+
+	/*
+	 * Write to clear bit
+	 */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Selects card and sets default block size
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+int XSdPs_Select_Card (XSdPs *InstancePtr)
+{
+	u32 Status = 0;
+
+	/*
+	 * Send CMD7 - Select card
+	 */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD7,
+			InstancePtr->RelCardAddr, 0);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	/*
+	 * Set default block size
+	 */
+	Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to setup ADMA2 descriptor table
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	BlkCnt - block count.
+* @param	Buff pointer to data buffer.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff)
+{
+	u32 TotalDescLines = 0;
+	u32 DescNum = 0;
+	u32 BlkSize = 0;
+
+	/*
+	 * Setup ADMA2 - Write descriptor table and point ADMA SAR to it
+	 */
+	BlkSize = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_BLK_SIZE_OFFSET);
+	BlkSize = BlkSize & XSDPS_BLK_SIZE_MASK;
+
+	if((BlkCnt*BlkSize) < XSDPS_DESC_MAX_LENGTH) {
+
+		TotalDescLines = 1;
+
+	}else {
+
+		TotalDescLines = ((BlkCnt*BlkSize) / XSDPS_DESC_MAX_LENGTH);
+		if ((BlkCnt * BlkSize) % XSDPS_DESC_MAX_LENGTH)
+			TotalDescLines += 1;
+
+	}
+
+	for (DescNum = 0; DescNum < (TotalDescLines-1); DescNum++) {
+		InstancePtr->Adma2_DescrTbl[DescNum].Address =
+				(u32)(Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
+		InstancePtr->Adma2_DescrTbl[DescNum].Attribute =
+				XSDPS_DESC_TRAN | XSDPS_DESC_VALID;
+		/*
+		 * This will write '0' to length field which indicates 65536
+		 */
+		InstancePtr->Adma2_DescrTbl[DescNum].Length =
+				(u16)XSDPS_DESC_MAX_LENGTH;
+	}
+
+	InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Address =
+			(u32)(Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
+
+	InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Attribute =
+			XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID;
+
+	InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Length =
+			(BlkCnt*BlkSize) - (DescNum*XSDPS_DESC_MAX_LENGTH);
+
+
+	XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET,
+			(u32)&(InstancePtr->Adma2_DescrTbl[0]));
+
+}
+
+/*****************************************************************************/
+/**
+* Mmc initialization is done in this function
+*
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because
+* 			a) MMC is already initialized
+* 			b) There is no card inserted
+* 			c) One of the steps (commands) in the initialization
+*			   cycle failed
+* @note 	This function initializes the SD card by following its
+*		initialization and identification state diagram.
+*		CMD0 is sent to reset card.
+*		CMD1 sent to identify voltage and high capacity support
+*		CMD2 and CMD3 are sent to obtain Card ID and
+*		Relative card address respectively.
+*		CMD9 is sent to read the card specific data.
+*
+******************************************************************************/
+int XSdPs_MmcCardInitialize(XSdPs *InstancePtr)
+{
+	u32 PresentStateReg;
+	u32 Status;
+	u32 RespOCR = 0x0;
+	u32 CSD[4];
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Check the present state register to make sure
+	 * card is inserted and detected by host controller
+	 */
+	PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_PRES_STATE_OFFSET);
+	if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0)	{
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * 74 CLK delay after card is powered up, before the first command.
+	 */
+
+#ifdef __arm__
+
+	usleep(XSDPS_INIT_DELAY);
+
+#endif
+
+#ifdef __MICROBLAZE__
+
+	/* 2 msec delay */
+	MB_Sleep(2);
+
+#endif
+
+	/*
+	 * CMD0 no response expected
+	 */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0, 0);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	RespOCR = 0;
+	/*
+	 * Send CMD1 while card is still busy with power up
+	 */
+	while ((RespOCR & XSDPS_RESPOCR_READY) == 0) {
+
+		/*
+		 * Host High Capacity support & High volage window
+		 */
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD1,
+				XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/*
+		 * Response with card capacity
+		 */
+		RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_RESP0_OFFSET);
+
+	}
+
+	/*
+	 * Update HCS support flag based on card capacity response
+	 */
+	if (RespOCR & XSDPS_ACMD41_HCS)
+		InstancePtr->HCS = 1;
+
+	/*
+	 * CMD2 for Card ID
+	 */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0, 0);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	InstancePtr->CardID[0] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+	InstancePtr->CardID[1] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP1_OFFSET);
+	InstancePtr->CardID[2] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP2_OFFSET);
+	InstancePtr->CardID[3] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP3_OFFSET);
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD3, 0, 0);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Relative card address is stored as the upper 16 bits
+	 * This is to avoid shifting when sending commands
+	 */
+	InstancePtr->RelCardAddr =
+			XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_RESP0_OFFSET) & 0xFFFF0000;
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Card specific data is read.
+	 * Currently not used for any operation.
+	 */
+	CSD[0] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+	CSD[1] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP1_OFFSET);
+	CSD[2] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP2_OFFSET);
+	CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP3_OFFSET);
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+	return Status;
+
+}
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_1/src/xsdps.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_1/src/xsdps.h
new file mode 100644
index 000000000..e9f3e2ecf
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_1/src/xsdps.h
@@ -0,0 +1,192 @@
+/******************************************************************************
+*
+* (c) Copyright 2013-2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps.h
+*
+* This file contains the implementation of XSdPs driver.
+* This driver is used initialize read from and write to the SD card.
+* Features such as switching bus width to 4-bit and switching to high speed,
+* changing clock frequency, block size etc. are supported.
+* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however
+* is done using 1-bit bus width and 400KHz clock frequency.
+* SD commands are classified as broadcast and addressed. Commands can be
+* those with response only (using only command line) or
+* response + data (using command and data lines).
+* Only one command can be sent at a time. During a data transfer however,
+* when dsta lines are in use, certain commands (which use only the command
+* line) can be sent, most often to obtain status.
+* This driver does not support multi card slots at present.
+*
+* Intialization:
+* This includes initialization on the host controller side to select
+* clock frequency, bus power and default transfer related parameters.
+* The default voltage is 3.3V.
+* On the SD card side, the initialization and identification state diagram is
+* implemented. This resets the card, gives it a unique address/ID and
+* identifies key card related specifications.
+*
+* Data transfer:
+* The SD card is put in tranfer state to read from or write to it.
+* The default block size is 512 bytes and if supported,
+* default bus width is 4-bit and bus speed is High speed.
+* The read and write functions are implemented in polled mode using ADMA2.
+*
+* At any point, when key parameters such as block size or
+* clock/speed or bus width are modified, this driver takes care of
+* maintaining the same selection on host and card.
+* All error bits in host controller are monitored by the driver and in the
+* event one of them is set, driver will clear the interrupt status and
+* communicate failure to the upper layer.
+*
+* File system use:
+* This driver can be used with xilffs library to read and write files to SD.
+* (Please refer to procedure in diskio.c). The file system read/write example
+* in polled mode can used for reference.
+*
+* There is no example for using SD driver without file system at present.
+* However, the driver can be used without the file system. The glue layer
+* in filesytem can be used as reference for the same. The block count
+* passed to the read/write function in one call is limited by the ADMA2
+* descriptor table and hence care will have to be taken to call read/write
+* API's in a loop for large file sizes.
+*
+* Interrupt mode is not supported because it offers no improvement when used
+* with file system.
+*
+* eMMC support:
+* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK.
+* The features of eMMC supported by the driver will depend on those supported
+* by the host controller. The current driver supports read/write on eMMC card
+* using 4-bit and high speed mode currently.
+*
+* Features not supported include - card write protect, password setting,
+* lock/unlock, interrupts, SDMA mode, programmed I/O mode and
+* 64-bit addressed ADMA2, erase/pre-erase commands.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.0   hk      03/07/14 Version number revised.
+* 2.1   hk     04/18/14 Increase sleep for eMMC switch command.
+*                       Add sleep for microblaze designs. CR# 781117.
+*
+* 

+*
+******************************************************************************/
+
+
+#ifndef SDPS_H_
+#define SDPS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xstatus.h"
+#include "xsdps_hw.h"
+#include 
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;			/**< Unique ID  of device */
+	u32 BaseAddress;		/**< Base address of the device */
+	u32 InputClockHz;		/**< Input clock frequency */
+} XSdPs_Config;
+
+/*
+ * ADMA2 descriptor table
+ */
+typedef struct {
+	u16 Attribute;		/**< Attributes of descriptor */
+	u16 Length;		/**< Length of current dma transfer */
+	u32 Address;		/**< Address of current dma transfer */
+} XSdPs_Adma2Descriptor;
+
+/**
+ * The XSdPs driver instance data. The user is required to allocate a
+ * variable of this type for every SD device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XSdPs_Config Config;	/**< Configuration structure */
+	u32 IsReady;		/**< Device is initialized and ready */
+	u32 Host_Caps;		/**< Capabilities of host controller */
+	u32 HCS;		/**< High capacity support in card */
+	u32 CardID[4];		/**< Card ID */
+	u32 RelCardAddr;	/**< Relative Card Address */
+	XSdPs_Adma2Descriptor Adma2_DescrTbl[32]; /**< ADMA Descriptors */
+} XSdPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId);
+int XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
+				u32 EffectiveAddr);
+int XSdPs_SdCardInitialize(XSdPs *InstancePtr);
+int XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
+int XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff);
+int XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize);
+int XSdPs_Select_Card (XSdPs *InstancePtr);
+int XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq);
+int XSdPs_Change_BusWidth(XSdPs *InstancePtr);
+int XSdPs_Change_BusSpeed(XSdPs *InstancePtr);
+int XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR);
+int XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff);
+int XSdPs_Pullup(XSdPs *InstancePtr);
+int XSdPs_MmcCardInitialize(XSdPs *InstancePtr);
+int XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SD_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_1/src/xsdps_g.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_1/src/xsdps_g.c
new file mode 100644
index 000000000..ef651291f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_1/src/xsdps_g.c
@@ -0,0 +1,32 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSM.
+* Version: 
+* DO NOT EDIT.
+*
+*  v (64-bit)
+SW Build (by ) on 
+Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xsdps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XSdPs_Config XSdPs_ConfigTable[] =
+{
+	{
+		XPAR_PS7_SD_0_DEVICE_ID,
+		XPAR_PS7_SD_0_BASEADDR,
+		XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_1/src/xsdps_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_1/src/xsdps_hw.h
new file mode 100644
index 000000000..32ef073c4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_1/src/xsdps_hw.h
@@ -0,0 +1,614 @@
+/******************************************************************************
+*
+* (c) Copyright 2013-2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_hw.h
+*
+* This header file contains the identifiers and basic HW access driver
+* functions (or  macros) that can be used to access the device. Other driver
+* functions are defined in xsdps.h.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+*
+* 

+*
+******************************************************************************/
+
+#ifndef SD_HW_H_
+#define SD_HW_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of an SD device.
+ * @{
+ */
+
+#define XSDPS_SDMA_SYS_ADDR_OFFSET	0x00	/**< SDMA System Address
+							Register */
+#define XSDPS_BLK_SIZE_OFFSET		0x04	/**< Block Size Register */
+#define XSDPS_BLK_CNT_OFFSET		0x06	/**< Block Count Register */
+#define XSDPS_ARGMT_OFFSET		0x08	/**< Argument Register */
+#define XSDPS_XFER_MODE_OFFSET		0x0C	/**< Transfer Mode Register */
+#define XSDPS_CMD_OFFSET		0x0E	/**< Command Register */
+#define XSDPS_RESP0_OFFSET		0x10	/**< Response0 Register */
+#define XSDPS_RESP1_OFFSET		0x14	/**< Response1 Register */
+#define XSDPS_RESP2_OFFSET		0x18	/**< Response2 Register */
+#define XSDPS_RESP3_OFFSET		0x1C	/**< Response3 Register */
+#define XSDPS_BUF_DAT_PORT_OFFSET	0x20	/**< Buffer Data Port */
+#define XSDPS_PRES_STATE_OFFSET		0x24	/**< Present State */
+#define XSDPS_HOST_CTRL1_OFFSET		0x28	/**< Host Control 1 */
+#define XSDPS_POWER_CTRL_OFFSET		0x29	/**< Power Control */
+#define XSDPS_BLK_GAP_CTRL_OFFSET	0x2A	/**< Block Gap Control */
+#define XSDPS_WAKE_UP_CTRL_OFFSET	0x2B	/**< Wake Up Control */
+#define XSDPS_CLK_CTRL_OFFSET		0x2C	/**< Clock Control */
+#define XSDPS_TIMEOUT_CTRL_OFFSET	0x2E	/**< Timeout Control */
+#define XSDPS_SW_RST_OFFSET		0x2F	/**< Software Reset */
+#define XSDPS_NORM_INTR_STS_OFFSET 	0x30	/**< Normal Interrupt
+							Status Register */
+#define XSDPS_ERR_INTR_STS_OFFSET 	0x32	/**< Error Interrupt
+							Status Register */
+#define XSDPS_NORM_INTR_STS_EN_OFFSET	0x34	/**< Normal Interrupt
+						Status Enable Register */
+#define XSDPS_ERR_INTR_STS_EN_OFFSET	0x36	/**< Error Interrupt
+						Status Enable Register */
+#define XSDPS_NORM_INTR_SIG_EN_OFFSET	0x38	/**< Normal Interrupt
+						Signal Enable Register */
+#define XSDPS_ERR_INTR_SIG_EN_OFFSET	0x3A	/**< Error Interrupt
+						Signal Enable Register */
+
+#define XSDPS_AUTO_CMD12_ERR_STS_OFFSET	0x3C	/**< Auto CMD12 Error Status
+							Register */
+#define XSDPS_HOST_CTRL2_OFFSET		0x3E	/**< Host Control2 Register */
+#define XSDPS_CAPS_OFFSET 		0x40	/**< Capabilities Register */
+#define XSDPS_CAPS_EXT_OFFSET 		0x44	/**< Capabilities Extended */
+#define XSDPS_MAX_CURR_CAPS_OFFSET	0x48	/**< Maximum Current
+						Capabilities Register */
+#define XSDPS_MAX_CURR_CAPS_EXT_OFFSET	0x4C	/**< Maximum Current
+						Capabilities Ext Register */
+#define XSDPS_FE_ERR_INT_STS_OFFSET	0x52	/**< Force Event for
+						Error Interrupt Status */
+#define XSDPS_FE_AUTO_CMD12_EIS_OFFSET	0x50	/**< Auto CM12 Error Interrupt
+							Status Register */
+#define XSDPS_ADMA_ERR_STS_OFFSET	0x54	/**< ADMA Error Status
+							Register */
+#define XSDPS_ADMA_SAR_OFFSET		0x58	/**< ADMA System Address
+							Register */
+#define XSDPS_ADMA_SAR_EXT_OFFSET	0x5C	/**< ADMA System Address
+							Extended Register */
+#define XSDPS_PRE_VAL_1_OFFSET		0x60	/**< Preset Value Register */
+#define XSDPS_PRE_VAL_2_OFFSET		0x64	/**< Preset Value Register */
+#define XSDPS_PRE_VAL_3_OFFSET		0x68	/**< Preset Value Register */
+#define XSDPS_PRE_VAL_4_OFFSET		0x6C	/**< Preset Value Register */
+#define XSDPS_SHARED_BUS_CTRL_OFFSET	0xE0	/**< Shared Bus Control
+							Register */
+#define XSDPS_SLOT_INTR_STS_OFFSET	0xFC	/**< Slot Interrupt Status
+							Register */
+#define XSDPS_HOST_CTRL_VER_OFFSET	0xFE	/**< Host Controller Version
+							Register */
+
+/* @} */
+
+/** @name Control Register - Host control, Power control,
+ * 			Block Gap control and Wakeup control
+ *
+ * This register contains bits for various configuration options of
+ * the SD host controller. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XSDPS_HC_LED_MASK		0x00000001 /**< LED Control */
+#define XSDPS_HC_WIDTH_MASK		0x00000002 /**< Bus width */
+#define XSDPS_HC_SPEED_MASK		0x00000004 /**< High Speed */
+#define XSDPS_HC_DMA_MASK		0x00000018 /**< DMA Mode Select */
+#define XSDPS_HC_DMA_SDMA_MASK		0x00000000 /**< SDMA Mode */
+#define XSDPS_HC_DMA_ADMA1_MASK		0x00000008 /**< ADMA1 Mode */
+#define XSDPS_HC_DMA_ADMA2_32_MASK	0x00000010 /**< ADMA2 Mode - 32 bit */
+#define XSDPS_HC_DMA_ADMA2_64_MASK	0x00000018 /**< ADMA2 Mode - 64 bit */
+#define XSDPS_HC_EXT_BUS_WIDTH		0x00000020 /**< Bus width - 8 bit */
+#define XSDPS_HC_CARD_DET_TL_MASK	0x00000040 /**< Card Detect Tst Lvl */
+#define XSDPS_HC_CARD_DET_SD_MASK	0x00000080 /**< Card Detect Sig Det */
+
+#define XSDPS_PC_BUS_PWR_MASK		0x00000001 /**< Bus Power Control */
+#define XSDPS_PC_BUS_VSEL_MASK		0x0000000E /**< Bus Voltage Select */
+#define XSDPS_PC_BUS_VSEL_3V3_MASK	0x0000000E /**< Bus Voltage 3.3V */
+#define XSDPS_PC_BUS_VSEL_3V0_MASK	0x0000000C /**< Bus Voltage 3.0V */
+#define XSDPS_PC_BUS_VSEL_1V8_MASK	0x0000000A /**< Bus Voltage 1.8V */
+
+#define XSDPS_BGC_STP_REQ_MASK		0x00000001 /**< Block Gap Stop Req */
+#define XSDPS_BGC_CNT_REQ_MASK		0x00000002 /**< Block Gap Cont Req */
+#define XSDPS_BGC_RWC_MASK		0x00000004 /**< Block Gap Rd Wait */
+#define XSDPS_BGC_INTR_MASK		0x00000008 /**< Block Gap Intr */
+#define XSDPS_BGC_SPI_MODE_MASK		0x00000010 /**< Block Gap SPI Mode */
+#define XSDPS_BGC_BOOT_EN_MASK		0x00000020 /**< Block Gap Boot Enb */
+#define XSDPS_BGC_ALT_BOOT_EN_MASK	0x00000040 /**< Block Gap Alt BootEn */
+#define XSDPS_BGC_BOOT_ACK_MASK		0x00000080 /**< Block Gap Boot Ack */
+
+#define XSDPS_WC_WUP_ON_INTR_MASK	0x00000001 /**< Wakeup Card Intr */
+#define XSDPS_WC_WUP_ON_INSRT_MASK	0x00000002 /**< Wakeup Card Insert */
+#define XSDPS_WC_WUP_ON_REM_MASK	0x00000004 /**< Wakeup Card Removal */
+
+/* @} */
+
+/** @name Control Register - Clock control, Timeout control & Software reset
+ *
+ * This register contains bits for configuration options of clock, timeout and
+ * software reset.
+ * Read/Write except for Inter_Clock_Stable bit (read only) and reserved bits.
+ * @{
+ */
+
+#define XSDPS_CC_INT_CLK_EN_MASK		0x00000001
+#define XSDPS_CC_INT_CLK_STABLE_MASK	0x00000002
+#define XSDPS_CC_SD_CLK_EN_MASK			0x00000004
+#define XSDPS_CC_SD_CLK_GEN_SEL_MASK		0x00000020
+#define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK	0x000000C0
+#define XSDPS_CC_SDCLK_FREQ_SEL_MASK		0x0000FF00
+#define XSDPS_CC_SDCLK_FREQ_D256_MASK		0x00008000
+#define XSDPS_CC_SDCLK_FREQ_D128_MASK		0x00004000
+#define XSDPS_CC_SDCLK_FREQ_D64_MASK		0x00002000
+#define XSDPS_CC_SDCLK_FREQ_D32_MASK		0x00001000
+#define XSDPS_CC_SDCLK_FREQ_D16_MASK		0x00000800
+#define XSDPS_CC_SDCLK_FREQ_D8_MASK		0x00000400
+#define XSDPS_CC_SDCLK_FREQ_D4_MASK		0x00000200
+#define XSDPS_CC_SDCLK_FREQ_D2_MASK		0x00000100
+#define XSDPS_CC_SDCLK_FREQ_BASE_MASK	0x00000000
+
+#define XSDPS_TC_CNTR_VAL_MASK			0x0000000F
+
+#define XSDPS_SWRST_ALL_MASK			0x00000001
+#define XSDPS_SWRST_CMD_LINE_MASK		0x00000002
+#define XSDPS_SWRST_DAT_LINE_MASK		0x00000004
+
+#define XSDPS_CC_MAX_NUM_OF_DIV		9
+#define XSDPS_CC_DIV_SHIFT		8
+
+/* @} */
+
+/** @name SD Interrupt Registers
+ *
+ *  Normal and Error Interrupt Status Register 
+ * This register shows the normal and error interrupt status.
+ * Status enable register affects reads of this register.
+ * If Signal enable register is set and the corresponding status bit is set,
+ * interrupt is generated.
+ * Write to clear except
+ * Error_interrupt and Card_Interrupt bits - Read only
+ *
+ *  Normal and Error Interrupt Status Enable Register 
+ * Setting this register bits enables Interrupt status.
+ * Read/Write except Fixed_to_0 bit (Read only)
+ *
+ *  Normal and Error Interrupt Signal Enable Register 
+ * This register is used to select which interrupt status is
+ * indicated to the Host System as the interrupt.
+ * Read/Write except Fixed_to_0 bit (Read only)
+ *
+ * All three registers have same bit definitions
+ * @{
+ */
+
+#define XSDPS_INTR_CC_MASK		0x00000001 /**< Command Complete */
+#define XSDPS_INTR_TC_MASK		0x00000002 /**< Transfer Complete */
+#define XSDPS_INTR_BGE_MASK		0x00000004 /**< Block Gap Event */
+#define XSDPS_INTR_DMA_MASK		0x00000008 /**< DMA Interrupt */
+#define XSDPS_INTR_BWR_MASK		0x00000010 /**< Buffer Write Ready */
+#define XSDPS_INTR_BRR_MASK		0x00000020 /**< Buffer Read Ready */
+#define XSDPS_INTR_CARD_INSRT_MASK	0x00000040 /**< Card Insert */
+#define XSDPS_INTR_CARD_REM_MASK	0x00000080 /**< Card Remove */
+#define XSDPS_INTR_CARD_MASK		0x00000100 /**< Card Interrupt */
+#define XSDPS_INTR_INT_A_MASK		0x00000200 /**< INT A Interrupt */
+#define XSDPS_INTR_INT_B_MASK		0x00000400 /**< INT B Interrupt */
+#define XSDPS_INTR_INT_C_MASK		0x00000800 /**< INT C Interrupt */
+#define XSDPS_INTR_RE_TUNING_MASK	0x00001000 /**< Re-Tuning Interrupt */
+#define XSDPS_INTR_BOOT_TERM_MASK	0x00002000 /**< Boot Terminate
+							Interrupt */
+#define XSDPS_INTR_BOOT_ACK_RECV_MASK	0x00004000 /**< Boot Ack Recv
+							Interrupt */
+#define XSDPS_INTR_ERR_MASK		0x00008000 /**< Error Interrupt */
+#define XSDPS_NORM_INTR_ALL_MASK	0x0000FFFF
+
+#define XSDPS_INTR_ERR_CT_MASK		0x00000001 /**< Command Timeout
+							Error */
+#define XSDPS_INTR_ERR_CCRC_MASK	0x00000002 /**< Command CRC Error */
+#define XSDPS_INTR_ERR_CEB_MASK		0x00000004 /**< Command End Bit
+							Error */
+#define XSDPS_INTR_ERR_CI_MASK		0x00000008 /**< Command Index Error */
+#define XSDPS_INTR_ERR_DT_MASK		0x00000010 /**< Data Timeout Error */
+#define XSDPS_INTR_ERR_DCRC_MASK	0x00000020 /**< Data CRC Error */
+#define XSDPS_INTR_ERR_DEB_MASK		0x00000040 /**< Data End Bit Error */
+#define XSDPS_INTR_ERR_I_LMT_MASK	0x00000080 /**< Current Limit Error */
+#define XSDPS_INTR_ERR_AUTO_CMD12_MASK	0x00000100 /**< Auto CMD12 Error */
+#define XSDPS_INTR_ERR_ADMA_MASK	0x00000200 /**< ADMA Error */
+#define XSDPS_INTR_ERR_TR_MASK		0x00001000 /**< Tuning Error */
+#define XSDPS_INTR_VEND_SPF_ERR_MASK	0x0000E000 /**< Vendor Specific
+							Error */
+#define XSDPS_ERROR_INTR_ALL_MASK	0x0000F3FF /**< Mask for error bits */
+/* @} */
+
+/** @name Block Size and Block Count Register
+ *
+ * This register contains the block count for current transfer,
+ * block size and SDMA buffer size.
+ * Read/Write except for reserved bits.
+ * @{
+ */
+
+#define XSDPS_BLK_SIZE_MASK		0x00000FFF /**< Transfer Block Size */
+#define XSDPS_SDMA_BUFF_SIZE_MASK	0x00007000 /**< Host SDMA Buffer Size */
+#define XSDPS_BLK_CNT_MASK		0x0000FFFF /**< Block Count for
+								Current Transfer */
+
+/* @} */
+
+/** @name Transfer Mode and Command Register
+ *
+ * The Transfer Mode register is used to control the data transfers and
+ * Command register is used for command generation
+ * Read/Write except for reserved bits.
+ * @{
+ */
+
+#define XSDPS_TM_DMA_EN_MASK		0x00000001 /**< DMA Enable */
+#define XSDPS_TM_BLK_CNT_EN_MASK	0x00000002 /**< Block Count Enable */
+#define XSDPS_TM_AUTO_CMD12_EN_MASK	0x00000004 /**< Auto CMD12 Enable */
+#define XSDPS_TM_DAT_DIR_SEL_MASK	0x00000010 /**< Data Transfer
+							Direction Select */
+#define XSDPS_TM_MUL_SIN_BLK_SEL_MASK	0x00000020 /**< Multi/Single
+							Block Select */
+
+#define XSDPS_CMD_RESP_SEL_MASK		0x00000003 /**< Response Type
+							Select */
+#define XSDPS_CMD_RESP_NONE_MASK	0x00000000 /**< No Response */
+#define XSDPS_CMD_RESP_L136_MASK	0x00000001 /**< Response length 138 */
+#define XSDPS_CMD_RESP_L48_MASK		0x00000002 /**< Response length 48 */
+#define XSDPS_CMD_RESP_L48_BSY_CHK_MASK	0x00000003 /**< Response length 48 &
+							check busy after
+							response */
+#define XSDPS_CMD_CRC_CHK_EN_MASK	0x00000008 /**< Command CRC Check
+							Enable */
+#define XSDPS_CMD_INX_CHK_EN_MASK	0x00000010 /**< Command Index Check
+							Enable */
+#define XSDPS_DAT_PRESENT_SEL_MASK	0x00000020 /**< Data Present Select */
+#define XSDPS_CMD_TYPE_MASK		0x000000C0 /**< Command Type */
+#define XSDPS_CMD_TYPE_NORM_MASK	0x00000000 /**< CMD Type - Normal */
+#define XSDPS_CMD_TYPE_SUSPEND_MASK	0x00000040 /**< CMD Type - Suspend */
+#define XSDPS_CMD_TYPE_RESUME_MASK	0x00000080 /**< CMD Type - Resume */
+#define XSDPS_CMD_TYPE_ABORT_MASK	0x000000C0 /**< CMD Type - Abort */
+#define XSDPS_CMD_MASK			0x00003F00 /**< Command Index Mask -
+							Set to CMD0-63,
+							AMCD0-63 */
+
+/* @} */
+
+/** @name Capabilities Register
+ *
+ * Capabilities register is a read only register which contains
+ * information about the host controller.
+ * Sufficient if read once after power on.
+ * Read Only
+ * @{
+ */
+#define XSDPS_CAP_TOUT_CLK_FREQ_MASK	0x0000003F /**< Timeout clock freq
+							select */
+#define XSDPS_CAP_TOUT_CLK_UNIT_MASK	0x00000080 /**< Timeout clock unit -
+							MHz/KHz */
+#define XSDPS_CAP_MAX_BLK_LEN_MASK	0x00030000 /**< Max block length */
+#define XSDPS_CAP_MAX_BLK_LEN_512B_MASK	0x00000000 /**< Max block 512 bytes */
+#define XSDPS_CAP_EXT_MEDIA_BUS_MASK	0x00040000 /**< Extended media bus */
+#define XSDPS_CAP_ADMA2_MASK		0x00080000 /**< ADMA2 support */
+#define XSDPS_CAP_HIGH_SPEED_MASK	0x00200000 /**< High speed support */
+#define XSDPS_CAP_SDMA_MASK		0x00400000 /**< SDMA support */
+#define XSDPS_CAP_SUSP_RESUME_MASK	0x00800000 /**< Suspend/Resume
+							support */
+#define XSDPS_CAP_VOLT_3V3_MASK		0x01000000 /**< 3.3V support */
+#define XSDPS_CAP_VOLT_3V0_MASK		0x02000000 /**< 3.0V support */
+#define XSDPS_CAP_VOLT_1V8_MASK		0x04000000 /**< 1.8V support */
+#define XSDPS_CAP_INTR_MODE_MASK	0x08000000 /**< Interrupt mode
+						 	support */
+#define XSDPS_CAP_SYS_BUS_64_MASK	0x10000000 /**< 64 bit system bus
+							support */
+#define XSDPS_CAP_SPI_MODE_MASK		0x20000000 /**< SPI mode */
+#define XSDPS_CAP_SPI_BLOCK_MODE_MASK	0x20000000 /**< SPI block mode */
+/* @} */
+
+/** @name Present State Register
+ *
+ * Gives the current status of the host controller
+ * Read Only
+ * @{
+ */
+
+#define XSDPS_PSR_INHIBIT_CMD_MASK	0x00000001 /**< Command inhibit - CMD */
+#define XSDPS_PSR_INHIBIT_DAT_MASK	0x00000002 /**< Command Inhibit - DAT */
+#define XSDPS_PSR_DAT_ACTIVE_MASK	0x00000004 /**< DAT line active */
+#define XSDPS_PSR_WR_ACTIVE_MASK	0x00000100 /**< Write transfer active */
+#define XSDPS_PSR_RD_ACTIVE_MASK	0x00000200 /**< Read transfer active */
+#define XSDPS_PSR_BUFF_WR_EN_MASK	0x00000400 /**< Buffer write enable */
+#define XSDPS_PSR_BUFF_RD_EN_MASK	0x00000800 /**< Buffer read enable */
+#define XSDPS_PSR_CARD_INSRT_MASK	0x00010000 /**< Card inserted */
+#define XSDPS_PSR_CARD_STABLE_MASK	0x00020000 /**< Card state stable */
+#define XSDPS_PSR_CARD_DPL_MASK		0x00040000 /**< Card detect pin level */
+#define XSDPS_PSR_WPS_PL_MASK		0x00080000 /**< Write protect switch
+								pin level */
+
+/* @} */
+
+/** @name Block size mask for 512 bytes
+ *
+ * Block size mask for 512 bytes - This is the default block size.
+ * @{
+ */
+
+#define XSDPS_BLK_SIZE_512_MASK	0x200
+
+/* @} */
+
+/** @name Commands
+ *
+ * Constant definitions for commands and response related to SD
+ * @{
+ */
+
+#define XSDPS_APP_CMD_PREFIX	 0x8000
+#define CMD0	 0x0000
+#define CMD1	 0x0100
+#define CMD2	 0x0200
+#define CMD3	 0x0300
+#define CMD4	 0x0400
+#define CMD5	 0x0500
+#define CMD6     0x0600
+#define ACMD6    (XSDPS_APP_CMD_PREFIX + 0x0600)
+#define CMD7	 0x0700
+#define CMD8	 0x0800
+#define CMD9	 0x0900
+#define CMD10	 0x0A00
+#define CMD12	 0x0C00
+#define ACMD13	 (XSDPS_APP_CMD_PREFIX + 0x0D00)
+#define CMD16	 0x1000
+#define CMD17	 0x1100
+#define CMD18	 0x1200
+#define CMD23	 0x1700
+#define ACMD23	 (XSDPS_APP_CMD_PREFIX + 0x1700)
+#define CMD24	 0x1800
+#define CMD25	 0x1900
+#define CMD41	 0x2900
+#define ACMD41	 (XSDPS_APP_CMD_PREFIX + 0x2900)
+#define ACMD42	 (XSDPS_APP_CMD_PREFIX + 0x2A00)
+#define ACMD51	 (XSDPS_APP_CMD_PREFIX + 0x3300)
+#define CMD52	 0x3400
+#define CMD55	 0x3700
+#define CMD58	 0x3A00
+
+#define RESP_NONE	XSDPS_CMD_RESP_NONE_MASK
+#define RESP_R1		XSDPS_CMD_RESP_L48_MASK | XSDPS_CMD_CRC_CHK_EN_MASK | \
+			XSDPS_CMD_INX_CHK_EN_MASK
+
+#define RESP_R1B	XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
+			XSDPS_CMD_CRC_CHK_EN_MASK | XSDPS_CMD_INX_CHK_EN_MASK
+
+#define RESP_R2		XSDPS_CMD_RESP_L136_MASK | XSDPS_CMD_CRC_CHK_EN_MASK
+#define RESP_R3		XSDPS_CMD_RESP_L48_MASK
+
+#define RESP_R6		XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
+			XSDPS_CMD_CRC_CHK_EN_MASK | XSDPS_CMD_INX_CHK_EN_MASK
+
+/* @} */
+
+/** @name ADMA2 Descriptor related definitions
+ *
+ * ADMA2 Descriptor related definitions
+ * @{
+ */
+
+#define XSDPS_DESC_MAX_LENGTH 65536
+
+#define XSDPS_DESC_VALID     	(0x1 << 0)
+#define XSDPS_DESC_END       	(0x1 << 1)
+#define XSDPS_DESC_INT       	(0x1 << 2)
+#define XSDPS_DESC_TRAN  	(0x2 << 4)
+
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XSdPs_In32 Xil_In32
+#define XSdPs_Out32 Xil_Out32
+
+#define XSdPs_In16 Xil_In16
+#define XSdPs_Out16 Xil_Out16
+
+#define XSdPs_In8 Xil_In8
+#define XSdPs_Out8 Xil_Out8
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg(BaseAddress, RegOffset) \
+	XSdPs_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u32 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+	XSdPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg16(BaseAddress, RegOffset) \
+	XSdPs_In16((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u16 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg16(BaseAddress, RegOffset, RegisterValue) \
+	XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg8(BaseAddress, RegOffset) \
+	XSdPs_In8((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u8 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg8(BaseAddress, RegOffset, RegisterValue) \
+	XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue))
+
+/***************************************************************************/
+/**
+* Macro to get present status register
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u8 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_GetPresentStatusReg(BaseAddress) \
+		XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SD_HW_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_1/src/xsdps_options.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_1/src/xsdps_options.c
new file mode 100644
index 000000000..f14a66b59
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_1/src/xsdps_options.c
@@ -0,0 +1,813 @@
+/******************************************************************************
+*
+* (c) Copyright 2013-2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_options.c
+*
+* Contains API's for changing the various options in host and card.
+* See xsdps.h for a detailed description of the device and driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.1   hk     04/18/14 Increase sleep for eMMC switch command.
+*                       Add sleep for microblaze designs. CR# 781117.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xsdps.h"
+/*
+ * The header sleep.h and API usleep() can only be used with an arm design.
+ * MB_Sleep() is used for microblaze design.
+ */
+#ifdef __arm__
+
+#include "sleep.h"
+
+#endif
+
+#ifdef __MICROBLAZE__
+
+#include "microblaze_sleep.h"
+
+#endif
+
+/************************** Constant Definitions *****************************/
+#define XSDPS_SCR_BLKCNT	1
+#define XSDPS_SCR_BLKSIZE	8
+#define XSDPS_4_BIT_WIDTH	0x2
+#define XSDPS_SWITCH_CMD_BLKCNT		1
+#define XSDPS_SWITCH_CMD_BLKSIZE	64
+#define XSDPS_SWITCH_CMD_HS_GET	0x00FFFFF0
+#define XSDPS_SWITCH_CMD_HS_SET	0x80FFFFF1
+#define XSDPS_EXT_CSD_CMD_BLKCNT	1
+#define XSDPS_EXT_CSD_CMD_BLKSIZE	512
+#define XSDPS_CLK_52_MHZ		52000000
+#define XSDPS_MMC_HIGH_SPEED_ARG	0x03B90100
+#define XSDPS_MMC_4_BIT_BUS_ARG		0x03B70100
+#define XSDPS_MMC_DELAY_FOR_SWITCH	2000
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+int XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
+void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
+
+/*****************************************************************************/
+/**
+* Update Block size for read/write operations.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	BlkSize - Block size passed by the user.
+*
+* @return	None
+*
+******************************************************************************/
+int XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize)
+{
+	u32 Status = 0;
+	u32 PresentStateReg = 0;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_PRES_STATE_OFFSET);
+
+	if (PresentStateReg & (XSDPS_PSR_INHIBIT_CMD_MASK |
+			XSDPS_PSR_INHIBIT_DAT_MASK |
+			XSDPS_PSR_WR_ACTIVE_MASK | XSDPS_PSR_RD_ACTIVE_MASK)) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+
+	/*
+	 * Send block write command
+	 */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD16, BlkSize, 0);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	/*
+	 * Set block size to the value passed
+	 */
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
+			 BlkSize);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to get bus width support by card.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	SCR - buffer to store SCR register returned by card.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+int XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR)
+{
+	u32 Status = 0;
+	u32 StatusReg = 0x0;
+	u16 BlkCnt;
+	u16 BlkSize;
+	int LoopCnt;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	for (LoopCnt = 0; LoopCnt < 8; LoopCnt++) {
+		SCR[LoopCnt] = 0;
+	}
+
+	/*
+	 * Send block write command
+	 */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
+			InstancePtr->RelCardAddr, 0);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	BlkCnt = XSDPS_SCR_BLKCNT;
+	BlkSize = XSDPS_SCR_BLKSIZE;
+
+	/*
+	 * Set block size to the value passed
+	 */
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, SCR);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
+
+	Status = XSdPs_CmdTransfer(InstancePtr, ACMD51, 0, BlkCnt);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if (StatusReg & XSDPS_INTR_ERR_MASK) {
+			/*
+			 * Write to clear error bits
+			 */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0);
+
+	/*
+	 * Write to clear bit
+	 */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set bus width to 4-bit in card and host
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+int XSdPs_Change_BusWidth(XSdPs *InstancePtr)
+{
+	u32 Status = 0;
+	u32 StatusReg = 0x0;
+	u32 Arg = 0;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+#ifndef MMC_CARD
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
+			InstancePtr->RelCardAddr, 0);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Arg = XSDPS_4_BIT_WIDTH;
+	Status = XSdPs_CmdTransfer(InstancePtr, ACMD6, Arg, 0);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+					XSDPS_HOST_CTRL1_OFFSET);
+	StatusReg |= XSDPS_HC_WIDTH_MASK;
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL1_OFFSET,StatusReg);
+
+	Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+#else
+
+	Arg = XSDPS_MMC_4_BIT_BUS_ARG;
+	Status = XSdPs_CmdTransfer(InstancePtr, ACMD6, Arg, 0);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+#ifdef __arm__
+
+	usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
+
+#endif
+
+#ifdef __MICROBLAZE__
+
+	/* 2 msec delay */
+	MB_Sleep(2);
+
+#endif
+
+	StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+					XSDPS_HOST_CTRL1_OFFSET);
+	StatusReg |= XSDPS_HC_WIDTH_MASK;
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL1_OFFSET,StatusReg);
+
+	Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+#endif
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to get bus speed supported by card.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	ReadBuff - buffer to store function group support data
+*		returned by card.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+int XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff)
+{
+	u32 Status = 0;
+	u32 StatusReg = 0x0;
+	u32 Arg = 0;
+	u16 BlkCnt;
+	u16 BlkSize;
+	int LoopCnt;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	for (LoopCnt = 0; LoopCnt < 64; LoopCnt++) {
+		ReadBuff[LoopCnt] = 0;
+	}
+
+	BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
+	BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
+
+	Arg = XSDPS_SWITCH_CMD_HS_GET;
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if (StatusReg & XSDPS_INTR_ERR_MASK) {
+			/*
+			 * Write to clear error bits
+			 */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0);
+
+	/*
+	 * Write to clear bit
+	 */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set high speed in card and host. Changes clock in host accordingly.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+int XSdPs_Change_BusSpeed(XSdPs *InstancePtr)
+{
+	u32 Status = 0;
+	u32 StatusReg = 0x0;
+	u32 Arg = 0;
+
+#ifndef MMC_CARD
+	u32 ClockReg;
+	u8 ReadBuff[64];
+	u16 BlkCnt;
+	u16 BlkSize;
+#endif
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+#ifndef MMC_CARD
+
+	BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
+	BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
+
+	Arg = XSDPS_SWITCH_CMD_HS_SET;
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if (StatusReg & XSDPS_INTR_ERR_MASK) {
+			/*
+			 * Write to clear error bits
+			 */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0);
+
+	/*
+	 * Write to clear bit
+	 */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	ClockReg &= ~(XSDPS_CC_INT_CLK_EN_MASK | XSDPS_CC_SD_CLK_EN_MASK);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET, ClockReg);
+
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	ClockReg &= (~XSDPS_CC_SDCLK_FREQ_SEL_MASK);
+	ClockReg |= XSDPS_CC_SDCLK_FREQ_BASE_MASK | XSDPS_CC_INT_CLK_EN_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET, ClockReg);
+
+	/*
+	 * Wait for internal clock to stabilize
+	 */
+	while((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+		XSDPS_CLK_CTRL_OFFSET) & XSDPS_CC_INT_CLK_STABLE_MASK) == 0);
+
+	/*
+	 * Enable SD clock
+	 */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET,
+			ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
+
+
+	StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+					XSDPS_HOST_CTRL1_OFFSET);
+	StatusReg |= XSDPS_HC_SPEED_MASK;
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL1_OFFSET,StatusReg);
+
+	Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+#else
+
+	Arg = XSDPS_MMC_HIGH_SPEED_ARG;
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+#ifdef __arm__
+
+	usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
+
+#endif
+
+#ifdef __MICROBLAZE__
+
+	/* 2 msec delay */
+	MB_Sleep(2);
+
+#endif
+
+	XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_52_MHZ);
+
+	StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+					XSDPS_HOST_CTRL1_OFFSET);
+	StatusReg |= XSDPS_HC_SPEED_MASK;
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL1_OFFSET,StatusReg);
+
+	Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+#endif
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to change clock freq to given value.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	SelFreq - Clock frequency in Hz.
+*
+* @return	None
+*
+* @note		This API will change clock frequency to the value less than
+*		or equal to the given value using the permissible dividors.
+*
+******************************************************************************/
+int XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq)
+{
+	u16 ClockReg;
+	int DivCnt;
+	u16 Divisor;
+	u16 ClkLoopCnt;
+	int Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Disable clock
+	 */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	ClockReg &= ~(XSDPS_CC_INT_CLK_EN_MASK | XSDPS_CC_SD_CLK_EN_MASK);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET, ClockReg);
+
+	/*
+	 * Calculate divisor
+	 */
+	DivCnt = 0x1;
+	for(ClkLoopCnt = 0; ClkLoopCnt < XSDPS_CC_MAX_NUM_OF_DIV;
+		ClkLoopCnt++) {
+		if( ((InstancePtr->Config.InputClockHz)/DivCnt) <= SelFreq) {
+			Divisor = DivCnt/2;
+			Divisor = Divisor << XSDPS_CC_DIV_SHIFT;
+			break;
+		}
+		DivCnt = DivCnt << 1;
+	}
+
+	if(ClkLoopCnt == 9) {
+
+		/*
+		 * No valid divisor found for given frequency
+		 */
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Set clock divisor
+	 */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	ClockReg &= (~XSDPS_CC_SDCLK_FREQ_SEL_MASK);
+
+	ClockReg |= Divisor | XSDPS_CC_INT_CLK_EN_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET, ClockReg);
+
+	/*
+	 * Wait for internal clock to stabilize
+	 */
+	while((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+		XSDPS_CLK_CTRL_OFFSET) & XSDPS_CC_INT_CLK_STABLE_MASK) == 0);
+
+	/*
+	 * Enable SD clock
+	 */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET,
+			ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to send pullup command to card before using DAT line 3(using 4-bit bus)
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+int XSdPs_Pullup(XSdPs *InstancePtr)
+{
+	u32 Status = 0;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
+			InstancePtr->RelCardAddr, 0);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = XSdPs_CmdTransfer(InstancePtr, ACMD42, 0, 0);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to get EXT_CSD register of eMMC.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	ReadBuff - buffer to store EXT_CSD
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+int XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff)
+{
+	u32 Status = 0;
+	u32 StatusReg = 0x0;
+	u32 Arg = 0;
+	u16 BlkCnt;
+	u16 BlkSize;
+	int LoopCnt;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	for (LoopCnt = 0; LoopCnt < 512; LoopCnt++) {
+		ReadBuff[LoopCnt] = 0;
+	}
+
+	BlkCnt = XSDPS_EXT_CSD_CMD_BLKCNT;
+	BlkSize = XSDPS_EXT_CSD_CMD_BLKSIZE;
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
+
+	Arg = 0;
+
+	/*
+	 * Send SEND_EXT_CSD command
+	 */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD8, Arg, 1);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if (StatusReg & XSDPS_INTR_ERR_MASK) {
+			/*
+			 * Write to clear error bits
+			 */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0);
+
+	/*
+	 * Write to clear bit
+	 */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_1/src/xsdps_sinit.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_1/src/xsdps_sinit.c
new file mode 100644
index 000000000..6d8e195c2
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_1/src/xsdps_sinit.c
@@ -0,0 +1,105 @@
+/******************************************************************************
+*
+* (c) Copyright 2013-2014 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_sinit.c
+*
+* The implementation of the XSdPs component's static initialization
+* functionality.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xstatus.h"
+#include "xsdps.h"
+#include "xparameters.h"
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XSdPs_Config XSdPs_ConfigTable[];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the ID of the device to look up the
+*		configuration for.
+*
+* @return
+*
+* A pointer to the configuration found or NULL if the specified device ID was
+* not found. See xsdps.h for the definition of XSdPs_Config.
+*
+* @note		None.
+*
+******************************************************************************/
+XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId)
+{
+	XSdPs_Config *CfgPtr = NULL;
+	int Index;
+
+	for (Index = 0; Index < XPAR_XSDPS_NUM_INSTANCES; Index++) {
+		if (XSdPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XSdPs_ConfigTable[Index];
+			break;
+		}
+	}
+	return CfgPtr;
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/Makefile
new file mode 100644
index 000000000..f7bba6f6b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/Makefile
@@ -0,0 +1,72 @@
+######################################################################
+# Copyright (c) 2011-13 Xilinx, Inc.  All rights reserved. 
+# 
+# Xilinx, Inc. 
+# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A 
+# COURTESY TO YOU.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS 
+# ONE POSSIBLE   IMPLEMENTATION OF THIS FEATURE, APPLICATION OR 
+# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION 
+# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE 
+# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. 
+# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO 
+# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO 
+# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE 
+# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY 
+# AND FITNESS FOR A PARTICULAR PURPOSE. 
+######################################################################
+
+include config.make
+
+AS=arm-xilinx-eabi-as
+CC=arm-xilinx-eabi-gcc
+AR=arm-xilinx-eabi-ar
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+LIB=libxil.a
+
+CC_FLAGS = $(subst -pg, -DPROFILING, $(COMPILER_FLAGS))
+ECC_FLAGS = $(subst -pg, -DPROFILING, $(EXTRA_COMPILER_FLAGS))
+
+ifeq ($(COMPILER) , arm-eabi-gcc)
+ ECC_FLAGS	=	+= -nostartfiles
+endif
+
+#The following flags are required for PEEP. We can remove them later
+ECC_FLAGS	+= -march=armv7-a \
+		  -mfloat-abi=soft \
+		  -mfpu=neon
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+INCLUDEFILES=*.h
+
+libs: $(LIBS)
+
+standalone_libs: $(LIBSOURCES)
+	echo "Compiling standalone"
+	$(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $^
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} 
+
+profile_libs:
+	$(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(ARCHIVER)" AS="$(AS)" libs
+
+.PHONY: include
+include: standalone_includes profile_includes
+
+standalone_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+profile_includes:
+	$(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(ARCHIVER)" AS="$(AS)" include
+
+clean:
+	rm -rf ${OUTS}
+	$(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(ARCHIVER)" AS="$(AS)" clean
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/_exit.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/_exit.c
new file mode 100644
index 000000000..20df10bc3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/_exit.c
@@ -0,0 +1,50 @@
+/******************************************************************************
+*
+* (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+#include 
+
+/* _exit - Simple implementation. Does not return.
+*/
+void _exit (int status)
+{
+  (void)status;
+  while (1);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/_open.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/_open.c
new file mode 100644
index 000000000..95ad8c503
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/_open.c
@@ -0,0 +1,62 @@
+/******************************************************************************
+*
+* (c) Copyright 2009-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+	int _open(const char *buf, int flags, int mode);
+}
+#endif
+
+/*
+ * _open -- open a file descriptor. We don't have a filesystem, so
+ *         we return an error.
+ */
+int _open(const char *buf, int flags, int mode)
+{
+  (void)buf;
+  (void)flags;
+  (void)mode;
+  errno = EIO;
+  return (-1);
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/_sbrk.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/_sbrk.c
new file mode 100644
index 000000000..325100561
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/_sbrk.c
@@ -0,0 +1,70 @@
+/******************************************************************************
+*
+* (c) Copyright 2009-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+#include 
+
+extern int  _heap_start;
+extern int _heap_end;
+
+#ifdef __cplusplus
+extern "C" {
+	caddr_t _sbrk ( int incr );
+}
+#endif
+
+caddr_t _sbrk ( int incr )
+{
+  static unsigned char *heap = NULL;
+  unsigned char *prev_heap;
+
+  if (heap == NULL) {
+    heap = (unsigned char *)&_heap_start;
+  }
+  prev_heap = heap;
+
+  heap += incr;
+
+  if ((unsigned)heap > (unsigned)&_heap_end){
+		  return (caddr_t) -1;
+  }
+  return (caddr_t) prev_heap;
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/abort.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/abort.c
new file mode 100644
index 000000000..e8f17bb5d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/abort.c
@@ -0,0 +1,51 @@
+/******************************************************************************
+*
+* (c) Copyright 2009-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+#include 
+#include 
+
+/*
+ * abort -- go out via exit...
+ */
+void abort(void)
+{
+  _exit(1);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/asm_vectors.S b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/asm_vectors.S
new file mode 100644
index 000000000..60e34dd95
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/asm_vectors.S
@@ -0,0 +1,208 @@
+/******************************************************************************
+*
+* (c) Copyright 2009-14 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file asm_vectors.s
+*
+* This file contains the initial vector table for the Cortex A9 processor
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 10/20/09 Initial version
+* 3.05a sdm	02/02/12 Save lr when profiling is enabled
+* 3.10a srt     04/18/13 Implemented ARM Erratas. Please refer to file
+*			 'xil_errata.h' for errata description
+* 4.00a pkp	22/01/14 Modified return addresses for interrupt 
+*			 handlers (DataAbortHandler and SVCHandler)
+*			 to fix CR#767251
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+#include "xil_errata.h"
+
+#define __ARM_NEON__ 1
+
+.org 0
+.text
+
+.globl _boot
+.globl _vector_table
+
+.globl FIQInterrupt
+.globl IRQInterrupt
+.globl SWInterrupt
+.globl DataAbortInterrupt
+.globl PrefetchAbortInterrupt
+
+.globl IRQHandler
+.globl prof_pc
+
+.section .vectors
+_vector_table:
+	B	_boot
+	B	Undefined
+	B	SVCHandler
+	B	PrefetchAbortHandler
+	B	DataAbortHandler
+	NOP	/* Placeholder for address exception vector*/
+	B	IRQHandler
+	B	FIQHandler
+
+
+IRQHandler:					/* IRQ vector handler */
+	
+	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code*/
+#ifdef __ARM_NEON__
+	vpush {d0-d7}
+	vpush {d16-d31}
+	vmrs r1, FPSCR
+	push {r1}
+	vmrs r1, FPEXC
+	push {r1}
+#endif
+
+#ifdef PROFILING
+	ldr	r2, =prof_pc
+	subs	r3, lr, #0
+	str	r3, [r2]
+#endif
+
+	bl	IRQInterrupt			/* IRQ vector */
+	
+#ifdef __ARM_NEON__
+	pop 	{r1}
+	vmsr    FPEXC, r1
+	pop 	{r1}
+	vmsr    FPSCR, r1
+	vpop    {d16-d31}
+	vpop    {d0-d7}
+#endif
+	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
+	
+
+	subs	pc, lr, #4			/* adjust return */
+
+
+FIQHandler:					/* FIQ vector handler */
+	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code */
+#ifdef __ARM_NEON__
+	vpush {d0-d7}
+	vpush {d16-d31}
+	vmrs r1, FPSCR
+	push {r1}
+	vmrs r1, FPEXC
+	push {r1}
+#endif
+
+FIQLoop:
+	bl	FIQInterrupt			/* FIQ vector */
+
+#ifdef __ARM_NEON__
+	pop 	{r1}
+	vmsr    FPEXC, r1
+	pop 	{r1}
+	vmsr    FPSCR, r1
+	vpop    {d16-d31}
+	vpop    {d0-d7}
+#endif
+	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
+	subs	pc, lr, #4			/* adjust return */
+
+
+Undefined:					/* Undefined handler */
+	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code */
+
+	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
+
+	b	_prestart			
+
+	movs	pc, lr
+
+
+SVCHandler:					/* SWI handler */
+	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code */
+
+	tst	r0, #0x20			/* check the T bit */
+	ldrneh	r0, [lr,#-2]			/* Thumb mode */
+	bicne	r0, r0, #0xff00			/* Thumb mode */
+	ldreq	r0, [lr,#-4]			/* ARM mode */
+	biceq	r0, r0, #0xff000000		/* ARM mode */
+
+	bl	SWInterrupt			/* SWInterrupt: call C function here */
+
+	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
+
+	movs	pc, lr		/*return to the next instruction after the SWI instruction */
+
+
+DataAbortHandler:				/* Data Abort handler */
+#ifdef CONFIG_ARM_ERRATA_775420
+	dsb
+#endif
+	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code */
+
+	bl	DataAbortInterrupt		/*DataAbortInterrupt :call C function here */
+
+	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
+
+	subs	pc, lr, #8			/* points to the instruction that caused the Data Abort exception */
+
+PrefetchAbortHandler:				/* Prefetch Abort handler */
+#ifdef CONFIG_ARM_ERRATA_775420
+	dsb
+#endif
+	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code */
+
+	bl	PrefetchAbortInterrupt		/* PrefetchAbortInterrupt: call C function here */
+
+	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
+
+	subs	pc, lr, #4			/* points to the instruction that caused the Prefetch Abort exception */
+
+
+.end
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/boot.S b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/boot.S
new file mode 100644
index 000000000..e07b42193
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/boot.S
@@ -0,0 +1,448 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-2013 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file boot.S
+*
+* This file contains the initial startup code for the Cortex A9 processor
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 10/20/09 Initial version
+* 3.06a sgd     05/15/12 Updated L2CC Auxiliary and Tag RAM Latency control 
+*			 register settings.
+* 3.06a asa 	06/17/12 Modified the TTBR settings and L2 Cache auxiliary
+*		         register settings.
+* 3.07a asa     07/16/12 Modified the L2 Cache controller settings to improve
+*			 performance. Changed the property of the ".boot"
+*			 section.
+* 3.07a sgd     08/21/12 Modified the L2 Cache controller and cp15 Aux Control 
+*               Register settings
+* 3.09a sgd     02/06/13 Updated SLCR l2c Ram Control register to a 
+*               value of 0x00020202. Fix for CR 697094 (SI#687034).
+* 3.10a srt     04/18/13 Implemented ARM Erratas. Please refer to file
+*			 'xil_errata.h' for errata description
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#include "xparameters.h"
+#include "xil_errata.h"
+
+.globl MMUTable
+.global _prestart
+.global _boot
+.global __stack
+.global __irq_stack
+.global __supervisor_stack
+.global __abort_stack
+.global __fiq_stack
+.global __undef_stack
+.global _vector_table
+
+.set PSS_L2CC_BASE_ADDR, 0xF8F02000
+.set PSS_SLCR_BASE_ADDR, 0xF8000000
+
+.set RESERVED,		0x0fffff00
+.set TblBase ,		MMUTable
+.set LRemap,		0xFE00000F		/* set the base address of the peripheral block as not shared */
+.set L2CCWay,		(PSS_L2CC_BASE_ADDR + 0x077C)	/*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_INVLD_WAY_OFFSET)*/
+.set L2CCSync,		(PSS_L2CC_BASE_ADDR + 0x0730)	/*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_SYNC_OFFSET)*/
+.set L2CCCrtl,		(PSS_L2CC_BASE_ADDR + 0x0100)	/*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CNTRL_OFFSET)*/
+.set L2CCAuxCrtl,	(PSS_L2CC_BASE_ADDR + 0x0104)	/*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_AUX_CNTRL_OFFSET)*/
+.set L2CCTAGLatReg,	(PSS_L2CC_BASE_ADDR + 0x0108)	/*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_TAG_RAM_CNTRL_OFFSET)*/
+.set L2CCDataLatReg,	(PSS_L2CC_BASE_ADDR + 0x010C)	/*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_DATA_RAM_CNTRL_OFFSET)*/
+.set L2CCIntClear,	(PSS_L2CC_BASE_ADDR + 0x0220)	/*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_IAR_OFFSET)*/
+.set L2CCIntRaw,	(PSS_L2CC_BASE_ADDR + 0x021C)	/*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_ISR_OFFSET)*/
+
+.set SLCRlockReg,	    (PSS_SLCR_BASE_ADDR + 0x04)	/*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_LOCK_OFFSET)*/
+.set SLCRUnlockReg,     (PSS_SLCR_BASE_ADDR + 0x08)	/*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_UNLOCK_OFFSET)*/
+.set SLCRL2cRamReg,     (PSS_SLCR_BASE_ADDR + 0xA1C) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_L2C_RAM_OFFSET)*/
+
+/* workaround for simulation not working when L1 D and I caches,MMU and  L2 cache enabled - DT568997 */
+.if SIM_MODE == 1
+.set CRValMmuCac,	0b00000000000000	/* Disable IDC, and MMU */
+.else 
+.set CRValMmuCac,	0b01000000000101	/* Enable IDC, and MMU */
+.endif
+
+.set CRValHiVectorAddr,	0b10000000000000	/* Set the Vector address to high, 0xFFFF0000 */
+
+.set L2CCAuxControl,	0x72360000		/* Enable all prefetching, Cache replacement policy, Parity enable, 
+                                        Event monitor bus enable and Way Size (64 KB) */
+.set L2CCControl,	0x01			/* Enable L2CC */
+.set L2CCTAGLatency,	0x0111			/* latency for TAG RAM */
+.set L2CCDataLatency,	0x0121			/* latency for DATA RAM */
+
+.set SLCRlockKey,	        0x767B			/* SLCR lock key */
+.set SLCRUnlockKey,	        0xDF0D			/* SLCR unlock key */
+.set SLCRL2cRamConfig,      0x00020202      /* SLCR L2C ram configuration */
+
+/* Stack Pointer locations for boot code */
+.set Undef_stack,	__undef_stack
+.set FIQ_stack,		__fiq_stack
+.set Abort_stack,	__abort_stack
+.set SPV_stack,		__supervisor_stack
+.set IRQ_stack,		__irq_stack
+.set SYS_stack,		__stack
+
+.set vector_base,	_vector_table
+
+.set FPEXC_EN,		0x40000000		/* FPU enable bit, (1 << 30) */
+
+.section .boot,"ax"
+
+
+/* this initializes the various processor modes */
+
+_prestart:
+_boot:
+
+#if XPAR_CPU_ID==0
+/* only allow cpu0 through */
+	mrc	p15,0,r1,c0,c0,5
+	and	r1, r1, #0xf
+	cmp	r1, #0
+	beq	OKToRun
+EndlessLoop0:
+	wfe
+	b	EndlessLoop0
+
+#elif XPAR_CPU_ID==1
+/* only allow cpu1 through */
+	mrc	p15,0,r1,c0,c0,5
+	and	r1, r1, #0xf
+	cmp	r1, #1
+	beq	OKToRun
+EndlessLoop1:
+	wfe
+	b	EndlessLoop1
+#endif
+
+OKToRun:
+	mrc     p15, 0, r0, c0, c0, 0		/* Get the revision */
+	and     r5, r0, #0x00f00000 
+	and     r6, r0, #0x0000000f
+	orr     r6, r6, r5, lsr #20-4
+
+#ifdef CONFIG_ARM_ERRATA_742230
+        cmp     r6, #0x22                       /* only present up to r2p2 */
+        mrcle   p15, 0, r10, c15, c0, 1         /* read diagnostic register */
+        orrle   r10, r10, #1 << 4               /* set bit #4 */
+        mcrle   p15, 0, r10, c15, c0, 1         /* write diagnostic register */
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_743622
+	teq     r5, #0x00200000                 /* only present in r2p* */
+	mrceq   p15, 0, r10, c15, c0, 1         /* read diagnostic register */
+	orreq   r10, r10, #1 << 6               /* set bit #6 */
+	mcreq   p15, 0, r10, c15, c0, 1         /* write diagnostic register */
+#endif
+
+	/* set VBAR to the _vector_table address in linker script */
+	ldr	r0, =vector_base
+	mcr	p15, 0, r0, c12, c0, 0
+
+	/*set scu enable bit in scu*/
+	ldr	r7, =0xf8f00000
+	ldr	r0, [r7]
+	orr	r0, r0, #0x1  
+	str	r0, [r7]
+
+	/*invalidate scu*/
+	ldr	r7, =0xf8f0000c
+	ldr	r6, =0xffff
+	str	r6, [r7]
+
+	/* Write to ACTLR */
+	mrc	p15, 0, r0, c1, c0, 1		/* Read ACTLR*/
+	orr	r0, r0, #(0x01 << 6)		/* set SMP bit */
+	orr	r0, r0, #(0x01 )		/* */		
+	mcr	p15, 0, r0, c1, c0, 1		/* Write ACTLR*/
+
+/* Invalidate caches and TLBs */
+	mov	r0,#0				/* r0 = 0  */
+	mcr	p15, 0, r0, c8, c7, 0		/* invalidate TLBs */
+	mcr	p15, 0, r0, c7, c5, 0		/* invalidate icache */
+	mcr	p15, 0, r0, c7, c5, 6		/* Invalidate branch predictor array */
+	bl	invalidate_dcache		/* invalidate dcache */
+
+/* Invalidate L2c Cache */
+/* For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux) */
+#if USE_AMP!=1
+	ldr	r0,=L2CCCrtl			/* Load L2CC base address base + control register */
+	mov	r1, #0				/* force the disable bit */
+	str	r1, [r0]			/* disable the L2 Caches */
+
+	ldr	r0,=L2CCAuxCrtl			/* Load L2CC base address base + Aux control register */
+	ldr	r1,[r0]				/* read the register */
+	ldr	r2,=L2CCAuxControl		/* set the default bits */
+	orr	r1,r1,r2
+	str	r1, [r0]			/* store the Aux Control Register */
+
+	ldr	r0,=L2CCTAGLatReg		/* Load L2CC base address base + TAG Latency address */
+	ldr	r1,=L2CCTAGLatency		/* set the latencies for the TAG*/
+	str	r1, [r0]			/* store the TAG Latency register Register */
+
+	ldr	r0,=L2CCDataLatReg		/* Load L2CC base address base + Data Latency address */
+	ldr	r1,=L2CCDataLatency		/* set the latencies for the Data*/
+	str	r1, [r0]			/* store the Data Latency register Register */
+
+	ldr	r0,=L2CCWay			/* Load L2CC base address base + way register*/
+	ldr	r2, =0xFFFF
+	str	r2, [r0]			/* force invalidate */
+
+	ldr	r0,=L2CCSync			/* need to poll 0x730, PSS_L2CC_CACHE_SYNC_OFFSET */
+						/* Load L2CC base address base + sync register*/
+	/* poll for completion */
+Sync:	ldr	r1, [r0]
+	cmp	r1, #0
+	bne	Sync
+
+	ldr	r0,=L2CCIntRaw			/* clear pending interrupts */
+	ldr	r1,[r0]
+	ldr	r0,=L2CCIntClear	
+	str	r1,[r0]
+#endif
+
+	/* Disable MMU, if enabled */
+	mrc	p15, 0, r0, c1, c0, 0		/* read CP15 register 1 */
+	bic	r0, r0, #0x1			/* clear bit 0 */
+	mcr	p15, 0, r0, c1, c0, 0		/* write value back */
+
+#ifdef SHAREABLE_DDR
+	/* Mark the entire DDR memory as shareable */
+	ldr	r3, =0x3ff			/* 1024 entries to cover 1G DDR */
+	ldr	r0, =TblBase			/* MMU Table address in memory */
+	ldr	r2, =0x15de6			/* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
+shareable_loop:
+	str	r2, [r0]			/* write the entry to MMU table */
+	add	r0, r0, #0x4			/* next entry in the table */
+	add	r2, r2, #0x100000		/* next section */
+	subs	r3, r3, #1
+	bge	shareable_loop			/* loop till 1G is covered */
+#endif
+
+	/* In case of AMP, map virtual address 0x20000000 to 0x00000000  and mark it as non-cacheable */
+#if USE_AMP==1
+	ldr	r3, =0x1ff			/* 512 entries to cover 512MB DDR */
+	ldr	r0, =TblBase			/* MMU Table address in memory */
+	add	r0, r0, #0x800			/* Address of entry in MMU table, for 0x20000000 */
+	ldr	r2, =0x0c02			/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */
+mmu_loop:
+	str	r2, [r0]			/* write the entry to MMU table */
+	add	r0, r0, #0x4			/* next entry in the table */
+	add	r2, r2, #0x100000		/* next section */
+	subs	r3, r3, #1
+	bge	mmu_loop			/* loop till 512MB is covered */
+#endif
+
+	mrs	r0, cpsr			/* get the current PSR */
+	mvn	r1, #0x1f			/* set up the irq stack pointer */
+	and	r2, r1, r0
+	orr	r2, r2, #0x12			/* IRQ mode */
+	msr	cpsr, r2
+	ldr	r13,=IRQ_stack			/* IRQ stack pointer */
+
+	mrs	r0, cpsr			/* get the current PSR */
+	mvn	r1, #0x1f			/* set up the supervisor stack pointer */
+	and	r2, r1, r0
+	orr	r2, r2, #0x13			/* supervisor mode */
+	msr	cpsr, r2
+	ldr	r13,=SPV_stack			/* Supervisor stack pointer */
+
+	mrs	r0, cpsr			/* get the current PSR */
+	mvn	r1, #0x1f			/* set up the Abort  stack pointer */
+	and	r2, r1, r0
+	orr	r2, r2, #0x17			/* Abort mode */
+	msr	cpsr, r2
+	ldr	r13,=Abort_stack		/* Abort stack pointer */
+
+	mrs	r0, cpsr			/* get the current PSR */
+	mvn	r1, #0x1f			/* set up the FIQ stack pointer */
+	and	r2, r1, r0
+	orr	r2, r2, #0x11			/* FIQ mode */
+	msr	cpsr, r2
+	ldr	r13,=FIQ_stack			/* FIQ stack pointer */
+
+	mrs	r0, cpsr			/* get the current PSR */
+	mvn	r1, #0x1f			/* set up the Undefine stack pointer */
+	and	r2, r1, r0
+	orr	r2, r2, #0x1b			/* Undefine mode */
+	msr	cpsr, r2
+	ldr	r13,=Undef_stack		/* Undefine stack pointer */
+
+	mrs	r0, cpsr			/* get the current PSR */
+	mvn	r1, #0x1f			/* set up the system stack pointer */
+	and	r2, r1, r0
+	orr	r2, r2, #0x1F			/* SYS mode */
+	msr	cpsr, r2
+	ldr	r13,=SYS_stack			/* SYS stack pointer */
+
+	/* enable MMU and cache */
+
+	ldr	r0,=TblBase			/* Load MMU translation table base */
+	orr	r0, r0, #0x5B			/* Outer-cacheable, WB */
+	mcr	15, 0, r0, c2, c0, 0		/* TTB0 */
+	
+	
+	mvn	r0,#0				/* Load MMU domains -- all ones=manager */
+	mcr	p15,0,r0,c3,c0,0
+
+	/* Enable mmu, icahce and dcache */
+	ldr	r0,=CRValMmuCac
+
+	mcr	p15,0,r0,c1,c0,0		/* Enable cache and MMU */
+	dsb					/* dsb	allow the MMU to start up */
+
+	isb					/* isb	flush prefetch buffer */
+
+/* For AMP, assume running on CPU1. Don't initialize L2 Cache (up to Linux) */
+#if USE_AMP!=1
+	ldr	r0,=SLCRUnlockReg		/* Load SLCR base address base + unlock register */
+	ldr	r1,=SLCRUnlockKey	    /* set unlock key */
+	str	r1, [r0]		    /* Unlock SLCR */
+
+   	ldr	r0,=SLCRL2cRamReg		/* Load SLCR base address base + l2c Ram Control register */
+	ldr	r1,=SLCRL2cRamConfig        /* set the configuration value */
+	str	r1, [r0]	        /* store the L2c Ram Control Register */
+
+   	ldr	r0,=SLCRlockReg         /* Load SLCR base address base + lock register */
+	ldr	r1,=SLCRlockKey	        /* set lock key */
+	str	r1, [r0]	        /* lock SLCR */
+
+	ldr	r0,=L2CCCrtl			/* Load L2CC base address base + control register */
+	ldr	r1,[r0]				/* read the register */
+	mov	r2, #L2CCControl		/* set the enable bit */
+	orr	r1,r1,r2
+	str	r1, [r0]			/* enable the L2 Caches */
+#endif
+
+	mov	r0, r0
+	mrc	p15, 0, r1, c1, c0, 2		/* read cp access control register (CACR) into r1 */
+	orr	r1, r1, #(0xf << 20)		/* enable full access for p10 & p11 */
+	mcr	p15, 0, r1, c1, c0, 2		/* write back into CACR */
+
+	/* enable vfp */
+	fmrx	r1, FPEXC			/* read the exception register */
+	orr	r1,r1, #FPEXC_EN		/* set VFP enable bit, leave the others in orig state */
+	fmxr	FPEXC, r1			/* write back the exception register */
+
+	mrc	p15,0,r0,c1,c0,0		/* flow prediction enable */
+	orr	r0, r0, #(0x01 << 11)		/* #0x8000 */		
+	mcr	p15,0,r0,c1,c0,0
+
+	mrc	p15,0,r0,c1,c0,1		/* read Auxiliary Control Register */
+	orr	r0, r0, #(0x1 << 2)		/* enable Dside prefetch */
+	orr	r0, r0, #(0x1 << 1)		/* enable L2 Prefetch hint */
+	mcr	p15,0,r0,c1,c0,1		/* write Auxiliary Control Register */
+
+	b	_start				/* jump to C startup code */
+	and	r0, r0, r0			/* no op */
+	
+.Ldone:	b	.Ldone				/* Paranoia: we should never get here */
+
+
+/*
+ *************************************************************************
+ *
+ * invalidate_dcache - invalidate the entire d-cache by set/way
+ *
+ * Note: for Cortex-A9, there is no cp instruction for invalidating
+ * the whole D-cache. Need to invalidate each line.
+ *
+ *************************************************************************
+ */
+invalidate_dcache:
+	mrc	p15, 1, r0, c0, c0, 1		/* read CLIDR */
+	ands	r3, r0, #0x7000000
+	mov	r3, r3, lsr #23			/* cache level value (naturally aligned) */
+	beq	finished
+	mov	r10, #0				/* start with level 0 */
+loop1:
+	add	r2, r10, r10, lsr #1		/* work out 3xcachelevel */
+	mov	r1, r0, lsr r2			/* bottom 3 bits are the Cache type for this level */
+	and	r1, r1, #7			/* get those 3 bits alone */
+	cmp	r1, #2
+	blt	skip				/* no cache or only instruction cache at this level */
+	mcr	p15, 2, r10, c0, c0, 0		/* write the Cache Size selection register */
+	isb					/* isb to sync the change to the CacheSizeID reg */
+	mrc	p15, 1, r1, c0, c0, 0		/* reads current Cache Size ID register */
+	and	r2, r1, #7			/* extract the line length field */
+	add	r2, r2, #4			/* add 4 for the line length offset (log2 16 bytes) */
+	ldr	r4, =0x3ff
+	ands	r4, r4, r1, lsr #3		/* r4 is the max number on the way size (right aligned) */
+	clz	r5, r4				/* r5 is the bit position of the way size increment */
+	ldr	r7, =0x7fff
+	ands	r7, r7, r1, lsr #13		/* r7 is the max number of the index size (right aligned) */
+loop2:
+	mov	r9, r4				/* r9 working copy of the max way size (right aligned) */
+loop3:
+	orr	r11, r10, r9, lsl r5		/* factor in the way number and cache number into r11 */
+	orr	r11, r11, r7, lsl r2		/* factor in the index number */
+	mcr	p15, 0, r11, c7, c6, 2		/* invalidate by set/way */
+	subs	r9, r9, #1			/* decrement the way number */
+	bge	loop3
+	subs	r7, r7, #1			/* decrement the index */
+	bge	loop2
+skip:
+	add	r10, r10, #2			/* increment the cache number */
+	cmp	r3, r10
+	bgt	loop1
+
+finished:
+	mov	r10, #0				/* swith back to cache level 0 */
+	mcr	p15, 2, r10, c0, c0, 0		/* select current cache level in cssr */
+	dsb
+	isb
+
+	bx	lr
+
+.end
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/bspconfig.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/bspconfig.h
new file mode 100644
index 000000000..efc25d1ea
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/bspconfig.h
@@ -0,0 +1,16 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSM.
+* Version: 
+* DO NOT EDIT.
+*
+*  v (64-bit)
+SW Build (by ) on 
+Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
+* 
+* Description: Configurations for Standalone BSP
+*
+*******************************************************************/
+
+#define MICROBLAZE_PVR_NONE
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/changelog.txt b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/changelog.txt
new file mode 100644
index 000000000..5ae028a31
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/changelog.txt
@@ -0,0 +1,175 @@
+/*****************************************************************************
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- ---------------------------------------------------
+ * 3.02a sdm  05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+ * 3.02a sdm  06/27/11 Added INST_SYNC and DATA_SYNC macros for all the CPUs
+ * 3.02a sdm  07/07/11 Updated ppc440 boot.S to set guarded bit for all but
+ *                     cacheable regions
+ *                     Update ppc440/xil_cache.c to use CACHEABLE_REGION_MASK
+ *                     generated by the cpu driver, for enabling caches
+ * 3.02a sdm  07/08/11 Updated microblaze cache flush APIs based on write-back/
+ *                     write-thru caches
+ * 3.03a sdm  08/20/11 Updated the tag/data RAM latency values for L2CC
+ *		       Updated the MMU table to mark OCM in high address space
+ *		       as inner cacheable and reserved space as Invalid
+ * 3.03a sdm  08/20/11 Changes to support FreeRTOS
+ *		       Updated the MMU table to mark upper half of the DDR as
+ *		       non-cacheable
+ *		       Setup supervisor and abort mode stacks
+ *		       Do not initialize/enable L2CC in case of AMP
+ *		       Initialize UART1 for 9600bps in case of AMP
+ * 3.03a sdm  08/27/11 Setup abort and supervisor mode stacks and don't init SMC
+ *		       in case of AMP
+ * 3.03a sdm  09/14/11 Added code for performance monitor and L2CC event
+ *		       counters
+ * 3.03a sdm  11/08/11 Updated microblaze xil_cache.h file to include
+ *		       xparameters.h file for CR630532 -  Xil_DCacheFlush()/
+ *		       Xil_DCacheFlushRange() functions in standalone BSP v3_02a
+ *		       for MicroBlaze will invalidate data in the cache instead
+ *		       of flushing it for writeback caches
+ * 3.04a sdm  11/21/11 Updated to initialize stdio device for 115200bps, for PS7
+ * 3.04a sdm  01/02/12 Updated to clear cp15 regs with unknown reset values
+ *		       Remove redundant dsb/dmb instructions in cache maintenance
+ *		       APIs
+ *		       Remove redundant dsb in mcr instruction
+ * 3.04a sdm  01/13/12 Updated MMU table to mark DDR memory as Shareable
+ * 3.05a sdm  02/02/12 Removed some of the defines as they are being generated through
+ *                     driver tcl in xparameters.h. Update the gcc/translationtable.s
+ *                     for the QSPI complete address range - DT644567
+ *                     Removed profile directory for armcc compiler and changed
+ *                     profiling setting to false in standalone_v2_1_0.tcl file
+ *                     Deleting boot.S file after preprocessing for armcc compiler
+ * 3.05a asa  03/11/12 Updated the function Xil_EnableMMU in file xil_mmu.c to
+ *		       invalidate the caches before enabling back the MMU and
+ *		       D cache.
+ * 3.05a asa  04/15/12 Updated the function Xil_SetTlbAttributes in file
+ *		       xil_mmu.c. Now we invalidate UTLB, Branch predictor
+ *		       array, flush the D-cache before changing the attributes
+ *		       in translation table. The user need not call Xil_DisableMMU
+ *		       before calling Xil_SetTlbAttributes.
+ * 3.06a asa/ 06/17/12 Removed the UART initialization for Zynq. For PEEP, the UART
+ *	 sgd	       initialization is present. Changes for this were done in
+ *		       uart.c and xil-crt0.s.
+ *		       Made changes in xil_io.c to use volatile pointers.
+ *		       Made changes in xil_mmu.c to correct the function
+ *		       Xil_SetTlbAttributes.
+ *		       Changes are made xil-crt0.s to initialize the static
+ *		       C++ constructors.
+ *		       Changes are made in boot.s, to fix the TTBR settings,
+ *		       correct the L2 Cache Auxiliary register settings, L2 cache
+ *		       latency settings.
+ * 3.07a asa/ 07/16/12 Made changes in cortexa9/xtime_l.c, xtime_l.h, sleep.c
+ *	 sgd	       usleep.c to use global timer intstead of CP15.
+ *		       Made changes in cortexa9/gcc/translation_table.s to map
+ *		       the peripheral devices as shareable device memory.
+ *		       Made changes in cortexa9/gcc/xil-crt0.s to initialize
+ *		       the global timer.
+ *		       Made changes in cortexa9/armcc/boot.S to initialize
+ *		       the global timer.
+ *		       Made changes in cortexa9/armcc/translation_table.s to
+ *		       map the peripheral devices as shareable device memory.
+ *		       Made changes in cortexa9/gcc/boot.S to optimize the
+ *		       L2 cache settings. Changes the section properties for
+ *		       ".mmu_tbl" and ".boot" sections in cortexa9/gcc/boot.S
+ *			and cortexa9/gcc/translation_table.S.
+ *		       Made changes in cortexa9/xil_cache.c to change the
+ *		       cache invalidation order.
+ * 3.07a asa  08/17/12 Made changes across files for Cortexa9 to remove
+ *		       compilation/linking issues for C++ compiler.
+ *		       Made changes in mb_interface.h to remove compilation/
+ *		       linking issues for C++ compiler.
+ *		       Added macros for swapb and swaph microblaze instructions
+ *		       mb_interface.h
+ *		       Remove barrier usage (SYNCHRONIZE_IO) from xil_io.c
+ *		       for CortexA9.
+ * 3.07a asa  08/30/12 Updated for CR 675636 to provide the L2 Base Address
+ * 3.07a asa  08/31/12 Added xil_printf.h include
+ * 3.07a sgd  09/18/12 Corrected the L2 cache enable settings
+ *				Corrected L2 cache sequence disable sequence
+ * 3.07a sgd  10/19/12 SMC NOR and SRAM initialization with compiler option
+ * 3.09a asa  01/25/13 Updated to push and pop neon registers into stack for
+ *		       irq/fiq handling.
+ *		       Relocated COUNTS_PER_SECOND from sleep.c to xtime_l.h. This
+ *		       fixes the CR #692094.
+ * 3.09a sgd  02/14/13 Fix for CRs 697094 (SI#687034) and 675552.
+ * 3.10a srt  04/18/13 Implemented ARM Erratas. 
+ *		       Cortex A9 Errata - 742230, 743622, 775420, 794073
+ *		       L2Cache PL310 Errata - 588369, 727915, 759370
+ *		       Please refer to file 'xil_errata.h' for errata
+ *		       description.
+ * 3.10a asa  05/04/13 Added support for L2 cache in MicroBlaze BSP. The older
+ *		       cache APIs were corresponding to only Layer 1 cache 
+ *		       memories. New APIs were now added and the existing cache
+ *		       related APIs were changed to provide a uniform interface
+ *		       to flush/invalidate/enable/disable the complete cache
+ *		       system which includes both L1 and L2 caches. The changes
+ *		       for these were done in:
+ *		       src/microblaze/xil_cache.c and src/microblaze/xil_cache.h
+ *		       files.
+ *		       Four new files were added for supporting L2 cache. They are:
+ *		       microblaze_flush_cache_ext.S-> Flushes L2 cache
+ *		       microblaze_flush_cache_ext_range.S -> Flushes a range of
+ *		       memory in L2 cache.
+ *		       microblaze_invalidate_cache_ext.S-> Invalidates L2 cache
+ *		       microblaze_invalidate_cache_ext_range -> Invalidates a
+ *		       range of memory in L2 cache.
+ *		       These changes are done to implement PR #697214.	
+ * 3.10a  asa 05/13/13 Modified cache disable APIs at src/cortexa9/xil_cache.c to
+ *		       fix the CR #706464. L2 cache disabling happens independent
+ *		       of L1 data cache disable operation. Changes are done in the
+ *		       same file in cache handling APIs to do a L2 cache sync 
+ *		       (poll reg7_?cache_?sync). This fixes CR #700542.		       
+ * 3.10a asa  05/20/13 Added API/Macros for enabling and disabling nested 
+ *		       interrupts for ARM. These are done to fix the CR#699680.
+ * 3.10a srt  05/20/13 Made changes in cache maintenance APIs to do a proper cach
+ *		       sync operation. This fixes the CR# 716781.
+ * 3.11a asa  09/07/13 Updated armcc specific BSP files to have proper support
+ *		       for armcc toolchain.
+ *		       Modified asm_vectors.S (gcc) and asm_vectors.s (armcc) to
+ *		       fix issues related to NEON context saving. The assembly
+ *		       routines for IRQ and FIQ handling are modified.
+ *		       Deprecated the older BSP (3.10a).
+ * 3.11a asa  09/22/13 Fix for CR#732704. Cache APIs are modified to avoid 
+ *		       various potential issues. Made changes in the function
+ *		       Xil_SetAttributes in file xil_mmu.c.
+ * 3.11a asa  09/23/13 Added files xil_misc_psreset_api.c and xil_misc_psreset_api.h
+ *		       in src\cortexa9 and src\microblaze folders. 
+ * 3.11a asa  09/28/13 Modified the cache APIs (src\cortexa9) to fix handling of
+ *		       L2 cache sync operation and to fix issues around complete
+ *		       L2 cache flush/invalidation by ways.
+ * 3.12a asa  10/22/13 Modified the files xpseudo_asm_rvct.c and xpseudo_asm_rvct.h
+ *		       to fix linking issues with armcc/DS-5. Modified the armcc
+ *		       makefile to fix issues.
+ * 3.12a asa  11/15/13 Fix for CR#754800. It fixes issues around profiling for MB.
+ * 4.0   hk   12/13/13 Added check for STDOUT_BASEADDRESS where outbyte is used. 
+ * 4.0 	 pkp  22/01/14 Modified return addresses for interrupt handlers (DataAbortHandler
+ *		       and SWIHandler) in asm_vector.S (src\cortexa9\gcc\ and 
+ *		       src\cortexa9\armcc\) to fix CR#767251
+ * 4.0	 pkp  24/01/14 Modified cache APIs (Xil_DCacheInvalidateRange and 
+ *		       Xil_L1DCacheInvalidate) in xil_cache.c (src\cortexa9) to fix the bugs.
+ *		       Few cache lines were missed to invalidate when unaligned address
+ *		       invalidation was accommodated in Xil_DCacheInvalidateRange. 
+ *		       In Xil_L1DCacheInvalidate, while invalidating all L1D cache
+ *		       stack memory (which contains return address) was invalidated. So
+ *		       stack memory is flushed first and then L1D cache is invalidated.
+ *		       This is done to fix CR #763829
+ * 4.0 adk   22/02/2014 Fixed the CR:775379 removed unnecessay _t(unit32_t etc) from 
+ *			mblaze_nt_types.h file and replace uint32_t with u32 in the 
+ *			profile_hist.c to fix the above CR. 
+ * 4.1 bss   04/14/14  Updated driver tcl to remove _interrupt_handler.o from libgloss.a
+ * 		       instead of libxil.a and added prototypes for 
+ *		       microblaze_invalidate_cache_ext and microblaze_flush_cache_ext in
+ *		       mb_interface.h
+ * 4.1 hk    04/18/14  Add sleep function.
+ * 4.1 asa   04/21/14  Fix for CR#764881. Added support for msrset and msrclr. Renamed
+ *		       some of the *.s files inMB BSP source to *.S.
+ * 4.1 asa   04/28/14  Fix for CR#772280. Made changes in file cortexa9/gcc/read.c.
+ * 4.1 bss   04/29/14  Modified driver tcl to use libxil.a if libgloss.a does not exist
+ *			CR#794205
+ * 4.1 asa   05/09/14  Fix for CR#798230. Made changes in cortexa9/xil_cache.c and
+ *		       common/xil_testcache.c
+ *	               Fix for CR#764881.
+ *
+ *****************************************************************************************/
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/close.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/close.c
new file mode 100644
index 000000000..173b55dc2
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/close.c
@@ -0,0 +1,55 @@
+/******************************************************************************
+*
+* (c) Copyright 2009-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+#ifdef __cplusplus
+extern "C" {
+	int _close(int fd);
+}
+#endif
+
+/*
+ * close -- We don't need to do anything, but pretend we did.
+ */
+
+int _close(int fd)
+{
+  (void)fd;
+  return (0);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/config.make b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/config.make
new file mode 100644
index 000000000..81ed997d5
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/config.make
@@ -0,0 +1,3 @@
+LIBSOURCES = *.c *.s *.S
+PROFILE_ARCH_OBJS = profile_mcount_arm.o
+LIBS = standalone_libs
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/cpu_init.S b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/cpu_init.S
new file mode 100644
index 000000000..a4b1a6564
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/cpu_init.S
@@ -0,0 +1,88 @@
+/******************************************************************************
+*
+* (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file cpu_init.s
+*
+* This file contains CPU specific initialization. Invoked from main CRT
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 10/20/09 Initial version
+* 3.04a sdm	01/02/12 Updated to clear cp15 regs with unknown reset values
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+	.text
+	.global __cpu_init
+	.align 2    
+__cpu_init:
+
+/* Clear cp15 regs with unknown reset values */
+	mov	r0, #0x0
+	mcr	p15, 0, r0, c5, c0, 0	/* DFSR */
+	mcr	p15, 0, r0, c5, c0, 1	/* IFSR */
+	mcr	p15, 0, r0, c6, c0, 0	/* DFAR */
+	mcr	p15, 0, r0, c6, c0, 2	/* IFAR */
+	mcr	p15, 0, r0, c9, c13, 2	/* PMXEVCNTR */
+	mcr	p15, 0, r0, c13, c0, 2	/* TPIDRURW */
+	mcr	p15, 0, r0, c13, c0, 3	/* TPIDRURO */
+	mcr	p15, 5, r0, c15, c5, 2	/* Write Lockdown TLB VA */
+
+/* Reset and start Cycle Counter */
+	mov	r2, #0x80000000		/* clear overflow */
+	mcr	p15, 0, r2, c9, c12, 3
+	mov	r2, #0xd		/* D, C, E */
+	mcr	p15, 0, r2, c9, c12, 0
+	mov	r2, #0x80000000		/* enable cycle counter */
+	mcr	p15, 0, r2, c9, c12, 1
+
+	bx	lr
+
+.end
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/errno.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/errno.c
new file mode 100644
index 000000000..78a61a345
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/errno.c
@@ -0,0 +1,59 @@
+/******************************************************************************
+*
+* (c) Copyright 2009-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+/* The errno variable is stored in the reentrancy structure.  This
+   function returns its address for use by the macro errno defined in
+   errno.h.  */
+
+#include 
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+	int * __errno ();
+}
+#endif
+
+int *
+__errno ()
+{
+  return &_REENT->_errno;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/fcntl.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/fcntl.c
new file mode 100644
index 000000000..be641813a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/fcntl.c
@@ -0,0 +1,54 @@
+/******************************************************************************
+*
+* (c) Copyright 2009-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+#include 
+
+/*
+ * fcntl -- Manipulate a file descriptor.
+ *          We don't have a filesystem, so we do nothing.
+ */
+int fcntl (int fd, int cmd, long arg)
+{
+  (void)fd;
+  (void)cmd;
+  (void)arg;
+  return 0;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/fstat.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/fstat.c
new file mode 100644
index 000000000..2f647c70a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/fstat.c
@@ -0,0 +1,58 @@
+/******************************************************************************
+*
+* (c) Copyright 2009-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+	int _fstat(int fd, struct stat *buf);
+}
+#endif
+/*
+ * fstat -- Since we have no file system, we just return an error.
+ */
+int _fstat(int fd, struct stat *buf)
+{
+  (void)fd;
+  buf->st_mode = S_IFCHR; /* Always pretend to be a tty */
+
+  return (0);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/getpid.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/getpid.c
new file mode 100644
index 000000000..6f5fb55de
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/getpid.c
@@ -0,0 +1,59 @@
+/******************************************************************************
+*
+* (c) Copyright 2009-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+/*
+ * getpid -- only one process, so just return 1.
+ */
+#ifdef __cplusplus
+extern "C" {
+	int _getpid();
+}
+#endif
+
+int getpid()
+{
+  return 1;
+}
+
+int _getpid()
+{
+  return 1;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/inbyte.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/inbyte.c
new file mode 100644
index 000000000..a5a6448d4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/inbyte.c
@@ -0,0 +1,14 @@
+#include "xparameters.h"
+#include "xuartps_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+char inbyte(void);
+#ifdef __cplusplus
+}
+#endif 
+
+char inbyte(void) {
+	 return XUartPs_RecvByte(STDIN_BASEADDRESS);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/isatty.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/isatty.c
new file mode 100644
index 000000000..a42edfa3b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/isatty.c
@@ -0,0 +1,64 @@
+/******************************************************************************
+*
+* (c) Copyright 2009-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+	int _isatty(int fd);
+}
+#endif
+
+/*
+ * isatty -- returns 1 if connected to a terminal device,
+ *           returns 0 if not. Since we're hooked up to a
+ *           serial port, we'll say yes _AND return a 1.
+ */
+int isatty(int fd)
+{
+  (void)fd;
+  return (1);
+}
+
+int _isatty(int fd)
+{
+  (void)fd;
+  return (1);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/kill.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/kill.c
new file mode 100644
index 000000000..6b7df0c89
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/kill.c
@@ -0,0 +1,67 @@
+/******************************************************************************
+*
+* (c) Copyright 2009-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+#include 
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+	int _kill(int pid, int sig);
+}
+#endif
+
+/*
+ * kill -- go out via exit...
+ */
+
+int kill(int pid, int sig)
+{
+  if(pid == 1)
+    _exit(sig);
+  return 0;
+}
+
+int _kill(int pid, int sig)
+{
+  if(pid == 1)
+    _exit(sig);
+  return 0;
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/lseek.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/lseek.c
new file mode 100644
index 000000000..45e7ec3f9
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/lseek.c
@@ -0,0 +1,69 @@
+/******************************************************************************
+*
+* (c) Copyright 2009-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+#include 
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+	off_t _lseek(int fd, off_t offset, int whence);
+}
+#endif
+/*
+ * lseek --  Since a serial port is non-seekable, we return an error.
+ */
+off_t lseek(int fd, off_t offset, int whence)
+{
+  (void)fd;
+  (void)offset;
+  (void)whence;
+  errno = ESPIPE;
+  return ((off_t)-1);
+}
+
+off_t _lseek(int fd, off_t offset, int whence)
+{
+  (void)fd;
+  (void)offset;
+  (void)whence;
+  errno = ESPIPE;
+  return ((off_t)-1);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/open.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/open.c
new file mode 100644
index 000000000..0a5b553a6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/open.c
@@ -0,0 +1,61 @@
+/******************************************************************************
+*
+* (c) Copyright 2009-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+	int open(const char *buf, int flags, int mode);
+}
+#endif
+/*
+ * open -- open a file descriptor. We don't have a filesystem, so
+ *         we return an error.
+ */
+int open(const char *buf, int flags, int mode)
+{
+  (void)buf;
+  (void)flags;
+  (void)mode;
+  errno = EIO;
+  return (-1);
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/outbyte.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/outbyte.c
new file mode 100644
index 000000000..3c6430886
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/outbyte.c
@@ -0,0 +1,15 @@
+#include "xparameters.h"
+#include "xuartps_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+void outbyte(char c); 
+
+#ifdef __cplusplus
+}
+#endif 
+
+void outbyte(char c) {
+	 XUartPs_SendByte(STDOUT_BASEADDRESS, c);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/print.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/print.c
new file mode 100644
index 000000000..be29280ca
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/print.c
@@ -0,0 +1,31 @@
+/* print.c -- print a string on the output device.
+ *
+ * Copyright (c) 1995 Cygnus Support
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ *
+ */
+
+/*
+ * print -- do a raw print of a string
+ */
+#include "xil_printf.h"
+
+void print(const char *ptr)
+{
+#ifdef STDOUT_BASEADDRESS
+  while (*ptr) {
+    outbyte (*ptr++);
+  }
+#else
+(void)ptr;
+#endif
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/Makefile
new file mode 100644
index 000000000..9a33fda02
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/Makefile
@@ -0,0 +1,65 @@
+#######################################################################
+#
+# Copyright (c) 2002 Xilinx, Inc.  All rights reserved. 
+# Xilinx, Inc. 
+#
+# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A 
+# COURTESY TO YOU.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS 
+# ONE POSSIBLE   IMPLEMENTATION OF THIS FEATURE, APPLICATION OR 
+# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION 
+# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE 
+# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. 
+# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO 
+# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO 
+# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE 
+# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY 
+# AND FITNESS FOR A PARTICULAR PURPOSE. 
+#
+# $Id: Makefile,v 1.1.2.1 2011/05/17 04:37:55 sadanan Exp $
+#
+# Makefile for profiler
+# 
+#######################################################################
+
+# PROFILE_ARCH_OBJS - Processor Architecture Dependent files defined here
+include ../config.make
+
+AS=mb-as
+COMPILER = mb-gcc 
+ARCHIVER = mb-ar
+CP = cp
+COMPILER_FLAGS=-O2 
+EXTRA_COMPILER_FLAGS=
+LIB = libxil.a
+DUMMYLIB = libxilprofile.a
+
+CC_FLAGS = $(subst -pg, , $(COMPILER_FLAGS))
+ECC_FLAGS = $(subst -pg, , $(EXTRA_COMPILER_FLAGS))
+
+RELEASEDIR = ../../../../lib
+INCLUDEDIR = ../../../../include
+INCLUDES = -I./. -I${INCLUDEDIR}
+
+OBJS = _profile_init.o _profile_clean.o _profile_timer_hw.o profile_hist.o profile_cg.o 
+DUMMYOBJ = dummy.o
+INCLUDEFILES = profile.h mblaze_nt_types.h _profile_timer_hw.h
+
+libs : reallibs dummylibs
+
+reallibs : $(OBJS) $(PROFILE_ARCH_OBJS)
+	$(ARCHIVER) -r $(RELEASEDIR)/$(LIB) $(OBJS) $(PROFILE_ARCH_OBJS)
+
+dummylibs : $(DUMMYOBJ)
+	$(ARCHIVER) -r $(RELEASEDIR)/$(DUMMYLIB) $(DUMMYOBJ)
+
+%.o:%.c
+	$(COMPILER) $(CC_FLAGS) $(ECC_FLAGS) -c $< -o $@ $(INCLUDES)
+
+%.o:%.S
+	$(COMPILER) $(CC_FLAGS) $(ECC_FLAGS) -c $< -o $@ $(INCLUDES)
+
+include: 
+	$(CP) -rf $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -f $(OBJS) $(PROFILE_ARCH_OBJS) $(LIB)
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/_profile_clean.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/_profile_clean.c
new file mode 100644
index 000000000..b4e3e3347
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/_profile_clean.c
@@ -0,0 +1,33 @@
+//
+// Copyright (c) 2002 Xilinx, Inc.  All rights reserved.
+// Xilinx, Inc.
+//
+// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+// COURTESY TO YOU.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE   IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
+// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
+// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
+// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
+// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
+// AND FITNESS FOR A PARTICULAR PURPOSE.
+//
+// $Id: _profile_clean.c,v 1.1.2.1 2011/05/17 04:37:55 sadanan Exp $
+//
+
+#include "profile.h"
+#include "_profile_timer_hw.h"
+#include "xil_exception.h"
+
+/*
+ * This function is the exit routine and is called by the crtinit, when the
+ * program terminates. The name needs to be changed later..
+ */
+void _profile_clean( void )
+{
+	Xil_ExceptionDisable();
+	disable_timer();
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/_profile_init.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/_profile_init.c
new file mode 100644
index 000000000..e3a8a0143
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/_profile_init.c
@@ -0,0 +1,80 @@
+//////////////////////////////////////////////////////////////////////
+//
+// Copyright (c) 2002-2011 Xilinx, Inc.  All rights reserved.
+// Xilinx, Inc.
+//
+// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+// COURTESY TO YOU.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE   IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
+// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
+// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
+// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
+// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
+// AND FITNESS FOR A PARTICULAR PURPOSE.
+//
+// $Id: _profile_init.c,v 1.1.2.1 2011/05/17 04:37:56 sadanan Exp $
+//
+// _program_init.c:
+//	Initialize the Profiling Structures.
+//
+//////////////////////////////////////////////////////////////////////
+
+#include "profile.h"
+
+// XMD Initializes the following Global Variables Value during Program
+// Download with appropriate values.
+
+#ifdef PROC_MICROBLAZE
+
+extern int microblaze_init(void);
+
+#elif defined PROC_PPC
+
+extern int powerpc405_init(void);
+
+#else
+
+extern int cortexa9_init(void);
+
+#endif
+
+
+
+int profile_version = 1;	// Version of S/W Intrusive Profiling library
+
+int binsize = BINSIZE;    			// Histogram Bin Size
+unsigned int cpu_clk_freq = CPU_FREQ_HZ ;	// CPU Clock Frequency
+unsigned int sample_freq_hz = SAMPLE_FREQ_HZ ;	// Histogram Sampling Frequency
+unsigned int timer_clk_ticks = TIMER_CLK_TICKS ;// Timer Clock Ticks for the Timer
+
+// Structure for Storing the Profiling Data
+struct gmonparam *_gmonparam = (struct gmonparam *)0xffffffff;
+int n_gmon_sections = 1;
+
+// This is the initialization code, which is called from the crtinit.
+//
+void _profile_init( void )
+{
+/* 	print("Gmon Init called....\r\n") ; */
+/* 	putnum(n_gmon_sections) ; print("\r\n") ; */
+/* 	if( _gmonparam == 0xffffffff ) */
+/* 		printf("Gmonparam is NULL !!\r\n"); */
+/* 	for( i = 0; i < n_gmon_sections; i++ ){ */
+/* 		putnum(_gmonparam[i].lowpc) ; print("\t") ; */
+/* 		putnum(_gmonparam[i].highpc) ; print("\r\n") ; */
+/* 		putnum( _gmonparam[i].textsize ); print("\r\n") ; */
+/* 		putnum( _gmonparam[i].kcountsize * sizeof(unsigned short));print("\r\n"); */
+/* 	} */
+
+#ifdef PROC_MICROBLAZE
+	microblaze_init();
+#elif defined PROC_PPC
+	powerpc405_init();
+#else
+	cortexa9_init ();
+#endif
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/_profile_timer_hw.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/_profile_timer_hw.c
new file mode 100644
index 000000000..7f9548336
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/_profile_timer_hw.c
@@ -0,0 +1,346 @@
+//////////////////////////////////////////////////////////////////////
+//
+// Copyright (c) 2004-2010 Xilinx, Inc.  All rights reserved.
+// Xilinx, Inc.
+//
+// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+// COURTESY TO YOU.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE   IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
+// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
+// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
+// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
+// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
+// AND FITNESS FOR A PARTICULAR PURPOSE.
+//
+// $Id: _profile_timer_hw.c,v 1.1.2.1 2011/05/17 04:37:56 sadanan Exp $
+//
+// _program_timer_hw.c:
+//	Timer related functions
+//
+//////////////////////////////////////////////////////////////////////
+
+#include "profile.h"
+#include "_profile_timer_hw.h"
+
+#include "xil_exception.h"
+
+#ifdef PROC_PPC
+#include "xtime_l.h"
+#include "xpseudo_asm.h"
+#endif
+
+#ifdef TIMER_CONNECT_INTC
+#include "xintc_l.h"
+#include "xintc.h"
+#endif	// TIMER_CONNECT_INTC
+
+//#ifndef PPC_PIT_INTERRUPT
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+#include "xtmrctr_l.h"
+#endif
+
+extern unsigned int timer_clk_ticks ;
+
+//--------------------------------------------------------------------
+// PowerPC Target - Timer related functions
+//--------------------------------------------------------------------
+#ifdef PROC_PPC405
+
+
+//--------------------------------------------------------------------
+// PowerPC PIT Timer Init.
+//	Defined only if PIT Timer is used for Profiling
+//
+//--------------------------------------------------------------------
+#ifdef PPC_PIT_INTERRUPT
+int ppc_pit_init( void )
+{
+	// 1. Register Profile_intr_handler as Interrupt handler
+	// 2. Set PIT Timer Interrupt and Enable it.
+	Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_PIT_INT,
+			    (Xil_ExceptionHandler)profile_intr_handler,(void *)0);
+	XTime_PITSetInterval( timer_clk_ticks ) ;
+	XTime_PITEnableAutoReload() ;
+	return 0;
+}
+#endif
+
+
+//--------------------------------------------------------------------
+// PowerPC Timer Initialization functions.
+//	For PowerPC, PIT and opb_timer can be used for Profiling. This
+//	is selected by the user in standalone BSP
+//
+//--------------------------------------------------------------------
+int powerpc405_init()
+{
+	Xil_ExceptionInit() ;
+	Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
+
+	// Initialize the Timer.
+	// 1. If PowerPC PIT Timer has to be used, initialize PIT timer.
+	// 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC
+#ifdef PPC_PIT_INTERRUPT
+	ppc_pit_init();
+#else
+#ifdef TIMER_CONNECT_INTC
+	Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+			      (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,(void *)0);
+	XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
+			     (XInterruptHandler)profile_intr_handler,(void*)0);
+#else
+	Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+			      (Xil_ExceptionHandler)profile_intr_handler,(void *)0);
+#endif
+	// Initialize the timer with Timer Ticks
+	opb_timer_init() ;
+#endif
+
+	// Enable Interrupts in the System, if Profile Timer is the only Interrupt
+	// in the System.
+#ifdef ENABLE_SYS_INTR
+#ifdef PPC_PIT_INTERRUPT
+	XTime_PITEnableInterrupt() ;
+#elif TIMER_CONNECT_INTC
+	XIntc_MasterEnable( INTC_BASEADDR );
+	XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
+	XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
+#endif
+	Xil_ExceptionEnableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
+#endif
+	return 0;
+}
+
+#endif	// PROC_PPC
+
+
+
+//--------------------------------------------------------------------
+// PowerPC440 Target - Timer related functions
+//--------------------------------------------------------------------
+#ifdef PROC_PPC440
+
+
+//--------------------------------------------------------------------
+// PowerPC DEC Timer Init.
+//	Defined only if DEC Timer is used for Profiling
+//
+//--------------------------------------------------------------------
+#ifdef PPC_PIT_INTERRUPT
+int ppc_dec_init( void )
+{
+	// 1. Register Profile_intr_handler as Interrupt handler
+	// 2. Set DEC Timer Interrupt and Enable it.
+	Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_DEC_INT,
+			    (Xil_ExceptionHandler)profile_intr_handler,(void *)0);
+	XTime_DECSetInterval( timer_clk_ticks ) ;
+	XTime_DECEnableAutoReload() ;
+	return 0;
+}
+#endif
+
+
+//--------------------------------------------------------------------
+// PowerPC Timer Initialization functions.
+//	For PowerPC, DEC and opb_timer can be used for Profiling. This
+//	is selected by the user in standalone BSP
+//
+//--------------------------------------------------------------------
+int powerpc405_init(void)
+{
+	Xil_ExceptionInit();
+	Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
+
+	// Initialize the Timer.
+	// 1. If PowerPC DEC Timer has to be used, initialize DEC timer.
+	// 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC
+#ifdef PPC_PIT_INTERRUPT
+	ppc_dec_init();
+#else
+#ifdef TIMER_CONNECT_INTC
+	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+				     (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,(void *)0);
+
+	XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
+			     (XInterruptHandler)profile_intr_handler,(void*)0);
+#else
+	Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+			      (Xil_ExceptionHandler)profile_intr_handler,(void *)0);
+	Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+			      (Xil_ExceptionHandler)profile_intr_handler,(void *)0);
+#endif
+	// Initialize the timer with Timer Ticks
+	opb_timer_init() ;
+#endif
+
+	// Enable Interrupts in the System, if Profile Timer is the only Interrupt
+	// in the System.
+#ifdef ENABLE_SYS_INTR
+#ifdef PPC_PIT_INTERRUPT
+	XTime_DECEnableInterrupt() ;
+#elif TIMER_CONNECT_INTC
+	XIntc_MasterEnable( INTC_BASEADDR );
+	XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
+	XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
+#endif
+	Xil_ExceptionEnableMask( XEXC_NON_CRITICAL ) ;
+#endif
+	return 0;
+}
+
+#endif	// PROC_PPC440
+
+//--------------------------------------------------------------------
+// opb_timer Initialization for PowerPC and MicroBlaze. This function
+// is not needed if DEC timer is used in PowerPC
+//
+//--------------------------------------------------------------------
+//#ifndef PPC_PIT_INTERRUPT
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+int opb_timer_init( void )
+{
+	// set the number of cycles the timer counts before interrupting
+	XTmrCtr_SetLoadReg(PROFILE_TIMER_BASEADDR, 0, timer_clk_ticks);
+
+	// reset the timers, and clear interrupts
+	XTmrCtr_SetControlStatusReg(PROFILE_TIMER_BASEADDR, 0,
+				     XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK );
+
+	// start the timers
+	XTmrCtr_SetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, XTC_CSR_ENABLE_TMR_MASK
+			     | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK);
+	return 0;
+}
+#endif
+
+
+//--------------------------------------------------------------------
+// MicroBlaze Target - Timer related functions
+//--------------------------------------------------------------------
+#ifdef PROC_MICROBLAZE
+
+//--------------------------------------------------------------------
+// Initialize the Profile Timer for MicroBlaze Target.
+//	For MicroBlaze, opb_timer is used. The opb_timer can be directly
+//	connected to MicroBlaze or connected through Interrupt Controller.
+//
+//--------------------------------------------------------------------
+int microblaze_init(void)
+{
+	// Register profile_intr_handler
+	// 1. If timer is connected to Interrupt Controller, register the handler
+	//    to Interrupt Controllers vector table.
+	// 2. If timer is directly connected to MicroBlaze, register the handler
+	//    as Interrupt handler
+	Xil_ExceptionInit();
+
+#ifdef TIMER_CONNECT_INTC
+	XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
+			     (XInterruptHandler)profile_intr_handler,(void*)0);
+#else
+	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+				     (Xil_ExceptionHandler)profile_intr_handler,
+				     (void *)0) ;
+#endif
+
+	// Initialize the timer with Timer Ticks
+	opb_timer_init() ;
+
+	// Enable Interrupts in the System, if Profile Timer is the only Interrupt
+	// in the System.
+#ifdef ENABLE_SYS_INTR
+#ifdef TIMER_CONNECT_INTC
+	XIntc_MasterEnable( INTC_BASEADDR );
+	XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
+	XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
+	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+				     (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,(void *)0);
+#endif
+
+#endif
+
+	Xil_ExceptionEnable();
+
+	return 0;
+
+}
+
+#endif	// PROC_MICROBLAZE
+
+
+
+//--------------------------------------------------------------------
+// Cortex A9 Target - Timer related functions
+//--------------------------------------------------------------------
+#ifdef PROC_CORTEXA9
+
+//--------------------------------------------------------------------
+// Initialize the Profile Timer for Cortex A9 Target.
+//	The scu private timer is connected to the Scu GIC controller.
+//
+//--------------------------------------------------------------------
+int scu_timer_init( void )
+{
+	// set the number of cycles the timer counts before interrupting
+	// scu timer runs at half the cpu clock
+	XScuTimer_SetLoadReg(PROFILE_TIMER_BASEADDR, timer_clk_ticks/2);
+
+	// clear any pending interrupts
+	XScuTimer_SetIntrReg(PROFILE_TIMER_BASEADDR, 1);
+
+	// enable interrupts, auto-reload mode and start the timer
+	XScuTimer_SetControlReg(PROFILE_TIMER_BASEADDR, XSCUTIMER_CONTROL_IRQ_ENABLE_MASK |
+				XSCUTIMER_CONTROL_AUTO_RELOAD_MASK | XSCUTIMER_CONTROL_ENABLE_MASK);
+
+	return 0;
+}
+
+int cortexa9_init(void)
+{
+
+	Xil_ExceptionInit();
+
+	XScuGic_DeviceInitialize(0);
+
+	/*
+	 * Connect the interrupt controller interrupt handler to the hardware
+	 * interrupt handling logic in the processor.
+	 */
+	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
+				(Xil_ExceptionHandler)XScuGic_DeviceInterruptHandler,
+				(void *)0);
+
+	/*
+	 * Connect the device driver handler that will be called when an
+	 * interrupt for the device occurs, the handler defined above performs
+	 * the specific interrupt processing for the device.
+	 */
+	XScuGic_RegisterHandler(SCUGIC_CPU_BASEADDR,
+				PROFILE_TIMER_INTR_ID,
+				(Xil_ExceptionHandler)profile_intr_handler,
+				(void *)0);
+
+	/*
+	 * Enable the interrupt for scu timer.
+	 */
+	XScuGic_EnableIntr(SCUGIC_DIST_BASEADDR, PROFILE_TIMER_INTR_ID);
+
+	/*
+	 * Enable interrupts in the Processor.
+	 */
+	Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
+
+	/*
+	 * Initialize the timer with Timer Ticks
+	 */
+	scu_timer_init() ;
+
+	Xil_ExceptionEnable();
+
+	return 0;
+}
+
+#endif	// PROC_CORTEXA9
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/_profile_timer_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/_profile_timer_hw.h
new file mode 100644
index 000000000..19499f7c5
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/_profile_timer_hw.h
@@ -0,0 +1,292 @@
+//////////////////////////////////////////////////////////////////////
+//
+// Copyright (c) 2004-11 Xilinx, Inc.  All rights reserved.
+// Xilinx, Inc.
+//
+// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+// COURTESY TO YOU.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE   IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
+// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
+// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
+// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
+// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
+// AND FITNESS FOR A PARTICULAR PURPOSE.
+//
+// $Id: _profile_timer_hw.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $
+//
+// _program_timer_hw.h:
+//	Timer related functions
+//
+//////////////////////////////////////////////////////////////////////
+
+#ifndef _PROFILE_TIMER_HW_H
+#define _PROFILE_TIMER_HW_H
+
+#include "profile.h"
+
+#ifdef PROC_PPC
+#if defined __GNUC__
+#  define SYNCHRONIZE_IO __asm__ volatile ("eieio")
+#elif defined __DCC__
+#  define SYNCHRONIZE_IO __asm volatile(" eieio")
+#else
+#  define SYNCHRONIZE_IO
+#endif
+#endif
+
+#ifdef PROC_PPC
+#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO;
+#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
+#else
+#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr));
+#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); }
+#endif
+
+#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
+	ProfIo_Out32(((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] +	\
+			   (RegOffset)), (ValueToWrite))
+
+#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset)	\
+	ProfIo_In32((BaseAddress) + XTmrCtr_Offsets[(TmrCtrNumber)] + (RegOffset))
+
+#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
+	ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET,     \
+					   (RegisterValue))
+
+#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber)		\
+	ProfTimerCtr_mReadReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef PROC_PPC
+#include "xexception_l.h"
+#include "xtime_l.h"
+#include "xpseudo_asm.h"
+#endif
+
+#ifdef TIMER_CONNECT_INTC
+#include "xintc_l.h"
+#include "xintc.h"
+#endif	// TIMER_CONNECT_INTC
+
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+#include "xtmrctr_l.h"
+#endif
+
+#ifdef PROC_CORTEXA9
+#include "xscutimer_hw.h"
+#include "xscugic.h"
+#endif
+
+extern unsigned int timer_clk_ticks ;
+
+//--------------------------------------------------------------------
+// PowerPC Target - Timer related functions
+//--------------------------------------------------------------------
+#ifdef PROC_PPC
+
+#ifdef PPC_PIT_INTERRUPT
+unsigned long timer_lo_clk_ticks ;	// Clk ticks when Timer is disabled in CG
+#endif
+
+#ifdef PROC_PPC440
+#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE
+#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS
+#define XREG_SPR_PIT XREG_SPR_DEC
+#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT
+#endif
+
+//--------------------------------------------------------------------
+// Disable the Timer - During Profiling
+//
+// For PIT Timer -
+//	1. XTime_PITDisableInterrupt() ;
+//	2. Store the remaining timer clk tick
+//	3. Stop the PIT Timer
+//--------------------------------------------------------------------
+
+#ifdef PPC_PIT_INTERRUPT
+#define disable_timer() 		\
+	{				\
+		unsigned long val;	\
+		val=mfspr(XREG_SPR_TCR);	\
+		mtspr(XREG_SPR_TCR, val & ~XREG_TCR_PIT_INTERRUPT_ENABLE);	\
+		timer_lo_clk_ticks = mfspr(XREG_SPR_PIT);			\
+		mtspr(XREG_SPR_PIT, 0);	\
+	}
+#else
+#define disable_timer() 	\
+   { \
+      u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
+      u32 tmp_v = ProfIo_In32(addr); \
+      tmp_v = tmp_v & ~XTC_CSR_ENABLE_TMR_MASK; \
+      ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
+   }
+#endif
+
+
+
+//--------------------------------------------------------------------
+// Enable the Timer
+//
+// For PIT Timer -
+//	1. Load the remaining timer clk ticks
+//	2. XTime_PITEnableInterrupt() ;
+//--------------------------------------------------------------------
+#ifdef PPC_PIT_INTERRUPT
+#define enable_timer()				\
+	{					\
+		unsigned long val;		\
+		val=mfspr(XREG_SPR_TCR);	\
+		mtspr(XREG_SPR_PIT, timer_lo_clk_ticks);	\
+		mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \
+	}
+#else
+#define enable_timer()						\
+	{							\
+      u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
+      u32 tmp_v = ProfIo_In32(addr); \
+      tmp_v = tmp_v |  XTC_CSR_ENABLE_TMR_MASK; \
+      ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
+	}
+#endif
+
+
+
+//--------------------------------------------------------------------
+// Send Ack to Timer Interrupt
+//
+// For PIT Timer -
+// 	1. Load the timer clk ticks
+//	2. Enable AutoReload and Interrupt
+//	3. Clear PIT Timer Status bits
+//--------------------------------------------------------------------
+#ifdef PPC_PIT_INTERRUPT
+#define timer_ack()							\
+	{								\
+		unsigned long val;					\
+		mtspr(XREG_SPR_PIT, timer_clk_ticks);			\
+		mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS);	\
+		val=mfspr(XREG_SPR_TCR);				\
+		mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \
+	}
+#else
+#define timer_ack()				\
+	{						\
+		unsigned int csr;			\
+		csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0);	\
+		ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr);	\
+	}
+#endif
+
+//--------------------------------------------------------------------
+#endif	// PROC_PPC
+//--------------------------------------------------------------------
+
+
+
+
+//--------------------------------------------------------------------
+// MicroBlaze Target - Timer related functions
+//--------------------------------------------------------------------
+#ifdef PROC_MICROBLAZE
+
+//--------------------------------------------------------------------
+// Disable the Timer during Call-Graph Data collection
+//
+//--------------------------------------------------------------------
+#define disable_timer()					\
+	{						\
+      u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
+      u32 tmp_v = ProfIo_In32(addr); \
+      tmp_v = tmp_v & ~XTC_CSR_ENABLE_TMR_MASK; \
+      ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
+    }
+
+
+//--------------------------------------------------------------------
+// Enable the Timer after Call-Graph Data collection
+//
+//--------------------------------------------------------------------
+#define enable_timer()					\
+	{						\
+      u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
+      u32 tmp_v = ProfIo_In32(addr); \
+      tmp_v = tmp_v |  XTC_CSR_ENABLE_TMR_MASK; \
+      ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
+	}
+
+
+//--------------------------------------------------------------------
+// Send Ack to Timer Interrupt
+//
+//--------------------------------------------------------------------
+#define timer_ack()				\
+	{						\
+		unsigned int csr;			\
+		csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0);	\
+		ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr);	\
+	}
+
+//--------------------------------------------------------------------
+#endif	// PROC_MICROBLAZE
+//--------------------------------------------------------------------
+
+//--------------------------------------------------------------------
+// Cortex A9 Target - Timer related functions
+//--------------------------------------------------------------------
+#ifdef PROC_CORTEXA9
+
+//--------------------------------------------------------------------
+// Disable the Timer during Call-Graph Data collection
+//
+//--------------------------------------------------------------------
+#define disable_timer()							\
+{								\
+	u32 Reg;							\
+	Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
+	Reg &= ~XSCUTIMER_CONTROL_ENABLE_MASK;\
+	Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
+}								\
+
+
+//--------------------------------------------------------------------
+// Enable the Timer after Call-Graph Data collection
+//
+//--------------------------------------------------------------------
+#define enable_timer()							\
+{								\
+	u32 Reg;							\
+	Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
+	Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \
+	Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
+}								\
+
+
+//--------------------------------------------------------------------
+// Send Ack to Timer Interrupt
+//
+//--------------------------------------------------------------------
+#define timer_ack()						\
+{							\
+	Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_ISR_OFFSET, \
+		XSCUTIMER_ISR_EVENT_FLAG_MASK);\
+}
+
+//--------------------------------------------------------------------
+#endif	// PROC_CORTEXA9
+//--------------------------------------------------------------------
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/dummy.S b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/dummy.S
new file mode 100644
index 000000000..98c5fa86e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/dummy.S
@@ -0,0 +1,50 @@
+//
+// Copyright (c) 2002 Xilinx, Inc.  All rights reserved. 
+// Xilinx, Inc. 
+//
+// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A 
+// COURTESY TO YOU.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS 
+// ONE POSSIBLE   IMPLEMENTATION OF THIS FEATURE, APPLICATION OR 
+// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION 
+// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE 
+// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. 
+// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO 
+// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO 
+// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE 
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY 
+// AND FITNESS FOR A PARTICULAR PURPOSE. 
+//
+// $Id: dummy.S,v 1.1.2.1 2011/05/17 04:37:56 sadanan Exp $
+//
+	.globl dummy_f
+
+#ifdef PROC_MICROBLAZE
+	.text 
+	.align 2
+	.ent dummy_f
+
+dummy_f:
+	nop
+
+	.end dummy_f 
+#endif
+
+#ifdef PROC_PPC		
+	.section .text
+	.align 2
+	.type dummy_f@function
+	
+dummy_f:	
+	b dummy_f
+			
+#endif
+
+#ifdef PROC_CORTEXA9		
+	.section .text
+	.align 2
+	.type dummy_f, %function
+	
+dummy_f:	
+	b dummy_f
+			
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/mblaze_nt_types.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/mblaze_nt_types.h
new file mode 100644
index 000000000..b008b7f55
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/mblaze_nt_types.h
@@ -0,0 +1,42 @@
+//////////////////////////////////////////////////////////////////////
+//
+// Copyright (c) 2002-11 Xilinx, Inc.  All rights reserved.
+// Xilinx, Inc.
+//
+// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+// COURTESY TO YOU.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE   IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
+// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
+// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
+// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
+// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
+// AND FITNESS FOR A PARTICULAR PURPOSE.
+//
+// $Id: mblaze_nt_types.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $
+//
+//////////////////////////////////////////////////////////////////////
+
+#ifndef _MBLAZE_NT_TYPES_H
+#define _MBLAZE_NT_TYPES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef char            byte;
+typedef short           half;
+typedef int             word;
+typedef unsigned char   ubyte;
+typedef unsigned short  uhalf;
+typedef unsigned int    uword;
+typedef ubyte           boolean;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/profile.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/profile.h
new file mode 100644
index 000000000..6f95903d3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/profile.h
@@ -0,0 +1,130 @@
+//////////////////////////////////////////////////////////////////////
+//
+// Copyright (c) 2002-11 Xilinx, Inc.  All rights reserved.
+// Xilinx, Inc.
+//
+// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+// COURTESY TO YOU.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE   IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
+// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
+// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
+// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
+// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
+// AND FITNESS FOR A PARTICULAR PURPOSE.
+//
+// $Id: profile.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $
+//
+//////////////////////////////////////////////////////////////////////
+
+#ifndef	_PROFILE_H
+#define	_PROFILE_H	1
+
+#include 
+#include "profile_config.h"
+
+#ifdef PROC_MICROBLAZE
+#include "mblaze_nt_types.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void _system_init( void ) ;
+void _system_clean( void ) ;
+void mcount(unsigned long frompc, unsigned long selfpc);
+void profile_intr_handler( void ) ;
+
+
+
+/****************************************************************************
+ * Profiling on hardware - Hash table maintained on hardware and data sent
+ * to xmd for gmon.out generation.
+ ****************************************************************************/
+/*
+ * histogram counters are unsigned shorts (according to the kernel).
+ */
+#define	HISTCOUNTER	unsigned short
+
+struct tostruct {
+	unsigned long  selfpc;
+	long	       count;
+	short 	       link;
+	unsigned short pad;
+};
+
+struct fromstruct {
+	unsigned long frompc ;
+	short link ;
+	unsigned short pad ;
+} ;
+
+/*
+ * general rounding functions.
+ */
+#define ROUNDDOWN(x,y)	(((x)/(y))*(y))
+#define ROUNDUP(x,y)	((((x)+(y)-1)/(y))*(y))
+
+/*
+ * The profiling data structures are housed in this structure.
+ */
+struct gmonparam {
+	long int		state;
+
+	// Histogram Information
+	unsigned short		*kcount;	/* No. of bins in histogram */
+	unsigned long		kcountsize;	/* Histogram samples */
+
+	// Call-graph Information
+	struct fromstruct	*froms;
+	unsigned long		fromssize;
+	struct tostruct		*tos;
+	unsigned long		tossize;
+
+	// Initialization I/Ps
+	unsigned long    	lowpc;
+	unsigned long		highpc;
+	unsigned long		textsize;
+	//unsigned long 		cg_froms;
+	//unsigned long 		cg_tos;
+};
+extern struct gmonparam *_gmonparam;
+extern int n_gmon_sections;
+
+/*
+ * Possible states of profiling.
+ */
+#define	GMON_PROF_ON	0
+#define	GMON_PROF_BUSY	1
+#define	GMON_PROF_ERROR	2
+#define	GMON_PROF_OFF	3
+
+/*
+ * Sysctl definitions for extracting profiling information from the kernel.
+ */
+#define	GPROF_STATE	0	/* int: profiling enabling variable */
+#define	GPROF_COUNT	1	/* struct: profile tick count buffer */
+#define	GPROF_FROMS	2	/* struct: from location hash bucket */
+#define	GPROF_TOS	3	/* struct: destination/count structure */
+#define	GPROF_GMONPARAM	4	/* struct: profiling parameters (see above) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 		/* _PROFILE_H */
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/profile_cg.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/profile_cg.c
new file mode 100644
index 000000000..e94bd2865
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/profile_cg.c
@@ -0,0 +1,148 @@
+//
+// Copyright (c) 2002-2010 Xilinx, Inc.  All rights reserved.
+// Xilinx, Inc.
+//
+// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+// COURTESY TO YOU.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE   IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
+// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
+// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
+// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
+// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
+// AND FITNESS FOR A PARTICULAR PURPOSE.
+//
+// $Id: profile_cg.c,v 1.1.2.1 2011/05/17 04:37:57 sadanan Exp $
+//
+
+#include "profile.h"
+#include "_profile_timer_hw.h"
+#ifdef PROC_MICROBLAZE
+#include "mblaze_nt_types.h"
+#endif
+
+/*
+ * The mcount fucntion is excluded from the library, if the user defines
+ * PROFILE_NO_GRAPH.
+ */
+#ifndef PROFILE_NO_GRAPH
+
+#include 
+#include 
+#include 
+
+extern struct gmonparam *_gmonparam;
+
+#ifdef PROFILE_NO_FUNCPTR
+int searchpc( struct fromto_struct *cgtable, int cgtable_size, unsigned long frompc )
+{
+	int index = 0 ;
+
+	while( (index < cgtable_size) && (cgtable[index].frompc != frompc) ){
+		index++ ;
+	}
+	if( index == cgtable_size )
+		return -1 ;
+	else
+		return index ;
+}
+#else
+int searchpc( struct fromstruct *froms, int fromssize, unsigned long frompc )
+{
+	int index = 0 ;
+
+	while( (index < fromssize) && (froms[index].frompc != frompc) ){
+		index++ ;
+	}
+	if( index == fromssize )
+		return -1 ;
+	else
+		return index ;
+}
+#endif		/* PROFILE_NO_FUNCPTR */
+
+
+void mcount( unsigned long frompc, unsigned long selfpc )
+{
+	register struct gmonparam *p = NULL;
+	register long toindex, fromindex;
+	int j;
+
+	disable_timer();
+
+	//print("CG: "); putnum(frompc); print("->"); putnum(selfpc); print("\r\n");
+	// check that frompcindex is a reasonable pc value.
+	// for example:	signal catchers get called from the stack,
+	//		not from text space.  too bad.
+	//
+	for(j = 0; j < n_gmon_sections; j++ ){
+		if((frompc >= _gmonparam[j].lowpc) && (frompc < _gmonparam[j].highpc)) {
+			p = &_gmonparam[j];
+			break;
+		}
+	}
+	if( j == n_gmon_sections )
+		goto done;
+
+#ifdef PROFILE_NO_FUNCPTR
+	fromindex = searchpc( p->cgtable, p->cgtable_size, frompc ) ;
+	if( fromindex == -1 ) {
+		fromindex = p->cgtable_size ;
+		p->cgtable_size++ ;
+		p->cgtable[fromindex].frompc = frompc ;
+		p->cgtable[fromindex].selfpc = selfpc ;
+		p->cgtable[fromindex].count = 1 ;
+		goto done ;
+	}
+	p->cgtable[fromindex].count++ ;
+#else
+	fromindex = searchpc( p->froms, p->fromssize, frompc ) ;
+	if( fromindex == -1 ) {
+		fromindex = p->fromssize ;
+		p->fromssize++ ;
+		//if( fromindex >= N_FROMS ) {
+		//print("Error : From PC table overflow\r\n") ;
+		//goto overflow ;
+		//}
+		p->froms[fromindex].frompc = frompc ;
+		p->froms[fromindex].link = -1 ;
+	}else {
+		toindex = p->froms[fromindex].link ;
+		while(toindex != -1) {
+			toindex = (p->tossize - toindex)-1 ;
+			if( p->tos[toindex].selfpc == selfpc ) {
+				p->tos[toindex].count++ ;
+				goto done ;
+			}
+			toindex = p->tos[toindex].link ;
+		}
+	}
+
+	//if( toindex == -1 ) {
+	p->tos-- ;
+	p->tossize++ ;
+	//if( toindex >= N_TOS ) {
+	//print("Error : To PC table overflow\r\n") ;
+	//goto overflow ;
+	//}
+	p->tos[0].selfpc = selfpc ;
+	p->tos[0].count = 1 ;
+	p->tos[0].link = p->froms[fromindex].link ;
+	p->froms[fromindex].link = p->tossize-1 ;
+#endif
+
+ done:
+	p->state = GMON_PROF_ON;
+	goto enable_timer ;
+ //overflow:
+	p->state = GMON_PROF_ERROR;
+ enable_timer:
+	enable_timer();
+	return ;
+}
+
+
+#endif		/* PROFILE_NO_GRAPH */
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/profile_config.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/profile_config.h
new file mode 100644
index 000000000..76ddbe80c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/profile_config.h
@@ -0,0 +1,36 @@
+//////////////////////////////////////////////////////////////////////
+//
+// Copyright (c) 2002-11 Xilinx, Inc.  All rights reserved.
+// Xilinx, Inc.
+//
+// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+// COURTESY TO YOU.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE   IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
+// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
+// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
+// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
+// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
+// AND FITNESS FOR A PARTICULAR PURPOSE.
+//
+// $Id: profile_config.h,v 1.1.2.2 2011/05/30 06:46:18 svemula Exp $
+//
+//////////////////////////////////////////////////////////////////////
+
+#ifndef _PROFILE_CONFIG_H
+#define _PROFILE_CONFIG_H
+
+#define BINSIZE 4
+#define SAMPLE_FREQ_HZ 100000
+#define TIMER_CLK_TICKS 1000
+
+#define PROFILE_NO_FUNCPTR_FLAG 0
+
+#define PROFILE_TIMER_BASEADDR 0x00608000
+#define PROFILE_TIMER_INTR_ID 0
+
+#define TIMER_CONNECT_INTC
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/profile_hist.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/profile_hist.c
new file mode 100644
index 000000000..a3832008e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/profile_hist.c
@@ -0,0 +1,58 @@
+//
+// Copyright (c) 2002-2010 Xilinx, Inc.  All rights reserved.
+// Xilinx, Inc.
+//
+// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+// COURTESY TO YOU.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE   IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
+// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
+// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
+// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
+// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
+// AND FITNESS FOR A PARTICULAR PURPOSE.
+//
+// $Id: profile_hist.c,v 1.1.2.1 2011/05/17 04:37:57 sadanan Exp $
+//
+#include "profile.h"
+#include "_profile_timer_hw.h"
+
+#ifdef PROC_MICROBLAZE
+#include "mblaze_nt_types.h"
+#endif
+
+#ifdef PROC_PPC
+#include "xpseudo_asm.h"
+#define SPR_SRR0 0x01A
+#endif
+
+#include "xil_types.h" 
+
+extern int binsize ;
+u32 prof_pc ;
+
+void profile_intr_handler( void )
+{
+
+	int j;
+
+#ifdef PROC_MICROBLAZE
+	asm( "swi r14, r0, prof_pc" ) ;
+#elif defined PROC_PPC
+	prof_pc = mfspr(SPR_SRR0);
+#else
+	// for cortexa9, lr is saved in asm interrupt handler
+#endif
+	//print("PC: "); putnum(prof_pc); print("\r\n");
+	for(j = 0; j < n_gmon_sections; j++ ){
+		if((prof_pc >= _gmonparam[j].lowpc) && (prof_pc < _gmonparam[j].highpc)) {
+			_gmonparam[j].kcount[(prof_pc-_gmonparam[j].lowpc)/(4 * binsize)]++;
+			break;
+		}
+	}
+	// Ack the Timer Interrupt
+	timer_ack();
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/profile_mcount_arm.S b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/profile_mcount_arm.S
new file mode 100644
index 000000000..fef9ad861
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/profile_mcount_arm.S
@@ -0,0 +1,33 @@
+//
+// Copyright (c) 2012 Xilinx, Inc.  All rights reserved.
+// Xilinx, Inc.
+//
+// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+// COURTESY TO YOU.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE   IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
+// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
+// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
+// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
+// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
+// AND FITNESS FOR A PARTICULAR PURPOSE.
+//
+// $Id: profile_mcount_arm.S,v 1.1.2.1 2011/05/17 04:37:57 sadanan Exp $
+//
+
+// based on "ARM Profiling Implementation" from Sourcery G++ Lite for ARM EABI
+
+.globl __gnu_mcount_nc
+.type __gnu_mcount_nc, %function
+
+__gnu_mcount_nc:
+	push	{r0, r1, r2, r3, lr}
+	subs	r1, lr, #0			/* callee - current lr */
+	ldr	r0, [sp, #20]			/* caller - at the top of the stack */
+	bl	mcount				/* when __gnu_mcount_nc is called */
+	pop	{r0, r1, r2, r3, ip, lr}
+	bx	ip
+
+	.end __gnu_mcount_nc
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/profile_mcount_mb.S b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/profile_mcount_mb.S
new file mode 100644
index 000000000..7667a194e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/profile_mcount_mb.S
@@ -0,0 +1,55 @@
+//
+// Copyright (c) 2002 Xilinx, Inc.  All rights reserved. 
+// Xilinx, Inc. 
+//
+// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A 
+// COURTESY TO YOU.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS 
+// ONE POSSIBLE   IMPLEMENTATION OF THIS FEATURE, APPLICATION OR 
+// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION 
+// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE 
+// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. 
+// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO 
+// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO 
+// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE 
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY 
+// AND FITNESS FOR A PARTICULAR PURPOSE. 
+//
+// $Id: profile_mcount_mb.S,v 1.1.2.1 2011/05/17 04:37:58 sadanan Exp $
+//
+	.globl _mcount 
+	.text 
+	.align 2
+	.ent _mcount
+
+	#ifndef PROFILE_NO_GRAPH
+	
+_mcount:
+	addi r1, r1, -48
+	swi r11, r1, 44
+	swi r12, r1, 40
+	swi r5, r1, 36
+	swi r6, r1, 32
+	swi r7, r1, 28
+	swi r8, r1, 24
+	swi r9, r1, 20
+	swi r10, r1, 16
+	swi r15, r1, 12
+	add r5, r0, r15
+	brlid r15, mcount
+	add r6, r0, r16
+
+	lwi r11, r1, 44
+	lwi r12, r1, 40	
+	lwi r5, r1, 36
+	lwi r6, r1, 32
+	lwi r7, r1, 28
+	lwi r8, r1, 24
+	lwi r9, r1, 20
+	lwi r10, r1, 16
+	lwi r15, r1, 12
+	rtsd r15, 4
+	addi r1, r1, 48
+
+	#endif	/* PROFILE_NO_GRAPH */
+	
+	.end _mcount 
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/profile_mcount_ppc.S b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/profile_mcount_ppc.S
new file mode 100644
index 000000000..73e1dc698
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/profile/profile_mcount_ppc.S
@@ -0,0 +1,58 @@
+//
+// Copyright (c) 2002 Xilinx, Inc.  All rights reserved. 
+// Xilinx, Inc. 
+//
+// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A 
+// COURTESY TO YOU.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS 
+// ONE POSSIBLE   IMPLEMENTATION OF THIS FEATURE, APPLICATION OR 
+// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION 
+// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE 
+// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. 
+// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO 
+// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO 
+// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE 
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY 
+// AND FITNESS FOR A PARTICULAR PURPOSE. 
+//
+// $Id: profile_mcount_ppc.S,v 1.1.2.1 2011/05/17 04:37:58 sadanan Exp $
+//
+	.globl _mcount
+	
+	#define _MCOUNT_STACK_FRAME 48			
+	.section .text 
+	.align 2
+	.type _mcount@function
+
+
+_mcount:
+	stwu 1,	-_MCOUNT_STACK_FRAME(1)
+	stw 3, 8(1)
+	stw 4, 12(1)
+	stw 5, 16(1)
+	stw 6, 20(1)
+	stw 7, 24(1)
+	stw 8, 28(1)
+	stw 9, 32(1)
+	stw 10, 36(1)
+	stw 11, 40(1)
+	stw 12, 44(1)
+	mflr 4
+	stw 4, (_MCOUNT_STACK_FRAME+4)(1)
+	lwz 3, (_MCOUNT_STACK_FRAME)(1)
+	lwz 3, 4(3)	
+	bl mcount
+	lwz 4, (_MCOUNT_STACK_FRAME+4)(1)
+	mtlr 4
+	lwz 12, 44(1)
+	lwz 11, 40(1)
+	lwz 10, 36(1)
+	lwz 9, 32(1)
+	lwz 8, 28(1)
+	lwz 7, 24(1)
+	lwz 6, 20(1)
+	lwz 5, 16(1)
+	lwz 4, 12(1)
+	lwz 3, 8(1)	
+	addi 1,1, _MCOUNT_STACK_FRAME
+	blr
+	
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/putnum.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/putnum.c
new file mode 100644
index 000000000..f2af0ae27
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/putnum.c
@@ -0,0 +1,41 @@
+/* putnum.c -- put a hex number on the output device.
+ * 
+ * Copyright (c) 1995 Cygnus Support
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+ * putnum -- print a 32 bit number in hex
+ */
+
+extern void print (char* );
+
+void putnum(unsigned int num)
+{
+  char  buf[9];
+  int   cnt;
+  char  *ptr;
+  int   digit;
+  
+  ptr = buf;
+  for (cnt = 7 ; cnt >= 0 ; cnt--) {
+    digit = (num >> (cnt * 4)) & 0xf;
+    
+    if (digit <= 9)
+      *ptr++ = (char) ('0' + digit);
+    else
+      *ptr++ = (char) ('a' - 10 + digit);
+  }
+
+  *ptr = (char) 0;
+  print (buf);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/read.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/read.c
new file mode 100644
index 000000000..8933ab861
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/read.c
@@ -0,0 +1,106 @@
+/******************************************************************************
+*
+* (c) Copyright 2009-14  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+/* read.c -- read bytes from a input device.
+ */
+
+#include "xparameters.h"
+#include "xil_printf.h"
+
+#ifdef __cplusplus
+extern "C" {
+	int _read (int fd, char* buf, int nbytes);
+}
+#endif
+
+/*
+ * read  -- read bytes from the serial port. Ignore fd, since
+ *          we only have stdin.
+ */
+int
+read (int fd, char* buf, int nbytes)
+{
+#ifdef STDIN_BASEADDRESS
+  int i = 0;
+
+  (void)fd;
+  for (i = 0; i < nbytes; i++) {
+    *(buf + i) = inbyte();
+    if ((*(buf + i) == '\n' || *(buf + i) == '\r'))
+    {
+        i++;
+        break;
+    }
+  }
+
+  return (i);
+#else
+  (void)fd;
+  (void)buf;
+  (void)nbytes;
+  return 0;
+#endif
+}
+
+int
+_read (int fd, char* buf, int nbytes)
+{
+#ifdef STDIN_BASEADDRESS
+  int i = 0;
+
+  (void)fd;
+  for (i = 0; i < nbytes; i++) {
+    *(buf + i) = inbyte();
+    if ((*(buf + i) == '\n' || *(buf + i) == '\r'))
+    {
+        i++;
+        break;
+    }
+  }
+
+  return (i);
+#else
+  (void)fd;
+  (void)buf;
+  (void)nbytes;
+  return 0;
+#endif
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/sbrk.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/sbrk.c
new file mode 100644
index 000000000..a6fc4e349
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/sbrk.c
@@ -0,0 +1,76 @@
+/******************************************************************************
+*
+* (c) Copyright 2009-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+#include 
+#ifdef __cplusplus
+extern "C" {
+	char *sbrk (int nbytes);
+}
+#endif
+
+extern char _heap_start[];
+extern char _heap_end[];
+extern char HeapBase[];
+extern char HeapLimit[];
+
+static char *heap_ptr;
+
+char *sbrk (int nbytes)
+{
+  char *base;
+
+  if (!heap_ptr)
+    /*heap_ptr = (char *)&_heap_start;*/
+    heap_ptr = (char *)&HeapBase;
+
+  base = heap_ptr;
+  heap_ptr += nbytes;
+
+/*  if (heap_ptr <= ((char *)&_heap_end + 1))*/
+  if (heap_ptr <= ((char *)&HeapLimit + 1))
+    return base;
+
+  else
+  {
+    errno = ENOMEM;
+    return ((char *)-1);
+  }
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/sleep.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/sleep.c
new file mode 100644
index 000000000..64c9625e4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/sleep.c
@@ -0,0 +1,89 @@
+/******************************************************************************
+*
+* (c) Copyright 2009-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************
+*
+* @file sleep.c
+*
+* This function provides a second delay using the Global Timer register in
+* the ARM Cortex A9 MP core.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  11/11/09 First release
+* 3.07a sgd      07/05/12 Updated sleep function to make use Global Timer
+* 

+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "sleep.h"
+#include "xtime_l.h"
+#include "xparameters.h"
+
+/*****************************************************************************/
+/*
+*
+* This API is used to provide delays in seconds
+*
+* @param	seconds requested
+*
+* @return	0 always
+*
+* @note		None.
+*
+****************************************************************************/
+int sleep(unsigned int seconds)
+{
+  XTime tEnd, tCur;
+
+  XTime_GetTime(&tCur);
+  tEnd  = tCur + ((XTime) seconds) * COUNTS_PER_SECOND;
+  do
+  {
+    XTime_GetTime(&tCur);
+  } while (tCur < tEnd);
+
+  return 0;
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/sleep.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/sleep.h
new file mode 100644
index 000000000..4d9dd5abd
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/sleep.h
@@ -0,0 +1,58 @@
+/******************************************************************************
+*
+* (c) Copyright 2009-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+#ifndef SLEEP_H
+#define SLEEP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void nanosleep(unsigned int nanoseconds);
+int usleep(unsigned int useconds);
+int sleep(unsigned int seconds);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/smc.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/smc.c
new file mode 100644
index 000000000..c6490285e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/smc.c
@@ -0,0 +1,146 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file smc.c
+*
+* This file contains APIs for configuring the PL353 Static Memory Controller
+* interfaces for NAND flash, SRAM and NOR flash.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  08/02/10 Initial version
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "smc.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * Register values for using NOR interface of SMC Controller
+ */
+#define NOR_SET_CYCLES ((0x0 << 20) | /* set_t6 or we_time from sram_cycles */ \
+			(0x1 << 17) | /* set_t5 or t_tr from sram_cycles */    \
+			(0x2 << 14) | /* set_t4 or t_pc from sram_cycles */    \
+			(0x5 << 11) | /* set_t3 or t_wp from sram_cycles */    \
+			(0x2 << 8)  | /* set_t2 t_ceoe from sram_cycles */     \
+			(0x7 << 4)  | /* set_t1 t_wc from sram_cycles */       \
+			(0x7))	      /* set_t0 t_rc from sram_cycles */
+
+#define NOR_SET_OPMODE ((0x1 << 13) | /* set_burst_align,set to 32 beats */    \
+			(0x1 << 12) | /* set_bls,set to default */	       \
+			(0x0 << 11) | /* set_adv bit, set to default */	       \
+			(0x0 << 10) | /* set_baa, we don't use baa_n */	       \
+			(0x0 << 7)  | /* set_wr_bl,write brust len,set to 0 */ \
+			(0x0 << 6)  | /* set_wr_sync, set to 0 */	       \
+			(0x0 << 3)  | /* set_rd_bl,read brust len,set to 0 */  \
+			(0x0 << 2)  | /* set_rd_sync, set to 0 */	       \
+			(0x0))	      /* set_mw, memory width, 16bits width*/
+				      /* 0x00002000 */
+#define NOR_DIRECT_CMD ((0x0 << 23) | /* Chip 0 from interface 0 */	       \
+			(0x2 << 21) | /* UpdateRegs operation */	       \
+			(0x0 << 20) | /* No ModeReg write */		       \
+			(0x0))	      /* Addr, not used in UpdateRegs */
+
+/* Register values for using SRAM interface of SMC Controller */
+#define SRAM_SET_CYCLES (0x00125155)
+#define SRAM_SET_OPMODE (0x00003000)
+#define SRAM_DIRECT_CMD (0x00C00000)	/* Chip 1 */
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+/****************************************************************************
+*
+* Configure the SMC interface for SRAM.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XSmc_SramInit (void)
+{
+	Xil_Out32(XPAR_XPARPORTPS_CTRL_BASEADDR + XSMCPSS_MC_SET_CYCLES,
+		  SRAM_SET_CYCLES);
+	Xil_Out32(XPAR_XPARPORTPS_CTRL_BASEADDR + XSMCPSS_MC_SET_OPMODE,
+		  SRAM_SET_OPMODE);
+	Xil_Out32(XPAR_XPARPORTPS_CTRL_BASEADDR + XSMCPSS_MC_DIRECT_CMD,
+		  SRAM_DIRECT_CMD);
+}
+
+/****************************************************************************
+*
+* Configure the SMC interface for NOR flash.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XSmc_NorInit(void)
+{
+	Xil_Out32(XPAR_XPARPORTPS_CTRL_BASEADDR + XSMCPSS_MC_SET_CYCLES,
+		  NOR_SET_CYCLES);
+	Xil_Out32(XPAR_XPARPORTPS_CTRL_BASEADDR + XSMCPSS_MC_SET_OPMODE,
+		  NOR_SET_OPMODE);
+	Xil_Out32(XPAR_XPARPORTPS_CTRL_BASEADDR + XSMCPSS_MC_DIRECT_CMD,
+		  NOR_DIRECT_CMD);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/smc.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/smc.h
new file mode 100644
index 000000000..fcfccebaa
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/smc.h
@@ -0,0 +1,124 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file smc.h
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  11/03/09 Initial release.
+* 

+*
+* @note		None.
+*
+******************************************************************************/
+
+#ifndef SMC_H /* prevent circular inclusions */
+#define SMC_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xil_io.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/* Memory controller configuration register offset */
+#define XSMCPSS_MC_STATUS		0x000	/* Controller status reg, RO */
+#define XSMCPSS_MC_INTERFACE_CONFIG	0x004	/* Interface config reg, RO */
+#define XSMCPSS_MC_SET_CONFIG		0x008	/* Set configuration reg, WO */
+#define XSMCPSS_MC_CLR_CONFIG		0x00C	/* Clear config reg, WO */
+#define XSMCPSS_MC_DIRECT_CMD		0x010	/* Direct command reg, WO */
+#define XSMCPSS_MC_SET_CYCLES		0x014	/* Set cycles register, WO */
+#define XSMCPSS_MC_SET_OPMODE		0x018	/* Set opmode register, WO */
+#define XSMCPSS_MC_REFRESH_PERIOD_0	0x020	/* Refresh period_0 reg, RW */
+#define XSMCPSS_MC_REFRESH_PERIOD_1	0x024	/* Refresh period_1 reg, RW */
+
+/* Chip select configuration register offset */
+#define XSMCPSS_CS_IF0_CHIP_0_OFFSET	0x100	/* Interface 0 chip 0 config */
+#define XSMCPSS_CS_IF0_CHIP_1_OFFSET	0x120	/* Interface 0 chip 1 config */
+#define XSMCPSS_CS_IF0_CHIP_2_OFFSET	0x140	/* Interface 0 chip 2 config */
+#define XSMCPSS_CS_IF0_CHIP_3_OFFSET	0x160	/* Interface 0 chip 3 config */
+#define XSMCPSS_CS_IF1_CHIP_0_OFFSET	0x180	/* Interface 1 chip 0 config */
+#define XSMCPSS_CS_IF1_CHIP_1_OFFSET	0x1A0	/* Interface 1 chip 1 config */
+#define XSMCPSS_CS_IF1_CHIP_2_OFFSET	0x1C0	/* Interface 1 chip 2 config */
+#define XSMCPSS_CS_IF1_CHIP_3_OFFSET	0x1E0	/* Interface 1 chip 3 config */
+
+/* User configuration register offset */
+#define XSMCPSS_UC_STATUS_OFFSET	0x200	/* User status reg, RO */
+#define XSMCPSS_UC_CONFIG_OFFSET	0x204	/* User config reg, WO */
+
+/* Integration test register offset */
+#define XSMCPSS_IT_OFFSET		0xE00
+
+/* ID configuration register offset */
+#define XSMCPSS_ID_PERIP_0_OFFSET	0xFE0
+#define XSMCPSS_ID_PERIP_1_OFFSET	0xFE4
+#define XSMCPSS_ID_PERIP_2_OFFSET	0xFE8
+#define XSMCPSS_ID_PERIP_3_OFFSET	0xFEC
+#define XSMCPSS_ID_PCELL_0_OFFSET	0xFF0
+#define XSMCPSS_ID_PCELL_1_OFFSET	0xFF4
+#define XSMCPSS_ID_PCELL_2_OFFSET	0xFF8
+#define XSMCPSS_ID_PCELL_3_OFFSET	0xFFC
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void XSmc_SramInit (void);
+void XSmc_NorInit(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* SMC_H */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/translation_table.s b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/translation_table.s
new file mode 100644
index 000000000..c842ee9d4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/translation_table.s
@@ -0,0 +1,141 @@
+/******************************************************************************
+*
+* (c) Copyright 2009-2013 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file translation_table.s
+*
+* This file contains the initialization for the MMU table in RAM
+* needed by the Cortex A9 processor
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm  10/20/09 Initial version
+* 3.04a sdm  01/13/12 Updated MMU table to mark DDR memory as Shareable
+* 3.07a sgd  07/05/2012 Configuring device address spaces as shareable device
+*		       instead of strongly-ordered.
+* 3.07a asa  07/17/2012 Changed the property of the ".mmu_tbl" section.
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+	.globl  MMUTable
+
+	.section .mmu_tbl,"a"
+
+MMUTable:
+	/* Each table entry occupies one 32-bit word and there are
+	 * 4096 entries, so the entire table takes up 16KB.
+	 * Each entry covers a 1MB section.
+	 */
+
+.set SECT, 0
+
+.rept	0x0400			/* 0x00000000 - 0x3fffffff (DDR Cacheable) */
+.word	SECT + 0x15de6		/* S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 */
+.set	SECT, SECT+0x100000
+.endr
+
+.rept	0x0400			/* 0x40000000 - 0x7fffffff (FPGA slave0) */
+.word	SECT + 0xc02		/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
+.set	SECT, SECT+0x100000
+.endr
+
+.rept	0x0400			/* 0x80000000 - 0xbfffffff (FPGA slave1) */
+.word	SECT + 0xc02		/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
+.set	SECT, SECT+0x100000
+.endr
+
+.rept	0x0200			/* 0xc0000000 - 0xdfffffff (unassigned/reserved).
+				 * Generates a translation fault if accessed */
+.word	SECT + 0x0		/* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
+.set	SECT, SECT+0x100000
+.endr
+
+.rept	0x0020			/* 0xe0000000 - 0xe1ffffff (Memory mapped devices)
+				 * UART/USB/IIC/SPI/CAN/GEM/GPIO/QSPI/SD/NAND */
+.word	SECT + 0xc06		/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
+.set	SECT, SECT+0x100000
+.endr
+
+.rept	0x0020			/* 0xe2000000 - 0xe3ffffff (NOR) */
+.word	SECT + 0xc06		/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
+.set	SECT, SECT+0x100000
+.endr
+
+.rept	0x0020			/* 0xe4000000 - 0xe5ffffff (SRAM) */
+.word	SECT + 0xc0e		/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 */
+.set	SECT, SECT+0x100000
+.endr
+
+.rept	0x0120			/* 0xe6000000 - 0xf7ffffff (unassigned/reserved).
+				 * Generates a translation fault if accessed */
+.word	SECT + 0x0		/* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
+.set	SECT, SECT+0x100000
+.endr
+
+.rept	0x0010			/* 0xf8000000 - 0xf8ffffff (AMBA APB Peripherals) */
+.word	SECT + 0xc06		/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */
+.set	SECT, SECT+0x100000
+.endr
+
+.rept	0x0030			/* 0xf9000000 - 0xfbffffff (unassigned/reserved).
+				 * Generates a translation fault if accessed */
+.word	SECT + 0x0		/* S=b0 TEX=b000 AP=b00, Domain=b0, C=b0, B=b0 */
+.set	SECT, SECT+0x100000
+.endr
+
+.rept	0x003f			/* 0xfc000000 - 0xffefffff (Linear QSPI - XIP) */
+.word	SECT + 0xc0a		/* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 */
+.set	SECT, SECT+0x100000
+.endr
+
+				/* 256K OCM when mapped to high address space
+				 * inner-cacheable */
+.word	SECT + 0x4c0e		/* S=b0 TEX=b100 AP=b11, Domain=b0, C=b1, B=b1 */
+.set	SECT, SECT+0x100000
+
+.end
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/uart.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/uart.c
new file mode 100644
index 000000000..ba7240ed2
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/uart.c
@@ -0,0 +1,159 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file uart.c
+*
+* This file contains APIs for configuring the UART.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  08/02/10 Initial version
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#include "xparameters.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/* Register offsets */
+#define UART_CR_OFFSET		0x00
+#define UART_MR_OFFSET		0x04
+#define UART_BAUDGEN_OFFSET	0x18
+#define UART_BAUDDIV_OFFSET	0x34
+
+#define MAX_BAUD_ERROR_RATE	3	/* max % error allowed */
+#define UART_BAUDRATE	115200
+
+void Init_Uart(void);
+
+void Init_Uart(void)
+{
+#ifdef STDOUT_BASEADDRESS
+	u8 IterBAUDDIV;		/* Iterator for available baud divisor values */
+	u32 BRGR_Value;		/* Calculated value for baud rate generator */
+	u32 CalcBaudRate;	/* Calculated baud rate */
+	u32 BaudError;		/* Diff between calculated and requested baud
+				 * rate */
+	u32 Best_BRGR = 0;	/* Best value for baud rate generator */
+	u8 Best_BAUDDIV = 0;	/* Best value for baud divisor */
+	u32 Best_Error = 0xFFFFFFFF;
+	u32 PercentError;
+	u32 InputClk;
+   u32 BaudRate = UART_BAUDRATE;
+
+#if (STDOUT_BASEADDRESS == XPAR_XUARTPS_0_BASEADDR)
+	InputClk = XPAR_XUARTPS_0_UART_CLK_FREQ_HZ;
+#elif (STDOUT_BASEADDRESS == XPAR_XUARTPS_1_BASEADDR)
+	InputClk = XPAR_XUARTPS_1_UART_CLK_FREQ_HZ;
+#else
+	/* STDIO is not set or axi_uart is being used for STDIO */
+	return;
+#endif
+
+	/*
+	 * Determine the Baud divider. It can be 4to 254.
+	 * Loop through all possible combinations
+	 */
+	for (IterBAUDDIV = 4; IterBAUDDIV < 255; IterBAUDDIV++) {
+
+		/*
+		 * Calculate the value for BRGR register
+		 */
+		BRGR_Value = InputClk / (BaudRate * (IterBAUDDIV + 1));
+
+		/*
+		 * Calculate the baud rate from the BRGR value
+		 */
+		CalcBaudRate = InputClk/ (BRGR_Value * (IterBAUDDIV + 1));
+
+		/*
+		 * Avoid unsigned integer underflow
+		 */
+		if (BaudRate > CalcBaudRate) {
+			BaudError = BaudRate - CalcBaudRate;
+		} else {
+			BaudError = CalcBaudRate - BaudRate;
+		}
+
+		/*
+		 * Find the calculated baud rate closest to requested baud rate.
+		 */
+		if (Best_Error > BaudError) {
+
+			Best_BRGR = BRGR_Value;
+			Best_BAUDDIV = IterBAUDDIV;
+			Best_Error = BaudError;
+		}
+	}
+
+	/*
+	 * Make sure the best error is not too large.
+	 */
+	PercentError = (Best_Error * 100) / BaudRate;
+	if (MAX_BAUD_ERROR_RATE < PercentError) {
+		return;
+	}
+
+	/* set CD and BDIV */
+	Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDGEN_OFFSET, Best_BRGR);
+	Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDDIV_OFFSET, Best_BAUDDIV);
+
+	/*
+	 * 8 data, 1 stop, 0 parity bits
+	 * sel_clk=uart_clk=APB clock
+	 */
+	Xil_Out32(STDOUT_BASEADDRESS + UART_MR_OFFSET, 0x20);
+
+	/* enable Tx/Rx and reset Tx/Rx data path */
+	Xil_Out32((STDOUT_BASEADDRESS + UART_CR_OFFSET), 0x17);
+
+	return;
+#endif
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/unlink.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/unlink.c
new file mode 100644
index 000000000..908457004
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/unlink.c
@@ -0,0 +1,58 @@
+/******************************************************************************
+*
+* (c) Copyright 2009-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+	int unlink(char *path);
+}
+#endif
+/*
+ * unlink -- since we have no file system,
+ *           we just return an error.
+ */
+int unlink(char *path)
+{
+  (void)path;
+  errno = EIO;
+  return (-1);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/usleep.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/usleep.c
new file mode 100644
index 000000000..84c0f20e3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/usleep.c
@@ -0,0 +1,113 @@
+/******************************************************************************
+*
+* (c) Copyright 2009-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file usleep.c
+*
+* This function provides a microsecond delay using the Global Timer register in
+* the ARM Cortex A9 MP core.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  11/11/09 First release
+* 3.07a sgd      07/05/12 Upadted micro sleep function to make use Global Timer
+* 

+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "sleep.h"
+#include "xtime_l.h"
+#include "xparameters.h"
+#include "xpseudo_asm.h"
+#include "xreg_cortexa9.h"
+
+/* Global Timer is always clocked at half of the CPU frequency */
+#define COUNTS_PER_USECOND  (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ / (2*1000000))
+
+/*****************************************************************************/
+/**
+*
+* This is not implemented .
+*
+* @param	nanoseconds
+*
+* @return	None
+*
+* @note		None.
+*
+****************************************************************************/
+void nanosleep(unsigned int nanoseconds){
+	/* not implemented */
+	(void)nanoseconds;
+}
+
+/*****************************************************************************/
+/**
+*
+* This API gives a delay in microseconds
+*
+* @param	useconds requested
+*
+* @return	0 if the delay can be achieved, -1 if the requested delay
+*		is out of range
+*
+* @note		None.
+*
+****************************************************************************/
+int usleep(unsigned int useconds)
+{
+	XTime tEnd, tCur;
+
+	XTime_GetTime(&tCur);
+	tEnd = tCur + ((XTime) useconds) * COUNTS_PER_USECOND;
+	do
+	{
+		XTime_GetTime(&tCur);
+	} while (tCur < tEnd);
+
+	return 0;
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/vectors.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/vectors.c
new file mode 100644
index 000000000..dd010d7ef
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/vectors.c
@@ -0,0 +1,177 @@
+/******************************************************************************
+*
+* (c) Copyright 2009-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file vectors.c
+*
+* This file contains the C level vectors for the ARM Cortex A9 core.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm  10/20/09 Initial version, moved over from bsp area
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "xil_exception.h"
+#include "vectors.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+typedef struct {
+	Xil_ExceptionHandler Handler;
+	void *Data;
+} XExc_VectorTableEntry;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+extern XExc_VectorTableEntry XExc_VectorTable[];
+
+/************************** Function Prototypes ******************************/
+
+
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the FIQ interrupt called from the vectors.s
+* file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void FIQInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_FIQ_INT].Handler(XExc_VectorTable[
+					XIL_EXCEPTION_ID_FIQ_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the IRQ interrupt called from the vectors.s
+* file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void IRQInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_IRQ_INT].Handler(XExc_VectorTable[
+					XIL_EXCEPTION_ID_IRQ_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the SW Interrupt called from the vectors.s
+* file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void SWInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_SWI_INT].Handler(XExc_VectorTable[
+					XIL_EXCEPTION_ID_SWI_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the DataAbort Interrupt called from the
+* vectors.s file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void DataAbortInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Handler(
+		XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the PrefetchAbort Interrupt called from the
+* vectors.s file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void PrefetchAbortInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Handler(
+		XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Data);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/vectors.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/vectors.h
new file mode 100644
index 000000000..1b094cd17
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/vectors.h
@@ -0,0 +1,90 @@
+/******************************************************************************
+*
+* (c) Copyright 2009-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file vectors.h
+*
+* This file contains the C level vector prototypes for the ARM Cortex A9 core.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm  10/20/10 Initial version, moved over from bsp area
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _VECTORS_H_
+#define _VECTORS_H_
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+void FIQInterrupt(void);
+void IRQInterrupt(void);
+void SWInterrupt(void);
+void DataAbortInterrupt(void);
+void PrefetchAbortInterrupt(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/write.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/write.c
new file mode 100644
index 000000000..fff2882ad
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/write.c
@@ -0,0 +1,103 @@
+/******************************************************************************
+*
+* (c) Copyright 2009-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+
+/* write.c -- write bytes to an output device.
+ */
+
+#include "xparameters.h"
+#include "xil_printf.h"
+
+#ifdef __cplusplus
+extern "C" {
+	int _write (int fd, char* buf, int nbytes);
+}
+#endif
+
+/*
+ * write -- write bytes to the serial port. Ignore fd, since
+ *          stdout and stderr are the same. Since we have no filesystem,
+ *          open will only return an error.
+ */
+int
+write (int fd, char* buf, int nbytes)
+
+{
+#ifdef STDOUT_BASEADDRESS
+  int i;
+
+  (void)fd;
+  for (i = 0; i < nbytes; i++) {
+    if (*(buf + i) == '\n') {
+      outbyte ('\r');
+    }
+    outbyte (*(buf + i));
+  }
+  return (nbytes);
+#else
+  (void)fd;
+  (void)buf;
+  (void)nbytes;
+  return 0;
+#endif
+}
+
+int
+_write (int fd, char* buf, int nbytes)
+{
+#ifdef STDOUT_BASEADDRESS
+  int i;
+
+  (void)fd;
+  for (i = 0; i < nbytes; i++) {
+    if (*(buf + i) == '\n') {
+      outbyte ('\r');
+    }
+    outbyte (*(buf + i));
+  }
+  return (nbytes);
+#else
+  (void)fd;
+  (void)buf;
+  (void)nbytes;
+  return 0;
+#endif
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xbasic_types.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xbasic_types.h
new file mode 100644
index 000000000..b603c300b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xbasic_types.h
@@ -0,0 +1,128 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-12 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xbasic_types.h
+*
+*
+* @note  Dummy File for backwards compatibility
+*
+
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a adk   1/31/14  Added in bsp common folder for backward compatibility
+* 

+*
+******************************************************************************/
+
+#ifndef XBASIC_TYPES_H	/* prevent circular inclusions */
+#define XBASIC_TYPES_H	/* by using protection macros */
+
+/** @name Legacy types
+ * Deprecated legacy types.
+ * @{
+ */
+typedef unsigned char	Xuint8;		/**< unsigned 8-bit */
+typedef char		Xint8;		/**< signed 8-bit */
+typedef unsigned short	Xuint16;	/**< unsigned 16-bit */
+typedef short		Xint16;		/**< signed 16-bit */
+typedef unsigned long	Xuint32;	/**< unsigned 32-bit */
+typedef long		Xint32;		/**< signed 32-bit */
+typedef float		Xfloat32;	/**< 32-bit floating point */
+typedef double		Xfloat64;	/**< 64-bit double precision FP */
+typedef unsigned long	Xboolean;	/**< boolean (XTRUE or XFALSE) */
+
+#if !defined __XUINT64__
+typedef struct
+{
+	Xuint32 Upper;
+	Xuint32 Lower;
+} Xuint64;
+#endif
+
+/** @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XIL_TYPES_H
+typedef Xuint32         u32;
+typedef Xuint16         u16;
+typedef Xuint8          u8;
+#endif
+#else
+#include 
+#endif
+
+#ifndef TRUE
+#  define TRUE		1
+#endif
+
+#ifndef FALSE
+#  define FALSE		0
+#endif
+
+#ifndef NULL
+#define NULL		0
+#endif
+
+/*
+ * Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
+ * Please use NULL, TRUE and FALSE
+ */
+#define XNULL		NULL
+#define XTRUE		TRUE
+#define XFALSE		FALSE
+
+/*
+ * This file is deprecated and users
+ * should use xil_types.h and xil_assert.h\n\r
+ */
+#warning  The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
+#warning  Please refer the Standalone BSP UG647 for further details
+
+
+#endif	/* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xdebug.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xdebug.h
new file mode 100644
index 000000000..8ab5e212c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xdebug.h
@@ -0,0 +1,61 @@
+#ifndef XDEBUG
+#define XDEBUG
+  
+#undef DEBUG
+
+#if defined(DEBUG) && !defined(NDEBUG)
+
+#ifndef XDEBUG_WARNING
+#define XDEBUG_WARNING
+#warning DEBUG is enabled
+#endif
+
+int printf(const char *format, ...);
+
+#define XDBG_DEBUG_ERROR             0x00000001    /* error  condition messages */
+#define XDBG_DEBUG_GENERAL           0x00000002    /* general debug  messages */
+#define XDBG_DEBUG_ALL               0xFFFFFFFF    /* all debugging data */
+
+#define XDBG_DEBUG_FIFO_REG          0x00000100    /* display register reads/writes */
+#define XDBG_DEBUG_FIFO_RX           0x00000101    /* receive debug messages */
+#define XDBG_DEBUG_FIFO_TX           0x00000102    /* transmit debug messages */
+#define XDBG_DEBUG_FIFO_ALL          0x0000010F    /* all fifo debug messages */
+
+#define XDBG_DEBUG_TEMAC_REG         0x00000400    /* display register reads/writes */
+#define XDBG_DEBUG_TEMAC_RX          0x00000401    /* receive debug messages */
+#define XDBG_DEBUG_TEMAC_TX          0x00000402    /* transmit debug messages */
+#define XDBG_DEBUG_TEMAC_ALL         0x0000040F    /* all temac  debug messages */
+
+#define XDBG_DEBUG_TEMAC_ADPT_RX     0x00000800    /* receive debug messages */
+#define XDBG_DEBUG_TEMAC_ADPT_TX     0x00000801    /* transmit debug messages */
+#define XDBG_DEBUG_TEMAC_ADPT_IOCTL  0x00000802    /* ioctl debug messages */
+#define XDBG_DEBUG_TEMAC_ADPT_MISC   0x00000803    /* debug msg for other routines */
+#define XDBG_DEBUG_TEMAC_ADPT_ALL    0x0000080F    /* all temac adapter debug messages */
+
+#define xdbg_current_types (XDBG_DEBUG_ERROR)
+
+#define xdbg_stmnt(x)  x
+
+/* In VxWorks, if _WRS_GNU_VAR_MACROS is defined, special syntax is needed for
+ * macros that accept variable number of arguments
+ */
+#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
+#define xdbg_printf(type, args...) (((type) & xdbg_current_types) ? printf (## args) : 0)
+#else /* ANSI Syntax */
+#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
+#endif
+
+#else /* defined(DEBUG) && !defined(NDEBUG) */
+
+#define xdbg_stmnt(x)
+
+/* See VxWorks comments above */
+#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
+#define xdbg_printf(type, args...)
+#else /* ANSI Syntax */
+#define xdbg_printf(...)
+#endif
+
+#endif /* defined(DEBUG) && !defined(NDEBUG) */
+
+#endif /* XDEBUG */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xenv.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xenv.h
new file mode 100644
index 000000000..27cb76810
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xenv.h
@@ -0,0 +1,177 @@
+/******************************************************************************
+*
+*       XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+*       AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
+*       SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,
+*       OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+*       APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
+*       THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
+*       AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+*       FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
+*       WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+*       IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+*       REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+*       INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*       FOR A PARTICULAR PURPOSE.
+*
+*       (c) Copyright 2002 Xilinx Inc.
+*       All rights reserved.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv.h
+*
+* Defines common services that are typically found in a host operating.
+* environment. This include file simply includes an OS specific file based
+* on the compile-time constant BUILD_ENV_*, where * is the name of the target
+* environment.
+*
+* All services are defined as macros.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b ch   10/24/02 Added XENV_LINUX
+* 1.00a rmm  04/17/02 First release
+* 

+*
+******************************************************************************/
+
+#ifndef XENV_H /* prevent circular inclusions */
+#define XENV_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Select which target environment we are operating under
+ */
+
+/* VxWorks target environment */
+#if defined XENV_VXWORKS
+#include "xenv_vxworks.h"
+
+/* Linux target environment */
+#elif defined XENV_LINUX
+#include "xenv_linux.h"
+
+/* Unit test environment */
+#elif defined XENV_UNITTEST
+#include "ut_xenv.h"
+
+/* Integration test environment */
+#elif defined XENV_INTTEST
+#include "int_xenv.h"
+
+/* Standalone environment selected */
+#else
+#include "xenv_standalone.h"
+#endif
+
+
+/*
+ * The following comments specify the types and macro wrappers that are
+ * expected to be defined by the target specific header files
+ */
+
+/**************************** Type Definitions *******************************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP
+ *
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param   DestPtr is the destination address to copy data to.
+ * @param   SrcPtr is the source address to copy data from.
+ * @param   Bytes is the number of bytes to copy.
+ *
+ * @return  None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param   DestPtr is the destination address to set.
+ * @param   Data contains the value to set.
+ * @param   Bytes is the number of bytes to set.
+ *
+ * @return  None
+ */
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ *
+ * Samples the processor's or external timer's time base counter.
+ *
+ * @param   StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return  None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param   Stamp1Ptr - First sampled time stamp.
+ * @param   Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return  An unsigned int value with units of microseconds.
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param   Stamp1Ptr - First sampled time stamp.
+ * @param   Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return  An unsigned int value with units of milliseconds.
+ */
+
+/*****************************************************************************//**
+ *
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds.
+ *
+ * @param   delay is the number of microseconds to delay.
+ *
+ * @return  None
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif            /* end of protection macro */
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xenv_standalone.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xenv_standalone.h
new file mode 100644
index 000000000..f2b2b6887
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xenv_standalone.h
@@ -0,0 +1,356 @@
+/******************************************************************************
+*
+*       XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+*       AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
+*       SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,
+*       OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+*       APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
+*       THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
+*       AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+*       FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
+*       WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+*       IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+*       REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+*       INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*       FOR A PARTICULAR PURPOSE.
+*
+*       (c) Copyright 2002-2008 Xilinx Inc.
+*       All rights reserved.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv_standalone.h
+*
+* Defines common services specified by xenv.h.
+*
+* @note
+* 	This file is not intended to be included directly by driver code.
+* 	Instead, the generic xenv.h file is intended to be included by driver
+* 	code.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a wgr  02/28/07 Added cache handling macros.
+* 1.00a wgr  02/27/07 Simplified code. Deprecated old-style macro names.
+* 1.00a rmm  01/24/06 Implemented XENV_USLEEP. Assume implementation is being
+*                     used under Xilinx standalone BSP.
+* 1.00a xd   11/03/04 Improved support for doxygen.
+* 1.00a rmm  03/21/02 First release
+* 1.00a wgr  03/22/07 Converted to new coding style.
+* 1.00a rpm  06/29/07 Added udelay macro for standalone
+* 1.00a xd   07/19/07 Included xparameters.h as XPAR_ constants are referred
+*                     to in MICROBLAZE section
+* 1.00a ecm  09/19/08 updated for v7.20 of Microblaze, new functionality
+*
+* 

+*
+*
+******************************************************************************/
+
+#ifndef XENV_STANDALONE_H
+#define XENV_STANDALONE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+/******************************************************************************
+ *
+ * Get the processor dependent includes
+ *
+ ******************************************************************************/
+
+#include 
+
+#if defined __MICROBLAZE__
+#  include "mb_interface.h"
+#  include "xparameters.h"   /* XPAR constants used below in MB section */
+
+#elif defined __PPC__
+#  include "sleep.h"
+#  include "xcache_l.h"      /* also include xcache_l.h for caching macros */
+#endif
+
+/******************************************************************************
+ *
+ * MEMCPY / MEMSET related macros.
+ *
+ * The following are straight forward implementations of memset and memcpy.
+ *
+ * NOTE: memcpy may not work if source and target memory area are overlapping.
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	SrcPtr
+ * 		Source address to copy data from.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ * @note
+ * 		The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
+ *
+ * @note
+ * 		This implemention MAY BREAK work if source and target memory
+ * 		area are overlapping.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
+	memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
+
+
+
+/*****************************************************************************/
+/**
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	Data
+ * 		Value to set.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ * @note
+ * 		The use of XENV_MEM_FILL is deprecated. Use memset() instead.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
+	memset((void *) DestPtr, (int) Data, (size_t) Bytes)
+
+
+
+/******************************************************************************
+ *
+ * TIME related macros
+ *
+ ******************************************************************************/
+
+/**
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+typedef int XENV_TIME_STAMP;
+
+/*****************************************************************************/
+/**
+ *
+ * Time is derived from the 64 bit PPC timebase register
+ *
+ * @param   StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return  None.
+ *
+ * @note
+ *
+ * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ * 


+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_GET(StampPtr)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr)     (0)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr)     (0)
+
+/*****************************************************************************/
+/**
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds. Not implemented without OS
+ * support.
+ *
+ * @param	delay
+ * 		Number of microseconds to delay.
+ *
+ * @return	None.
+ *
+ *****************************************************************************/
+
+#ifdef __PPC__
+#define XENV_USLEEP(delay)	usleep(delay)
+#define udelay(delay)	usleep(delay)
+#else
+#define XENV_USLEEP(delay)
+#define udelay(delay)
+#endif
+
+
+/******************************************************************************
+ *
+ * CACHE handling macros / mappings
+ *
+ ******************************************************************************/
+/******************************************************************************
+ *
+ * Processor independent macros
+ *
+ ******************************************************************************/
+
+#define XCACHE_ENABLE_CACHE()	\
+		{ XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
+
+#define XCACHE_DISABLE_CACHE()	\
+		{ XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
+
+
+/******************************************************************************
+ *
+ * MicroBlaze case
+ *
+ * NOTE: Currently the following macros will only work on systems that contain
+ * only ONE MicroBlaze processor. Also, the macros will only be enabled if the
+ * system is built using a xparameters.h file.
+ *
+ ******************************************************************************/
+
+#if defined __MICROBLAZE__
+
+/* Check if MicroBlaze data cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
+#  define XCACHE_ENABLE_DCACHE()		microblaze_enable_dcache()
+#  define XCACHE_DISABLE_DCACHE()		microblaze_disable_dcache()
+#  define XCACHE_INVALIDATE_DCACHE()  	microblaze_invalidate_dcache()
+
+#  define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_dcache_range((int)(Addr), (int)(Len))
+
+#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
+#  define XCACHE_FLUSH_DCACHE()  		microblaze_flush_dcache()
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+			microblaze_flush_dcache_range((int)(Addr), (int)(Len))
+#else
+#  define XCACHE_FLUSH_DCACHE()  		microblaze_invalidate_dcache()
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_dcache_range((int)(Addr), (int)(Len))
+#endif	/*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
+
+#else
+#  define XCACHE_ENABLE_DCACHE()
+#  define XCACHE_DISABLE_DCACHE()
+#  define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
+#endif	/*XPAR_MICROBLAZE_USE_DCACHE*/
+
+
+/* Check if MicroBlaze instruction cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
+#  define XCACHE_ENABLE_ICACHE()		microblaze_enable_icache()
+#  define XCACHE_DISABLE_ICACHE()		microblaze_disable_icache()
+
+#  define XCACHE_INVALIDATE_ICACHE()  	microblaze_invalidate_icache()
+
+#  define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_icache_range((int)(Addr), (int)(Len))
+
+#else
+#  define XCACHE_ENABLE_ICACHE()
+#  define XCACHE_DISABLE_ICACHE()
+#endif	/*XPAR_MICROBLAZE_USE_ICACHE*/
+
+
+/******************************************************************************
+ *
+ * PowerPC case
+ *
+ *   Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
+ *   specific memory region (0x80000001). Each bit (0-30) in the regions
+ *   bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
+ *   range.
+ *
+ *   regions    --> cached address range
+ *   ------------|--------------------------------------------------
+ *   0x80000000  | [0, 0x7FFFFFF]
+ *   0x00000001  | [0xF8000000, 0xFFFFFFFF]
+ *   0x80000001  | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
+ *
+ ******************************************************************************/
+
+#elif defined __PPC__
+
+#define XCACHE_ENABLE_DCACHE()		XCache_EnableDCache(0x80000001)
+#define XCACHE_DISABLE_DCACHE()		XCache_DisableDCache()
+#define XCACHE_ENABLE_ICACHE()		XCache_EnableICache(0x80000001)
+#define XCACHE_DISABLE_ICACHE()		XCache_DisableICache()
+
+#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+		XCache_InvalidateDCacheRange((unsigned int)(Addr), (unsigned)(Len))
+
+#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+		XCache_FlushDCacheRange((unsigned int)(Addr), (unsigned)(Len))
+
+#define XCACHE_INVALIDATE_ICACHE()	XCache_InvalidateICache()
+
+
+/******************************************************************************
+ *
+ * Unknown processor / architecture
+ *
+ ******************************************************************************/
+
+#else
+/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* #ifndef XENV_STANDALONE_H */
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil-crt0.S b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil-crt0.S
new file mode 100644
index 000000000..d5409c29d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil-crt0.S
@@ -0,0 +1,166 @@
+/******************************************************************************
+*
+* (c) Copyright 2009-2013 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil-crt0.S
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm  10/20/09 Initial version
+* 3.05a sdm  02/02/12 Added code for profiling
+* 3.06a sgd  05/16/12 Added global constructors and cleanup code
+*                     Uart initialization based on compiler flag
+* 3.07a sgd  07/05/12 Updated with reset and start Global Timer
+* 3.07a sgd	 10/19/12 SMC NOR and SRAM initialization with build option
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+.extern XSmc_NorInit
+.extern XSmc_SramInit
+
+	.file	"xil-crt0.S"
+	.section ".got2","aw"
+	.align	2
+
+	.text
+.Lsbss_start:
+	.long	__sbss_start
+
+.Lsbss_end:
+	.long	__sbss_end
+
+.Lbss_start:
+	.long	__bss_start
+
+.Lbss_end:	
+	.long	__bss_end
+
+.Lstack:	
+	.long	__stack
+
+    
+	.globl	_start
+_start:
+	bl      __cpu_init		/* Initialize the CPU first (BSP provides this) */
+
+	mov	r0, #0
+	
+	/* clear sbss */
+	ldr 	r1,.Lsbss_start		/* calculate beginning of the SBSS */
+	ldr	r2,.Lsbss_end		/* calculate end of the SBSS */
+
+.Lloop_sbss:
+	cmp	r1,r2
+	bge	.Lenclsbss		/* If no SBSS, no clearing required */
+	str	r0, [r1], #4
+	b	.Lloop_sbss
+
+.Lenclsbss:  
+	/* clear bss */
+	ldr	r1,.Lbss_start		/* calculate beginning of the BSS */
+	ldr	r2,.Lbss_end		/* calculate end of the BSS */
+
+.Lloop_bss:	
+	cmp	r1,r2
+	bge	.Lenclbss		/* If no BSS, no clearing required */
+	str	r0, [r1], #4
+	b	.Lloop_bss
+
+.Lenclbss:
+
+	/* set stack pointer */
+	ldr	r13,.Lstack		/* stack address */
+
+    /* Reset and start Global Timer */
+	mov	r0, #0x0
+	mov	r1, #0x0
+    bl XTime_SetTime
+    	
+#ifdef PEEP
+	/* Initialize STDOUT */
+	bl	Init_Uart
+
+	/* Initialize the SMC interfaces for NOR */
+	bl	XSmc_NorInit
+
+    /* Initialize the SMC interfaces for SRAM */
+	bl	XSmc_SramInit
+#endif
+
+#ifdef PROFILING			/* defined in Makefile */
+	/* Setup profiling stuff */
+	bl	_profile_init
+#endif /* PROFILING */
+
+   /* run global constructors */ 
+   bl __libc_init_array 
+
+	/* make sure argc and argv are valid */
+	mov	r0, #0
+	mov	r1, #0
+
+	/* Let her rip */
+	bl	main
+
+   /* Cleanup global constructors */ 
+   bl __libc_fini_array 
+
+#ifdef PROFILING
+	/* Cleanup profiling stuff */
+	bl	_profile_clean
+#endif /* PROFILING */
+
+        /* All done */
+	bl	exit
+
+.Lexit:	/* should never get here */
+	b .Lexit
+
+.Lstart:
+	.size	_start,.Lstart-_start
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_assert.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_assert.c
new file mode 100644
index 000000000..1a11195fe
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_assert.c
@@ -0,0 +1,157 @@
+/******************************************************************************
+*
+*
+* (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_assert.c
+*
+* This file contains basic assert related functions for Xilinx software IP.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 Initial release
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/**
+ * This variable allows testing to be done easier with asserts. An assert
+ * sets this variable such that a driver can evaluate this variable
+ * to determine if an assert occurred.
+ */
+unsigned int Xil_AssertStatus;
+
+/**
+ * This variable allows the assert functionality to be changed for testing
+ * such that it does not wait infinitely. Use the debugger to disable the
+ * waiting during testing of asserts.
+ */
+int Xil_AssertWait = TRUE;
+
+/* The callback function to be invoked when an assert is taken */
+static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL;
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* Implement assert. Currently, it calls a user-defined callback function
+* if one has been set.  Then, it potentially enters an infinite loop depending
+* on the value of the Xil_AssertWait variable.
+*
+* @param    file is the name of the filename of the source
+* @param    line is the linenumber within File
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+void Xil_Assert(const char *File, int Line)
+{
+	/* if the callback has been set then invoke it */
+	if (Xil_AssertCallbackRoutine != 0) {
+		(*Xil_AssertCallbackRoutine)(File, Line);
+	}
+
+	/* if specified, wait indefinitely such that the assert will show up
+	 * in testing
+	 */
+	while (Xil_AssertWait) {
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Set up a callback function to be invoked when an assert occurs. If there
+* was already a callback installed, then it is replaced.
+*
+* @param    routine is the callback to be invoked when an assert is taken
+*
+* @return   None.
+*
+* @note     This function has no effect if NDEBUG is set
+*
+******************************************************************************/
+void Xil_AssertSetCallback(Xil_AssertCallback Routine)
+{
+	Xil_AssertCallbackRoutine = Routine;
+}
+
+/*****************************************************************************/
+/**
+*
+* Null handler function. This follows the XInterruptHandler signature for
+* interrupt handlers. It can be used to assign a null handler (a stub) to an
+* interrupt controller vector table.
+*
+* @param    NullParameter is an arbitrary void pointer and not used.
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+void XNullHandler(void *NullParameter)
+{
+ (void) NullParameter;
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_assert.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_assert.h
new file mode 100644
index 000000000..d08663b7c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_assert.h
@@ -0,0 +1,196 @@
+/******************************************************************************
+*
+* (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_assert.h
+*
+* This file contains assert related functions.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 First release
+* 

+*
+******************************************************************************/
+
+#ifndef XIL_ASSERT_H	/* prevent circular inclusions */
+#define XIL_ASSERT_H	/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+
+/************************** Constant Definitions *****************************/
+
+#define XIL_ASSERT_NONE     0
+#define XIL_ASSERT_OCCURRED 1
+#define XNULL NULL
+
+extern unsigned int Xil_AssertStatus;
+extern void Xil_Assert(const char *, int);
+void XNullHandler(void *NullParameter);
+
+/**
+ * This data type defines a callback to be invoked when an
+ * assert occurs. The callback is invoked only when asserts are enabled
+ */
+typedef void (*Xil_AssertCallback) (const char *File, int Line);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#ifndef NDEBUG
+
+/*****************************************************************************/
+/**
+* This assert macro is to be used for functions that do not return anything
+* (void). This in conjunction with the Xil_AssertWait boolean can be used to
+* accomodate tests so that asserts which fail allow execution to continue.
+*
+* @param    expression is the expression to evaluate. If it evaluates to
+*           false, the assert occurs.
+*
+* @return   Returns void unless the Xil_AssertWait variable is true, in which
+*           case no return is made and an infinite loop is entered.
+*
+* @note     None.
+*
+******************************************************************************/
+#define Xil_AssertVoid(Expression)                \
+{                                                  \
+    if (Expression) {                              \
+        Xil_AssertStatus = XIL_ASSERT_NONE;       \
+    } else {                                       \
+        Xil_Assert(__FILE__, __LINE__);            \
+        Xil_AssertStatus = XIL_ASSERT_OCCURRED;   \
+        return;                                    \
+    }                                              \
+}
+
+/*****************************************************************************/
+/**
+* This assert macro is to be used for functions that do return a value. This in
+* conjunction with the Xil_AssertWait boolean can be used to accomodate tests
+* so that asserts which fail allow execution to continue.
+*
+* @param    expression is the expression to evaluate. If it evaluates to false,
+*           the assert occurs.
+*
+* @return   Returns 0 unless the Xil_AssertWait variable is true, in which
+* 	    case no return is made and an infinite loop is entered.
+*
+* @note     None.
+*
+******************************************************************************/
+#define Xil_AssertNonvoid(Expression)             \
+{                                                  \
+    if (Expression) {                              \
+        Xil_AssertStatus = XIL_ASSERT_NONE;       \
+    } else {                                       \
+        Xil_Assert(__FILE__, __LINE__);            \
+        Xil_AssertStatus = XIL_ASSERT_OCCURRED;   \
+        return 0;                                  \
+    }                                              \
+}
+
+/*****************************************************************************/
+/**
+* Always assert. This assert macro is to be used for functions that do not
+* return anything (void). Use for instances where an assert should always
+* occur.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+*	  case no return is made and an infinite loop is entered.
+*
+* @note   None.
+*
+******************************************************************************/
+#define Xil_AssertVoidAlways()                   \
+{                                                  \
+   Xil_Assert(__FILE__, __LINE__);                 \
+   Xil_AssertStatus = XIL_ASSERT_OCCURRED;        \
+   return;                                         \
+}
+
+/*****************************************************************************/
+/**
+* Always assert. This assert macro is to be used for functions that do return
+* a value. Use for instances where an assert should always occur.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+*	  case no return is made and an infinite loop is entered.
+*
+* @note   None.
+*
+******************************************************************************/
+#define Xil_AssertNonvoidAlways()                \
+{                                                  \
+   Xil_Assert(__FILE__, __LINE__);                 \
+   Xil_AssertStatus = XIL_ASSERT_OCCURRED;        \
+   return 0;                                       \
+}
+
+
+#else
+
+#define Xil_AssertVoid(Expression)
+#define Xil_AssertVoidAlways()
+#define Xil_AssertNonvoid(Expression)
+#define Xil_AssertNonvoidAlways()
+
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void Xil_AssertSetCallback(Xil_AssertCallback Routine);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_cache.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_cache.c
new file mode 100644
index 000000000..d15edd782
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_cache.c
@@ -0,0 +1,1497 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-14  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache.c
+*
+* Contains required functions for the ARM cache functionality.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver    Who Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a  ecm 01/29/10 First release
+* 1.00a  ecm 06/24/10 Moved the L1 and L2 specific function prototypes
+*		      to xil_cache_mach.h to give access to sophisticated users
+* 3.02a  sdm 04/07/11 Updated Flush/InvalidateRange APIs to flush/invalidate
+*		      L1 and L2 caches in a single loop and used dsb, L2 sync
+*		      at the end of the loop.
+* 3.04a  sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
+*		      APIs.
+* 3.07a  asa 07/16/12 Corrected the L1 and L2 cache invalidation order.
+* 3.07a  sgd 09/18/12 Corrected the L2 cache enable and disable sequence.
+* 3.10a  srt 04/18/13 Implemented ARM Erratas. Please refer to file
+*		      'xil_errata.h' for errata description
+* 3.10a  asa 05/13/13 Modified cache disable APIs. The L2 cache disable
+*			  operation was being done with L1 Data cache disabled. This is
+*			  fixed so that L2 cache disable operation happens independent of
+*			  L1 cache disable operation. This fixes CR #706464.
+*			  Changes are done to do a L2 cache sync (poll reg7_?cache_?sync).
+*			  This is done to fix the CR #700542.
+* 3.11a  asa 09/23/13 Modified the Xil_DCacheFlushRange and
+*			 Xil_DCacheInvalidateRange to fix potential issues. Fixed other
+*			 relevant cache APIs to disable and enable back the interrupts.
+*			 This fixes CR #663885.
+* 3.11a  asa 09/28/13 Made changes for L2 cache sync operation. It is found
+*			 out that for L2 cache flush/clean/invalidation by cache lines
+*			 does not need a cache sync as these are atomic nature. Similarly
+*			 figured out that for complete L2 cache flush/invalidation by way
+*			 we need to wait for some more time in a loop till the status
+*			 shows that the cache operation is completed.
+* 4.00	 pkp 24/01/14 Modified Xil_DCacheInvalidateRange to fix the bug. Few
+*			 cache lines were missed to invalidate when unaligned address
+*			 invalidation was accommodated. That fixes CR #766768. 
+*			 Also in Xil_L1DCacheInvalidate, while invalidating all L1D cache
+*			 stack memory which contains return address was invalidated. So
+*			 stack memory was flushed first and then L1D cache is invalidated.
+*			 This is done to fix CR #763829
+* 4.01   asa 05/09/14 Made changes in cortexa9/xil_cache.c to fix CR# 798230.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xil_cache_l.h"
+#include "xil_io.h"
+#include "xpseudo_asm.h"
+#include "xparameters.h"
+#include "xreg_cortexa9.h"
+#include "xl2cc.h"
+#include "xil_errata.h"
+#include "xil_exception.h"
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#define IRQ_FIQ_MASK 0xC0	/* Mask IRQ and FIQ interrupts in cpsr */
+
+#ifdef __GNUC__
+	extern int  _stack_end;
+	extern int  _stack;
+#endif
+
+/****************************************************************************
+*
+* Access L2 Debug Control Register.
+*
+* @param	Value, value to be written to Debug Control Register.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+#ifdef __GNUC__
+static inline void Xil_L2WriteDebugCtrl(u32 Value)
+#else
+static void Xil_L2WriteDebugCtrl(u32 Value)
+#endif
+{
+#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DEBUG_CTRL_OFFSET, Value);
+#else
+	(void)(Value);
+#endif
+}
+
+/****************************************************************************
+*
+* Perform L2 Cache Sync Operation.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+#ifdef __GNUC__
+static inline void Xil_L2CacheSync(void)
+#else
+static void Xil_L2CacheSync(void)
+#endif
+{
+#ifdef CONFIG_PL310_ERRATA_753970
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET, 0x0);
+#else
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_SYNC_OFFSET, 0x0);
+#endif
+}
+
+/****************************************************************************
+*
+* Enable the Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheEnable(void)
+{
+	Xil_L1DCacheEnable();
+	Xil_L2CacheEnable();
+}
+
+/****************************************************************************
+*
+* Disable the Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheDisable(void)
+{
+	Xil_L2CacheDisable();
+	Xil_L1DCacheDisable();
+}
+
+/****************************************************************************
+*
+* Invalidate the entire Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheInvalidate(void)
+{
+	unsigned int currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	Xil_L2CacheInvalidate();
+	Xil_L1DCacheInvalidate();
+
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Invalidate a Data cache line. If the byte specified by the address (adr)
+* is cached by the Data cache, the cacheline containing that byte is
+* invalidated.	If the cacheline is modified (dirty), the modified contents
+* are lost and are NOT written to system memory before the line is
+* invalidated.
+*
+* @param	Address to be flushed.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheInvalidateLine(unsigned int adr)
+{
+	unsigned int currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	Xil_L2CacheInvalidateLine(adr);
+	Xil_L1DCacheInvalidateLine(adr);
+
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Invalidate the Data cache for the given address range.
+* If the bytes specified by the address (adr) are cached by the Data cache,
+* the cacheline containing that byte is invalidated.	If the cacheline
+* is modified (dirty), the modified contents are lost and are NOT
+* written to system memory before the line is invalidated.
+*
+* @param	Start address of range to be invalidated.
+* @param	Length of range to be invalidated in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheInvalidateRange(unsigned int adr, unsigned len)
+{
+	const unsigned cacheline = 32;
+	unsigned int end;
+	unsigned int tempadr = adr;
+	unsigned int tempend;
+	unsigned int currmask;
+	volatile u32 *L2CCOffset = (volatile u32 *) (XPS_L2CC_BASEADDR +
+				    XPS_L2CC_CACHE_INVLD_PA_OFFSET);
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	if (len != 0) {
+		end = tempadr + len;
+		tempend = end;
+		/* Select L1 Data cache in CSSR */
+		mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+
+		if (tempadr & (cacheline-1)) {
+			tempadr &= ~(cacheline - 1);
+
+			Xil_L1DCacheFlushLine(tempadr);
+			/* Disable Write-back and line fills */
+			Xil_L2WriteDebugCtrl(0x3);
+			Xil_L2CacheFlushLine(tempadr);
+			/* Enable Write-back and line fills */
+			Xil_L2WriteDebugCtrl(0x0);
+			Xil_L2CacheSync();
+			tempadr += cacheline;
+		}
+		if (tempend & (cacheline-1)) {
+			tempend &= ~(cacheline - 1);
+
+			Xil_L1DCacheFlushLine(tempend);
+			/* Disable Write-back and line fills */
+			Xil_L2WriteDebugCtrl(0x3);
+			Xil_L2CacheFlushLine(tempend);
+			/* Enable Write-back and line fills */
+			Xil_L2WriteDebugCtrl(0x0);
+			Xil_L2CacheSync();
+		}
+
+		while (tempadr < tempend) {
+			/* Invalidate L2 cache line */
+			*L2CCOffset = tempadr;
+			dsb();
+#ifdef __GNUC__
+			/* Invalidate L1 Data cache line */
+			__asm__ __volatile__("mcr " \
+			XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (tempadr));
+#else
+			{ volatile register unsigned int Reg
+				__asm(XREG_CP15_INVAL_DC_LINE_MVA_POC);
+			  Reg = tempadr; }
+#endif
+			tempadr += cacheline;
+		}
+	}
+
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Flush the entire Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheFlush(void)
+{
+	unsigned int currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+	Xil_L1DCacheFlush();
+	Xil_L2CacheFlush();
+
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Flush a Data cache line. If the byte specified by the address (adr)
+* is cached by the Data cache, the cacheline containing that byte is
+* invalidated.	If the cacheline is modified (dirty), the entire
+* contents of the cacheline are written to system memory before the
+* line is invalidated.
+*
+* @param	Address to be flushed.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheFlushLine(unsigned int adr)
+{
+	unsigned int currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+	Xil_L1DCacheFlushLine(adr);
+
+	/* Disable Write-back and line fills */
+	Xil_L2WriteDebugCtrl(0x3);
+
+	Xil_L2CacheFlushLine(adr);
+
+	/* Enable Write-back and line fills */
+	Xil_L2WriteDebugCtrl(0x0);
+	Xil_L2CacheSync();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+* Flush the Data cache for the given address range.
+* If the bytes specified by the address (adr) are cached by the Data cache,
+* the cacheline containing that byte is invalidated.	If the cacheline
+* is modified (dirty), the written to system memory first before the
+* before the line is invalidated.
+*
+* @param	Start address of range to be flushed.
+* @param	Length of range to be flushed in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheFlushRange(unsigned int adr, unsigned len)
+{
+	const unsigned cacheline = 32;
+	unsigned int end;
+	unsigned int currmask;
+	volatile u32 *L2CCOffset = (volatile u32 *) (XPS_L2CC_BASEADDR +
+				    XPS_L2CC_CACHE_INV_CLN_PA_OFFSET);
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	if (len != 0) {
+		/* Back the starting address up to the start of a cache line
+		 * perform cache operations until adr+len
+		 */
+		end = adr + len;
+		adr &= ~(cacheline - 1);
+
+		while (adr < end) {
+#ifdef __GNUC__
+			/* Flush L1 Data cache line */
+			__asm__ __volatile__("mcr " \
+			XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (adr));
+#else
+			{ volatile register unsigned int Reg
+				__asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC);
+			  Reg = adr; }
+#endif
+			/* Flush L2 cache line */
+			*L2CCOffset = adr;
+			dsb();
+			adr += cacheline;
+		}
+	}
+	dsb();
+	mtcpsr(currmask);
+}
+/****************************************************************************
+*
+* Store a Data cache line. If the byte specified by the address (adr)
+* is cached by the Data cache and the cacheline is modified (dirty),
+* the entire contents of the cacheline are written to system memory.
+* After the store completes, the cacheline is marked as unmodified
+* (not dirty).
+*
+* @param	Address to be stored.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheStoreLine(unsigned int adr)
+{
+	unsigned int currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	Xil_L1DCacheStoreLine(adr);
+	Xil_L2CacheStoreLine(adr);
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Enable the instruction cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ICacheEnable(void)
+{
+	Xil_L1ICacheEnable();
+	Xil_L2CacheEnable();
+}
+
+/****************************************************************************
+*
+* Disable the instruction cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ICacheDisable(void)
+{
+	Xil_L2CacheDisable();
+	Xil_L1ICacheDisable();
+}
+
+/****************************************************************************
+*
+* Invalidate the entire instruction cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ICacheInvalidate(void)
+{
+	unsigned int currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	Xil_L2CacheInvalidate();
+	Xil_L1ICacheInvalidate();
+
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Invalidate an instruction cache line.	If the instruction specified by the
+* parameter adr is cached by the instruction cache, the cacheline containing
+* that instruction is invalidated.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_ICacheInvalidateLine(unsigned int adr)
+{
+	unsigned int currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+	Xil_L2CacheInvalidateLine(adr);
+	Xil_L1ICacheInvalidateLine(adr);
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Invalidate the instruction cache for the given address range.
+* If the bytes specified by the address (adr) are cached by the Data cache,
+* the cacheline containing that byte is invalidated. If the cacheline
+* is modified (dirty), the modified contents are lost and are NOT
+* written to system memory before the line is invalidated.
+*
+* @param	Start address of range to be invalidated.
+* @param	Length of range to be invalidated in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ICacheInvalidateRange(unsigned int adr, unsigned len)
+{
+	const unsigned cacheline = 32;
+	unsigned int end;
+	volatile u32 *L2CCOffset = (volatile u32 *) (XPS_L2CC_BASEADDR +
+				    XPS_L2CC_CACHE_INVLD_PA_OFFSET);
+
+	unsigned int currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+	if (len != 0) {
+		/* Back the starting address up to the start of a cache line
+		 * perform cache operations until adr+len
+		 */
+		end = adr + len;
+		adr = adr & ~(cacheline - 1);
+
+		/* Select cache L0 I-cache in CSSR */
+		mtcp(XREG_CP15_CACHE_SIZE_SEL, 1);
+
+		while (adr < end) {
+		/* Invalidate L2 cache line */
+		*L2CCOffset = adr;
+		dsb();
+#ifdef __GNUC__
+			/* Invalidate L1 I-cache line */
+			__asm__ __volatile__("mcr " \
+			XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (adr));
+#else
+			{ volatile register unsigned int Reg
+				__asm(XREG_CP15_INVAL_IC_LINE_MVA_POU);
+			  Reg = adr; }
+#endif
+
+			adr += cacheline;
+		}
+	}
+
+	/* Wait for L1 and L2 invalidate to complete */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Enable the level 1 Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L1DCacheEnable(void)
+{
+	register unsigned int CtrlReg;
+
+	/* enable caches only if they are disabled */
+#ifdef __GNUC__
+	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#else
+	{ volatile register unsigned int Reg __asm(XREG_CP15_SYS_CONTROL);
+	  CtrlReg = Reg; }
+#endif
+	if (CtrlReg & XREG_CP15_CONTROL_C_BIT) {
+		return;
+	}
+
+	/* clean and invalidate the Data cache */
+	Xil_L1DCacheInvalidate();
+
+	/* enable the Data cache */
+	CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+
+	mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/****************************************************************************
+*
+* Disable the level 1 Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L1DCacheDisable(void)
+{
+	register unsigned int CtrlReg;
+
+	/* clean and invalidate the Data cache */
+	Xil_L1DCacheFlush();
+
+#ifdef __GNUC__
+	/* disable the Data cache */
+	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#else
+	{ volatile register unsigned int Reg __asm(XREG_CP15_SYS_CONTROL);
+	  CtrlReg = Reg; }
+#endif
+
+	CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+
+	mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/****************************************************************************
+*
+* Invalidate the level 1 Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		In Cortex A9, there is no cp instruction for invalidating
+*		the whole D-cache. This function invalidates each line by
+*		set/way.
+*
+****************************************************************************/
+void Xil_L1DCacheInvalidate(void)
+{
+	register unsigned int CsidReg, C7Reg;
+	unsigned int CacheSize, LineSize, NumWays;
+	unsigned int Way, WayIndex, Set, SetIndex, NumSet;
+	unsigned int currmask;
+	
+#ifdef __GNUC__
+	unsigned int stack_start,stack_end,stack_size;
+#endif 
+	
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+	
+#ifdef __GNUC__
+	stack_end = (unsigned int )&_stack_end;
+	stack_start = (unsigned int )&_stack;
+	stack_size=stack_start-stack_end;
+
+	/*Flush stack memory to save return address*/
+	Xil_DCacheFlushRange(stack_end, stack_size);
+#endif
+	
+	/* Select cache level 0 and D cache in CSSR */
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+
+#ifdef __GNUC__
+	CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
+#else
+	{ volatile register unsigned int Reg __asm(XREG_CP15_CACHE_SIZE_ID);
+	  CsidReg = Reg; }
+#endif
+	/* Determine Cache Size */
+	CacheSize = (CsidReg >> 13) & 0x1FF;
+	CacheSize +=1;
+	CacheSize *=128;    /* to get number of bytes */
+
+	/* Number of Ways */
+	NumWays = (CsidReg & 0x3ff) >> 3;
+	NumWays += 1;
+
+	/* Get the cacheline size, way size, index size from csidr */
+	LineSize = (CsidReg & 0x07) + 4;
+
+	NumSet = CacheSize/NumWays;
+	NumSet /= (1 << LineSize);
+
+	Way = 0UL;
+	Set = 0UL;
+
+	/* Invalidate all the cachelines */
+	for (WayIndex =0; WayIndex < NumWays; WayIndex++) {
+		for (SetIndex =0; SetIndex < NumSet; SetIndex++) {
+			C7Reg = Way | Set;
+#ifdef __GNUC__
+			/* Invalidate by Set/Way */
+			__asm__ __volatile__("mcr " \
+			XREG_CP15_INVAL_DC_LINE_SW :: "r" (C7Reg));
+#else
+			//mtcp(XREG_CP15_INVAL_DC_LINE_SW, C7Reg);
+			{ volatile register unsigned int Reg
+				__asm(XREG_CP15_INVAL_DC_LINE_SW);
+			  Reg = C7Reg; }
+#endif
+			Set += (1 << LineSize);
+		}
+		Set=0UL;
+		Way += 0x40000000;
+	}
+
+	/* Wait for L1 invalidate to complete */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Invalidate a level 1 Data cache line. If the byte specified by the address
+* (Addr) is cached by the Data cache, the cacheline containing that byte is
+* invalidated.	If the cacheline is modified (dirty), the modified contents
+* are lost and are NOT written to system memory before the line is
+* invalidated.
+*
+* @param	Address to be flushed.
+*
+* @return	None.
+*
+* @note		The bottom 5 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L1DCacheInvalidateLine(unsigned int adr)
+{
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+	mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F)));
+
+	/* Wait for L1 invalidate to complete */
+	dsb();
+}
+
+/****************************************************************************
+*
+* Invalidate the level 1 Data cache for the given address range.
+* If the bytes specified by the address (adr) are cached by the Data cache,
+* the cacheline containing that byte is invalidated. If the cacheline
+* is modified (dirty), the modified contents are lost and are NOT
+* written to system memory before the line is invalidated.
+*
+* @param	Start address of range to be invalidated.
+* @param	Length of range to be invalidated in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L1DCacheInvalidateRange(unsigned int adr, unsigned len)
+{
+	const unsigned cacheline = 32;
+	unsigned int end;
+	unsigned int currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	if (len != 0) {
+		/* Back the starting address up to the start of a cache line
+		 * perform cache operations until adr+len
+		 */
+		end = adr + len;
+		adr = adr & ~(cacheline - 1);
+
+		/* Select cache L0 D-cache in CSSR */
+		mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+
+		while (adr < end) {
+#ifdef __GNUC__
+			__asm__ __volatile__("mcr " \
+			XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (adr));
+#else
+			{ volatile register unsigned int Reg
+				__asm(XREG_CP15_INVAL_DC_LINE_MVA_POC);
+			  Reg = adr; }
+#endif
+			adr += cacheline;
+		}
+	}
+
+	/* Wait for L1 invalidate to complete */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Flush the level 1 Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		In Cortex A9, there is no cp instruction for flushing
+*		the whole D-cache. Need to flush each line.
+*
+****************************************************************************/
+void Xil_L1DCacheFlush(void)
+{
+	register unsigned int CsidReg, C7Reg;
+	unsigned int CacheSize, LineSize, NumWays;
+	unsigned int Way, WayIndex, Set, SetIndex, NumSet;
+	unsigned int currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	/* Select cache level 0 and D cache in CSSR */
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+
+#ifdef __GNUC__
+	CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
+#else
+	{ volatile register unsigned int Reg __asm(XREG_CP15_CACHE_SIZE_ID);
+	  CsidReg = Reg; }
+#endif
+
+	/* Determine Cache Size */
+
+	CacheSize = (CsidReg >> 13) & 0x1FF;
+	CacheSize +=1;
+	CacheSize *=128;    /* to get number of bytes */
+
+	/* Number of Ways */
+	NumWays = (CsidReg & 0x3ff) >> 3;
+	NumWays += 1;
+
+	/* Get the cacheline size, way size, index size from csidr */
+	LineSize = (CsidReg & 0x07) + 4;
+
+	NumSet = CacheSize/NumWays;
+	NumSet /= (1 << LineSize);
+
+	Way = 0UL;
+	Set = 0UL;
+
+	/* Invalidate all the cachelines */
+	for (WayIndex =0; WayIndex < NumWays; WayIndex++) {
+		for (SetIndex =0; SetIndex < NumSet; SetIndex++) {
+			C7Reg = Way | Set;
+			/* Flush by Set/Way */
+#ifdef __GNUC__
+			__asm__ __volatile__("mcr " \
+			XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (C7Reg));
+#else
+			{ volatile register unsigned int Reg
+				__asm(XREG_CP15_CLEAN_INVAL_DC_LINE_SW);
+			  Reg = C7Reg; }
+#endif
+			Set += (1 << LineSize);
+		}
+		Set = 0UL;
+		Way += 0x40000000;
+	}
+
+	/* Wait for L1 flush to complete */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Flush a level 1 Data cache line. If the byte specified by the address (adr)
+* is cached by the Data cache, the cacheline containing that byte is
+* invalidated.	If the cacheline is modified (dirty), the entire
+* contents of the cacheline are written to system memory before the
+* line is invalidated.
+*
+* @param	Address to be flushed.
+*
+* @return	None.
+*
+* @note		The bottom 5 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L1DCacheFlushLine(unsigned int adr)
+{
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+	mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F)));
+
+	/* Wait for L1 flush to complete */
+	dsb();
+}
+
+/****************************************************************************
+* Flush the level 1  Data cache for the given address range.
+* If the bytes specified by the address (adr) are cached by the Data cache,
+* the cacheline containing that byte is invalidated.	If the cacheline
+* is modified (dirty), the written to system memory first before the
+* before the line is invalidated.
+*
+* @param	Start address of range to be flushed.
+* @param	Length of range to be flushed in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L1DCacheFlushRange(unsigned int adr, unsigned len)
+{
+	const unsigned cacheline = 32;
+	unsigned int end;
+	unsigned int currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	if (len != 0) {
+		/* Back the starting address up to the start of a cache line
+		 * perform cache operations until adr+len
+		 */
+		end = adr + len;
+		adr = adr & ~(cacheline - 1);
+
+		/* Select cache L0 D-cache in CSSR */
+		mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+
+		while (adr < end) {
+#ifdef __GNUC__
+			__asm__ __volatile__("mcr " \
+			XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (adr));
+#else
+			{ volatile register unsigned int Reg
+				__asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC);
+			  Reg = adr; }
+#endif
+			adr += cacheline;
+		}
+	}
+
+	/* Wait for L1 flush to complete */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Store a level 1  Data cache line. If the byte specified by the address (adr)
+* is cached by the Data cache and the cacheline is modified (dirty),
+* the entire contents of the cacheline are written to system memory.
+* After the store completes, the cacheline is marked as unmodified
+* (not dirty).
+*
+* @param	Address to be stored.
+*
+* @return	None.
+*
+* @note		The bottom 5 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L1DCacheStoreLine(unsigned int adr)
+{
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+	mtcp(XREG_CP15_CLEAN_DC_LINE_MVA_POC, (adr & (~0x1F)));
+
+	/* Wait for L1 store to complete */
+	dsb();
+}
+
+/****************************************************************************
+*
+* Enable the level 1 instruction cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L1ICacheEnable(void)
+{
+	register unsigned int CtrlReg;
+
+	/* enable caches only if they are disabled */
+#ifdef __GNUC__
+	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#else
+	{ volatile register unsigned int Reg __asm(XREG_CP15_SYS_CONTROL);
+	  CtrlReg = Reg; }
+#endif
+	if (CtrlReg & XREG_CP15_CONTROL_I_BIT) {
+		return;
+	}
+
+	/* invalidate the instruction cache */
+	mtcp(XREG_CP15_INVAL_IC_POU, 0);
+
+	/* enable the instruction cache */
+	CtrlReg |= (XREG_CP15_CONTROL_I_BIT);
+
+	mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/****************************************************************************
+*
+* Disable level 1 the instruction cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L1ICacheDisable(void)
+{
+	register unsigned int CtrlReg;
+
+	dsb();
+
+	/* invalidate the instruction cache */
+	mtcp(XREG_CP15_INVAL_IC_POU, 0);
+
+	/* disable the instruction cache */
+#ifdef __GNUC__
+	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#else
+	{ volatile register unsigned int Reg __asm(XREG_CP15_SYS_CONTROL);
+	  CtrlReg = Reg; }
+#endif
+	CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT);
+
+	mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/****************************************************************************
+*
+* Invalidate the entire level 1 instruction cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L1ICacheInvalidate(void)
+{
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 1);
+	/* invalidate the instruction cache */
+	mtcp(XREG_CP15_INVAL_IC_POU, 0);
+
+	/* Wait for L1 invalidate to complete */
+	dsb();
+}
+
+/****************************************************************************
+*
+* Invalidate a level 1  instruction cache line.	If the instruction specified by
+* the parameter adr is cached by the instruction cache, the cacheline containing
+* that instruction is invalidated.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		The bottom 5 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L1ICacheInvalidateLine(unsigned int adr)
+{
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 1);
+	mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, (adr & (~0x1F)));
+
+	/* Wait for L1 invalidate to complete */
+	dsb();
+}
+
+/****************************************************************************
+*
+* Invalidate the level 1 instruction cache for the given address range.
+* If the bytes specified by the address (adr) are cached by the Data cache,
+* the cacheline containing that byte is invalidated.	If the cacheline
+* is modified (dirty), the modified contents are lost and are NOT
+* written to system memory before the line is invalidated.
+*
+* @param	Start address of range to be invalidated.
+* @param	Length of range to be invalidated in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L1ICacheInvalidateRange(unsigned int adr, unsigned len)
+{
+	const unsigned cacheline = 32;
+	unsigned int end;
+	unsigned int currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	if (len != 0) {
+		/* Back the starting address up to the start of a cache line
+		 * perform cache operations until adr+len
+		 */
+		end = adr + len;
+		adr = adr & ~(cacheline - 1);
+
+		/* Select cache L0 I-cache in CSSR */
+		mtcp(XREG_CP15_CACHE_SIZE_SEL, 1);
+
+		while (adr < end) {
+#ifdef __GNUC__
+			__asm__ __volatile__("mcr " \
+			XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (adr));
+#else
+			{ volatile register unsigned int Reg
+				__asm(XREG_CP15_INVAL_IC_LINE_MVA_POU);
+			  Reg = adr; }
+#endif
+			adr += cacheline;
+		}
+	}
+
+	/* Wait for L1 invalidate to complete */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Enable the L2 cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L2CacheEnable(void)
+{
+	register unsigned int L2CCReg;
+
+	L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
+
+	/* only enable if L2CC is currently disabled */
+	if ((L2CCReg & 0x01) == 0) {
+		/* set up the way size and latencies */
+		L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
+				   XPS_L2CC_AUX_CNTRL_OFFSET);
+		L2CCReg &= XPS_L2CC_AUX_REG_ZERO_MASK;
+		L2CCReg |= XPS_L2CC_AUX_REG_DEFAULT_MASK;
+		Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_AUX_CNTRL_OFFSET,
+			  L2CCReg);
+		Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_TAG_RAM_CNTRL_OFFSET,
+			  XPS_L2CC_TAG_RAM_DEFAULT_MASK);
+		Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DATA_RAM_CNTRL_OFFSET,
+			  XPS_L2CC_DATA_RAM_DEFAULT_MASK);
+
+		/* Clear the pending interrupts */
+		L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
+				   XPS_L2CC_ISR_OFFSET);
+		Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_IAR_OFFSET, L2CCReg);
+
+		Xil_L2CacheInvalidate();
+		/* Enable the L2CC */
+		L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
+				   XPS_L2CC_CNTRL_OFFSET);
+		Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET,
+			  (L2CCReg | (0x01)));
+
+        Xil_L2CacheSync();
+        /* synchronize the processor */
+	    dsb();
+
+    }
+}
+
+/****************************************************************************
+*
+* Disable the L2 cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L2CacheDisable(void)
+{
+    register unsigned int L2CCReg;
+
+	L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
+
+    if(L2CCReg & 0x1) {
+
+        /* Clean and Invalidate L2 Cache */
+        Xil_L2CacheFlush();
+
+	    /* Disable the L2CC */
+    	L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
+	    Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET,
+		      (L2CCReg & (~0x01)));
+		/* Wait for the cache operations to complete */
+
+		dsb();
+    }
+}
+
+/****************************************************************************
+*
+* Invalidate the L2 cache. If the byte specified by the address (adr)
+* is cached by the Data cache, the cacheline containing that byte is
+* invalidated.	If the cacheline is modified (dirty), the modified contents
+* are lost and are NOT written to system memory before the line is
+* invalidated.
+*
+* @param	Address to be flushed.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L2CacheInvalidate(void)
+{
+	/* Invalidate the caches */
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET,
+		  0x0000FFFF);
+	while((Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET))
+																& 0x0000FFFF);
+
+	/* Wait for the invalidate to complete */
+	Xil_L2CacheSync();
+
+	/* synchronize the processor */
+	dsb();
+}
+
+/****************************************************************************
+*
+* Invalidate a level 2 cache line. If the byte specified by the address (adr)
+* is cached by the Data cache, the cacheline containing that byte is
+* invalidated.	If the cacheline is modified (dirty), the modified contents
+* are lost and are NOT written to system memory before the line is
+* invalidated.
+*
+* @param	Address to be flushed.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L2CacheInvalidateLine(unsigned int adr)
+{
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, adr);
+	/* synchronize the processor */
+	dsb();
+}
+
+/****************************************************************************
+*
+* Invalidate the level 2 cache for the given address range.
+* If the bytes specified by the address (adr) are cached by the Data cache,
+* the cacheline containing that byte is invalidated.	If the cacheline
+* is modified (dirty), the modified contents are lost and are NOT
+* written to system memory before the line is invalidated.
+*
+* @param	Start address of range to be invalidated.
+* @param	Length of range to be invalidated in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L2CacheInvalidateRange(unsigned int adr, unsigned len)
+{
+	const unsigned cacheline = 32;
+	unsigned int end;
+	volatile u32 *L2CCOffset = (volatile u32 *) (XPS_L2CC_BASEADDR +
+				    XPS_L2CC_CACHE_INVLD_PA_OFFSET);
+
+	unsigned int currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	if (len != 0) {
+		/* Back the starting address up to the start of a cache line
+		 * perform cache operations until adr+len
+		 */
+		end = adr + len;
+		adr = adr & ~(cacheline - 1);
+
+		/* Disable Write-back and line fills */
+		Xil_L2WriteDebugCtrl(0x3);
+
+		while (adr < end) {
+			*L2CCOffset = adr;
+			adr += cacheline;
+		}
+
+		/* Enable Write-back and line fills */
+		Xil_L2WriteDebugCtrl(0x0);
+	}
+
+	/* synchronize the processor */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Flush the L2 cache. If the byte specified by the address (adr)
+* is cached by the Data cache, the cacheline containing that byte is
+* invalidated. If the cacheline is modified (dirty), the entire
+* contents of the cacheline are written to system memory before the
+* line is invalidated.
+*
+* @param	Address to be flushed.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L2CacheFlush(void)
+{
+
+	/* Flush the caches */
+
+	/* Disable Write-back and line fills */
+	Xil_L2WriteDebugCtrl(0x3);
+
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET,
+		  0x0000FFFF);
+
+	while((Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET))
+															& 0x0000FFFF);
+
+	Xil_L2CacheSync();
+	/* Enable Write-back and line fills */
+	Xil_L2WriteDebugCtrl(0x0);
+
+	/* synchronize the processor */
+	dsb();
+}
+
+/****************************************************************************
+*
+* Flush a level 2 cache line. If the byte specified by the address (adr)
+* is cached by the Data cache, the cacheline containing that byte is
+* invalidated. If the cacheline is modified (dirty), the entire
+* contents of the cacheline are written to system memory before the
+* line is invalidated.
+*
+* @param	Address to be flushed.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L2CacheFlushLine(unsigned int adr)
+{
+#ifdef CONFIG_PL310_ERRATA_588369
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr);
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, adr);
+#else
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_PA_OFFSET, adr);
+#endif
+	/* synchronize the processor */
+	dsb();
+}
+
+/****************************************************************************
+* Flush the level 2 cache for the given address range.
+* If the bytes specified by the address (adr) are cached by the Data cache,
+* the cacheline containing that byte is invalidated.	If the cacheline
+* is modified (dirty), the written to system memory first before the
+* before the line is invalidated.
+*
+* @param	Start address of range to be flushed.
+* @param	Length of range to be flushed in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L2CacheFlushRange(unsigned int adr, unsigned len)
+{
+	const unsigned cacheline = 32;
+	unsigned int end;
+	volatile u32 *L2CCOffset = (volatile u32 *) (XPS_L2CC_BASEADDR +
+				    XPS_L2CC_CACHE_INV_CLN_PA_OFFSET);
+
+	unsigned int currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+	if (len != 0) {
+		/* Back the starting address up to the start of a cache line
+		 * perform cache operations until adr+len
+		 */
+		end = adr + len;
+		adr = adr & ~(cacheline - 1);
+
+		/* Disable Write-back and line fills */
+		Xil_L2WriteDebugCtrl(0x3);
+
+		while (adr < end) {
+			*L2CCOffset = adr;
+			Xil_L2CacheSync();
+			adr += cacheline;
+		}
+
+		/* Enable Write-back and line fills */
+		Xil_L2WriteDebugCtrl(0x0);
+	}
+	/* synchronize the processor */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Store a level 2 cache line. If the byte specified by the address (adr)
+* is cached by the Data cache and the cacheline is modified (dirty),
+* the entire contents of the cacheline are written to system memory.
+* After the store completes, the cacheline is marked as unmodified
+* (not dirty).
+*
+* @param	Address to be stored.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L2CacheStoreLine(unsigned int adr)
+{
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr);
+	/* synchronize the processor */
+	dsb();
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_cache.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_cache.h
new file mode 100644
index 000000000..e1e0adaac
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_cache.h
@@ -0,0 +1,84 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache.h
+*
+* Contains required functions for the ARM cache functionality
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  01/29/10 First release
+* 3.04a sdm  01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
+*		      APIs.
+* 

+*
+******************************************************************************/
+#ifndef XIL_CACHE_H
+#define XIL_CACHE_H
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void Xil_DCacheEnable(void);
+void Xil_DCacheDisable(void);
+void Xil_DCacheInvalidate(void);
+void Xil_DCacheInvalidateRange(unsigned int adr, unsigned len);
+void Xil_DCacheFlush(void);
+void Xil_DCacheFlushRange(unsigned int adr, unsigned len);
+
+void Xil_ICacheEnable(void);
+void Xil_ICacheDisable(void);
+void Xil_ICacheInvalidate(void);
+void Xil_ICacheInvalidateRange(unsigned int adr, unsigned len);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_cache_l.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_cache_l.h
new file mode 100644
index 000000000..d0c3f40e6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_cache_l.h
@@ -0,0 +1,103 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache_l.h
+*
+* Contains L1 and L2 specific functions for the ARM cache functionality
+* used by xcache.c. This functionality is being made available here for
+* more sophisticated users.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  01/24/10 First release
+* 

+*
+******************************************************************************/
+#ifndef XIL_CACHE_MACH_H
+#define XIL_CACHE_MACH_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void Xil_DCacheInvalidateLine(unsigned int adr);
+void Xil_DCacheFlushLine(unsigned int adr);
+void Xil_DCacheStoreLine(unsigned int adr);
+void Xil_ICacheInvalidateLine(unsigned int adr);
+
+void Xil_L1DCacheEnable(void);
+void Xil_L1DCacheDisable(void);
+void Xil_L1DCacheInvalidate(void);
+void Xil_L1DCacheInvalidateLine(unsigned int adr);
+void Xil_L1DCacheInvalidateRange(unsigned int adr, unsigned len);
+void Xil_L1DCacheFlush(void);
+void Xil_L1DCacheFlushLine(unsigned int adr);
+void Xil_L1DCacheFlushRange(unsigned int adr, unsigned len);
+void Xil_L1DCacheStoreLine(unsigned int adr);
+
+void Xil_L1ICacheEnable(void);
+void Xil_L1ICacheDisable(void);
+void Xil_L1ICacheInvalidate(void);
+void Xil_L1ICacheInvalidateLine(unsigned int adr);
+void Xil_L1ICacheInvalidateRange(unsigned int adr, unsigned len);
+
+void Xil_L2CacheEnable(void);
+void Xil_L2CacheDisable(void);
+void Xil_L2CacheInvalidate(void);
+void Xil_L2CacheInvalidateLine(unsigned int adr);
+void Xil_L2CacheInvalidateRange(unsigned int adr, unsigned len);
+void Xil_L2CacheFlush(void);
+void Xil_L2CacheFlushLine(unsigned int adr);
+void Xil_L2CacheFlushRange(unsigned int adr, unsigned len);
+void Xil_L2CacheStoreLine(unsigned int adr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_cache_vxworks.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_cache_vxworks.h
new file mode 100644
index 000000000..3ad8965df
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_cache_vxworks.h
@@ -0,0 +1,103 @@
+/******************************************************************************
+*
+* (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache_vxworks.h
+*
+* Contains the cache related functions for VxWorks that is wrapped by
+* xil_cache. 
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  12/11/09 Initial release
+*
+* 

+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_CACHE_VXWORKS_H
+#define XIL_CACHE_VXWORKS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "vxWorks.h"
+#include "vxLib.h"
+#include "sysLibExtra.h"
+#include "cacheLib.h"
+
+#if (CPU_FAMILY==PPC)
+
+#define Xil_DCacheEnable()		cacheEnable(DATA_CACHE)
+
+#define Xil_DCacheDisable()		cacheDisable(DATA_CACHE)
+
+#define Xil_DCacheInvalidateRange(Addr, Len) \
+		cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_DCacheFlushRange(Addr, Len) \
+		cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_ICacheEnable()		cacheEnable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheDisable()		cacheDisable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheInvalidateRange(Addr, Len) \
+		cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
+
+
+#else
+#error "Unknown processor / architecture. Must be PPC for VxWorks."
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_errata.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_errata.h
new file mode 100644
index 000000000..bb09eef3f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_errata.h
@@ -0,0 +1,117 @@
+/*******************************************************************************
+*
+* (c) Copyright 2013 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_errata.h
+*
+* This header file contains Cortex A9 and PL310 Errata definitions.
+*
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a srt  04/18/13 First release
+* 

+*
+******************************************************************************/
+#ifndef XIL_ERRATA_H
+#define XIL_ERRATA_H
+
+#define ENABLE_ARM_ERRATA 1
+
+#ifdef ENABLE_ARM_ERRATA
+/* Cortex A9 ARM Errata */
+
+/*
+ *  Errata No: 	 742230
+ *  Description: DMB operation may be faulty
+ */
+#define CONFIG_ARM_ERRATA_742230 1
+
+/*
+ *  Errata No: 	 743622
+ *  Description: Faulty hazard checking in the Store Buffer may lead
+ *	         to data corruption.
+ */
+#define CONFIG_ARM_ERRATA_743622 1
+
+/*
+ *  Errata No: 	 775420
+ *  Description: A data cache maintenance operation which aborts, 
+ *		 might lead to deadlock
+ */
+#define CONFIG_ARM_ERRATA_775420 1
+
+/*
+ *  Errata No: 	 794073
+ *  Description: Speculative instruction fetches with MMU disabled 
+ *               might not comply with architectural requirements
+ */
+#define CONFIG_ARM_ERRATA_794073 1
+
+
+/* PL310 L2 Cache Errata */
+
+/*
+ *  Errata No: 	 588369
+ *  Description: Clean & Invalidate maintenance operations do not 
+ *	   	 invalidate clean lines
+ */
+#define CONFIG_PL310_ERRATA_588369 1
+
+/*
+ *  Errata No: 	 727915
+ *  Description: Background Clean and Invalidate by Way operation
+ *		 can cause data corruption
+ */
+#define CONFIG_PL310_ERRATA_727915 1
+
+/*
+ *  Errata No: 	 753970
+ *  Description: Cache sync operation may be faulty
+ */
+#define CONFIG_PL310_ERRATA_753970 1
+
+#endif  /* ENABLE_ARM_ERRATA */
+
+#endif  /* XIL_ERRATA_H */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_exception.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_exception.c
new file mode 100644
index 000000000..77ab9986d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_exception.c
@@ -0,0 +1,188 @@
+/*****************************************************************************
+*
+* (c) Copyright 2009-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xil_exception.c
+*
+* This file contains low-level driver functions for the Cortex A9 exception
+* Handler.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  11/04/09 First release
+* 3.05a sdm	 02/02/12 Updated to resiter a null handler only if a handler
+*			  is not already registered
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+#include "xpseudo_asm.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+typedef struct {
+	Xil_ExceptionHandler Handler;
+	void *Data;
+} XExc_VectorTableEntry;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+
+/************************** Variable Definitions *****************************/
+/*
+ * Exception vector table to store handlers for each exception vector.
+ */
+XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1];
+
+/*****************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* This function is a stub Handler that is the default Handler that gets called
+* if the application has not setup a Handler for a specific  exception. The
+* function interface has to match the interface specified for a Handler even
+* though none of the arguments are used.
+*
+* @param	Data is unused by this function.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void Xil_ExceptionNullHandler(void *Data)
+{
+	(void)Data;
+DieLoop: goto DieLoop;
+}
+
+/****************************************************************************/
+/**
+*
+* Initialize exception handling for the Processor. The exception vector table
+* is setup with the stub Handler for all exceptions.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xil_ExceptionInit(void)
+{
+	unsigned long index;
+
+	/*
+	 * Initialize the vector table. Register the stub Handler for each
+	 * exception.
+	 */
+	for(index = XIL_EXCEPTION_ID_FIRST; index < XIL_EXCEPTION_ID_LAST + 1;
+	    index++) {
+		if (XExc_VectorTable[index].Handler == NULL) {
+			Xil_ExceptionRegisterHandler(index,
+						     Xil_ExceptionNullHandler,
+						     NULL);
+		}
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Makes the connection between the Id of the exception source and the
+* associated Handler that is to run when the exception is recognized. The
+* argument provided in this call as the Data is used as the argument
+* for the Handler when it is called.
+*
+* @param	exception_id contains the ID of the exception source and should
+*		be in the range of 0 to XIL_EXCEPTION_ID_LAST.
+		See xil_exception_l.h for further information.
+* @param	Handler to the Handler for that exception.
+* @param	Data is a reference to Data that will be passed to the
+*		Handler when it gets called.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ExceptionRegisterHandler(u32 exception_id,
+				    Xil_ExceptionHandler Handler,
+				    void *Data)
+{
+	XExc_VectorTable[exception_id].Handler = Handler;
+	XExc_VectorTable[exception_id].Data = Data;
+}
+
+/*****************************************************************************/
+/**
+*
+* Removes the Handler for a specific exception Id. The stub Handler is then
+* registered for this exception Id.
+*
+* @param	exception_id contains the ID of the exception source and should
+*		be in the range of 0 to XIL_EXCEPTION_ID_LAST.
+*		See xil_exception_l.h for further information.
+
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ExceptionRemoveHandler(u32 exception_id)
+{
+	Xil_ExceptionRegisterHandler(exception_id,
+				       Xil_ExceptionNullHandler,
+				       NULL);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_exception.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_exception.h
new file mode 100644
index 000000000..dfe2285e8
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_exception.h
@@ -0,0 +1,231 @@
+/******************************************************************************
+*
+* (c) Copyright 2009-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_exception.h
+*
+* This header file contains ARM Cortex A9 specific exception related APIs.
+* For exception related functions that can be used across all Xilinx supported
+* processors, please use xil_exception.h.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  11/04/09 First release
+* 

+*
+******************************************************************************/
+
+#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
+#define XIL_EXCEPTION_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions ****************************/
+
+#define XIL_EXCEPTION_FIQ	XREG_CPSR_FIQ_ENABLE
+#define XIL_EXCEPTION_IRQ	XREG_CPSR_IRQ_ENABLE
+#define XIL_EXCEPTION_ALL	(XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
+
+#define XIL_EXCEPTION_ID_FIRST			0
+#define XIL_EXCEPTION_ID_RESET			0
+#define XIL_EXCEPTION_ID_UNDEFINED_INT		1
+#define XIL_EXCEPTION_ID_SWI_INT		2
+#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT	3
+#define XIL_EXCEPTION_ID_DATA_ABORT_INT		4
+#define XIL_EXCEPTION_ID_IRQ_INT		5
+#define XIL_EXCEPTION_ID_FIQ_INT		6
+#define XIL_EXCEPTION_ID_LAST			6
+
+/*
+ * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
+ */
+#define XIL_EXCEPTION_ID_INT	XIL_EXCEPTION_ID_IRQ_INT
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef is the exception handler function.
+ */
+typedef void (*Xil_ExceptionHandler)(void *data);
+typedef void (*Xil_InterruptHandler)(void *data);
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* Enable Exceptions.
+*
+* @param	Mask for exceptions to be enabled.
+*
+* @return	None.
+*
+* @note		If bit is 0, exception is enabled.
+*		C-Style signature: void Xil_ExceptionEnableMask(Mask);
+*
+******************************************************************************/
+#ifdef __GNUC__
+#define Xil_ExceptionEnableMask(Mask)	\
+		mtcpsr(mfcpsr() & ~ (Mask & XIL_EXCEPTION_ALL))
+#else
+#define Xil_ExceptionEnableMask(Mask)	\
+		{ register unsigned int Reg __asm("cpsr"); \
+		  mtcpsr(Reg & ~ (Mask & XIL_EXCEPTION_ALL)) }
+#endif
+
+/****************************************************************************/
+/**
+* Enable the IRQ exception.
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+#define Xil_ExceptionEnable() \
+		Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
+
+/****************************************************************************/
+/**
+* Disable Exceptions.
+*
+* @param	Mask for exceptions to be enabled.
+*
+* @return	None.
+*
+* @note		If bit is 1, exception is disabled.
+*		C-Style signature: Xil_ExceptionDisableMask(Mask);
+*
+******************************************************************************/
+#ifdef __GNUC__
+#define Xil_ExceptionDisableMask(Mask)	\
+		mtcpsr(mfcpsr() | (Mask & XIL_EXCEPTION_ALL))
+#else
+#define Xil_ExceptionDisableMask(Mask)	\
+		{ register unsigned int Reg __asm("cpsr"); \
+		  mtcpsr(Reg | (Mask & XIL_EXCEPTION_ALL)) }
+#endif
+
+/****************************************************************************/
+/**
+* Disable the IRQ exception.
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+#define Xil_ExceptionDisable() \
+		Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
+
+/****************************************************************************/
+/**
+* Enable nested interrupts by clearing the I and F bits it CPSR
+*
+* @return   None.
+*
+* @note     This macro is supposed to be used from interrupt handlers. In the
+*			interrupt handler the interrupts are disabled by default (I and F
+*			are 1). To allow nesting of interrupts, this macro should be
+*			used. It clears the I and F bits by changing the ARM mode to
+*			system mode. Once these bits are cleared and provided the
+*			preemption of interrupt conditions are met in the GIC, nesting of
+*			interrupts will start happening.
+*			Caution: This macro must be used with caution. Before calling this
+*			macro, the user must ensure that the source of the current IRQ
+*			is appropriately cleared. Otherwise, as soon as we clear the I and
+*			F bits, there can be an infinite loop of interrupts with an
+*			eventual crash (all the stack space getting consumed).
+******************************************************************************/
+#define Xil_EnableNestedInterrupts() \
+		__asm__ __volatile__ ("mrs     lr, spsr");  \
+		__asm__ __volatile__ ("stmfd   sp!, {lr}"); \
+		__asm__ __volatile__ ("msr     cpsr_c, #0x1F"); \
+		__asm__ __volatile__ ("stmfd   sp!, {lr}");
+
+/****************************************************************************/
+/**
+* Disable the nested interrupts by setting the I and F bits.
+*
+* @return   None.
+*
+* @note     This macro is meant to be called in the interrupt service routines.
+*			This macro cannot be used independently. It can only be used when
+*			nesting of interrupts have been enabled by using the macro
+*			Xil_EnableNestedInterrupts(). In a typical flow, the user first
+*			calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
+*			point. The user then must call this macro before exiting the interrupt
+*			service routine. This macro puts the ARM back in IRQ/FIQ mode and
+*			hence sets back the I and F bits.
+******************************************************************************/
+#define Xil_DisableNestedInterrupts() \
+		__asm__ __volatile__ ("ldmfd   sp!, {lr}");   \
+		__asm__ __volatile__ ("msr     cpsr_c, #0x92"); \
+		__asm__ __volatile__ ("ldmfd   sp!, {lr}"); \
+		__asm__ __volatile__ ("msr     spsr_cxsf, lr");
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+extern void Xil_ExceptionRegisterHandler(u32 id,
+					 Xil_ExceptionHandler handler,
+					 void *data);
+
+extern void Xil_ExceptionRemoveHandler(u32 id);
+
+extern void Xil_ExceptionInit(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_EXCEPTION_H */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_hal.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_hal.h
new file mode 100644
index 000000000..b58c7eb8a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_hal.h
@@ -0,0 +1,71 @@
+/******************************************************************************
+*
+* (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_hal.h
+*
+* Contains all the HAL header files.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/28/09 Initial release
+*
+* 

+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_HAL_H
+#define XIL_HAL_H
+
+#include "xil_cache.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+#include "xil_types.h"
+
+#endif
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_io.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_io.c
new file mode 100644
index 000000000..a091b232e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_io.c
@@ -0,0 +1,350 @@
+/******************************************************************************
+*
+* (c) Copyright 2009-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+*******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.c
+*
+* Contains I/O functions for memory-mapped or non-memory-mapped I/O
+* architectures.  These functions encapsulate Cortex A9 architecture-specific
+* I/O requirements.
+*
+* @note
+*
+* This file contains architecture-dependent code.
+* 
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  10/24/09 First release
+* 3.06a sgd      05/15/12 Pointer volatile used for the all read functions
+* 3.07a sgd      08/17/12 Removed barriers (SYNCHRONIZE_IO) calls.
+* 3.09a sgd      02/05/13 Comments cleanup 
+* 

+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+#include "xil_io.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xpseudo_asm.h"
+#include "xreg_cortexa9.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for an 8-bit memory location by reading from the
+* specified address and returning the Value read from that address.
+*
+* @param	Addr contains the address to perform the input operation
+*		at.
+*
+* @return	The Value read from the specified input address.
+*
+* @note		None.
+*
+******************************************************************************/
+u8 Xil_In8(u32 Addr)
+{
+	return *(volatile u8 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 16-bit memory location by reading from the
+* specified address and returning the Value read from that address.
+*
+* @param	Addr contains the address to perform the input operation
+*		at.
+*
+* @return	The Value read from the specified input address.
+*
+* @note		None.
+*
+******************************************************************************/
+u16 Xil_In16(u32 Addr)
+{
+	return *(volatile u16 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 32-bit memory location by reading from the
+* specified address and returning the Value read from that address.
+*
+* @param	Addr contains the address to perform the input operation
+*		at.
+*
+* @return	The Value read from the specified input address.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 Xil_In32(u32 Addr)
+{
+	return *(volatile u32 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for an 8-bit memory location by writing the
+* specified Value to the the specified address.
+*
+* @param	OutAddress contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void Xil_Out8(u32 OutAddress, u8 Value)
+{
+	*(volatile u8 *) OutAddress = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 16-bit memory location by writing the
+* specified Value to the the specified address.
+*
+* @param	OutAddress contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void Xil_Out16(u32 OutAddress, u16 Value)
+{
+	*(volatile u16 *) OutAddress = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 32-bit memory location by writing the
+* specified Value to the the specified address.
+*
+* @param	OutAddress contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void Xil_Out32(u32 OutAddress, u32 Value)
+{
+	*(volatile u32 *) OutAddress = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 16-bit memory location by reading from the
+* specified address and returning the byte-swapped Value read from that
+* address.
+*
+* @param	Addr contains the address to perform the input operation
+*		at.
+*
+* @return	The byte-swapped Value read from the specified input address.
+*
+* @note		None.
+*
+******************************************************************************/
+u16 Xil_In16BE(u32 Addr)
+{
+	u16 temp;
+	u16 result;
+
+	temp = Xil_In16(Addr);
+
+	result = Xil_EndianSwap16(temp);
+
+	return result;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 32-bit memory location by reading from the
+* specified address and returning the byte-swapped Value read from that
+* address.
+*
+* @param	Addr contains the address to perform the input operation
+*		at.
+*
+* @return	The byte-swapped Value read from the specified input address.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 Xil_In32BE(u32 Addr)
+{
+	u32 temp;
+	u32 result;
+
+	temp = Xil_In32(Addr);
+
+	result = Xil_EndianSwap32(temp);
+
+	return result;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 16-bit memory location by writing the
+* specified Value to the the specified address. The Value is byte-swapped
+* before being written.
+*
+* @param	OutAddress contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void Xil_Out16BE(u32 OutAddress, u16 Value)
+{
+	u16 temp;
+
+	temp = Xil_EndianSwap16(Value);
+
+    Xil_Out16(OutAddress, temp);
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 32-bit memory location by writing the
+* specified Value to the the specified address. The Value is byte-swapped
+* before being written.
+*
+* @param	OutAddress contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void Xil_Out32BE(u32 OutAddress, u32 Value)
+{
+	u32 temp;
+
+	temp = Xil_EndianSwap32(Value);
+
+    Xil_Out32(OutAddress, temp);
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a 16-bit endian converion.
+*
+* @param	Data contains the value to be converted.
+*
+* @return	converted value.
+*
+* @note		None.
+*
+******************************************************************************/
+u16 Xil_EndianSwap16(u16 Data)
+{
+	return (u16) (((Data & 0xFF00) >> 8) | ((Data & 0x00FF) << 8));
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a 32-bit endian converion.
+*
+* @param	Data contains the value to be converted.
+*
+* @return	converted value.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 Xil_EndianSwap32(u32 Data)
+{
+	u16 LoWord;
+	u16 HiWord;
+
+	/* get each of the half words from the 32 bit word */
+
+	LoWord = (u16) (Data & 0x0000FFFF);
+	HiWord = (u16) ((Data & 0xFFFF0000) >> 16);
+
+	/* byte swap each of the 16 bit half words */
+
+	LoWord = (((LoWord & 0xFF00) >> 8) | ((LoWord & 0x00FF) << 8));
+	HiWord = (((HiWord & 0xFF00) >> 8) | ((HiWord & 0x00FF) << 8));
+
+	/* swap the half words before returning the value */
+
+	return (u32) ((LoWord << 16) | HiWord);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_io.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_io.h
new file mode 100644
index 000000000..06e83bfa8
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_io.h
@@ -0,0 +1,254 @@
+/******************************************************************************
+*
+* (c) Copyright 2009-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.h
+*
+* This file contains the interface for the general IO component, which
+* encapsulates the Input/Output functions for processors that do not
+* require any special I/O handling.
+*
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  10/24/09 First release
+* 1.00a sdm      07/21/10 Added Xil_Htonl/s, Xil_Ntohl/s
+* 3.07a asa	     08/31/12 Added xil_printf.h include
+* 3.08a sgd	     11/05/12 Reverted SYNC macros definitions
+* 

+******************************************************************************/
+
+#ifndef XIL_IO_H           /* prevent circular inclusions */
+#define XIL_IO_H           /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+#include "xil_printf.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#if defined __GNUC__
+#  define SYNCHRONIZE_IO	dmb()
+#  define INST_SYNC		isb()
+#  define DATA_SYNC		dsb()
+#else
+#  define SYNCHRONIZE_IO
+#  define INST_SYNC
+#  define DATA_SYNC
+#endif /* __GNUC__ */
+
+/*****************************************************************************/
+/**
+*
+* Perform an big-endian input operation for a 16-bit memory location
+* by reading from the specified address and returning the Value read from
+* that address.
+*
+* @param	Addr contains the address to perform the input operation at.
+*
+* @return	The Value read from the specified input address with the
+*		proper endianness. The return Value has the same endianness
+*		as that of the processor, i.e. if the processor is
+*		little-engian, the return Value is the byte-swapped Value read
+*		from the address.
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_In16LE(Addr) Xil_In16(Addr)
+
+/*****************************************************************************/
+/**
+*
+* Perform a big-endian input operation for a 32-bit memory location
+* by reading from the specified address and returning the Value read from
+* that address.
+*
+* @param	Addr contains the address to perform the input operation at.
+*
+* @return	The Value read from the specified input address with the
+*		proper endianness. The return Value has the same endianness
+*		as that of the processor, i.e. if the processor is
+*		little-engian, the return Value is the byte-swapped Value read
+*		from the address.
+*
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_In32LE(Addr) Xil_In32(Addr)
+
+/*****************************************************************************/
+/**
+*
+* Perform a big-endian output operation for a 16-bit memory location
+* by writing the specified Value to the specified address.
+*
+* @param	Addr contains the address to perform the output operation at.
+* @param	Value contains the Value to be output at the specified address.
+*		The Value has the same endianness as that of the processor.
+*		If the processor is little-endian, the byte-swapped Value is
+*		written to the address.
+*
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Out16LE(Addr, Value) Xil_Out16(Addr, Value)
+
+/*****************************************************************************/
+/**
+*
+* Perform a big-endian output operation for a 32-bit memory location
+* by writing the specified Value to the specified address.
+*
+* @param	Addr contains the address to perform the output operation at.
+* @param	Value contains the Value to be output at the specified address.
+*		The Value has the same endianness as that of the processor.
+*		If the processor is little-endian, the byte-swapped Value is
+*		written to the address.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Out32LE(Addr, Value) Xil_Out32(Addr, Value)
+
+/*****************************************************************************/
+/**
+*
+* Convert a 32-bit number from host byte order to network byte order.
+*
+* @param	Data the 32-bit number to be converted.
+*
+* @return	The converted 32-bit number in network byte order.
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Htonl(Data) Xil_EndianSwap32(Data)
+
+/*****************************************************************************/
+/**
+*
+* Convert a 16-bit number from host byte order to network byte order.
+*
+* @param	Data the 16-bit number to be converted.
+*
+* @return	The converted 16-bit number in network byte order.
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Htons(Data) Xil_EndianSwap16(Data)
+
+/*****************************************************************************/
+/**
+*
+* Convert a 32-bit number from network byte order to host byte order.
+*
+* @param	Data the 32-bit number to be converted.
+*
+* @return	The converted 32-bit number in host byte order.
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Ntohl(Data) Xil_EndianSwap32(Data)
+
+/*****************************************************************************/
+/**
+*
+* Convert a 16-bit number from network byte order to host byte order.
+*
+* @param	Data the 16-bit number to be converted.
+*
+* @return	The converted 16-bit number in host byte order.
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Ntohs(Data) Xil_EndianSwap16(Data)
+
+/************************** Function Prototypes ******************************/
+
+/* The following functions allow the software to be transportable across
+ * processors which may use memory mapped I/O or I/O which is mapped into a
+ * seperate address space.
+ */
+u8 Xil_In8(u32 Addr);
+u16 Xil_In16(u32 Addr);
+u32 Xil_In32(u32 Addr);
+
+void Xil_Out8(u32 Addr, u8 Value);
+void Xil_Out16(u32 Addr, u16 Value);
+void Xil_Out32(u32 Addr, u32 Value);
+
+u16 Xil_In16BE(u32 Addr);
+u32 Xil_In32BE(u32 Addr);
+void Xil_Out16BE(u32 Addr, u16 Value);
+void Xil_Out32BE(u32 Addr, u32 Value);
+
+u16 Xil_EndianSwap16(u16 Data);
+u32 Xil_EndianSwap32(u32 Data);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_macroback.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_macroback.h
new file mode 100644
index 000000000..c614daaf5
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_macroback.h
@@ -0,0 +1,1069 @@
+/*********************************************************************/
+/**
+ * (c) Copyright 2010 Xilinx, Inc. All rights reserved.
+ * 
+ * This file contains confidential and proprietary information
+ * of Xilinx, Inc. and is protected under U.S. and
+ * international copyright and other intellectual property
+ * laws.
+ * 
+ * DISCLAIMER
+ * This disclaimer is not a license and does not grant any
+ * rights to the materials distributed herewith. Except as
+ * otherwise provided in a valid license issued to you by
+ * Xilinx, and to the maximum extent permitted by applicable
+ * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+ * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+ * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+ * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+ * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+ * (2) Xilinx shall not be liable (whether in contract or tort,
+ * including negligence, or under any other theory of
+ * liability) for any loss or damage of any kind or nature
+ * related to, arising under or in connection with these
+ * materials, including for any direct, or any indirect,
+ * special, incidental, or consequential loss or damage
+ * (including loss of data, profits, goodwill, or any type of
+ * loss or damage suffered as a result of any action brought
+ * by a third party) even if such damage or loss was
+ * reasonably foreseeable or Xilinx had been advised of the
+ * possibility of the same.
+ * 
+ * CRITICAL APPLICATIONS
+ * Xilinx products are not designed or intended to be fail-
+ * safe, or for use in any application requiring fail-safe
+ * performance, such as life-support or safety devices or
+ * systems, Class III medical devices, nuclear facilities,
+ * applications related to the deployment of airbags, or any
+ * other applications that could lead to death, personal
+ * injury, or severe property or environmental damage
+ * (individually and collectively, "Critical
+ * Applications"). Customer assumes the sole risk and
+ * liability of any use of Xilinx products in Critical
+ * Applications, subject only to applicable laws and
+ * regulations governing limitations on product liability.
+ * 
+ * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+ * PART OF THIS FILE AT ALL TIMES.
+ *********************************************************************/
+
+/*********************************************************************/
+/**
+ * @file xil_macroback.h
+ * 
+ * This header file is meant to bring back the removed _m macros.
+ * This header file must be included last.
+ * The following macros are not defined here due to the driver change:
+ *   XGpio_mSetDataDirection
+ *   XGpio_mGetDataReg
+ *   XGpio_mSetDataReg
+ *   XIIC_RESET
+ *   XIIC_CLEAR_STATS
+ *   XSpi_mReset
+ *   XSysAce_mSetCfgAddr
+ *   XSysAce_mIsCfgDone
+ *   XTft_mSetPixel
+ *   XTft_mGetPixel
+ *   XWdtTb_mEnableWdt
+ *   XWdtTb_mDisbleWdt
+ *   XWdtTb_mRestartWdt
+ *   XWdtTb_mGetTimebaseReg
+ *   XWdtTb_mHasReset
+ * 
+ * Please refer the corresonding driver document for replacement.
+ * 
+ *********************************************************************/
+
+#ifndef XIL_MACROBACK_H
+#define XIL_MACROBACK_H
+
+/*********************************************************************/
+/**
+ * Macros for Driver XCan
+ * 
+ *********************************************************************/
+#ifndef XCan_mReadReg
+#define XCan_mReadReg XCan_ReadReg
+#endif
+
+#ifndef XCan_mWriteReg
+#define XCan_mWriteReg XCan_WriteReg
+#endif
+
+#ifndef XCan_mIsTxDone
+#define XCan_mIsTxDone XCan_IsTxDone
+#endif
+
+#ifndef XCan_mIsTxFifoFull
+#define XCan_mIsTxFifoFull XCan_IsTxFifoFull
+#endif
+
+#ifndef XCan_mIsHighPriorityBufFull
+#define XCan_mIsHighPriorityBufFull XCan_IsHighPriorityBufFull
+#endif
+
+#ifndef XCan_mIsRxEmpty
+#define XCan_mIsRxEmpty XCan_IsRxEmpty
+#endif
+
+#ifndef XCan_mIsAcceptFilterBusy
+#define XCan_mIsAcceptFilterBusy XCan_IsAcceptFilterBusy
+#endif
+
+#ifndef XCan_mCreateIdValue
+#define XCan_mCreateIdValue XCan_CreateIdValue
+#endif
+
+#ifndef XCan_mCreateDlcValue
+#define XCan_mCreateDlcValue XCan_CreateDlcValue
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDmaCentral
+ * 
+ *********************************************************************/
+#ifndef XDmaCentral_mWriteReg
+#define XDmaCentral_mWriteReg XDmaCentral_WriteReg
+#endif
+
+#ifndef XDmaCentral_mReadReg
+#define XDmaCentral_mReadReg XDmaCentral_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDsAdc
+ * 
+ *********************************************************************/
+#ifndef XDsAdc_mWriteReg
+#define XDsAdc_mWriteReg XDsAdc_WriteReg
+#endif
+
+#ifndef XDsAdc_mReadReg
+#define XDsAdc_mReadReg XDsAdc_ReadReg
+#endif
+
+#ifndef XDsAdc_mIsEmpty
+#define XDsAdc_mIsEmpty XDsAdc_IsEmpty
+#endif
+
+#ifndef XDsAdc_mSetFstmReg
+#define XDsAdc_mSetFstmReg XDsAdc_SetFstmReg
+#endif
+
+#ifndef XDsAdc_mGetFstmReg
+#define XDsAdc_mGetFstmReg XDsAdc_GetFstmReg
+#endif
+
+#ifndef XDsAdc_mEnableConversion
+#define XDsAdc_mEnableConversion XDsAdc_EnableConversion
+#endif
+
+#ifndef XDsAdc_mDisableConversion
+#define XDsAdc_mDisableConversion XDsAdc_DisableConversion
+#endif
+
+#ifndef XDsAdc_mGetFifoOccyReg
+#define XDsAdc_mGetFifoOccyReg XDsAdc_GetFifoOccyReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDsDac
+ * 
+ *********************************************************************/
+#ifndef XDsDac_mWriteReg
+#define XDsDac_mWriteReg XDsDac_WriteReg
+#endif
+
+#ifndef XDsDac_mReadReg
+#define XDsDac_mReadReg XDsDac_ReadReg
+#endif
+
+#ifndef XDsDac_mIsEmpty
+#define XDsDac_mIsEmpty XDsDac_IsEmpty
+#endif
+
+#ifndef XDsDac_mFifoIsFull
+#define XDsDac_mFifoIsFull XDsDac_FifoIsFull
+#endif
+
+#ifndef XDsDac_mGetVacancy
+#define XDsDac_mGetVacancy XDsDac_GetVacancy
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XEmacLite
+ * 
+ *********************************************************************/
+#ifndef XEmacLite_mReadReg
+#define XEmacLite_mReadReg XEmacLite_ReadReg
+#endif
+
+#ifndef XEmacLite_mWriteReg
+#define XEmacLite_mWriteReg XEmacLite_WriteReg
+#endif
+
+#ifndef XEmacLite_mGetTxStatus
+#define XEmacLite_mGetTxStatus XEmacLite_GetTxStatus
+#endif
+
+#ifndef XEmacLite_mSetTxStatus
+#define XEmacLite_mSetTxStatus XEmacLite_SetTxStatus
+#endif
+
+#ifndef XEmacLite_mGetRxStatus
+#define XEmacLite_mGetRxStatus XEmacLite_GetRxStatus
+#endif
+
+#ifndef XEmacLite_mSetRxStatus
+#define XEmacLite_mSetRxStatus XEmacLite_SetRxStatus
+#endif
+
+#ifndef XEmacLite_mIsTxDone
+#define XEmacLite_mIsTxDone XEmacLite_IsTxDone
+#endif
+
+#ifndef XEmacLite_mIsRxEmpty
+#define XEmacLite_mIsRxEmpty XEmacLite_IsRxEmpty
+#endif
+
+#ifndef XEmacLite_mNextTransmitAddr
+#define XEmacLite_mNextTransmitAddr XEmacLite_NextTransmitAddr
+#endif
+
+#ifndef XEmacLite_mNextReceiveAddr
+#define XEmacLite_mNextReceiveAddr XEmacLite_NextReceiveAddr
+#endif
+
+#ifndef XEmacLite_mIsMdioConfigured
+#define XEmacLite_mIsMdioConfigured XEmacLite_IsMdioConfigured
+#endif
+
+#ifndef XEmacLite_mIsLoopbackConfigured
+#define XEmacLite_mIsLoopbackConfigured XEmacLite_IsLoopbackConfigured
+#endif
+
+#ifndef XEmacLite_mGetReceiveDataLength
+#define XEmacLite_mGetReceiveDataLength XEmacLite_GetReceiveDataLength
+#endif
+
+#ifndef XEmacLite_mGetTxActive
+#define XEmacLite_mGetTxActive XEmacLite_GetTxActive
+#endif
+
+#ifndef XEmacLite_mSetTxActive
+#define XEmacLite_mSetTxActive XEmacLite_SetTxActive
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XGpio
+ * 
+ *********************************************************************/
+#ifndef XGpio_mWriteReg
+#define XGpio_mWriteReg XGpio_WriteReg
+#endif
+
+#ifndef XGpio_mReadReg
+#define XGpio_mReadReg XGpio_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XHwIcap
+ * 
+ *********************************************************************/
+#ifndef XHwIcap_mFifoWrite
+#define XHwIcap_mFifoWrite XHwIcap_FifoWrite
+#endif
+
+#ifndef XHwIcap_mFifoRead
+#define XHwIcap_mFifoRead XHwIcap_FifoRead
+#endif
+
+#ifndef XHwIcap_mSetSizeReg
+#define XHwIcap_mSetSizeReg XHwIcap_SetSizeReg
+#endif
+
+#ifndef XHwIcap_mGetControlReg
+#define XHwIcap_mGetControlReg XHwIcap_GetControlReg
+#endif
+
+#ifndef XHwIcap_mStartConfig
+#define XHwIcap_mStartConfig XHwIcap_StartConfig
+#endif
+
+#ifndef XHwIcap_mStartReadBack
+#define XHwIcap_mStartReadBack XHwIcap_StartReadBack
+#endif
+
+#ifndef XHwIcap_mGetStatusReg
+#define XHwIcap_mGetStatusReg XHwIcap_GetStatusReg
+#endif
+
+#ifndef XHwIcap_mIsTransferDone
+#define XHwIcap_mIsTransferDone XHwIcap_IsTransferDone
+#endif
+
+#ifndef XHwIcap_mIsDeviceBusy
+#define XHwIcap_mIsDeviceBusy XHwIcap_IsDeviceBusy
+#endif
+
+#ifndef XHwIcap_mIntrGlobalEnable
+#define XHwIcap_mIntrGlobalEnable XHwIcap_IntrGlobalEnable
+#endif
+
+#ifndef XHwIcap_mIntrGlobalDisable
+#define XHwIcap_mIntrGlobalDisable XHwIcap_IntrGlobalDisable
+#endif
+
+#ifndef XHwIcap_mIntrGetStatus
+#define XHwIcap_mIntrGetStatus XHwIcap_IntrGetStatus
+#endif
+
+#ifndef XHwIcap_mIntrDisable
+#define XHwIcap_mIntrDisable XHwIcap_IntrDisable
+#endif
+
+#ifndef XHwIcap_mIntrEnable
+#define XHwIcap_mIntrEnable XHwIcap_IntrEnable
+#endif
+
+#ifndef XHwIcap_mIntrGetEnabled
+#define XHwIcap_mIntrGetEnabled XHwIcap_IntrGetEnabled
+#endif
+
+#ifndef XHwIcap_mIntrClear
+#define XHwIcap_mIntrClear XHwIcap_IntrClear
+#endif
+
+#ifndef XHwIcap_mGetWrFifoVacancy
+#define XHwIcap_mGetWrFifoVacancy XHwIcap_GetWrFifoVacancy
+#endif
+
+#ifndef XHwIcap_mGetRdFifoOccupancy
+#define XHwIcap_mGetRdFifoOccupancy XHwIcap_GetRdFifoOccupancy
+#endif
+
+#ifndef XHwIcap_mSliceX2Col
+#define XHwIcap_mSliceX2Col XHwIcap_SliceX2Col
+#endif
+
+#ifndef XHwIcap_mSliceY2Row
+#define XHwIcap_mSliceY2Row XHwIcap_SliceY2Row
+#endif
+
+#ifndef XHwIcap_mSliceXY2Slice
+#define XHwIcap_mSliceXY2Slice XHwIcap_SliceXY2Slice
+#endif
+
+#ifndef XHwIcap_mReadReg
+#define XHwIcap_mReadReg XHwIcap_ReadReg
+#endif
+
+#ifndef XHwIcap_mWriteReg
+#define XHwIcap_mWriteReg XHwIcap_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XIic
+ * 
+ *********************************************************************/
+#ifndef XIic_mReadReg
+#define XIic_mReadReg XIic_ReadReg
+#endif
+
+#ifndef XIic_mWriteReg
+#define XIic_mWriteReg XIic_WriteReg
+#endif
+
+#ifndef XIic_mEnterCriticalRegion
+#define XIic_mEnterCriticalRegion XIic_IntrGlobalDisable
+#endif
+
+#ifndef XIic_mExitCriticalRegion
+#define XIic_mExitCriticalRegion XIic_IntrGlobalEnable
+#endif
+
+#ifndef XIIC_GINTR_DISABLE
+#define XIIC_GINTR_DISABLE XIic_IntrGlobalDisable
+#endif
+
+#ifndef XIIC_GINTR_ENABLE
+#define XIIC_GINTR_ENABLE XIic_IntrGlobalEnable
+#endif
+
+#ifndef XIIC_IS_GINTR_ENABLED
+#define XIIC_IS_GINTR_ENABLED XIic_IsIntrGlobalEnabled
+#endif
+
+#ifndef XIIC_WRITE_IISR
+#define XIIC_WRITE_IISR XIic_WriteIisr
+#endif
+
+#ifndef XIIC_READ_IISR
+#define XIIC_READ_IISR XIic_ReadIisr
+#endif
+
+#ifndef XIIC_WRITE_IIER
+#define XIIC_WRITE_IIER XIic_WriteIier
+#endif
+
+#ifndef XIic_mClearIisr
+#define XIic_mClearIisr XIic_ClearIisr
+#endif
+
+#ifndef XIic_mSend7BitAddress
+#define XIic_mSend7BitAddress XIic_Send7BitAddress
+#endif
+
+#ifndef XIic_mDynSend7BitAddress
+#define XIic_mDynSend7BitAddress XIic_DynSend7BitAddress
+#endif
+
+#ifndef XIic_mDynSendStartStopAddress
+#define XIic_mDynSendStartStopAddress XIic_DynSendStartStopAddress
+#endif
+
+#ifndef XIic_mDynSendStop
+#define XIic_mDynSendStop XIic_DynSendStop
+#endif
+
+#ifndef XIic_mSend10BitAddrByte1
+#define XIic_mSend10BitAddrByte1 XIic_Send10BitAddrByte1
+#endif
+
+#ifndef XIic_mSend10BitAddrByte2
+#define XIic_mSend10BitAddrByte2 XIic_Send10BitAddrByte2
+#endif
+
+#ifndef XIic_mSend7BitAddr
+#define XIic_mSend7BitAddr XIic_Send7BitAddr
+#endif
+
+#ifndef XIic_mDisableIntr
+#define XIic_mDisableIntr XIic_DisableIntr
+#endif
+
+#ifndef XIic_mEnableIntr
+#define XIic_mEnableIntr XIic_EnableIntr
+#endif
+
+#ifndef XIic_mClearIntr
+#define XIic_mClearIntr XIic_ClearIntr
+#endif
+
+#ifndef XIic_mClearEnableIntr
+#define XIic_mClearEnableIntr XIic_ClearEnableIntr
+#endif
+
+#ifndef XIic_mFlushRxFifo
+#define XIic_mFlushRxFifo XIic_FlushRxFifo
+#endif
+
+#ifndef XIic_mFlushTxFifo
+#define XIic_mFlushTxFifo XIic_FlushTxFifo
+#endif
+
+#ifndef XIic_mReadRecvByte
+#define XIic_mReadRecvByte XIic_ReadRecvByte
+#endif
+
+#ifndef XIic_mWriteSendByte
+#define XIic_mWriteSendByte XIic_WriteSendByte
+#endif
+
+#ifndef XIic_mSetControlRegister
+#define XIic_mSetControlRegister XIic_SetControlRegister
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XIntc
+ * 
+ *********************************************************************/
+#ifndef XIntc_mMasterEnable
+#define XIntc_mMasterEnable XIntc_MasterEnable
+#endif
+
+#ifndef XIntc_mMasterDisable
+#define XIntc_mMasterDisable XIntc_MasterDisable
+#endif
+
+#ifndef XIntc_mEnableIntr
+#define XIntc_mEnableIntr XIntc_EnableIntr
+#endif
+
+#ifndef XIntc_mDisableIntr
+#define XIntc_mDisableIntr XIntc_DisableIntr
+#endif
+
+#ifndef XIntc_mAckIntr
+#define XIntc_mAckIntr XIntc_AckIntr
+#endif
+
+#ifndef XIntc_mGetIntrStatus
+#define XIntc_mGetIntrStatus XIntc_GetIntrStatus
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XLlDma
+ * 
+ *********************************************************************/
+#ifndef XLlDma_mBdRead
+#define XLlDma_mBdRead XLlDma_BdRead
+#endif
+
+#ifndef XLlDma_mBdWrite
+#define XLlDma_mBdWrite XLlDma_BdWrite
+#endif
+
+#ifndef XLlDma_mWriteReg
+#define XLlDma_mWriteReg XLlDma_WriteReg
+#endif
+
+#ifndef XLlDma_mReadReg
+#define XLlDma_mReadReg XLlDma_ReadReg
+#endif
+
+#ifndef XLlDma_mBdClear
+#define XLlDma_mBdClear XLlDma_BdClear
+#endif
+
+#ifndef XLlDma_mBdSetStsCtrl
+#define XLlDma_mBdSetStsCtrl XLlDma_BdSetStsCtrl
+#endif
+
+#ifndef XLlDma_mBdGetStsCtrl
+#define XLlDma_mBdGetStsCtrl XLlDma_BdGetStsCtrl
+#endif
+
+#ifndef XLlDma_mBdSetLength
+#define XLlDma_mBdSetLength XLlDma_BdSetLength
+#endif
+
+#ifndef XLlDma_mBdGetLength
+#define XLlDma_mBdGetLength XLlDma_BdGetLength
+#endif
+
+#ifndef XLlDma_mBdSetId
+#define XLlDma_mBdSetId XLlDma_BdSetId
+#endif
+
+#ifndef XLlDma_mBdGetId
+#define XLlDma_mBdGetId XLlDma_BdGetId
+#endif
+
+#ifndef XLlDma_mBdSetBufAddr
+#define XLlDma_mBdSetBufAddr XLlDma_BdSetBufAddr
+#endif
+
+#ifndef XLlDma_mBdGetBufAddr
+#define XLlDma_mBdGetBufAddr XLlDma_BdGetBufAddr
+#endif
+
+#ifndef XLlDma_mBdGetLength
+#define XLlDma_mBdGetLength XLlDma_BdGetLength
+#endif
+
+#ifndef XLlDma_mGetTxRing
+#define XLlDma_mGetTxRing XLlDma_GetTxRing
+#endif
+
+#ifndef XLlDma_mGetRxRing
+#define XLlDma_mGetRxRing XLlDma_GetRxRing
+#endif
+
+#ifndef XLlDma_mGetCr
+#define XLlDma_mGetCr XLlDma_GetCr
+#endif
+
+#ifndef XLlDma_mSetCr
+#define XLlDma_mSetCr XLlDma_SetCr
+#endif
+
+#ifndef XLlDma_mBdRingCntCalc
+#define XLlDma_mBdRingCntCalc XLlDma_BdRingCntCalc
+#endif
+
+#ifndef XLlDma_mBdRingMemCalc
+#define XLlDma_mBdRingMemCalc XLlDma_BdRingMemCalc
+#endif
+
+#ifndef XLlDma_mBdRingGetCnt
+#define XLlDma_mBdRingGetCnt XLlDma_BdRingGetCnt
+#endif
+
+#ifndef XLlDma_mBdRingGetFreeCnt
+#define XLlDma_mBdRingGetFreeCnt XLlDma_BdRingGetFreeCnt
+#endif
+
+#ifndef XLlDma_mBdRingSnapShotCurrBd
+#define XLlDma_mBdRingSnapShotCurrBd XLlDma_BdRingSnapShotCurrBd
+#endif
+
+#ifndef XLlDma_mBdRingNext
+#define XLlDma_mBdRingNext XLlDma_BdRingNext
+#endif
+
+#ifndef XLlDma_mBdRingPrev
+#define XLlDma_mBdRingPrev XLlDma_BdRingPrev
+#endif
+
+#ifndef XLlDma_mBdRingGetSr
+#define XLlDma_mBdRingGetSr XLlDma_BdRingGetSr
+#endif
+
+#ifndef XLlDma_mBdRingSetSr
+#define XLlDma_mBdRingSetSr XLlDma_BdRingSetSr
+#endif
+
+#ifndef XLlDma_mBdRingGetCr
+#define XLlDma_mBdRingGetCr XLlDma_BdRingGetCr
+#endif
+
+#ifndef XLlDma_mBdRingSetCr
+#define XLlDma_mBdRingSetCr XLlDma_BdRingSetCr
+#endif
+
+#ifndef XLlDma_mBdRingBusy
+#define XLlDma_mBdRingBusy XLlDma_BdRingBusy
+#endif
+
+#ifndef XLlDma_mBdRingIntEnable
+#define XLlDma_mBdRingIntEnable XLlDma_BdRingIntEnable
+#endif
+
+#ifndef XLlDma_mBdRingIntDisable
+#define XLlDma_mBdRingIntDisable XLlDma_BdRingIntDisable
+#endif
+
+#ifndef XLlDma_mBdRingIntGetEnabled
+#define XLlDma_mBdRingIntGetEnabled XLlDma_BdRingIntGetEnabled
+#endif
+
+#ifndef XLlDma_mBdRingGetIrq
+#define XLlDma_mBdRingGetIrq XLlDma_BdRingGetIrq
+#endif
+
+#ifndef XLlDma_mBdRingAckIrq
+#define XLlDma_mBdRingAckIrq XLlDma_BdRingAckIrq
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMbox
+ * 
+ *********************************************************************/
+#ifndef XMbox_mWriteReg
+#define XMbox_mWriteReg XMbox_WriteReg
+#endif
+
+#ifndef XMbox_mReadReg
+#define XMbox_mReadReg XMbox_ReadReg
+#endif
+
+#ifndef XMbox_mWriteMBox
+#define XMbox_mWriteMBox XMbox_WriteMBox
+#endif
+
+#ifndef XMbox_mReadMBox
+#define XMbox_mReadMBox XMbox_ReadMBox
+#endif
+
+#ifndef XMbox_mFSLReadMBox
+#define XMbox_mFSLReadMBox XMbox_FSLReadMBox
+#endif
+
+#ifndef XMbox_mFSLWriteMBox
+#define XMbox_mFSLWriteMBox XMbox_FSLWriteMBox
+#endif
+
+#ifndef XMbox_mFSLIsEmpty
+#define XMbox_mFSLIsEmpty XMbox_FSLIsEmpty
+#endif
+
+#ifndef XMbox_mFSLIsFull
+#define XMbox_mFSLIsFull XMbox_FSLIsFull
+#endif
+
+#ifndef XMbox_mIsEmpty
+#define XMbox_mIsEmpty XMbox_IsEmptyHw
+#endif
+
+#ifndef XMbox_mIsFull
+#define XMbox_mIsFull XMbox_IsFullHw
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMpmc
+ * 
+ *********************************************************************/
+#ifndef XMpmc_mReadReg
+#define XMpmc_mReadReg XMpmc_ReadReg
+#endif
+
+#ifndef XMpmc_mWriteReg
+#define XMpmc_mWriteReg XMpmc_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMutex
+ * 
+ *********************************************************************/
+#ifndef XMutex_mWriteReg
+#define XMutex_mWriteReg XMutex_WriteReg
+#endif
+
+#ifndef XMutex_mReadReg
+#define XMutex_mReadReg XMutex_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XPcie
+ * 
+ *********************************************************************/
+#ifndef XPcie_mReadReg
+#define XPcie_mReadReg XPcie_ReadReg
+#endif
+
+#ifndef XPcie_mWriteReg
+#define XPcie_mWriteReg XPcie_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSpi
+ * 
+ *********************************************************************/
+#ifndef XSpi_mIntrGlobalEnable
+#define XSpi_mIntrGlobalEnable XSpi_IntrGlobalEnable
+#endif
+
+#ifndef XSpi_mIntrGlobalDisable
+#define XSpi_mIntrGlobalDisable XSpi_IntrGlobalDisable
+#endif
+
+#ifndef XSpi_mIsIntrGlobalEnabled
+#define XSpi_mIsIntrGlobalEnabled XSpi_IsIntrGlobalEnabled
+#endif
+
+#ifndef XSpi_mIntrGetStatus
+#define XSpi_mIntrGetStatus XSpi_IntrGetStatus
+#endif
+
+#ifndef XSpi_mIntrClear
+#define XSpi_mIntrClear XSpi_IntrClear
+#endif
+
+#ifndef XSpi_mIntrEnable
+#define XSpi_mIntrEnable XSpi_IntrEnable
+#endif
+
+#ifndef XSpi_mIntrDisable
+#define XSpi_mIntrDisable XSpi_IntrDisable
+#endif
+
+#ifndef XSpi_mIntrGetEnabled
+#define XSpi_mIntrGetEnabled XSpi_IntrGetEnabled
+#endif
+
+#ifndef XSpi_mSetControlReg
+#define XSpi_mSetControlReg XSpi_SetControlReg
+#endif
+
+#ifndef XSpi_mGetControlReg
+#define XSpi_mGetControlReg XSpi_GetControlReg
+#endif
+
+#ifndef XSpi_mGetStatusReg
+#define XSpi_mGetStatusReg XSpi_GetStatusReg
+#endif
+
+#ifndef XSpi_mSetSlaveSelectReg
+#define XSpi_mSetSlaveSelectReg XSpi_SetSlaveSelectReg
+#endif
+
+#ifndef XSpi_mGetSlaveSelectReg
+#define XSpi_mGetSlaveSelectReg XSpi_GetSlaveSelectReg
+#endif
+
+#ifndef XSpi_mEnable
+#define XSpi_mEnable XSpi_Enable
+#endif
+
+#ifndef XSpi_mDisable
+#define XSpi_mDisable XSpi_Disable
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSysAce
+ * 
+ *********************************************************************/
+#ifndef XSysAce_mGetControlReg
+#define XSysAce_mGetControlReg XSysAce_GetControlReg
+#endif
+
+#ifndef XSysAce_mSetControlReg
+#define XSysAce_mSetControlReg XSysAce_SetControlReg
+#endif
+
+#ifndef XSysAce_mOrControlReg
+#define XSysAce_mOrControlReg XSysAce_OrControlReg
+#endif
+
+#ifndef XSysAce_mAndControlReg
+#define XSysAce_mAndControlReg XSysAce_AndControlReg
+#endif
+
+#ifndef XSysAce_mGetErrorReg
+#define XSysAce_mGetErrorReg XSysAce_GetErrorReg
+#endif
+
+#ifndef XSysAce_mGetStatusReg
+#define XSysAce_mGetStatusReg XSysAce_GetStatusReg
+#endif
+
+#ifndef XSysAce_mWaitForLock
+#define XSysAce_mWaitForLock XSysAce_WaitForLock
+#endif
+
+#ifndef XSysAce_mEnableIntr
+#define XSysAce_mEnableIntr XSysAce_EnableIntr
+#endif
+
+#ifndef XSysAce_mDisableIntr
+#define XSysAce_mDisableIntr XSysAce_DisableIntr
+#endif
+
+#ifndef XSysAce_mIsReadyForCmd
+#define XSysAce_mIsReadyForCmd XSysAce_IsReadyForCmd
+#endif
+
+#ifndef XSysAce_mIsMpuLocked
+#define XSysAce_mIsMpuLocked XSysAce_IsMpuLocked
+#endif
+
+#ifndef XSysAce_mIsIntrEnabled
+#define XSysAce_mIsIntrEnabled XSysAce_IsIntrEnabled
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSysMon
+ * 
+ *********************************************************************/
+#ifndef XSysMon_mIsEventSamplingModeSet
+#define XSysMon_mIsEventSamplingModeSet XSysMon_IsEventSamplingModeSet
+#endif
+
+#ifndef XSysMon_mIsDrpBusy
+#define XSysMon_mIsDrpBusy XSysMon_IsDrpBusy
+#endif
+
+#ifndef XSysMon_mIsDrpLocked
+#define XSysMon_mIsDrpLocked XSysMon_IsDrpLocked
+#endif
+
+#ifndef XSysMon_mRawToTemperature
+#define XSysMon_mRawToTemperature XSysMon_RawToTemperature
+#endif
+
+#ifndef XSysMon_mRawToVoltage
+#define XSysMon_mRawToVoltage XSysMon_RawToVoltage
+#endif
+
+#ifndef XSysMon_mTemperatureToRaw
+#define XSysMon_mTemperatureToRaw XSysMon_TemperatureToRaw
+#endif
+
+#ifndef XSysMon_mVoltageToRaw
+#define XSysMon_mVoltageToRaw XSysMon_VoltageToRaw
+#endif
+
+#ifndef XSysMon_mReadReg
+#define XSysMon_mReadReg XSysMon_ReadReg
+#endif
+
+#ifndef XSysMon_mWriteReg
+#define XSysMon_mWriteReg XSysMon_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XTmrCtr
+ * 
+ *********************************************************************/
+#ifndef XTimerCtr_mReadReg
+#define XTimerCtr_mReadReg XTimerCtr_ReadReg
+#endif
+
+#ifndef XTmrCtr_mWriteReg
+#define XTmrCtr_mWriteReg XTmrCtr_WriteReg
+#endif
+
+#ifndef XTmrCtr_mSetControlStatusReg
+#define XTmrCtr_mSetControlStatusReg XTmrCtr_SetControlStatusReg
+#endif
+
+#ifndef XTmrCtr_mGetControlStatusReg
+#define XTmrCtr_mGetControlStatusReg XTmrCtr_GetControlStatusReg
+#endif
+
+#ifndef XTmrCtr_mGetTimerCounterReg
+#define XTmrCtr_mGetTimerCounterReg XTmrCtr_GetTimerCounterReg
+#endif
+
+#ifndef XTmrCtr_mSetLoadReg
+#define XTmrCtr_mSetLoadReg XTmrCtr_SetLoadReg
+#endif
+
+#ifndef XTmrCtr_mGetLoadReg
+#define XTmrCtr_mGetLoadReg XTmrCtr_GetLoadReg
+#endif
+
+#ifndef XTmrCtr_mEnable
+#define XTmrCtr_mEnable XTmrCtr_Enable
+#endif
+
+#ifndef XTmrCtr_mDisable
+#define XTmrCtr_mDisable XTmrCtr_Disable
+#endif
+
+#ifndef XTmrCtr_mEnableIntr
+#define XTmrCtr_mEnableIntr XTmrCtr_EnableIntr
+#endif
+
+#ifndef XTmrCtr_mDisableIntr
+#define XTmrCtr_mDisableIntr XTmrCtr_DisableIntr
+#endif
+
+#ifndef XTmrCtr_mLoadTimerCounterReg
+#define XTmrCtr_mLoadTimerCounterReg XTmrCtr_LoadTimerCounterReg
+#endif
+
+#ifndef XTmrCtr_mHasEventOccurred
+#define XTmrCtr_mHasEventOccurred XTmrCtr_HasEventOccurred
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUartLite
+ * 
+ *********************************************************************/
+#ifndef XUartLite_mUpdateStats
+#define XUartLite_mUpdateStats XUartLite_UpdateStats
+#endif
+
+#ifndef XUartLite_mWriteReg
+#define XUartLite_mWriteReg XUartLite_WriteReg
+#endif
+
+#ifndef XUartLite_mReadReg
+#define XUartLite_mReadReg XUartLite_ReadReg
+#endif
+
+#ifndef XUartLite_mClearStats
+#define XUartLite_mClearStats XUartLite_ClearStats
+#endif
+
+#ifndef XUartLite_mSetControlReg
+#define XUartLite_mSetControlReg XUartLite_SetControlReg
+#endif
+
+#ifndef XUartLite_mGetStatusReg
+#define XUartLite_mGetStatusReg XUartLite_GetStatusReg
+#endif
+
+#ifndef XUartLite_mIsReceiveEmpty
+#define XUartLite_mIsReceiveEmpty XUartLite_IsReceiveEmpty
+#endif
+
+#ifndef XUartLite_mIsTransmitFull
+#define XUartLite_mIsTransmitFull XUartLite_IsTransmitFull
+#endif
+
+#ifndef XUartLite_mIsIntrEnabled
+#define XUartLite_mIsIntrEnabled XUartLite_IsIntrEnabled
+#endif
+
+#ifndef XUartLite_mEnableIntr
+#define XUartLite_mEnableIntr XUartLite_EnableIntr
+#endif
+
+#ifndef XUartLite_mDisableIntr
+#define XUartLite_mDisableIntr XUartLite_DisableIntr
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUartNs550
+ * 
+ *********************************************************************/
+#ifndef XUartNs550_mUpdateStats
+#define XUartNs550_mUpdateStats XUartNs550_UpdateStats
+#endif
+
+#ifndef XUartNs550_mReadReg
+#define XUartNs550_mReadReg XUartNs550_ReadReg
+#endif
+
+#ifndef XUartNs550_mWriteReg
+#define XUartNs550_mWriteReg XUartNs550_WriteReg
+#endif
+
+#ifndef XUartNs550_mClearStats
+#define XUartNs550_mClearStats XUartNs550_ClearStats
+#endif
+
+#ifndef XUartNs550_mGetLineStatusReg
+#define XUartNs550_mGetLineStatusReg XUartNs550_GetLineStatusReg
+#endif
+
+#ifndef XUartNs550_mGetLineControlReg
+#define XUartNs550_mGetLineControlReg XUartNs550_GetLineControlReg
+#endif
+
+#ifndef XUartNs550_mSetLineControlReg
+#define XUartNs550_mSetLineControlReg XUartNs550_SetLineControlReg
+#endif
+
+#ifndef XUartNs550_mEnableIntr
+#define XUartNs550_mEnableIntr XUartNs550_EnableIntr
+#endif
+
+#ifndef XUartNs550_mDisableIntr
+#define XUartNs550_mDisableIntr XUartNs550_DisableIntr
+#endif
+
+#ifndef XUartNs550_mIsReceiveData
+#define XUartNs550_mIsReceiveData XUartNs550_IsReceiveData
+#endif
+
+#ifndef XUartNs550_mIsTransmitEmpty
+#define XUartNs550_mIsTransmitEmpty XUartNs550_IsTransmitEmpty
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUsb
+ * 
+ *********************************************************************/
+#ifndef XUsb_mReadReg
+#define XUsb_mReadReg XUsb_ReadReg
+#endif
+
+#ifndef XUsb_mWriteReg
+#define XUsb_mWriteReg XUsb_WriteReg
+#endif
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_misc_psreset_api.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_misc_psreset_api.c
new file mode 100644
index 000000000..8763931a6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_misc_psreset_api.c
@@ -0,0 +1,531 @@
+/******************************************************************************
+*
+* (c) Copyright 2013  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_misc_reset.c
+*
+* This file contains the implementation of the reset sequence for various
+* zynq ps devices like DDR,OCM,Slcr,Ethernet,Usb.. controllers. The reset
+* sequence provided to the interfaces is based on the provision in  
+* slcr reset functional blcok.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00b kpc   03/07/13 First release 
+* 

+*
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+#include "xil_misc_psreset_api.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for ddr reset.
+* 
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XDdr_ResetHw()
+{
+	u32 RegVal;
+	
+ 	/* Unlock the slcr register access lock */
+	 Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE); 
+	/* Assert and deassert the ddr softreset bit */ 
+     RegVal = 	Xil_In32(XDDRC_CTRL_BASEADDR);
+	 RegVal &= ~XDDRPS_CTRL_RESET_MASK;
+	 Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal);	
+	 RegVal |= XDDRPS_CTRL_RESET_MASK;	 
+	 Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal);		 
+
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for remapping the ocm memory region
+* 
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XOcm_Remap()
+{
+	u32 RegVal;
+	
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Map the ocm region to postbootrom state */	
+	RegVal = Xil_In32(XSLCR_OCM_CFG_ADDR);
+	RegVal = (RegVal & ~XSLCR_OCM_CFG_HIADDR_MASK) | XSLCR_OCM_CFG_RESETVAL;
+	Xil_Out32(XSLCR_OCM_CFG_ADDR, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for SMC reset sequence
+* 
+* @param   BaseAddress of the interface
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSmc_ResetHw(u32 BaseAddress)
+{
+	u32 RegVal;
+	
+	/* Clear the interuupts */
+	RegVal = Xil_In32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET);
+	RegVal = RegVal | XSMC_MEMC_CLR_CONFIG_MASK; 
+	Xil_Out32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET, RegVal);
+	/* Clear the idle counter registers */	
+	Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_0_OFFSET, 0x0);	
+	Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_1_OFFSET, 0x0);	
+	/* Update the ecc registers with reset values */	
+	Xil_Out32(BaseAddress + XSMC_ECC_MEMCFG1_OFFSET, 
+							XSMC_ECC_MEMCFG1_RESET_VAL);	
+	Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD1_OFFSET,
+							XSMC_ECC_MEMCMD1_RESET_VAL);	
+	Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD2_OFFSET, 
+							XSMC_ECC_MEMCMD2_RESET_VAL);	
+
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for updating the slcr mio registers 
+* with reset values
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_MioWriteResetValues()
+{
+	u32 i;
+	
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Update all the MIO registers with reset values */	
+    for (i=0; i<=1;i++);
+	{
+		Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4)), 
+								XSLCR_MIO_PIN_00_RESET_VAL);	
+	}
+	for (; i<=8;i++);
+	{
+		Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4)),
+								XSLCR_MIO_PIN_02_RESET_VAL);	
+	}
+	for (; i<=53 ;i++);
+	{
+		Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4)), 
+								XSLCR_MIO_PIN_00_RESET_VAL);	
+	}	
+	
+
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for updating the slcr pll registers 
+* with reset values
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_PllWriteResetValues()
+{
+
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	
+	/* update the pll control registers with reset values */	
+	Xil_Out32(XSLCR_IO_PLL_CTRL_ADDR, XSLCR_IO_PLL_CTRL_RESET_VAL);
+	Xil_Out32(XSLCR_ARM_PLL_CTRL_ADDR, XSLCR_ARM_PLL_CTRL_RESET_VAL);
+	Xil_Out32(XSLCR_DDR_PLL_CTRL_ADDR, XSLCR_DDR_PLL_CTRL_RESET_VAL);	
+	/* update the pll config registers with reset values */		
+	Xil_Out32(XSLCR_IO_PLL_CFG_ADDR, XSLCR_IO_PLL_CFG_RESET_VAL);
+	Xil_Out32(XSLCR_ARM_PLL_CFG_ADDR, XSLCR_ARM_PLL_CFG_RESET_VAL);
+	Xil_Out32(XSLCR_DDR_PLL_CFG_ADDR, XSLCR_DDR_PLL_CFG_RESET_VAL);	
+	/* update the clock control registers with reset values */			
+	Xil_Out32(XSLCR_ARM_CLK_CTRL_ADDR, XSLCR_ARM_CLK_CTRL_RESET_VAL);	
+	Xil_Out32(XSLCR_DDR_CLK_CTRL_ADDR, XSLCR_DDR_CLK_CTRL_RESET_VAL);		
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for disabling the level shifters
+* 
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_DisableLevelShifters()
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */	
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Disable the level shifters */
+	RegVal = Xil_In32(XSLCR_LVL_SHFTR_EN_ADDR);
+	RegVal = RegVal & ~XSLCR_LVL_SHFTR_EN_MASK; 
+	Xil_Out32(XSLCR_LVL_SHFTR_EN_ADDR, RegVal);
+	
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for OCM software reset from the 
+* slcr 
+* 
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_OcmReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */	
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR);
+	RegVal = RegVal | XSLCR_OCM_RST_CTRL_VAL;
+	Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */	
+	RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR);
+	RegVal = RegVal & ~XSLCR_OCM_RST_CTRL_VAL;
+	Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal);	
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for Ethernet software reset from 
+* the slcr 
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_EmacPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */	
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR);
+	RegVal = RegVal | XSLCR_GEM_RST_CTRL_VAL;
+	Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */	
+	RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR);
+	RegVal = RegVal & ~XSLCR_GEM_RST_CTRL_VAL;
+	Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal);		
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for USB software reset from the 
+* slcr 
+* 
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_UsbPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */	
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR);
+	RegVal = RegVal | XSLCR_USB_RST_CTRL_VAL;
+	Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */	
+	RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR);
+	RegVal = RegVal & ~XSLCR_USB_RST_CTRL_VAL;
+	Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal);	
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for QSPI software reset from the
+* slcr 
+* 
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_QspiPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */	
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR);
+	RegVal = RegVal | XSLCR_QSPI_RST_CTRL_VAL;
+	Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */	
+	RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR);
+	RegVal = RegVal & ~XSLCR_QSPI_RST_CTRL_VAL;
+	Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for SPI software reset from the 
+* slcr 
+* 
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_SpiPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */	
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR);
+	RegVal = RegVal | XSLCR_SPI_RST_CTRL_VAL;
+	Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */	
+	RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR);
+	RegVal = RegVal & ~XSLCR_SPI_RST_CTRL_VAL;
+	Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal);	
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for i2c software reset from the slcr 
+* 
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_I2cPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */	
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR);
+	RegVal = RegVal | XSLCR_I2C_RST_CTRL_VAL;
+	Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */	
+	RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR);
+	RegVal = RegVal & ~XSLCR_I2C_RST_CTRL_VAL;
+	Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal);		
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for UART software reset from the
+* slcr 
+* 
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_UartPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */	
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR);
+	RegVal = RegVal | XSLCR_UART_RST_CTRL_VAL;
+	Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */	
+	RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR);
+	RegVal = RegVal & ~XSLCR_UART_RST_CTRL_VAL;
+	Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal);		
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for CAN software reset from slcr 
+* registers
+* 
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_CanPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */	
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR);
+	RegVal = RegVal | XSLCR_CAN_RST_CTRL_VAL;
+	Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */	
+	RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR);
+	RegVal = RegVal & ~XSLCR_CAN_RST_CTRL_VAL;
+	Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal);		
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for SMC software reset from the slcr
+* 
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_SmcPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */	
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR);
+	RegVal = RegVal | XSLCR_SMC_RST_CTRL_VAL;
+	Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */	
+	RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR);
+	RegVal = RegVal & ~XSLCR_SMC_RST_CTRL_VAL;
+	Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal);	
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for DMA controller software reset
+* from the slcr 
+* 
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_DmaPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */	
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR);
+	RegVal = RegVal | XSLCR_DMAC_RST_CTRL_VAL;
+	Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */	
+	RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR);
+	RegVal = RegVal & ~XSLCR_DMAC_RST_CTRL_VAL;
+	Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for Gpio AMBA software reset from 
+* the slcr
+* 
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_GpioPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */	
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR);
+	RegVal = RegVal | XSLCR_GPIO_RST_CTRL_VAL;
+	Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */	
+	RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR);
+	RegVal = RegVal & ~XSLCR_GPIO_RST_CTRL_VAL;
+	Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal);
+}
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_misc_psreset_api.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_misc_psreset_api.h
new file mode 100644
index 000000000..ed628566c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_misc_psreset_api.h
@@ -0,0 +1,286 @@
+/******************************************************************************
+*
+* (c) Copyright 2013  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_misc_psreset_api.h
+*
+* This file contains the various register defintions and function prototypes for
+* implementing the reset functionality of zynq ps devices
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00b kpc   03/07/13 First release.
+* 

+*
+******************************************************************************/
+
+#ifndef XIL_MISC_RESET_H		/* prevent circular inclusions */
+#define XIL_MISC_RESET_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+#define XDDRC_CTRL_BASEADDR				0xF8006000
+#define XSLCR_BASEADDR					0xF8000000	
+/**< OCM configuration register */		
+#define XSLCR_OCM_CFG_ADDR				(XSLCR_BASEADDR + 0x910) 
+/**< SLCR unlock register */		
+#define XSLCR_UNLOCK_ADDR				(XSLCR_BASEADDR + 0x8) 
+/**< SLCR GEM0 rx clock control register */		
+#define XSLCR_GEM0_RCLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x138)
+/**< SLCR GEM1 rx clock control register */		
+#define XSLCR_GEM1_RCLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x13C)
+/**< SLCR GEM0 clock control register */		
+#define XSLCR_GEM0_CLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x140)
+/**< SLCR GEM1 clock control register */		
+#define XSLCR_GEM1_CLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x144)
+/**< SLCR SMC clock control register */	
+#define XSLCR_SMC_CLK_CTRL_ADDR			(XSLCR_BASEADDR + 0x148)
+/**< SLCR GEM reset control register */	
+#define XSLCR_GEM_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x214)
+/**< SLCR USB0 clock control register */	
+#define XSLCR_USB0_CLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x130)
+/**< SLCR USB1 clock control register */	
+#define XSLCR_USB1_CLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x134)
+/**< SLCR USB1 reset control register */
+#define XSLCR_USB_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x210)
+/**< SLCR SMC reset control register */
+#define XSLCR_SMC_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x234)
+/**< SLCR Level shifter enable register */
+#define XSLCR_LVL_SHFTR_EN_ADDR			(XSLCR_BASEADDR + 0x900)
+/**< SLCR ARM pll control register */
+#define XSLCR_ARM_PLL_CTRL_ADDR			(XSLCR_BASEADDR + 0x100)
+/**< SLCR DDR pll control register */
+#define XSLCR_DDR_PLL_CTRL_ADDR			(XSLCR_BASEADDR + 0x104)
+/**< SLCR IO pll control register */
+#define XSLCR_IO_PLL_CTRL_ADDR			(XSLCR_BASEADDR + 0x108)
+/**< SLCR ARM pll configuration register */
+#define XSLCR_ARM_PLL_CFG_ADDR			(XSLCR_BASEADDR + 0x110)
+/**< SLCR DDR pll configuration register */
+#define XSLCR_DDR_PLL_CFG_ADDR			(XSLCR_BASEADDR + 0x114)
+/**< SLCR IO pll configuration register */
+#define XSLCR_IO_PLL_CFG_ADDR			(XSLCR_BASEADDR + 0x118)
+/**< SLCR ARM clock control register */
+#define XSLCR_ARM_CLK_CTRL_ADDR			(XSLCR_BASEADDR + 0x120)
+/**< SLCR DDR clock control register */
+#define XSLCR_DDR_CLK_CTRL_ADDR			(XSLCR_BASEADDR + 0x124)
+/**< SLCR MIO pin address register */
+#define XSLCR_MIO_PIN_00_ADDR			(XSLCR_BASEADDR + 0x700)
+/**< SLCR DMAC reset control address register */
+#define XSLCR_DMAC_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x20C)
+/**< SLCR USB reset control address register */
+#define XSLCR_USB_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x210)
+/**< SLCR GEM reset control address register */
+#define XSLCR_GEM_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x214)
+/**< SLCR SDIO reset control address register */
+#define XSLCR_SDIO_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x218)
+/**< SLCR SPI reset control address register */
+#define XSLCR_SPI_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x21C)
+/**< SLCR CAN reset control address register */
+#define XSLCR_CAN_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x220)
+/**< SLCR I2C reset control address register */
+#define XSLCR_I2C_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x224)
+/**< SLCR UART reset control address register */
+#define XSLCR_UART_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x228)
+/**< SLCR GPIO reset control address register */
+#define XSLCR_GPIO_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x22C)
+/**< SLCR LQSPI reset control address register */
+#define XSLCR_LQSPI_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x230)
+/**< SLCR SMC reset control address register */
+#define XSLCR_SMC_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x234)
+/**< SLCR OCM reset control address register */
+#define XSLCR_OCM_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x238)
+
+/**< SMC mem controller clear config register */
+#define XSMC_MEMC_CLR_CONFIG_OFFSET			0x0C
+/**< SMC idlecount configuration register */
+#define XSMC_REFRESH_PERIOD_0_OFFSET		0x20
+#define XSMC_REFRESH_PERIOD_1_OFFSET		0x24
+/**< SMC ECC configuration register */
+#define XSMC_ECC_MEMCFG1_OFFSET				0x404
+/**< SMC ECC command 1 register */
+#define XSMC_ECC_MEMCMD1_OFFSET				0x404
+/**< SMC ECC command 2 register */
+#define XSMC_ECC_MEMCMD2_OFFSET				0x404
+
+/**< SLCR unlock code */
+#define XSLCR_UNLOCK_CODE		0x0000DF0D
+
+/**< SMC mem clear configuration mask */
+#define XSMC_MEMC_CLR_CONFIG_MASK 	0x5F
+/**< SMC ECC memconfig 1 reset value */
+#define XSMC_ECC_MEMCFG1_RESET_VAL 	0x43
+/**< SMC ECC memcommand 1 reset value */
+#define XSMC_ECC_MEMCMD1_RESET_VAL 	0x01300080
+/**< SMC ECC memcommand 2 reset value */
+#define XSMC_ECC_MEMCMD2_RESET_VAL 	0x01E00585
+
+/**< DDR controller reset bit mask */
+#define XDDRPS_CTRL_RESET_MASK 		0x1
+/**< SLCR OCM configuration reset value*/
+#define XSLCR_OCM_CFG_RESETVAL		0x8
+/**< SLCR OCM bank selection mask*/
+#define XSLCR_OCM_CFG_HIADDR_MASK	0xF
+/**< SLCR level shifter enable mask*/
+#define XSLCR_LVL_SHFTR_EN_MASK		0xF
+
+/**< SLCR PLL register reset values */
+#define XSLCR_ARM_PLL_CTRL_RESET_VAL	0x0001A008	
+#define XSLCR_DDR_PLL_CTRL_RESET_VAL	0x0001A008
+#define XSLCR_IO_PLL_CTRL_RESET_VAL		0x0001A008
+#define XSLCR_ARM_PLL_CFG_RESET_VAL		0x00177EA0
+#define XSLCR_DDR_PLL_CFG_RESET_VAL		0x00177EA0
+#define XSLCR_IO_PLL_CFG_RESET_VAL		0x00177EA0
+#define XSLCR_ARM_CLK_CTRL_RESET_VAL	0x1F000400
+#define XSLCR_DDR_CLK_CTRL_RESET_VAL	0x18400003
+
+/**< SLCR MIO register default values */
+#define XSLCR_MIO_PIN_00_RESET_VAL		0x00001601
+#define XSLCR_MIO_PIN_02_RESET_VAL		0x00000601
+
+/**< SLCR Reset control registers default values */
+#define XSLCR_DMAC_RST_CTRL_VAL			0x1
+#define XSLCR_GEM_RST_CTRL_VAL			0xF3
+#define XSLCR_USB_RST_CTRL_VAL			0x3			
+#define XSLCR_I2C_RST_CTRL_VAL			0x3
+#define XSLCR_SPI_RST_CTRL_VAL			0xF
+#define XSLCR_UART_RST_CTRL_VAL			0xF
+#define XSLCR_QSPI_RST_CTRL_VAL			0x3
+#define XSLCR_GPIO_RST_CTRL_VAL			0x1
+#define XSLCR_SMC_RST_CTRL_VAL			0x3
+#define XSLCR_OCM_RST_CTRL_VAL			0x1		
+#define XSLCR_SDIO_RST_CTRL_VAL			0x33
+#define XSLCR_CAN_RST_CTRL_VAL			0x3
+/**************************** Type Definitions *******************************/
+
+/* the following data type is used to hold a null terminated version string
+ * consisting of the following format, "X.YYX"
+ */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+/*
+ * Performs reset operation to the ddr interface
+ */
+void XDdr_ResetHw();
+/*
+ * Map the ocm region to post bootrom state
+ */
+void XOcm_Remap();
+/*
+ * Performs the smc interface reset
+ */
+void XSmc_ResetHw(u32 BaseAddress);
+/*
+ * updates the MIO registers with reset values
+ */
+void XSlcr_MioWriteResetValues();
+/*
+ * updates the PLL and clock registers with reset values
+ */
+void XSlcr_PllWriteResetValues();
+/*
+ * Disables the level shifters
+ */
+void XSlcr_DisableLevelShifters();
+/*
+ * provides softreset to the GPIO interface
+ */
+void XSlcr_GpioPsReset(void);
+/*
+ * provides softreset to the DMA interface
+ */
+void XSlcr_DmaPsReset(void);
+/*
+ * provides softreset to the SMC interface
+ */
+void XSlcr_SmcPsReset(void);
+/*
+ * provides softreset to the CAN interface
+ */
+void XSlcr_CanPsReset(void);
+/*
+ * provides softreset to the Uart interface
+ */
+void XSlcr_UartPsReset(void);
+/*
+ * provides softreset to the I2C interface
+ */
+void XSlcr_I2cPsReset(void);
+/*
+ * provides softreset to the SPI interface
+ */
+void XSlcr_SpiPsReset(void);
+/*
+ * provides softreset to the QSPI interface
+ */
+void XSlcr_QspiPsReset(void);
+/*
+ * provides softreset to the USB interface
+ */
+void XSlcr_UsbPsReset(void);
+/*
+ * provides softreset to the GEM interface
+ */
+void XSlcr_EmacPsReset(void);
+/*
+ * provides softreset to the OCM interface
+ */
+void XSlcr_OcmReset(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XIL_MISC_RESET_H */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_mmu.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_mmu.c
new file mode 100644
index 000000000..bd8c343c3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_mmu.c
@@ -0,0 +1,185 @@
+/******************************************************************************
+*
+* (c) Copyright 2012 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_mmu.c
+*
+* This file provides APIs for enabling/disabling MMU and setting the memory
+* attributes for sections, in the MMU translation table.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  01/12/12 Initial version
+* 3.05a asa  03/10/12 Modified the Xil_EnableMMU to invalidate the caches
+*		      before enabling back.
+* 3.05a asa  04/15/12 Modified the Xil_SetTlbAttributes routine so that
+*		      translation table and branch predictor arrays are
+*		      invalidated, D-cache flushed before the attribute
+*		      change is applied. This is done so that the user
+*		      need not call Xil_DisableMMU before calling
+*		      Xil_SetTlbAttributes.
+* 3.10a  srt 04/18/13 Implemented ARM Erratas. Please refer to file
+*		      'xil_errata.h' for errata description
+* 3.11a  asa 09/23/13 Modified Xil_SetTlbAttributes to flush the complete
+*			 D cache after the translation table update. Removed the
+*			 redundant TLB invalidation in the same API at the beginning.
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+#include "xil_mmu.h"
+#include "xil_errata.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Variable Definitions *****************************/
+
+extern u32 MMUTable;
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************
+*
+* Set the memory attributes for a section, in the translation table. Each
+* section covers 1MB of memory.
+*
+* @param	addr is the address for which attributes are to be set.
+* @param	attrib specifies the attributes for that memory region.
+*
+* @return	None.
+*
+* @note		The MMU and D-cache need not be disabled before changing an
+*		translation table attribute.
+*
+******************************************************************************/
+void Xil_SetTlbAttributes(u32 addr, u32 attrib)
+{
+	u32 *ptr;
+	u32 section;
+
+	section = addr / 0x100000;
+	ptr = &MMUTable + section;
+	*ptr = (addr & 0xFFF00000) | attrib;
+
+	Xil_DCacheFlush();
+
+	mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0);
+	/* Invalidate all branch predictors */
+	mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0);
+
+	dsb(); /* ensure completion of the BP and TLB invalidation */
+    isb(); /* synchronize context on this processor */
+}
+
+/*****************************************************************************
+*
+* Invalidate the caches, enable MMU and D Caches for Cortex A9 processor.
+*
+* @param	None.
+* @return	None.
+*
+******************************************************************************/
+void Xil_EnableMMU(void)
+{
+	u32 Reg;
+	Xil_DCacheInvalidate();
+	Xil_ICacheInvalidate();
+
+#ifdef __GNUC__
+	Reg = mfcp(XREG_CP15_SYS_CONTROL);
+#else
+	{ volatile register unsigned int Cp15Reg __asm(XREG_CP15_SYS_CONTROL);
+	  Reg = Cp15Reg; }
+#endif
+	Reg |= 0x05;
+	mtcp(XREG_CP15_SYS_CONTROL, Reg);
+
+	dsb();
+	isb();
+}
+
+/*****************************************************************************
+*
+* Disable MMU for Cortex A9 processors. This function invalidates the TLBs,
+* Branch Predictor Array and flushed the D Caches before disabling
+* the MMU and D cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+******************************************************************************/
+void Xil_DisableMMU(void)
+{
+	u32 Reg;
+
+	mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0);
+	mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0);
+	Xil_DCacheFlush();
+
+#ifdef __GNUC__
+	Reg = mfcp(XREG_CP15_SYS_CONTROL);
+#else
+	{ volatile register unsigned int Cp15Reg __asm(XREG_CP15_SYS_CONTROL);
+	  Reg = Cp15Reg; }
+#endif
+	Reg &= ~0x05;
+#ifdef CONFIG_ARM_ERRATA_794073
+	/* Disable Branch Prediction */
+	Reg &= ~0x800;
+#endif
+	mtcp(XREG_CP15_SYS_CONTROL, Reg);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_mmu.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_mmu.h
new file mode 100644
index 000000000..37dc1806f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_mmu.h
@@ -0,0 +1,87 @@
+/******************************************************************************
+*
+* (c) Copyright 2012 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_mmu.h
+*
+*
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  01/12/12 Initial version
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef XIL_MMU_H
+#define XIL_MMU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/***************************** Include Files *********************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xil_SetTlbAttributes(u32 addr, u32 attrib);
+void Xil_EnableMMU(void);
+void Xil_DisableMMU(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_MMU_H */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_printf.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_printf.c
new file mode 100644
index 000000000..7660a8b4a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_printf.c
@@ -0,0 +1,281 @@
+/*---------------------------------------------------*/
+/* Modified from :                                   */
+/* Public Domain version of printf                   */
+/* Rud Merriam, Compsult, Inc. Houston, Tx.          */
+/* For Embedded Systems Programming, 1991            */
+/*                                                   */
+/*---------------------------------------------------*/
+#include "xil_printf.h"
+#include 
+#include 
+#include 
+
+
+typedef struct params_s {
+    int len;
+    int num1;
+    int num2;
+    char pad_character;
+    int do_padding;
+    int left_flag;
+} params_t;
+
+
+/*---------------------------------------------------*/
+/* The purpose of this routine is to output data the */
+/* same as the standard printf function without the  */
+/* overhead most run-time libraries involve. Usually */
+/* the printf brings in many kilobytes of code and   */
+/* that is unacceptable in most embedded systems.    */
+/*---------------------------------------------------*/
+
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine puts pad characters into the output  */
+/* buffer.                                           */
+/*                                                   */
+void padding( const int l_flag, params_t *par)
+{
+    int i;
+
+    if (par->do_padding && l_flag && (par->len < par->num1))
+        for (i=par->len; inum1; i++) {
+#ifdef STDOUT_BASEADDRESS
+            outbyte( par->pad_character);
+#endif
+    }
+}
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine moves a string to the output buffer  */
+/* as directed by the padding and positioning flags. */
+/*                                                   */
+void outs( charptr lp, params_t *par)
+{
+    /* pad on left if needed                         */
+    par->len = strlen( lp);
+    padding( !(par->left_flag), par);
+
+    /* Move string to the buffer                     */
+    while (*lp && (par->num2)--) {
+#ifdef STDOUT_BASEADDRESS
+        outbyte( *lp++);
+#endif
+}
+
+    /* Pad on right if needed                        */
+    /* CR 439175 - elided next stmt. Seemed bogus.   */
+    /* par->len = strlen( lp);                       */
+    padding( par->left_flag, par);
+}
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine moves a number to the output buffer  */
+/* as directed by the padding and positioning flags. */
+/*                                                   */
+
+void outnum( const long n, const long base, params_t *par)
+{
+    charptr cp;
+    int negative;
+    char outbuf[32];
+    const char digits[] = "0123456789ABCDEF";
+    unsigned long num;
+
+    /* Check if number is negative                   */
+    if (base == 10 && n < 0L) {
+        negative = 1;
+        num = -(n);
+    }
+    else{
+        num = (n);
+        negative = 0;
+    }
+
+    /* Build number (backwards) in outbuf            */
+    cp = outbuf;
+    do {
+        *cp++ = digits[(int)(num % base)];
+    } while ((num /= base) > 0);
+    if (negative)
+        *cp++ = '-';
+    *cp-- = 0;
+
+    /* Move the converted number to the buffer and   */
+    /* add in the padding where needed.              */
+    par->len = strlen(outbuf);
+    padding( !(par->left_flag), par);
+    while (cp >= outbuf) {
+#ifdef STDOUT_BASEADDRESS
+        outbyte( *cp--);
+#endif
+}
+    padding( par->left_flag, par);
+}
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine gets a number from the format        */
+/* string.                                           */
+/*                                                   */
+int getnum( charptr* linep)
+{
+    int n;
+    charptr cp;
+
+    n = 0;
+    cp = *linep;
+    while (isdigit(((int)*cp)))
+        n = n*10 + ((*cp++) - '0');
+    *linep = cp;
+    return(n);
+}
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine operates just like a printf/sprintf  */
+/* routine. It outputs a set of data under the       */
+/* control of a formatting string. Not all of the    */
+/* standard C format control are supported. The ones */
+/* provided are primarily those needed for embedded  */
+/* systems work. Primarily the floaing point         */
+/* routines are omitted. Other formats could be      */
+/* added easily by following the examples shown for  */
+/* the supported formats.                            */
+/*                                                   */
+
+/* void esp_printf( const func_ptr f_ptr,
+   const charptr ctrl1, ...) */
+void xil_printf( const char *ctrl1, ...)
+{
+
+    int long_flag;
+    int dot_flag;
+
+    params_t par;
+
+    char ch;
+    va_list argp;
+    char *ctrl = (char *)ctrl1;
+
+    va_start( argp, ctrl1);
+
+    for ( ; *ctrl; ctrl++) {
+
+        /* move format string chars to buffer until a  */
+        /* format control is found.                    */
+        if (*ctrl != '%') {
+#ifdef STDOUT_BASEADDRESS
+            outbyte(*ctrl);
+#endif
+            continue;
+        }
+
+        /* initialize all the flags for this format.   */
+        dot_flag   = long_flag = par.left_flag = par.do_padding = 0;
+        par.pad_character = ' ';
+        par.num2=32767;
+
+ try_next:
+        ch = *(++ctrl);
+
+        if (isdigit((int)ch)) {
+            if (dot_flag)
+                par.num2 = getnum(&ctrl);
+            else {
+                if (ch == '0')
+                    par.pad_character = '0';
+
+                par.num1 = getnum(&ctrl);
+                par.do_padding = 1;
+            }
+            ctrl--;
+            goto try_next;
+        }
+
+        switch (tolower((int)ch)) {
+            case '%':
+#ifdef STDOUT_BASEADDRESS
+                outbyte( '%');
+#endif
+                continue;
+
+            case '-':
+                par.left_flag = 1;
+                break;
+
+            case '.':
+                dot_flag = 1;
+                break;
+
+            case 'l':
+                long_flag = 1;
+                break;
+
+            case 'd':
+                if (long_flag || ch == 'D') {
+                    outnum( va_arg(argp, long), 10L, &par);
+                    continue;
+                }
+                else {
+                    outnum( va_arg(argp, int), 10L, &par);
+                    continue;
+                }
+            case 'x':
+                outnum((long)va_arg(argp, int), 16L, &par);
+                continue;
+
+            case 's':
+                outs( va_arg( argp, char *), &par);
+                continue;
+
+            case 'c':
+#ifdef STDOUT_BASEADDRESS
+                outbyte( va_arg( argp, int));
+#endif
+                continue;
+
+            case '\\':
+                switch (*ctrl) {
+                    case 'a':
+#ifdef STDOUT_BASEADDRESS
+                        outbyte( 0x07);
+#endif
+                        break;
+                    case 'h':
+#ifdef STDOUT_BASEADDRESS
+                        outbyte( 0x08);
+#endif
+                        break;
+                    case 'r':
+#ifdef STDOUT_BASEADDRESS
+                        outbyte( 0x0D);
+#endif
+                        break;
+                    case 'n':
+#ifdef STDOUT_BASEADDRESS
+                        outbyte( 0x0D);
+                        outbyte( 0x0A);
+#endif
+                        break;
+                    default:
+#ifdef STDOUT_BASEADDRESS
+                        outbyte( *ctrl);
+#endif
+                        break;
+                }
+                ctrl++;
+                break;
+
+            default:
+                continue;
+        }
+        goto try_next;
+    }
+    va_end( argp);
+}
+
+/*---------------------------------------------------*/
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_printf.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_printf.h
new file mode 100644
index 000000000..89a051c23
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_printf.h
@@ -0,0 +1,47 @@
+ #ifndef XIL_PRINTF_H
+ #define XIL_PRINTF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include 
+#include 
+#include 
+#include "xparameters.h"
+#include "xil_types.h"
+
+/*----------------------------------------------------*/
+/* Use the following parameter passing structure to   */
+/* make xil_printf re-entrant.                        */
+/*----------------------------------------------------*/
+
+struct params_s;
+
+
+/*---------------------------------------------------*/
+/* The purpose of this routine is to output data the */
+/* same as the standard printf function without the  */
+/* overhead most run-time libraries involve. Usually */
+/* the printf brings in many kilobytes of code and   */
+/* that is unacceptable in most embedded systems.    */
+/*---------------------------------------------------*/
+
+typedef char* charptr;
+typedef int (*func_ptr)(int c);
+
+/*                                                   */
+void padding( const int l_flag, struct params_s *par);
+void outs( charptr lp, struct params_s *par);
+void outnum( const long n, const long base, struct params_s *par);
+int getnum( charptr* linep);
+void xil_printf( const char *ctrl1, ...);
+void print( const char *ptr);
+void outbyte (char);
+char inbyte(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_testcache.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_testcache.c
new file mode 100644
index 000000000..03fa33989
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_testcache.c
@@ -0,0 +1,225 @@
+/******************************************************************************
+*
+* (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testcache.c
+*
+* Contains utility functions to test cache.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/28/09 Initial release
+* 4.1   asa  05/09/14 Ensured that the address uses for cache test is aligned
+*				      cache line.
+* 

+*
+* @note
+*
+* This file contain functions that all operate on HAL.
+*
+******************************************************************************/
+#include "xil_cache.h"
+#include "xil_testcache.h"
+
+extern void xil_printf(const char *ctrl1, ...);
+
+#define DATA_LENGTH 128
+
+static u32 Data[DATA_LENGTH] __attribute__ ((aligned(32)));
+
+/**
+* Perform DCache range related API test such as Xil_DCacheFlushRange and
+* Xil_DCacheInvalidateRange. This test function writes a constant value
+* to the Data array, flushes the range, writes a new value, then invalidates
+* the corresponding range.
+*
+* @return
+*
+*     - 0 is returned for a pass
+*     - -1 is returned for a failure
+*/
+int Xil_TestDCacheRange(void)
+{
+	int Index;
+	int Status;
+
+	u32 Value;
+
+	xil_printf("-- Cache Range Test --\n\r");
+
+
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0xA0A00505;
+
+	xil_printf("    initialize Data done:\r\n");
+
+	Xil_DCacheFlushRange((u32)Data, DATA_LENGTH * sizeof(u32));
+
+	xil_printf("    flush range done\r\n");
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = Index + 3;
+
+	Xil_DCacheInvalidateRange((u32)Data, DATA_LENGTH * sizeof(u32));
+
+	xil_printf("    invalidate dcache range done\r\n");
+
+	Status = 0;
+
+	for (Index = 0; Index < DATA_LENGTH; Index++) {
+		Value = Data[Index];
+		if (Value != 0xA0A00505) {
+			Status = -1;
+			xil_printf("Data[%d] = %x\r\n", Index, Value);
+			break;
+		}
+	}
+
+	if (!Status) {
+		xil_printf("    Invalidate worked\r\n");
+	}
+	else {
+		xil_printf("Error: Invalidate dcache range not working\r\n");
+	}
+
+	xil_printf("-- Cache Range Test Complete --\r\n");
+
+	return Status;
+
+}
+
+/**
+* Perform DCache all related API test such as Xil_DCacheFlush and
+* Xil_DCacheInvalidate. This test function writes a constant value
+* to the Data array, flushes the DCache, writes a new value, then invalidates
+* the DCache.
+*
+* @return
+*     - 0 is returned for a pass
+*     - -1 is returned for a failure
+*/
+int Xil_TestDCacheAll(void)
+{
+	int Index;
+	int Status;
+	u32 Value;
+
+	xil_printf("-- Cache All Test --\n\r");
+
+
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0x50500A0A;
+
+	xil_printf("    initialize Data done:\r\n");
+
+	Xil_DCacheFlush();
+
+	xil_printf("    flush all done\r\n");
+
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = Index + 3;
+
+	Xil_DCacheInvalidate();
+
+	xil_printf("    invalidate all done\r\n");
+
+	Status = 0;
+
+	for (Index = 0; Index < DATA_LENGTH; Index++) {
+		Value = Data[Index];
+		if (Value != 0x50500A0A) {
+			Status = -1;
+			xil_printf("Data[%d] = %x\r\n", Index, Value);
+			break;
+		}
+	}
+
+	if (!Status) {
+		xil_printf("    Invalidate all worked\r\n");
+	}
+	else {
+		xil_printf("Error: Invalidate dcache all not working\r\n");
+	}
+
+	xil_printf("-- DCache all Test Complete --\n\r");
+
+	return Status;
+
+}
+
+
+/**
+* Perform Xil_ICacheInvalidateRange() on a few function pointers.
+*
+* @return
+*
+*     - 0 is returned for a pass
+*     The function will hang if it fails.
+*/
+int Xil_TestICacheRange(void)
+{
+
+	Xil_ICacheInvalidateRange((u32)Xil_TestICacheRange, 1024);
+	Xil_ICacheInvalidateRange((u32)Xil_TestDCacheRange, 1024);
+	Xil_ICacheInvalidateRange((u32)Xil_TestDCacheAll, 1024);
+
+	xil_printf("-- Invalidate icache range done --\r\n");
+
+	return 0;
+}
+
+/**
+* Perform Xil_ICacheInvalidate().
+*
+* @return
+*
+*     - 0 is returned for a pass
+*     The function will hang if it fails.
+*/
+int Xil_TestICacheAll(void)
+{
+	Xil_ICacheInvalidate();
+	xil_printf("-- Invalidate icache all done --\r\n");
+	return 0;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_testcache.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_testcache.h
new file mode 100644
index 000000000..db6d29652
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_testcache.h
@@ -0,0 +1,71 @@
+/******************************************************************************
+*
+*
+* (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testcache.h
+*
+* This file contains utility functions to test cache.
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  07/29/09 First release
+*
+******************************************************************************/
+
+#ifndef XIL_TESTCACHE_H	/* prevent circular inclusions */
+#define XIL_TESTCACHE_H	/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern int Xil_TestDCacheRange(void);
+extern int Xil_TestDCacheAll(void);
+extern int Xil_TestICacheRange(void);
+extern int Xil_TestICacheAll(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_testio.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_testio.c
new file mode 100644
index 000000000..5aa779058
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_testio.c
@@ -0,0 +1,304 @@
+/******************************************************************************
+*
+*
+* (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmemend.c
+*
+* Contains the memory test utility functions.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  08/25/09 First release
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xil_testio.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+/************************** Function Prototypes *****************************/
+
+
+
+/**
+ *
+ * Endian swap a 16-bit word.
+ * @param	Data is the 16-bit word to be swapped.
+ * @return	The endian swapped valud.
+ *
+ */
+static u16 Swap16(u16 Data)
+{
+	return ((Data >> 8) & 0x00FF) | ((Data << 8) & 0xFF00);
+}
+
+/**
+ *
+ * Endian swap a 32-bit word.
+ * @param	Data is the 32-bit word to be swapped.
+ * @return	The endian swapped valud.
+ *
+ */
+static u32 Swap32(u32 Data)
+{
+	u16 Lo16;
+	u16 Hi16;
+
+	u16 Swap16Lo;
+	u16 Swap16Hi;
+
+	Hi16 = (u16)((Data >> 16) & 0x0000FFFF);
+	Lo16 = (u16)(Data & 0x0000FFFF);
+
+	Swap16Lo = Swap16(Lo16);
+	Swap16Hi = Swap16(Hi16);
+
+	return (((u32)(Swap16Lo)) << 16) | ((u32)Swap16Hi);
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a destructive 8-bit wide register IO test where the register is
+* accessed using Xil_Out8 and Xil_In8, and comparing the reading and writing
+* values.
+*
+* @param	Addr is a pointer to the region of memory to be tested.
+* @param	Len is the length of the block.
+* @param	Value is the constant used for writting the memory.
+*
+* @return
+*
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+*****************************************************************************/
+
+int Xil_TestIO8(u8 *Addr, int Len, u8 Value)
+{
+	u8 ValueIn;
+	int Index;
+
+	for (Index = 0; Index < Len; Index++) {
+		Xil_Out8((u32)Addr, Value);
+
+		ValueIn = Xil_In8((u32)Addr);
+
+		if (Value != ValueIn) {
+			return -1;
+		}
+	}
+
+	return 0;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a destructive 16-bit wide register IO test. Each location is tested
+* by sequentially writing a 16-bit wide register, reading the register, and
+* comparing value. This function tests three kinds of register IO functions,
+* normal register IO, little-endian register IO, and big-endian register IO.
+* When testing little/big-endian IO, the function performs the following
+* sequence, Xil_Out16LE/Xil_Out16BE, Xil_In16, Compare In-Out values,
+* Xil_Out16, Xil_In16LE/Xil_In16BE, Compare In-Out values. Whether to swap the
+* read-in value before comparing is controlled by the 5th argument.
+*
+* @param	Addr is a pointer to the region of memory to be tested.
+* @param	Len is the length of the block.
+* @param	Value is the constant used for writting the memory.
+* @param	Kind is the test kind. Acceptable values are:
+*		XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
+* @param	Swap indicates whether to byte swap the read-in value.
+*
+* @return
+*
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+*****************************************************************************/
+
+int Xil_TestIO16(u16 *Addr, int Len, u16 Value, int Kind, int Swap)
+{
+	u16 ValueIn;
+	int Index;
+
+	for (Index = 0; Index < Len; Index++) {
+		switch (Kind) {
+		case XIL_TESTIO_LE:
+			Xil_Out16LE((u32)Addr, Value);
+			break;
+		case XIL_TESTIO_BE:
+			Xil_Out16BE((u32)Addr, Value);
+			break;
+		default:
+			Xil_Out16((u32)Addr, Value);
+			break;
+		}
+
+		ValueIn = Xil_In16((u32)Addr);
+
+		if (Kind && Swap)
+			ValueIn = Swap16(ValueIn);
+
+		if (Value != ValueIn) {
+			return -1;
+		}
+
+		/* second round */
+		Xil_Out16((u32)Addr, Value);
+
+		switch (Kind) {
+		case XIL_TESTIO_LE:
+			ValueIn = Xil_In16LE((u32)Addr);
+			break;
+		case XIL_TESTIO_BE:
+			ValueIn = Xil_In16BE((u32)Addr);
+			break;
+		default:
+			ValueIn = Xil_In16((u32)Addr);
+			break;
+		}
+
+
+		if (Kind && Swap)
+			ValueIn = Swap16(ValueIn);
+
+		if (Value != ValueIn) {
+			return -1;
+		}
+		Addr++;
+	}
+
+	return 0;
+
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Perform a destructive 32-bit wide register IO test. Each location is tested
+* by sequentially writing a 32-bit wide regsiter, reading the register, and
+* comparing value. This function tests three kinds of register IO functions,
+* normal register IO, little-endian register IO, and big-endian register IO.
+* When testing little/big-endian IO, the function perform the following
+* sequence, Xil_Out32LE/Xil_Out32BE, Xil_In32, Compare,
+* Xil_Out32, Xil_In32LE/Xil_In32BE, Compare. Whether to swap the read-in value
+* before comparing is controlled by the 5th argument.
+*
+* @param	Addr is a pointer to the region of memory to be tested.
+* @param	Len is the length of the block.
+* @param	Value is the constant used for writting the memory.
+* @param	Kind is the test kind. Acceptable values are:
+*		XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
+* @param	Swap indicates whether to byte swap the read-in value.
+*
+* @return
+*
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+*****************************************************************************/
+int Xil_TestIO32(u32 *Addr, int Len, u32 Value, int Kind, int Swap)
+{
+	u32 ValueIn;
+	int Index;
+
+	for (Index = 0; Index < Len; Index++) {
+		switch (Kind) {
+		case XIL_TESTIO_LE:
+			Xil_Out32LE((u32)Addr, Value);
+			break;
+		case XIL_TESTIO_BE:
+			Xil_Out32BE((u32)Addr, Value);
+			break;
+		default:
+			Xil_Out32((u32)Addr, Value);
+			break;
+		}
+
+		ValueIn = Xil_In32((u32)Addr);
+
+		if (Kind && Swap)
+			ValueIn = Swap32(ValueIn);
+
+		if (Value != ValueIn) {
+			return -1;
+		}
+
+		/* second round */
+		Xil_Out32((u32)Addr, Value);
+
+
+		switch (Kind) {
+		case XIL_TESTIO_LE:
+			ValueIn = Xil_In32LE((u32)Addr);
+			break;
+		case XIL_TESTIO_BE:
+			ValueIn = Xil_In32BE((u32)Addr);
+			break;
+		default:
+			ValueIn = Xil_In32((u32)Addr);
+			break;
+		}
+
+		if (Kind && Swap)
+			ValueIn = Swap32(ValueIn);
+
+		if (Value != ValueIn) {
+			return -1;
+		}
+		Addr++;
+	}
+	return 0;
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_testio.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_testio.h
new file mode 100644
index 000000000..33a8286f1
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_testio.h
@@ -0,0 +1,101 @@
+/******************************************************************************
+*
+* (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmemend.h
+*
+* This file contains utility functions to teach endian related memory
+* IO functions.
+*
+* Memory test description
+*
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+*
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00 hbm  08/05/09 First release
+* 

+*
+******************************************************************************/
+
+#ifndef XIL_TESTIO_H	/* prevent circular inclusions */
+#define XIL_TESTIO_H	/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+#define XIL_TESTIO_DEFAULT 	0
+#define XIL_TESTIO_LE		1
+#define XIL_TESTIO_BE		2
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+extern int Xil_TestIO8(u8 *Addr, int Len, u8 Value);
+extern int Xil_TestIO16(u16 *Addr, int Len, u16 Value, int Kind, int Swap);
+extern int Xil_TestIO32(u32 *Addr, int Len, u32 Value, int Kind, int Swap);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_testmem.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_testmem.c
new file mode 100644
index 000000000..27a1a1270
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_testmem.c
@@ -0,0 +1,1004 @@
+/******************************************************************************
+*
+* (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmem.c
+*
+* Contains the memory test utility functions.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  08/25/09 First release
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xil_testmem.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions ****************************/
+/************************** Function Prototypes *****************************/
+
+static u32 RotateLeft(u32 Input, u8 Width);
+
+/* define ROTATE_RIGHT to give access to this functionality */
+/* #define ROTATE_RIGHT */
+#ifdef ROTATE_RIGHT
+static u32 RotateRight(u32 Input, u8 Width);
+#endif /* ROTATE_RIGHT */
+
+
+/*****************************************************************************/
+/**
+*
+* Perform a destructive 32-bit wide memory test.
+*
+* @param    Addr is a pointer to the region of memory to be tested.
+* @param    Words is the length of the block.
+* @param    Pattern is the constant used for the constant pattern test, if 0,
+*           0xDEADBEEF is used.
+* @param    Subtest is the test selected. See xil_testmem.h for possible
+*	    values.
+*
+* @return
+*
+* - 0 is returned for a pass
+* - -1 is returned for a failure
+*
+* @note
+*
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** Width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*****************************************************************************/
+int Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest)
+{
+	u32 I;
+	u32 J;
+	u32 Val;
+	u32 FirtVal;
+	u32 Word;
+
+	Xil_AssertNonvoid(Words != 0);
+	Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
+
+	/*
+	 * variable initialization
+	 */
+	Val = XIL_TESTMEM_INIT_VALUE;
+	FirtVal = XIL_TESTMEM_INIT_VALUE;
+
+	/*
+	 * Select the proper Subtest
+	 */
+	switch (Subtest) {
+
+	case XIL_TESTMEM_ALLMEMTESTS:
+
+		/* this case executes all of the Subtests */
+
+		/* fall through case statement */
+
+	case XIL_TESTMEM_INCREMENT:
+		
+		/*
+		 * Fill the memory with incrementing
+		 * values starting from 'FirtVal'
+		 */
+		for (I = 0L; I < Words; I++) {
+			Addr[I] = Val;
+			Val++;
+		}
+
+		/*
+		 * Restore the reference 'Val' to the
+		 * initial value
+		 */
+		Val = FirtVal;
+
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the incrementing reference
+		 * Val
+		 */
+
+		for (I = 0L; I < Words; I++) {
+			Word = Addr[I];
+
+			if (Word != Val) {
+				return -1;
+			}
+
+			Val++;
+		}
+
+
+		if (Subtest != XIL_TESTMEM_ALLMEMTESTS) {
+			return 0;
+		}
+
+
+		/* end of case 1 */
+
+		/* fall through case statement */
+
+	case XIL_TESTMEM_WALKONES:
+		/*
+		 * set up to cycle through all possible initial
+		 * test Patterns for walking ones test
+		 */
+		
+		for (J = 0L; J < 32; J++) {
+			/*
+			 * Generate an initial value for walking ones test
+			 * to test for bad data bits
+			 */
+			
+			Val = 1 << J;
+
+			/*
+			 * START walking ones test
+			 * Write a one to each data bit indifferent locations
+			 */
+
+			for (I = 0L; I < 32; I++) {
+				/* write memory location */
+				Addr[I] = Val;
+				Val = (u32) RotateLeft(Val, 32);
+			}
+
+			/*
+			 * Restore the reference 'val' to the
+			 * initial value
+			 */
+			Val = 1 << J;
+
+			/* Read the values from each location that was
+			 * written */
+			for (I = 0L; I < 32; I++) {
+				/* read memory location */
+				
+				Word = Addr[I];
+
+				if (Word != Val) {
+					return -1;
+				}
+
+				Val = (u32)RotateLeft(Val, 32);
+			}
+
+		}
+
+		if (Subtest != XIL_TESTMEM_ALLMEMTESTS) {
+			return 0;
+		}
+
+		/* end of case 2 */
+		/* fall through case statement */
+
+	case XIL_TESTMEM_WALKZEROS:
+		/*
+		 * set up to cycle through all possible
+		 * initial test Patterns for walking zeros test
+		 */
+
+		for (J = 0L; J < 32; J++) {
+
+			/*
+			 * Generate an initial value for walking ones test
+			 * to test for bad data bits
+			 */
+
+			Val = ~(1 << J);
+
+			/*
+			 * START walking zeros test
+			 * Write a one to each data bit indifferent locations
+			 */
+			
+			for (I = 0L; I < 32; I++) {
+				/* write memory location */
+				Addr[I] = Val;
+				Val = ~((u32)RotateLeft(~Val, 32));
+			}
+
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+
+			Val = ~(1 << J);
+
+			/* Read the values from each location that was
+			 * written */
+			for (I = 0L; I < 32; I++) {
+				/* read memory location */
+				Word = Addr[I];
+				if (Word != Val) {
+					return -1;
+				}
+				Val = ~((u32)RotateLeft(~Val, 32));
+			}
+
+		}
+
+		if (Subtest != XIL_TESTMEM_ALLMEMTESTS) {
+			return 0;
+		}
+
+		/* end of case 3 */
+
+		/* fall through case statement */
+
+	case XIL_TESTMEM_INVERSEADDR:
+		/* Fill the memory with inverse of address */
+		for (I = 0L; I < Words; I++) {
+			/* write memory location */
+			Val = (u32) (~((u32) (&Addr[I])));
+			Addr[I] = Val;
+		}
+
+		/*
+		 * Check every word within the words
+		 * of tested memory
+		 */
+		
+		for (I = 0L; I < Words; I++) {
+			/* Read the location */
+			Word = Addr[I];
+			Val = (u32) (~((u32) (&Addr[I])));
+			
+			if ((Word ^ Val) != 0x00000000) {
+				return -1;
+			}
+		}
+
+		if (Subtest != XIL_TESTMEM_ALLMEMTESTS) {
+			return 0;
+		}
+		/* end of case 4 */
+
+		/* fall through case statement */
+
+	case XIL_TESTMEM_FIXEDPATTERN:
+		/*
+		 * Generate an initial value for
+		 * memory testing
+		 */
+
+		if (Pattern == 0) {
+			Val = 0xDEADBEEF;
+		}
+		else {
+			Val = Pattern;
+		}
+
+		/*
+		 * Fill the memory with fixed Pattern
+		 */
+
+		for (I = 0L; I < Words; I++) {
+			/* write memory location */
+			Addr[I] = Val;
+		}
+
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the fixed Pattern
+		 */
+		
+		for (I = 0L; I < Words; I++) {
+			
+			/* read memory location */
+			
+			Word = Addr[I];
+			if (Word != Val) {
+				return -1;
+			}
+		}
+
+		if (Subtest != XIL_TESTMEM_ALLMEMTESTS) {
+			return 0;
+		}
+		/* end of case 5 */
+
+		/* this break is for the prior fall through case statements */
+
+		break;
+
+	default:
+		return -1;
+
+	}			/* end of switch */
+
+	/* Successfully passed memory test ! */
+
+	return 0;
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a destructive 16-bit wide memory test.
+*
+* @param    Addr is a pointer to the region of memory to be tested.
+* @param    Words is the length of the block.
+* @param    Pattern is the constant used for the constant Pattern test, if 0,
+*           0xDEADBEEF is used.
+* @param    Subtest is the test selected. See xil_testmem.h for possible
+*	    values.
+*
+* @return
+*
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+* @note
+*
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** Width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*****************************************************************************/
+int Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest)
+{
+	u32 I;
+	u32 J;
+	u16 Val;
+	u16 FirtVal;
+	u16 Word;
+
+	Xil_AssertNonvoid(Words != 0);
+	Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
+
+	/*
+	 * variable initialization
+	 */
+	Val = XIL_TESTMEM_INIT_VALUE;
+	FirtVal = XIL_TESTMEM_INIT_VALUE;
+
+	/*
+	 * selectthe proper Subtest(s)
+	 */
+
+	switch (Subtest) {
+
+	case XIL_TESTMEM_ALLMEMTESTS:
+
+		/* this case executes all of the Subtests */
+
+		/* fall through case statement */
+
+	case XIL_TESTMEM_INCREMENT:
+		/*
+		 * Fill the memory with incrementing
+		 * values starting from 'FirtVal'
+		 */
+		for (I = 0L; I < Words; I++) {
+			/* write memory location */
+			Addr[I] = Val;
+			Val++;
+		}
+		/*
+		 * Restore the reference 'Val' to the
+		 * initial value
+		 */
+		Val = FirtVal;
+
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the incrementing reference val
+		 */
+		
+		for (I = 0L; I < Words; I++) {
+			/* read memory location */
+			Word = Addr[I];
+			if (Word != Val) {
+				return -1;
+			}
+			Val++;
+		}
+		if (Subtest != XIL_TESTMEM_ALLMEMTESTS) {
+			return 0;
+		}
+
+		/* end of case 1 */
+		/* fall through case statement */
+
+	case XIL_TESTMEM_WALKONES:
+		/*
+		 * set up to cycle through all possible initial test
+		 * Patterns for walking ones test
+		 */
+		
+		for (J = 0L; J < 16; J++) {
+			/*
+			 * Generate an initial value for walking ones test
+			 * to test for bad data bits
+			 */
+			
+			Val = 1 << J;
+			/*
+			 * START walking ones test
+			 * Write a one to each data bit indifferent locations
+			 */
+
+			for (I = 0L; I < 16; I++) {
+				/* write memory location */
+				Addr[I] = Val;
+				Val = (u16)RotateLeft(Val, 16);
+			}
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+			Val = 1 << J;
+			/* Read the values from each location that was written */
+			for (I = 0L; I < 16; I++) {
+				/* read memory location */
+				Word = Addr[I];
+				if (Word != Val) {
+					return -1;
+				}
+				Val = (u16)RotateLeft(Val, 16);
+			}
+
+		}
+		if (Subtest != XIL_TESTMEM_ALLMEMTESTS) {
+			return 0;
+		}
+		/* end of case 2 */
+		/* fall through case statement */
+
+	case XIL_TESTMEM_WALKZEROS:
+		/*
+		 * set up to cycle through all possible initial
+		 * test Patterns for walking zeros test
+		 */
+
+		for (J = 0L; J < 16; J++) {
+			/*
+			 * Generate an initial value for walking ones
+			 * test to test for bad
+			 * data bits
+			 */
+
+			Val = ~(1 << J);
+			/*
+			 * START walking zeros test
+			 * Write a one to each data bit indifferent locations
+			 */
+			
+			for (I = 0L; I < 16; I++) {
+				/* write memory location */
+				Addr[I] = Val;
+				Val = ~((u16)RotateLeft(~Val, 16));
+			}
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+			Val = ~(1 << J);
+			/* Read the values from each location that was written */
+			for (I = 0L; I < 16; I++) {
+				/* read memory location */
+				Word = Addr[I];
+				if (Word != Val) {
+					return -1;
+				}
+				Val = ~((u16)RotateLeft(~Val, 16));
+			}
+
+		}
+		if (Subtest != XIL_TESTMEM_ALLMEMTESTS) {
+			return 0;
+		}
+		/* end of case 3 */
+		/* fall through case statement */
+
+	case XIL_TESTMEM_INVERSEADDR:
+		/* Fill the memory with inverse of address */
+		for (I = 0L; I < Words; I++) {
+			/* write memory location */
+			Val = (u16) (~((u32) (&Addr[I])));
+			Addr[I] = Val;
+		}
+		/*
+		 * Check every word within the words
+		 * of tested memory
+		 */
+
+		for (I = 0L; I < Words; I++) {
+			/* read memory location */
+			Word = Addr[I];
+			Val = (u16) (~((u32) (&Addr[I])));
+			if ((Word ^ Val) != 0x0000) {
+				return -1;
+			}
+		}
+		if (Subtest != XIL_TESTMEM_ALLMEMTESTS) {
+			return 0;
+		}
+		/* end of case 4 */
+		/* fall through case statement */
+
+	case XIL_TESTMEM_FIXEDPATTERN:
+		/*
+		 * Generate an initial value for
+		 * memory testing
+		 */
+		if (Pattern == 0) {
+			Val = 0xDEAD;
+		}
+		else {
+			Val = Pattern;
+		}
+
+		/*
+		 * Fill the memory with fixed pattern
+		 */
+
+		for (I = 0L; I < Words; I++) {
+			/* write memory location */
+			Addr[I] = Val;
+		}
+
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the fixed pattern
+		 */
+		
+		for (I = 0L; I < Words; I++) {
+			/* read memory location */
+			Word = Addr[I];
+			if (Word != Val) {
+				return -1;
+			}
+		}
+		if (Subtest != XIL_TESTMEM_ALLMEMTESTS) {
+			return 0;
+		}
+		/* end of case 5 */
+		/* this break is for the prior fall through case statements */
+
+		break;
+
+	default:
+		return -1;
+
+	}			/* end of switch */
+
+	/* Successfully passed memory test ! */
+
+	return 0;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Perform a destructive 8-bit wide memory test.
+*
+* @param    Addr is a pointer to the region of memory to be tested.
+* @param    Words is the length of the block.
+* @param    Pattern is the constant used for the constant pattern test, if 0,
+*           0xDEADBEEF is used.
+* @param    Subtest is the test selected. See xil_testmem.h for possible
+*	    values.
+*
+* @return
+*
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+* @note
+*
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** Width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*****************************************************************************/
+int Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest)
+{
+	u32 I;
+	u32 J;
+	u8 Val;
+	u8 FirtVal;
+	u8 Word;
+
+	Xil_AssertNonvoid(Words != 0);
+	Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
+
+	/*
+	 * variable initialization
+	 */
+	Val = XIL_TESTMEM_INIT_VALUE;
+	FirtVal = XIL_TESTMEM_INIT_VALUE;
+
+	/*
+	 * select the proper Subtest(s)
+	 */
+
+	switch (Subtest) {
+
+	case XIL_TESTMEM_ALLMEMTESTS:
+		/* this case executes all of the Subtests */
+		/* fall through case statement */
+
+	case XIL_TESTMEM_INCREMENT:
+		/*
+		 * Fill the memory with incrementing
+		 * values starting from 'FirtVal'
+		 */
+		for (I = 0L; I < Words; I++) {
+			/* write memory location */
+			Addr[I] = Val;
+			Val++;
+		}
+		/*
+		 * Restore the reference 'Val' to the
+		 * initial value
+		 */
+		Val = FirtVal;
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the incrementing reference
+		 * Val
+		 */
+
+		for (I = 0L; I < Words; I++) {
+			/* read memory location */
+			Word = Addr[I];
+			if (Word != Val) {
+				return -1;
+			}
+			Val++;
+		}
+
+		if (Subtest != XIL_TESTMEM_ALLMEMTESTS) {
+			return 0;
+		}
+		/* end of case 1 */
+
+		/* fall through case statement */
+
+	case XIL_TESTMEM_WALKONES:
+		/*
+		 * set up to cycle through all possible initial
+		 * test Patterns for walking ones test
+		 */
+
+		for (J = 0L; J < 8; J++) {
+			/*
+			 * Generate an initial value for walking ones test
+			 * to test for bad data bits
+			 */
+			Val = 1 << J;
+			/*
+			 * START walking ones test
+			 * Write a one to each data bit indifferent locations
+			 */
+			for (I = 0L; I < 8; I++) {
+				/* write memory location */
+				Addr[I] = Val;
+				Val = (u8)RotateLeft(Val, 8);
+			}
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+			Val = 1 << J;
+			/* Read the values from each location that was written */
+			for (I = 0L; I < 8; I++) {
+				/* read memory location */
+				Word = Addr[I];
+				if (Word != Val) {
+					return -1;
+				}
+				Val = (u8)RotateLeft(Val, 8);
+			}
+		}
+
+		if (Subtest != XIL_TESTMEM_ALLMEMTESTS) {
+			return 0;
+		}
+		/* end of case 2 */
+		/* fall through case statement */
+
+	case XIL_TESTMEM_WALKZEROS:
+		/*
+		 * set up to cycle through all possible initial test
+		 * Patterns for walking zeros test
+		 */
+
+		for (J = 0L; J < 8; J++) {
+			/*
+			 * Generate an initial value for walking ones test to test
+			 * for bad data bits
+			 */
+			Val = ~(1 << J);
+			/*
+			 * START walking zeros test
+			 * Write a one to each data bit indifferent locations
+			 */
+			for (I = 0L; I < 8; I++) {
+				/* write memory location */
+				Addr[I] = Val;
+				Val = ~((u8)RotateLeft(~Val, 8));
+			}
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+			Val = ~(1 << J);
+			/* Read the values from each location that was written */
+			for (I = 0L; I < 8; I++) {
+				/* read memory location */
+				Word = Addr[I];
+				if (Word != Val) {
+					return -1;
+				}
+
+				Val = ~((u8)RotateLeft(~Val, 8));
+			}
+		}
+
+		if (Subtest != XIL_TESTMEM_ALLMEMTESTS) {
+			return 0;
+		}
+		/* end of case 3 */
+		/* fall through case statement */
+
+	case XIL_TESTMEM_INVERSEADDR:
+		/* Fill the memory with inverse of address */
+		for (I = 0L; I < Words; I++) {
+			/* write memory location */
+			Val = (u8) (~((u32) (&Addr[I])));
+			Addr[I] = Val;
+		}
+		
+		/*
+		 * Check every word within the words
+		 * of tested memory
+		 */
+		
+		for (I = 0L; I < Words; I++) {
+			/* read memory location */
+			Word = Addr[I];
+			Val = (u8) (~((u32) (&Addr[I])));
+			if ((Word ^ Val) != 0x00) {
+				return -1;
+			}
+		}
+		if (Subtest != XIL_TESTMEM_ALLMEMTESTS) {
+			return 0;
+		}
+		/* end of case 4 */
+		/* fall through case statement */
+
+	case XIL_TESTMEM_FIXEDPATTERN:
+		/*
+		 * Generate an initial value for
+		 * memory testing
+		 */
+
+		if (Pattern == 0) {
+			Val = 0xA5;
+		}
+		else {
+			Val = Pattern;
+		}
+		/*
+		 * Fill the memory with fixed Pattern
+		 */
+		for (I = 0L; I < Words; I++) {
+			/* write memory location */
+			Addr[I] = Val;
+		}
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the fixed Pattern
+		 */
+		
+		for (I = 0L; I < Words; I++) {
+			/* read memory location */
+			Word = Addr[I];
+			if (Word != Val) {
+				return -1;
+			}
+		}
+
+		if (Subtest != XIL_TESTMEM_ALLMEMTESTS) {
+			return 0;
+		}
+
+		/* end of case 5 */
+
+		/* this break is for the prior fall through case statements */
+
+		break;
+
+	default:
+		return -1;
+
+	}	/* end of switch */
+
+	/* Successfully passed memory test ! */
+
+	return 0;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Rotates the provided value to the left one bit position
+*
+* @param    Input is value to be rotated to the left
+* @param    Width is the number of bits in the input data
+*
+* @return
+*
+* The resulting unsigned long value of the rotate left
+*
+* @note
+*
+* None.
+*
+*****************************************************************************/
+static u32 RotateLeft(u32 Input, u8 Width)
+{
+	u32 Msb;
+	u32 ReturnVal;
+	u32 WidthMask;
+	u32 MsbMask;
+
+	/*
+	 * set up the WidthMask and the MsbMask
+	 */
+
+	MsbMask = 1 << (Width - 1);
+
+	WidthMask = (MsbMask << 1) - 1;
+
+	/*
+	 * set the Width of the Input to the correct width
+	 */
+
+	Input = Input & WidthMask;
+
+	Msb = Input & MsbMask;
+
+	ReturnVal = Input << 1;
+
+	if (Msb != 0x00000000) {
+		ReturnVal = ReturnVal | 0x00000001;
+	}
+
+	ReturnVal = ReturnVal & WidthMask;
+
+	return ReturnVal;
+
+}
+
+#ifdef ROTATE_RIGHT
+/*****************************************************************************/
+/**
+*
+* Rotates the provided value to the right one bit position
+*
+* @param    Input is value to be rotated to the right
+* @param    Width is the number of bits in the input data
+*
+* @return
+*
+* The resulting u32 value of the rotate right
+*
+* @note
+*
+* None.
+*
+*****************************************************************************/
+static u32 RotateRight(u32 Input, u8 Width)
+{
+	u32 Lsb;
+	u32 ReturnVal;
+	u32 WidthMask;
+	u32 MsbMask;
+
+	/*
+	 * set up the WidthMask and the MsbMask
+	 */
+
+	MsbMask = 1 << (Width - 1);
+
+	WidthMask = (MsbMask << 1) - 1;
+
+	/*
+	 * set the width of the input to the correct width
+	 */
+
+	Input = Input & WidthMask;
+
+	ReturnVal = Input >> 1;
+
+	Lsb = Input & 0x00000001;
+
+	if (Lsb != 0x00000000) {
+		ReturnVal = ReturnVal | MsbMask;
+	}
+
+	ReturnVal = ReturnVal & WidthMask;
+
+	return ReturnVal;
+
+}
+#endif /* ROTATE_RIGHT */
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_testmem.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_testmem.h
new file mode 100644
index 000000000..74e131d5b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_testmem.h
@@ -0,0 +1,173 @@
+/******************************************************************************
+*
+*
+* (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmem.h
+*
+* This file contains utility functions to test memory.
+*
+* Memory test description
+*
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+*
+* Subtest descriptions:
+* 
+* XIL_TESTMEM_ALLMEMTESTS:
+*       Runs all of the following tests
+*
+* XIL_TESTMEM_INCREMENT:
+*       Incrementing Value Test.
+*       This test starts at 'XIL_TESTMEM_INIT_VALUE' and uses the
+*	incrementing value as the test value for memory.
+*
+* XIL_TESTMEM_WALKONES:
+*       Walking Ones Test.
+*       This test uses a walking '1' as the test value for memory.
+*       location 1 = 0x00000001
+*       location 2 = 0x00000002
+*       ...
+*
+* XIL_TESTMEM_WALKZEROS:
+*       Walking Zero's Test.
+*       This test uses the inverse value of the walking ones test
+*       as the test value for memory.
+*       location 1 = 0xFFFFFFFE
+*       location 2 = 0xFFFFFFFD
+*       ...
+*
+* XIL_TESTMEM_INVERSEADDR:
+*       Inverse Address Test.
+*       This test uses the inverse of the address of the location under test
+*       as the test value for memory.
+*
+* XIL_TESTMEM_FIXEDPATTERN:
+*       Fixed Pattern Test.
+*       This test uses the provided patters as the test value for memory.
+*       If zero is provided as the pattern the test uses '0xDEADBEEF".
+* 

+*
+* WARNING
+*
+* The tests are DESTRUCTIVE. Run before any initialized memory spaces
+* have been set up.
+*
+* The address provided to the memory tests is not checked for
+* validity except for the NULL case. It is possible to provide a code-space
+* pointer for this test to start with and ultimately destroy executable code
+* causing random failures.
+*
+* @note
+*
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  08/25/09 First release
+* 

+*
+******************************************************************************/
+
+#ifndef XIL_TESTMEM_H	/* prevent circular inclusions */
+#define XIL_TESTMEM_H	/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/* xutil_memtest defines */
+
+#define XIL_TESTMEM_INIT_VALUE  1
+
+/** @name Memory subtests
+ * @{
+ */
+/**
+ * See the detailed description of the subtests in the file description.
+ */
+#define XIL_TESTMEM_ALLMEMTESTS     0
+#define XIL_TESTMEM_INCREMENT       1
+#define XIL_TESTMEM_WALKONES        2
+#define XIL_TESTMEM_WALKZEROS       3
+#define XIL_TESTMEM_INVERSEADDR     4
+#define XIL_TESTMEM_FIXEDPATTERN    5
+#define XIL_TESTMEM_MAXTEST         XIL_TESTMEM_FIXEDPATTERN
+/* @} */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/* xutil_testmem prototypes */
+
+extern int Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
+extern int Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
+extern int Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_types.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_types.h
new file mode 100644
index 000000000..087ddb530
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xil_types.h
@@ -0,0 +1,173 @@
+/******************************************************************************
+*
+* (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_types.h
+*
+* This file contains basic types for Xilinx software IP.
+
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 First release
+* 3.03a sdm  05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+* 

+*
+******************************************************************************/
+
+#ifndef XIL_TYPES_H	/* prevent circular inclusions */
+#define XIL_TYPES_H	/* by using protection macros */
+
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#  define TRUE		1
+#endif
+
+#ifndef FALSE
+#  define FALSE		0
+#endif
+
+#ifndef NULL
+#define NULL		0
+#endif
+
+#define XIL_COMPONENT_IS_READY     0x11111111  /**< component has been initialized */
+#define XIL_COMPONENT_IS_STARTED   0x22222222  /**< component has been started */
+
+/** @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XBASIC_TYPES_H
+/**
+ * guarded against xbasic_types.h.
+ */
+typedef unsigned char u8;
+typedef unsigned short u16;
+typedef unsigned long u32;
+
+#define __XUINT64__
+typedef struct
+{
+	u32 Upper;
+	u32 Lower;
+} Xuint64;
+
+
+/*****************************************************************************/
+/**
+* Return the most significant half of the 64 bit data type.
+*
+* @param    x is the 64 bit word.
+*
+* @return   The upper 32 bits of the 64 bit word.
+*
+* @note     None.
+*
+******************************************************************************/
+#define XUINT64_MSW(x) ((x).Upper)
+
+/*****************************************************************************/
+/**
+* Return the least significant half of the 64 bit data type.
+*
+* @param    x is the 64 bit word.
+*
+* @return   The lower 32 bits of the 64 bit word.
+*
+* @note     None.
+*
+******************************************************************************/
+#define XUINT64_LSW(x) ((x).Lower)
+
+#endif /* XBASIC_TYPES_H */
+
+/**
+ * xbasic_types.h does not typedef s* or u64
+ */
+typedef unsigned long long u64;
+
+typedef char s8;
+typedef short s16;
+typedef long s32;
+typedef long long s64;
+#else
+#include 
+#endif
+
+
+/**
+ * This data type defines an interrupt handler for a device.
+ * The argument points to the instance of the component
+ */
+typedef void (*XInterruptHandler) (void *InstancePtr);
+
+/**
+ * This data type defines an exception handler for a processor.
+ * The argument points to the instance of the component
+ */
+typedef void (*XExceptionHandler) (void *InstancePtr);
+
+/*@}*/
+
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#define TRUE		1
+#endif
+
+#ifndef FALSE
+#define FALSE		0
+#endif
+
+#ifndef NULL
+#define NULL		0
+#endif
+
+#endif	/* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xl2cc.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xl2cc.h
new file mode 100644
index 000000000..13b6f763d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xl2cc.h
@@ -0,0 +1,180 @@
+/******************************************************************************
+*
+* (c) Copyright 2011-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xl2cc.h
+*
+* This file contains the address definitions for the PL310 Level-2 Cache
+* Controller.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  02/01/10 Initial version
+* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
+*		      'xil_errata.h' for errata description
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _XL2CC_H_
+#define _XL2CC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+/* L2CC Register Offsets */
+#define XPS_L2CC_ID_OFFSET		0x0000
+#define XPS_L2CC_TYPE_OFFSET		0x0004
+#define XPS_L2CC_CNTRL_OFFSET		0x0100
+#define XPS_L2CC_AUX_CNTRL_OFFSET	0x0104
+#define XPS_L2CC_TAG_RAM_CNTRL_OFFSET	0x0108
+#define XPS_L2CC_DATA_RAM_CNTRL_OFFSET	0x010C
+
+#define XPS_L2CC_EVNT_CNTRL_OFFSET	0x0200
+#define XPS_L2CC_EVNT_CNT1_CTRL_OFFSET	0x0204
+#define XPS_L2CC_EVNT_CNT0_CTRL_OFFSET	0x0208
+#define XPS_L2CC_EVNT_CNT1_VAL_OFFSET	0x020C
+#define XPS_L2CC_EVNT_CNT0_VAL_OFFSET	0x0210
+
+#define XPS_L2CC_IER_OFFSET		0x0214		/* Interrupt Mask */
+#define XPS_L2CC_IPR_OFFSET		0x0218		/* Masked interrupt status */
+#define XPS_L2CC_ISR_OFFSET		0x021C		/* Raw Interrupt Status */
+#define XPS_L2CC_IAR_OFFSET		0x0220		/* Interrupt Clear */
+
+#define XPS_L2CC_CACHE_SYNC_OFFSET		0x0730		/* Cache Sync */
+#define XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET	0x0740		/* Dummy Register for Cache Sync */
+#define XPS_L2CC_CACHE_INVLD_PA_OFFSET		0x0770		/* Cache Invalid by PA */
+#define XPS_L2CC_CACHE_INVLD_WAY_OFFSET		0x077C		/* Cache Invalid by Way */
+#define XPS_L2CC_CACHE_CLEAN_PA_OFFSET		0x07B0		/* Cache Clean by PA */
+#define XPS_L2CC_CACHE_CLEAN_INDX_OFFSET	0x07B8		/* Cache Clean by Index */
+#define XPS_L2CC_CACHE_CLEAN_WAY_OFFSET		0x07BC		/* Cache Clean by Way */
+#define XPS_L2CC_CACHE_INV_CLN_PA_OFFSET	0x07F0		/* Cache Invalidate and Clean by PA */
+#define XPS_L2CC_CACHE_INV_CLN_INDX_OFFSET	0x07F8		/* Cache Invalidate and Clean by Index */
+#define XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET	0x07FC		/* Cache Invalidate and Clean by Way */
+
+#define XPS_L2CC_CACHE_DLCKDWN_0_WAY_OFFSET	0x0900		/* Cache Data Lockdown 0 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_0_WAY_OFFSET	0x0904		/* Cache Instruction Lockdown 0 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_1_WAY_OFFSET	0x0908		/* Cache Data Lockdown 1 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_1_WAY_OFFSET	0x090C		/* Cache Instruction Lockdown 1 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_2_WAY_OFFSET	0x0910		/* Cache Data Lockdown 2 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_2_WAY_OFFSET	0x0914		/* Cache Instruction Lockdown 2 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_3_WAY_OFFSET	0x0918		/* Cache Data Lockdown 3 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_3_WAY_OFFSET	0x091C		/* Cache Instruction Lockdown 3 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_4_WAY_OFFSET	0x0920		/* Cache Data Lockdown 4 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_4_WAY_OFFSET	0x0924		/* Cache Instruction Lockdown 4 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_5_WAY_OFFSET	0x0928		/* Cache Data Lockdown 5 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_5_WAY_OFFSET	0x092C		/* Cache Instruction Lockdown 5 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_6_WAY_OFFSET	0x0930		/* Cache Data Lockdown 6 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_6_WAY_OFFSET	0x0934		/* Cache Instruction Lockdown 6 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_7_WAY_OFFSET	0x0938		/* Cache Data Lockdown 7 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_7_WAY_OFFSET	0x093C		/* Cache Instruction Lockdown 7 by Way */
+
+#define XPS_L2CC_CACHE_LCKDWN_LINE_ENABLE_OFFSET 0x0950		/* Cache Lockdown Line Enable */
+#define XPS_L2CC_CACHE_UUNLOCK_ALL_WAY_OFFSET	0x0954		/* Cache Unlock All Lines by Way */
+
+#define XPS_L2CC_ADDR_FILTER_START_OFFSET	0x0C00		/* Start of address filtering */
+#define XPS_L2CC_ADDR_FILTER_END_OFFSET		0x0C04		/* Start of address filtering */
+
+#define XPS_L2CC_DEBUG_CTRL_OFFSET		0x0F40		/* Debug Control Register */
+
+/* XPS_L2CC_CNTRL_OFFSET bit masks */
+#define XPS_L2CC_ENABLE_MASK		0x00000001	/* enables the L2CC */
+
+/* XPS_L2CC_AUX_CNTRL_OFFSET bit masks */
+#define XPS_L2CC_AUX_EBRESPE_MASK	0x40000000	/* Early BRESP Enable */
+#define XPS_L2CC_AUX_IPFE_MASK		0x20000000	/* Instruction Prefetch Enable */
+#define XPS_L2CC_AUX_DPFE_MASK		0x10000000	/* Data Prefetch Enable */
+#define XPS_L2CC_AUX_NSIC_MASK		0x08000000	/* Non-secure interrupt access control */
+#define XPS_L2CC_AUX_NSLE_MASK		0x04000000	/* Non-secure lockdown enable */
+#define XPS_L2CC_AUX_CRP_MASK		0x02000000	/* Cache replacement policy */
+#define XPS_L2CC_AUX_FWE_MASK		0x01800000	/* Force write allocate */
+#define XPS_L2CC_AUX_SAOE_MASK		0x00400000	/* Shared attribute override enable */
+#define XPS_L2CC_AUX_PE_MASK		0x00200000	/* Parity enable */
+#define XPS_L2CC_AUX_EMBE_MASK		0x00100000	/* Event monitor bus enable */
+#define XPS_L2CC_AUX_WAY_SIZE_MASK	0x000E0000	/* Way-size */
+#define XPS_L2CC_AUX_ASSOC_MASK		0x00010000	/* Associativity */
+#define XPS_L2CC_AUX_SAIE_MASK		0x00002000	/* Shared attribute invalidate enable */
+#define XPS_L2CC_AUX_EXCL_CACHE_MASK	0x00001000	/* Exclusive cache configuration */
+#define XPS_L2CC_AUX_SBDLE_MASK		0x00000800	/* Store buffer device limitation Enable */
+#define XPS_L2CC_AUX_HPSODRE_MASK	0x00000400	/* High Priority for SO and Dev Reads Enable */
+#define XPS_L2CC_AUX_FLZE_MASK		0x00000001	/* Full line of zero enable */
+
+#define XPS_L2CC_AUX_REG_DEFAULT_MASK	0x72360000	/* Enable all prefetching, */
+                                                    /* Cache replacement policy, Parity enable, */
+                                                    /* Event monitor bus enable and Way Size (64 KB) */
+#define XPS_L2CC_AUX_REG_ZERO_MASK	0xFFF1FFFF	/* */
+
+#define XPS_L2CC_TAG_RAM_DEFAULT_MASK	0x00000111	/* latency for TAG RAM */
+#define XPS_L2CC_DATA_RAM_DEFAULT_MASK	0x00000121	/* latency for DATA RAM */
+
+/* Interrupt bit masks */
+#define XPS_L2CC_IXR_DECERR_MASK	0x00000100	/* DECERR from L3 */
+#define XPS_L2CC_IXR_SLVERR_MASK	0x00000080	/* SLVERR from L3 */
+#define XPS_L2CC_IXR_ERRRD_MASK		0x00000040	/* Error on L2 data RAM (Read) */
+#define XPS_L2CC_IXR_ERRRT_MASK		0x00000020	/* Error on L2 tag RAM (Read) */
+#define XPS_L2CC_IXR_ERRWD_MASK		0x00000010	/* Error on L2 data RAM (Write) */
+#define XPS_L2CC_IXR_ERRWT_MASK		0x00000008	/* Error on L2 tag RAM (Write) */
+#define XPS_L2CC_IXR_PARRD_MASK		0x00000004	/* Parity Error on L2 data RAM (Read) */
+#define XPS_L2CC_IXR_PARRT_MASK		0x00000002	/* Parity Error on L2 tag RAM (Read) */
+#define XPS_L2CC_IXR_ECNTR_MASK		0x00000001	/* Event Counter1/0 Overflow Increment */
+
+/* Address filtering mask and enable bit */
+#define XPS_L2CC_ADDR_FILTER_VALID_MASK	0xFFF00000	/* Address filtering valid bits*/
+#define XPS_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001	/* Address filtering enable bit*/
+
+/* Debug control bits */
+#define XPS_L2CC_DEBUG_SPIDEN_MASK	0x00000004	/* Debug SPIDEN bit */
+#define XPS_L2CC_DEBUG_DWB_MASK		0x00000002	/* Debug DWB bit, forces write through */
+#define XPS_L2CC_DEBUG_DCL_MASK		0x00000002	/* Debug DCL bit, disables cache line fill */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xl2cc_counter.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xl2cc_counter.c
new file mode 100644
index 000000000..b17d21734
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xl2cc_counter.c
@@ -0,0 +1,174 @@
+/******************************************************************************
+*
+* (c) Copyright 2011-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xl2cc_counter.c
+*
+* This file contains APIs for configuring and controlling the event counters
+* in PL310 L2 cache controller. For more information about the event counters,
+* see xl2cc_counter.h.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm  07/11/11 First release
+* 3.07a asa  08/30/12 Updated for CR 675636 to provide the L2 Base Address
+*		      inside the APIs
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include 
+#include "xparameters_ps.h"
+#include "xl2cc_counter.h"
+#include "xl2cc.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void XL2cc_EventCtrReset(void);
+
+/******************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* This function initializes the event counters in L2 Cache controller with a
+* set of event codes specified by the user.
+*
+* @param	Event0 is the event code for counter 0.
+* @param	Event1 is the event code for counter 1.
+*		Use the event codes defined by XL2CC_* in xl2cc_counter.h.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XL2cc_EventCtrInit(int Event0, int Event1)
+{
+
+	/* Write event code into cnt1 cfg reg */
+	*((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_CTRL_OFFSET)) = (Event1 << 2);
+
+	/* Write event code into cnt0 cfg reg */
+	*((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT0_CTRL_OFFSET)) = (Event0 << 2);
+
+	/* Reset counters */
+	XL2cc_EventCtrReset();
+}
+
+/****************************************************************************/
+/**
+*
+* This function starts the event counters in L2 Cache controller.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XL2cc_EventCtrStart(void)
+{
+	XL2cc_EventCtrReset();
+
+	/* Enable counter */
+	*((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 1;
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables the event counters in L2 Cache controller, saves the
+* counter values and resets the counters.
+*
+* @param	EveCtr0 is an output parameter which is used to return the value
+*		in event counter 0.
+*		EveCtr1 is an output parameter which is used to return the value
+*		in event counter 1.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1)
+{
+	/* Disable counter */
+	*((volatile u32*) (XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0;
+
+	/* Save counter values */
+	*EveCtr1 = *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_VAL_OFFSET));
+	*EveCtr0 = *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT0_VAL_OFFSET));
+
+	XL2cc_EventCtrReset();
+}
+
+/****************************************************************************/
+/**
+*
+* This function resets the event counters in L2 Cache controller.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XL2cc_EventCtrReset(void)
+{
+	*((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0x6;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xl2cc_counter.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xl2cc_counter.h
new file mode 100644
index 000000000..30952b1dc
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xl2cc_counter.h
@@ -0,0 +1,117 @@
+/******************************************************************************
+*
+* (c) Copyright 2011-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xl2cc_counter.h
+*
+* This header file contains APIs for configuring and controlling the event
+* counters in PL310 L2 cache controller.
+* PL310 has 2 event counters which can be used to count a variety of events
+* like DRHIT, DRREQ, DWHIT, DWREQ, etc. This file defines configurations,
+* where value configures the event counters to count a set of events.
+*
+* XL2cc_EventCtrInit API can be used to select a set of events and
+* XL2cc_EventCtrStart configures the event counters and starts the counters.
+* XL2cc_EventCtrStop diables the event counters and returns the counter values.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm  07/11/11 First release
+* 3.07a asa  08/30/12 Updated for CR 675636 to provide the L2 Base Address
+*		      inside the APIs
+* 

+*
+******************************************************************************/
+
+#ifndef L2CCCOUNTER_H /* prevent circular inclusions */
+#define L2CCCOUNTER_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constants define the event codes for the event counters.
+ */
+#define XL2CC_CO		0x1
+#define XL2CC_DRHIT		0x2
+#define XL2CC_DRREQ		0x3
+#define XL2CC_DWHIT		0x4
+#define XL2CC_DWREQ		0x5
+#define XL2CC_DWTREQ		0x6
+#define XL2CC_IRHIT		0x7
+#define XL2CC_IRREQ		0x8
+#define XL2CC_WA		0x9
+#define XL2CC_IPFALLOC		0xa
+#define XL2CC_EPFHIT		0xb
+#define XL2CC_EPFALLOC		0xc
+#define XL2CC_SRRCVD		0xd
+#define XL2CC_SRCONF		0xe
+#define XL2CC_EPFRCVD		0xf
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+void XL2cc_EventCtrInit(int Event0, int Event1);
+void XL2cc_EventCtrStart(void);
+void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* L2CCCOUNTER_H */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xparameters_ps.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xparameters_ps.h
new file mode 100644
index 000000000..766e1705b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xparameters_ps.h
@@ -0,0 +1,334 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-2013  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xparameters_ps.h
+*
+* This file contains the address definitions for the hard peripherals
+* attached to the ARM Cortex A9 core.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 02/01/10 Initial version
+* 3.04a sdm     02/02/12 Removed some of the defines as they are being generated through
+*                        driver tcl
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _XPARAMETERS_PS_H_
+#define _XPARAMETERS_PS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock
+ */
+
+/* Canonical definitions for DDR MEMORY */
+#define XPAR_DDR_MEM_BASEADDR		0x00000000
+#define XPAR_DDR_MEM_HIGHADDR		0x3FFFFFFF
+
+/* Canonical definitions for Interrupts  */
+#define XPAR_XUARTPS_0_INTR		XPS_UART0_INT_ID
+#define XPAR_XUARTPS_1_INTR		XPS_UART1_INT_ID
+#define XPAR_XUSBPS_0_INTR		XPS_USB0_INT_ID
+#define XPAR_XUSBPS_1_INTR		XPS_USB1_INT_ID
+#define XPAR_XIICPS_0_INTR		XPS_I2C0_INT_ID
+#define XPAR_XIICPS_1_INTR		XPS_I2C1_INT_ID
+#define XPAR_XSPIPS_0_INTR		XPS_SPI0_INT_ID
+#define XPAR_XSPIPS_1_INTR		XPS_SPI1_INT_ID
+#define XPAR_XCANPS_0_INTR		XPS_CAN0_INT_ID
+#define XPAR_XCANPS_1_INTR		XPS_CAN1_INT_ID
+#define XPAR_XGPIOPS_0_INTR		XPS_GPIO_INT_ID
+#define XPAR_XEMACPS_0_INTR		XPS_GEM0_INT_ID
+#define XPAR_XEMACPS_0_WAKE_INTR	XPS_GEM0_WAKE_INT_ID
+#define XPAR_XEMACPS_1_INTR		XPS_GEM1_INT_ID
+#define XPAR_XEMACPS_1_WAKE_INTR	XPS_GEM1_WAKE_INT_ID
+#define XPAR_XSDIOPS_0_INTR		XPS_SDIO0_INT_ID
+#define XPAR_XQSPIPS_0_INTR		XPS_QSPI_INT_ID
+#define XPAR_XSDIOPS_1_INTR		XPS_SDIO1_INT_ID
+#define XPAR_XWDTPS_0_INTR		XPS_WDT_INT_ID
+#define XPAR_XDCFG_0_INTR		XPS_DVC_INT_ID
+#define XPAR_SCUTIMER_INTR		XPS_SCU_TMR_INT_ID
+#define XPAR_SCUWDT_INTR		XPS_SCU_WDT_INT_ID
+#define XPAR_XTTCPS_0_INTR		XPS_TTC0_0_INT_ID
+#define XPAR_XTTCPS_1_INTR		XPS_TTC0_1_INT_ID
+#define XPAR_XTTCPS_2_INTR		XPS_TTC0_2_INT_ID
+#define XPAR_XTTCPS_3_INTR		XPS_TTC1_0_INT_ID
+#define XPAR_XTTCPS_4_INTR		XPS_TTC1_1_INT_ID
+#define XPAR_XTTCPS_5_INTR		XPS_TTC1_2_INT_ID
+#define XPAR_XDMAPS_0_FAULT_INTR	XPS_DMA0_ABORT_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_0	XPS_DMA0_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_1	XPS_DMA1_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_2	XPS_DMA2_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_3	XPS_DMA3_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_4	XPS_DMA4_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_5	XPS_DMA5_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_6	XPS_DMA6_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_7	XPS_DMA7_INT_ID
+
+
+#define XPAR_XQSPIPS_0_LINEAR_BASEADDR	XPS_QSPI_LINEAR_BASEADDR
+#define XPAR_XPARPORTPS_CTRL_BASEADDR	XPS_PARPORT_CRTL_BASEADDR
+
+
+
+/* Canonical definitions for DMAC */
+
+
+/* Canonical definitions for WDT */
+
+/* Canonical definitions for SLCR */
+#define XPAR_XSLCR_NUM_INSTANCES	1
+#define XPAR_XSLCR_0_DEVICE_ID		0
+#define XPAR_XSLCR_0_BASEADDR		XPS_SYS_CTRL_BASEADDR
+
+/* Canonical definitions for SCU GIC */
+#define XPAR_SCUGIC_NUM_INSTANCES	1
+#define XPAR_SCUGIC_SINGLE_DEVICE_ID	0
+#define XPAR_SCUGIC_CPU_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x0100)
+#define XPAR_SCUGIC_DIST_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x1000)
+#define XPAR_SCUGIC_ACK_BEFORE		0
+
+/* Canonical definitions for Global Timer */
+#define XPAR_GLOBAL_TMR_NUM_INSTANCES	1
+#define XPAR_GLOBAL_TMR_DEVICE_ID	0
+#define XPAR_GLOBAL_TMR_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x200)
+#define XPAR_GLOBAL_TMR_INTR		XPS_GLOBAL_TMR_INT_ID
+
+
+/* Xilinx Parallel Flash Library (XilFlash) User Settings */
+#define XPAR_AXI_EMC
+
+
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock. These have been put for bacwards compatibilty
+ */
+
+#define XPS_PERIPHERAL_BASEADDR		0xE0000000
+#define XPS_UART0_BASEADDR		0xE0000000
+#define XPS_UART1_BASEADDR		0xE0001000
+#define XPS_USB0_BASEADDR		0xE0002000
+#define XPS_USB1_BASEADDR		0xE0003000
+#define XPS_I2C0_BASEADDR		0xE0004000
+#define XPS_I2C1_BASEADDR		0xE0005000
+#define XPS_SPI0_BASEADDR		0xE0006000
+#define XPS_SPI1_BASEADDR		0xE0007000
+#define XPS_CAN0_BASEADDR		0xE0008000
+#define XPS_CAN1_BASEADDR		0xE0009000
+#define XPS_GPIO_BASEADDR		0xE000A000
+#define XPS_GEM0_BASEADDR		0xE000B000
+#define XPS_GEM1_BASEADDR		0xE000C000
+#define XPS_QSPI_BASEADDR		0xE000D000
+#define XPS_PARPORT_CRTL_BASEADDR	0xE000E000
+#define XPS_SDIO0_BASEADDR		0xE0100000
+#define XPS_SDIO1_BASEADDR		0xE0101000
+#define XPS_IOU_BUS_CFG_BASEADDR	0xE0200000
+#define XPS_NAND_BASEADDR		0xE1000000
+#define XPS_PARPORT0_BASEADDR		0xE2000000
+#define XPS_PARPORT1_BASEADDR		0xE4000000
+#define XPS_QSPI_LINEAR_BASEADDR	0xFC000000
+#define XPS_SYS_CTRL_BASEADDR		0xF8000000	/* AKA SLCR */
+#define XPS_TTC0_BASEADDR		0xF8001000
+#define XPS_TTC1_BASEADDR		0xF8002000
+#define XPS_DMAC0_SEC_BASEADDR		0xF8003000
+#define XPS_DMAC0_NON_SEC_BASEADDR	0xF8004000
+#define XPS_WDT_BASEADDR		0xF8005000
+#define XPS_DDR_CTRL_BASEADDR		0xF8006000
+#define XPS_DEV_CFG_APB_BASEADDR	0xF8007000
+#define XPS_AFI0_BASEADDR		0xF8008000
+#define XPS_AFI1_BASEADDR		0xF8009000
+#define XPS_AFI2_BASEADDR		0xF800A000
+#define XPS_AFI3_BASEADDR		0xF800B000
+#define XPS_OCM_BASEADDR		0xF800C000
+#define XPS_EFUSE_BASEADDR		0xF800D000
+#define XPS_CORESIGHT_BASEADDR		0xF8800000
+#define XPS_TOP_BUS_CFG_BASEADDR	0xF8900000
+#define XPS_SCU_PERIPH_BASE		0xF8F00000
+#define XPS_L2CC_BASEADDR		0xF8F02000
+#define XPS_SAM_RAM_BASEADDR		0xFFFC0000
+#define XPS_FPGA_AXI_S0_BASEADDR	0x40000000
+#define XPS_FPGA_AXI_S1_BASEADDR	0x80000000
+#define XPS_IOU_S_SWITCH_BASEADDR	0xE0000000
+#define XPS_PERIPH_APB_BASEADDR		0xF8000000
+
+/* Shared Peripheral Interrupts (SPI) */
+#define XPS_CORE_PARITY0_INT_ID		32
+#define XPS_CORE_PARITY1_INT_ID		33
+#define XPS_L2CC_INT_ID			34
+#define XPS_OCMINTR_INT_ID		35
+#define XPS_ECC_INT_ID			36
+#define XPS_PMU0_INT_ID			37
+#define XPS_PMU1_INT_ID			38
+#define XPS_SYSMON_INT_ID		39
+#define XPS_DVC_INT_ID			40
+#define XPS_WDT_INT_ID			41
+#define XPS_TTC0_0_INT_ID		42
+#define XPS_TTC0_1_INT_ID		43
+#define XPS_TTC0_2_INT_ID 		44
+#define XPS_DMA0_ABORT_INT_ID		45
+#define XPS_DMA0_INT_ID			46
+#define XPS_DMA1_INT_ID			47
+#define XPS_DMA2_INT_ID			48
+#define XPS_DMA3_INT_ID			49
+#define XPS_SMC_INT_ID			50
+#define XPS_QSPI_INT_ID			51
+#define XPS_GPIO_INT_ID			52
+#define XPS_USB0_INT_ID			53
+#define XPS_GEM0_INT_ID			54
+#define XPS_GEM0_WAKE_INT_ID		55
+#define XPS_SDIO0_INT_ID		56
+#define XPS_I2C0_INT_ID			57
+#define XPS_SPI0_INT_ID			58
+#define XPS_UART0_INT_ID		59
+#define XPS_CAN0_INT_ID			60
+#define XPS_FPGA0_INT_ID		61
+#define XPS_FPGA1_INT_ID		62
+#define XPS_FPGA2_INT_ID		63
+#define XPS_FPGA3_INT_ID		64
+#define XPS_FPGA4_INT_ID		65
+#define XPS_FPGA5_INT_ID		66
+#define XPS_FPGA6_INT_ID		67
+#define XPS_FPGA7_INT_ID		68
+#define XPS_TTC1_0_INT_ID		69
+#define XPS_TTC1_1_INT_ID		70
+#define XPS_TTC1_2_INT_ID		71
+#define XPS_DMA4_INT_ID			72
+#define XPS_DMA5_INT_ID			73
+#define XPS_DMA6_INT_ID			74
+#define XPS_DMA7_INT_ID			75
+#define XPS_USB1_INT_ID			76
+#define XPS_GEM1_INT_ID			77
+#define XPS_GEM1_WAKE_INT_ID		78
+#define XPS_SDIO1_INT_ID		79
+#define XPS_I2C1_INT_ID			80
+#define XPS_SPI1_INT_ID			81
+#define XPS_UART1_INT_ID		82
+#define XPS_CAN1_INT_ID			83
+#define XPS_FPGA8_INT_ID		84
+#define XPS_FPGA9_INT_ID		85
+#define XPS_FPGA10_INT_ID		86
+#define XPS_FPGA11_INT_ID		87
+#define XPS_FPGA12_INT_ID		88
+#define XPS_FPGA13_INT_ID		89
+#define XPS_FPGA14_INT_ID		90
+#define XPS_FPGA15_INT_ID		91
+
+/* Private Peripheral Interrupts (PPI) */
+#define XPS_GLOBAL_TMR_INT_ID		27	/* SCU Global Timer interrupt */
+#define XPS_FIQ_INT_ID			28	/* FIQ from FPGA fabric */
+#define XPS_SCU_TMR_INT_ID		29	/* SCU Private Timer interrupt */
+#define XPS_SCU_WDT_INT_ID		30	/* SCU Private WDT interrupt */
+#define XPS_IRQ_INT_ID			31	/* IRQ from FPGA fabric */
+
+
+/* REDEFINES for TEST APP */
+/* Definitions for UART */
+#define XPAR_PS7_UART_0_INTR		XPS_UART0_INT_ID
+#define XPAR_PS7_UART_1_INTR		XPS_UART1_INT_ID
+#define XPAR_PS7_USB_0_INTR		XPS_USB0_INT_ID
+#define XPAR_PS7_USB_1_INTR		XPS_USB1_INT_ID
+#define XPAR_PS7_I2C_0_INTR		XPS_I2C0_INT_ID
+#define XPAR_PS7_I2C_1_INTR		XPS_I2C1_INT_ID
+#define XPAR_PS7_SPI_0_INTR		XPS_SPI0_INT_ID
+#define XPAR_PS7_SPI_1_INTR		XPS_SPI1_INT_ID
+#define XPAR_PS7_CAN_0_INTR		XPS_CAN0_INT_ID
+#define XPAR_PS7_CAN_1_INTR		XPS_CAN1_INT_ID
+#define XPAR_PS7_GPIO_0_INTR		XPS_GPIO_INT_ID
+#define XPAR_PS7_ETHERNET_0_INTR	XPS_GEM0_INT_ID
+#define XPAR_PS7_ETHERNET_0_WAKE_INTR	XPS_GEM0_WAKE_INT_ID
+#define XPAR_PS7_ETHERNET_1_INTR	XPS_GEM1_INT_ID
+#define XPAR_PS7_ETHERNET_1_WAKE_INTR	XPS_GEM1_WAKE_INT_ID
+#define XPAR_PS7_QSPI_0_INTR		XPS_QSPI_INT_ID
+#define XPAR_PS7_WDT_0_INTR		XPS_WDT_INT_ID
+#define XPAR_PS7_SCUWDT_0_INTR		XPS_SCU_WDT_INT_ID
+#define XPAR_PS7_SCUTIMER_0_INTR	XPS_SCU_TMR_INT_ID
+#define XPAR_PS7_XADC_0_INTR		XPS_SYSMON_INT_ID
+
+#define XPAR_XADCPS_INT_ID		XPS_SYSMON_INT_ID
+
+/* For backwards compatibilty */
+#define XPAR_XUARTPS_0_CLOCK_HZ		XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
+#define XPAR_XUARTPS_1_CLOCK_HZ		XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
+#define XPAR_XTTCPS_0_CLOCK_HZ		XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_1_CLOCK_HZ		XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_2_CLOCK_HZ		XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_3_CLOCK_HZ		XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_4_CLOCK_HZ		XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_5_CLOCK_HZ		XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
+#define XPAR_XIICPS_0_CLOCK_HZ		XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
+#define XPAR_XIICPS_1_CLOCK_HZ		XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
+
+#define XPAR_XQSPIPS_0_CLOCK_HZ		XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
+
+#ifdef XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+#endif
+
+#ifdef XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
+#endif
+
+#define XPAR_SCUTIMER_DEVICE_ID		0
+#define XPAR_SCUWDT_DEVICE_ID		0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xpm_counter.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xpm_counter.c
new file mode 100644
index 000000000..1e03f8a3e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xpm_counter.c
@@ -0,0 +1,300 @@
+/******************************************************************************
+*
+* (c) Copyright 2011-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpm_counter.c
+*
+* This file contains APIs for configuring and controlling the Cortex-A9
+* Performance Monitor Events. For more information about the event counters,
+* see xpm_counter.h.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm  07/11/11 First release
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xpm_counter.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+typedef const u32 PmcrEventCfg[XPM_CTRCOUNT];
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions *****************************/
+
+static PmcrEventCfg PmcrEvents[] = {
+	{
+		XPM_EVENT_SOFTINCR,
+		XPM_EVENT_INSRFETCH_CACHEREFILL,
+		XPM_EVENT_INSTRFECT_TLBREFILL,
+		XPM_EVENT_DATA_CACHEREFILL,
+		XPM_EVENT_DATA_CACHEACCESS,
+		XPM_EVENT_DATA_TLBREFILL
+	},
+	{
+		XPM_EVENT_DATA_READS,
+		XPM_EVENT_DATA_WRITE,
+		XPM_EVENT_EXCEPTION,
+		XPM_EVENT_EXCEPRETURN,
+		XPM_EVENT_CHANGECONTEXT,
+		XPM_EVENT_SW_CHANGEPC
+	},
+	{
+		XPM_EVENT_IMMEDBRANCH,
+		XPM_EVENT_UNALIGNEDACCESS,
+		XPM_EVENT_BRANCHMISS,
+		XPM_EVENT_CLOCKCYCLES,
+		XPM_EVENT_BRANCHPREDICT,
+		XPM_EVENT_JAVABYTECODE
+	},
+	{
+		XPM_EVENT_SWJAVABYTECODE,
+		XPM_EVENT_JAVABACKBRANCH,
+		XPM_EVENT_COHERLINEMISS,
+		XPM_EVENT_COHERLINEHIT,
+		XPM_EVENT_INSTRSTALL,
+		XPM_EVENT_DATASTALL
+	},
+	{
+		XPM_EVENT_MAINTLBSTALL,
+		XPM_EVENT_STREXPASS,
+		XPM_EVENT_STREXFAIL,
+		XPM_EVENT_DATAEVICT,
+		XPM_EVENT_NODISPATCH,
+		XPM_EVENT_ISSUEEMPTY
+	},
+	{
+		XPM_EVENT_INSTRRENAME,
+		XPM_EVENT_PREDICTFUNCRET,
+		XPM_EVENT_MAINEXEC,
+		XPM_EVENT_SECEXEC,
+		XPM_EVENT_LDRSTR,
+		XPM_EVENT_FLOATRENAME
+	},
+	{
+		XPM_EVENT_NEONRENAME,
+		XPM_EVENT_PLDSTALL,
+		XPM_EVENT_WRITESTALL,
+		XPM_EVENT_INSTRTLBSTALL,
+		XPM_EVENT_DATATLBSTALL,
+		XPM_EVENT_INSTR_uTLBSTALL
+	},
+	{
+		XPM_EVENT_DATA_uTLBSTALL,
+		XPM_EVENT_DMB_STALL,
+		XPM_EVENT_INT_CLKEN,
+		XPM_EVENT_DE_CLKEN,
+		XPM_EVENT_INSTRISB,
+		XPM_EVENT_INSTRDSB
+	},
+	{
+		XPM_EVENT_INSTRDMB,
+		XPM_EVENT_EXTINT,
+		XPM_EVENT_PLE_LRC,
+		XPM_EVENT_PLE_LRS,
+		XPM_EVENT_PLE_FLUSH,
+		XPM_EVENT_PLE_CMPL
+	},
+	{
+		XPM_EVENT_PLE_OVFL,
+		XPM_EVENT_PLE_PROG,
+		XPM_EVENT_PLE_LRC,
+		XPM_EVENT_PLE_LRS,
+		XPM_EVENT_PLE_FLUSH,
+		XPM_EVENT_PLE_CMPL
+	},
+	{
+		XPM_EVENT_DATASTALL,
+		XPM_EVENT_INSRFETCH_CACHEREFILL,
+		XPM_EVENT_INSTRFECT_TLBREFILL,
+		XPM_EVENT_DATA_CACHEREFILL,
+		XPM_EVENT_DATA_CACHEACCESS,
+		XPM_EVENT_DATA_TLBREFILL
+	},
+};
+
+/************************** Function Prototypes ******************************/
+
+void Xpm_DisableEventCounters(void);
+void Xpm_EnableEventCounters (void);
+void Xpm_ResetEventCounters (void);
+
+/******************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* This function disables the Cortex A9 event counters.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xpm_DisableEventCounters(void)
+{
+	/* Disable the event counters */
+	mtcp(XREG_CP15_COUNT_ENABLE_CLR, 0x3f);
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the Cortex A9 event counters.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xpm_EnableEventCounters(void)
+{
+	/* Enable the event counters */
+	mtcp(XREG_CP15_COUNT_ENABLE_SET, 0x3f);
+}
+
+/****************************************************************************/
+/**
+*
+* This function resets the Cortex A9 event counters.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xpm_ResetEventCounters(void)
+{
+	u32 Reg;
+
+#ifdef __GNUC__
+	Reg = mfcp(XREG_CP15_PERF_MONITOR_CTRL);
+#else
+	{ register unsigned int C15Reg __asm(XREG_CP15_PERF_MONITOR_CTRL);
+	  Reg = C15Reg; }
+#endif
+	Reg |= (1 << 2); /* reset event counters */
+	mtcp(XREG_CP15_PERF_MONITOR_CTRL, Reg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function configures the Cortex A9 event counters controller, with the
+* event codes, in a configuration selected by the user and enables the counters.
+*
+* @param	PmcrCfg is configuration value based on which the event counters
+*		are configured.
+*		Use XPM_CNTRCFG* values defined in xpm_counter.h.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xpm_SetEvents(int PmcrCfg)
+{
+	u32 Counter;
+	const u32 *Ptr = PmcrEvents[PmcrCfg];
+
+	Xpm_DisableEventCounters();
+
+	for(Counter = 0; Counter < XPM_CTRCOUNT; Counter++) {
+
+		/* Selecet event counter */
+		mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
+
+		/* Set the event */
+		mtcp(XREG_CP15_EVENT_TYPE_SEL, Ptr[Counter]);
+	}
+
+	Xpm_ResetEventCounters();
+	Xpm_EnableEventCounters();
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables the event counters and returns the counter values.
+*
+* @param	PmCtrValue is a pointer to an array of type u32 PmCtrValue[6].
+*		It is an output parameter which is used to return the PM
+*		counter values.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xpm_GetEventCounters(u32 *PmCtrValue)
+{
+	u32 Counter;
+
+	Xpm_DisableEventCounters();
+
+	for(Counter = 0; Counter < XPM_CTRCOUNT; Counter++) {
+
+		mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
+#ifdef __GNUC__
+		PmCtrValue[Counter] = mfcp(XREG_CP15_PERF_MONITOR_COUNT);
+#else
+		{ register unsigned int Cp15Reg __asm(XREG_CP15_PERF_MONITOR_COUNT);
+		  PmCtrValue[Counter] = Cp15Reg; }
+#endif
+	}
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xpm_counter.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xpm_counter.h
new file mode 100644
index 000000000..2ef3f9fab
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xpm_counter.h
@@ -0,0 +1,580 @@
+/******************************************************************************
+*
+* (c) Copyright 2011-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpm_counter.h
+*
+* This header file contains APIs for configuring and controlling the Cortex-A9
+* Performance Monitor Events.
+* Cortex-A9 Performance Monitor has 6 event counters which can be used to
+* count a variety of events described in Coretx-A9 TRM. This file defines
+* configurations, where value configures the event counters to count a
+* set of events.
+*
+* Xpm_SetEvents can be used to set the event counters to count a set of events
+* and Xpm_GetEventCounters can be used to read the counter values.
+*
+* @note
+*
+* This file doesn't handle the Cortex-A9 cycle counter, as the cycle counter is
+* being used for time keeping.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm  07/11/11 First release
+* 

+*
+******************************************************************************/
+
+#ifndef XPMCOUNTER_H /* prevent circular inclusions */
+#define XPMCOUNTER_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include 
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/* Number of performance counters */
+#define XPM_CTRCOUNT 6
+
+/* The following constants define the Cortex-A9 Performance Monitor Events */
+
+/*
+ * Software increment. The register is incremented only on writes to the
+ * Software Increment Register
+ */
+#define XPM_EVENT_SOFTINCR 0x00
+
+/*
+ * Instruction fetch that causes a refill at (at least) the lowest level(s) of
+ * instruction or unified cache. Includes the speculative linefills in the
+ * count
+ */
+#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01
+
+/*
+ * Instruction fetch that causes a TLB refill at (at least) the lowest level of
+ * TLB. Includes the speculative requests in the count
+ */
+#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02
+
+/*
+ * Data read or write operation that causes a refill at (at least) the lowest
+ * level(s)of data or unified cache. Counts the number of allocations performed
+ * in the Data Cache due to a read or a write
+ */
+#define XPM_EVENT_DATA_CACHEREFILL 0x03
+
+/*
+ * Data read or write operation that causes a cache access at (at least) the
+ * lowest level(s) of data or unified cache. This includes speculative reads
+ */
+#define XPM_EVENT_DATA_CACHEACCESS 0x04
+
+/*
+ * Data read or write operation that causes a TLB refill at (at least) the
+ * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI,
+ * CP15 Cache operation by MVA and CP15 VA to PA operations
+ */
+#define XPM_EVENT_DATA_TLBREFILL 0x05
+
+/*
+ * Data read architecturally executed. Counts the number of data read
+ * instructions accepted by the Load Store Unit. This includes counting the
+ * speculative and aborted LDR/LDM, as well as the reads due to the SWP
+ * instructions
+ */
+#define XPM_EVENT_DATA_READS 0x06
+
+/*
+ * Data write architecturally executed. Counts the number of data write
+ * instructions accepted by the Load Store Unit. This includes counting the
+ * speculative and aborted STR/STM, as well as the writes due to the SWP
+ * instructions
+ */
+#define XPM_EVENT_DATA_WRITE 0x07
+
+/* Exception taken. Counts the number of exceptions architecturally taken.*/
+#define XPM_EVENT_EXCEPTION 0x09
+
+/* Exception return architecturally executed.*/
+#define XPM_EVENT_EXCEPRETURN 0x0A
+
+/*
+ * Change to ContextID retired. Counts the number of instructions
+ * architecturally executed writing into the ContextID Register
+ */
+#define XPM_EVENT_CHANGECONTEXT 0x0B
+
+/*
+ * Software change of PC, except by an exception, architecturally executed.
+ * Count the number of PC changes architecturally executed, excluding the PC
+ * changes due to taken exceptions
+ */
+#define XPM_EVENT_SW_CHANGEPC 0x0C
+
+/*
+ * Immediate branch architecturally executed (taken or not taken). This includes
+ * the branches which are flushed due to a previous load/store which aborts
+ * late
+ */
+#define XPM_EVENT_IMMEDBRANCH 0x0D
+
+/*
+ * Unaligned access architecturally executed. Counts the number of aborted
+ * unaligned accessed architecturally executed, and the number of not-aborted
+ * unaligned accesses, including the speculative ones
+ */
+#define XPM_EVENT_UNALIGNEDACCESS 0x0F
+
+/*
+ * Branch mispredicted/not predicted. Counts the number of mispredicted or
+ * not-predicted branches executed. This includes the branches which are flushed
+ * due to a previous load/store which aborts late
+ */
+#define XPM_EVENT_BRANCHMISS 0x10
+
+/*
+ * Counts clock cycles when the Cortex-A9 processor is not in WFE/WFI. This
+ * event is not exported on the PMUEVENT bus
+ */
+#define XPM_EVENT_CLOCKCYCLES 0x11
+
+/*
+ * Branches or other change in program flow that could have been predicted by
+ * the branch prediction resources of the processor. This includes the branches
+ * which are flushed due to a previous load/store which aborts late
+ */
+#define XPM_EVENT_BRANCHPREDICT 0x12
+
+/*
+ * Java bytecode execute. Counts the number of Java bytecodes being decoded,
+ * including speculative ones
+ */
+#define XPM_EVENT_JAVABYTECODE 0x40
+
+/*
+ * Software Java bytecode executed. Counts the number of software java bytecodes
+ * being decoded, including speculative ones
+ */
+#define XPM_EVENT_SWJAVABYTECODE 0x41
+
+/*
+ * Jazelle backward branches executed. Counts the number of Jazelle taken
+ * branches being executed. This includes the branches which are flushed due
+ * to a previous load/store which aborts late
+ */
+#define XPM_EVENT_JAVABACKBRANCH 0x42
+
+/*
+ * Coherent linefill miss Counts the number of coherent linefill requests
+ * performed by the Cortex-A9 processor which also miss in all the other
+ * Cortex-A9 processors, meaning that the request is sent to the external
+ * memory
+ */
+#define XPM_EVENT_COHERLINEMISS 0x50
+
+/*
+ * Coherent linefill hit. Counts the number of coherent linefill requests
+ * performed by the Cortex-A9 processor which hit in another Cortex-A9
+ * processor, meaning that the linefill data is fetched directly from the
+ * relevant Cortex-A9 cache
+ */
+#define XPM_EVENT_COHERLINEHIT 0x51
+
+/*
+ * Instruction cache dependent stall cycles. Counts the number of cycles where
+ * the processor is ready to accept new instructions, but does not receive any
+ * due to the instruction side not being able to provide any and the
+ * instruction cache is currently performing at least one linefill
+ */
+#define XPM_EVENT_INSTRSTALL 0x60
+
+/*
+ * Data cache dependent stall cycles. Counts the number of cycles where the core
+ * has some instructions that it cannot issue to any pipeline, and the Load
+ * Store unit has at least one pending linefill request, and no pending
+ */
+#define XPM_EVENT_DATASTALL 0x61
+
+/*
+ * Main TLB miss stall cycles. Counts the number of cycles where the processor
+ * is stalled waiting for the completion of translation table walks from the
+ * main TLB. The processor stalls can be due to the instruction side not being
+ * able to provide the instructions, or to the data side not being able to
+ * provide the necessary data, due to them waiting for the main TLB translation
+ * table walk to complete
+ */
+#define XPM_EVENT_MAINTLBSTALL 0x62
+
+/*
+ * Counts the number of STREX instructions architecturally executed and
+ * passed
+ */
+#define XPM_EVENT_STREXPASS 0x63
+
+/*
+ * Counts the number of STREX instructions architecturally executed and
+ * failed
+ */
+#define XPM_EVENT_STREXFAIL 0x64
+
+/*
+ * Data eviction. Counts the number of eviction requests due to a linefill in
+ * the data cache
+ */
+#define XPM_EVENT_DATAEVICT 0x65
+
+/*
+ * Counts the number of cycles where the issue stage does not dispatch any
+ * instruction because it is empty or cannot dispatch any instructions
+ */
+#define XPM_EVENT_NODISPATCH 0x66
+
+/*
+ * Counts the number of cycles where the issue stage is empty
+ */
+#define XPM_EVENT_ISSUEEMPTY 0x67
+
+/*
+ * Counts the number of instructions going through the Register Renaming stage.
+ * This number is an approximate number of the total number of instructions
+ * speculatively executed, and even more approximate of the total number of
+ * instructions architecturally executed. The approximation depends mainly on
+ * the branch misprediction rate.
+ * The renaming stage can handle two instructions in the same cycle so the event
+ * is two bits long:
+ *    - b00 no instructions renamed
+ *    - b01 one instruction renamed
+ *    - b10 two instructions renamed
+ */
+#define XPM_EVENT_INSTRRENAME 0x68
+
+/*
+ * Counts the number of procedure returns whose condition codes do not fail,
+ * excluding all returns from exception. This count includes procedure returns
+ * which are flushed due to a previous load/store which aborts late.
+ * Only the following instructions are reported:
+ * - BX R14
+ * - MOV PC LR
+ * - POP {..,pc}
+ * - LDR pc,[sp],#offset
+ * The following instructions are not reported:
+ * - LDMIA R9!,{..,PC} (ThumbEE state only)
+ * - LDR PC,[R9],#offset (ThumbEE state only)
+ * - BX R0 (Rm != R14)
+ * - MOV PC,R0 (Rm != R14)
+ * - LDM SP,{...,PC} (writeback not specified)
+ * - LDR PC,[SP,#offset] (wrong addressing mode)
+ */
+#define XPM_EVENT_PREDICTFUNCRET 0x6E
+
+/*
+ * Counts the number of instructions being executed in the main execution
+ * pipeline of the processor, the multiply pipeline and arithmetic logic unit
+ * pipeline. The counted instructions are still speculative
+ */
+#define XPM_EVENT_MAINEXEC 0x70
+
+/*
+ * Counts the number of instructions being executed in the processor second
+ * execution pipeline (ALU). The counted instructions are still speculative
+ */
+#define XPM_EVENT_SECEXEC 0x71
+
+/*
+ * Counts the number of instructions being executed in the Load/Store unit. The
+ * counted instructions are still speculative
+ */
+#define XPM_EVENT_LDRSTR 0x72
+
+/*
+ * Counts the number of Floating-point instructions going through the Register
+ * Rename stage. Instructions are still speculative in this stage.
+ *Two floating-point instructions can be renamed in the same cycle so the event
+ * is two bitslong:
+ *0b00 no floating-point instruction renamed
+ *0b01 one floating-point instruction renamed
+ *0b10 two floating-point instructions renamed
+ */
+#define XPM_EVENT_FLOATRENAME 0x73
+
+/*
+ * Counts the number of Neon instructions going through the Register Rename
+ * stage.Instructions are still speculative in this stage.
+ * Two NEON instructions can be renamed in the same cycle so the event is two
+ * bits long:
+ *0b00 no NEON instruction renamed
+ *0b01 one NEON instruction renamed
+ *0b10 two NEON instructions renamed
+ */
+#define XPM_EVENT_NEONRENAME 0x74
+
+/*
+ * Counts the number of cycles where the processor is stalled because PLD slots
+ * are all full
+ */
+#define XPM_EVENT_PLDSTALL 0x80
+
+/*
+ * Counts the number of cycles when the processor is stalled and the data side
+ * is stalled too because it is full and executing writes to the external
+ * memory
+ */
+#define XPM_EVENT_WRITESTALL 0x81
+
+/*
+ * Counts the number of stall cycles due to main TLB misses on requests issued
+ * by the instruction side
+ */
+#define XPM_EVENT_INSTRTLBSTALL 0x82
+
+/*
+ * Counts the number of stall cycles due to main TLB misses on requests issued
+ * by the data side
+ */
+#define XPM_EVENT_DATATLBSTALL 0x83
+
+/*
+ * Counts the number of stall cycles due to micro TLB misses on the instruction
+ * side. This event does not include main TLB miss stall cycles that are already
+ * counted in the corresponding main TLB event
+ */
+#define XPM_EVENT_INSTR_uTLBSTALL 0x84
+
+/*
+ * Counts the number of stall cycles due to micro TLB misses on the data side.
+ * This event does not include main TLB miss stall cycles that are already
+ * counted in the corresponding main TLB event
+ */
+#define XPM_EVENT_DATA_uTLBSTALL 0x85
+
+/*
+ * Counts the number of stall cycles because of the execution of a DMB memory
+ * barrier. This includes all DMB instructions being executed, even
+ * speculatively
+ */
+#define XPM_EVENT_DMB_STALL 0x86
+
+/*
+ * Counts the number of cycles during which the integer core clock is enabled
+ */
+#define XPM_EVENT_INT_CLKEN 0x8A
+
+/*
+ * Counts the number of cycles during which the Data Engine clock is enabled
+ */
+#define XPM_EVENT_DE_CLKEN 0x8B
+
+/*
+ * Counts the number of ISB instructions architecturally executed
+ */
+#define XPM_EVENT_INSTRISB 0x90
+
+/*
+ * Counts the number of DSB instructions architecturally executed
+ */
+#define XPM_EVENT_INSTRDSB 0x91
+
+/*
+ * Counts the number of DMB instructions speculatively executed
+ */
+#define XPM_EVENT_INSTRDMB 0x92
+
+/*
+ * Counts the number of external interrupts executed by the processor
+ */
+#define XPM_EVENT_EXTINT 0x93
+
+/*
+ * PLE cache line request completed
+ */
+#define XPM_EVENT_PLE_LRC 0xA0
+
+/*
+ * PLE cache line request skipped
+ */
+#define XPM_EVENT_PLE_LRS 0xA1
+
+/*
+ * PLE FIFO flush
+ */
+#define XPM_EVENT_PLE_FLUSH 0xA2
+
+/*
+ * PLE request complete
+ */
+#define XPM_EVENT_PLE_CMPL 0xA3
+
+/*
+ * PLE FIFO overflow
+ */
+#define XPM_EVENT_PLE_OVFL 0xA4
+
+/*
+ * PLE request programmed
+ */
+#define XPM_EVENT_PLE_PROG 0xA5
+
+/*
+ * The following constants define the configurations for Cortex-A9 Performance
+ * Monitor Events. Each configuration configures the event counters for a set
+ * of events.
+ * -----------------------------------------------
+ * Config		PmCtr0... PmCtr5
+ * -----------------------------------------------
+ * XPM_CNTRCFG1		{ XPM_EVENT_SOFTINCR,
+ *			  XPM_EVENT_INSRFETCH_CACHEREFILL,
+ *			  XPM_EVENT_INSTRFECT_TLBREFILL,
+ *			  XPM_EVENT_DATA_CACHEREFILL,
+ *			  XPM_EVENT_DATA_CACHEACCESS,
+ *			  XPM_EVENT_DATA_TLBREFILL }
+ *
+ * XPM_CNTRCFG2		{ XPM_EVENT_DATA_READS,
+ *			  XPM_EVENT_DATA_WRITE,
+ *			  XPM_EVENT_EXCEPTION,
+ *			  XPM_EVENT_EXCEPRETURN,
+ *			  XPM_EVENT_CHANGECONTEXT,
+ *			  XPM_EVENT_SW_CHANGEPC }
+ *
+ * XPM_CNTRCFG3		{ XPM_EVENT_IMMEDBRANCH,
+ *			  XPM_EVENT_UNALIGNEDACCESS,
+ *			  XPM_EVENT_BRANCHMISS,
+ *			  XPM_EVENT_CLOCKCYCLES,
+ *			  XPM_EVENT_BRANCHPREDICT,
+ *			  XPM_EVENT_JAVABYTECODE }
+ *
+ * XPM_CNTRCFG4		{ XPM_EVENT_SWJAVABYTECODE,
+ *			  XPM_EVENT_JAVABACKBRANCH,
+ *			  XPM_EVENT_COHERLINEMISS,
+ *			  XPM_EVENT_COHERLINEHIT,
+ *			  XPM_EVENT_INSTRSTALL,
+ *			  XPM_EVENT_DATASTALL }
+ *
+ * XPM_CNTRCFG5		{ XPM_EVENT_MAINTLBSTALL,
+ *			  XPM_EVENT_STREXPASS,
+ *			  XPM_EVENT_STREXFAIL,
+ *			  XPM_EVENT_DATAEVICT,
+ *			  XPM_EVENT_NODISPATCH,
+ *			  XPM_EVENT_ISSUEEMPTY }
+ *
+ * XPM_CNTRCFG6		{ XPM_EVENT_INSTRRENAME,
+ *			  XPM_EVENT_PREDICTFUNCRET,
+ *			  XPM_EVENT_MAINEXEC,
+ *			  XPM_EVENT_SECEXEC,
+ *			  XPM_EVENT_LDRSTR,
+ *			  XPM_EVENT_FLOATRENAME }
+ *
+ * XPM_CNTRCFG7		{ XPM_EVENT_NEONRENAME,
+ *			  XPM_EVENT_PLDSTALL,
+ *			  XPM_EVENT_WRITESTALL,
+ *			  XPM_EVENT_INSTRTLBSTALL,
+ *			  XPM_EVENT_DATATLBSTALL,
+ *			  XPM_EVENT_INSTR_uTLBSTALL }
+ *
+ * XPM_CNTRCFG8		{ XPM_EVENT_DATA_uTLBSTALL,
+ *			  XPM_EVENT_DMB_STALL,
+ *			  XPM_EVENT_INT_CLKEN,
+ *			  XPM_EVENT_DE_CLKEN,
+ *			  XPM_EVENT_INSTRISB,
+ *			  XPM_EVENT_INSTRDSB }
+ *
+ * XPM_CNTRCFG9		{ XPM_EVENT_INSTRDMB,
+ *			  XPM_EVENT_EXTINT,
+ *			  XPM_EVENT_PLE_LRC,
+ *			  XPM_EVENT_PLE_LRS,
+ *			  XPM_EVENT_PLE_FLUSH,
+ *			  XPM_EVENT_PLE_CMPL }
+ *
+ * XPM_CNTRCFG10	{ XPM_EVENT_PLE_OVFL,
+ *			  XPM_EVENT_PLE_PROG,
+ *			  XPM_EVENT_PLE_LRC,
+ *			  XPM_EVENT_PLE_LRS,
+ *			  XPM_EVENT_PLE_FLUSH,
+ *			  XPM_EVENT_PLE_CMPL }
+ *
+ * XPM_CNTRCFG11	{ XPM_EVENT_DATASTALL,
+ *			  XPM_EVENT_INSRFETCH_CACHEREFILL,
+ *			  XPM_EVENT_INSTRFECT_TLBREFILL,
+ *			  XPM_EVENT_DATA_CACHEREFILL,
+ *			  XPM_EVENT_DATA_CACHEACCESS,
+ *			  XPM_EVENT_DATA_TLBREFILL }
+ */
+#define XPM_CNTRCFG1	0
+#define XPM_CNTRCFG2	1
+#define XPM_CNTRCFG3	2
+#define XPM_CNTRCFG4	3
+#define XPM_CNTRCFG5	4
+#define XPM_CNTRCFG6	5
+#define XPM_CNTRCFG7	6
+#define XPM_CNTRCFG8	7
+#define XPM_CNTRCFG9	8
+#define XPM_CNTRCFG10	9
+#define XPM_CNTRCFG11	10
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/* Interface fuctions to access perfromance counters from abstraction layer */
+void Xpm_SetEvents(int PmcrCfg);
+void Xpm_GetEventCounters(u32 *PmCtrValue);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xpseudo_asm.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xpseudo_asm.h
new file mode 100644
index 000000000..22a168b72
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xpseudo_asm.h
@@ -0,0 +1,62 @@
+/*******************************************************************************
+*
+* (c) Copyright 2009-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm.h
+*
+* This header file contains macros for using inline assembler code.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  10/18/09 First release
+* 3.04a sdm  01/02/12 Remove redundant dsb in mcr instruction.
+* 

+*
+******************************************************************************/
+#include "xreg_cortexa9.h"
+#ifdef __GNUC__
+ #include "xpseudo_asm_gcc.h"
+#else
+ #include "xpseudo_asm_rvct.h"
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xpseudo_asm_gcc.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xpseudo_asm_gcc.h
new file mode 100644
index 000000000..52fac3b34
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xpseudo_asm_gcc.h
@@ -0,0 +1,183 @@
+/******************************************************************************
+*
+* (c) Copyright 2009-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm_gcc.h
+*
+* This header file contains macros for using inline assembler code. It is
+* written specifically for the GNU compiler.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  10/28/09 First release
+* 

+*
+******************************************************************************/
+
+#ifndef XPSEUDO_ASM_GCC_H  /* prevent circular inclusions */
+#define XPSEUDO_ASM_GCC_H  /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/* necessary for pre-processor */
+#define stringify(s)	tostring(s)
+#define tostring(s)	#s
+
+/* pseudo assembler instructions */
+#define mfcpsr()	({unsigned int rval; \
+			  __asm__ __volatile__(\
+			    "mrs	%0, cpsr\n"\
+			    : "=r" (rval)\
+			  );\
+			  rval;\
+			 })
+
+#define mtcpsr(v)	__asm__ __volatile__(\
+			  "msr	cpsr,%0\n"\
+			  : : "r" (v)\
+			)
+
+#define cpsiei()	__asm__ __volatile__("cpsie	i\n")
+#define cpsidi()	__asm__ __volatile__("cpsid	i\n")
+
+#define cpsief()	__asm__ __volatile__("cpsie	f\n")
+#define cpsidf()	__asm__ __volatile__("cpsid	f\n")
+
+
+
+#define mtgpr(rn, v)	__asm__ __volatile__(\
+			  "mov r" stringify(rn) ", %0 \n"\
+			  : : "r" (v)\
+			)
+
+#define mfgpr(rn)	({unsigned int rval; \
+			  __asm__ __volatile__(\
+			    "mov %0,r" stringify(rn) "\n"\
+			    : "=r" (rval)\
+			  );\
+			  rval;\
+			 })
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() __asm__ __volatile__ ("isb" : : : "memory")
+
+/* Data Synchronization Barrier */
+#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
+
+/* Data Memory Barrier */
+#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
+
+
+/* Memory Operations */
+#define ldr(adr)	({unsigned long rval; \
+			  __asm__ __volatile__(\
+			    "ldr	%0,[%1]"\
+			    : "=r" (rval) : "r" (adr)\
+			  );\
+			  rval;\
+			 })
+
+#define ldrb(adr)	({unsigned char rval; \
+			  __asm__ __volatile__(\
+			    "ldrb	%0,[%1]"\
+			    : "=r" (rval) : "r" (adr)\
+			  );\
+			  rval;\
+			 })
+
+#define str(adr, val)	__asm__ __volatile__(\
+			  "str	%0,[%1]\n"\
+			  : : "r" (val), "r" (adr)\
+			)
+
+#define strb(adr, val)	__asm__ __volatile__(\
+			  "strb	%0,[%1]\n"\
+			  : : "r" (val), "r" (adr)\
+			)
+
+/* Count leading zeroes (clz) */
+#define clz(arg)	({unsigned char rval; \
+			  __asm__ __volatile__(\
+			    "clz	%0,%1"\
+			    : "=r" (rval) : "r" (arg)\
+			  );\
+			  rval;\
+			 })
+
+/* CP15 operations */
+#define mtcp(rn, v)	__asm__ __volatile__(\
+			 "mcr " rn "\n"\
+			 : : "r" (v)\
+			);
+
+#define mfcp(rn)	({unsigned int rval; \
+			 __asm__ __volatile__(\
+			   "mrc " rn "\n"\
+			   : "=r" (rval)\
+			 );\
+			 rval;\
+			 })
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XPSEUDO_ASM_GCC_H */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xreg_cortexa9.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xreg_cortexa9.h
new file mode 100644
index 000000000..0a3a7b0fa
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xreg_cortexa9.h
@@ -0,0 +1,599 @@
+/*******************************************************************************
+*
+* (c) Copyright 2009-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xreg_cortexa9.h
+*
+* This header file contains definitions for using inline assembler code. It is
+* written specifically for the GNU, ARMCC compiler.
+*
+* All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along
+* with the positions of the bits within the registers.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  10/20/09 First release
+* 

+*
+******************************************************************************/
+#ifndef XREG_CORTEXA9_H
+#define XREG_CORTEXA9_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* GPRs */
+#define XREG_GPR0				r0
+#define XREG_GPR1				r1
+#define XREG_GPR2				r2
+#define XREG_GPR3				r3
+#define XREG_GPR4				r4
+#define XREG_GPR5				r5
+#define XREG_GPR6				r6
+#define XREG_GPR7				r7
+#define XREG_GPR8				r8
+#define XREG_GPR9				r9
+#define XREG_GPR10				r10
+#define XREG_GPR11				r11
+#define XREG_GPR12				r12
+#define XREG_GPR13				r13
+#define XREG_GPR14				r14
+#define XREG_GPR15				r15
+#define XREG_CPSR				cpsr
+
+/* Coprocessor number defines */
+#define XREG_CP0				0
+#define XREG_CP1				1
+#define XREG_CP2				2
+#define XREG_CP3				3
+#define XREG_CP4				4
+#define XREG_CP5				5
+#define XREG_CP6				6
+#define XREG_CP7				7
+#define XREG_CP8				8
+#define XREG_CP9				9
+#define XREG_CP10				10
+#define XREG_CP11				11
+#define XREG_CP12				12
+#define XREG_CP13				13
+#define XREG_CP14				14
+#define XREG_CP15				15
+
+/* Coprocessor control register defines */
+#define XREG_CR0				cr0
+#define XREG_CR1				cr1
+#define XREG_CR2				cr2
+#define XREG_CR3				cr3
+#define XREG_CR4				cr4
+#define XREG_CR5				cr5
+#define XREG_CR6				cr6
+#define XREG_CR7				cr7
+#define XREG_CR8				cr8
+#define XREG_CR9				cr9
+#define XREG_CR10				cr10
+#define XREG_CR11				cr11
+#define XREG_CR12				cr12
+#define XREG_CR13				cr13
+#define XREG_CR14				cr14
+#define XREG_CR15				cr15
+
+/* Current Processor Status Register (CPSR) Bits */
+#define XREG_CPSR_THUMB_MODE			0x20
+#define XREG_CPSR_MODE_BITS			0x1F
+#define XREG_CPSR_SYSTEM_MODE			0x1F
+#define XREG_CPSR_UNDEFINED_MODE		0x1B
+#define XREG_CPSR_DATA_ABORT_MODE		0x17
+#define XREG_CPSR_SVC_MODE			0x13
+#define XREG_CPSR_IRQ_MODE			0x12
+#define XREG_CPSR_FIQ_MODE			0x11
+#define XREG_CPSR_USER_MODE			0x10
+
+#define XREG_CPSR_IRQ_ENABLE			0x80
+#define XREG_CPSR_FIQ_ENABLE			0x40
+
+#define XREG_CPSR_N_BIT				0x80000000
+#define XREG_CPSR_Z_BIT				0x40000000
+#define XREG_CPSR_C_BIT				0x20000000
+#define XREG_CPSR_V_BIT				0x10000000
+
+
+/* CP15 defines */
+#if defined (__GNUC__)
+/* C0 Register defines */
+#define XREG_CP15_MAIN_ID			"p15, 0, %0,  c0,  c0, 0"
+#define XREG_CP15_CACHE_TYPE			"p15, 0, %0,  c0,  c0, 1"
+#define XREG_CP15_TCM_TYPE			"p15, 0, %0,  c0,  c0, 2"
+#define XREG_CP15_TLB_TYPE			"p15, 0, %0,  c0,  c0, 3"
+#define XREG_CP15_MULTI_PROC_AFFINITY		"p15, 0, %0,  c0,  c0, 5"
+
+#define XREG_CP15_PROC_FEATURE_0		"p15, 0, %0,  c0,  c1, 0"
+#define XREG_CP15_PROC_FEATURE_1		"p15, 0, %0,  c0,  c1, 1"
+#define XREG_CP15_DEBUG_FEATURE_0		"p15, 0, %0,  c0,  c1, 2"
+#define XREG_CP15_MEMORY_FEATURE_0		"p15, 0, %0,  c0,  c1, 4"
+#define XREG_CP15_MEMORY_FEATURE_1		"p15, 0, %0,  c0,  c1, 5"
+#define XREG_CP15_MEMORY_FEATURE_2		"p15, 0, %0,  c0,  c1, 6"
+#define XREG_CP15_MEMORY_FEATURE_3		"p15, 0, %0,  c0,  c1, 7"
+
+#define XREG_CP15_INST_FEATURE_0		"p15, 0, %0,  c0,  c2, 0"
+#define XREG_CP15_INST_FEATURE_1		"p15, 0, %0,  c0,  c2, 1"
+#define XREG_CP15_INST_FEATURE_2		"p15, 0, %0,  c0,  c2, 2"
+#define XREG_CP15_INST_FEATURE_3		"p15, 0, %0,  c0,  c2, 3"
+#define XREG_CP15_INST_FEATURE_4		"p15, 0, %0,  c0,  c2, 4"
+
+#define XREG_CP15_CACHE_SIZE_ID			"p15, 1, %0,  c0,  c0, 0"
+#define XREG_CP15_CACHE_LEVEL_ID		"p15, 1, %0,  c0,  c0, 1"
+#define XREG_CP15_AUXILARY_ID			"p15, 1, %0,  c0,  c0, 7"
+
+#define XREG_CP15_CACHE_SIZE_SEL		"p15, 2, %0,  c0,  c0, 0"
+
+/* C1 Register Defines */
+#define XREG_CP15_SYS_CONTROL			"p15, 0, %0,  c1,  c0, 0"
+#define XREG_CP15_AUX_CONTROL			"p15, 0, %0,  c1,  c0, 1"
+#define XREG_CP15_CP_ACCESS_CONTROL		"p15, 0, %0,  c1,  c0, 2"
+
+#define XREG_CP15_SECURE_CONFIG			"p15, 0, %0,  c1,  c1, 0"
+#define XREG_CP15_SECURE_DEBUG_ENABLE		"p15, 0, %0,  c1,  c1, 1"
+#define XREG_CP15_NS_ACCESS_CONTROL		"p15, 0, %0,  c1,  c1, 2"
+#define XREG_CP15_VIRTUAL_CONTROL		"p15, 0, %0,  c1,  c1, 3"
+
+#else /* RVCT */
+/* C0 Register defines */
+#define XREG_CP15_MAIN_ID			"cp15:0:c0:c0:0"
+#define XREG_CP15_CACHE_TYPE			"cp15:0:c0:c0:1"
+#define XREG_CP15_TCM_TYPE			"cp15:0:c0:c0:2"
+#define XREG_CP15_TLB_TYPE			"cp15:0:c0:c0:3"
+#define XREG_CP15_MULTI_PROC_AFFINITY		"cp15:0:c0:c0:5"
+
+#define XREG_CP15_PROC_FEATURE_0		"cp15:0:c0:c1:0"
+#define XREG_CP15_PROC_FEATURE_1		"cp15:0:c0:c1:1"
+#define XREG_CP15_DEBUG_FEATURE_0		"cp15:0:c0:c1:2"
+#define XREG_CP15_MEMORY_FEATURE_0		"cp15:0:c0:c1:4"
+#define XREG_CP15_MEMORY_FEATURE_1		"cp15:0:c0:c1:5"
+#define XREG_CP15_MEMORY_FEATURE_2		"cp15:0:c0:c1:6"
+#define XREG_CP15_MEMORY_FEATURE_3		"cp15:0:c0:c1:7"
+
+#define XREG_CP15_INST_FEATURE_0		"cp15:0:c0:c2:0"
+#define XREG_CP15_INST_FEATURE_1		"cp15:0:c0:c2:1"
+#define XREG_CP15_INST_FEATURE_2		"cp15:0:c0:c2:2"
+#define XREG_CP15_INST_FEATURE_3		"cp15:0:c0:c2:3"
+#define XREG_CP15_INST_FEATURE_4		"cp15:0:c0:c2:4"
+
+#define XREG_CP15_CACHE_SIZE_ID			"cp15:1:c0:c0:0"
+#define XREG_CP15_CACHE_LEVEL_ID		"cp15:1:c0:c0:1"
+#define XREG_CP15_AUXILARY_ID			"cp15:1:c0:c0:7"
+
+#define XREG_CP15_CACHE_SIZE_SEL		"cp15:2:c0:c0:0"
+
+/* C1 Register Defines */
+#define XREG_CP15_SYS_CONTROL			"cp15:0:c1:c0:0"
+#define XREG_CP15_AUX_CONTROL			"cp15:0:c1:c0:1"
+#define XREG_CP15_CP_ACCESS_CONTROL		"cp15:0:c1:c0:2"
+
+#define XREG_CP15_SECURE_CONFIG			"cp15:0:c1:c1:0"
+#define XREG_CP15_SECURE_DEBUG_ENABLE		"cp15:0:c1:c1:1"
+#define XREG_CP15_NS_ACCESS_CONTROL		"cp15:0:c1:c1:2"
+#define XREG_CP15_VIRTUAL_CONTROL		"cp15:0:c1:c1:3"
+#endif
+
+/* XREG_CP15_CONTROL bit defines */
+#define XREG_CP15_CONTROL_TE_BIT		0x40000000
+#define XREG_CP15_CONTROL_AFE_BIT		0x20000000
+#define XREG_CP15_CONTROL_TRE_BIT		0x10000000
+#define XREG_CP15_CONTROL_NMFI_BIT		0x08000000
+#define XREG_CP15_CONTROL_EE_BIT		0x02000000
+#define XREG_CP15_CONTROL_HA_BIT		0x00020000
+#define XREG_CP15_CONTROL_RR_BIT		0x00004000
+#define XREG_CP15_CONTROL_V_BIT			0x00002000
+#define XREG_CP15_CONTROL_I_BIT			0x00001000
+#define XREG_CP15_CONTROL_Z_BIT			0x00000800
+#define XREG_CP15_CONTROL_SW_BIT		0x00000400
+#define XREG_CP15_CONTROL_B_BIT			0x00000080
+#define XREG_CP15_CONTROL_C_BIT			0x00000004
+#define XREG_CP15_CONTROL_A_BIT			0x00000002
+#define XREG_CP15_CONTROL_M_BIT			0x00000001
+
+#if defined (__GNUC__)
+/* C2 Register Defines */
+#define XREG_CP15_TTBR0				"p15, 0, %0,  c2,  c0, 0"
+#define XREG_CP15_TTBR1				"p15, 0, %0,  c2,  c0, 1"
+#define XREG_CP15_TTB_CONTROL			"p15, 0, %0,  c2,  c0, 2"
+
+/* C3 Register Defines */
+#define XREG_CP15_DOMAIN_ACCESS_CTRL		"p15, 0, %0,  c3,  c0, 0"
+
+/* C4 Register Defines */
+/* Not Used */
+
+/* C5 Register Defines */
+#define XREG_CP15_DATA_FAULT_STATUS		"p15, 0, %0,  c5,  c0, 0"
+#define XREG_CP15_INST_FAULT_STATUS		"p15, 0, %0,  c5,  c0, 1"
+
+#define XREG_CP15_AUX_DATA_FAULT_STATUS		"p15, 0, %0,  c5,  c1, 0"
+#define XREG_CP15_AUX_INST_FAULT_STATUS		"p15, 0, %0,  c5,  c1, 1"
+
+/* C6 Register Defines */
+#define XREG_CP15_DATA_FAULT_ADDRESS		"p15, 0, %0,  c6,  c0, 0"
+#define XREG_CP15_INST_FAULT_ADDRESS		"p15, 0, %0,  c6,  c0, 2"
+
+/* C7 Register Defines */
+#define XREG_CP15_NOP				"p15, 0, %0,  c7,  c0, 4"
+
+#define XREG_CP15_INVAL_IC_POU_IS		"p15, 0, %0,  c7,  c1, 0"
+#define XREG_CP15_INVAL_BRANCH_ARRAY_IS		"p15, 0, %0,  c7,  c1, 6"
+
+#define XREG_CP15_PHYS_ADDR			"p15, 0, %0,  c7,  c4, 0"
+
+#define XREG_CP15_INVAL_IC_POU			"p15, 0, %0,  c7,  c5, 0"
+#define XREG_CP15_INVAL_IC_LINE_MVA_POU		"p15, 0, %0,  c7,  c5, 1"
+
+/* The CP15 register access below has been deprecated in favor of the new
+ * isb instruction in Cortex A9.
+ */
+#define XREG_CP15_INST_SYNC_BARRIER		"p15, 0, %0,  c7,  c5, 4"
+#define XREG_CP15_INVAL_BRANCH_ARRAY		"p15, 0, %0,  c7,  c5, 6"
+
+#define XREG_CP15_INVAL_DC_LINE_MVA_POC		"p15, 0, %0,  c7,  c6, 1"
+#define XREG_CP15_INVAL_DC_LINE_SW		"p15, 0, %0,  c7,  c6, 2"
+
+#define XREG_CP15_VA_TO_PA_CURRENT_0		"p15, 0, %0,  c7,  c8, 0"
+#define XREG_CP15_VA_TO_PA_CURRENT_1		"p15, 0, %0,  c7,  c8, 1"
+#define XREG_CP15_VA_TO_PA_CURRENT_2		"p15, 0, %0,  c7,  c8, 2"
+#define XREG_CP15_VA_TO_PA_CURRENT_3		"p15, 0, %0,  c7,  c8, 3"
+
+#define XREG_CP15_VA_TO_PA_OTHER_0		"p15, 0, %0,  c7,  c8, 4"
+#define XREG_CP15_VA_TO_PA_OTHER_1		"p15, 0, %0,  c7,  c8, 5"
+#define XREG_CP15_VA_TO_PA_OTHER_2		"p15, 0, %0,  c7,  c8, 6"
+#define XREG_CP15_VA_TO_PA_OTHER_3		"p15, 0, %0,  c7,  c8, 7"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POC		"p15, 0, %0,  c7, c10, 1"
+#define XREG_CP15_CLEAN_DC_LINE_SW		"p15, 0, %0,  c7, c10, 2"
+
+/* The next two CP15 register accesses below have been deprecated in favor
+ * of the new dsb and dmb instructions in Cortex A9.
+ */
+#define XREG_CP15_DATA_SYNC_BARRIER		"p15, 0, %0,  c7, c10, 4"
+#define XREG_CP15_DATA_MEMORY_BARRIER		"p15, 0, %0,  c7, c10, 5"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POU		"p15, 0, %0,  c7, c11, 1"
+
+#define XREG_CP15_NOP2				"p15, 0, %0,  c7, c13, 1"
+
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC	"p15, 0, %0,  c7, c14, 1"
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW	"p15, 0, %0,  c7, c14, 2"
+
+/* C8 Register Defines */
+#define XREG_CP15_INVAL_TLB_IS			"p15, 0, %0,  c8,  c3, 0"
+#define XREG_CP15_INVAL_TLB_MVA_IS		"p15, 0, %0,  c8,  c3, 1"
+#define XREG_CP15_INVAL_TLB_ASID_IS		"p15, 0, %0,  c8,  c3, 2"
+#define XREG_CP15_INVAL_TLB_MVA_ASID_IS		"p15, 0, %0,  c8,  c3, 3"
+
+#define XREG_CP15_INVAL_ITLB_UNLOCKED		"p15, 0, %0,  c8,  c5, 0"
+#define XREG_CP15_INVAL_ITLB_MVA		"p15, 0, %0,  c8,  c5, 1"
+#define XREG_CP15_INVAL_ITLB_ASID		"p15, 0, %0,  c8,  c5, 2"
+
+#define XREG_CP15_INVAL_DTLB_UNLOCKED		"p15, 0, %0,  c8,  c6, 0"
+#define XREG_CP15_INVAL_DTLB_MVA		"p15, 0, %0,  c8,  c6, 1"
+#define XREG_CP15_INVAL_DTLB_ASID		"p15, 0, %0,  c8,  c6, 2"
+
+#define XREG_CP15_INVAL_UTLB_UNLOCKED		"p15, 0, %0,  c8,  c7, 0"
+#define XREG_CP15_INVAL_UTLB_MVA		"p15, 0, %0,  c8,  c7, 1"
+#define XREG_CP15_INVAL_UTLB_ASID		"p15, 0, %0,  c8,  c7, 2"
+#define XREG_CP15_INVAL_UTLB_MVA_ASID		"p15, 0, %0,  c8,  c7, 3"
+
+/* C9 Register Defines */
+#define XREG_CP15_PERF_MONITOR_CTRL		"p15, 0, %0,  c9, c12, 0"
+#define XREG_CP15_COUNT_ENABLE_SET		"p15, 0, %0,  c9, c12, 1"
+#define XREG_CP15_COUNT_ENABLE_CLR		"p15, 0, %0,  c9, c12, 2"
+#define XREG_CP15_V_FLAG_STATUS			"p15, 0, %0,  c9, c12, 3"
+#define XREG_CP15_SW_INC			"p15, 0, %0,  c9, c12, 4"
+#define XREG_CP15_EVENT_CNTR_SEL		"p15, 0, %0,  c9, c12, 5"
+
+#define XREG_CP15_PERF_CYCLE_COUNTER		"p15, 0, %0,  c9, c13, 0"
+#define XREG_CP15_EVENT_TYPE_SEL		"p15, 0, %0,  c9, c13, 1"
+#define XREG_CP15_PERF_MONITOR_COUNT		"p15, 0, %0,  c9, c13, 2"
+
+#define XREG_CP15_USER_ENABLE			"p15, 0, %0,  c9, c14, 0"
+#define XREG_CP15_INTR_ENABLE_SET		"p15, 0, %0,  c9, c14, 1"
+#define XREG_CP15_INTR_ENABLE_CLR		"p15, 0, %0,  c9, c14, 2"
+
+/* C10 Register Defines */
+#define XREG_CP15_TLB_LOCKDWN			"p15, 0, %0, c10,  c0, 0"
+
+#define XREG_CP15_PRI_MEM_REMAP			"p15, 0, %0, c10,  c2, 0"
+#define XREG_CP15_NORM_MEM_REMAP		"p15, 0, %0, c10,  c2, 1"
+
+/* C11 Register Defines */
+/* Not used */
+
+/* C12 Register Defines */
+#define XREG_CP15_VEC_BASE_ADDR			"p15, 0, %0, c12,  c0, 0"
+#define XREG_CP15_MONITOR_VEC_BASE_ADDR		"p15, 0, %0, c12,  c0, 1"
+
+#define XREG_CP15_INTERRUPT_STATUS		"p15, 0, %0, c12,  c1, 0"
+#define XREG_CP15_VIRTUALIZATION_INTR		"p15, 0, %0, c12,  c1, 1"
+
+/* C13 Register Defines */
+#define XREG_CP15_CONTEXT_ID			"p15, 0, %0, c13,  c0, 1"
+#define USER_RW_THREAD_PID			"p15, 0, %0, c13,  c0, 2"
+#define USER_RO_THREAD_PID			"p15, 0, %0, c13,  c0, 3"
+#define USER_PRIV_THREAD_PID			"p15, 0, %0, c13,  c0, 4"
+
+/* C14 Register Defines */
+/* not used */
+
+/* C15 Register Defines */
+#define XREG_CP15_POWER_CTRL			"p15, 0, %0, c15,  c0, 0"
+#define XREG_CP15_CONFIG_BASE_ADDR		"p15, 4, %0, c15,  c0, 0"
+
+#define XREG_CP15_READ_TLB_ENTRY		"p15, 5, %0, c15,  c4, 2"
+#define XREG_CP15_WRITE_TLB_ENTRY		"p15, 5, %0, c15,  c4, 4"
+
+#define XREG_CP15_MAIN_TLB_VA			"p15, 5, %0, c15,  c5, 2"
+
+#define XREG_CP15_MAIN_TLB_PA			"p15, 5, %0, c15,  c6, 2"
+
+#define XREG_CP15_MAIN_TLB_ATTR			"p15, 5, %0, c15,  c7, 2"
+
+#else
+/* C2 Register Defines */
+#define XREG_CP15_TTBR0				"cp15:0:c2:c0:0"
+#define XREG_CP15_TTBR1				"cp15:0:c2:c0:1"
+#define XREG_CP15_TTB_CONTROL			"cp15:0:c2:c0:2"
+
+/* C3 Register Defines */
+#define XREG_CP15_DOMAIN_ACCESS_CTRL		"cp15:0:c3:c0:0"
+
+/* C4 Register Defines */
+/* Not Used */
+
+/* C5 Register Defines */
+#define XREG_CP15_DATA_FAULT_STATUS		"cp15:0:c5:c0:0"
+#define XREG_CP15_INST_FAULT_STATUS		"cp15:0:c5:c0:1"
+
+#define XREG_CP15_AUX_DATA_FAULT_STATUS		"cp15:0:c5:c1:0"
+#define XREG_CP15_AUX_INST_FAULT_STATUS		"cp15:0:c5:c1:1"
+
+/* C6 Register Defines */
+#define XREG_CP15_DATA_FAULT_ADDRESS		"cp15:0:c6:c0:0"
+#define XREG_CP15_INST_FAULT_ADDRESS		"cp15:0:c6:c0:2"
+
+/* C7 Register Defines */
+#define XREG_CP15_NOP				"cp15:0:c7:c0:4"
+
+#define XREG_CP15_INVAL_IC_POU_IS		"cp15:0:c7:c1:0"
+#define XREG_CP15_INVAL_BRANCH_ARRAY_IS		"cp15:0:c7:c1:6"
+
+#define XREG_CP15_PHYS_ADDR			"cp15:0:c7:c4:0"
+
+#define XREG_CP15_INVAL_IC_POU			"cp15:0:c7:c5:0"
+#define XREG_CP15_INVAL_IC_LINE_MVA_POU		"cp15:0:c7:c5:1"
+
+/* The CP15 register access below has been deprecated in favor of the new
+ * isb instruction in Cortex A9.
+ */
+#define XREG_CP15_INST_SYNC_BARRIER		"cp15:0:c7:c5:4"
+#define XREG_CP15_INVAL_BRANCH_ARRAY		"cp15:0:c7:c5:6"
+
+#define XREG_CP15_INVAL_DC_LINE_MVA_POC		"cp15:0:c7:c6:1"
+#define XREG_CP15_INVAL_DC_LINE_SW		"cp15:0:c7:c6:2"
+
+#define XREG_CP15_VA_TO_PA_CURRENT_0		"cp15:0:c7:c8:0"
+#define XREG_CP15_VA_TO_PA_CURRENT_1		"cp15:0:c7:c8:1"
+#define XREG_CP15_VA_TO_PA_CURRENT_2		"cp15:0:c7:c8:2"
+#define XREG_CP15_VA_TO_PA_CURRENT_3		"cp15:0:c7:c8:3"
+
+#define XREG_CP15_VA_TO_PA_OTHER_0		"cp15:0:c7:c8:4"
+#define XREG_CP15_VA_TO_PA_OTHER_1		"cp15:0:c7:c8:5"
+#define XREG_CP15_VA_TO_PA_OTHER_2		"cp15:0:c7:c8:6"
+#define XREG_CP15_VA_TO_PA_OTHER_3		"cp15:0:c7:c8:7"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POC		"cp15:0:c7:c10:1"
+#define XREG_CP15_CLEAN_DC_LINE_SW		"cp15:0:c7:c10:2"
+
+/* The next two CP15 register accesses below have been deprecated in favor
+ * of the new dsb and dmb instructions in Cortex A9.
+ */
+#define XREG_CP15_DATA_SYNC_BARRIER		"cp15:0:c7:c10:4"
+#define XREG_CP15_DATA_MEMORY_BARRIER		"cp15:0:c7:c10:5"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POU		"cp15:0:c7:c11:1"
+
+#define XREG_CP15_NOP2				"cp15:0:c7:c13:1"
+
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC	"cp15:0:c7:c14:1"
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW	"cp15:0:c7:c14:2"
+
+/* C8 Register Defines */
+#define XREG_CP15_INVAL_TLB_IS			"cp15:0:c8:c3:0"
+#define XREG_CP15_INVAL_TLB_MVA_IS		"cp15:0:c8:c3:1"
+#define XREG_CP15_INVAL_TLB_ASID_IS		"cp15:0:c8:c3:2"
+#define XREG_CP15_INVAL_TLB_MVA_ASID_IS		"cp15:0:c8:c3:3"
+
+#define XREG_CP15_INVAL_ITLB_UNLOCKED		"cp15:0:c8:c5:0"
+#define XREG_CP15_INVAL_ITLB_MVA		"cp15:0:c8:c5:1"
+#define XREG_CP15_INVAL_ITLB_ASID		"cp15:0:c8:c5:2"
+
+#define XREG_CP15_INVAL_DTLB_UNLOCKED		"cp15:0:c8:c6:0"
+#define XREG_CP15_INVAL_DTLB_MVA		"cp15:0:c8:c6:1"
+#define XREG_CP15_INVAL_DTLB_ASID		"cp15:0:c8:c6:2"
+
+#define XREG_CP15_INVAL_UTLB_UNLOCKED		"cp15:0:c8:c7:0"
+#define XREG_CP15_INVAL_UTLB_MVA		"cp15:0:c8:c7:1"
+#define XREG_CP15_INVAL_UTLB_ASID		"cp15:0:c8:c7:2"
+#define XREG_CP15_INVAL_UTLB_MVA_ASID		"cp15:0:c8:c7:3"
+
+/* C9 Register Defines */
+#define XREG_CP15_PERF_MONITOR_CTRL		"cp15:0:c9:c12:0"
+#define XREG_CP15_COUNT_ENABLE_SET		"cp15:0:c9:c12:1"
+#define XREG_CP15_COUNT_ENABLE_CLR		"cp15:0:c9:c12:2"
+#define XREG_CP15_V_FLAG_STATUS			"cp15:0:c9:c12:3"
+#define XREG_CP15_SW_INC			"cp15:0:c9:c12:4"
+#define XREG_CP15_EVENT_CNTR_SEL		"cp15:0:c9:c12:5"
+
+#define XREG_CP15_PERF_CYCLE_COUNTER		"cp15:0:c9:c13:0"
+#define XREG_CP15_EVENT_TYPE_SEL		"cp15:0:c9:c13:1"
+#define XREG_CP15_PERF_MONITOR_COUNT		"cp15:0:c9:c13:2"
+
+#define XREG_CP15_USER_ENABLE			"cp15:0:c9:c14:0"
+#define XREG_CP15_INTR_ENABLE_SET		"cp15:0:c9:c14:1"
+#define XREG_CP15_INTR_ENABLE_CLR		"cp15:0:c9:c14:2"
+
+/* C10 Register Defines */
+#define XREG_CP15_TLB_LOCKDWN			"cp15:0:c10:c0:0"
+
+#define XREG_CP15_PRI_MEM_REMAP			"cp15:0:c10:c2:0"
+#define XREG_CP15_NORM_MEM_REMAP		"cp15:0:c10:c2:1"
+
+/* C11 Register Defines */
+/* Not used */
+
+/* C12 Register Defines */
+#define XREG_CP15_VEC_BASE_ADDR			"cp15:0:c12:c0:0"
+#define XREG_CP15_MONITOR_VEC_BASE_ADDR		"cp15:0:c12:c0:1"
+
+#define XREG_CP15_INTERRUPT_STATUS		"cp15:0:c12:c1:0"
+#define XREG_CP15_VIRTUALIZATION_INTR		"cp15:0:c12:c1:1"
+
+/* C13 Register Defines */
+#define XREG_CP15_CONTEXT_ID			"cp15:0:c13:c0:1"
+#define USER_RW_THREAD_PID			"cp15:0:c13:c0:2"
+#define USER_RO_THREAD_PID			"cp15:0:c13:c0:3"
+#define USER_PRIV_THREAD_PID			"cp15:0:c13:c0:4"
+
+/* C14 Register Defines */
+/* not used */
+
+/* C15 Register Defines */
+#define XREG_CP15_POWER_CTRL			"cp15:0:c15:c0:0"
+#define XREG_CP15_CONFIG_BASE_ADDR		"cp15:4:c15:c0:0"
+
+#define XREG_CP15_READ_TLB_ENTRY		"cp15:5:c15:c4:2"
+#define XREG_CP15_WRITE_TLB_ENTRY		"cp15:5:c15:c4:4"
+
+#define XREG_CP15_MAIN_TLB_VA			"cp15:5:c15:c5:2"
+
+#define XREG_CP15_MAIN_TLB_PA			"cp15:5:c15:c6:2"
+
+#define XREG_CP15_MAIN_TLB_ATTR			"cp15:5:c15:c7:2"
+#endif
+
+
+/* MPE register definitions */
+#define XREG_FPSID				c0
+#define XREG_FPSCR				c1
+#define XREG_MVFR1				c6
+#define XREG_MVFR0				c7
+#define XREG_FPEXC				c8
+#define XREG_FPINST				c9
+#define XREG_FPINST2				c10
+
+/* FPSID bits */
+#define XREG_FPSID_IMPLEMENTER_BIT	(24)
+#define XREG_FPSID_IMPLEMENTER_MASK	(0xFF << FPSID_IMPLEMENTER_BIT)
+#define XREG_FPSID_SOFTWARE		(1<<23)
+#define XREG_FPSID_ARCH_BIT		(16)
+#define XREG_FPSID_ARCH_MASK		(0xF  << FPSID_ARCH_BIT)
+#define XREG_FPSID_PART_BIT		(8)
+#define XREG_FPSID_PART_MASK		(0xFF << FPSID_PART_BIT)
+#define XREG_FPSID_VARIANT_BIT		(4)
+#define XREG_FPSID_VARIANT_MASK		(0xF  << FPSID_VARIANT_BIT)
+#define XREG_FPSID_REV_BIT		(0)
+#define XREG_FPSID_REV_MASK		(0xF  << FPSID_REV_BIT)
+
+/* FPSCR bits */
+#define XREG_FPSCR_N_BIT		(1 << 31)
+#define XREG_FPSCR_Z_BIT		(1 << 30)
+#define XREG_FPSCR_C_BIT		(1 << 29)
+#define XREG_FPSCR_V_BIT		(1 << 28)
+#define XREG_FPSCR_QC			(1 << 27)
+#define XREG_FPSCR_AHP			(1 << 26)
+#define XREG_FPSCR_DEFAULT_NAN		(1 << 25)
+#define XREG_FPSCR_FLUSHTOZERO		(1 << 24)
+#define XREG_FPSCR_ROUND_NEAREST	(0 << 22)
+#define XREG_FPSCR_ROUND_PLUSINF	(1 << 22)
+#define XREG_FPSCR_ROUND_MINUSINF	(2 << 22)
+#define XREG_FPSCR_ROUND_TOZERO		(3 << 22)
+#define XREG_FPSCR_RMODE_BIT		(22)
+#define XREG_FPSCR_RMODE_MASK		(3 << FPSCR_RMODE_BIT)
+#define XREG_FPSCR_STRIDE_BIT		(20)
+#define XREG_FPSCR_STRIDE_MASK		(3 << FPSCR_STRIDE_BIT)
+#define XREG_FPSCR_LENGTH_BIT		(16)
+#define XREG_FPSCR_LENGTH_MASK		(7 << FPSCR_LENGTH_BIT)
+#define XREG_FPSCR_IDC			(1 << 7)
+#define XREG_FPSCR_IXC			(1 << 4)
+#define XREG_FPSCR_UFC			(1 << 3)
+#define XREG_FPSCR_OFC			(1 << 2)
+#define XREG_FPSCR_DZC			(1 << 1)
+#define XREG_FPSCR_IOC			(1 << 0)
+
+/* MVFR0 bits */
+#define XREG_MVFR0_RMODE_BIT		(28)
+#define XREG_MVFR0_RMODE_MASK		(0xF << XREG_MVFR0_RMODE_BIT)
+#define XREG_MVFR0_SHORT_VEC_BIT	(24)
+#define XREG_MVFR0_SHORT_VEC_MASK	(0xF << XREG_MVFR0_SHORT_VEC_BIT)
+#define XREG_MVFR0_SQRT_BIT		(20)
+#define XREG_MVFR0_SQRT_MASK		(0xF << XREG_MVFR0_SQRT_BIT)
+#define XREG_MVFR0_DIVIDE_BIT		(16)
+#define XREG_MVFR0_DIVIDE_MASK		(0xF << XREG_MVFR0_DIVIDE_BIT)
+#define XREG_MVFR0_EXEC_TRAP_BIT	(12)
+#define XREG_MVFR0_EXEC_TRAP_MASK	(0xF << XREG_MVFR0_EXEC_TRAP_BIT)
+#define XREG_MVFR0_DP_BIT		(8)
+#define XREG_MVFR0_DP_MASK		(0xF << XREG_MVFR0_DP_BIT)
+#define XREG_MVFR0_SP_BIT		(4)
+#define XREG_MVFR0_SP_MASK		(0xF << XREG_MVFR0_SP_BIT)
+#define XREG_MVFR0_A_SIMD_BIT		(0)
+#define XREG_MVFR0_A_SIMD_MASK		(0xF << MVFR0_A_SIMD_BIT)
+
+/* FPEXC bits */
+#define XREG_FPEXC_EX			(1 << 31)
+#define XREG_FPEXC_EN			(1 << 30)
+#define XREG_FPEXC_DEX			(1 << 29)
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XREG_CORTEXA9_H */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xstatus.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xstatus.h
new file mode 100644
index 000000000..76d2a94c7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xstatus.h
@@ -0,0 +1,439 @@
+/******************************************************************************
+*
+* (c) Copyright 2002-2013  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xstatus.h
+*
+* This file contains Xilinx software status codes.  Status codes have their
+* own data type called int.  These codes are used throughout the Xilinx
+* device drivers.
+*
+******************************************************************************/
+
+#ifndef XSTATUS_H		/* prevent circular inclusions */
+#define XSTATUS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/*********************** Common statuses 0 - 500 *****************************/
+
+#define XST_SUCCESS                     0L
+#define XST_FAILURE                     1L
+#define XST_DEVICE_NOT_FOUND            2L
+#define XST_DEVICE_BLOCK_NOT_FOUND      3L
+#define XST_INVALID_VERSION             4L
+#define XST_DEVICE_IS_STARTED           5L
+#define XST_DEVICE_IS_STOPPED           6L
+#define XST_FIFO_ERROR                  7L	/* an error occurred during an
+						   operation with a FIFO such as
+						   an underrun or overrun, this
+						   error requires the device to
+						   be reset */
+#define XST_RESET_ERROR                 8L	/* an error occurred which requires
+						   the device to be reset */
+#define XST_DMA_ERROR                   9L	/* a DMA error occurred, this error
+						   typically requires the device
+						   using the DMA to be reset */
+#define XST_NOT_POLLED                  10L	/* the device is not configured for
+						   polled mode operation */
+#define XST_FIFO_NO_ROOM                11L	/* a FIFO did not have room to put
+						   the specified data into */
+#define XST_BUFFER_TOO_SMALL            12L	/* the buffer is not large enough
+						   to hold the expected data */
+#define XST_NO_DATA                     13L	/* there was no data available */
+#define XST_REGISTER_ERROR              14L	/* a register did not contain the
+						   expected value */
+#define XST_INVALID_PARAM               15L	/* an invalid parameter was passed
+						   into the function */
+#define XST_NOT_SGDMA                   16L	/* the device is not configured for
+						   scatter-gather DMA operation */
+#define XST_LOOPBACK_ERROR              17L	/* a loopback test failed */
+#define XST_NO_CALLBACK                 18L	/* a callback has not yet been
+						   registered */
+#define XST_NO_FEATURE                  19L	/* device is not configured with
+						   the requested feature */
+#define XST_NOT_INTERRUPT               20L	/* device is not configured for
+						   interrupt mode operation */
+#define XST_DEVICE_BUSY                 21L	/* device is busy */
+#define XST_ERROR_COUNT_MAX             22L	/* the error counters of a device
+						   have maxed out */
+#define XST_IS_STARTED                  23L	/* used when part of device is
+						   already started i.e.
+						   sub channel */
+#define XST_IS_STOPPED                  24L	/* used when part of device is
+						   already stopped i.e.
+						   sub channel */
+#define XST_DATA_LOST                   26L	/* driver defined error */
+#define XST_RECV_ERROR                  27L	/* generic receive error */
+#define XST_SEND_ERROR                  28L	/* generic transmit error */
+#define XST_NOT_ENABLED                 29L	/* a requested service is not
+						   available because it has not
+						   been enabled */
+
+/***************** Utility Component statuses 401 - 500  *********************/
+
+#define XST_MEMTEST_FAILED              401L	/* memory test failed */
+
+
+/***************** Common Components statuses 501 - 1000 *********************/
+
+/********************* Packet Fifo statuses 501 - 510 ************************/
+
+#define XST_PFIFO_LACK_OF_DATA          501L	/* not enough data in FIFO   */
+#define XST_PFIFO_NO_ROOM               502L	/* not enough room in FIFO   */
+#define XST_PFIFO_BAD_REG_VALUE         503L	/* self test, a register value
+						   was invalid after reset */
+#define XST_PFIFO_ERROR                 504L	/* generic packet FIFO error */
+#define XST_PFIFO_DEADLOCK              505L	/* packet FIFO is reporting
+						 * empty and full simultaneously
+						 */
+
+/************************** DMA statuses 511 - 530 ***************************/
+
+#define XST_DMA_TRANSFER_ERROR          511L	/* self test, DMA transfer
+						   failed */
+#define XST_DMA_RESET_REGISTER_ERROR    512L	/* self test, a register value
+						   was invalid after reset */
+#define XST_DMA_SG_LIST_EMPTY           513L	/* scatter gather list contains
+						   no buffer descriptors ready
+						   to be processed */
+#define XST_DMA_SG_IS_STARTED           514L	/* scatter gather not stopped */
+#define XST_DMA_SG_IS_STOPPED           515L	/* scatter gather not running */
+#define XST_DMA_SG_LIST_FULL            517L	/* all the buffer desciptors of
+						   the scatter gather list are
+						   being used */
+#define XST_DMA_SG_BD_LOCKED            518L	/* the scatter gather buffer
+						   descriptor which is to be
+						   copied over in the scatter
+						   list is locked */
+#define XST_DMA_SG_NOTHING_TO_COMMIT    519L	/* no buffer descriptors have been
+						   put into the scatter gather
+						   list to be commited */
+#define XST_DMA_SG_COUNT_EXCEEDED       521L	/* the packet count threshold
+						   specified was larger than the
+						   total # of buffer descriptors
+						   in the scatter gather list */
+#define XST_DMA_SG_LIST_EXISTS          522L	/* the scatter gather list has
+						   already been created */
+#define XST_DMA_SG_NO_LIST              523L	/* no scatter gather list has
+						   been created */
+#define XST_DMA_SG_BD_NOT_COMMITTED     524L	/* the buffer descriptor which was
+						   being started was not committed
+						   to the list */
+#define XST_DMA_SG_NO_DATA              525L	/* the buffer descriptor to start
+						   has already been used by the
+						   hardware so it can't be reused
+						 */
+#define XST_DMA_SG_LIST_ERROR           526L	/* general purpose list access
+						   error */
+#define XST_DMA_BD_ERROR                527L	/* general buffer descriptor
+						   error */
+
+/************************** IPIF statuses 531 - 550 ***************************/
+
+#define XST_IPIF_REG_WIDTH_ERROR        531L	/* an invalid register width
+						   was passed into the function */
+#define XST_IPIF_RESET_REGISTER_ERROR   532L	/* the value of a register at
+						   reset was not valid */
+#define XST_IPIF_DEVICE_STATUS_ERROR    533L	/* a write to the device interrupt
+						   status register did not read
+						   back correctly */
+#define XST_IPIF_DEVICE_ACK_ERROR       534L	/* the device interrupt status
+						   register did not reset when
+						   acked */
+#define XST_IPIF_DEVICE_ENABLE_ERROR    535L	/* the device interrupt enable
+						   register was not updated when
+						   other registers changed */
+#define XST_IPIF_IP_STATUS_ERROR        536L	/* a write to the IP interrupt
+						   status register did not read
+						   back correctly */
+#define XST_IPIF_IP_ACK_ERROR           537L	/* the IP interrupt status register
+						   did not reset when acked */
+#define XST_IPIF_IP_ENABLE_ERROR        538L	/* IP interrupt enable register was
+						   not updated correctly when other
+						   registers changed */
+#define XST_IPIF_DEVICE_PENDING_ERROR   539L	/* The device interrupt pending
+						   register did not indicate the
+						   expected value */
+#define XST_IPIF_DEVICE_ID_ERROR        540L	/* The device interrupt ID register
+						   did not indicate the expected
+						   value */
+#define XST_IPIF_ERROR                  541L	/* generic ipif error */
+
+/****************** Device specific statuses 1001 - 4095 *********************/
+
+/********************* Ethernet statuses 1001 - 1050 *************************/
+
+#define XST_EMAC_MEMORY_SIZE_ERROR  1001L	/* Memory space is not big enough
+						 * to hold the minimum number of
+						 * buffers or descriptors */
+#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L	/* Memory allocation failed */
+#define XST_EMAC_MII_READ_ERROR     1003L	/* MII read error */
+#define XST_EMAC_MII_BUSY           1004L	/* An MII operation is in progress */
+#define XST_EMAC_OUT_OF_BUFFERS     1005L	/* Driver is out of buffers */
+#define XST_EMAC_PARSE_ERROR        1006L	/* Invalid driver init string */
+#define XST_EMAC_COLLISION_ERROR    1007L	/* Excess deferral or late
+						 * collision on polled send */
+
+/*********************** UART statuses 1051 - 1075 ***************************/
+#define XST_UART
+
+#define XST_UART_INIT_ERROR         1051L
+#define XST_UART_START_ERROR        1052L
+#define XST_UART_CONFIG_ERROR       1053L
+#define XST_UART_TEST_FAIL          1054L
+#define XST_UART_BAUD_ERROR         1055L
+#define XST_UART_BAUD_RANGE         1056L
+
+
+/************************ IIC statuses 1076 - 1100 ***************************/
+
+#define XST_IIC_SELFTEST_FAILED         1076	/* self test failed            */
+#define XST_IIC_BUS_BUSY                1077	/* bus found busy              */
+#define XST_IIC_GENERAL_CALL_ADDRESS    1078	/* mastersend attempted with   */
+					     /* general call address        */
+#define XST_IIC_STAND_REG_RESET_ERROR   1079	/* A non parameterizable reg   */
+					     /* value after reset not valid */
+#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080	/* Tx fifo included in design  */
+					     /* value after reset not valid */
+#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081	/* Rx fifo included in design  */
+					     /* value after reset not valid */
+#define XST_IIC_TBA_REG_RESET_ERROR     1082	/* 10 bit addr incl in design  */
+					     /* value after reset not valid */
+#define XST_IIC_CR_READBACK_ERROR       1083	/* Read of the control register */
+					     /* didn't return value written */
+#define XST_IIC_DTR_READBACK_ERROR      1084	/* Read of the data Tx reg     */
+					     /* didn't return value written */
+#define XST_IIC_DRR_READBACK_ERROR      1085	/* Read of the data Receive reg */
+					     /* didn't return value written */
+#define XST_IIC_ADR_READBACK_ERROR      1086	/* Read of the data Tx reg     */
+					     /* didn't return value written */
+#define XST_IIC_TBA_READBACK_ERROR      1087	/* Read of the 10 bit addr reg */
+					     /* didn't return written value */
+#define XST_IIC_NOT_SLAVE               1088	/* The device isn't a slave    */
+
+/*********************** ATMC statuses 1101 - 1125 ***************************/
+
+#define XST_ATMC_ERROR_COUNT_MAX    1101L	/* the error counters in the ATM
+						   controller hit the max value
+						   which requires the statistics
+						   to be cleared */
+
+/*********************** Flash statuses 1126 - 1150 **************************/
+
+#define XST_FLASH_BUSY                1126L	/* Flash is erasing or programming
+						 */
+#define XST_FLASH_READY               1127L	/* Flash is ready for commands */
+#define XST_FLASH_ERROR               1128L	/* Flash had detected an internal
+						   error. Use XFlash_DeviceControl
+						   to retrieve device specific codes
+						 */
+#define XST_FLASH_ERASE_SUSPENDED     1129L	/* Flash is in suspended erase state
+						 */
+#define XST_FLASH_WRITE_SUSPENDED     1130L	/* Flash is in suspended write state
+						 */
+#define XST_FLASH_PART_NOT_SUPPORTED  1131L	/* Flash type not supported by
+						   driver */
+#define XST_FLASH_NOT_SUPPORTED       1132L	/* Operation not supported */
+#define XST_FLASH_TOO_MANY_REGIONS    1133L	/* Too many erase regions */
+#define XST_FLASH_TIMEOUT_ERROR       1134L	/* Programming or erase operation
+						   aborted due to a timeout */
+#define XST_FLASH_ADDRESS_ERROR       1135L	/* Accessed flash outside its
+						   addressible range */
+#define XST_FLASH_ALIGNMENT_ERROR     1136L	/* Write alignment error */
+#define XST_FLASH_BLOCKING_CALL_ERROR 1137L	/* Couldn't return immediately from
+						   write/erase function with
+						   XFL_NON_BLOCKING_WRITE/ERASE
+						   option cleared */
+#define XST_FLASH_CFI_QUERY_ERROR     1138L	/* Failed to query the device */
+
+/*********************** SPI statuses 1151 - 1175 ****************************/
+
+#define XST_SPI_MODE_FAULT          1151	/* master was selected as slave */
+#define XST_SPI_TRANSFER_DONE       1152	/* data transfer is complete */
+#define XST_SPI_TRANSMIT_UNDERRUN   1153	/* slave underruns transmit register */
+#define XST_SPI_RECEIVE_OVERRUN     1154	/* device overruns receive register */
+#define XST_SPI_NO_SLAVE            1155	/* no slave has been selected yet */
+#define XST_SPI_TOO_MANY_SLAVES     1156	/* more than one slave is being
+						 * selected */
+#define XST_SPI_NOT_MASTER          1157	/* operation is valid only as master */
+#define XST_SPI_SLAVE_ONLY          1158	/* device is configured as slave-only
+						 */
+#define XST_SPI_SLAVE_MODE_FAULT    1159	/* slave was selected while disabled */
+#define XST_SPI_SLAVE_MODE          1160	/* device has been addressed as slave */
+#define XST_SPI_RECEIVE_NOT_EMPTY   1161	/* device received data in slave mode */
+
+#define XST_SPI_COMMAND_ERROR       1162	/* unrecognised command - qspi only */
+
+/********************** OPB Arbiter statuses 1176 - 1200 *********************/
+
+#define XST_OPBARB_INVALID_PRIORITY  1176	/* the priority registers have either
+						 * one master assigned to two or more
+						 * priorities, or one master not
+						 * assigned to any priority
+						 */
+#define XST_OPBARB_NOT_SUSPENDED     1177	/* an attempt was made to modify the
+						 * priority levels without first
+						 * suspending the use of priority
+						 * levels
+						 */
+#define XST_OPBARB_PARK_NOT_ENABLED  1178	/* bus parking by id was enabled but
+						 * bus parking was not enabled
+						 */
+#define XST_OPBARB_NOT_FIXED_PRIORITY 1179	/* the arbiter must be in fixed
+						 * priority mode to allow the
+						 * priorities to be changed
+						 */
+
+/************************ Intc statuses 1201 - 1225 **************************/
+
+#define XST_INTC_FAIL_SELFTEST      1201	/* self test failed */
+#define XST_INTC_CONNECT_ERROR      1202	/* interrupt already in use */
+
+/********************** TmrCtr statuses 1226 - 1250 **************************/
+
+#define XST_TMRCTR_TIMER_FAILED     1226	/* self test failed */
+
+/********************** WdtTb statuses 1251 - 1275 ***************************/
+
+#define XST_WDTTB_TIMER_FAILED      1251L
+
+/********************** PlbArb statuses 1276 - 1300 **************************/
+
+#define XST_PLBARB_FAIL_SELFTEST    1276L
+
+/********************** Plb2Opb statuses 1301 - 1325 *************************/
+
+#define XST_PLB2OPB_FAIL_SELFTEST   1301L
+
+/********************** Opb2Plb statuses 1326 - 1350 *************************/
+
+#define XST_OPB2PLB_FAIL_SELFTEST   1326L
+
+/********************** SysAce statuses 1351 - 1360 **************************/
+
+#define XST_SYSACE_NO_LOCK          1351L	/* No MPU lock has been granted */
+
+/********************** PCI Bridge statuses 1361 - 1375 **********************/
+
+#define XST_PCI_INVALID_ADDRESS     1361L
+
+/********************** FlexRay constants 1400 - 1409 *************************/
+
+#define XST_FR_TX_ERROR			1400
+#define XST_FR_TX_BUSY			1401
+#define XST_FR_BUF_LOCKED		1402
+#define XST_FR_NO_BUF			1403
+
+/****************** USB constants 1410 - 1420  *******************************/
+
+#define XST_USB_ALREADY_CONFIGURED	1410
+#define XST_USB_BUF_ALIGN_ERROR		1411
+#define XST_USB_NO_DESC_AVAILABLE	1412
+#define XST_USB_BUF_TOO_BIG		1413
+#define XST_USB_NO_BUF			1414
+
+/****************** HWICAP constants 1421 - 1429  *****************************/
+
+#define XST_HWICAP_WRITE_DONE		1421
+
+
+/****************** AXI VDMA constants 1430 - 1440  *****************************/
+
+#define XST_VDMA_MISMATCH_ERROR		1430
+
+/*********************** NAND Flash statuses 1441 - 1459  *********************/
+
+#define XST_NAND_BUSY			1441L	/* Flash is erasing or
+						 * programming
+						 */
+#define XST_NAND_READY			1442L	/* Flash is ready for commands
+						 */
+#define XST_NAND_ERROR			1443L	/* Flash had detected an
+						 * internal error.
+						 */
+#define XST_NAND_PART_NOT_SUPPORTED	1444L	/* Flash type not supported by
+						 * driver
+						 */
+#define XST_NAND_OPT_NOT_SUPPORTED	1445L	/* Operation not supported
+						 */
+#define XST_NAND_TIMEOUT_ERROR		1446L	/* Programming or erase
+						 * operation aborted due to a
+						 * timeout
+						 */
+#define XST_NAND_ADDRESS_ERROR		1447L	/* Accessed flash outside its
+						 * addressible range
+						 */
+#define XST_NAND_ALIGNMENT_ERROR	1448L	/* Write alignment error
+						 */
+#define XST_NAND_PARAM_PAGE_ERROR	1449L	/* Failed to read parameter
+						 * page of the device
+						 */
+#define XST_NAND_CACHE_ERROR		1450L	/* Flash page buffer error
+						 */
+
+#define XST_NAND_WRITE_PROTECTED	1451L	/* Flash is write protected
+						 */
+
+/**************************** Type Definitions *******************************/
+
+typedef int XStatus;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xtime_l.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xtime_l.c
new file mode 100644
index 000000000..723d19acf
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xtime_l.c
@@ -0,0 +1,129 @@
+/******************************************************************************
+*
+* (c) Copyright 2009-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xtime_l.c
+*
+* This file contains low level functions to get/set time from the Global Timer
+* register in the ARM Cortex A9 MP core.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 1.00a rp/sdm 11/03/09 Initial release.
+* 3.07a sgd    07/05/12 Upadted get/set time functions to make use Global Timer
+* 

+*
+* @note		None.
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "xtime_l.h"
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+/****************************************************************************
+*
+* Set the time in the Global Timer Counter Register.
+*
+* @param	Value to be written to the Global Timer Counter Register.
+*
+* @return	None.
+*
+* @note		In multiprocessor environment reference time will reset/lost for
+*		all processors, when this function called by any one processor.
+*
+****************************************************************************/
+void XTime_SetTime(XTime Xtime)
+{
+	/* Disable Global Timer */
+	Xil_Out32(GLOBAL_TMR_BASEADDR + GTIMER_CONTROL_OFFSET, 0x0);
+
+	/* Updating Global Timer Counter Register */
+	Xil_Out32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_LOWER_OFFSET, (u32)Xtime);
+	Xil_Out32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET,
+		(u32)(Xtime>>32));
+
+	/* Enable Global Timer */
+	Xil_Out32(GLOBAL_TMR_BASEADDR + GTIMER_CONTROL_OFFSET, 0x1);
+}
+
+/****************************************************************************
+*
+* Get the time from the Global Timer Counter Register.
+*
+* @param	Pointer to the location to be updated with the time.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XTime_GetTime(XTime *Xtime)
+{
+	u32 low;
+	u32 high;
+
+	/* Reading Global Timer Counter Register */
+	do
+	{
+		high = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET);
+		low = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_LOWER_OFFSET);
+	} while(Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET) != high);
+
+	*Xtime = (((XTime) high) << 32) | (XTime) low;
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xtime_l.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xtime_l.h
new file mode 100644
index 000000000..e6550d3ce
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v4_1/src/xtime_l.h
@@ -0,0 +1,96 @@
+/******************************************************************************
+*
+* (c) Copyright 2009-13  Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xtime_l.h
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 1.00a rp/sdm 11/03/09 Initial release.
+* 3.06a sgd    05/15/12 Upadted get/set time functions to make use Global Timer
+* 3.06a asa    06/17/12 Reverted back the changes to make use Global Timer.
+* 3.07a sgd    07/05/12 Upadted get/set time functions to make use Global Timer
+* 

+*
+* @note		None.
+*
+******************************************************************************/
+
+#ifndef XTIME_H /* prevent circular inclusions */
+#define XTIME_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xparameters.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+typedef unsigned long long XTime;
+
+/************************** Constant Definitions *****************************/
+#define GLOBAL_TMR_BASEADDR               XPAR_GLOBAL_TMR_BASEADDR
+#define GTIMER_COUNTER_LOWER_OFFSET       0x00
+#define GTIMER_COUNTER_UPPER_OFFSET       0x04
+#define GTIMER_CONTROL_OFFSET             0x08
+
+
+/* Global Timer is always clocked at half of the CPU frequency */
+#define COUNTS_PER_SECOND          (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2)
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void XTime_SetTime(XTime Xtime);
+void XTime_GetTime(XTime *Xtime);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XTIME_H */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v2_0/src/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v2_0/src/Makefile
new file mode 100644
index 000000000..49cc5b517
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v2_0/src/Makefile
@@ -0,0 +1,41 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner ttcps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling ttcps"
+
+ttcps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: ttcps_includes
+
+ttcps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v2_0/src/xttcps.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v2_0/src/xttcps.c
new file mode 100644
index 000000000..7200f74fd
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v2_0/src/xttcps.c
@@ -0,0 +1,434 @@
+/* $Id: xttcps.c,v 1.1.2.1 2011/01/20 04:08:59 sadanan Exp $ */
+/******************************************************************************
+*
+* (c) Copyright 2010 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps.c
+*
+* This file contains the implementation of the XTtcPs driver. This driver
+* controls the operation of one timer counter in the Triple Timer Counter (TTC)
+* module in the Ps block. Refer to xttcps.h for more detailed description
+* of the driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -------------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xttcps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XTtcPs instance such that the driver is ready to use.
+* This function initializes a single timer counter in the triple timer counter
+* function block.
+*
+* The state of the device after initialization is:
+*  - Overflow Mode
+*  - Internal (pclk) selected
+*  - Counter disabled
+*  - All Interrupts disabled
+*  - Output waveforms disabled
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	ConfigPtr is a reference to a structure containing information
+*		about a specific TTC device.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, then use
+*		ConfigPtr->BaseAddress for this parameter, passing the physical
+*		address instead.
+*
+* @return
+*
+* 		- XST_SUCCESS if the initialization is successful.
+*		- XST_DEVICE_IS_STARTED if the device is started. It must be
+*		  stopped to re-initialize.
+*
+* @note		Device has to be stopped first to call this function to
+*		initialize it.
+*
+******************************************************************************/
+int XTtcPs_CfgInitialize(XTtcPs *InstancePtr, XTtcPs_Config *ConfigPtr,
+			      u32 EffectiveAddr)
+{
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * Set some default values
+	 */
+	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+	InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
+
+	/*
+	 * If the timer counter has already started, return an error
+	 * Device should be stopped first.
+	 */
+	if(XTtcPs_IsStarted(InstancePtr)) {
+		return XST_DEVICE_IS_STARTED;
+	}
+
+	/*
+	 * Reset the count control register to it's default value.
+	 */
+	XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XTTCPS_CNT_CNTRL_OFFSET,
+			  XTTCPS_CNT_CNTRL_RESET_VALUE);
+
+	/*
+	 * Reset the rest of the registers to the default values.
+	 */
+	XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XTTCPS_CLK_CNTRL_OFFSET, 0x00);
+	XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XTTCPS_INTERVAL_VAL_OFFSET, 0x00);
+	XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XTTCPS_MATCH_1_OFFSET, 0x00);
+	XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XTTCPS_MATCH_2_OFFSET, 0x00);
+	XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XTTCPS_MATCH_2_OFFSET, 0x00);
+	XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XTTCPS_IER_OFFSET, 0x00);
+	XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XTTCPS_ISR_OFFSET, XTTCPS_IXR_ALL_MASK);
+
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	/*
+	 * Reset the counter value
+	 */
+	XTtcPs_ResetCounterValue(InstancePtr);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function is used to set the match registers. There are three match
+* registers.
+*
+* The match 0 register is special. If the waveform output mode is enabled, the
+* waveform will change polarity when the count matches the value in the match 0
+* register. The polarity of the waveform output can also be set using the
+* XTtcPs_SetOptions() function.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	MatchIndex is the index to the match register to be set.
+*		Valid values are 0, 1, or 2.
+* @param	Value is the 16-bit value to be set in the match register.
+*
+* @return	None
+*
+* @note		None
+*
+****************************************************************************/
+void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value)
+{
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(MatchIndex < XTTCPS_NUM_MATCH_REG);
+
+	/*
+	 * Write the value to the correct match register with MatchIndex
+	 */
+	XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XTtcPs_Match_N_Offset(MatchIndex), Value);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function is used to get the value of the match registers. There are
+* three match registers.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	MatchIndex is the index to the match register to be set.
+*		Valid values are 0, 1, or 2.
+*
+* @return	None
+*
+* @note		None
+*
+****************************************************************************/
+u16 XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex)
+{
+	u32 MatchReg;
+
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(MatchIndex < XTTCPS_NUM_MATCH_REG);
+
+	MatchReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+			    XTtcPs_Match_N_Offset(MatchIndex));
+
+	return (u16) MatchReg;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the prescaler enable bit and if needed sets the prescaler
+* bits in the control register.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	PrescalerValue is a number from 0-16 that sets the prescaler
+*		to use.
+*		If the parameter is 0 - 15, use a prescaler on the clock of
+*		2^(PrescalerValue+1), or 2-65536.
+*		If the parameter is XTTCPS_CLK_CNTRL_PS_DISABLE, do not use a
+*		prescaler.
+*
+* @return	None
+*
+* @note		None
+*
+****************************************************************************/
+void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue)
+{
+	u32 ClockReg;
+
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(PrescalerValue <= XTTCPS_CLK_CNTRL_PS_DISABLE);
+
+	/*
+	 * Read the clock control register
+	 */
+	ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+			   XTTCPS_CLK_CNTRL_OFFSET);
+
+	/*
+	 * Clear all of the prescaler control bits in the register
+	 */
+	ClockReg &=
+		~(XTTCPS_CLK_CNTRL_PS_VAL_MASK | XTTCPS_CLK_CNTRL_PS_EN_MASK);
+
+	if (PrescalerValue < XTTCPS_CLK_CNTRL_PS_DISABLE) {
+		/*
+		 * Set the prescaler value and enable prescaler
+		 */
+		ClockReg |= (PrescalerValue << XTTCPS_CLK_CNTRL_PS_VAL_SHIFT) &
+			XTTCPS_CLK_CNTRL_PS_VAL_MASK;
+		ClockReg |= XTTCPS_CLK_CNTRL_PS_EN_MASK;
+	}
+
+	/*
+	 * Write the register with the new values.
+	 */
+	XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XTTCPS_CLK_CNTRL_OFFSET, ClockReg);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the input clock prescaler
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* 
+* @return	The value(n) from which the prescalar value is calculated
+*		as 2^(n+1). Some example values are given below :
+*
+* 	Value		Prescaler
+* 	0		2
+* 	1		4
+* 	N		2^(n+1)
+* 	15		65536
+* 	16		1
+* 

+*
+* @note		None.
+*
+****************************************************************************/
+u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr)
+{
+	u32 ClockReg;
+
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the clock control register
+	 */
+	ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XTTCPS_CLK_CNTRL_OFFSET);
+
+	if (0 == (ClockReg & XTTCPS_CLK_CNTRL_PS_EN_MASK)) {
+		/*
+		 * Prescaler is disabled. Return the correct flag value
+		 */
+		return XTTCPS_CLK_CNTRL_PS_DISABLE;
+	}
+
+	return ((ClockReg & XTTCPS_CLK_CNTRL_PS_VAL_MASK) >>
+		XTTCPS_CLK_CNTRL_PS_VAL_SHIFT);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function calculates the interval value as well as the prescaler value
+* for a given frequency.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	Freq is the requested output frequency for the device.
+* @param	Interval is the interval value for the given frequency,
+*		it is the output value for this function.
+* @param	Prescaler is the prescaler value for the given frequency,
+*		it is the output value for this function.
+*
+* @return	None.
+*
+* @note
+*  Upon successful calculation for the given frequency, Interval and Prescaler
+*  carry the settings for the timer counter; Upon unsuccessful calculation,
+*  Interval and Prescaler are set to 0xFF(FF) for their maximum values to
+*  signal the caller of failure. Therefore, caller needs to check the return
+*  interval or prescaler values for whether the function has succeeded.
+*
+****************************************************************************/
+void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
+        u16 *Interval, u8 *Prescaler)
+{
+	u8 TmpPrescaler;
+	u32 TempValue;
+	u32 InputClock;
+
+	InputClock = InstancePtr->Config.InputClockHz;
+	/*
+	 * Find the smallest prescaler that will work for a given frequency. The
+	 * smaller the prescaler, the larger the count and the more accurate the
+	 *  PWM setting.
+	 */
+	TempValue = InputClock/ Freq;
+
+	if (TempValue < 4) {
+		/*
+		 * The frequency is too high, it is too close to the input
+		 * clock value. Use maximum values to signal caller.
+		 */
+		*Interval = 0xFFFF;
+		*Prescaler = 0xFF;
+		return;
+	}
+
+	/*
+	 * First, do we need a prescaler or not?
+	 */
+	if (65536 > TempValue) {
+		/*
+		 * We do not need a prescaler, so set the values appropriately
+		 */
+		*Interval = TempValue;
+		*Prescaler = XTTCPS_CLK_CNTRL_PS_DISABLE;
+		return;
+	}
+
+
+	for (TmpPrescaler = 0; TmpPrescaler < XTTCPS_CLK_CNTRL_PS_DISABLE;
+	     TmpPrescaler++) {
+		TempValue =	InputClock/ (Freq * (1 << (TmpPrescaler + 1)));
+
+		/*
+		 * The first value less than 2^16 is the best bet
+		 */
+		if (65536 > TempValue) {
+			/*
+			 * Set the values appropriately
+			 */
+			*Interval = TempValue;
+			*Prescaler = TmpPrescaler;
+			return;
+		}
+	}
+
+	/* Can not find interval values that work for the given frequency.
+	 * Return maximum values to signal caller.
+	 */
+	*Interval = 0XFFFF;
+	*Prescaler = 0XFF;
+	return;
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v2_0/src/xttcps.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v2_0/src/xttcps.h
new file mode 100644
index 000000000..2afdffe5d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v2_0/src/xttcps.h
@@ -0,0 +1,417 @@
+/* $Id: xttcps.h,v 1.1.2.1 2011/01/20 04:08:59 sadanan Exp $ */
+/******************************************************************************
+*
+* (c) Copyright 2010 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps.h
+*
+* This is the driver for one 16-bit timer counter in the Triple Timer Counter
+* (TTC) module in the Ps block.
+*
+* The TTC module provides three independent timer/counter modules that can each
+* be clocked using either the system clock (pclk) or an externally driven
+* clock (ext_clk). In addition, each counter can independently prescale its
+* selected clock input (divided by 2 to 65536). Counters can be set to
+* decrement or increment.
+*
+* Each of the counters can be programmed to generate interrupt pulses:
+*	. At a regular, predefined period, that is on a timed interval
+*	. When the counter registers overflow
+* 	. When the count matches any one of the three 'match' registers
+*
+* Therefore, up to six different events can trigger a timer interrupt: three
+* match interrupts, an overflow interrupt, an interval interrupt and an event
+* timer interrupt. Note that the overflow interrupt and the interval interrupt
+* are mutually exclusive.
+*
+* Initialization & Configuration
+*
+* An XTtcPs_Config structure is used to configure a driver instance.
+* Information in the XTtcPs_Config structure is the hardware properties
+* about the device.
+*
+* A driver instance is initialized through
+* XTtcPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr). Where CfgPtr
+* is a pointer to the XTtcPs_Config structure, it can be looked up statically
+* through XTtcPs_LookupConfig(DeviceID), or passed in by the caller. The
+* EffectiveAddr can be the static base address of the device or virtual
+* mapped address if address translation is supported.
+*
+* Interrupts
+*
+* Interrupt handler is not provided by the driver, as handling of interrupt
+* is application specific.
+*
+* @note
+* The default setting for a timer/counter is:
+*  - Overflow Mode
+*  - Internal clock (pclk) selected
+*  - Counter disabled
+*  - All Interrupts disabled
+*  - Output waveforms disabled
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -----------------------------------------------------
+* 1.00a drg/jz 01/20/10 First release..
+* 2.0   adk    12/10/13 Updated as per the New Tcl API's
+*
+* 

+*
+******************************************************************************/
+
+#ifndef XTTCPS_H		/* prevent circular inclusions */
+#define XTTCPS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xttcps_hw.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Configuration options
+ *
+ * Options for the device. Each of the options is bit field, so more than one
+ * options can be specified.
+ *
+ * @{
+ */
+#define XTTCPS_OPTION_EXTERNAL_CLK	0x0001 	/**< External clock source */
+#define XTTCPS_OPTION_CLK_EDGE_NEG	0x0002	/**< Clock on trailing edge for
+						     external clock*/
+#define XTTCPS_OPTION_INTERVAL_MODE	0x0004	/**< Interval mode */
+#define XTTCPS_OPTION_DECREMENT		0x0008	/**< Decrement the counter */
+#define XTTCPS_OPTION_MATCH_MODE	0x0010	/**< Match mode */
+#define XTTCPS_OPTION_WAVE_DISABLE	0x0020 	/**< No waveform output */
+#define XTTCPS_OPTION_WAVE_POLARITY	0x0040	/**< Waveform polarity */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;	  /**< Unique ID for device */
+	u32 BaseAddress;  /**< Base address for device */
+	u32 InputClockHz; /**< Input clock frequency */
+} XTtcPs_Config;
+
+/**
+ * The XTtcPs driver instance data. The user is required to allocate a
+ * variable of this type for each PS timer/counter device in the system. A
+ * pointer to a variable of this type is then passed to various driver API
+ * functions.
+ */
+typedef struct {
+	XTtcPs_Config Config;	/**< Configuration structure */
+	u32 IsReady;		/**< Device is initialized and ready */
+} XTtcPs;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*
+ * Internal helper macros
+ */
+#define InstReadReg(InstancePtr, RegOffset) \
+    (Xil_In32(((InstancePtr)->Config.BaseAddress) + (RegOffset)))
+
+#define InstWriteReg(InstancePtr, RegOffset, Data) \
+    (Xil_Out32(((InstancePtr)->Config.BaseAddress) + (RegOffset), (Data)))
+
+/*****************************************************************************/
+/**
+*
+* This function starts the counter/timer without resetting the counter value.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	None
+*
+* @note		C-style signature:
+*		void XTtcPs_Start(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_Start(InstancePtr)	\
+		InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET,	\
+		(InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) &	\
+		 ~XTTCPS_CNT_CNTRL_DIS_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function stops the counter/timer. This macro may be called at any time
+* to stop the counter. The counter holds the last value until it is reset,
+* restarted or enabled.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	None
+*
+* @note		C-style signature:
+*		void XTtcPs_Stop(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_Stop(InstancePtr)		\
+		InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET,	\
+		(InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) |	\
+		 XTTCPS_CNT_CNTRL_DIS_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function checks whether the timer counter has already started.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance
+*
+* @return	Non-zero if the device has started, '0' otherwise.
+*
+* @note		C-style signature:
+*		int XTtcPs_IsStarted(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_IsStarted(InstancePtr) \
+     (int)((InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \
+       XTTCPS_CNT_CNTRL_DIS_MASK) == 0)
+
+/*****************************************************************************/
+/**
+*
+* This function returns the current 16-bit counter value. It may be called at
+* any time.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	16-bit counter value.
+*
+* @note		C-style signature:
+*		u16 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_GetCounterValue(InstancePtr) \
+		(u16)InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function sets the interval value to be used in interval mode.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	Value is the 16-bit value to be set in the interval register.
+*
+* @return	None
+*
+* @note		C-style signature:
+*		void XTtcPs_SetInterval(XTtcPs *InstancePtr, u16 Value)
+*
+****************************************************************************/
+#define XTtcPs_SetInterval(InstancePtr, Value)	\
+		InstWriteReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET, (Value))
+
+/*****************************************************************************/
+/**
+*
+* This function gets the interval value from the interval register.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	16-bit interval value
+*
+* @note		C-style signature:
+*		u16 XTtcPs_GetInterval(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_GetInterval(InstancePtr) \
+		(u16)InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This macro resets the count register. It may be called at any time. The
+* counter is reset to either 0 or 0xFFFF, or the interval value, depending on
+* the increment/decrement mode. The state of the counter, as started or
+* stopped, is not affected by calling reset.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	None
+*
+* @note		C-style signature:
+*		void XTtcPs_ResetCounterValue(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_ResetCounterValue(InstancePtr) \
+		InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET,	\
+		(InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \
+		 XTTCPS_CNT_CNTRL_RST_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function enables the interrupts.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	InterruptMask defines which interrupt should be enabled.
+*		Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
+*		This is a bit mask, all set bits will be enabled, cleared bits
+*		will not be disabled.
+*
+* @return	None.
+*
+* @note
+* C-style signature:
+*	void XTtcPs_EnableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
+*
+******************************************************************************/
+#define XTtcPs_EnableInterrupts(InstancePtr, InterruptMask)		\
+		InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET,		\
+		(InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) |	\
+		 (InterruptMask)))
+
+/*****************************************************************************/
+/**
+*
+* This function disables the interrupts.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	InterruptMask defines which interrupt should be disabled.
+*		Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
+*		This is a bit mask, all set bits will be disabled, cleared bits
+*		will not be disabled.
+*
+* @return	None.
+*
+* @note
+* C-style signature:
+*	void XTtcPs_DisableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
+*
+******************************************************************************/
+#define XTtcPs_DisableInterrupts(InstancePtr, InterruptMask) \
+		InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET,	\
+		(InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) &	\
+		 ~(InterruptMask)))
+
+/*****************************************************************************/
+/**
+*
+* This function reads the interrupt status.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		u32 XTtcPs_GetInterruptStatus(XTtcPs *InstancePtr)
+*
+******************************************************************************/
+#define XTtcPs_GetInterruptStatus(InstancePtr)	 \
+		InstReadReg((InstancePtr), XTTCPS_ISR_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function clears the interrupt status.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	InterruptMask defines which interrupt should be cleared.
+*		Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
+*		This is a bit mask, all set bits will be cleared, cleared bits
+*		will not be cleared.
+*
+* @return	None.
+*
+* @note
+* C-style signature:
+*	void XTtcPs_ClearInterruptStatus(XTtcPs *InstancePtr, u32 InterruptMask)
+*
+******************************************************************************/
+#define XTtcPs_ClearInterruptStatus(InstancePtr, InterruptMask) \
+		InstWriteReg((InstancePtr), XTTCPS_ISR_OFFSET, \
+		 (InterruptMask))
+
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Initialization functions in xttcps_sinit.c
+ */
+XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Required functions, in xttcps.c
+ */
+int XTtcPs_CfgInitialize(XTtcPs *InstancePtr,
+         XTtcPs_Config * ConfigPtr, u32 EffectiveAddr);
+
+void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value);
+u16 XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex);
+
+void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue);
+u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr);
+
+void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
+        u16 *Interval, u8 *Prescaler);
+
+/*
+ * Functions for options, in file xttcps_options.c
+ */
+int XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options);
+u32 XTtcPs_GetOptions(XTtcPs *InstancePtr);
+
+/*
+ * Function for self-test, in file xttcps_selftest.c
+ */
+int XTtcPs_SelfTest(XTtcPs *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v2_0/src/xttcps_g.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v2_0/src/xttcps_g.c
new file mode 100644
index 000000000..98accc834
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v2_0/src/xttcps_g.c
@@ -0,0 +1,42 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSM.
+* Version: 
+* DO NOT EDIT.
+*
+*  v (64-bit)
+SW Build (by ) on 
+Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xttcps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XTtcPs_Config XTtcPs_ConfigTable[] =
+{
+	{
+		XPAR_PS7_TTC_0_DEVICE_ID,
+		XPAR_PS7_TTC_0_BASEADDR,
+		XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PS7_TTC_1_DEVICE_ID,
+		XPAR_PS7_TTC_1_BASEADDR,
+		XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PS7_TTC_2_DEVICE_ID,
+		XPAR_PS7_TTC_2_BASEADDR,
+		XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v2_0/src/xttcps_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v2_0/src/xttcps_hw.h
new file mode 100644
index 000000000..5f361e088
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v2_0/src/xttcps_hw.h
@@ -0,0 +1,218 @@
+/* $Id: xttcps_hw.h,v 1.1.2.1 2011/01/20 04:08:59 sadanan Exp $ */
+/******************************************************************************
+*
+* (c) Copyright 2010 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_hw.h
+*
+* This file defines the hardware interface to one of the three timer counters
+* in the Ps block.
+*
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -------------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+*
+* 

+*
+******************************************************************************/
+
+#ifndef XTTCPS_HW_H		/* prevent circular inclusions */
+#define XTTCPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of the device.
+ *
+ * @{
+ */
+#define XTTCPS_CLK_CNTRL_OFFSET		0x00000000  /**< Clock Control Register */
+#define XTTCPS_CNT_CNTRL_OFFSET		0x0000000C  /**< Counter Control Register*/
+#define XTTCPS_COUNT_VALUE_OFFSET	0x00000018  /**< Current Counter Value */
+#define XTTCPS_INTERVAL_VAL_OFFSET	0x00000024  /**< Interval Count Value */
+#define XTTCPS_MATCH_0_OFFSET		0x00000030  /**< Match 1 value */
+#define XTTCPS_MATCH_1_OFFSET		0x0000003C  /**< Match 2 value */
+#define XTTCPS_MATCH_2_OFFSET		0x00000048  /**< Match 3 value */
+#define XTTCPS_ISR_OFFSET		0x00000054  /**< Interrupt Status Register */
+#define XTTCPS_IER_OFFSET		0x00000060  /**< Interrupt Enable Register */
+/* @} */
+
+/** @name Clock Control Register
+ * Clock Control Register definitions
+ * @{
+ */
+#define XTTCPS_CLK_CNTRL_PS_EN_MASK	0x00000001  /**< Prescale enable */
+#define XTTCPS_CLK_CNTRL_PS_VAL_MASK	0x0000001E  /**< Prescale value */
+#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT		1   /**< Prescale shift */
+#define XTTCPS_CLK_CNTRL_PS_DISABLE		16  /**< Prescale disable */
+#define XTTCPS_CLK_CNTRL_SRC_MASK	0x00000020  /**< Clock source */
+#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK	0x00000040  /**< External Clock edge */
+/* @} */
+
+/** @name Counter Control Register
+ * Counter Control Register definitions
+ * @{
+ */
+#define XTTCPS_CNT_CNTRL_DIS_MASK	0x00000001 /**< Disable the counter */
+#define XTTCPS_CNT_CNTRL_INT_MASK	0x00000002 /**< Interval mode */
+#define XTTCPS_CNT_CNTRL_DECR_MASK	0x00000004 /**< Decrement mode */
+#define XTTCPS_CNT_CNTRL_MATCH_MASK	0x00000008 /**< Match mode */
+#define XTTCPS_CNT_CNTRL_RST_MASK	0x00000010 /**< Reset counter */
+#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK	0x00000020 /**< Enable waveform */
+#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK	0x00000040 /**< Waveform polarity */
+#define XTTCPS_CNT_CNTRL_RESET_VALUE	0x00000021 /**< Reset value */
+/* @} */
+
+/** @name Current Counter Value Register
+ * Current Counter Value Register definitions
+ * @{
+ */
+#define XTTCPS_COUNT_VALUE_MASK		0x0000FFFF /**< 16-bit counter value */
+/* @} */
+
+/** @name Interval Value Register
+ * Interval Value Register is the maximum value the counter will count up or
+ * down to.
+ * @{
+ */
+#define XTTCPS_INTERVAL_VAL_MASK	0x0000FFFF /**< 16-bit Interval value*/
+/* @} */
+
+/** @name Match Registers
+ * Definitions for Match registers, each timer counter has three match
+ * registers.
+ * @{
+ */
+#define XTTCPS_MATCH_MASK		0x0000FFFF /**< 16-bit Match value */
+#define XTTCPS_NUM_MATCH_REG			3  /**< Num of Match reg */
+/* @} */
+
+/** @name Interrupt Registers
+ * Following register bit mask is for all interrupt registers.
+ *
+ * @{
+ */
+#define XTTCPS_IXR_INTERVAL_MASK	0x00000001  /**< Interval Interrupt */
+#define XTTCPS_IXR_MATCH_0_MASK		0x00000002  /**< Match 1 Interrupt */
+#define XTTCPS_IXR_MATCH_1_MASK		0x00000004  /**< Match 2 Interrupt */
+#define XTTCPS_IXR_MATCH_2_MASK		0x00000008  /**< Match 3 Interrupt */
+#define XTTCPS_IXR_CNT_OVR_MASK		0x00000010  /**< Counter Overflow */
+#define XTTCPS_IXR_ALL_MASK		0x0000001F  /**< All valid Interrupts */
+/* @} */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given Timer Counter register.
+*
+* @param	BaseAddress is the base address of the timer counter device.
+* @param	RegOffset is the register offset to be read
+*
+* @return	The 32-bit value of the register
+*
+* @note		C-style signature:
+*		u32 XTtcPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XTtcPs_ReadReg(BaseAddress, RegOffset) \
+    (Xil_In32((BaseAddress) + (RegOffset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Timer Counter register.
+*
+* @param	BaseAddress is the base address of the timer counter device.
+* @param	RegOffset is the register offset to be written
+* @param	Data is the 32-bit value to write to the register
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XTtcPs_WriteReg(XTtcPs BaseAddress, u32 RegOffset,
+*		u32 Data)
+*
+*****************************************************************************/
+#define XTtcPs_WriteReg(BaseAddress, RegOffset, Data) \
+    (Xil_Out32((BaseAddress) + (RegOffset), (Data)))
+
+/****************************************************************************/
+/**
+*
+* Calculate a match register offset using the Match Register index.
+*
+* @param	MatchIndex is the 0-2 value of the match register
+*
+* @return	MATCH_N_OFFSET.
+*
+* @note		C-style signature:
+*		u32 XTtcPs_Match_N_Offset(u8 MatchIndex)
+*
+*****************************************************************************/
+#define XTtcPs_Match_N_Offset(MatchIndex) \
+		(XTTCPS_MATCH_0_OFFSET + (12 * (MatchIndex)))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v2_0/src/xttcps_options.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v2_0/src/xttcps_options.c
new file mode 100644
index 000000000..e83dc7ab0
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v2_0/src/xttcps_options.c
@@ -0,0 +1,242 @@
+/* $Id: xttcps_options.c,v 1.1.2.1 2011/01/20 04:08:59 sadanan Exp $ */
+/******************************************************************************
+*
+* (c) Copyright 2010 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_options.c
+*
+* This file contains functions to get or set option features for the device.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 1.01a nm     03/05/2012 Removed break statement after return to remove
+*                         compilation warnings.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xttcps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+/*
+ * Create the table of options which are processed to get/set the device
+ * options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+typedef struct {
+	u32 Option;
+	u32 Mask;
+	u32 Register;
+} OptionsMap;
+
+static OptionsMap TmrCtrOptionsTable[] = {
+	{XTTCPS_OPTION_EXTERNAL_CLK, XTTCPS_CLK_CNTRL_SRC_MASK,
+	 XTTCPS_CLK_CNTRL_OFFSET},
+	{XTTCPS_OPTION_CLK_EDGE_NEG, XTTCPS_CLK_CNTRL_EXT_EDGE_MASK,
+	 XTTCPS_CLK_CNTRL_OFFSET},
+	{XTTCPS_OPTION_INTERVAL_MODE, XTTCPS_CNT_CNTRL_INT_MASK,
+	 XTTCPS_CNT_CNTRL_OFFSET},
+	{XTTCPS_OPTION_DECREMENT, XTTCPS_CNT_CNTRL_DECR_MASK,
+	 XTTCPS_CNT_CNTRL_OFFSET},
+	{XTTCPS_OPTION_MATCH_MODE, XTTCPS_CNT_CNTRL_MATCH_MASK,
+	 XTTCPS_CNT_CNTRL_OFFSET},
+	{XTTCPS_OPTION_WAVE_DISABLE, XTTCPS_CNT_CNTRL_EN_WAVE_MASK,
+	 XTTCPS_CNT_CNTRL_OFFSET},
+	{XTTCPS_OPTION_WAVE_POLARITY, XTTCPS_CNT_CNTRL_POL_WAVE_MASK,
+	 XTTCPS_CNT_CNTRL_OFFSET},
+};
+
+#define XTTCPS_NUM_TMRCTR_OPTIONS (sizeof(TmrCtrOptionsTable) / \
+				sizeof(OptionsMap))
+
+/*****************************************************************************/
+/**
+*
+* This function sets the options for the TTC device.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	Options contains the specified options to be set. This is a bit
+*		mask where a 1 means to turn the option on, and a 0 means to
+*		turn the option off. One or more bit values may be contained
+*		in the mask. See the bit definitions named XTTCPS_*_OPTION in
+*		the file xttcps.h.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_FAILURE if any of the options are unknown.
+*
+* @note		None
+*
+******************************************************************************/
+int XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options)
+{
+	u32 CountReg;
+	u32 ClockReg;
+	unsigned Index;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XTTCPS_CLK_CNTRL_OFFSET);
+	CountReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XTTCPS_CNT_CNTRL_OFFSET);
+
+	/*
+	 * Loop through the options table, turning the option on or off
+	 * depending on whether the bit is set in the incoming options flag.
+	 */
+	for (Index = 0; Index < XTTCPS_NUM_TMRCTR_OPTIONS; Index++) {
+		if (Options & TmrCtrOptionsTable[Index].Option) {
+
+			switch (TmrCtrOptionsTable[Index].Register) {
+
+			case XTTCPS_CLK_CNTRL_OFFSET:
+				/* Add option */
+				ClockReg |= TmrCtrOptionsTable[Index].Mask;
+				break;
+
+			case XTTCPS_CNT_CNTRL_OFFSET:
+				/* Add option */
+				CountReg |= TmrCtrOptionsTable[Index].Mask;
+				break;
+
+			default:
+				return XST_FAILURE;
+			}
+		}
+		else {
+			switch (TmrCtrOptionsTable[Index].Register) {
+
+			case XTTCPS_CLK_CNTRL_OFFSET:
+				/* Remove option*/
+				ClockReg &= ~TmrCtrOptionsTable[Index].Mask;
+				break;
+
+			case XTTCPS_CNT_CNTRL_OFFSET:
+				/* Remove option*/
+				CountReg &= ~TmrCtrOptionsTable[Index].Mask;
+				break;
+
+			default:
+				return XST_FAILURE;
+			}
+		}
+	}
+
+	/*
+	 * Now write the registers. Leave it to the upper layers to restart the
+	 * device.
+	 */
+	XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XTTCPS_CLK_CNTRL_OFFSET, ClockReg);
+	XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XTTCPS_CNT_CNTRL_OFFSET, CountReg);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the settings for the options for the TTC device.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return
+*
+* The return u32 contains the specified options that are set. This is a bit
+* mask where a '1' means the option is on, and a'0' means the option is off.
+* One or more bit values may be contained in the mask. See the bit definitions
+* named XTTCPS_*_OPTION in the file xttcps.h.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XTtcPs_GetOptions(XTtcPs *InstancePtr)
+{
+	u32 OptionsFlag = 0;
+	u32 Register;
+	unsigned Index;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+	/*
+	 * Loop through the options table to determine which options are set
+	 */
+	for (Index = 0; Index < XTTCPS_NUM_TMRCTR_OPTIONS; Index++) {
+		/*
+		 * Get the control register to determine which options are
+		 * currently set.
+		 */
+		Register = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+					      TmrCtrOptionsTable[Index].
+					      Register);
+
+		if (Register & TmrCtrOptionsTable[Index].Mask) {
+			OptionsFlag |= TmrCtrOptionsTable[Index].Option;
+		}
+	}
+
+	return OptionsFlag;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v2_0/src/xttcps_selftest.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v2_0/src/xttcps_selftest.c
new file mode 100644
index 000000000..b8128f23d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v2_0/src/xttcps_selftest.c
@@ -0,0 +1,112 @@
+/* $Id: xttcps_selftest.c,v 1.1.2.1 2011/01/20 04:08:59 sadanan Exp $ */
+/******************************************************************************
+*
+* (c) Copyright 2010 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_selftest.c
+*
+* This file contains the implementation of self test function for the
+* XTtcPs driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xttcps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Runs a self-test on the driver/device.
+*
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return
+*
+*	- XST_SUCCESS if successful
+*	- XST_FAILURE indicates a register did not read or write correctly
+*
+* @note		This test fails if it is not called right after initialization.
+*
+******************************************************************************/
+int XTtcPs_SelfTest(XTtcPs *InstancePtr)
+{
+	u32 TempReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * All the TTC registers should be in their default state right now.
+	 */
+	TempReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XTTCPS_CNT_CNTRL_OFFSET);
+	if (XTTCPS_CNT_CNTRL_RESET_VALUE != TempReg) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v2_0/src/xttcps_sinit.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v2_0/src/xttcps_sinit.c
new file mode 100644
index 000000000..d3d202c1f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v2_0/src/xttcps_sinit.c
@@ -0,0 +1,104 @@
+/* $Id: xttcps_sinit.c,v 1.1.2.1 2011/01/20 04:08:59 sadanan Exp $ */
+/******************************************************************************
+*
+* (c) Copyright 2010 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_sinit.c
+*
+* The implementation of the XTtcPs driver's static initialization functionality.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xttcps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XTtcPs_Config XTtcPs_ConfigTable[];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the unique ID of the device
+*
+* @return
+*
+* A pointer to the configuration found or NULL if the specified device ID was
+* not found. See xttcps.h for the definition of XTtcPs_Config.
+*
+* @note		None.
+*
+******************************************************************************/
+XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId)
+{
+	XTtcPs_Config *CfgPtr = NULL;
+	unsigned Index;
+
+	for (Index = 0; Index < XPAR_XTTCPS_NUM_INSTANCES; Index++) {
+		if (XTtcPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XTtcPs_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return CfgPtr;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/Makefile
new file mode 100644
index 000000000..7d608cdae
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/Makefile
@@ -0,0 +1,41 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xuartps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling uartps"
+
+xuartps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xuartps_includes
+
+xuartps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps.c
new file mode 100644
index 000000000..ff89c9456
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps.c
@@ -0,0 +1,673 @@
+/*****************************************************************************
+*
+* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+*****************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps.c
+*
+* This file contains the implementation of the interface functions for XUartPs
+* driver. Refer to the header file xuartps.h for more detailed information.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	 Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	drg/jz 01/13/10 First Release
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xuartps.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+
+/* The following constant defines the amount of error that is allowed for
+ * a specified baud rate. This error is the difference between the actual
+ * baud rate that will be generated using the specified clock and the
+ * desired baud rate.
+ */
+#define XUARTPS_MAX_BAUD_ERROR_RATE		 3	/* max % error allowed */
+
+/**************************** Type Definitions ******************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+
+static void XUartPs_StubHandler(void *CallBackRef, u32 Event,
+				 unsigned int ByteCount);
+
+unsigned int XUartPs_SendBuffer(XUartPs *InstancePtr);
+
+unsigned int XUartPs_ReceiveBuffer(XUartPs *InstancePtr);
+
+/************************** Variable Definitions ****************************/
+
+/****************************************************************************/
+/**
+*
+* Initializes a specific XUartPs instance such that it is ready to be used.
+* The data format of the device is setup for 8 data bits, 1 stop bit, and no
+* parity by default. The baud rate is set to a default value specified by
+* Config->DefaultBaudRate if set, otherwise it is set to 19.2K baud. The
+* receive FIFO threshold is set for 8 bytes. The default operating mode of the
+* driver is polled mode.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	Config is a reference to a structure containing information
+*		about a specific XUartPs driver.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, pass in the physical
+*		address instead.
+*
+* @return
+*
+*		- XST_SUCCESS if initialization was successful
+*		- XST_UART_BAUD_ERROR if the baud rate is not possible because
+*		  the inputclock frequency is not divisible with an acceptable
+*		  amount of error
+*
+* @note
+*
+* The default configuration for the UART after initialization is:
+*
+* - 19,200 bps or XPAR_DFT_BAUDRATE if defined
+* - 8 data bits
+* - 1 stop bit
+* - no parity
+* - FIFO's are enabled with a receive threshold of 8 bytes
+* - The RX timeout is enabled with a timeout of 1 (4 char times)
+*
+*   All interrupts are disabled.
+*
+*****************************************************************************/
+int XUartPs_CfgInitialize(XUartPs *InstancePtr,
+				   XUartPs_Config * Config, u32 EffectiveAddr)
+{
+	int Status;
+	u32 ModeRegister;
+	u32 BaudRate;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Config != NULL);
+
+	/*
+	 * Setup the driver instance using passed in parameters
+	 */
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+	InstancePtr->Config.InputClockHz = Config->InputClockHz;
+	InstancePtr->Config.ModemPinsConnected = Config->ModemPinsConnected;
+
+	/*
+	 * Initialize other instance data to default values
+	 */
+	InstancePtr->Handler = XUartPs_StubHandler;
+
+	InstancePtr->SendBuffer.NextBytePtr = NULL;
+	InstancePtr->SendBuffer.RemainingBytes = 0;
+	InstancePtr->SendBuffer.RequestedBytes = 0;
+
+	InstancePtr->ReceiveBuffer.NextBytePtr = NULL;
+	InstancePtr->ReceiveBuffer.RemainingBytes = 0;
+	InstancePtr->ReceiveBuffer.RequestedBytes = 0;
+
+	/*
+	 * Flag that the driver instance is ready to use
+	 */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	/*
+	 * Set the default baud rate here, can be changed prior to
+	 * starting the device
+	 */
+	BaudRate = XUARTPS_DFT_BAUDRATE;
+	Status = XUartPs_SetBaudRate(InstancePtr, BaudRate);
+	if (Status != XST_SUCCESS) {
+		InstancePtr->IsReady = 0;
+		return Status;
+	}
+
+	/*
+	 * Set up the default data format: 8 bit data, 1 stop bit, no
+	 * parity
+	 */
+	ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_MR_OFFSET);
+
+	/*
+	 * Mask off what's already there
+	 */
+	ModeRegister &= ~(XUARTPS_MR_CHARLEN_MASK |
+					 XUARTPS_MR_STOPMODE_MASK |
+					 XUARTPS_MR_PARITY_MASK);
+
+	/*
+	 * Set the register value to the desired data format
+	 */
+	ModeRegister |=	(XUARTPS_MR_CHARLEN_8_BIT |
+					XUARTPS_MR_STOPMODE_1_BIT |
+					XUARTPS_MR_PARITY_NONE);
+
+	/*
+	 * Write the mode register out
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+			   ModeRegister);
+
+	/*
+	 * Set the RX FIFO trigger at 8 data bytes.
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_RXWM_OFFSET, 0x08);
+
+	/*
+	 * Set the RX timeout to 1, which will be 4 character time
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_RXTOUT_OFFSET, 0x01);
+
+	/*
+	 * Disable all interrupts, polled mode is the default
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+			   XUARTPS_IXR_MASK);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This functions sends the specified buffer using the device in either
+* polled or interrupt driven mode. This function is non-blocking, if the device
+* is busy sending data, it will return and indicate zero bytes were sent.
+* Otherwise, it fills the TX FIFO as much as it can, and return the number of
+* bytes sent.
+*
+* In a polled mode, this function will only send as much data as TX FIFO can
+* buffer. The application may need to call it repeatedly to send the entire
+* buffer.
+*
+* In interrupt mode, this function will start sending the specified buffer,
+* then the interrupt handler will continue sending data until the entire
+* buffer has been sent. A callback function, as specified by the application,
+* will be called to indicate the completion of sending.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	BufferPtr is pointer to a buffer of data to be sent.
+* @param  	NumBytes contains the number of bytes to be sent. A value of
+*		zero will stop a previous send operation that is in progress
+*		in interrupt mode. Any data that was already put into the
+*		transmit FIFO will be sent.
+*
+* @return	The number of bytes actually sent.
+*
+* @note
+*
+* The number of bytes is not asserted so that this function may be called with
+* a value of zero to stop an operation that is already in progress.
+* 


+*
+*****************************************************************************/
+unsigned int XUartPs_Send(XUartPs *InstancePtr, u8 *BufferPtr,
+			   unsigned int NumBytes)
+{
+	unsigned int BytesSent;
+
+	/*
+	 * Asserts validate the input arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(BufferPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Disable the UART transmit interrupts to allow this call to stop a
+	 * previous operation that may be interrupt driven.
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+					  (XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_TXFULL));
+
+	/*
+	 * Setup the buffer parameters
+	 */
+	InstancePtr->SendBuffer.RequestedBytes = NumBytes;
+	InstancePtr->SendBuffer.RemainingBytes = NumBytes;
+	InstancePtr->SendBuffer.NextBytePtr = BufferPtr;
+
+	/*
+	 * Transmit interrupts will be enabled in XUartPs_SendBuffer(), after
+	 * filling the TX FIFO.
+	 */
+	BytesSent = XUartPs_SendBuffer(InstancePtr);
+
+	return BytesSent;
+}
+
+/****************************************************************************/
+/**
+*
+* This function attempts to receive a specified number of bytes of data
+* from the device and store it into the specified buffer. This function works
+* for both polled or interrupt driven modes. It is non-blocking.
+*
+* In a polled mode, this function will only receive the data already in the
+* RX FIFO. The application may need to call it repeatedly to receive the
+* entire buffer. Polled mode is the default mode of operation for the device.
+*
+* In interrupt mode, this function will start the receiving, if not the entire
+* buffer has been received, the interrupt handler will continue receiving data
+* until the entire buffer has been received. A callback function, as specified
+* by the application, will be called to indicate the completion of the
+* receiving or error conditions.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	BufferPtr is pointer to buffer for data to be received into
+* @param	NumBytes is the number of bytes to be received. A value of zero
+*		will stop a previous receive operation that is in progress in
+*		interrupt mode.
+*
+* @return	The number of bytes received.
+*
+* @note
+*
+* The number of bytes is not asserted so that this function may be called
+* with a value of zero to stop an operation that is already in progress.
+*
+*****************************************************************************/
+unsigned int XUartPs_Recv(XUartPs *InstancePtr,
+			   u8 *BufferPtr, unsigned int NumBytes)
+{
+	unsigned int ReceivedCount;
+	u32 ImrRegister;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(BufferPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Disable all the interrupts.
+	 * This stops a previous operation that may be interrupt driven
+	 */
+	ImrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_IMR_OFFSET);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+		XUARTPS_IXR_MASK);
+
+	/*
+	 * Setup the buffer parameters
+	 */
+	InstancePtr->ReceiveBuffer.RequestedBytes = NumBytes;
+	InstancePtr->ReceiveBuffer.RemainingBytes = NumBytes;
+	InstancePtr->ReceiveBuffer.NextBytePtr = BufferPtr;
+
+	/*
+	 * Receive the data from the device
+	 */
+	ReceivedCount = XUartPs_ReceiveBuffer(InstancePtr);
+
+	/*
+	 * Restore the interrupt state
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IER_OFFSET,
+		ImrRegister);
+
+	return ReceivedCount;
+}
+
+/****************************************************************************/
+/*
+*
+* This function sends a buffer that has been previously specified by setting
+* up the instance variables of the instance. This function is an internal
+* function for the XUartPs driver such that it may be called from a shell
+* function that sets up the buffer or from an interrupt handler.
+*
+* This function sends the specified buffer in either polled or interrupt
+* driven modes. This function is non-blocking.
+*
+* In a polled mode, this function only sends as much data as the TX FIFO
+* can buffer. The application may need to call it repeatedly to send the
+* entire buffer.
+*
+* In interrupt mode, this function starts the sending of the buffer, if not
+* the entire buffer has been sent, then the interrupt handler continues the
+* sending until the entire buffer has been sent. A callback function, as
+* specified by the application, will be called to indicate the completion of
+* sending.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	The number of bytes actually sent
+*
+* @note		None.
+*
+*****************************************************************************/
+unsigned int XUartPs_SendBuffer(XUartPs *InstancePtr)
+{
+	unsigned int SentCount = 0;
+	u32 ImrRegister;
+
+	/*
+	 * If the TX FIFO is full, send nothing.
+	 * Otherwise put bytes into the TX FIFO unil it is full, or all of the
+	 * data has been put into the FIFO.
+	 */
+	while ((!XUartPs_IsTransmitFull(InstancePtr->Config.BaseAddress)) &&
+		   (InstancePtr->SendBuffer.RemainingBytes > SentCount)) {
+
+		/*
+		 * Fill the FIFO from the buffer
+		 */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_FIFO_OFFSET,
+				   InstancePtr->SendBuffer.
+				   NextBytePtr[SentCount]);
+
+		/*
+		 * Incriment the send count.
+		 */
+		SentCount++;
+	}
+
+	/*
+	 * Update the buffer to reflect the bytes that were sent from it
+	 */
+	InstancePtr->SendBuffer.NextBytePtr += SentCount;
+	InstancePtr->SendBuffer.RemainingBytes -= SentCount;
+
+	/*
+	 * If interrupts are enabled as indicated by the receive interrupt, then
+	 * enable the TX FIFO empty interrupt, so further action can be taken
+	 * for this sending.
+	 */
+	ImrRegister =
+		XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_IMR_OFFSET);
+	if ((ImrRegister & XUARTPS_IXR_RXFULL) ||
+		(ImrRegister & XUARTPS_IXR_RXEMPTY) ||
+		(ImrRegister & XUARTPS_IXR_RXOVR)) {
+
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_IER_OFFSET,
+				   ImrRegister | XUARTPS_IXR_TXEMPTY);
+	}
+
+	return SentCount;
+}
+
+/****************************************************************************/
+/*
+*
+* This function receives a buffer that has been previously specified by setting
+* up the instance variables of the instance. This function is an internal
+* function, and it may be called from a shell function that sets up the buffer
+* or from an interrupt handler.
+*
+* This function attempts to receive a specified number of bytes from the
+* device and store it into the specified buffer. This function works for
+* either polled or interrupt driven modes. It is non-blocking.
+*
+* In polled mode, this function only receives as much data as in the RX FIFO.
+* The application may need to call it repeatedly to receive the entire buffer.
+* Polled mode is the default mode for the driver.
+*
+* In interrupt mode, this function starts the receiving, if not the entire
+* buffer has been received, the interrupt handler will continue until the
+* entire buffer has been received. A callback function, as specified by the
+* application, will be called to indicate the completion of the receiving or
+* error conditions.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	The number of bytes received.
+*
+* @note		None.
+*
+*****************************************************************************/
+unsigned int XUartPs_ReceiveBuffer(XUartPs *InstancePtr)
+{
+	u32 CsrRegister;
+	unsigned int ReceivedCount = 0;
+
+	/*
+ 	 * Read the Channel Status Register to determine if there is any data in
+	 * the RX FIFO
+	 */
+	CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XUARTPS_SR_OFFSET);
+
+	/*
+	 * Loop until there is no more data in RX FIFO or the specified
+	 * number of bytes has been received
+	 */
+	while((ReceivedCount < InstancePtr->ReceiveBuffer.RemainingBytes)&&
+		(0 == (CsrRegister & XUARTPS_SR_RXEMPTY))){
+
+		InstancePtr->ReceiveBuffer.NextBytePtr[ReceivedCount] =
+			XUartPs_ReadReg(InstancePtr->Config.
+				  BaseAddress,
+				  XUARTPS_FIFO_OFFSET);
+
+		ReceivedCount++;
+
+		CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+								XUARTPS_SR_OFFSET);
+	}
+
+	/*
+	 * Update the receive buffer to reflect the number of bytes just
+	 * received
+	 */
+	InstancePtr->ReceiveBuffer.NextBytePtr += ReceivedCount;
+	InstancePtr->ReceiveBuffer.RemainingBytes -= ReceivedCount;
+
+	return ReceivedCount;
+}
+
+/*****************************************************************************/
+/**
+*
+* Sets the baud rate for the device. Checks the input value for
+* validity and also verifies that the requested rate can be configured to
+* within the maximum error range specified by XUARTPS_MAX_BAUD_ERROR_RATE.
+* If the provided rate is not possible, the current setting is unchanged.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	BaudRate to be set
+*
+* @return
+*		- XST_SUCCESS if everything configured as expected
+*		- XST_UART_BAUD_ERROR if the requested rate is not available
+*		  because there was too much error
+*
+* @note		None.
+*
+*****************************************************************************/
+int XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate)
+{
+	u8 IterBAUDDIV;		/* Iterator for available baud divisor values */
+	u32 BRGR_Value;		/* Calculated value for baud rate generator */
+	u32 CalcBaudRate;	/* Calculated baud rate */
+	u32 BaudError;		/* Diff between calculated and requested baud rate */
+	u32 Best_BRGR = 0;	/* Best value for baud rate generator */
+	u8 Best_BAUDDIV = 0;	/* Best value for baud divisor */
+	u32 Best_Error = 0xFFFFFFFF;
+	u32 PercentError;
+	u32 ModeReg;
+	u32 InputClk;
+
+	/*
+	 * Asserts validate the input arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(BaudRate <= XUARTPS_MAX_RATE);
+	Xil_AssertNonvoid(BaudRate >= XUARTPS_MIN_RATE);
+
+	/*
+	 * Make sure the baud rate is not impossilby large.
+	 * Fastest possible baud rate is Input Clock / 2.
+	 */
+	if ((BaudRate * 2) > InstancePtr->Config.InputClockHz) {
+		return XST_UART_BAUD_ERROR;
+	}
+	/*
+	 * Check whether the input clock is divided by 8
+	 */
+	ModeReg = XUartPs_ReadReg( InstancePtr->Config.BaseAddress,
+				 XUARTPS_MR_OFFSET);
+
+	InputClk = InstancePtr->Config.InputClockHz;
+	if(ModeReg & XUARTPS_MR_CLKSEL) {
+		InputClk = InstancePtr->Config.InputClockHz / 8;
+	}
+
+	/*
+	 * Determine the Baud divider. It can be 4to 254.
+	 * Loop through all possible combinations
+	 */
+	for (IterBAUDDIV = 4; IterBAUDDIV < 255; IterBAUDDIV++) {
+
+		/*
+		 * Calculate the value for BRGR register
+		 */
+		BRGR_Value = InputClk / (BaudRate * (IterBAUDDIV + 1));
+
+		/*
+		 * Calculate the baud rate from the BRGR value
+		 */
+		CalcBaudRate = InputClk/ (BRGR_Value * (IterBAUDDIV + 1));
+
+		/*
+		 * Avoid unsigned integer underflow
+		 */
+		if (BaudRate > CalcBaudRate) {
+			BaudError = BaudRate - CalcBaudRate;
+		}
+		else {
+			BaudError = CalcBaudRate - BaudRate;
+		}
+
+		/*
+		 * Find the calculated baud rate closest to requested baud rate.
+		 */
+		if (Best_Error > BaudError) {
+
+			Best_BRGR = BRGR_Value;
+			Best_BAUDDIV = IterBAUDDIV;
+			Best_Error = BaudError;
+		}
+	}
+
+	/*
+	 * Make sure the best error is not too large.
+	 */
+	PercentError = (Best_Error * 100) / BaudRate;
+	if (XUARTPS_MAX_BAUD_ERROR_RATE < PercentError) {
+		return XST_UART_BAUD_ERROR;
+	}
+
+	/*
+	 * Disable TX and RX to avoid glitches when setting the baud rate.
+	 */
+	XUartPs_DisableUart(InstancePtr);
+
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_BAUDGEN_OFFSET, Best_BRGR);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_BAUDDIV_OFFSET, Best_BAUDDIV);
+
+	/*
+	 * Enable device
+	 */
+	XUartPs_EnableUart(InstancePtr);
+
+	InstancePtr->BaudRate = BaudRate;
+
+	return XST_SUCCESS;
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function is a stub handler that is the default handler such that if the
+* application has not set the handler when interrupts are enabled, this
+* function will be called.
+*
+* @param	CallBackRef is unused by this function.
+* @param	Event is unused by this function.
+* @param	ByteCount is unused by this function.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void XUartPs_StubHandler(void *CallBackRef, u32 Event,
+				 unsigned int ByteCount)
+{
+	(void) CallBackRef;
+	(void) Event;
+	(void) ByteCount;
+	/*
+	 * Assert occurs always since this is a stub and should never be called
+	 */
+	Xil_AssertVoidAlways();
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps.h
new file mode 100644
index 000000000..4687bbe1f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps.h
@@ -0,0 +1,513 @@
+/*****************************************************************************
+*
+* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+*****************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps.h
+*
+* This driver supports the following features:
+*
+* - Dynamic data format (baud rate, data bits, stop bits, parity)
+* - Polled mode
+* - Interrupt driven mode
+* - Transmit and receive FIFOs (32 byte FIFO depth)
+* - Access to the external modem control lines
+*
+* Initialization & Configuration
+*
+* The XUartPs_Config structure is used by the driver to configure itself.
+* Fields inside this structure are properties of XUartPs based on its hardware
+* build.
+*
+* To support multiple runtime loading and initialization strategies employed
+* by various operating systems, the driver instance can be initialized in the
+* following way:
+*
+*   - XUartPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+*	 configuration structure provided by the caller. If running in a system
+*	 with address translation, the parameter EffectiveAddr should be the
+* 	  virtual address.
+*
+* Baud Rate
+*
+* The UART has an internal baud rate generator, which furnishes the baud rate
+* clock for both the receiver and the transmitter. Ther input clock frequency
+* can be either the master clock or the master clock divided by 8, configured
+* through the mode register.
+*
+* Accompanied with the baud rate divider register, the baud rate is determined
+* by:
+* 
+*	baud_rate = input_clock / (bgen * (bdiv + 1)
+* 

+* where bgen is the value of the baud rate generator, and bdiv is the value of
+* baud rate divider.
+*
+* Interrupts
+*
+* The FIFOs are not flushed when the driver is initialized, but a function is
+* provided to allow the user to reset the FIFOs if desired.
+*
+* The driver defaults to no interrupts at initialization such that interrupts
+* must be enabled if desired. An interrupt is generated for one of the
+* following conditions.
+*
+* - A change in the modem signals
+* - Data in the receive FIFO for a configuable time without receiver activity
+* - A parity error
+* - A framing error
+* - An overrun error
+* - Transmit FIFO is full
+* - Transmit FIFO is empty
+* - Receive FIFO is full
+* - Receive FIFO is empty
+* - Data in the receive FIFO equal to the receive threshold
+*
+* The application can control which interrupts are enabled using the
+* XUartPs_SetInterruptMask() function.
+*
+* In order to use interrupts, it is necessary for the user to connect the
+* driver interrupt handler, XUartPs_InterruptHandler(), to the interrupt
+* system of the application. A separate handler should be provided by the
+* application to communicate with the interrupt system, and conduct
+* application specific interrupt handling. An application registers its own
+* handler through the XUartPs_SetHandler() function.
+*
+* Data Transfer
+*
+* The functions, XUartPs_Send() and XUartPs_Recv(), are provided in the
+* driver to allow data to be sent and received. They can be used in either
+* polled or interrupt mode.
+*
+* @note
+*
+* The default configuration for the UART after initialization is:
+*
+* - 9,600 bps or XPAR_DFT_BAUDRATE if defined
+* - 8 data bits
+* - 1 stop bit
+* - no parity
+* - FIFO's are enabled with a receive threshold of 8 bytes
+* - The RX timeout is enabled with a timeout of 1 (4 char times)
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00a	drg/jz 01/12/10 First Release
+* 1.00a sdm    09/27/11 Fixed compiler warnings and also a bug
+*		        in XUartPs_SetFlowDelay where the value was not
+*			being written to the register.
+* 1.01a sdm    12/20/11 Removed the InputClockHz parameter from the XUartPs
+*			instance structure and the driver is updated to use
+*			InputClockHz parameter from the XUartPs_Config config
+*			structure.
+*			Added a parameter to XUartPs_Config structure which
+*			specifies whether the user has selected Modem pins
+*			to be connected to MIO or FMIO.
+*			Added the tcl file to generate the xparameters.h
+* 1.02a sg     05/16/12	Changed XUARTPS_RXWM_MASK to 0x3F for CR 652540 fix.
+* 1.03a sg     07/16/12 Updated XUARTPS_FORMAT_7_BITS and XUARTPS_FORMAT_6_BITS
+*			with the correct values for CR 666724
+* 			Added defines for XUARTPS_IXR_TOVR,  XUARTPS_IXR_TNFUL
+*			and XUARTPS_IXR_TTRIG.
+*			Modified the name of these defines
+*			XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+*			XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+*			XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+*			XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk     08/22/13 Added API for uart reset and related
+*			constant definitions.
+* 2.0   hk      03/07/14 Version number revised.
+* 2.1   hk     04/16/14 Change XUARTPS_MAX_RATE to 921600. CR# 780625.
+*
+* 

+*
+*****************************************************************************/
+
+#ifndef XUARTPS_H		/* prevent circular inclusions */
+#define XUARTPS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xuartps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constants indicate the max and min baud rates and these
+ * numbers are based only on the testing that has been done. The hardware
+ * is capable of other baud rates.
+ */
+#define XUARTPS_MAX_RATE	 921600
+#define XUARTPS_MIN_RATE	 110
+
+#define XUARTPS_DFT_BAUDRATE  115200   /* Default baud rate */
+
+/** @name Configuration options
+ * @{
+ */
+/**
+ * These constants specify the options that may be set or retrieved
+ * with the driver, each is a unique bit mask such that multiple options
+ * may be specified.  These constants indicate the available options
+ * in active state.
+ *
+ */
+
+#define XUARTPS_OPTION_SET_BREAK	0x0080 /**< Starts break transmission */
+#define XUARTPS_OPTION_STOP_BREAK	0x0040 /**< Stops break transmission */
+#define XUARTPS_OPTION_RESET_TMOUT	0x0020 /**< Reset the receive timeout */
+#define XUARTPS_OPTION_RESET_TX		0x0010 /**< Reset the transmitter */
+#define XUARTPS_OPTION_RESET_RX		0x0008 /**< Reset the receiver */
+#define XUARTPS_OPTION_ASSERT_RTS	0x0004 /**< Assert the RTS bit */
+#define XUARTPS_OPTION_ASSERT_DTR	0x0002 /**< Assert the DTR bit */
+#define XUARTPS_OPTION_SET_FCM		0x0001 /**< Turn on flow control mode */
+/*@}*/
+
+
+/** @name Channel Operational Mode
+ *
+ * The UART can operate in one of four modes: Normal, Local Loopback, Remote
+ * Loopback, or automatic echo.
+ *
+ * @{
+ */
+
+#define XUARTPS_OPER_MODE_NORMAL	0x00	/**< Normal Mode */
+#define XUARTPS_OPER_MODE_AUTO_ECHO	0x01	/**< Auto Echo Mode */
+#define XUARTPS_OPER_MODE_LOCAL_LOOP	0x02	/**< Local Loopback Mode */
+#define XUARTPS_OPER_MODE_REMOTE_LOOP	0x03	/**< Remote Loopback Mode */
+
+/* @} */
+
+/** @name Data format values
+ *
+ * These constants specify the data format that the driver supports.
+ * The data format includes the number of data bits, the number of stop
+ * bits and parity.
+ *
+ * @{
+ */
+#define XUARTPS_FORMAT_8_BITS		0 /**< 8 data bits */
+#define XUARTPS_FORMAT_7_BITS		2 /**< 7 data bits */
+#define XUARTPS_FORMAT_6_BITS		3 /**< 6 data bits */
+
+#define XUARTPS_FORMAT_NO_PARITY	4 /**< No parity */
+#define XUARTPS_FORMAT_MARK_PARITY	3 /**< Mark parity */
+#define XUARTPS_FORMAT_SPACE_PARITY	2 /**< parity */
+#define XUARTPS_FORMAT_ODD_PARITY	1 /**< Odd parity */
+#define XUARTPS_FORMAT_EVEN_PARITY	0 /**< Even parity */
+
+#define XUARTPS_FORMAT_2_STOP_BIT	2 /**< 2 stop bits */
+#define XUARTPS_FORMAT_1_5_STOP_BIT	1 /**< 1.5 stop bits */
+#define XUARTPS_FORMAT_1_STOP_BIT	0 /**< 1 stop bit */
+/*@}*/
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that an application can handle
+ * using its specific handler function. Note that these constants are not bit
+ * mask, so only one event can be passed to an application at a time.
+ *
+ * @{
+ */
+#define XUARTPS_EVENT_RECV_DATA		1 /**< Data receiving done */
+#define XUARTPS_EVENT_RECV_TOUT		2 /**< A receive timeout occurred */
+#define XUARTPS_EVENT_SENT_DATA		3 /**< Data transmission done */
+#define XUARTPS_EVENT_RECV_ERROR	4 /**< A receive error detected */
+#define XUARTPS_EVENT_MODEM		5 /**< Modem status changed */
+/*@}*/
+
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;	 /**< Unique ID  of device */
+	u32 BaseAddress; /**< Base address of device (IPIF) */
+	u32 InputClockHz;/**< Input clock frequency */
+	int ModemPinsConnected; /** Specifies whether modem pins are connected
+				 *  to MIO or FMIO */
+} XUartPs_Config;
+
+/*
+ * Keep track of state information about a data buffer in the interrupt mode.
+ */
+typedef struct {
+	u8 *NextBytePtr;
+	unsigned int RequestedBytes;
+	unsigned int RemainingBytes;
+} XUartPsBuffer;
+
+/**
+ * Keep track of data format setting of a device.
+ */
+typedef struct {
+	u32 BaudRate;	/**< In bps, ie 1200 */
+	u32 DataBits;	/**< Number of data bits */
+	u32 Parity;	/**< Parity */
+	u8 StopBits;	/**< Number of stop bits */
+} XUartPsFormat;
+
+/******************************************************************************/
+/**
+ * This data type defines a handler that an application defines to communicate
+ * with interrupt system to retrieve state information about an application.
+ *
+ * @param	CallBackRef is a callback reference passed in by the upper layer
+ *		when setting the handler, and is passed back to the upper layer
+ *		when the handler is called. It is used to find the device driver
+ *		instance.
+ * @param	Event contains one of the event constants indicating events that
+ *		have occurred.
+ * @param	EventData contains the number of bytes sent or received at the
+ *		time of the call for send and receive events and contains the
+ *		modem status for modem events.
+ *
+ ******************************************************************************/
+typedef void (*XUartPs_Handler) (void *CallBackRef, u32 Event,
+				  unsigned int EventData);
+
+/**
+ * The XUartPs driver instance data structure. A pointer to an instance data
+ * structure is passed around by functions to refer to a specific driver
+ * instance.
+ */
+typedef struct {
+	XUartPs_Config Config;	/* Configuration data structure */
+	u32 InputClockHz;	/* Input clock frequency */
+	u32 IsReady;		/* Device is initialized and ready */
+	u32 BaudRate;		/* Current baud rate */
+
+	XUartPsBuffer SendBuffer;
+	XUartPsBuffer ReceiveBuffer;
+
+	XUartPs_Handler Handler;
+	void *CallBackRef;	/* Callback reference for event handler */
+} XUartPs;
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* Get the UART Channel Status Register.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u16 XUartPs_GetChannelStatus(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_GetChannelStatus(InstancePtr)   \
+	Xil_In32(((InstancePtr)->Config.BaseAddress) + XUARTPS_SR_OFFSET)
+
+/****************************************************************************/
+/**
+* Get the UART Mode Control Register.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XUartPs_GetControl(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_GetModeControl(InstancePtr)  \
+	Xil_In32(((InstancePtr)->Config.BaseAddress) + XUARTPS_CR_OFFSET)
+
+/****************************************************************************/
+/**
+* Set the UART Mode Control Register.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*	void XUartPs_SetModeControl(XUartPs *InstancePtr, u16 RegisterValue)
+*
+******************************************************************************/
+#define XUartPs_SetModeControl(InstancePtr, RegisterValue) \
+   Xil_Out32(((InstancePtr)->Config.BaseAddress) + XUARTPS_CR_OFFSET, \
+			(RegisterValue))
+
+/****************************************************************************/
+/**
+* Enable the transmitter and receiver of the UART.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XUartPs_EnableUart(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_EnableUart(InstancePtr) \
+   Xil_Out32(((InstancePtr)->Config.BaseAddress + XUARTPS_CR_OFFSET), \
+	  ((Xil_In32((InstancePtr)->Config.BaseAddress + XUARTPS_CR_OFFSET) & \
+	  ~XUARTPS_CR_EN_DIS_MASK) | (XUARTPS_CR_RX_EN | XUARTPS_CR_TX_EN)))
+
+/****************************************************************************/
+/**
+* Disable the transmitter and receiver of the UART.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XUartPs_DisableUart(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_DisableUart(InstancePtr) \
+   Xil_Out32(((InstancePtr)->Config.BaseAddress + XUARTPS_CR_OFFSET), \
+	  (((Xil_In32((InstancePtr)->Config.BaseAddress + XUARTPS_CR_OFFSET)) & \
+	  ~XUARTPS_CR_EN_DIS_MASK) | (XUARTPS_CR_RX_DIS | XUARTPS_CR_TX_DIS)))
+
+/****************************************************************************/
+/**
+* Determine if the transmitter FIFO is empty.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*		- TRUE if a byte can be sent
+*		- FALSE if the Transmitter Fifo is not empty
+*
+* @note		C-Style signature:
+*		u32 XUartPs_IsTransmitEmpty(XUartPs InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_IsTransmitEmpty(InstancePtr)				\
+	((Xil_In32(((InstancePtr)->Config.BaseAddress) + XUARTPS_SR_OFFSET) & \
+	 XUARTPS_SR_TXEMPTY) == XUARTPS_SR_TXEMPTY)
+
+
+/************************** Function Prototypes *****************************/
+
+/*
+ * Static lookup function implemented in xuartps_sinit.c
+ */
+XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Interface functions implemented in xuartps.c
+ */
+int XUartPs_CfgInitialize(XUartPs *InstancePtr,
+				   XUartPs_Config * Config, u32 EffectiveAddr);
+
+unsigned int XUartPs_Send(XUartPs *InstancePtr, u8 *BufferPtr,
+			   unsigned int NumBytes);
+
+unsigned int XUartPs_Recv(XUartPs *InstancePtr, u8 *BufferPtr,
+			   unsigned int NumBytes);
+
+int XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate);
+
+/*
+ * Options functions in xuartps_options.c
+ */
+void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options);
+
+u16 XUartPs_GetOptions(XUartPs *InstancePtr);
+
+void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel);
+
+u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr);
+
+u16 XUartPs_GetModemStatus(XUartPs *InstancePtr);
+
+u32 XUartPs_IsSending(XUartPs *InstancePtr);
+
+u8 XUartPs_GetOperMode(XUartPs *InstancePtr);
+
+void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode);
+
+u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr);
+
+void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue);
+
+u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr);
+
+void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout);
+
+int XUartPs_SetDataFormat(XUartPs *InstancePtr, XUartPsFormat * Format);
+void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * Format);
+
+/*
+ * interrupt functions in xuartps_intr.c
+ */
+u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr);
+
+void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask);
+
+void XUartPs_InterruptHandler(XUartPs *InstancePtr);
+
+void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
+			 void *CallBackRef);
+
+/*
+ * self-test functions in xuartps_selftest.c
+ */
+int XUartPs_SelfTest(XUartPs *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps_g.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps_g.c
new file mode 100644
index 000000000..777bca4b5
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps_g.c
@@ -0,0 +1,33 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSM.
+* Version: 
+* DO NOT EDIT.
+*
+*  v (64-bit)
+SW Build (by ) on 
+Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xuartps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XUartPs_Config XUartPs_ConfigTable[] =
+{
+	{
+		XPAR_PS7_UART_1_DEVICE_ID,
+		XPAR_PS7_UART_1_BASEADDR,
+		XPAR_PS7_UART_1_UART_CLK_FREQ_HZ,
+		XPAR_PS7_UART_1_HAS_MODEM
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps_hw.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps_hw.c
new file mode 100644
index 000000000..b7fe10ab8
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps_hw.c
@@ -0,0 +1,201 @@
+/*****************************************************************************
+*
+* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+*****************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_hw.c
+*
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	drg/jz 01/12/10 First Release
+* 1.05a hk     08/22/13 Added reset function
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xuartps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* This function sends one byte using the device. This function operates in
+* polled mode and blocks until the data has been put into the TX FIFO register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	Data contains the byte to be sent.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SendByte(u32 BaseAddress, u8 Data)
+{
+		/*
+		 * Wait until there is space in TX FIFO
+		 */
+		while (XUartPs_IsTransmitFull(BaseAddress));
+
+		/*
+		 * Write the byte into the TX FIFO
+		 */
+		XUartPs_WriteReg(BaseAddress, XUARTPS_FIFO_OFFSET, Data);
+}
+
+/****************************************************************************/
+/**
+*
+* This function receives a byte from the device. It operates in polled mode
+* and blocks until a byte has received.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	The data byte received.
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_RecvByte(u32 BaseAddress)
+{
+		/*
+		 * Wait until there is data
+		 */
+		while (!XUartPs_IsReceiveData(BaseAddress));
+
+		/*
+		 * Return the byte received
+		 */
+		return (XUartPs_ReadReg(BaseAddress, XUARTPS_FIFO_OFFSET));
+}
+
+/****************************************************************************/
+/**
+*
+* This function resets UART
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	None
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_ResetHw(u32 BaseAddress)
+{
+
+	/*
+	 * Disable interrupts
+	 */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_IDR_OFFSET, XUARTPS_IXR_MASK);
+
+	/*
+	 * Disable receive and transmit
+	 */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+				XUARTPS_CR_RX_DIS | XUARTPS_CR_TX_DIS);
+
+	/*
+	 * Software reset of receive and transmit
+	 * This clears the FIFO.
+	 */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+				XUARTPS_CR_TXRST | XUARTPS_CR_RXRST);
+
+	/*
+	 * Clear status flags - SW reset wont clear sticky flags.
+	 */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_ISR_OFFSET, XUARTPS_IXR_MASK);
+
+	/*
+	 * Mode register reset value : All zeroes
+	 * Normal mode, even parity, 1 stop bit
+	 */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_MR_OFFSET,
+				XUARTPS_MR_CHMODE_NORM);
+
+	/*
+	 * Rx and TX trigger register reset values
+	 */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_RXWM_OFFSET,
+				XUARTPS_RXWM_RESET_VAL);
+	XUartPs_WriteReg(BaseAddress, XUARTPS_TXWM_OFFSET,
+				XUARTPS_TXWM_RESET_VAL);
+
+	/*
+	 * Rx timeout disabled by default
+	 */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_RXTOUT_OFFSET,
+				XUARTPS_RXTOUT_DISABLE);
+
+	/*
+	 * Baud rate generator and dividor reset values
+	 */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDGEN_OFFSET,
+				XUARTPS_BAUDGEN_RESET_VAL);
+	XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDDIV_OFFSET,
+				XUARTPS_BAUDDIV_RESET_VAL);
+
+	/*
+	 * Control register reset value -
+	 * RX and TX are disable by default
+	 */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+				XUARTPS_CR_RX_DIS | XUARTPS_CR_TX_DIS |
+				XUARTPS_CR_STOPBRK);
+
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps_hw.h
new file mode 100644
index 000000000..768e38027
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps_hw.h
@@ -0,0 +1,432 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xuartps_hw.h
+*
+* This header file contains the hardware interface of an XUartPs device.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	drg/jz 01/12/10 First Release
+* 1.03a sg     09/04/12 Added defines for XUARTPS_IXR_TOVR,  XUARTPS_IXR_TNFUL
+*			and XUARTPS_IXR_TTRIG.
+*			Modified the names of these defines
+*			XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+*			XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+*			XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+*			XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk     08/22/13 Added prototype for uart reset and related
+*			constant definitions.
+*
+* 

+*
+******************************************************************************/
+#ifndef XUARTPS_HW_H		/* prevent circular inclusions */
+#define XUARTPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the UART.
+ * @{
+ */
+#define XUARTPS_CR_OFFSET	0x00  /**< Control Register [8:0] */
+#define XUARTPS_MR_OFFSET	0x04  /**< Mode Register [9:0] */
+#define XUARTPS_IER_OFFSET	0x08  /**< Interrupt Enable [12:0] */
+#define XUARTPS_IDR_OFFSET	0x0C  /**< Interrupt Disable [12:0] */
+#define XUARTPS_IMR_OFFSET	0x10  /**< Interrupt Mask [12:0] */
+#define XUARTPS_ISR_OFFSET	0x14  /**< Interrupt Status [12:0]*/
+#define XUARTPS_BAUDGEN_OFFSET	0x18  /**< Baud Rate Generator [15:0] */
+#define XUARTPS_RXTOUT_OFFSET	0x1C  /**< RX Timeout [7:0] */
+#define XUARTPS_RXWM_OFFSET	0x20  /**< RX FIFO Trigger Level [5:0] */
+#define XUARTPS_MODEMCR_OFFSET	0x24  /**< Modem Control [5:0] */
+#define XUARTPS_MODEMSR_OFFSET	0x28  /**< Modem Status [8:0] */
+#define XUARTPS_SR_OFFSET	0x2C  /**< Channel Status [14:0] */
+#define XUARTPS_FIFO_OFFSET	0x30  /**< FIFO [7:0] */
+#define XUARTPS_BAUDDIV_OFFSET	0x34  /**< Baud Rate Divider [7:0] */
+#define XUARTPS_FLOWDEL_OFFSET	0x38  /**< Flow Delay [5:0] */
+#define XUARTPS_TXWM_OFFSET	0x44  /**< TX FIFO Trigger Level [5:0] */
+/* @} */
+
+/** @name Control Register
+ *
+ * The Control register (CR) controls the major functions of the device.
+ *
+ * Control Register Bit Definition
+ */
+
+#define XUARTPS_CR_STOPBRK	0x00000100  /**< Stop transmission of break */
+#define XUARTPS_CR_STARTBRK	0x00000080  /**< Set break */
+#define XUARTPS_CR_TORST	0x00000040  /**< RX timeout counter restart */
+#define XUARTPS_CR_TX_DIS	0x00000020  /**< TX disabled. */
+#define XUARTPS_CR_TX_EN	0x00000010  /**< TX enabled */
+#define XUARTPS_CR_RX_DIS	0x00000008  /**< RX disabled. */
+#define XUARTPS_CR_RX_EN	0x00000004  /**< RX enabled */
+#define XUARTPS_CR_EN_DIS_MASK	0x0000003C  /**< Enable/disable Mask */
+#define XUARTPS_CR_TXRST	0x00000002  /**< TX logic reset */
+#define XUARTPS_CR_RXRST	0x00000001  /**< RX logic reset */
+/* @}*/
+
+
+/** @name Mode Register
+ *
+ * The mode register (MR) defines the mode of transfer as well as the data
+ * format. If this register is modified during transmission or reception,
+ * data validity cannot be guaranteed.
+ *
+ * Mode Register Bit Definition
+ * @{
+ */
+#define XUARTPS_MR_CCLK			0x00000400 /**< Input clock selection */
+#define XUARTPS_MR_CHMODE_R_LOOP	0x00000300 /**< Remote loopback mode */
+#define XUARTPS_MR_CHMODE_L_LOOP	0x00000200 /**< Local loopback mode */
+#define XUARTPS_MR_CHMODE_ECHO		0x00000100 /**< Auto echo mode */
+#define XUARTPS_MR_CHMODE_NORM		0x00000000 /**< Normal mode */
+#define XUARTPS_MR_CHMODE_SHIFT			8  /**< Mode shift */
+#define XUARTPS_MR_CHMODE_MASK		0x00000300 /**< Mode mask */
+#define XUARTPS_MR_STOPMODE_2_BIT	0x00000080 /**< 2 stop bits */
+#define XUARTPS_MR_STOPMODE_1_5_BIT	0x00000040 /**< 1.5 stop bits */
+#define XUARTPS_MR_STOPMODE_1_BIT	0x00000000 /**< 1 stop bit */
+#define XUARTPS_MR_STOPMODE_SHIFT		6  /**< Stop bits shift */
+#define XUARTPS_MR_STOPMODE_MASK	0x000000A0 /**< Stop bits mask */
+#define XUARTPS_MR_PARITY_NONE		0x00000020 /**< No parity mode */
+#define XUARTPS_MR_PARITY_MARK		0x00000018 /**< Mark parity mode */
+#define XUARTPS_MR_PARITY_SPACE		0x00000010 /**< Space parity mode */
+#define XUARTPS_MR_PARITY_ODD		0x00000008 /**< Odd parity mode */
+#define XUARTPS_MR_PARITY_EVEN		0x00000000 /**< Even parity mode */
+#define XUARTPS_MR_PARITY_SHIFT			3  /**< Parity setting shift */
+#define XUARTPS_MR_PARITY_MASK		0x00000038 /**< Parity mask */
+#define XUARTPS_MR_CHARLEN_6_BIT	0x00000006 /**< 6 bits data */
+#define XUARTPS_MR_CHARLEN_7_BIT	0x00000004 /**< 7 bits data */
+#define XUARTPS_MR_CHARLEN_8_BIT	0x00000000 /**< 8 bits data */
+#define XUARTPS_MR_CHARLEN_SHIFT		1  /**< Data Length shift */
+#define XUARTPS_MR_CHARLEN_MASK		0x00000006 /**< Data length mask */
+#define XUARTPS_MR_CLKSEL		0x00000001 /**< Input clock selection */
+/* @} */
+
+
+/** @name Interrupt Registers
+ *
+ * Interrupt control logic uses the interrupt enable register (IER) and the
+ * interrupt disable register (IDR) to set the value of the bits in the
+ * interrupt mask register (IMR). The IMR determines whether to pass an
+ * interrupt to the interrupt status register (ISR).
+ * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
+ * interrupt. IMR and ISR are read only, and IER and IDR are write only.
+ * Reading either IER or IDR returns 0x00.
+ *
+ * All four registers have the same bit definitions.
+ *
+ * @{
+ */
+#define XUARTPS_IXR_TOVR	0x00001000 /**< Tx FIFO Overflow interrupt */
+#define XUARTPS_IXR_TNFUL	0x00000800 /**< Tx FIFO Nearly Full interrupt */
+#define XUARTPS_IXR_TTRIG	0x00000400 /**< Tx Trig interrupt */
+#define XUARTPS_IXR_DMS		0x00000200 /**< Modem status change interrupt */
+#define XUARTPS_IXR_TOUT	0x00000100 /**< Timeout error interrupt */
+#define XUARTPS_IXR_PARITY 	0x00000080 /**< Parity error interrupt */
+#define XUARTPS_IXR_FRAMING	0x00000040 /**< Framing error interrupt */
+#define XUARTPS_IXR_OVER	0x00000020 /**< Overrun error interrupt */
+#define XUARTPS_IXR_TXFULL 	0x00000010 /**< TX FIFO full interrupt. */
+#define XUARTPS_IXR_TXEMPTY	0x00000008 /**< TX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXFULL 	0x00000004 /**< RX FIFO full interrupt. */
+#define XUARTPS_IXR_RXEMPTY	0x00000002 /**< RX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXOVR  	0x00000001 /**< RX FIFO trigger interrupt. */
+#define XUARTPS_IXR_MASK	0x00001FFF /**< Valid bit mask */
+/* @} */
+
+
+/** @name Baud Rate Generator Register
+ *
+ * The baud rate generator control register (BRGR) is a 16 bit register that
+ * controls the receiver bit sample clock and baud rate.
+ * Valid values are 1 - 65535.
+ *
+ * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
+ * in the MR register.
+ * @{
+ */
+#define XUARTPS_BAUDGEN_DISABLE		0x00000000 /**< Disable clock */
+#define XUARTPS_BAUDGEN_MASK		0x0000FFFF /**< Valid bits mask */
+#define XUARTPS_BAUDGEN_RESET_VAL	0x0000028B /**< Reset value */
+
+/** @name Baud Divisor Rate register
+ *
+ * The baud rate divider register (BDIV) controls how much the bit sample
+ * rate is divided by. It sets the baud rate.
+ * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored.
+ *
+ * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by
+ * the MR_CCLK bit in the MR register.
+ * @{
+ */
+#define XUARTPS_BAUDDIV_MASK        0x000000FF	/**< 8 bit baud divider mask */
+#define XUARTPS_BAUDDIV_RESET_VAL   0x0000000F	/**< Reset value */
+/* @} */
+
+
+/** @name Receiver Timeout Register
+ *
+ * Use the receiver timeout register (RTR) to detect an idle condition on
+ * the receiver data line.
+ *
+ * @{
+ */
+#define XUARTPS_RXTOUT_DISABLE		0x00000000  /**< Disable time out */
+#define XUARTPS_RXTOUT_MASK		0x000000FF  /**< Valid bits mask */
+
+/** @name Receiver FIFO Trigger Level Register
+ *
+ * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at
+ * which the RX FIFO triggers an interrupt event.
+ * @{
+ */
+
+#define XUARTPS_RXWM_DISABLE	0x00000000  /**< Disable RX trigger interrupt */
+#define XUARTPS_RXWM_MASK	0x0000003F  /**< Valid bits mask */
+#define XUARTPS_RXWM_RESET_VAL	0x00000020  /**< Reset value */
+/* @} */
+
+/** @name Transmit FIFO Trigger Level Register
+ *
+ * Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at
+ * which the TX FIFO triggers an interrupt event.
+ * @{
+ */
+
+#define XUARTPS_TXWM_MASK	0x0000003F  /**< Valid bits mask */
+#define XUARTPS_TXWM_RESET_VAL	0x00000020  /**< Reset value */
+/* @} */
+
+/** @name Modem Control Register
+ *
+ * This register (MODEMCR) controls the interface with the modem or data set,
+ * or a peripheral device emulating a modem.
+ *
+ * @{
+ */
+#define XUARTPS_MODEMCR_FCM	0x00000010  /**< Flow control mode */
+#define XUARTPS_MODEMCR_RTS	0x00000002  /**< Request to send */
+#define XUARTPS_MODEMCR_DTR	0x00000001  /**< Data terminal ready */
+/* @} */
+
+/** @name Modem Status Register
+ *
+ * This register (MODEMSR) indicates the current state of the control lines
+ * from a modem, or another peripheral device, to the CPU. In addition, four
+ * bits of the modem status register provide change information. These bits
+ * are set to a logic 1 whenever a control input from the modem changes state.
+ *
+ * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem
+ * status interrupt is generated and this is reflected in the modem status
+ * register.
+ *
+ * @{
+ */
+#define XUARTPS_MODEMSR_FCMS	0x00000100  /**< Flow control mode (FCMS) */
+#define XUARTPS_MODEMSR_DCD	0x00000080  /**< Complement of DCD input */
+#define XUARTPS_MODEMSR_RI	0x00000040  /**< Complement of RI input */
+#define XUARTPS_MODEMSR_DSR	0x00000020  /**< Complement of DSR input */
+#define XUARTPS_MODEMSR_CTS	0x00000010  /**< Complement of CTS input */
+#define XUARTPS_MODEMSR_DDCD	0x00000008  /**< Delta DCD indicator */
+#define XUARTPS_MODEMSR_TERI	0x00000004  /**< Trailing Edge Ring Indicator */
+#define XUARTPS_MODEMSR_DDSR	0x00000002  /**< Change of DSR */
+#define XUARTPS_MODEMSR_DCTS	0x00000001  /**< Change of CTS */
+/* @} */
+
+/** @name Channel Status Register
+ *
+ * The channel status register (CSR) is provided to enable the control logic
+ * to monitor the status of bits in the channel interrupt status register,
+ * even if these are masked out by the interrupt mask register.
+ *
+ * @{
+ */
+#define XUARTPS_SR_TNFUL	0x00004000 /**< TX FIFO Nearly Full Status */
+#define XUARTPS_SR_TTRIG	0x00002000 /**< TX FIFO Trigger Status */
+#define XUARTPS_SR_FLOWDEL	0x00001000 /**< RX FIFO fill over flow delay */
+#define XUARTPS_SR_TACTIVE	0x00000800 /**< TX active */
+#define XUARTPS_SR_RACTIVE	0x00000400 /**< RX active */
+#define XUARTPS_SR_DMS		0x00000200 /**< Delta modem status change */
+#define XUARTPS_SR_TOUT		0x00000100 /**< RX timeout */
+#define XUARTPS_SR_PARITY	0x00000080 /**< RX parity error */
+#define XUARTPS_SR_FRAME	0x00000040 /**< RX frame error */
+#define XUARTPS_SR_OVER		0x00000020 /**< RX overflow error */
+#define XUARTPS_SR_TXFULL	0x00000010 /**< TX FIFO full */
+#define XUARTPS_SR_TXEMPTY	0x00000008 /**< TX FIFO empty */
+#define XUARTPS_SR_RXFULL	0x00000004 /**< RX FIFO full */
+#define XUARTPS_SR_RXEMPTY	0x00000002 /**< RX FIFO empty */
+#define XUARTPS_SR_RXOVR	0x00000001 /**< RX FIFO fill over trigger */
+/* @} */
+
+/** @name Flow Delay Register
+ *
+ * Operation of the flow delay register (FLOWDEL) is very similar to the
+ * receive FIFO trigger register. An internal trigger signal activates when the
+ * FIFO is filled to the level set by this register. This trigger will not
+ * cause an interrupt, although it can be read through the channel status
+ * register. In hardware flow control mode, RTS is deactivated when the trigger
+ * becomes active. RTS only resets when the FIFO level is four less than the
+ * level of the flow delay trigger and the flow delay trigger is not activated.
+ * A value less than 4 disables the flow delay.
+ * @{
+ */
+#define XUARTPS_FLOWDEL_MASK	XUARTPS_RXWM_MASK	/**< Valid bit mask */
+/* @} */
+
+
+
+/*
+ * Defines for backwards compatabilty, will be removed
+ * in the next version of the driver
+ */
+#define XUARTPS_MEDEMSR_DCDX  XUARTPS_MODEMSR_DDCD
+#define XUARTPS_MEDEMSR_RIX   XUARTPS_MODEMSR_TERI
+#define XUARTPS_MEDEMSR_DSRX  XUARTPS_MODEMSR_DDSR
+#define	XUARTPS_MEDEMSR_CTSX  XUARTPS_MODEMSR_DCTS
+
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+* Read a UART register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the base address of the
+*		device.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset)
+*
+******************************************************************************/
+#define XUartPs_ReadReg(BaseAddress, RegOffset) \
+	Xil_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write a UART register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the base address of the
+*		device.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XUartPs_WriteReg(u32 BaseAddress, int RegOffset,
+*						   u16 RegisterValue)
+*
+******************************************************************************/
+#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+	Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+/****************************************************************************/
+/**
+* Determine if there is receive data in the receiver and/or FIFO.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	TRUE if there is receive data, FALSE otherwise.
+*
+* @note		C-Style signature:
+*		u32 XUartPs_IsReceiveData(u32 BaseAddress)
+*
+******************************************************************************/
+#define XUartPs_IsReceiveData(BaseAddress)			 \
+	!((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & 	\
+	XUARTPS_SR_RXEMPTY) == XUARTPS_SR_RXEMPTY)
+
+/****************************************************************************/
+/**
+* Determine if a byte of data can be sent with the transmitter.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	TRUE if the TX FIFO is full, FALSE if a byte can be put in the
+*		FIFO.
+*
+* @note		C-Style signature:
+*		u32 XUartPs_IsTransmitFull(u32 BaseAddress)
+*
+******************************************************************************/
+#define XUartPs_IsTransmitFull(BaseAddress)			 \
+	((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & 	\
+	 XUARTPS_SR_TXFULL) == XUARTPS_SR_TXFULL)
+
+/************************** Function Prototypes ******************************/
+
+void XUartPs_SendByte(u32 BaseAddress, u8 Data);
+
+u8 XUartPs_RecvByte(u32 BaseAddress);
+
+void XUartPs_ResetHw(u32 BaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps_intr.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps_intr.c
new file mode 100644
index 000000000..5cfbd0e6f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps_intr.c
@@ -0,0 +1,452 @@
+/*****************************************************************************
+*
+* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+*****************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_intr.c
+*
+* This file contains the functions for interrupt handling
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00  drg/jz 01/13/10 First Release
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xuartps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+
+static void ReceiveDataHandler(XUartPs *InstancePtr);
+static void SendDataHandler(XUartPs *InstancePtr, u32 isrstatus);
+static void ReceiveErrorHandler(XUartPs *InstancePtr);
+static void ReceiveTimeoutHandler(XUartPs *InstancePtr);
+static void ModemHandler(XUartPs *InstancePtr);
+
+
+/* Internal function prototypes implemented in xuartps.c */
+extern unsigned int XUartPs_ReceiveBuffer(XUartPs *InstancePtr);
+extern unsigned int XUartPs_SendBuffer(XUartPs *InstancePtr);
+
+/************************** Variable Definitions ****************************/
+
+typedef void (*Handler)(XUartPs *InstancePtr);
+
+/****************************************************************************/
+/**
+*
+* This function gets the interrupt mask
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*		The current interrupt mask. The mask indicates which interupts
+*		are enabled.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr)
+{
+	/*
+	 * Assert validates the input argument
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	/*
+	 * Read the Interrupt Mask register
+	 */
+	return (XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+			 XUARTPS_IMR_OFFSET));
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the interrupt mask.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	Mask contains the interrupts to be enabled or disabled.
+*		A '1' enables an interupt, and a '0' disables.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask)
+{
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	Mask &= XUARTPS_IXR_MASK;
+
+	/*
+	 * Write the mask to the IER Register
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+		 XUARTPS_IER_OFFSET, Mask);
+
+	/*
+	 * Write the inverse of the Mask to the IDR register
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+		 XUARTPS_IDR_OFFSET, (~Mask));
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the handler that will be called when an event (interrupt)
+* occurs that needs application's attention.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	FuncPtr is the pointer to the callback function.
+* @param	CallBackRef is the upper layer callback reference passed back
+*		when the callback function is invoked.
+*
+* @return	None.
+*
+* @note
+*
+* There is no assert on the CallBackRef since the driver doesn't know what it
+* is (nor should it)
+*
+*****************************************************************************/
+void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
+		 void *CallBackRef)
+{
+	/*
+	 * Asserts validate the input arguments
+	 * CallBackRef not checked, no way to know what is valid
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FuncPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	InstancePtr->Handler = FuncPtr;
+	InstancePtr->CallBackRef = CallBackRef;
+}
+
+/****************************************************************************/
+/**
+*
+* This function is the interrupt handler for the driver.
+* It must be connected to an interrupt system by the application such that it
+* can be called when an interrupt occurs.
+*
+* @param	InstancePtr contains a pointer to the driver instance
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XUartPs_InterruptHandler(XUartPs *InstancePtr)
+{
+	u32 IsrStatus;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the interrupt ID register to determine which
+	 * interrupt is active
+	 */
+	IsrStatus = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_IMR_OFFSET);
+
+	IsrStatus &= XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_ISR_OFFSET);
+
+	/*
+	 * Dispatch an appropiate handler.
+	 */
+	if(0 != (IsrStatus & (XUARTPS_IXR_RXOVR | XUARTPS_IXR_RXEMPTY |
+				 XUARTPS_IXR_RXFULL))) {
+		/* Recieved data interrupt */
+		ReceiveDataHandler(InstancePtr);
+	}
+
+	if(0 != (IsrStatus & (XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_TXFULL))) {
+		/* Transmit data interrupt */
+		SendDataHandler(InstancePtr, IsrStatus);
+	}
+
+	if(0 != (IsrStatus & (XUARTPS_IXR_OVER | XUARTPS_IXR_FRAMING |
+				XUARTPS_IXR_PARITY))) {
+		/* Recieved Error Status interrupt */
+		ReceiveErrorHandler(InstancePtr);
+	}
+
+	if(0 != (IsrStatus & XUARTPS_IXR_TOUT )) {
+		/* Recieved Timeout interrupt */
+		ReceiveTimeoutHandler(InstancePtr);
+	}
+
+	if(0 != (IsrStatus & XUARTPS_IXR_DMS)) {
+		/* Modem status interrupt */
+		ModemHandler(InstancePtr);
+	}
+
+	/*
+	 * Clear the interrupt status.
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_ISR_OFFSET,
+		IsrStatus);
+
+}
+
+/****************************************************************************/
+/*
+*
+* This function handles interrupts for receive errors which include
+* overrun errors, framing errors, parity errors, and the break interrupt.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void ReceiveErrorHandler(XUartPs *InstancePtr)
+{
+	/*
+	 * If there are bytes still to be received in the specified buffer
+	 * go ahead and receive them. Removing bytes from the RX FIFO will
+	 * clear the interrupt.
+	 */
+	if (InstancePtr->ReceiveBuffer.RemainingBytes != 0) {
+		XUartPs_ReceiveBuffer(InstancePtr);
+	}
+
+	/*
+	 * Call the application handler to indicate that there is a receive
+	 * error or a break interrupt, if the application cares about the
+	 * error it call a function to get the last errors.
+	 */
+	InstancePtr->Handler(InstancePtr->CallBackRef,
+				XUARTPS_EVENT_RECV_ERROR,
+				(InstancePtr->ReceiveBuffer.RequestedBytes -
+				InstancePtr->ReceiveBuffer.RemainingBytes));
+
+}
+/****************************************************************************/
+/**
+*
+* This function handles the receive timeout interrupt. This interrupt occurs
+* whenever a number of bytes have been present in the RX FIFO and the receive
+* data line has been idle for at lease 4 or more character times, (the timeout
+* is set using XUartPs_SetrecvTimeout() function).
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void ReceiveTimeoutHandler(XUartPs *InstancePtr)
+{
+	u32 Event;
+
+	/*
+	 * If there are bytes still to be received in the specified buffer
+	 * go ahead and receive them. Removing bytes from the RX FIFO will
+	 * clear the interrupt.
+	 */
+	if (InstancePtr->ReceiveBuffer.RemainingBytes != 0) {
+		XUartPs_ReceiveBuffer(InstancePtr);
+	}
+
+	/*
+	 * If there are no more bytes to receive then indicate that this is
+	 * not a receive timeout but the end of the buffer reached, a timeout
+	 * normally occurs if # of bytes is not divisible by FIFO threshold,
+	 * don't rely on previous test of remaining bytes since receive
+	 * function updates it
+	 */
+	if (InstancePtr->ReceiveBuffer.RemainingBytes != 0) {
+		Event = XUARTPS_EVENT_RECV_TOUT;
+	} else {
+		Event = XUARTPS_EVENT_RECV_DATA;
+	}
+
+	/*
+	 * Call the application handler to indicate that there is a receive
+	 * timeout or data event
+	 */
+	InstancePtr->Handler(InstancePtr->CallBackRef, Event,
+				 InstancePtr->ReceiveBuffer.RequestedBytes -
+				 InstancePtr->ReceiveBuffer.RemainingBytes);
+
+}
+/****************************************************************************/
+/**
+*
+* This function handles the interrupt when data is in RX FIFO.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void ReceiveDataHandler(XUartPs *InstancePtr)
+{
+	/*
+	 * If there are bytes still to be received in the specified buffer
+	 * go ahead and receive them. Removing bytes from the RX FIFO will
+	 * clear the interrupt.
+	 */
+	 if (InstancePtr->ReceiveBuffer.RemainingBytes != 0) {
+		XUartPs_ReceiveBuffer(InstancePtr);
+	}
+
+
+	/* If the last byte of a message was received then call the application
+	 * handler, this code should not use an else from the previous check of
+	 * the number of bytes to receive because the call to receive the buffer
+	 * updates the bytes ramained
+	 */
+	if (InstancePtr->ReceiveBuffer.RemainingBytes == 0) {
+		InstancePtr->Handler(InstancePtr->CallBackRef,
+				XUARTPS_EVENT_RECV_DATA,
+				(InstancePtr->ReceiveBuffer.RequestedBytes -
+				InstancePtr->ReceiveBuffer.RemainingBytes));
+	}
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function handles the interrupt when data has been sent, the transmit
+* FIFO is empty (transmitter holding register).
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	IsrStatus is the register value for channel status register
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void SendDataHandler(XUartPs *InstancePtr, u32 IsrStatus)
+{
+
+	/*
+	 * If there are not bytes to be sent from the specified buffer then disable
+	 * the transmit interrupt so it will stop interrupting as it interrupts
+	 * any time the FIFO is empty
+	 */
+	if (InstancePtr->SendBuffer.RemainingBytes == 0) {
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XUARTPS_IDR_OFFSET,
+				(XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_TXFULL));
+
+		/* Call the application handler to indicate the sending is done */
+		InstancePtr->Handler(InstancePtr->CallBackRef,
+					XUARTPS_EVENT_SENT_DATA,
+					InstancePtr->SendBuffer.RequestedBytes -
+					InstancePtr->SendBuffer.RemainingBytes);
+	}
+
+	/*
+	 * If TX FIFO is empty, send more.
+	 */
+	else if(IsrStatus & XUARTPS_IXR_TXEMPTY) {
+		XUartPs_SendBuffer(InstancePtr);
+	}
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function handles modem interrupts.  It does not do any processing
+* except to call the application handler to indicate a modem event.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void ModemHandler(XUartPs *InstancePtr)
+{
+	u32 MsrRegister;
+
+	/*
+	 * Read the modem status register so that the interrupt is acknowledged
+	 * and it can be passed to the callback handler with the event
+	 */
+	MsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+			  XUARTPS_MODEMSR_OFFSET);
+
+	/*
+	 * Call the application handler to indicate the modem status changed,
+	 * passing the modem status and the event data in the call
+	 */
+	InstancePtr->Handler(InstancePtr->CallBackRef,
+				  XUARTPS_EVENT_MODEM,
+				  MsrRegister);
+
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps_options.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps_options.c
new file mode 100644
index 000000000..6d7688df5
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps_options.c
@@ -0,0 +1,805 @@
+/*****************************************************************************
+*
+* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+*****************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_options.c
+*
+* The implementation of the options functions for the XUartPs driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00  drg/jz 01/13/10 First Release
+* 1.00  sdm    09/27/11 Fixed a bug in XUartPs_SetFlowDelay where the input
+*			value was not being written to the register.
+*
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xuartps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+/*
+ * The following data type is a map from an option to the offset in the
+ * register to which it belongs as well as its bit mask in that register.
+ */
+typedef struct {
+	u16 Option;
+	u16 RegisterOffset;
+	u32 Mask;
+} Mapping;
+
+/*
+ * Create the table which contains options which are to be processed to get/set
+ * the options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+
+static Mapping OptionsTable[] = {
+	{XUARTPS_OPTION_SET_BREAK, XUARTPS_CR_OFFSET, XUARTPS_CR_STARTBRK},
+	{XUARTPS_OPTION_STOP_BREAK, XUARTPS_CR_OFFSET, XUARTPS_CR_STOPBRK},
+	{XUARTPS_OPTION_RESET_TMOUT, XUARTPS_CR_OFFSET, XUARTPS_CR_TORST},
+	{XUARTPS_OPTION_RESET_TX, XUARTPS_CR_OFFSET, XUARTPS_CR_TXRST},
+	{XUARTPS_OPTION_RESET_RX, XUARTPS_CR_OFFSET, XUARTPS_CR_RXRST},
+	{XUARTPS_OPTION_ASSERT_RTS, XUARTPS_MODEMCR_OFFSET,
+	 XUARTPS_MODEMCR_RTS},
+	{XUARTPS_OPTION_ASSERT_DTR, XUARTPS_MODEMCR_OFFSET,
+	 XUARTPS_MODEMCR_DTR},
+	{XUARTPS_OPTION_SET_FCM, XUARTPS_MODEMCR_OFFSET, XUARTPS_MODEMCR_FCM}
+};
+
+/* Create a constant for the number of entries in the table */
+
+#define XUARTPS_NUM_OPTIONS	  (sizeof(OptionsTable) / sizeof(Mapping))
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* Gets the options for the specified driver instance. The options are
+* implemented as bit masks such that multiple options may be enabled or
+* disabled simulataneously.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The current options for the UART. The optionss are bit masks that are
+* contained in the file xuartps.h and named XUARTPS_OPTION_*.
+*
+* @note		None.
+*
+*****************************************************************************/
+u16 XUartPs_GetOptions(XUartPs *InstancePtr)
+{
+	u16 Options = 0;
+	u32 Register;
+	unsigned int Index;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Loop thru the options table to map the physical options in the
+	 * registers of the UART to the logical options to be returned
+	 */
+	for (Index = 0; Index < XUARTPS_NUM_OPTIONS; Index++) {
+		Register = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						 OptionsTable[Index].
+						 RegisterOffset);
+
+		/*
+		 * If the bit in the register which correlates to the option
+		 * is set, then set the corresponding bit in the options,
+		 * ignoring any bits which are zero since the options variable
+		 * is initialized to zero
+		 */
+		if (Register & OptionsTable[Index].Mask) {
+			Options |= OptionsTable[Index].Option;
+		}
+	}
+
+	return Options;
+}
+
+/****************************************************************************/
+/**
+*
+* Sets the options for the specified driver instance. The options are
+* implemented as bit masks such that multiple options may be enabled or
+* disabled simultaneously.
+*
+* The GetOptions function may be called to retrieve the currently enabled
+* options. The result is ORed in the desired new settings to be enabled and
+* ANDed with the inverse to clear the settings to be disabled. The resulting
+* value is then used as the options for the SetOption function call.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	Options contains the options to be set which are bit masks
+*		contained in the file xuartps.h and named XUARTPS_OPTION_*.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options)
+{
+	unsigned int Index;
+	u32 Register;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Loop thru the options table to map the logical options to the
+	 * physical options in the registers of the UART.
+	 */
+	for (Index = 0; Index < XUARTPS_NUM_OPTIONS; Index++) {
+
+		/*
+		 * Read the register which contains option so that the register
+		 * can be changed without destoying any other bits of the
+		 * register.
+		 */
+		Register = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						 OptionsTable[Index].
+						 RegisterOffset);
+
+		/*
+		 * If the option is set in the input, then set the corresponding
+		 * bit in the specified register, otherwise clear the bit in
+		 * the register.
+		 */
+		if (Options & OptionsTable[Index].Option) {
+			Register |= OptionsTable[Index].Mask;
+		}
+		else {
+			Register &= ~OptionsTable[Index].Mask;
+		}
+
+		/* Write the new value to the register to set the option */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   OptionsTable[Index].RegisterOffset,
+				   Register);
+	}
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the receive FIFO trigger level. The receive trigger
+* level indicates the number of bytes in the receive FIFO that cause a receive
+* data event (interrupt) to be generated.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	The current receive FIFO trigger level. This is a value
+*		from 0-31.
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr)
+{
+	u8 RtrigRegister;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the value of the FIFO control register so that the threshold
+	 * can be retrieved, this read takes special register processing
+	 */
+	RtrigRegister = (u8) XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						   XUARTPS_RXWM_OFFSET);
+
+	/* Return only the trigger level from the register value */
+
+	return (RtrigRegister & XUARTPS_RXWM_MASK);
+}
+
+/****************************************************************************/
+/**
+*
+* This functions sets the receive FIFO trigger level. The receive trigger
+* level specifies the number of bytes in the receive FIFO that cause a receive
+* data event (interrupt) to be generated.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	TriggerLevel contains the trigger level to set.
+*
+* @return	None
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel)
+{
+	u32 RtrigRegister;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(TriggerLevel <= XUARTPS_RXWM_MASK);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	RtrigRegister = TriggerLevel & XUARTPS_RXWM_MASK;
+
+	/*
+	 * Write the new value for the FIFO control register to it such that the
+	 * threshold is changed
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_RXWM_OFFSET, RtrigRegister);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the modem status from the specified UART. The modem
+* status indicates any changes of the modem signals. This function allows
+* the modem status to be read in a polled mode. The modem status is updated
+* whenever it is read such that reading it twice may not yield the same
+* results.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The modem status which are bit masks that are contained in the file
+* xuartps.h and named XUARTPS_MODEM_*.
+*
+* @note
+*
+* The bit masks used for the modem status are the exact bits of the modem
+* status register with no abstraction.
+*
+*****************************************************************************/
+u16 XUartPs_GetModemStatus(XUartPs *InstancePtr)
+{
+	u32 ModemStatusRegister;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Read the modem status register to return
+	 */
+	ModemStatusRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XUARTPS_MODEMSR_OFFSET);
+	return ModemStatusRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function determines if the specified UART is sending data.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*		- TRUE if the UART is sending data
+*		- FALSE if UART is not sending data
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XUartPs_IsSending(XUartPs *InstancePtr)
+{
+	u32 ChanStatRegister;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the channel status register to determine if the transmitter is
+	 * active
+	 */
+	ChanStatRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						 XUARTPS_SR_OFFSET);
+
+	/*
+	 * If the transmitter is active, or the TX FIFO is not empty, then indicate
+	 * that the UART is still sending some data
+	 */
+	return ((XUARTPS_SR_TACTIVE == (ChanStatRegister &
+					 XUARTPS_SR_TACTIVE)) ||
+		(XUARTPS_SR_TXEMPTY != (ChanStatRegister &
+					 XUARTPS_SR_TXEMPTY)));
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the operational mode of the UART. The UART can operate
+* in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic
+* echo.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The operational mode is specified by constants defined in xuartps.h. The
+* constants are named XUARTPS_OPER_MODE_*
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_GetOperMode(XUartPs *InstancePtr)
+{
+	u32 ModeRegister;
+	u8 OperMode;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Mode register.
+	 */
+	ModeRegister =
+		XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_MR_OFFSET);
+
+	ModeRegister &= XUARTPS_MR_CHMODE_MASK;
+	/*
+	 * Return the constant
+	 */
+	switch (ModeRegister) {
+	case XUARTPS_MR_CHMODE_NORM:
+		OperMode = XUARTPS_OPER_MODE_NORMAL;
+		break;
+	case XUARTPS_MR_CHMODE_ECHO:
+		OperMode = XUARTPS_OPER_MODE_AUTO_ECHO;
+		break;
+	case XUARTPS_MR_CHMODE_L_LOOP:
+		OperMode = XUARTPS_OPER_MODE_LOCAL_LOOP;
+		break;
+	case XUARTPS_MR_CHMODE_R_LOOP:
+		OperMode = XUARTPS_OPER_MODE_REMOTE_LOOP;
+		break;
+	default:
+		OperMode = (u8) ((ModeRegister & XUARTPS_MR_CHMODE_MASK) >>
+			XUARTPS_MR_CHMODE_SHIFT);
+	}
+
+	return OperMode;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the operational mode of the UART. The UART can operate
+* in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic
+* echo.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	OperationMode is the mode of the UART.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode)
+{
+	u32 ModeRegister;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(OperationMode <= XUARTPS_OPER_MODE_REMOTE_LOOP);
+
+	/*
+	 * Read the Mode register.
+	 */
+	ModeRegister =
+		XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_MR_OFFSET);
+
+	/*
+	 * Set the correct value by masking the bits, then ORing the const.
+	 */
+	ModeRegister &= ~XUARTPS_MR_CHMODE_MASK;
+
+	switch (OperationMode) {
+	case XUARTPS_OPER_MODE_NORMAL:
+		ModeRegister |= XUARTPS_MR_CHMODE_NORM;
+		break;
+	case XUARTPS_OPER_MODE_AUTO_ECHO:
+		ModeRegister |= XUARTPS_MR_CHMODE_ECHO;
+		break;
+	case XUARTPS_OPER_MODE_LOCAL_LOOP:
+		ModeRegister |= XUARTPS_MR_CHMODE_L_LOOP;
+		break;
+	case XUARTPS_OPER_MODE_REMOTE_LOOP:
+		ModeRegister |= XUARTPS_MR_CHMODE_R_LOOP;
+		break;
+	}
+
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+			   ModeRegister);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Flow Delay.
+* 0 - 3: Flow delay inactive
+* 4 - 32: If Flow Control mode is enabled, UART_rtsN is deactivated when the
+* receive FIFO fills to this level.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The Flow Delay is specified by constants defined in xuartps_hw.h. The
+* constants are named XUARTPS_FLOWDEL*
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr)
+{
+	u32 FdelRegister;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Mode register.
+	 */
+	FdelRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+					 XUARTPS_FLOWDEL_OFFSET);
+
+	/*
+	 * Return the contents of the flow delay register
+	 */
+	return (u8) (FdelRegister & XUARTPS_FLOWDEL_MASK);
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Flow Delay.
+* 0 - 3: Flow delay inactive
+* 4 - 63: If Flow Control mode is enabled, UART_rtsN is deactivated when the
+* receive FIFO fills to this level.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	FlowDelayValue is the Setting for the flow delay.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue)
+{
+	u32 FdelRegister;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FlowDelayValue > XUARTPS_FLOWDEL_MASK);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Set the correct value by shifting the input constant, then masking
+	 * the bits
+	 */
+	FdelRegister = (FlowDelayValue & XUARTPS_FLOWDEL_MASK);
+
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_FLOWDEL_OFFSET, FdelRegister);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the Receive Timeout of the UART.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	The current setting for receive time out.
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr)
+{
+	u32 RtoRegister;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Recieve Timeout register.
+	 */
+	RtoRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XUARTPS_RXTOUT_OFFSET);
+
+	/*
+	 * Return the contents of the mode register shifted appropriately
+	 */
+	return (RtoRegister & XUARTPS_RXTOUT_MASK);
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Receive Timeout of the UART.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	RecvTimeout setting allows the UART to detect an idle connection
+*		on the reciever data line.
+*		Timeout duration = RecvTimeout x 4 x Bit Period. 0 disables the
+*		timeout function.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout)
+{
+	u32 RtoRegister;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Set the correct value by masking the bits
+	 */
+	RtoRegister = (RecvTimeout & XUARTPS_RXTOUT_MASK);
+
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_RXTOUT_OFFSET, RtoRegister);
+
+	/*
+	 * Configure CR to restart the receiver timeout counter
+	 */
+	RtoRegister =
+		XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_CR_OFFSET);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_CR_OFFSET,
+			   (RtoRegister | XUARTPS_CR_TORST));
+
+}
+/****************************************************************************/
+/**
+*
+* Sets the data format for the device. The data format includes the
+* baud rate, number of data bits, number of stop bits, and parity. It is the
+* caller's responsibility to ensure that the UART is not sending or receiving
+* data when this function is called.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	FormatPtr is a pointer to a format structure containing the data
+*		format to be set.
+*
+* @return
+*		- XST_SUCCESS if the data format was successfully set.
+*		- XST_UART_BAUD_ERROR indicates the baud rate could not be
+*		set because of the amount of error with the baud rate and
+*		the input clock frequency.
+*		- XST_INVALID_PARAM if one of the parameters was not valid.
+*
+* @note
+*
+* The data types in the format type, data bits and parity, are 32 bit fields
+* to prevent a compiler warning.
+* The asserts in this function will cause a warning if these fields are
+* bytes.
+* 


+*
+*****************************************************************************/
+int XUartPs_SetDataFormat(XUartPs *InstancePtr,
+			XUartPsFormat * FormatPtr)
+{
+	int Status;
+	u32 ModeRegister;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(FormatPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Verify the inputs specified are valid
+	 */
+	if ((FormatPtr->DataBits > XUARTPS_FORMAT_6_BITS) ||
+		(FormatPtr->StopBits > XUARTPS_FORMAT_2_STOP_BIT) ||
+		(FormatPtr->Parity > XUARTPS_FORMAT_NO_PARITY)) {
+		return XST_INVALID_PARAM;
+	}
+
+	/*
+	 * Try to set the baud rate and if it's not successful then don't
+	 * continue altering the data format, this is done first to avoid the
+	 * format from being altered when an error occurs
+	 */
+	Status = XUartPs_SetBaudRate(InstancePtr, FormatPtr->BaudRate);
+	if (Status != XST_SUCCESS) {
+		return Status;
+	}
+
+	ModeRegister =
+		XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_MR_OFFSET);
+
+	/*
+	 * Set the length of data (8,7,6) by first clearing out the bits
+	 * that control it in the register, then set the length in the register
+	 */
+	ModeRegister &= ~XUARTPS_MR_CHARLEN_MASK;
+	ModeRegister |= (FormatPtr->DataBits << XUARTPS_MR_CHARLEN_SHIFT);
+
+	/*
+	 * Set the number of stop bits in the mode register by first clearing
+	 * out the bits that control it in the register, then set the number
+	 * of stop bits in the register.
+	 */
+	ModeRegister &= ~XUARTPS_MR_STOPMODE_MASK;
+	ModeRegister |= (FormatPtr->StopBits << XUARTPS_MR_STOPMODE_SHIFT);
+
+	/*
+	 * Set the parity by first clearing out the bits that control it in the
+	 * register, then set the bits in the register, the default is no parity
+	 * after clearing the register bits
+	 */
+	ModeRegister &= ~XUARTPS_MR_PARITY_MASK;
+	ModeRegister |= (FormatPtr->Parity << XUARTPS_MR_PARITY_SHIFT);
+
+	/*
+	 * Update the mode register
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+			   ModeRegister);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* Gets the data format for the specified UART. The data format includes the
+* baud rate, number of data bits, number of stop bits, and parity.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	FormatPtr is a pointer to a format structure that will contain
+*		the data format after this call completes.
+*
+* @return	None.
+*
+* @note		None.
+*
+*
+*****************************************************************************/
+void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr)
+{
+	u32 ModeRegister;
+
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FormatPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Get the baud rate from the instance, this is not retrieved from the
+	 * hardware because it is only kept as a divisor such that it is more
+	 * difficult to get back to the baud rate
+	 */
+	FormatPtr->BaudRate = InstancePtr->BaudRate;
+
+	ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_MR_OFFSET);
+
+	/*
+	 * Get the length of data (8,7,6,5)
+	 */
+	FormatPtr->DataBits =
+		(ModeRegister & XUARTPS_MR_CHARLEN_MASK) >>
+		XUARTPS_MR_CHARLEN_SHIFT;
+
+	/*
+	 * Get the number of stop bits
+	 */
+	FormatPtr->StopBits =
+		(ModeRegister & XUARTPS_MR_STOPMODE_MASK) >>
+		XUARTPS_MR_STOPMODE_SHIFT;
+
+	/*
+	 * Determine what parity is
+	 */
+	FormatPtr->Parity =
+		(ModeRegister & XUARTPS_MR_PARITY_MASK) >>
+		XUARTPS_MR_PARITY_SHIFT;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps_selftest.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps_selftest.c
new file mode 100644
index 000000000..42b8cafa9
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps_selftest.c
@@ -0,0 +1,176 @@
+/*****************************************************************************
+*
+* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+*****************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_selftest.c
+*
+* This file contains the self-test functions for the XUartPs driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00	drg/jz 01/13/108First Release
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xuartps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XUARTPS_TOTAL_BYTES 32
+
+/************************** Variable Definitions *****************************/
+
+static u8 TestString[XUARTPS_TOTAL_BYTES]="abcdefghABCDEFGH012345677654321";
+static u8 ReturnString[XUARTPS_TOTAL_BYTES];
+
+/************************** Function Prototypes ******************************/
+
+
+/****************************************************************************/
+/**
+*
+* This function runs a self-test on the driver and hardware device. This self
+* test performs a local loopback and verifies data can be sent and received.
+*
+* The time for this test is proportional to the baud rate that has been set
+* prior to calling this function.
+*
+* The mode and control registers are restored before return.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return
+*		 - XST_SUCCESS if the test was successful
+*		- XST_UART_TEST_FAIL if the test failed looping back the data
+*
+* @note
+*
+* This function can hang if the hardware is not functioning properly.
+*
+******************************************************************************/
+int XUartPs_SelfTest(XUartPs *InstancePtr)
+{
+	int Status = XST_SUCCESS;
+	u32 IntrRegister;
+	u32 ModeRegister;
+	u8 Index;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Disable all interrupts in the interrupt disable register
+	 */
+	IntrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_IMR_OFFSET);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+		XUARTPS_IXR_MASK);
+
+	/*
+	 * Setup for local loopback
+	 */
+	ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_MR_OFFSET);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+			   ((ModeRegister & (~XUARTPS_MR_CHMODE_MASK)) |
+				XUARTPS_MR_CHMODE_L_LOOP));
+
+	/*
+	 * Send a number of bytes and receive them, one at a time.
+	 */
+	for (Index = 0; Index < XUARTPS_TOTAL_BYTES; Index++) {
+		/*
+		 * Send out the byte and if it was not sent then the failure
+		 * will be caught in the comparison at the end
+		 */
+		XUartPs_Send(InstancePtr, &TestString[Index], 1);
+
+		/*
+		 * Wait until the byte is received. This can hang if the HW
+		 * is broken. Watch for the FIFO empty flag to be false.
+		 */
+		while (!(XUartPs_IsReceiveData(InstancePtr->Config.
+						BaseAddress)));
+
+		/*
+		 * Receive the byte
+		 */
+		XUartPs_Recv(InstancePtr, &ReturnString[Index], 1);
+	}
+
+	/*
+	 * Compare the bytes received to the bytes sent to verify the exact data
+	 * was received
+	 */
+	for (Index = 0; Index < XUARTPS_TOTAL_BYTES; Index++) {
+		if (TestString[Index] != ReturnString[Index]) {
+			Status = XST_UART_TEST_FAIL;
+		}
+	}
+
+	/*
+	 * Restore the registers which were altered to put into polling and
+	 * loopback modes so that this test is not destructive
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IER_OFFSET,
+			   IntrRegister);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+			   ModeRegister);
+
+	return Status;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps_sinit.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps_sinit.c
new file mode 100644
index 000000000..4a2c7d1a8
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v2_1/src/xuartps_sinit.c
@@ -0,0 +1,104 @@
+/*****************************************************************************
+*
+* (c) Copyright 2010-13 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+*****************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_sinit.c
+*
+* The implementation of the XUartPs driver's static initialzation
+* functionality.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00  drg/jz 01/13/10 First Release
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xuartps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+extern XUartPs_Config XUartPs_ConfigTable[];
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the ID of the device
+*
+* @return	A pointer to the configuration structure or NULL if the
+*		specified device is not in the system.
+*
+* @note		None.
+*
+******************************************************************************/
+XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId)
+{
+	XUartPs_Config *CfgPtr = NULL;
+
+	int Index;
+
+	for (Index = 0; Index < XPAR_XUARTPS_NUM_INSTANCES; Index++) {
+		if (XUartPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XUartPs_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return CfgPtr;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/Makefile
new file mode 100644
index 000000000..7cf97e2f0
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/Makefile
@@ -0,0 +1,41 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xusbps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling usbps"
+
+xusbps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xusbps_includes
+
+xusbps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps.c
new file mode 100644
index 000000000..fbd24bde0
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps.c
@@ -0,0 +1,370 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/******************************************************************************/
+/**
+ * @file xusbps.c
+ *
+ * The XUsbPs driver. Functions in this file are the minimum required
+ * functions for this driver. See xusbps.h for a detailed description of the
+ * driver.
+ *
+ * @note	None.
+ *
+ * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- --------------------------------------------------------
+ * 1.00a jz  10/10/10 First release
+ * 2.1   kpc 04/28/14 Removed ununsed functions
+ * 

+ ******************************************************************************/
+
+/***************************** Include Files **********************************/
+#include 
+#include "xusbps.h"
+
+/************************** Constant Definitions ******************************/
+
+/**************************** Type Definitions ********************************/
+
+/***************** Macros (Inline Functions) Definitions **********************/
+
+/************************** Variable Definitions ******************************/
+
+/************************** Function Prototypes *******************************/
+
+/*****************************************************************************/
+/**
+*
+* This function initializes a XUsbPs instance/driver.
+*
+* The initialization entails:
+* - Initialize all members of the XUsbPs structure.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	ConfigPtr is a pointer to a XUsbPs_Config configuration
+*		structure. This structure will contain the requested
+*		configuration for the device. Typically, this is a local
+*		structure and the content of which will be copied into the
+*		configuration structure within XUsbPs.
+* @param	VirtBaseAddress is the base address of the device. For systems
+*		with virtual memory, this address must be the virtual address
+*		of the device.
+* 		For systems that do not support virtual memory this address
+* 		should be the physical address of the device. For backwards
+* 		compatibilty NULL may be passed in systems that do not support
+* 		virtual memory (deprecated).
+*
+* @return
+*		- XST_SUCCESS no errors occured.
+*		- XST_FAILURE an error occured during initialization.
+*
+* @note
+*		After calling XUsbPs_CfgInitialize() the controller
+*		IS NOT READY for use. Before the controller can be used its
+*		DEVICE parameters must be configured. See xusbps.h
+*		for details.
+*
+******************************************************************************/
+int XUsbPs_CfgInitialize(XUsbPs *InstancePtr,
+			  const XUsbPs_Config *ConfigPtr, u32 VirtBaseAddress)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr   != NULL);
+
+	/* Copy the config structure. */
+	InstancePtr->Config = *ConfigPtr;
+
+	/* Check if the user provided a non-NULL base address. If so, we have
+	 * to overwrite the base address in the configuration structure.
+	 */
+	if (0 != VirtBaseAddress) {
+		InstancePtr->Config.BaseAddress = VirtBaseAddress;
+	}
+
+	/* Initialize the XUsbPs structure to default values. */
+	InstancePtr->CurrentAltSetting	= XUSBPS_DEFAULT_ALT_SETTING;
+
+	InstancePtr->HandlerFunc	= NULL;
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function performs device reset, device is stopped at the end.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @return	None.
+*
+* @note 	None.
+*
+******************************************************************************/
+void XUsbPs_DeviceReset(XUsbPs *InstancePtr)
+{
+	int Timeout;
+
+	/* Clear all setup token semaphores by reading the
+	 * XUSBPS_EPSTAT_OFFSET register and writing its value back to
+	 * itself.
+	 */
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPSTAT_OFFSET,
+		XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XUSBPS_EPSTAT_OFFSET));
+
+	/* Clear all the endpoint complete status bits by reading the
+	 * XUSBPS_EPCOMPL_OFFSET register and writings its value back
+	 * to itself.
+	 */
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPCOMPL_OFFSET,
+		XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XUSBPS_EPCOMPL_OFFSET));
+
+	/* Cancel all endpoint prime status by waiting until all bits
+	 * in XUSBPS_EPPRIME_OFFSET are 0 and then writing 0xFFFFFFFF
+	 * to XUSBPS_EPFLUSH_OFFSET.
+	 *
+	 * Avoid hanging here by using a Timeout counter...
+	 */
+	Timeout = XUSBPS_TIMEOUT_COUNTER;
+	while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_EPPRIME_OFFSET) &
+				XUSBPS_EP_ALL_MASK) && --Timeout) {
+		/* NOP */
+	}
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_EPFLUSH_OFFSET, 0xFFFFFFFF);
+
+	XUsbPs_Stop(InstancePtr);
+
+	/* Write to CR register for controller reset */
+ 	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET,
+		XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_CMD_OFFSET) | XUSBPS_CMD_RST_MASK);
+
+	/* Wait for reset to finish, hardware clears the reset bit once done  */
+	Timeout = 1000000;
+	while((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_CMD_OFFSET) &
+				XUSBPS_CMD_RST_MASK) && --Timeout) {
+		/* NOP */
+	}
+}
+/*****************************************************************************/
+/**
+*
+* This function resets the USB device. All the configuration registers are
+* reset to their default values. The function waits until the reset operation
+* is complete or for a certain duration within which the reset operation is
+* expected to be completed.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @return
+*		- XST_SUCCESS Reset operation completed successfully.
+*		- XST_FAILURE Reset operation timed out.
+*
+* @note 	None.
+*
+******************************************************************************/
+int XUsbPs_Reset(XUsbPs *InstancePtr)
+{
+	int Timeout;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	/* Write a 1 to the RESET bit. The RESET bit is cleared by HW once the
+	 * RESET is complete.
+	 *
+	 * We are going to wait for the RESET bit to clear before we return
+	 * from this function. Unfortunately we do not have timers available at
+	 * this point to determine when we should report a Timeout.
+	 *
+	 * However, by using a large number for the poll loop we can assume
+	 * that the polling operation will take longer than the expected time
+	 * the HW needs to RESET. If the poll loop expires we can assume a
+	 * Timeout. The drawback is that on a slow system (and even on a fast
+	 * system) this can lead to _very_ long Timeout periods.
+	 */
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_CMD_OFFSET, XUSBPS_CMD_RST_MASK);
+
+
+	/* Wait for the RESET bit to be cleared by HW. */
+	Timeout = XUSBPS_TIMEOUT_COUNTER;
+	while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_CMD_OFFSET) &
+				XUSBPS_CMD_RST_MASK) && --Timeout) {
+		/* NOP */
+	}
+
+	if (0 == Timeout) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * USB Suspend
+ *
+ * In order to conserve power, USB devices automatically enter the suspended
+ * state when the device has observed no bus traffic for a specified period.
+ * When suspended, the USB device maintains any internal status, including its
+ * address and configuration. Attached devices must be prepared to suspend at
+ * any time they are powered, regardless of if they have been assigned a
+ * non-default address, are configured, or neither. Bus activity may cease due
+ * to the host entering a suspend mode of its own. In addition, a USB device
+ * shall also enter the suspended state when the hub port it is attached to is
+ * disabled.
+ *
+ * A USB device exits suspend mode when there is bus activity. A USB device may
+ * also request the host to exit suspend mode or selective suspend by using
+ * electrical signaling to indicate remote wakeup. The ability of a device to
+ * signal remote wakeup is optional. If the USB device is capable of remote
+ * wakeup signaling, the device must support the ability of the host to enable
+ * and disable this capability. When the device is reset, remote wakeup
+ * signaling must be disabled.
+ *
+ * @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+ *
+ * @return
+ *		- XST_SUCCESS if the USB device has entered Suspend mode
+ *		successfully
+ *		- XST_FAILURE on any error
+ *
+ * @note 	None.
+ *
+ ******************************************************************************/
+int XUsbPs_Suspend(const XUsbPs *InstancePtr)
+{
+	(void) InstancePtr;
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+* USB Resume
+*
+ If the USB controller is suspended, its operation is resumed when any
+* non-idle signaling is received on its upstream facing port.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @return
+*		- XST_SUCCESS if the USB device has Resumed successfully
+*		- XST_FAILURE on any error
+*
+* @note 	None.
+*
+******************************************************************************/
+int XUsbPs_Resume(const XUsbPs *InstancePtr)
+{
+	(void) InstancePtr;
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+* USB Assert Resume
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @return
+*		- XST_SUCCESS if the USB device has Resumed successfully
+*		- XST_FAILURE on any error
+*
+* @note 	None.
+*
+******************************************************************************/
+
+int XUsbPs_RequestHostResume(const XUsbPs *InstancePtr)
+{
+	(void) InstancePtr;
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* This functions sets the controller's DEVICE address. It also sets the
+* advance bit so the controller will wait for the next IN-ACK before the new
+* address takes effect.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	Address is the Address of the device.
+*
+* @return
+*		- XST_SUCCESS: Address set successfully.
+*		- XST_FAILURE: An error occured.
+*		- XST_INVALID_PARAM: Invalid parameter passed, e.g. address
+*		value too big.
+*
+* @note 	None.
+*
+*****************************************************************************/
+int XUsbPs_SetDeviceAddress(XUsbPs *InstancePtr, u8 Address)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	/* Check address range validity. */
+	if (Address > XUSBPS_DEVICEADDR_MAX) {
+		return XST_INVALID_PARAM;
+	}
+
+	/* Set the address register with the Address value provided. Also set
+	 * the Address Advance Bit. This will cause the address to be set only
+	 * after an IN occured and has been ACKed on the endpoint.
+	 */
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_DEVICEADDR_OFFSET,
+			 	(Address << XUSBPS_DEVICEADDR_ADDR_SHIFT) |
+			 	XUSBPS_DEVICEADDR_DEVICEAADV_MASK);
+
+	return XST_SUCCESS;
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps.h
new file mode 100644
index 000000000..154b6a5cd
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps.h
@@ -0,0 +1,1091 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xusbps.h
+ *
+ * This file contains the implementation of the XUsbPs driver. It is the
+ * driver for an USB controller in DEVICE or HOST mode.
+ *
+ * 
Introduction

+ *
+ * The Spartan-3AF Embedded Peripheral Block contains a USB controller for
+ * communication with serial peripherals or hosts. The USB controller supports
+ * Host, Device and On the Go (OTG) applications.
+ *
+ * 
USB Controller Features

+ *
+ * - Supports Low Speed USB 1.1 (1.5Mbps), Full Speed USB 1.1 (12Mbps), and
+ *   High Speed USB 2.0 (480Mbps) data speeds
+ * - Supports Device, Host and OTG operational modes
+ * - ULPI transceiver interface for USB 2.0 operation
+ * - Integrated USB Full and Low speed serial transceiver interfaces for lowest
+ *   cost connections
+ *
+ * 
Initialization & Configuration

+ *
+ * The configuration of the USB driver happens in multiple stages:
+ *
+ * - (a) Configuration of the basic parameters:
+ *   In this stage the basic parameters for the driver are configured,
+ *   including the base address and the controller ID.
+ *
+ * - (b) Configuration of the DEVICE endpoints (if applicable):
+ *   If DEVICE mode is desired, the endpoints of the controller need to be
+ *   configured using the XUsbPs_DeviceConfig data structure. Once the
+ *   endpoint configuration is set up in the data structure, The user then
+ *   needs to allocate the required amount of DMAable memory and
+ *   finalize the configuration of the XUsbPs_DeviceConfig data structure,
+ *   e.g. setting the DMAMemVirt and DMAMemPhys members.
+ *
+ * - (c) Configuration of the DEVICE modes:
+ *   In the second stage the parameters for DEVICE are configured.
+ *   The caller only needs to configure the modes that are
+ *   actually used. Configuration is done with the:
+ *   	XUsbPs_ConfigureDevice()
+ * Configuration parameters are defined and passed
+ *   into these functions using the:
+ *      XUsbPs_DeviceConfig data structures.
+ *
+ *
+ * 
USB Device Endpoints

+ *
+ * The USB core supports up to 4 endpoints. Each endpoint has two directions,
+ * an OUT (RX) and an IN (TX) direction. Note that the direction is viewed from
+ * the host's perspective. Endpoint 0 defaults to be the control endpoint and
+ * does not need to be set up. Other endpoints need to be configured and set up
+ * depending on the application. Only endpoints that are actuelly used by the
+ * application need to be initialized.
+ * See the example code (xusbps_intr_example.c) for more information.
+ *
+ *
+ * 
Interrupt Handling

+ *
+ * The USB core uses one interrupt line to report interrupts to the CPU.
+ * Interrupts are handled by the driver's interrupt handler function
+ * XUsbPs_IntrHandler().
+ * It has to be registered with the OS's interrupt subsystem. The driver's
+ * interrupt handler divides incoming interrupts into two categories:
+ *
+ *  - General device interrupts
+ *  - Endopint related interrupts
+ *
+ * The user (typically the adapter layer) can register general interrupt
+ * handler fucntions and endpoint specific interrupt handler functions with the
+ * driver to receive those interrupts by calling the
+ *    XUsbPs_IntrSetHandler()
+ * and
+ *    XUsbPs_EpSetHandler()
+ * functions respectively. Calling these functions with a NULL pointer as the
+ * argument for the function pointer will "clear" the handler function.
+ *
+ * The user can register one handler function for the generic interrupts and
+ * two handler functions for each endpoint, one for the RX (OUT) and one for
+ * the TX (IN) direction. For some applications it may be useful to register a
+ * single endpoint handler function for muliple endpoints/directions.
+ *
+ * When a callback function is called by the driver, parameters identifying the
+ * type of the interrupt will be passed into the handler functions. For general
+ * interrupts the interrupt mask will be passed into the handler function. For
+ * endpoint interrupts the parameters include the number of the endpoint, the
+ * direction (OUT/IN) and the type of the interrupt.
+ *
+ *
+ * 
Data buffer handling

+ *
+ * Data buffers are sent to and received from endpoint using the
+ *    XUsbPs_EpBufferSend(), XUsbPs_EpBufferSendWithZLT()
+ * and
+ *    XUsbPs_EpBufferReceive()
+ * functions.
+ *
+ * User data buffer size is limited to 16 Kbytes. If the user wants to send a
+ * data buffer that is bigger than this limit it needs to break down the data
+ * buffer into multiple fragments and send the fragments individually.
+ *
+ * From the controller perspective Data buffers can be aligned at any boundary.
+ * if the buffers are from cache region then the buffer and buffer size should
+ * be aligned to cache line aligned
+ *
+ *
+ * 
Zero copy

+ *
+ * The driver uses a zero copy mechanism which imposes certain restrictions to
+ * the way the user can handle the data buffers.
+ *
+ * One restriction is that the user needs to release a buffer after it is done
+ * processing the data in the buffer.
+ *
+ * Similarly, when the user sends a data buffer it MUST not re-use the buffer
+ * until it is notified by the driver that the buffer has been transmitted. The
+ * driver will notify the user via the registered endpoint interrupt handling
+ * function by sending a XUSBPS_EP_EVENT_DATA_TX event.
+ *
+ *
+ * 
DMA

+ *
+ * The driver uses DMA internally to move data from/to memory. This behaviour
+ * is transparent to the user. Keeping the DMA handling hidden from the user
+ * has the advantage that the same API can be used with USB cores that do not
+ * support DMA.
+ *
+ *
+ * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- ----------------------------------------------------------
+ * 1.00a wgr  10/10/10 First release
+ * 1.02a wgr  05/16/12 Removed comments as they are showing up in SDK
+ *		       Tabs for CR 657898
+ * 1.03a nm   09/21/12 Fixed CR#678977. Added proper sequence for setup packet
+ *                    handling.
+ * 1.04a nm   10/23/12 Fixed CR# 679106.
+ *	      11/02/12 Fixed CR# 683931. Mult bits are set properly in dQH.
+ * 2.00a kpc 04/03/14 Fixed CR#777763. Corrected the setup tripwire macro val.
+ * 2.1   kpc 04/28/14 Removed unused function prototypes
+ * 

+ *
+ ******************************************************************************/
+
+#ifndef XUSBPS_H
+#define XUSBPS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xusbps_hw.h"
+#include "xil_types.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+
+/**
+ * @name System hang prevention Timeout counter value.
+ *
+ * This value is used throughout the code to initialize a Timeout counter that
+ * is used when hard polling a register. The ides is to initialize the Timeout
+ * counter to a value that is longer than any expected Timeout but short enough
+ * so the system will continue to work and report an error while the user is
+ * still paying attention. A reasonable Timeout time would be about 10 seconds.
+ * The XUSBPS_TIMEOUT_COUNTER value should be chosen so a polling loop would
+ * run about 10 seconds before a Timeout is detected. For example:
+ *
+ * 	int Timeout = XUSBPS_TIMEOUT_COUNTER;
+ *	while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ *				XUSBPS_CMD_OFFSET) &
+ *				XUSBPS_CMD_RST_MASK) && --Timeout) {
+ *		;
+ *	}
+ *	if (0 == Timeout) {
+ *		return XST_FAILURE;
+ *	}
+ *
+ */
+#define XUSBPS_TIMEOUT_COUNTER		1000000
+
+
+/**
+ * @name Endpoint Direction (bitmask)
+ * Definitions to be used with Endpoint related function that require a
+ * 'Direction' parameter.
+ *
+ * NOTE:
+ *   The direction is always defined from the perspective of the HOST! This
+ *   means that an IN endpoint on the controller is used for sending data while
+ *   the OUT endpoint on the controller is used for receiving data.
+ * @{
+ */
+#define XUSBPS_EP_DIRECTION_IN		0x01 /**< Endpoint direction IN. */
+#define XUSBPS_EP_DIRECTION_OUT		0x02 /**< Endpoint direction OUT. */
+/* @} */
+
+
+/**
+ * @name Endpoint Type
+ * Definitions to be used with Endpoint related functions that require a 'Type'
+ * parameter.
+ * @{
+ */
+#define XUSBPS_EP_TYPE_NONE		0 /**< Endpoint is not used. */
+#define XUSBPS_EP_TYPE_CONTROL		1 /**< Endpoint for Control Transfers */
+#define XUSBPS_EP_TYPE_ISOCHRONOUS 	2 /**< Endpoint for isochronous data */
+#define XUSBPS_EP_TYPE_BULK		3 /**< Endpoint for BULK Transfers. */
+#define XUSBPS_EP_TYPE_INTERRUPT	4 /**< Endpoint for interrupt Transfers */
+/* @} */
+
+/**
+ * Endpoint Max Packet Length in DeviceConfig is a coded value, ch9.6.6.
+ *
+ * @{
+ */
+#define ENDPOINT_MAXP_LENGTH		0x400
+#define ENDPOINT_MAXP_MULT_MASK		0xC00
+#define ENDPOINT_MAXP_MULT_SHIFT	10
+/* @} */
+
+/**
+ * @name Field names for status retrieval
+ * Definitions for the XUsbPs_GetStatus() function call 'StatusType'
+ * parameter.
+ * @{
+ */
+#define XUSBPS_EP_STS_ADDRESS		1 /**< Address of controller. */
+#define XUSBPS_EP_STS_CONTROLLER_STATE	2 /**< Current controller state. */
+/* @} */
+
+
+
+/**
+ * @name USB Default alternate setting
+ *
+ * @{
+ */
+#define XUSBPS_DEFAULT_ALT_SETTING	0 /**< The default alternate setting is 0 */
+/* @} */
+
+/**
+ * @name Endpoint event types
+ * Definitions that are used to identify events that occur on endpoints. Passed
+ * to the endpoint event handler functions registered with
+ * XUsbPs_EpSetHandler().
+ * @{
+ */
+#define XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED	0x01
+			/**< Setup data has been received on the enpoint. */
+#define XUSBPS_EP_EVENT_DATA_RX		0x02
+			/**< Data frame has been received on the endpoint. */
+#define XUSBPS_EP_EVENT_DATA_TX		0x03
+			/**< Data frame has been sent on the endpoint. */
+/* @} */
+
+
+/*
+ * Maximum packet size for endpoint, 1024
+ * @{
+ */
+#define XUSBPS_MAX_PACKET_SIZE		1024
+				/**< Maximum value can be put into the queue head */
+/* @} */
+/**************************** Type Definitions *******************************/
+
+/******************************************************************************
+ * This data type defines the callback function to be used for Endpoint
+ * handlers.
+ *
+ * @param	CallBackRef is the Callback reference passed in by the upper
+ *		layer when setting the handler, and is passed back to the upper
+ *		layer when the handler is called.
+ * @param	EpNum is the Number of the endpoint that caused the event.
+ * @param	EventType is the type of the event that occured on the endpoint.
+ * @param	Data is a pointer to user data pointer specified when callback
+ *		was registered.
+ */
+typedef void (*XUsbPs_EpHandlerFunc)(void *CallBackRef,
+				      u8 EpNum, u8 EventType, void *Data);
+
+
+/******************************************************************************
+ * This data type defines the callback function to be used for the general
+ * interrupt handler.
+ *
+ * @param	CallBackRef is the Callback reference passed in by the upper
+ *		layer when setting the handler, and is passed back to the upper
+ *		layer when the handler is called.
+ * @param	IrqMask is the Content of the interrupt status register. This
+ *		value can be used by the callback function to distinguish the
+ *		individual interrupt types.
+ */
+typedef void (*XUsbPs_IntrHandlerFunc)(void *CallBackRef, u32 IrqMask);
+
+
+/******************************************************************************/
+
+/* The following type definitions are used for referencing Queue Heads and
+ * Transfer Descriptors. The structures themselves are not used, however, the
+ * types are used in the API to avoid using (void *) pointers.
+ */
+typedef u8	XUsbPs_dQH[XUSBPS_dQH_ALIGN];
+typedef u8	XUsbPs_dTD[XUSBPS_dTD_ALIGN];
+
+
+/**
+ * The following data structures are used internally by the L0/L1 driver.
+ * Their contents MUST NOT be changed by the upper layers.
+ */
+
+/**
+ * The following data structure represents OUT endpoint.
+ */
+typedef struct {
+	XUsbPs_dQH	*dQH;
+		/**< Pointer to the Queue Head structure of the endpoint. */
+
+	XUsbPs_dTD	*dTDs;
+		/**< Pointer to the first dTD of the dTD list for this
+		 * endpoint. */
+
+	XUsbPs_dTD	*dTDCurr;
+		/**< Buffer to the currently processed descriptor. */
+
+	u8	*dTDBufs;
+		/**< Pointer to the first buffer of the buffer list for this
+		 * endpoint. */
+
+	XUsbPs_EpHandlerFunc	HandlerFunc;
+		/**< Handler function for this endpoint. */
+	void			*HandlerRef;
+		/**< User data reference for the handler. */
+} XUsbPs_EpOut;
+
+
+/**
+ * The following data structure represents IN endpoint.
+ */
+typedef struct {
+	XUsbPs_dQH	*dQH;
+		/**< Pointer to the Queue Head structure of the endpoint. */
+
+	XUsbPs_dTD	*dTDs;
+		/**< List of pointers to the Transfer Descriptors of the
+		 * endpoint. */
+
+	XUsbPs_dTD	*dTDHead;
+		/**< Buffer to the next available descriptor in the list. */
+
+	XUsbPs_dTD	*dTDTail;
+		/**< Buffer to the last unsent descriptor in the list*/
+
+	XUsbPs_EpHandlerFunc	HandlerFunc;
+		/**< Handler function for this endpoint. */
+	void			*HandlerRef;
+		/**< User data reference for the handler. */
+} XUsbPs_EpIn;
+
+
+/**
+ * The following data structure represents an endpoint used internally
+ * by the L0/L1 driver.
+ */
+typedef struct {
+	/* Each endpoint has an OUT and an IN component.
+	 */
+	XUsbPs_EpOut	Out;	/**< OUT endpoint structure */
+	XUsbPs_EpIn	In;	/**< IN endpoint structure */
+} XUsbPs_Endpoint;
+
+
+
+/**
+ * The following structure is used by the user to receive Setup Data from an
+ * endpoint. Using this structure simplifies the process of interpreting the
+ * setup data in the core's data fields.
+ *
+ * The naming scheme for the members of this structure is different from the
+ * naming scheme found elsewhere in the code. The members of this structure are
+ * defined in the Chapter 9 USB reference guide. Using this naming scheme makes
+ * it easier for people familiar with the standard to read the code.
+ */
+typedef struct {
+	u8  bmRequestType;	/**< bmRequestType in setup data */
+	u8  bRequest;		/**< bRequest in setup data */
+	u16 wValue;		/**< wValue in setup data */
+	u16 wIndex;		/**< wIndex in setup data */
+	u16 wLength;		/**< wLength in setup data */
+}
+XUsbPs_SetupData;
+
+
+/**
+ * Data structures used to configure endpoints.
+ */
+typedef struct {
+	u32	Type;
+		/**< Endpoint type:
+			- XUSBPS_EP_TYPE_CONTROL
+			- XUSBPS_EP_TYPE_ISOCHRONOUS
+			- XUSBPS_EP_TYPE_BULK
+			- XUSBPS_EP_TYPE_INTERRUPT */
+
+	u32	NumBufs;
+		/**< Number of buffers to be handled by this endpoint. */
+	u32	BufSize;
+		/**< Buffer size. Only relevant for OUT (receive) Endpoints. */
+
+	u16	MaxPacketSize;
+		/**< Maximum packet size for this endpoint. This number will
+		 * define the maximum number of bytes sent on the wire per
+		 * transaction. Range: 0..1024 */
+} XUsbPs_EpSetup;
+
+
+/**
+ * Endpoint configuration structure.
+ */
+typedef struct {
+	XUsbPs_EpSetup		Out; /**< OUT component of endpoint. */
+	XUsbPs_EpSetup		In;  /**< IN component of endpoint. */
+} XUsbPs_EpConfig;
+
+
+/**
+ * The XUsbPs_DeviceConfig structure contains the configuration information to
+ * configure the USB controller for DEVICE mode. This data structure is used
+ * with the XUsbPs_ConfigureDevice() function call.
+ */
+typedef struct {
+	u8  NumEndpoints;	/**< Number of Endpoints for the controller.
+				  This number depends on the runtime
+				  configuration of driver. The driver may
+				  configure fewer endpoints than are available
+				  in the core. */
+
+	XUsbPs_EpConfig	EpCfg[XUSBPS_MAX_ENDPOINTS];
+				/**< List of endpoint configurations. */
+
+
+	u32 DMAMemPhys;		/**< Physical base address of DMAable memory
+				  allocated for the driver. */
+
+	/* The following members are used internally by the L0/L1 driver.  They
+	 * MUST NOT be accesses and/or modified in any way by the upper layers.
+	 *
+	 * The reason for having these members is that we generally try to
+	 * avoid allocating memory in the L0/L1 driver as we want to be OS
+	 * independent. In order to avoid allocating memory for this data
+	 * structure wihin L0/L1 we put it into the XUsbPs_DeviceConfig
+	 * structure which is allocated by the caller.
+	 */
+	XUsbPs_Endpoint	Ep[XUSBPS_MAX_ENDPOINTS];
+				/**< List of endpoint metadata structures. */
+
+	u32 PhysAligned;	/**< 64 byte aligned base address of the DMA
+				   memory block. Will be computed and set by
+				   the L0/L1 driver. */
+} XUsbPs_DeviceConfig;
+
+
+/**
+ * The XUsbPs_Config structure contains configuration information for the USB
+ * controller.
+ *
+ * This structure only contains the basic configuration for the controller. The
+ * caller also needs to initialize the controller for the DEVICE mode
+ * using the XUsbPs_DeviceConfig data structures with the
+ * XUsbPs_ConfigureDevice() function call
+ */
+typedef struct {
+	u16 DeviceID;		/**< Unique ID of controller. */
+	u32 BaseAddress;	/**< Core register base address. */
+} XUsbPs_Config;
+
+
+/**
+ * The XUsbPs driver instance data. The user is required to allocate a
+ * variable of this type for every USB controller in the system. A pointer to a
+ * variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XUsbPs_Config Config;	/**< Configuration structure */
+
+	int CurrentAltSetting;	/**< Current alternative setting of interface */
+
+	void *UserDataPtr;	/**< Data pointer to be used by upper layers to
+				  store application dependent data structures.
+				  The upper layers are responsible to allocated
+				  and free the memory. The driver will not
+				  mofidy this data pointer. */
+
+	/**
+	 * The following structures hold the configuration for DEVICE mode
+	 * of the controller. They are initialized using the
+	 * XUsbPs_ConfigureDevice() function call.
+	 */
+	XUsbPs_DeviceConfig	DeviceConfig;
+				/**< Configuration for the DEVICE mode. */
+
+	XUsbPs_IntrHandlerFunc	HandlerFunc;
+		/**< Handler function for the controller. */
+	void			*HandlerRef;
+		/**< User data reference for the handler. */
+	u32			HandlerMask;
+		/**< User interrupt mask. Defines which interrupts will cause
+		 * the callback to be called. */
+} XUsbPs;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/******************************************************************************
+ *
+ * USB CONTROLLER RELATED MACROS
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ * This macro returns the current frame number.
+ *
+ * @param	InstancePtr is a pointer to the XUsbPs instance of the
+ *		controller.
+ *
+ * @return	The current frame number.
+ *
+ * @note	C-style signature:
+ *		u32 XUsbPs_GetFrameNum(const XUsbPs *InstancePtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_GetFrameNum(InstancePtr) \
+	XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, XUSBPS_FRAME_OFFSET)
+
+
+/*****************************************************************************/
+/**
+ * This macro starts the USB engine.
+ *
+ * @param	InstancePtr is a pointer to the XUsbPs instance of the
+ *		controller.
+ *
+ * @note	C-style signature:
+ * 		void XUsbPs_Start(XUsbPs *InstancePtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_Start(InstancePtr) \
+	XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK)
+
+
+/*****************************************************************************/
+/**
+ * This macro stops the USB engine.
+ *
+ * @param	InstancePtr is a pointer to the XUsbPs instance of the
+ *		controller.
+ *
+ * @note	C-style signature:
+ * 		void XUsbPs_Stop(XUsbPs *InstancePtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_Stop(InstancePtr) \
+	XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK)
+
+
+/*****************************************************************************/
+/**
+ * This macro forces the USB engine to be in Full Speed (FS) mode.
+ *
+ * @param	InstancePtr is a pointer to the XUsbPs instance of the
+ *		controller.
+ *
+ * @note	C-style signature:
+ * 		void XUsbPs_ForceFS(XUsbPs *InstancePtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_ForceFS(InstancePtr)					\
+	XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET,		\
+ 		XUSBPS_PORTSCR_PFSC_MASK)
+
+
+/*****************************************************************************/
+/**
+ * This macro starts the USB Timer 0, with repeat option for period of
+ * one second.
+ *
+ * @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+ * @param	Interval is the interval for Timer0 to generate an interrupt
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_StartTimer0(XUsbPs *InstancePtr, u32 Interval)
+ *
+ ******************************************************************************/
+#define XUsbPs_StartTimer0(InstancePtr, Interval) 			\
+{									\
+	XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, 		\
+			XUSBPS_TIMER0_LD_OFFSET, (Interval));		\
+	XUsbPs_SetBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET,		\
+			XUSBPS_TIMER_RUN_MASK |			\
+			XUSBPS_TIMER_RESET_MASK |			\
+			XUSBPS_TIMER_REPEAT_MASK);			\
+}									\
+
+
+/*****************************************************************************/
+/**
+* This macro stops Timer 0.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note		C-style signature:
+*		void XUsbPs_StopTimer0(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_StopTimer0(InstancePtr) \
+	XUsbPs_ClrBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET,		\
+		XUSBPS_TIMER_RUN_MASK)
+
+
+/*****************************************************************************/
+/**
+* This macro reads Timer 0.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note		C-style signature:
+*		void XUsbPs_ReadTimer0(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_ReadTimer0(InstancePtr) 				\
+	XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress,		\
+			XUSBPS_TIMER0_CTL_OFFSET) & 			\
+					XUSBPS_TIMER_COUNTER_MASK
+
+
+/*****************************************************************************/
+/**
+* This macro force remote wakeup on host
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note		C-style signature:
+*  		void XUsbPs_RemoteWakeup(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_RemoteWakeup(InstancePtr) \
+	XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET,		 \
+			XUSBPS_PORTSCR_FPR_MASK)
+
+
+/******************************************************************************
+ *
+ * ENDPOINT RELATED MACROS
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+* This macro enables the given endpoint for the given direction.
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+* @param	EpNum is number of the endpoint to enable.
+* @param	Dir is direction of the endpoint (bitfield):
+* 			- XUSBPS_EP_DIRECTION_OUT
+* 			- XUSBPS_EP_DIRECTION_IN
+*
+* @note		C-style signature:
+* 		void XUsbPs_EpEnable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpEnable(InstancePtr, EpNum, Dir) \
+	XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum),	 \
+	((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
+	((Dir) & XUSBPS_EP_DIRECTION_IN  ? XUSBPS_EPCR_TXE_MASK : 0))
+
+
+/*****************************************************************************/
+/**
+* This macro disables the given endpoint for the given direction.
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+* @param	EpNum is the number of the endpoint to disable.
+* @param	Dir is the direction of the endpoint (bitfield):
+* 		- XUSBPS_EP_DIRECTION_OUT
+* 		- XUSBPS_EP_DIRECTION_IN
+*
+* @note		C-style signature:
+* 		void XUsbPs_EpDisable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpDisable(InstancePtr, EpNum, Dir) \
+	XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum),		 \
+		((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
+		((Dir) & XUSBPS_EP_DIRECTION_IN  ? XUSBPS_EPCR_TXE_MASK : 0))
+
+
+/*****************************************************************************/
+/**
+* This macro stalls the given endpoint for the given direction, and flush
+* the buffers.
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+* @param	EpNum is number of the endpoint to stall.
+* @param	Dir is the direction of the endpoint (bitfield):
+* 			- XUSBPS_EP_DIRECTION_OUT
+* 			- XUSBPS_EP_DIRECTION_IN
+*
+* @note		C-style signature:
+*		void XUsbPs_EpStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpStall(InstancePtr, EpNum, Dir) \
+	XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum),	 \
+	((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
+	((Dir) & XUSBPS_EP_DIRECTION_IN  ? XUSBPS_EPCR_TXS_MASK : 0))
+
+
+/*****************************************************************************/
+/**
+* This macro unstalls the given endpoint for the given direction.
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+* @param	EpNum is the Number of the endpoint to unstall.
+* @param	Dir is the Direction of the endpoint (bitfield):
+* 		- XUSBPS_EP_DIRECTION_OUT
+* 		- XUSBPS_EP_DIRECTION_IN
+*
+* @note		C-style signature:
+* 		void XUsbPs_EpUnStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpUnStall(InstancePtr, EpNum, Dir) \
+	XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum),	 \
+	((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
+	((Dir) & XUSBPS_EP_DIRECTION_IN  ? XUSBPS_EPCR_TXS_MASK : 0))
+
+
+/*****************************************************************************/
+/**
+* This macro flush an endpoint upon interface disable
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+* @param	EpNum is the number of the endpoint to flush.
+* @param	Dir is the direction of the endpoint (bitfield):
+* 			- XUSBPS_EP_DIRECTION_OUT
+* 			- XUSBPS_EP_DIRECTION_IN
+*
+* @note		C-style signature:
+*		void XUsbPs_EpFlush(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpFlush(InstancePtr, EpNum, Dir) \
+	XUsbPs_SetBits(InstancePtr, XUSBPS_EPFLUSH_OFFSET,	\
+		EpNum << ((Dir) & XUSBPS_EP_DIRECTION_OUT ?		\
+			XUSBPS_EPFLUSH_RX_SHIFT:XUSBPS_EPFLUSH_TX_SHIFT)) \
+
+/*****************************************************************************/
+/**
+* This macro enables the interrupts defined by the bit mask.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	IntrMask is the Bit mask of interrupts to be enabled.
+*
+* @note		C-style signature:
+*		void XUsbPs_IntrEnable(XUsbPs *InstancePtr, u32 IntrMask)
+*
+******************************************************************************/
+#define XUsbPs_IntrEnable(InstancePtr, IntrMask)	\
+		XUsbPs_SetBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
+
+
+/*****************************************************************************/
+/**
+* This function disables the interrupts defined by the bit mask.
+*
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	IntrMask is a Bit mask of interrupts to be disabled.
+*
+* @note		C-style signature:
+* 		void XUsbPs_IntrDisable(XUsbPs *InstancePtr, u32 IntrMask)
+*
+******************************************************************************/
+#define XUsbPs_IntrDisable(InstancePtr, IntrMask)	\
+		XUsbPs_ClrBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
+
+
+/*****************************************************************************/
+/**
+* This macro enables the endpoint NAK interrupts defined by the bit mask.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	NakIntrMask is the Bit mask of endpoint NAK interrupts to be
+*		enabled.
+* @note		C-style signature:
+* 		void XUsbPs_NakIntrEnable(XUsbPs *InstancePtr, u32 NakIntrMask)
+*
+******************************************************************************/
+#define XUsbPs_NakIntrEnable(InstancePtr, NakIntrMask)	\
+	XUsbPs_SetBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask)
+
+
+/*****************************************************************************/
+/**
+* This macro disables the endpoint NAK interrupts defined by the bit mask.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	NakIntrMask is a Bit mask of endpoint NAK interrupts to be
+*		disabled.
+*
+* @note
+* 	C-style signature:
+* 	void XUsbPs_NakIntrDisable(XUsbPs *InstancePtr, u32 NakIntrMask)
+*
+******************************************************************************/
+#define XUsbPs_NakIntrDisable(InstancePtr, NakIntrMask)	\
+	XUsbPs_ClrBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask)
+
+
+/*****************************************************************************/
+/**
+* This function clears the endpoint NAK interrupts status defined by the
+* bit mask.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	NakIntrMask is the Bit mask of endpoint NAK interrupts to be cleared.
+*
+* @note		C-style signature:
+* 		void XUsbPs_NakIntrClear(XUsbPs *InstancePtr, u32 NakIntrMask)
+*
+******************************************************************************/
+#define XUsbPs_NakIntrClear(InstancePtr, NakIntrMask)			\
+	XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress,		\
+				XUSBPS_EPNAKISR_OFFSET, NakIntrMask)
+
+
+
+/*****************************************************************************/
+/**
+* This macro sets the Interrupt Threshold value in the control register
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	Threshold is the Interrupt threshold to be set.
+* 		Allowed values:
+*			- XUSBPS_CMD_ITHRESHOLD_0 - Immediate interrupt
+*			- XUSBPS_CMD_ITHRESHOLD_1 - 1 Frame
+*			- XUSBPS_CMD_ITHRESHOLD_2 - 2 Frames
+*			- XUSBPS_CMD_ITHRESHOLD_4 - 4 Frames
+*			- XUSBPS_CMD_ITHRESHOLD_8 - 8 Frames
+*			- XUSBPS_CMD_ITHRESHOLD_16 - 16 Frames
+*			- XUSBPS_CMD_ITHRESHOLD_32 - 32 Frames
+*			- XUSBPS_CMD_ITHRESHOLD_64 - 64 Frames
+*
+* @note
+* 	C-style signature:
+*	void XUsbPs_SetIntrThreshold(XUsbPs *InstancePtr, u8 Threshold)
+*
+******************************************************************************/
+#define XUsbPs_SetIntrThreshold(InstancePtr, Threshold)		\
+		XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress,	\
+					XUSBPS_CMD_OFFSET, (Threshold))\
+
+
+/*****************************************************************************/
+/**
+* This macro sets the Tripwire bit in the USB command register.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note		C-style signature:
+*		void XUsbPs_SetTripwire(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_SetSetupTripwire(InstancePtr)				\
+		XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET,	\
+				XUSBPS_CMD_SUTW_MASK)
+
+
+/*****************************************************************************/
+/**
+* This macro clears the Tripwire bit in the USB command register.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note		C-style signature:
+*		void XUsbPs_ClrTripwire(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_ClrSetupTripwire(InstancePtr)				\
+		XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET,	\
+				XUSBPS_CMD_SUTW_MASK)
+
+
+/*****************************************************************************/
+/**
+* This macro checks if the Tripwire bit in the USB command register is set.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @return
+* 		- TRUE: The tripwire bit is still set.
+* 		- FALSE: The tripwire bit has been cleared.
+*
+* @note		C-style signature:
+*		int XUsbPs_TripwireIsSet(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_SetupTripwireIsSet(InstancePtr)				\
+		(XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, 	\
+				XUSBPS_CMD_OFFSET) &			\
+				XUSBPS_CMD_SUTW_MASK ? TRUE : FALSE)
+
+
+/******************************************************************************
+*
+* GENERAL REGISTER / BIT MANIPULATION MACROS
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+* This macro sets the given bit mask in the register.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	RegOffset is the register offset to be written.
+* @param	Bits is the Bits to be set in the register
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XUsbPs_SetBits(u32 BaseAddress, u32 RegOffset, u32 Bits)
+*
+*****************************************************************************/
+#define XUsbPs_SetBits(InstancePtr, RegOffset, Bits) \
+	XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset,	\
+		XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, 	\
+					RegOffset) | (Bits));
+
+
+/****************************************************************************/
+/**
+*
+* This macro clears the given bits in the register.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	RegOffset is the register offset to be written.
+* @param	Bits are the bits to be cleared in the register
+*
+* @return	None.
+*
+* @note
+* 	C-style signature:
+*	void XUsbPs_ClrBits(u32 BaseAddress, u32 RegOffset, u32 Bits)
+*
+*****************************************************************************/
+#define XUsbPs_ClrBits(InstancePtr, RegOffset, Bits) \
+	XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset,	\
+		XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, 	\
+				RegOffset) & ~(Bits));
+
+
+/************************** Function Prototypes ******************************/
+
+/**
+ * Setup / Initialize functions.
+ *
+ * Implemented in file xusbps.c
+ */
+int XUsbPs_CfgInitialize(XUsbPs *InstancePtr,
+			  const XUsbPs_Config *ConfigPtr, u32 BaseAddress);
+
+int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr,
+				const XUsbPs_DeviceConfig *CfgPtr);
+
+/**
+ * Common functions used for DEVICE/HOST mode.
+ */
+int XUsbPs_Reset(XUsbPs *InstancePtr);
+
+/**
+ * DEVICE mode specific functions.
+ */
+int XUsbPs_BusReset(XUsbPs *InstancePtr);
+int XUsbPs_SetDeviceAddress(XUsbPs *InstancePtr, u8 Address);
+
+
+/**
+ * Handling Suspend and Resume.
+ *
+ * Implemented in xusbps.c
+ */
+int XUsbPs_Suspend(const XUsbPs *InstancePtr);
+int XUsbPs_Resume(const XUsbPs *InstancePtr);
+int XUsbPs_RequestHostResume(const XUsbPs *InstancePtr);
+
+
+/*
+ * Functions for managing Endpoints / Transfers
+ *
+ * Implemented in file xusbps_endpoint.c
+ */
+int XUsbPs_EpBufferSend(XUsbPs *InstancePtr, u8 EpNum,
+			const u8 *BufferPtr, u32 BufferLen);
+int XUsbPs_EpBufferSendWithZLT(XUsbPs *InstancePtr, u8 EpNum,
+			const u8 *BufferPtr, u32 BufferLen);
+int XUsbPs_EpBufferReceive(XUsbPs *InstancePtr, u8 EpNum,
+			u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle);
+void XUsbPs_EpBufferRelease(u32 Handle);
+
+int XUsbPs_EpSetHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction,
+			XUsbPs_EpHandlerFunc CallBackFunc,
+			void *CallBackRef);
+int XUsbPs_EpGetSetupData(XUsbPs *InstancePtr, int EpNum,
+			XUsbPs_SetupData *SetupDataPtr);
+
+int XUsbPs_EpPrime(XUsbPs *InstancePtr, u8 EpNum, u8 Direction);
+
+int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr,
+			int EpNum, unsigned short NewDirection, int DirectionChanged);
+
+/*
+ * Interrupt handling functions
+ *
+ * Implemented in file xusbps_intr.c
+ */
+void XUsbPs_IntrHandler(void *InstancePtr);
+
+int XUsbPs_IntrSetHandler(XUsbPs *InstancePtr,
+			   XUsbPs_IntrHandlerFunc CallBackFunc,
+			   void *CallBackRef, u32 Mask);
+/*
+ * Helper functions for static configuration.
+ * Implemented in xusbps_sinit.c
+ */
+XUsbPs_Config *XUsbPs_LookupConfig(u16 DeviceId);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XUSBPS_H */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps_endpoint.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps_endpoint.c
new file mode 100644
index 000000000..fb3917b54
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps_endpoint.c
@@ -0,0 +1,1455 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/******************************************************************************/
+/**
+ * @file xusbps_endpoint.c
+ *
+ * Endpoint specific function implementations.
+ *
+ * @note     None.
+ *
+ * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- --------------------------------------------------------
+ * 1.00a jz  10/10/10 First release
+ * 1.03a nm  09/21/12 Fixed CR#678977. Added proper sequence for setup packet
+ *                    handling.
+ * 1.04a nm  11/02/12 Fixed CR#683931. Mult bits are set properly in dQH.
+ * 2.00a kpc 04/03/14 Fixed CR#777763. Updated the macro names 
+ * 2.1   kpc 04/28/14 Added XUsbPs_EpBufferSendWithZLT api and merged common
+ *		      code to XUsbPs_EpQueueRequest.
+ * 

+ ******************************************************************************/
+
+/***************************** Include Files **********************************/
+
+#include  /* for bzero() */
+#include 
+
+#include "xusbps.h"
+#include "xusbps_endpoint.h"
+
+/************************** Constant Definitions ******************************/
+
+/**************************** Type Definitions ********************************/
+
+/************************** Variable Definitions ******************************/
+
+/************************** Function Prototypes ******************************/
+
+static void XUsbPs_EpListInit(XUsbPs_DeviceConfig *DevCfgPtr);
+static void XUsbPs_dQHInit(XUsbPs_DeviceConfig *DevCfgPtr);
+static int  XUsbPs_dTDInit(XUsbPs_DeviceConfig *DevCfgPtr);
+static int  XUsbPs_dTDAttachBuffer(XUsbPs_dTD *dTDPtr,
+					const u8 *BufferPtr, u32 BufferLen);
+
+static void XUsbPs_dQHSetMaxPacketLenISO(XUsbPs_dQH *dQHPtr, u32 Len);
+
+/* Functions to reconfigure endpoint upon host's set alternate interface
+ * request.
+ */
+static void XUsbPs_dQHReinitEp(XUsbPs_DeviceConfig *DevCfgPtr,
+					int EpNum, unsigned short NewDirection);
+static int XUsbPs_dTDReinitEp(XUsbPs_DeviceConfig *DevCfgPtr,
+					int EpNum, unsigned short NewDirection);
+static int XUsbPs_EpQueueRequest(XUsbPs *InstancePtr, u8 EpNum,
+				const u8 *BufferPtr, u32 BufferLen, u8 ReqZero);
+
+/******************************* Functions ************************************/
+
+/*****************************************************************************/
+/**
+ *
+ * This function configures the DEVICE side of the controller. The caller needs
+ * to pass in the desired configuration (e.g. number of endpoints) and a
+ * DMAable buffer that will hold the Queue Head List and the Transfer
+ * Descriptors. The required size for this buffer can be obtained by the caller
+ * using the: XUsbPs_DeviceMemRequired() macro.
+ *
+ * @param	InstancePtr is a pointer to the XUsbPs instance of the
+ *		controller.
+ * @param	CfgPtr is a pointer to the configuration structure that contains
+ *		the desired DEVICE side configuration.
+ *
+ * @return
+ *		- XST_SUCCESS: The operation completed successfully.
+ *		- XST_FAILURE: An error occured.
+ *
+ * @note
+ * 		The caller may configure the controller for both, DEVICE and
+ * 		HOST side.
+ *
+ ******************************************************************************/
+int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr,
+			    const XUsbPs_DeviceConfig *CfgPtr)
+{
+	int	Status;
+	u32 ModeValue = 0x0;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(CfgPtr      != NULL);
+
+	/* Copy the configuration data over into the local instance structure */
+	InstancePtr->DeviceConfig = *CfgPtr;
+
+
+	/* Align the buffer to a 2048 byte (XUSBPS_dQH_BASE_ALIGN) boundary.*/
+	InstancePtr->DeviceConfig.PhysAligned =
+		(InstancePtr->DeviceConfig.DMAMemPhys +
+					 XUSBPS_dQH_BASE_ALIGN) &
+						~(XUSBPS_dQH_BASE_ALIGN -1);
+
+	/* Initialize the endpoint pointer list data structure. */
+	XUsbPs_EpListInit(&InstancePtr->DeviceConfig);
+
+
+	/* Initialize the Queue Head structures in DMA memory. */
+	XUsbPs_dQHInit(&InstancePtr->DeviceConfig);
+
+
+	/* Initialize the Transfer Descriptors in DMA memory.*/
+	Status = XUsbPs_dTDInit(&InstancePtr->DeviceConfig);
+	if (XST_SUCCESS != Status) {
+		return XST_FAILURE;
+	}
+
+	/* Changing the DEVICE mode requires a controller RESET. */
+	if (XST_SUCCESS != XUsbPs_Reset(InstancePtr)) {
+		return XST_FAILURE;
+	}
+
+	/* Set the Queue Head List address. */
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_EPLISTADDR_OFFSET,
+				InstancePtr->DeviceConfig.PhysAligned);
+
+	/* Set the USB mode register to configure DEVICE mode.
+	 *
+	 * XUSBPS_MODE_SLOM_MASK note:
+	 *   Disable Setup Lockout. Setup Lockout is not required as we
+	 *   will be using the tripwire mechanism when handling setup
+	 *   packets.
+	 */
+	ModeValue = XUSBPS_MODE_CM_DEVICE_MASK | XUSBPS_MODE_SLOM_MASK;
+
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_MODE_OFFSET, ModeValue);
+
+	XUsbPs_SetBits(InstancePtr, XUSBPS_OTGCSR_OFFSET,
+				XUSBPS_OTGSC_OT_MASK);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* This function sends a given data buffer.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	EpNum is the number of the endpoint to receive data from.
+* @param	BufferPtr is a pointer to the buffer to send.
+* @param	BufferLen is the Buffer length.
+*
+* @return
+*		- XST_SUCCESS: The operation completed successfully.
+*		- XST_FAILURE: An error occured.
+*		- XST_USB_BUF_TOO_BIG: Provided buffer is too big (>16kB).
+*		- XST_USB_NO_DESC_AVAILABLE: No TX descriptor is available.
+*
+******************************************************************************/
+int XUsbPs_EpBufferSend(XUsbPs *InstancePtr, u8 EpNum,
+				const u8 *BufferPtr, u32 BufferLen)
+{
+	Xil_AssertNonvoid(InstancePtr  != NULL);
+	Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
+
+	return XUsbPs_EpQueueRequest(InstancePtr, EpNum, BufferPtr,
+					BufferLen, FALSE);
+}
+
+/*****************************************************************************/
+/**
+* This function sends a given data buffer and also zero length packet if the
+* Bufferlen is in multiples of endpoint max packet size.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	EpNum is the number of the endpoint to receive data from.
+* @param	BufferPtr is a pointer to the buffer to send.
+* @param	BufferLen is the Buffer length.
+*
+* @return
+*		- XST_SUCCESS: The operation completed successfully.
+*		- XST_FAILURE: An error occured.
+*		- XST_USB_BUF_TOO_BIG: Provided buffer is too big (>16kB).
+*		- XST_USB_NO_DESC_AVAILABLE: No TX descriptor is available.
+*
+******************************************************************************/
+int XUsbPs_EpBufferSendWithZLT(XUsbPs *InstancePtr, u8 EpNum,
+				const u8 *BufferPtr, u32 BufferLen)
+{
+	u8 ReqZero = FALSE;
+	XUsbPs_EpSetup *Ep;
+
+	Xil_AssertNonvoid(InstancePtr  != NULL);
+	Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
+
+	Ep = &InstancePtr->DeviceConfig.EpCfg[EpNum].In;
+
+	if ((BufferLen >= Ep->MaxPacketSize) &&
+		(BufferLen % Ep->MaxPacketSize == 0)) {
+		ReqZero = TRUE;
+	}
+
+	return XUsbPs_EpQueueRequest(InstancePtr, EpNum, BufferPtr,
+						BufferLen, ReqZero);
+}
+
+/*****************************************************************************/
+/**
+* This function sends a given data buffer and also sends ZLT packet if it is
+* requested.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	EpNum is the number of the endpoint to receive data from.
+* @param	BufferPtr is a pointer to the buffer to send.
+* @param	BufferLen is the Buffer length.
+* @param	ReqZero is the
+*
+* @return
+*		- XST_SUCCESS: The operation completed successfully.
+*		- XST_FAILURE: An error occured.
+*		- XST_USB_BUF_TOO_BIG: Provided buffer is too big (>16kB).
+*		- XST_USB_NO_DESC_AVAILABLE: No TX descriptor is available.
+*
+******************************************************************************/
+static int XUsbPs_EpQueueRequest(XUsbPs *InstancePtr, u8 EpNum,
+				const u8 *BufferPtr, u32 BufferLen, u8 ReqZero)
+{
+	int		Status;
+	u32		Token;
+	XUsbPs_EpIn	*Ep;
+	XUsbPs_dTD	*DescPtr;
+	u32 		Length;
+	u32		PipeEmpty = 1;
+	u32		Mask = 0x00010000;
+	u32		BitMask = Mask << EpNum;
+	u32		RegValue;
+	u32		Temp;
+	u32 exit = 1;
+
+
+	/* Locate the next available buffer in the ring. A buffer is available
+	 * if its descriptor is not active.
+	 */
+	Ep = &InstancePtr->DeviceConfig.Ep[EpNum].In;
+
+	Xil_DCacheFlushRange((unsigned int)BufferPtr, BufferLen);
+
+	if(Ep->dTDTail != Ep->dTDHead) {
+		PipeEmpty = 0;
+	}
+	XUsbPs_dTDInvalidateCache(Ep->dTDHead);
+
+	/* Tell the caller if we do not have any descriptors available. */
+	if (XUsbPs_dTDIsActive(Ep->dTDHead)) {
+		return XST_USB_NO_DESC_AVAILABLE;
+	}
+
+	/* Remember the current head. */
+	DescPtr = Ep->dTDHead;
+
+	do {
+		Length = (BufferLen > XUSBPS_dTD_BUF_MAX_SIZE) ? XUSBPS_dTD_BUF_MAX_SIZE : BufferLen;
+		/* Attach the provided buffer to the current descriptor.*/
+		Status = XUsbPs_dTDAttachBuffer(Ep->dTDHead, BufferPtr, Length);
+		if (XST_SUCCESS != Status) {
+			return XST_FAILURE;
+		}
+		BufferLen -= Length;
+		BufferPtr += Length;
+
+		XUsbPs_dTDSetActive(Ep->dTDHead);
+		if (BufferLen == 0 && (ReqZero == FALSE)) {
+			XUsbPs_dTDSetIOC(Ep->dTDHead);
+			exit = 0;
+		}
+		XUsbPs_dTDClrTerminate(Ep->dTDHead);
+		XUsbPs_dTDFlushCache(Ep->dTDHead);
+
+		/* Advance the head descriptor pointer to the next descriptor. */
+		Ep->dTDHead = XUsbPs_dTDGetNLP(Ep->dTDHead);
+		/* Terminate the next descriptor and flush the cache.*/
+		XUsbPs_dTDInvalidateCache(Ep->dTDHead);
+		/* Tell the caller if we do not have any descriptors available. */
+		if (XUsbPs_dTDIsActive(Ep->dTDHead)) {
+			return XST_USB_NO_DESC_AVAILABLE;
+		}
+
+		if (ReqZero && BufferLen == 0) {
+			ReqZero = FALSE;
+		}
+
+	} while(BufferLen || exit);
+
+	XUsbPs_dTDSetTerminate(Ep->dTDHead);
+	XUsbPs_dTDFlushCache(Ep->dTDHead);
+
+	if(!PipeEmpty) {
+		/* Read the endpoint prime register. */
+		RegValue = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_EPPRIME_OFFSET);
+		if(RegValue & BitMask) {
+			return XST_SUCCESS;
+		}
+
+		do {
+			RegValue = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET);
+			XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET,
+						RegValue | XUSBPS_CMD_ATDTW_MASK);
+			Temp = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_EPRDY_OFFSET)
+						& BitMask;
+		} while(!(XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET) &
+				XUSBPS_CMD_ATDTW_MASK));
+
+		RegValue = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET);
+		XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET,
+					RegValue & ~XUSBPS_CMD_ATDTW_MASK);
+
+		if(Temp) {
+			return XST_SUCCESS;
+		}
+	}
+
+	/* Check, if the DMA engine is still running. If it is running, we do
+	 * not clear Queue Head fields.
+	 *
+	 * Same cache rule as for the Transfer Descriptor applies for the Queue
+	 * Head.
+	 */
+	XUsbPs_dQHInvalidateCache(Ep->dQH);
+	/* Add the dTD to the dQH */
+	XUsbPs_WritedQH(Ep->dQH, XUSBPS_dQHdTDNLP, DescPtr);
+	Token = XUsbPs_ReaddQH(Ep->dQH, XUSBPS_dQHdTDTOKEN);
+	Token &= ~(XUSBPS_dTDTOKEN_ACTIVE_MASK | XUSBPS_dTDTOKEN_HALT_MASK);
+	XUsbPs_WritedQH(Ep->dQH, XUSBPS_dQHdTDTOKEN, Token);
+
+	XUsbPs_dQHFlushCache(Ep->dQH);
+
+	Status = XUsbPs_EpPrime(InstancePtr, EpNum, XUSBPS_EP_DIRECTION_IN);
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+ * This function receives a data buffer from the endpoint of the given endpoint
+ * number.
+ *
+ * @param	InstancePtr is a pointer to the XUsbPs instance of the
+ *		controller.
+ * @param	EpNum is the number of the endpoint to receive data from.
+ * @param	BufferPtr (OUT param) is a pointer to the buffer pointer to hold
+ *		the reference of the data buffer.
+ * @param	BufferLenPtr (OUT param) is a pointer to the integer that will
+ *		hold the buffer length.
+ * @param	Handle is the opaque handle to be used when the buffer is
+ *		released.
+ *
+ * @return
+ *		- XST_SUCCESS: The operation completed successfully.
+ *		- XST_FAILURE: An error occured.
+ *		- XST_USB_NO_BUF: No buffer available.
+ *
+ * @note
+ * 		After handling the data in the buffer, the user MUST release
+ * 		the buffer using the Handle by calling the
+ * 		XUsbPs_EpBufferRelease() function.
+ *
+ ******************************************************************************/
+int XUsbPs_EpBufferReceive(XUsbPs *InstancePtr, u8 EpNum,
+				u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle)
+{
+	XUsbPs_EpOut	*Ep;
+	XUsbPs_EpSetup	*EpSetup;
+	u32 length = 0;
+
+	Xil_AssertNonvoid(InstancePtr  != NULL);
+	Xil_AssertNonvoid(BufferPtr    != NULL);
+	Xil_AssertNonvoid(BufferLenPtr != NULL);
+	Xil_AssertNonvoid(Handle       != NULL);
+	Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
+
+	/* Locate the next available buffer in the ring. A buffer is available
+	 * if its descriptor is not active.
+	 */
+	Ep = &InstancePtr->DeviceConfig.Ep[EpNum].Out;
+
+	XUsbPs_dTDInvalidateCache(Ep->dTDCurr);
+
+	if (XUsbPs_dTDIsActive(Ep->dTDCurr)) {
+		return XST_USB_NO_BUF;
+	}
+
+	/* The buffer is not active which means that it has been processed by
+	 * the DMA engine and contains valid data.
+	 */
+	EpSetup = &InstancePtr->DeviceConfig.EpCfg[EpNum].Out;
+
+
+	/* Use the buffer pointer stored in the "user data" field of the
+	 * Transfer Descriptor.
+	 */
+	*BufferPtr = (u8 *) XUsbPs_ReaddTD(Ep->dTDCurr,
+						XUSBPS_dTDUSERDATA);
+
+	length = EpSetup->BufSize -
+			XUsbPs_dTDGetTransferLen(Ep->dTDCurr);
+
+	if(length > 0) {
+		*BufferLenPtr = length;
+	}else {
+		*BufferLenPtr = 0;
+	}
+
+	*Handle	= (u32) Ep->dTDCurr;
+
+
+	/* Reset the descriptor's BufferPointer0 and Transfer Length fields to
+	 * their original value. Note that we can not yet re-activate the
+	 * descriptor as the caller will be using the attached buffer. Once the
+	 * caller releases the buffer by calling XUsbPs_EpBufferRelease(), we
+	 * can re-activate the descriptor.
+	 */
+	XUsbPs_WritedTD(Ep->dTDCurr, XUSBPS_dTDBPTR0, *BufferPtr);
+	XUsbPs_dTDSetTransferLen(Ep->dTDCurr, EpSetup->BufSize);
+
+	XUsbPs_dTDFlushCache(Ep->dTDCurr);
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+* This function returns a previously received data buffer to the driver.
+*
+* @param	Handle is a pointer to the buffer that is returned.
+*
+* @return	None.
+*
+******************************************************************************/
+void XUsbPs_EpBufferRelease(u32 Handle)
+{
+	XUsbPs_dTD		*dTDPtr;
+
+	/* Perform sanity check on Handle.*/
+	Xil_AssertVoid((0 != Handle) && (0 == (Handle % XUSBPS_dTD_ALIGN)));
+
+	/* Activate the descriptor and clear the Terminate bit. Make sure to do
+	 * the proper cache handling.
+	 */
+	dTDPtr = (XUsbPs_dTD *) Handle;
+
+	XUsbPs_dTDInvalidateCache(dTDPtr);
+
+	XUsbPs_dTDClrTerminate(dTDPtr);
+	XUsbPs_dTDSetActive(dTDPtr);
+	XUsbPs_dTDSetIOC(dTDPtr);
+
+	XUsbPs_dTDFlushCache(dTDPtr);
+
+}
+
+
+/*****************************************************************************/
+/**
+ * This function sets the handler for endpoint events.
+ *
+ * @param	InstancePtr is a pointer to the XUsbPs instance of the
+ *		controller.
+ * @param	EpNum is the number of the endpoint to receive data from.
+ * @param	Direction is the direction of the endpoint (bitfield):
+ * 			- XUSBPS_EP_DIRECTION_OUT
+ * 			- XUSBPS_EP_DIRECTION_IN
+ * @param	CallBackFunc is the Handler callback function.
+ *		Can be NULL if the user wants to disable the handler entry.
+ * @param	CallBackRef is the user definable data pointer that will be
+ *		passed back if the handler is called. May be NULL.
+ *
+ * @return
+ *		- XST_SUCCESS: The operation completed successfully.
+ *		- XST_FAILURE: An error occured.
+ *		- XST_INVALID_PARAM: Invalid parameter passed.
+ *
+ * @note
+ * 		The user can disable a handler by setting the callback function
+ * 		pointer to NULL.
+ *
+ ******************************************************************************/
+int XUsbPs_EpSetHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction,
+			 XUsbPs_EpHandlerFunc CallBackFunc,
+			 void *CallBackRef)
+{
+	XUsbPs_Endpoint	*Ep;
+
+	Xil_AssertNonvoid(InstancePtr  != NULL);
+	Xil_AssertNonvoid(CallBackFunc != NULL);
+	Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
+
+	Ep = &InstancePtr->DeviceConfig.Ep[EpNum];
+
+	if(Direction & XUSBPS_EP_DIRECTION_OUT) {
+		Ep->Out.HandlerFunc	= CallBackFunc;
+		Ep->Out.HandlerRef	= CallBackRef;
+	}
+
+	if(Direction & XUSBPS_EP_DIRECTION_IN) {
+		Ep->In.HandlerFunc	= CallBackFunc;
+		Ep->In.HandlerRef	= CallBackRef;
+	}
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+* This function primes an endpoint.
+*
+* @param	InstancePtr is pointer to the XUsbPs instance.
+* @param	EpNum is the number of the endpoint to receive data from.
+* @param	Direction is the direction of the endpoint (bitfield):
+* 			- XUSBPS_EP_DIRECTION_OUT
+* 			- XUSBPS_EP_DIRECTION_IN
+*
+* @return
+*		- XST_SUCCESS: The operation completed successfully.
+*		- XST_FAILURE: An error occured.
+*		- XST_INVALID_PARAM: Invalid parameter passed.
+*
+* @note		None.
+*
+******************************************************************************/
+int XUsbPs_EpPrime(XUsbPs *InstancePtr, u8 EpNum, u8 Direction)
+{
+	u32	Mask;
+
+	Xil_AssertNonvoid(InstancePtr  != NULL);
+	Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
+
+	/* Get the right bit mask for the endpoint direction. */
+	switch (Direction) {
+
+	case XUSBPS_EP_DIRECTION_OUT:
+		Mask = 0x00000001;
+		break;
+
+	case XUSBPS_EP_DIRECTION_IN:
+		Mask = 0x00010000;
+		break;
+
+	default:
+		return XST_INVALID_PARAM;
+	}
+
+	/* Write the endpoint prime register. */
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_EPPRIME_OFFSET, Mask << EpNum);
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+* This function extracts the Setup Data from a given endpoint.
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+* @param	EpNum is the number of the endpoint to receive data from.
+* @param	SetupDataPtr is a pointer to the setup data structure to be
+*		filled.
+*
+* @return
+*		- XST_SUCCESS: The operation completed successfully.
+*		- XST_FAILURE: An error occured.
+*
+* @note		None.
+******************************************************************************/
+int XUsbPs_EpGetSetupData(XUsbPs *InstancePtr, int EpNum,
+				XUsbPs_SetupData *SetupDataPtr)
+{
+	XUsbPs_EpOut	*Ep;
+
+	u32	Data[2];
+	u8	*p;
+
+	int Timeout;
+
+	Xil_AssertNonvoid(InstancePtr  != NULL);
+	Xil_AssertNonvoid(SetupDataPtr != NULL);
+	Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
+
+	Ep = &InstancePtr->DeviceConfig.Ep[EpNum].Out;
+
+
+	/* Get the data from the Queue Heads Setup buffer into local variables
+	 * so we can extract the setup data values.
+	 */
+	do {
+		/* Arm the tripwire. The tripwire will tell us if a new setup
+		 * packet arrived (in which case the tripwire bit will be
+		 * cleared) while we were reading the buffer. If a new setup
+		 * packet arrived the buffer is corrupted and we continue
+		 * reading.
+		 */
+		XUsbPs_SetSetupTripwire(InstancePtr);
+
+		XUsbPs_dQHInvalidateCache(Ep->dQH);
+
+		Data[0] = XUsbPs_ReaddQH(Ep->dQH, XUSBPS_dQHSUB0);
+		Data[1] = XUsbPs_ReaddQH(Ep->dQH, XUSBPS_dQHSUB1);
+	} while (FALSE == XUsbPs_SetupTripwireIsSet(InstancePtr));
+
+	/* Clear the pending endpoint setup stat bit.
+	 */
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_EPSTAT_OFFSET, 1 << EpNum);
+
+	/* Clear the Tripwire bit and continue.
+	 */
+	XUsbPs_ClrSetupTripwire(InstancePtr);
+
+
+	/* Data in the setup buffer is being converted by the core to big
+	 * endian format. We have to take care of proper byte swapping when
+	 * reading the setup data values.
+	 *
+	 * Need to check if there is a smarter way to do this and take the
+	 * processor/memory-controller endianess into account?
+	 */
+	p = (u8 *) Data;
+
+	SetupDataPtr->bmRequestType	= p[0];
+	SetupDataPtr->bRequest		= p[1];
+	SetupDataPtr->wValue		= (p[3] << 8) | p[2];
+	SetupDataPtr->wIndex		= (p[5] << 8) | p[4];
+	SetupDataPtr->wLength		= (p[7] << 8) | p[6];
+
+	/* Before we leave we need to make sure that the endpoint setup bit has
+	 * cleared. It needs to be 0 before the endpoint can be re-primed.
+	 *
+	 * Note: According to the documentation this endpoint setup bit should
+	 * clear within 1-2us after it has been written above. This means that
+	 * we should never catch it being 1 here. However, we still need to
+	 * poll it to make sure. Just in case, we use a counter 'Timeout' so we
+	 * won't hang here if the bit is stuck for some reason.
+	 */
+	Timeout = XUSBPS_TIMEOUT_COUNTER;
+	while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_EPSTAT_OFFSET) &
+				(1 << EpNum)) && --Timeout) {
+		/* NOP */
+	}
+	if (0 == Timeout) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This function initializes the endpoint pointer data structure.
+*
+* The function sets up the local data structure with the aligned addresses for
+* the Queue Head and Transfer Descriptors.
+*
+* @param	DevCfgPtr is pointer to the XUsbPs DEVICE configuration
+*		structure.
+*
+* @return	none
+*
+* @note
+* 		Endpoints of type XUSBPS_EP_TYPE_NONE are not used in the
+* 		system. Therefore no memory is reserved for them.
+*
+******************************************************************************/
+static void XUsbPs_EpListInit(XUsbPs_DeviceConfig *DevCfgPtr)
+{
+	int	EpNum;
+	u8	*p;
+
+	XUsbPs_Endpoint	*Ep;
+	XUsbPs_EpConfig	*EpCfg;
+
+	/* Set up the XUsbPs_Endpoint array. This array is used to define the
+	 * location of the Queue Head list and the Transfer Descriptors in the
+	 * block of DMA memory that has been passed into the driver.
+	 *
+	 * 'p' is used to set the pointers in the local data structure.
+	 * Initially 'p' is pointed to the beginning of the DMAable memory
+	 * block. As pointers are assigned, 'p' is incremented by the size of
+	 * the respective object.
+	 */
+	Ep	= DevCfgPtr->Ep;
+	EpCfg	= DevCfgPtr->EpCfg;
+
+	/* Start off with 'p' pointing to the (aligned) beginning of the DMA
+	 * buffer.
+	 */
+	p = (u8 *) DevCfgPtr->PhysAligned;
+
+
+	/* Initialize the Queue Head pointer list.
+	 *
+	 * Each endpoint has two Queue Heads. One for the OUT direction and one
+	 * for the IN direction. An OUT Queue Head is always followed by an IN
+	 * Queue Head.
+	 *
+	 * Queue Head alignment is XUSBPS_dQH_ALIGN.
+	 *
+	 * Note that we have to reserve space here for unused endpoints.
+	 */
+	for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
+		/* OUT Queue Head */
+		Ep[EpNum].Out.dQH = (XUsbPs_dQH *) p;
+		p += XUSBPS_dQH_ALIGN;
+
+		/* IN Queue Head */
+		Ep[EpNum].In.dQH = (XUsbPs_dQH *) p;
+		p += XUSBPS_dQH_ALIGN;
+	}
+
+
+	/* 'p' now points to the first address after the Queue Head list. The
+	 * Transfer Descriptors start here.
+	 *
+	 * Each endpoint has a variable number of Transfer Descriptors
+	 * depending on user configuration.
+	 *
+	 * Transfer Descriptor alignment is XUSBPS_dTD_ALIGN.
+	 */
+	for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
+		/* OUT Descriptors.
+		 */
+		if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].Out.Type) {
+			Ep[EpNum].Out.dTDs		= (XUsbPs_dTD *) p;
+			Ep[EpNum].Out.dTDCurr	= (XUsbPs_dTD *) p;
+			p += XUSBPS_dTD_ALIGN * EpCfg[EpNum].Out.NumBufs;
+		}
+
+		/* IN Descriptors.
+		 */
+		if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].In.Type) {
+			Ep[EpNum].In.dTDs		= (XUsbPs_dTD *) p;
+			Ep[EpNum].In.dTDHead	= (XUsbPs_dTD *) p;
+			Ep[EpNum].In.dTDTail	= (XUsbPs_dTD *) p;
+			p += XUSBPS_dTD_ALIGN * EpCfg[EpNum].In.NumBufs;
+		}
+	}
+
+
+	/* 'p' now points to the first address after the Transfer Descriptors.
+	 * The data buffers for the OUT Transfer Desciptors start here.
+	 *
+	 * Note that IN (TX) Transfer Descriptors are not assigned buffers at
+	 * this point. Buffers will be assigned when the user calls the send()
+	 * function.
+	 */
+	for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
+
+		if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].Out.Type) {
+			/* If BufSize for this endpoint is set to 0 it means
+			 * that we do not need to attach a buffer to this
+			 * descriptor. We also initialize it's buffer pointer
+			 * to NULL.
+			 */
+			if (0 == EpCfg[EpNum].Out.BufSize) {
+				Ep[EpNum].Out.dTDBufs = NULL;
+				continue;
+			}
+
+			Ep[EpNum].Out.dTDBufs = p;
+			p += EpCfg[EpNum].Out.BufSize * EpCfg[EpNum].Out.NumBufs;
+		}
+	}
+
+
+	/* Initialize the endpoint event handlers to NULL.
+	 */
+	for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
+		Ep[EpNum].Out.HandlerFunc = NULL;
+		Ep[EpNum].In.HandlerFunc  = NULL;
+	}
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This function initializes the Queue Head List in memory.
+*
+* @param	DevCfgPtr is a pointer to the XUsbPs DEVICE configuration
+*		structure.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void XUsbPs_dQHInit(XUsbPs_DeviceConfig *DevCfgPtr)
+{
+	int	EpNum;
+
+	XUsbPs_Endpoint	*Ep;
+	XUsbPs_EpConfig	*EpCfg;
+
+	/* Setup pointers for simpler access. */
+	Ep	= DevCfgPtr->Ep;
+	EpCfg	= DevCfgPtr->EpCfg;
+
+
+	/* Go through the list of Queue Head entries and:
+	 *
+	 * - Set Transfer Descriptor addresses
+	 * - Set Maximum Packet Size
+	 * - Disable Zero Length Termination (ZLT) for non-isochronous transfers
+	 * - Enable Interrupt On Setup (IOS)
+	 *
+	 */
+	for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
+
+		/* OUT Queue Heads.*/
+		if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].Out.Type) {
+			XUsbPs_WritedQH(Ep[EpNum].Out.dQH,
+					XUSBPS_dQHCPTR, Ep[EpNum].Out.dTDs);
+
+			/* For isochronous, ep max packet size translates to different
+			 * values in queue head than other types.
+			 * Also	enable ZLT for isochronous.
+			 */
+			if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].Out.Type) {
+				XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].Out.dQH,
+                        EpCfg[EpNum].Out.MaxPacketSize);
+				XUsbPs_dQHEnableZLT(Ep[EpNum].Out.dQH);
+			}else {
+				XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].Out.dQH,
+					    EpCfg[EpNum].Out.MaxPacketSize);
+				XUsbPs_dQHDisableZLT(Ep[EpNum].Out.dQH);
+			}
+
+			/* Only control OUT needs this */
+			if(XUSBPS_EP_TYPE_CONTROL == EpCfg[EpNum].Out.Type) {
+				XUsbPs_dQHSetIOS(Ep[EpNum].Out.dQH);
+			}
+
+			/* Set up the overlay next dTD pointer. */
+			XUsbPs_WritedQH(Ep[EpNum].Out.dQH,
+					XUSBPS_dQHdTDNLP, Ep[EpNum].Out.dTDs);
+
+			XUsbPs_dQHFlushCache(Ep[EpNum].Out.dQH);
+		}
+
+
+		/* IN Queue Heads. */
+		if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].In.Type) {
+			XUsbPs_WritedQH(Ep[EpNum].In.dQH,
+				  XUSBPS_dQHCPTR, Ep[EpNum].In.dTDs);
+
+
+			/* Isochronous ep packet size can be larger than 1024.*/
+			if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].In.Type) {
+				XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].In.dQH,
+						EpCfg[EpNum].In.MaxPacketSize);
+				XUsbPs_dQHEnableZLT(Ep[EpNum].In.dQH);
+			}else {
+				XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].In.dQH,
+					    EpCfg[EpNum].In.MaxPacketSize);
+				XUsbPs_dQHDisableZLT(Ep[EpNum].In.dQH);
+			}
+
+			XUsbPs_dQHFlushCache(Ep[EpNum].In.dQH);
+		}
+	}
+}
+
+
+/*****************************************************************************/
+/**
+ *
+ * This function initializes the Transfer Descriptors lists in memory.
+ *
+ * @param	DevCfgPtr is a pointer to the XUsbPs DEVICE configuration
+ *		structure.
+ *
+ * @return
+ *		- XST_SUCCESS: The operation completed successfully.
+ *		- XST_FAILURE: An error occured.
+ *
+ ******************************************************************************/
+static int XUsbPs_dTDInit(XUsbPs_DeviceConfig *DevCfgPtr)
+{
+	int	EpNum;
+
+	XUsbPs_Endpoint	*Ep;
+	XUsbPs_EpConfig	*EpCfg;
+
+	/* Setup pointers for simpler access. */
+	Ep	= DevCfgPtr->Ep;
+	EpCfg	= DevCfgPtr->EpCfg;
+
+
+	/* Walk through the list of endpoints and initialize their Transfer
+	 * Descriptors.
+	 */
+	for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
+		int	Td;
+		int	NumdTD;
+
+		XUsbPs_EpOut	*Out = &Ep[EpNum].Out;
+		XUsbPs_EpIn	*In  = &Ep[EpNum].In;
+
+
+		/* OUT Descriptors
+		 * ===============
+		 *
+		 * + Set the next link pointer
+		 * + Set the interrupt complete and the active bit
+		 * + Attach the buffer to the dTD
+		 */
+		if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].Out.Type) {
+			NumdTD = EpCfg[EpNum].Out.NumBufs;
+		}
+		else {
+			NumdTD = 0;
+		}
+
+		for (Td = 0; Td < NumdTD; ++Td) {
+			int	Status;
+
+			int NextTd = (Td + 1) % NumdTD;
+
+			XUsbPs_dTDInvalidateCache(&Out->dTDs[Td]);
+
+			/* Set NEXT link pointer. */
+			XUsbPs_WritedTD(&Out->dTDs[Td], XUSBPS_dTDNLP,
+					  &Out->dTDs[NextTd]);
+
+			/* Set the OUT descriptor ACTIVE and enable the
+			 * interrupt on complete.
+			 */
+			XUsbPs_dTDSetActive(&Out->dTDs[Td]);
+			XUsbPs_dTDSetIOC(&Out->dTDs[Td]);
+
+
+			/* Set up the data buffer with the descriptor. If the
+			 * buffer pointer is NULL it means that we do not need
+			 * to attach a buffer to this descriptor.
+			 */
+			if (NULL == Out->dTDBufs) {
+				XUsbPs_dTDFlushCache(&Out->dTDs[Td]);
+				continue;
+			}
+
+			Status = XUsbPs_dTDAttachBuffer(
+					&Out->dTDs[Td],
+					Out->dTDBufs +
+						(Td * EpCfg[EpNum].Out.BufSize),
+					EpCfg[EpNum].Out.BufSize);
+			if (XST_SUCCESS != Status) {
+				return XST_FAILURE;
+			}
+
+			XUsbPs_dTDFlushCache(&Out->dTDs[Td]);
+		}
+
+
+		/* IN Descriptors
+		 * ==============
+		 *
+		 * + Set the next link pointer
+		 * + Set the Terminate bit to mark it available
+		 */
+		if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].In.Type) {
+			NumdTD = EpCfg[EpNum].In.NumBufs;
+		}
+		else {
+			NumdTD = 0;
+		}
+
+		for (Td = 0; Td < NumdTD; ++Td) {
+			int NextTd = (Td + 1) % NumdTD;
+
+			XUsbPs_dTDInvalidateCache(&In->dTDs[Td]);
+
+			/* Set NEXT link pointer. */
+			XUsbPs_WritedTD(In->dTDs[Td], XUSBPS_dTDNLP,
+					  In->dTDs[NextTd]);
+
+			/* Set the IN descriptor's TERMINATE bits. */
+			XUsbPs_dTDSetTerminate(In->dTDs[Td]);
+
+			XUsbPs_dTDFlushCache(&In->dTDs[Td]);
+		}
+	}
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+ *
+ * This function associates a buffer with a Transfer Descriptor. The function
+ * will take care of splitting the buffer into multiple 4kB aligned segments if
+ * the buffer happens to span one or more 4kB pages.
+ *
+ * @param	dTDIndex is a pointer to the Transfer Descriptor
+ * @param	BufferPtr is pointer to the buffer to link to the descriptor.
+ * @param	BufferLen is the length of the buffer.
+ *
+ * @return
+ *		- XST_SUCCESS: The operation completed successfully.
+ *		- XST_FAILURE: An error occured.
+ *		- XST_USB_BUF_TOO_BIG: The provided buffer is bigger than tha
+ *		maximum allowed buffer size (16k).
+ *
+ * @note
+ * 		Cache invalidation and flushing needs to be handler by the
+ * 		caller of this function.
+ *
+ ******************************************************************************/
+static int XUsbPs_dTDAttachBuffer(XUsbPs_dTD *dTDPtr,
+					const u8 *BufferPtr, u32 BufferLen)
+{
+	u32	BufAddr;
+	u32	BufEnd;
+	u32	PtrNum;
+
+	Xil_AssertNonvoid(dTDPtr    != NULL);
+
+	/* Check if the buffer is smaller than 16kB. */
+	if (BufferLen > XUSBPS_dTD_BUF_MAX_SIZE) {
+		return XST_USB_BUF_TOO_BIG;
+	}
+
+	/* Get a u32 of the buffer pointer to avoid casting in the following
+	 * logic operations.
+	 */
+	BufAddr = (u32) BufferPtr;
+
+
+	/* Set the buffer pointer 0. Buffer pointer 0 can point to any location
+	 * in memory. It does not need to be 4kB aligned. However, if the
+	 * provided buffer spans one or more 4kB boundaries, we need to set up
+	 * the subsequent buffer pointers which must be 4kB aligned.
+	 */
+	XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDBPTR(0), BufAddr);
+
+	/* Check if the buffer spans a 4kB boundary.
+	 *
+	 * Only do this check, if we are not sending a 0-length buffer.
+	 */
+	if (BufferLen > 0) {
+		BufEnd = BufAddr + BufferLen -1;
+		PtrNum = 1;
+
+		while ((BufAddr & 0xFFFFF000) != (BufEnd & 0xFFFFF000)) {
+			/* The buffer spans at least one boundary, let's set
+			 * the next buffer pointer and repeat the procedure
+			 * until the end of the buffer and the pointer written
+			 * are in the same 4kB page.
+			 */
+			BufAddr = (BufAddr + 0x1000) & 0xFFFFF000;
+			XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDBPTR(PtrNum),
+								BufAddr);
+			PtrNum++;
+		}
+	}
+
+	/* Set the length of the buffer. */
+	XUsbPs_dTDSetTransferLen(dTDPtr, BufferLen);
+
+
+	/* We remember the buffer pointer in the user data field (reserved
+	 * field in the dTD). This makes it easier to reset the buffer pointer
+	 * after a buffer has been received on the endpoint. The buffer pointer
+	 * needs to be reset because the DMA engine modifies the buffer pointer
+	 * while receiving.
+	 */
+	XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDUSERDATA, BufferPtr);
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+ * This function set the Max PacketLen for the queue head for isochronous EP.
+ *
+ * If the max packet length is greater than XUSBPS_MAX_PACKET_SIZE, then
+ * Mult bits are set to reflect that.
+ *
+ * @param	dQHPtr is a pointer to the dQH element.
+ * @param	Len is the Length to be set.
+ *
+ ******************************************************************************/
+static void XUsbPs_dQHSetMaxPacketLenISO(XUsbPs_dQH *dQHPtr, u32 Len)
+{
+	u32 Mult = (Len & ENDPOINT_MAXP_MULT_MASK) >> ENDPOINT_MAXP_MULT_SHIFT;
+	u32 MaxPktSize = (Mult > 1) ? ENDPOINT_MAXP_LENGTH : Len;
+
+	if (MaxPktSize > XUSBPS_MAX_PACKET_SIZE) {
+		return;
+	}
+
+	if (Mult > 3) {
+		return;
+	}
+
+	/* Set Max packet size */
+	XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG,
+		(XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) &
+			~XUSBPS_dQHCFG_MPL_MASK) |
+			(MaxPktSize << XUSBPS_dQHCFG_MPL_SHIFT));
+
+	/* Set Mult to tell hardware how many transactions in each microframe */
+	XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG,
+		(XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) &
+			~XUSBPS_dQHCFG_MULT_MASK) |
+			(Mult << XUSBPS_dQHCFG_MULT_SHIFT));
+
+}
+
+/*****************************************************************************/
+/**
+* This function reconfigures one Ep corresponding to host's request of setting
+* alternate interface. The endpoint has been disabled before this call.
+*
+* Both QH and dTDs are updated for the new configuration.
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+* @param	CfgPtr
+* 		Pointer to the updated XUsbPs DEVICE configuration structure.
+*
+* @param	EpNum
+*		The endpoint to be reconfigured.
+*
+* @param NewDirection
+*		The new transfer direction the endpoint.
+*
+* @param DirectionChanged
+*		A boolean value indicate whether the transfer direction has changed.
+*
+* @return
+*	XST_SUCCESS upon success, XST_FAILURE otherwise.
+*
+******************************************************************************/
+int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr,
+				int EpNum, unsigned short NewDirection,
+				int DirectionChanged) {
+
+	int Status = XST_SUCCESS;
+	XUsbPs_Endpoint *Ep;
+	XUsbPs_EpConfig *EpCfg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(CfgPtr      != NULL);
+
+	Ep = CfgPtr->Ep;
+	EpCfg = CfgPtr->EpCfg;
+
+	/* If transfer direction changes, dTDs has to be reset
+	 * Number of buffers are preset and should not to be changed.
+	 */
+	if(DirectionChanged) {
+		if(NewDirection == XUSBPS_EP_DIRECTION_OUT) {
+			u8 *p;
+
+			/* Swap the pointer to the dTDs.
+			 */
+			Ep[EpNum].Out.dTDs = Ep[EpNum].In.dTDs;
+			p = (u8 *)(Ep[EpNum].Out.dTDs + XUSBPS_dTD_ALIGN * EpCfg[EpNum].Out.NumBufs);
+
+			/* Set the OUT buffer if buffer size is not zero
+			 */
+			if(EpCfg[EpNum].Out.BufSize > 0) {
+				Ep[EpNum].Out.dTDBufs = p;
+			}
+		} else if(NewDirection == XUSBPS_EP_DIRECTION_IN) {
+			Ep[EpNum].In.dTDs = Ep[EpNum].Out.dTDs;
+		}
+	}
+
+	/* Reset dTD progress tracking pointers
+	 */
+	if(NewDirection == XUSBPS_EP_DIRECTION_IN) {
+		Ep[EpNum].In.dTDHead = Ep[EpNum].In.dTDTail = Ep[EpNum].In.dTDs;
+	} else if(NewDirection == XUSBPS_EP_DIRECTION_OUT) {
+		Ep[EpNum].Out.dTDCurr = Ep[EpNum].Out.dTDs;
+	}
+
+	/* Reinitialize information in QH
+	 */
+	XUsbPs_dQHReinitEp(CfgPtr, EpNum, NewDirection);
+
+	/* Reinitialize the dTD linked list, and flush the cache
+	 */
+	Status = XUsbPs_dTDReinitEp(CfgPtr, EpNum, NewDirection);
+	if(Status != XST_SUCCESS) {
+		return Status;
+	}
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+ * This function re-initializes the Queue Head List in memory.
+ * The endpoint 1 has been disabled before this call.
+ *
+ * @param	DevCfgPtr
+ * 		Pointer to the updated XUsbPs DEVICE configuration structure.
+ *
+ * @param	EpNum
+ *		The endpoint to be reconfigured.
+ *
+ * @param	NewDirection
+ *		The new transfer direction of endpoint 1
+ *
+ * @return	none
+ *
+ ******************************************************************************/
+static void XUsbPs_dQHReinitEp(XUsbPs_DeviceConfig *DevCfgPtr,
+int EpNum, unsigned short NewDirection)
+{
+	XUsbPs_Endpoint	*Ep;
+	XUsbPs_EpConfig	*EpCfg;
+
+	/* Setup pointers for simpler access.
+	 */
+	Ep	= DevCfgPtr->Ep;
+	EpCfg	= DevCfgPtr->EpCfg;
+
+
+	/* Go through the list of Queue Head entries and:
+	 *
+	 * - Set Transfer Descriptor addresses
+	 * - Set Maximum Packet Size
+	 * - Disable Zero Length Termination (ZLT) for non-isochronous transfers
+	 * - Enable Interrupt On Setup (IOS)
+	 *
+	 */
+	if(NewDirection == XUSBPS_EP_DIRECTION_OUT) {
+		/* OUT Queue Heads.
+		 */
+		XUsbPs_WritedQH(Ep[EpNum].Out.dQH,
+			XUSBPS_dQHCPTR, Ep[EpNum].Out.dTDs);
+
+		/* For isochronous, ep max packet size translates to different
+		 * values in queue head than other types.
+		 * Also	enable ZLT for isochronous.
+		 */
+		if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].Out.Type) {
+			XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].Out.dQH,
+   					EpCfg[EpNum].Out.MaxPacketSize);
+			XUsbPs_dQHEnableZLT(Ep[EpNum].Out.dQH);
+		}else {
+			XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].Out.dQH,
+				    EpCfg[EpNum].Out.MaxPacketSize);
+			XUsbPs_dQHDisableZLT(Ep[EpNum].Out.dQH);
+		}
+
+		XUsbPs_dQHSetIOS(Ep[EpNum].Out.dQH);
+
+		/* Set up the overlay next dTD pointer.
+		 */
+		XUsbPs_WritedQH(Ep[EpNum].Out.dQH,
+				XUSBPS_dQHdTDNLP, Ep[EpNum].Out.dTDs);
+
+		XUsbPs_dQHFlushCache(Ep[EpNum].Out.dQH);
+
+	} else if(NewDirection == XUSBPS_EP_DIRECTION_IN) {
+
+		/* IN Queue Heads.
+		 */
+		XUsbPs_WritedQH(Ep[EpNum].In.dQH,
+			  XUSBPS_dQHCPTR, Ep[EpNum].In.dTDs);
+
+		/* Isochronous ep packet size can be larger than 1024. */
+		if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].In.Type) {
+			XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].In.dQH,
+   				EpCfg[EpNum].In.MaxPacketSize);
+			XUsbPs_dQHEnableZLT(Ep[EpNum].In.dQH);
+		}else {
+			XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].In.dQH,
+			    EpCfg[EpNum].In.MaxPacketSize);
+			XUsbPs_dQHDisableZLT(Ep[EpNum].In.dQH);
+		}
+
+		XUsbPs_dQHSetIOS(Ep[EpNum].In.dQH);
+
+		XUsbPs_dQHFlushCache(Ep[EpNum].In.dQH);
+	}
+
+}
+
+/*****************************************************************************/
+/**
+ *
+ * This function re-initializes the Transfer Descriptors lists in memory.
+ * The endpoint has been disabled before the call. The transfer descriptors
+ * list pointer has been initialized too.
+ *
+ * @param	DevCfgPtr
+ * 		Pointer to the XUsbPs DEVICE configuration structure.
+ *
+ * @param	EpNum
+ *		The endpoint to be reconfigured.
+ *
+ * @param	NewDirection
+ *		The new transfer direction of endpoint 1
+ *
+ * @return
+ *		- XST_SUCCESS: The operation completed successfully.
+ *		- XST_FAILURE: An error occured.
+ *
+ ******************************************************************************/
+static int XUsbPs_dTDReinitEp(XUsbPs_DeviceConfig *DevCfgPtr,
+int EpNum, unsigned short NewDirection)
+{
+	XUsbPs_Endpoint	*Ep;
+	XUsbPs_EpConfig	*EpCfg;
+	int	Td;
+	int	NumdTD;
+
+
+	/* Setup pointers for simpler access.
+	 */
+	Ep	= DevCfgPtr->Ep;
+	EpCfg	= DevCfgPtr->EpCfg;
+
+
+	if(NewDirection == XUSBPS_EP_DIRECTION_OUT) {
+		XUsbPs_EpOut	*Out = &Ep[EpNum].Out;
+
+		/* OUT Descriptors
+		 * ===============
+		 *
+		 * + Set the next link pointer
+		 * + Set the interrupt complete and the active bit
+		 * + Attach the buffer to the dTD
+		 */
+		NumdTD = EpCfg[EpNum].Out.NumBufs;
+
+		for (Td = 0; Td < NumdTD; ++Td) {
+			int	Status;
+
+			int NextTd = (Td + 1) % NumdTD;
+
+			XUsbPs_dTDInvalidateCache(&Out->dTDs[Td]);
+
+			/* Set NEXT link pointer.
+			 */
+			XUsbPs_WritedTD(&Out->dTDs[Td], XUSBPS_dTDNLP,
+					  &Out->dTDs[NextTd]);
+
+			/* Set the OUT descriptor ACTIVE and enable the
+			 * interrupt on complete.
+			 */
+			XUsbPs_dTDSetActive(&Out->dTDs[Td]);
+			XUsbPs_dTDSetIOC(&Out->dTDs[Td]);
+
+			/* Set up the data buffer with the descriptor. If the
+			 * buffer pointer is NULL it means that we do not need
+			 * to attach a buffer to this descriptor.
+			 */
+			if (Out->dTDBufs != NULL) {
+
+				Status = XUsbPs_dTDAttachBuffer(
+						&Out->dTDs[Td],
+						Out->dTDBufs +
+							(Td * EpCfg[EpNum].Out.BufSize),
+						EpCfg[EpNum].Out.BufSize);
+				if (Status != XST_SUCCESS) {
+					return XST_FAILURE;
+				}
+			}
+			XUsbPs_dTDFlushCache(&Out->dTDs[Td]);
+		}
+	} else if(NewDirection == XUSBPS_EP_DIRECTION_IN) {
+		XUsbPs_EpIn	*In  = &Ep[EpNum].In;
+
+		/* IN Descriptors
+		 * ==============
+		 *
+		 * + Set the next link pointer
+		 * + Set the Terminate bit to mark it available
+		 */
+		NumdTD = EpCfg[EpNum].In.NumBufs;
+
+		for (Td = 0; Td < NumdTD; ++Td) {
+			int NextTd = (Td + 1) % NumdTD;
+
+			XUsbPs_dTDInvalidateCache(&In->dTDs[Td]);
+
+			/* Set NEXT link pointer.
+			 */
+			XUsbPs_WritedTD(&In->dTDs[Td], XUSBPS_dTDNLP,
+					  &In->dTDs[NextTd]);
+
+			/* Set the IN descriptor's TERMINATE bits.
+			 */
+			XUsbPs_dTDSetTerminate(&In->dTDs[Td]);
+
+			XUsbPs_dTDFlushCache(&In->dTDs[Td]);
+		}
+	}
+
+	return XST_SUCCESS;
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps_endpoint.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps_endpoint.h
new file mode 100644
index 000000000..8b6984980
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps_endpoint.h
@@ -0,0 +1,521 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xusbps_endpoint.h
+ *
+ * This is an internal file containung the definitions for endpoints. It is
+ * included by the xusbps_endpoint.c which is implementing the endpoint
+ * functions and by xusbps_intr.c.
+ *
+ * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- --------------------------------------------------------
+ * 1.00a wgr  10/10/10 First release
+ * 

+ *
+ ******************************************************************************/
+#ifndef XUSBPS_ENDPOINT_H
+#define XUSBPS_ENDPOINT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xusbps.h"
+#include "xil_types.h"
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+
+/**
+ * Endpoint Device Transfer Descriptor
+ *
+ * The dTD describes to the device controller the location and quantity of data
+ * to be sent/received for given transfer. The driver does not attempt to
+ * modify any field in an active dTD except the Next Link Pointer.
+ */
+#define XUSBPS_dTDNLP		0x00 /**< Pointer to the next descriptor */
+#define XUSBPS_dTDTOKEN	0x04 /**< Descriptor Token */
+#define XUSBPS_dTDBPTR0	0x08 /**< Buffer Pointer 0 */
+#define XUSBPS_dTDBPTR1	0x0C /**< Buffer Pointer 1 */
+#define XUSBPS_dTDBPTR2	0x10 /**< Buffer Pointer 2 */
+#define XUSBPS_dTDBPTR3	0x14 /**< Buffer Pointer 3 */
+#define XUSBPS_dTDBPTR4	0x18 /**< Buffer Pointer 4 */
+#define XUSBPS_dTDBPTR(n)	(XUSBPS_dTDBPTR0 + (n) * 0x04)
+#define XUSBPS_dTDRSRVD	0x1C /**< Reserved field */
+
+/* We use the reserved field in the dTD to store user data. */
+#define XUSBPS_dTDUSERDATA	XUSBPS_dTDRSRVD /**< Reserved field */
+
+
+/** @name dTD Next Link Pointer (dTDNLP) bit positions.
+ *  @{
+ */
+#define XUSBPS_dTDNLP_T_MASK		0x00000001
+				/**< USB dTD Next Link Pointer Terminate Bit */
+#define XUSBPS_dTDNLP_ADDR_MASK	0xFFFFFFE0
+				/**< USB dTD Next Link Pointer Address [31:5] */
+/* @} */
+
+
+/** @name dTD Token (dTDTOKEN) bit positions.
+ *  @{
+ */
+#define XUSBPS_dTDTOKEN_XERR_MASK	0x00000008 /**< dTD Transaction Error */
+#define XUSBPS_dTDTOKEN_BUFERR_MASK	0x00000020 /**< dTD Data Buffer Error */
+#define XUSBPS_dTDTOKEN_HALT_MASK	0x00000040 /**< dTD Halted Flag */
+#define XUSBPS_dTDTOKEN_ACTIVE_MASK	0x00000080 /**< dTD Active Bit */
+#define XUSBPS_dTDTOKEN_MULTO_MASK	0x00000C00 /**< Multiplier Override Field [1:0] */
+#define XUSBPS_dTDTOKEN_IOC_MASK	0x00008000 /**< Interrupt on Complete Bit */
+#define XUSBPS_dTDTOKEN_LEN_MASK	0x7FFF0000 /**< Transfer Length Field */
+/* @} */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ *
+ * IMPORTANT NOTE:
+ * ===============
+ *
+ * Many of the following macros modify Device Queue Head (dQH) data structures
+ * and Device Transfer Descriptor (dTD) data structures. Those structures can
+ * potentially reside in CACHED memory. Therefore, it's the callers
+ * responsibility to ensure cache coherency by using provided
+ *
+ * 	XUsbPs_dQHInvalidateCache()
+ * 	XUsbPs_dQHFlushCache()
+ * 	XUsbPs_dTDInvalidateCache()
+ * 	XUsbPs_dTDFlushCache()
+ *
+ * function calls.
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDInvalidateCache(dTDPtr) \
+		Xil_DCacheInvalidateRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
+
+#define XUsbPs_dTDFlushCache(dTDPtr) \
+		Xil_DCacheFlushRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
+
+#define XUsbPs_dQHInvalidateCache(dQHPtr) \
+		Xil_DCacheInvalidateRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH))
+
+#define XUsbPs_dQHFlushCache(dQHPtr) \
+		Xil_DCacheFlushRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH))
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Transfer Length for the given Transfer Descriptor.
+ *
+ * @param	dTDPtr is pointer to the dTD element.
+ * @param	Len is the length to be set. Range: 0..16384
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetTransferLen(dTDPtr, Len)				\
+		XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, 		\
+			(XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) &	\
+				~XUSBPS_dTDTOKEN_LEN_MASK) | ((Len) << 16))
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro gets the Next Link pointer of the given Transfer Descriptor.
+ *
+ * @param	dTDPtr is pointer to the dTD element.
+ *
+ * @return 	TransferLength field of the descriptor.
+ *
+ * @note	C-style signature:
+ *		u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDGetNLP(dTDPtr)					\
+		(XUsbPs_dTD *) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP)\
+					& XUSBPS_dTDNLP_ADDR_MASK))
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Next Link pointer of the given Transfer Descriptor.
+ *
+ * @param	dTDPtr is a pointer to the dTD element.
+ * @param	NLP is the Next Link Pointer
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetNLP(dTDPtr, NLP)					\
+		XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, 		\
+			(XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) &	\
+				~XUSBPS_dTDNLP_ADDR_MASK) |		\
+					((NLP) & XUSBPS_dTDNLP_ADDR_MASK))
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro gets the Transfer Length for the given Transfer Descriptor.
+ *
+ * @param	dTDPtr is a pointer to the dTD element.
+ *
+ * @return 	TransferLength field of the descriptor.
+ *
+ * @note	C-style signature:
+ *		u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDGetTransferLen(dTDPtr)				\
+		(u32) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) 	\
+				& XUSBPS_dTDTOKEN_LEN_MASK) >> 16)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Interrupt On Complete (IOC) bit for the given Transfer
+ * Descriptor.
+ *
+ * @param	dTDPtr is a pointer to the dTD element.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dTDSetIOC(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetIOC(dTDPtr)					\
+		XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, 		\
+			XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) |	\
+						XUSBPS_dTDTOKEN_IOC_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Terminate bit for the given Transfer Descriptor.
+ *
+ * @param	dTDPtr is a pointer to the dTD element.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dTDSetTerminate(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetTerminate(dTDPtr)				\
+		XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, 		\
+			XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) |	\
+						XUSBPS_dTDNLP_T_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro clears the Terminate bit for the given Transfer Descriptor.
+ *
+ * @param	dTDPtr is a pointer to the dTD element.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dTDClrTerminate(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDClrTerminate(dTDPtr)				\
+		XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, 		\
+			XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) &	\
+						~XUSBPS_dTDNLP_T_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro checks if the given descriptor is active.
+ *
+ * @param	dTDPtr is a pointer to the dTD element.
+ *
+ * @return
+ * 		- TRUE: The buffer is active.
+ * 		- FALSE: The buffer is not active.
+ *
+ * @note	C-style signature:
+ *		int XUsbPs_dTDIsActive(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDIsActive(dTDPtr)					\
+		((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) &		\
+				XUSBPS_dTDTOKEN_ACTIVE_MASK) ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Active bit for the given Transfer Descriptor.
+ *
+ * @param	dTDPtr is a pointer to the dTD element.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dTDSetActive(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetActive(dTDPtr)					\
+		XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, 		\
+			XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) |	\
+						XUSBPS_dTDTOKEN_ACTIVE_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro reads the content of a field in a Transfer Descriptor.
+ *
+ * @param	dTDPtr is a pointer to the dTD element.
+ * @param	Id is the field ID inside the dTD element to read.
+ *
+ * @note	C-style signature:
+ *		u32 XUsbPs_ReaddTD(u32 dTDPtr, u32 Id)
+ *
+ ******************************************************************************/
+#define XUsbPs_ReaddTD(dTDPtr, Id)	(*(u32 *)((u32)(dTDPtr) + (u32)(Id)))
+
+/*****************************************************************************/
+/**
+ *
+ * This macro writes a value to a field in a Transfer Descriptor.
+ *
+ * @param	dTDPtr is pointer to the dTD element.
+ * @param	Id is the field ID inside the dTD element to read.
+ * @param	Val is the value to write to the field.
+ *
+ * @note	C-style signature:
+ *		u32 XUsbPs_WritedTD(u32 dTDPtr, u32 Id, u32 Val)
+ *
+ ******************************************************************************/
+#define XUsbPs_WritedTD(dTDPtr, Id, Val)	\
+			(*(u32 *) ((u32)(dTDPtr) + (u32)(Id)) = (u32)(Val))
+
+
+/******************************************************************************/
+/**
+ * Endpoint Device Queue Head
+ *
+ * Device queue heads are arranged in an array in a continuous area of memory
+ * pointed to by the ENDPOINTLISTADDR pointer. The device controller will index
+ * into this array based upon the endpoint number received from the USB bus.
+ * All information necessary to respond to transactions for all primed
+ * transfers is contained in this list so the Device Controller can readily
+ * respond to incoming requests without having to traverse a linked list.
+ *
+ * The device Endpoint Queue Head (dQH) is where all transfers are managed. The
+ * dQH is a 48-byte data structure, but must be aligned on a 64-byte boundary.
+ * During priming of an endpoint, the dTD (device transfer descriptor) is
+ * copied into the overlay area of the dQH, which starts at the nextTD pointer
+ * DWord and continues through the end of the buffer pointers DWords. After a
+ * transfer is complete, the dTD status DWord is updated in the dTD pointed to
+ * by the currentTD pointer. While a packet is in progress, the overlay area of
+ * the dQH is used as a staging area for the dTD so that the Device Controller
+ * can access needed information with little minimal latency.
+ *
+ * @note
+ *    Software must ensure that no interface data structure reachable by the
+ *    Device Controller spans a 4K-page boundary.  The first element of the
+ *    Endpoint Queue Head List must be aligned on a 4K boundary.
+ */
+#define XUSBPS_dQHCFG			0x00 /**< dQH Configuration */
+#define XUSBPS_dQHCPTR			0x04 /**< dQH Current dTD Pointer */
+#define XUSBPS_dQHdTDNLP		0x08 /**< dTD Next Link Ptr in dQH
+					       overlay */
+#define XUSBPS_dQHdTDTOKEN		0x0C /**< dTD Token in dQH overlay */
+#define XUSBPS_dQHSUB0			0x28 /**< USB dQH Setup Buffer 0 */
+#define XUSBPS_dQHSUB1			0x2C /**< USB dQH Setup Buffer 1 */
+
+
+/** @name dQH Configuration (dQHCFG) bit positions.
+ *  @{
+ */
+#define XUSBPS_dQHCFG_IOS_MASK		0x00008000
+					/**< USB dQH Interrupt on Setup Bit */
+#define XUSBPS_dQHCFG_MPL_MASK		0x07FF0000
+					/**< USB dQH Maximum Packet Length
+					 * Field [10:0] */
+#define XUSBPS_dQHCFG_MPL_SHIFT    16
+#define XUSBPS_dQHCFG_ZLT_MASK		0x20000000
+					/**< USB dQH Zero Length Termination
+					 * Select Bit */
+#define XUSBPS_dQHCFG_MULT_MASK		0xC0000000
+					/* USB dQH Number of Transactions Field
+					 * [1:0] */
+#define XUSBPS_dQHCFG_MULT_SHIFT       30
+/* @} */
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Maximum Packet Length field of the give Queue Head.
+ *
+ * @param	dQHPtr is a pointer to the dQH element.
+ * @param	Len is the length to be set.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dQHSetMaxPacketLen(u32 dQHPtr, u32 Len)
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHSetMaxPacketLen(dQHPtr, Len)			\
+		XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, 		\
+			(XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) &	\
+				~XUSBPS_dQHCFG_MPL_MASK) | ((Len) << 16))
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Interrupt On Setup (IOS) bit for an endpoint.
+ *
+ * @param	dQHPtr is a pointer to the dQH element.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dQHSetIOS(u32 dQHPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHSetIOS(dQHPtr)					\
+		XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, 		\
+			XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) |	\
+						XUSBPS_dQHCFG_IOS_MASK)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro clears the Interrupt On Setup (IOS) bit for an endpoint.
+ *
+ * @param	dQHPtr is a pointer to the dQH element.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dQHClrIOS(u32 dQHPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHClrIOS(dQHPtr)					\
+		XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, 		\
+			XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) &	\
+						~XUSBPS_dQHCFG_IOS_MASK)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro enables Zero Length Termination for the endpoint.
+ *
+ * @param	dQHPtr is a pointer to the dQH element.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dQHEnableZLT(u32 dQHPtr)
+ *
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHEnableZLT(dQHPtr)					\
+		XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, 		\
+			XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) &	\
+						~XUSBPS_dQHCFG_ZLT_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro disables Zero Length Termination for the endpoint.
+ *
+ * @param	dQHPtr is a pointer to the dQH element.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dQHDisableZLT(u32 dQHPtr)
+ *
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHDisableZLT(dQHPtr)					\
+		XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, 		\
+			XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) |	\
+						XUSBPS_dQHCFG_ZLT_MASK)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro reads the content of a field in a Queue Head.
+ *
+ * @param	dQHPtr is a pointer to the dQH element.
+ * @param	Id is the Field ID inside the dQH element to read.
+ *
+ * @note	C-style signature:
+ *		u32 XUsbPs_ReaddQH(u32 dQHPtr, u32 Id)
+ *
+ ******************************************************************************/
+#define XUsbPs_ReaddQH(dQHPtr, Id)	(*(u32 *)((u32)(dQHPtr) + (u32) (Id)))
+
+/*****************************************************************************/
+/**
+ *
+ * This macro writes a value to a field in a Queue Head.
+ *
+ * @param	dQHPtr is a pointer to the dQH element.
+ * @param	Id is the Field ID inside the dQH element to read.
+ * @param	Val is the Value to write to the field.
+ *
+ * @note	C-style signature:
+ *		u32 XUsbPs_WritedQH(u32 dQHPtr, u32 Id, u32 Val)
+ *
+ ******************************************************************************/
+#define XUsbPs_WritedQH(dQHPtr, Id, Val)	\
+			(*(u32 *) ((u32)(dQHPtr) + (u32)(Id)) = (u32)(Val))
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XUSBPS_ENDPOINT_H */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps_g.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps_g.c
new file mode 100644
index 000000000..f49599da6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps_g.c
@@ -0,0 +1,31 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSM.
+* Version: 
+* DO NOT EDIT.
+*
+*  v (64-bit)
+SW Build (by ) on 
+Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xusbps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XUsbPs_Config XUsbPs_ConfigTable[] =
+{
+	{
+		XPAR_PS7_USB_0_DEVICE_ID,
+		XPAR_PS7_USB_0_BASEADDR
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps_hw.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps_hw.c
new file mode 100644
index 000000000..269d5a8ed
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps_hw.c
@@ -0,0 +1,128 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+ *
+ * @file xusbps_hw.c
+ *
+ * The implementation of the XUsbPs interface reset functionality
+ *
+ * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.05a kpc  10/10/10 first version
+ * 

+ *
+ *****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xusbps.h"
+#include "xparameters.h"
+
+
+/************************** Constant Definitions ****************************/
+#define XUSBPS_RESET_TIMEOUT 0xFFFFF
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+
+/************************** Function Prototypes *****************************/
+
+
+/*****************************************************************************/
+/**
+* This function perform the reset sequence to the given usbps interface by 
+* configuring the appropriate control bits in the usbps specifc registers.
+* the usbps reset sequence involves the below steps
+* 	Disbale the interrupts
+*	Clear the status registers
+*	Apply the reset command and wait for reset complete status
+*	Update the relevant control registers with reset values
+* @param   BaseAddress of the interface
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XUsbPs_ResetHw(u32 BaseAddress)
+{
+	u32 RegVal;
+	u32 Timeout = 0;
+	
+	/* Host and device mode */
+	/* Disable the interrupts */
+	XUsbPs_WriteReg(BaseAddress,XUSBPS_IER_OFFSET,0x0);
+	/* Clear the interuupt status */
+	RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_ISR_OFFSET);
+	XUsbPs_WriteReg(BaseAddress,XUSBPS_ISR_OFFSET,RegVal);
+
+	/* Perform the reset operation using USB CMD register */	
+	RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_CMD_OFFSET);
+	RegVal = RegVal | XUSBPS_CMD_RST_MASK;
+	XUsbPs_WriteReg(BaseAddress,XUSBPS_CMD_OFFSET,RegVal);
+	RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_CMD_OFFSET);
+	/* Wait till the reset operation returns success */
+	/*
+	* FIX ME: right now no indication to the caller or user about
+	* timeout overflow
+	*/
+	while ((RegVal & XUSBPS_CMD_RST_MASK) && (Timeout < XUSBPS_RESET_TIMEOUT))
+	{
+		RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_CMD_OFFSET);	
+		Timeout++;
+	}
+	/* Update periodic list base address register with reset value */		
+	XUsbPs_WriteReg(BaseAddress,XUSBPS_LISTBASE_OFFSET,0x0);	
+	/* Update async/endpoint list base address register with reset value */		
+	XUsbPs_WriteReg(BaseAddress,XUSBPS_ASYNCLISTADDR_OFFSET,0x0);		
+	
+}
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps_hw.h
new file mode 100644
index 000000000..5bab09165
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps_hw.h
@@ -0,0 +1,532 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xusbps_hw.h
+ *
+ * This header file contains identifiers and low-level driver functions (or
+ * macros) that can be used to access the device. High-level driver functions
+ * are defined in xusbps.h.
+ *
+ * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.00a wgr  10/10/10 First release
+ * 1.04a nm   10/23/12 Fixed CR# 679106.
+ * 1.05a kpc  07/03/13 Added XUsbPs_ResetHw function prototype
+ * 2.00a kpc  04/03/14 Fixed CR#777764. Corrected max endpoint vale and masks 
+ * 

+ *
+ ******************************************************************************/
+#ifndef XUSBPS_HW_H
+#define XUSBPS_HW_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+
+#define XUSBPS_REG_SPACING		4
+
+/** @name Timer 0 Register offsets
+ *
+ * @{
+ */
+#define XUSBPS_TIMER0_LD_OFFSET	0x00000080
+#define XUSBPS_TIMER0_CTL_OFFSET	0x00000084
+/* @} */
+
+/** @name Timer Control Register bit mask
+ *
+ * @{
+ */
+#define XUSBPS_TIMER_RUN_MASK		0x80000000
+#define XUSBPS_TIMER_STOP_MASK		0x80000000
+#define XUSBPS_TIMER_RESET_MASK	0x40000000
+#define XUSBPS_TIMER_REPEAT_MASK	0x01000000
+/* @} */
+
+/** @name Timer Control Register bit mask
+ *
+ * @{
+ */
+#define XUSBPS_TIMER_COUNTER_MASK	0x00FFFFFF
+/* @} */
+
+/** @name Device Hardware Parameters
+ *
+ * @{
+ */
+#define XUSBPS_HWDEVICE_OFFSET		0x0000000C
+
+#define XUSBPS_EP_NUM_MASK		0x3E
+#define XUSBPS_EP_NUM_SHIFT		1
+/* @} */
+
+/** @name Capability Regsiter offsets
+ */
+#define XUSBPS_HCSPARAMS_OFFSET		0x00000104
+
+/** @name Operational Register offsets.
+ * Register comments are tagged with "H:" and "D:" for Host and Device modes,
+ * respectively.
+ * Tags are only present for registers that have a different meaning DEVICE and
+ * HOST modes. Most registers are only valid for either DEVICE or HOST mode.
+ * Those registers don't have tags.
+ * @{
+ */
+#define XUSBPS_CMD_OFFSET		0x00000140 /**< Configuration */
+#define XUSBPS_ISR_OFFSET		0x00000144 /**< Interrupt Status */
+#define XUSBPS_IER_OFFSET		0x00000148 /**< Interrupt Enable */
+#define XUSBPS_FRAME_OFFSET		0x0000014C /**< USB Frame Index */
+#define XUSBPS_LISTBASE_OFFSET		0x00000154 /**< H: Periodic List Base Address */
+#define XUSBPS_DEVICEADDR_OFFSET	0x00000154 /**< D: Device Address */
+#define XUSBPS_ASYNCLISTADDR_OFFSET	0x00000158 /**< H: Async List Address */
+#define XUSBPS_EPLISTADDR_OFFSET	0x00000158 /**< D: Endpoint List Addr */
+#define XUSBPS_TTCTRL_OFFSET		0x0000015C /**< TT Control */
+#define XUSBPS_BURSTSIZE_OFFSET	0x00000160 /**< Burst Size */
+#define XUSBPS_TXFILL_OFFSET		0x00000164 /**< Tx Fill Tuning */
+#define XUSBPS_ULPIVIEW_OFFSET		0x00000170 /**< ULPI Viewport */
+#define XUSBPS_EPNAKISR_OFFSET		0x00000178 /**< Endpoint NAK IRQ Status */
+#define XUSBPS_EPNAKIER_OFFSET		0x0000017C /**< Endpoint NAK IRQ Enable */
+#define XUSBPS_PORTSCR1_OFFSET		0x00000184 /**< Port Control/Status 1 */
+
+/* NOTE: The Port Control / Status Register index is 1-based. */
+#define XUSBPS_PORTSCRn_OFFSET(n)	\
+		(XUSBPS_PORTSCR1_OFFSET + (((n)-1) * XUSBPS_REG_SPACING))
+
+
+#define XUSBPS_OTGCSR_OFFSET	0x000001A4 /**< OTG Status and Control */
+#define XUSBPS_MODE_OFFSET	0x000001A8 /**< USB Mode */
+#define XUSBPS_EPSTAT_OFFSET	0x000001AC /**< Endpoint Setup Status */
+#define XUSBPS_EPPRIME_OFFSET	0x000001B0 /**< Endpoint Prime */
+#define XUSBPS_EPFLUSH_OFFSET	0x000001B4 /**< Endpoint Flush */
+#define XUSBPS_EPRDY_OFFSET	0x000001B8 /**< Endpoint Ready */
+#define XUSBPS_EPCOMPL_OFFSET	0x000001BC /**< Endpoint Complete */
+#define XUSBPS_EPCR0_OFFSET	0x000001C0 /**< Endpoint Control 0 */
+#define XUSBPS_EPCR1_OFFSET	0x000001C4 /**< Endpoint Control 1 */
+#define XUSBPS_EPCR2_OFFSET	0x000001C8 /**< Endpoint Control 2 */
+#define XUSBPS_EPCR3_OFFSET	0x000001CC /**< Endpoint Control 3 */
+#define XUSBPS_EPCR4_OFFSET	0x000001D0 /**< Endpoint Control 4 */
+
+#define XUSBPS_MAX_ENDPOINTS	12	   /**< Number of supported Endpoints in
+					     *  this core. */
+#define XUSBPS_EP_OUT_MASK	0x00000FFF /**< OUR (RX) endpoint mask */
+#define XUSBPS_EP_IN_MASK	0x0FFF0000 /**< IN (TX) endpoint mask */
+#define XUSBPS_EP_ALL_MASK	0x0FFF0FFF /**< Mask used for endpoint control
+					     *  registers */
+#define XUSBPS_EPCRn_OFFSET(n)	\
+		(XUSBPS_EPCR0_OFFSET + ((n) * XUSBPS_REG_SPACING))
+
+#define  XUSBPS_EPFLUSH_RX_SHIFT   0
+#define  XUSBPS_EPFLUSH_TX_SHIFT  16
+
+/* @} */
+
+
+
+/** @name Endpoint Control Register (EPCR) bit positions.
+ *  @{
+ */
+
+/* Definitions for TX Endpoint bits */
+#define XUSBPS_EPCR_TXT_CONTROL_MASK	0x00000000 /**< Control Endpoint - TX */
+#define XUSBPS_EPCR_TXT_ISO_MASK	0x00040000 /**< Isochronous. Endpoint */
+#define XUSBPS_EPCR_TXT_BULK_MASK	0x00080000 /**< Bulk Endpoint - TX */
+#define XUSBPS_EPCR_TXT_INTR_MASK	0x000C0000 /**< Interrupt Endpoint */
+#define XUSBPS_EPCR_TXS_MASK		0x00010000 /**< Stall TX endpoint */
+#define XUSBPS_EPCR_TXE_MASK		0x00800000 /**< Transmit enable  - TX */
+#define XUSBPS_EPCR_TXR_MASK		0x00400000 /**< Data Toggle Reset Bit */
+
+
+/* Definitions for RX Endpoint bits */
+#define XUSBPS_EPCR_RXT_CONTROL_MASK	0x00000000 /**< Control Endpoint - RX */
+#define XUSBPS_EPCR_RXT_ISO_MASK	0x00000004 /**< Isochronous Endpoint */
+#define XUSBPS_EPCR_RXT_BULK_MASK	0x00000008 /**< Bulk Endpoint - RX */
+#define XUSBPS_EPCR_RXT_INTR_MASK	0x0000000C /**< Interrupt Endpoint */
+#define XUSBPS_EPCR_RXS_MASK		0x00000001 /**< Stall RX endpoint. */
+#define XUSBPS_EPCR_RXE_MASK		0x00000080 /**< Transmit enable. - RX */
+#define XUSBPS_EPCR_RXR_MASK		0x00000040 /**< Data Toggle Reset Bit */
+/* @} */
+
+
+/** @name USB Command Register (CR) bit positions.
+ *  @{
+ */
+#define XUSBPS_CMD_RS_MASK	0x00000001 /**< Run/Stop */
+#define XUSBPS_CMD_RST_MASK	0x00000002 /**< Controller RESET */
+#define XUSBPS_CMD_FS01_MASK	0x0000000C /**< Frame List Size bit 0,1 */
+#define XUSBPS_CMD_PSE_MASK	0x00000010 /**< Periodic Sched Enable */
+#define XUSBPS_CMD_ASE_MASK	0x00000020 /**< Async Sched Enable */
+#define XUSBPS_CMD_IAA_MASK	0x00000040 /**< IRQ Async Advance Doorbell */
+#define XUSBPS_CMD_ASP_MASK	0x00000300 /**< Async Sched Park Mode Cnt */
+#define XUSBPS_CMD_ASPE_MASK	0x00000800 /**< Async Sched Park Mode Enbl */
+#define XUSBPS_CMD_SUTW_MASK	0x00002000 /**< Setup TripWire */
+#define XUSBPS_CMD_ATDTW_MASK	0x00004000 /**< Add dTD TripWire */
+#define XUSBPS_CMD_FS2_MASK	0x00008000 /**< Frame List Size bit 2 */
+#define XUSBPS_CMD_ITC_MASK	0x00FF0000 /**< IRQ Threshold Control */
+/* @} */
+
+
+/**
+ * @name Interrupt Threshold
+ * These definitions are used by software to set the maximum rate at which the
+ * USB controller will generate interrupt requests. The interrupt interval is
+ * given in number of micro-frames.
+ *
+ * USB defines a full-speed 1 ms frame time indicated by a Start Of Frame (SOF)
+ * packet each and every 1ms. USB also defines a high-speed micro-frame with a
+ * 125us frame time. For each micro-frame a SOF (Start Of Frame) packet is
+ * generated. Data is sent in between the SOF packets. The interrupt threshold
+ * defines how many micro-frames the controller waits before issuing an
+ * interrupt after data has been received.
+ *
+ * For a threshold of 0 the controller will issue an interrupt immediately
+ * after the last byte of the data has been received. For a threshold n>0 the
+ * controller will wait for n micro-frames before issuing an interrupt.
+ *
+ * Therefore, a setting of 8 micro-frames (default) means that the controller
+ * will issue at most 1 interrupt per millisecond.
+ *
+ * @{
+ */
+#define XUSBPS_CMD_ITHRESHOLD_0	0x00 /**< Immediate interrupt. */
+#define XUSBPS_CMD_ITHRESHOLD_1	0x01 /**< 1 micro-frame */
+#define XUSBPS_CMD_ITHRESHOLD_2	0x02 /**< 2 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_4	0x04 /**< 4 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_8	0x08 /**< 8 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_16	0x10 /**< 16 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_32	0x20 /**< 32 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_64	0x40 /**< 64 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_MAX	XUSBPS_CMD_ITHRESHOLD_64
+#define XUSBPS_CMD_ITHRESHOLD_DEFAULT	XUSBPS_CMD_ITHRESHOLD_8
+/* @} */
+
+
+
+/** @name USB Interrupt Status Register (ISR) / Interrupt Enable Register (IER)
+ * bit positions.
+ *  @{
+ */
+#define XUSBPS_IXR_UI_MASK	0x00000001 /**< USB Transaction Complete */
+#define XUSBPS_IXR_UE_MASK	0x00000002 /**< Transaction Error */
+#define XUSBPS_IXR_PC_MASK	0x00000004 /**< Port Change Detect */
+#define XUSBPS_IXR_FRE_MASK	0x00000008 /**< Frame List Rollover */
+#define XUSBPS_IXR_AA_MASK	0x00000020 /**< Async Advance */
+#define XUSBPS_IXR_UR_MASK	0x00000040 /**< RESET Received */
+#define XUSBPS_IXR_SR_MASK	0x00000080 /**< Start of Frame */
+#define XUSBPS_IXR_SLE_MASK	0x00000100 /**< Device Controller Suspend */
+#define XUSBPS_IXR_ULPI_MASK	0x00000400 /**< ULPI IRQ */
+#define XUSBPS_IXR_HCH_MASK	0x00001000 /**< Host Controller Halted
+						* Read Only */
+#define XUSBPS_IXR_RCL_MASK	0x00002000 /**< USB Reclamation  Read Only */
+#define XUSBPS_IXR_PS_MASK	0x00004000 /**< Periodic Sched Status
+						* Read Only */
+#define XUSBPS_IXR_AS_MASK	0x00008000 /**< Async Sched Status Read only */
+#define XUSBPS_IXR_NAK_MASK	0x00010000 /**< NAK IRQ */
+#define XUSBPS_IXR_UA_MASK	0x00040000 /**< USB Host Async IRQ */
+#define XUSBPS_IXR_UP_MASK	0x00080000 /**< USB Host Periodic IRQ */
+#define XUSBPS_IXR_TI0_MASK	0x01000000 /**< Timer 0 Interrupt */
+#define XUSBPS_IXR_TI1_MASK	0x02000000 /**< Timer 1 Interrupt */
+
+#define XUSBPS_IXR_ALL			(XUSBPS_IXR_UI_MASK	| \
+					 XUSBPS_IXR_UE_MASK		| \
+					 XUSBPS_IXR_PC_MASK	| \
+					 XUSBPS_IXR_FRE_MASK	| \
+					 XUSBPS_IXR_AA_MASK	| \
+					 XUSBPS_IXR_UR_MASK		| \
+					 XUSBPS_IXR_SR_MASK		| \
+					 XUSBPS_IXR_SLE_MASK	| \
+					 XUSBPS_IXR_ULPI_MASK		| \
+					 XUSBPS_IXR_HCH_MASK	| \
+					 XUSBPS_IXR_RCL_MASK	| \
+					 XUSBPS_IXR_PS_MASK | \
+					 XUSBPS_IXR_AS_MASK		| \
+					 XUSBPS_IXR_NAK_MASK		| \
+					 XUSBPS_IXR_UA_MASK	| \
+					 XUSBPS_IXR_UP_MASK | \
+					 XUSBPS_IXR_TI0_MASK | \
+					 XUSBPS_IXR_TI1_MASK)
+					/**< Mask for ALL IRQ types */
+/* @} */
+
+
+/** @name USB Mode Register (MODE) bit positions.
+ *  @{
+ */
+#define XUSBPS_MODE_CM_MASK		0x00000003 /**< Controller Mode Select */
+#define XUSBPS_MODE_CM_IDLE_MASK	0x00000000
+#define XUSBPS_MODE_CM_DEVICE_MASK	0x00000002
+#define XUSBPS_MODE_CM_HOST_MASK	0x00000003
+#define XUSBPS_MODE_ES_MASK		0x00000004 /**< USB Endian Select */
+#define XUSBPS_MODE_SLOM_MASK		0x00000008 /**< USB Setup Lockout Mode Disable */
+#define XUSBPS_MODE_SDIS_MASK		0x00000010
+#define XUSBPS_MODE_VALID_MASK		0x0000001F
+
+/* @} */
+
+
+/** @name USB Device Address Register (DEVICEADDR) bit positions.
+ *  @{
+ */
+#define XUSBPS_DEVICEADDR_DEVICEAADV_MASK	0x01000000
+					/**< Device Addr Auto Advance */
+#define XUSBPS_DEVICEADDR_ADDR_MASK		0xFE000000
+					/**< Device Address */
+#define XUSBPS_DEVICEADDR_ADDR_SHIFT		25
+					/**< Address shift */
+#define XUSBPS_DEVICEADDR_MAX			127
+					/**< Biggest allowed address */
+/* @} */
+
+/** @name USB TT Control Register (TTCTRL) bit positions.
+ *  @{
+ */
+#define XUSBPS_TTCTRL_HUBADDR_MASK	0x7F000000 /**< TT Hub Address */
+/* @} */
+
+
+/** @name USB Burst Size Register (BURSTSIZE) bit posisions.
+ *  @{
+ */
+#define XUSBPS_BURSTSIZE_RX_MASK	0x000000FF /**< RX Burst Length */
+#define XUSBPS_BURSTSIZE_TX_MASK	0x0000FF00 /**< TX Burst Length */
+/* @} */
+
+
+/** @name USB Tx Fill Tuning Register (TXFILL) bit positions.
+ *  @{
+ */
+#define XUSBPS_TXFILL_OVERHEAD_MASK	0x000000FF
+					/**< Scheduler Overhead */
+#define XUSBPS_TXFILL_HEALTH_MASK	0x00001F00
+					/**< Scheduler Health Cntr */
+#define XUSBPS_TXFILL_BURST_MASK	0x003F0000
+					/**< FIFO Burst Threshold */
+/* @} */
+
+
+/** @name USB ULPI Viewport Register (ULPIVIEW) bit positions.
+ *  @{
+ */
+#define XUSBPS_ULPIVIEW_DATWR_MASK	0x000000FF /**< ULPI Data Write */
+#define XUSBPS_ULPIVIEW_DATRD_MASK	0x0000FF00 /**< ULPI Data Read */
+#define XUSBPS_ULPIVIEW_ADDR_MASK	0x00FF0000 /**< ULPI Data Address */
+#define XUSBPS_ULPIVIEW_PORT_MASK	0x07000000 /**< ULPI Port Number */
+#define XUSBPS_ULPIVIEW_SS_MASK	0x08000000 /**< ULPI Synchronous State */
+#define XUSBPS_ULPIVIEW_RW_MASK	0x20000000 /**< ULPI Read/Write Control */
+#define XUSBPS_ULPIVIEW_RUN_MASK	0x40000000 /**< ULPI Run */
+#define XUSBPS_ULPIVIEW_WU_MASK	0x80000000 /**< ULPI Wakeup */
+/* @} */
+
+
+/** @name Port Status Control Register bit positions.
+ *  @{
+ */
+#define XUSBPS_PORTSCR_CCS_MASK  0x00000001 /**< Current Connect Status */
+#define XUSBPS_PORTSCR_CSC_MASK  0x00000002 /**< Connect Status Change */
+#define XUSBPS_PORTSCR_PE_MASK	  0x00000004 /**< Port Enable/Disable */
+#define XUSBPS_PORTSCR_PEC_MASK  0x00000008 /**< Port Enable/Disable Change */
+#define XUSBPS_PORTSCR_OCA_MASK  0x00000010 /**< Over-current Active */
+#define XUSBPS_PORTSCR_OCC_MASK  0x00000020 /**< Over-current Change */
+#define XUSBPS_PORTSCR_FPR_MASK  0x00000040 /**< Force Port Resume */
+#define XUSBPS_PORTSCR_SUSP_MASK 0x00000080 /**< Suspend */
+#define XUSBPS_PORTSCR_PR_MASK	  0x00000100 /**< Port Reset */
+#define XUSBPS_PORTSCR_HSP_MASK  0x00000200 /**< High Speed Port */
+#define XUSBPS_PORTSCR_LS_MASK	  0x00000C00 /**< Line Status */
+#define XUSBPS_PORTSCR_PP_MASK	  0x00001000 /**< Port Power */
+#define XUSBPS_PORTSCR_PO_MASK	  0x00002000 /**< Port Owner */
+#define XUSBPS_PORTSCR_PIC_MASK  0x0000C000 /**< Port Indicator Control */
+#define XUSBPS_PORTSCR_PTC_MASK  0x000F0000 /**< Port Test Control */
+#define XUSBPS_PORTSCR_WKCN_MASK 0x00100000 /**< Wake on Connect Enable */
+#define XUSBPS_PORTSCR_WKDS_MASK 0x00200000 /**< Wake on Disconnect Enable */
+#define XUSBPS_PORTSCR_WKOC_MASK 0x00400000 /**< Wake on Over-current Enable */
+#define XUSBPS_PORTSCR_PHCD_MASK 0x00800000 /**< PHY Low Power Suspend -
+						* Clock Disable */
+#define XUSBPS_PORTSCR_PFSC_MASK 0x01000000 /**< Port Force Full Speed
+						* Connect */
+#define XUSBPS_PORTSCR_PSPD_MASK 0x0C000000 /**< Port Speed */
+/* @} */
+
+
+/** @name On-The-Go Status Control Register (OTGCSR) bit positions.
+ *  @{
+ */
+#define XUSBPS_OTGSC_VD_MASK	 0x00000001 /**< VBus Discharge Bit */
+#define XUSBPS_OTGSC_VC_MASK	 0x00000002 /**< VBus Charge Bit */
+#define XUSBPS_OTGSC_HAAR_MASK	 0x00000004 /**< HW Assist Auto Reset
+				 		       *  Enable Bit */
+#define XUSBPS_OTGSC_OT_MASK	 0x00000008 /**< OTG Termination Bit */
+#define XUSBPS_OTGSC_DP_MASK	 0x00000010 /**< Data Pulsing Pull-up
+				 		       *  Enable Bit */
+#define XUSBPS_OTGSC_IDPU_MASK	 0x00000020 /**< ID Pull-up Enable Bit */
+#define XUSBPS_OTGSC_HADP_MASK	 0x00000040 /**< HW Assist Data Pulse
+							* Enable Bit */
+#define XUSBPS_OTGSC_HABA_MASK	 0x00000080 /**< USB Hardware Assist
+						       *  B Disconnect to A
+						       *  Connect Enable Bit */
+#define XUSBPS_OTGSC_ID_MASK	 0x00000100 /**< ID Status Flag */
+#define XUSBPS_OTGSC_AVV_MASK	 0x00000200 /**< USB A VBus Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_ASV_MASK	 0x00000400 /**< USB A Session Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_BSV_MASK	 0x00000800 /**< USB B Session Valid Status Flag */
+#define XUSBPS_OTGSC_BSE_MASK	 0x00001000 /**< USB B Session End Status Flag */
+#define XUSBPS_OTGSC_1MST_MASK	 0x00002000 /**< USB 1 Millisecond Timer Status Flag */
+#define XUSBPS_OTGSC_DPS_MASK	 0x00004000 /**< Data Pulse Status Flag */
+#define XUSBPS_OTGSC_IDIS_MASK	 0x00010000 /**< USB ID Interrupt Status Flag */
+#define XUSBPS_OTGSC_AVVIS_MASK 0x00020000 /**< USB A VBus Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_ASVIS_MASK 0x00040000 /**< USB A Session Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_BSVIS_MASK 0x00080000 /**< USB B Session Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_BSEIS_MASK 0x00100000 /**< USB B Session End Interrupt Status Flag */
+#define XUSBPS_OTGSC_1MSS_MASK	 0x00200000 /**< 1 Millisecond Timer Interrupt Status Flag */
+#define XUSBPS_OTGSC_DPIS_MASK	 0x00400000 /**< Data Pulse Interrupt Status Flag */
+#define XUSBPS_OTGSC_IDIE_MASK	 0x01000000 /**< ID Interrupt Enable Bit */
+#define XUSBPS_OTGSC_AVVIE_MASK 0x02000000 /**< USB A VBus Valid Interrupt Enable Bit */
+#define XUSBPS_OTGSC_ASVIE_MASK 0x04000000 /**< USB A Session Valid Interrupt Enable Bit */
+#define XUSBPS_OTGSC_BSVIE_MASK 0x08000000 /**< USB B Session Valid Interrupt Enable Bit */
+#define XUSBPS_OTGSC_BSEE_MASK	 0x10000000 /**< USB B Session End Interrupt Enable Bit */
+#define XUSBPS_OTGSC_1MSE_MASK	 0x20000000 /**< 1 Millisecond Timer
+						* Interrupt Enable Bit */
+#define XUSBPS_OTGSC_DPIE_MASK	 0x40000000 /**< Data Pulse Interrupt
+							* Enable Bit */
+
+#define XUSBPS_OTG_ISB_ALL	(XUSBPS_OTGSC_IDIS_MASK |\
+				XUSBPS_OTGSC_AVVIS_MASK | \
+				XUSBPS_OTGSC_ASVIS_MASK | \
+				XUSBPS_OTGSC_BSVIS_MASK | \
+				XUSBPS_OTGSC_BSEIS_MASK | \
+				XUSBPS_OTGSC_1MSS_MASK | \
+				XUSBPS_OTGSC_DPIS_MASK)
+				/** Mask for All IRQ status masks */
+
+#define XUSBPS_OTG_IEB_ALL	(XUSBPS_OTGSC_IDIE_MASK |\
+				XUSBPS_OTGSC_AVVIE_MASK | \
+				XUSBPS_OTGSC_ASVIE_MASK | \
+				XUSBPS_OTGSC_BSVIE_MASK | \
+				XUSBPS_OTGSC_BSEE_IEB_MASK | \
+				XUSBPS_OTGSC_1MSE_MASK | \
+				XUSBPS_OTGSC_DPIE_MASK)
+				/** Mask for All IRQ Enable masks */
+/* @} */
+
+
+/**< Alignment of the Device Queue Head List BASE. */
+#define XUSBPS_dQH_BASE_ALIGN		2048
+
+/**< Alignment of a Device Queue Head structure. */
+#define XUSBPS_dQH_ALIGN		64
+
+/**< Alignment of a Device Transfer Descriptor structure. */
+#define XUSBPS_dTD_ALIGN		32
+
+/**< Size of one RX buffer for a OUT Transfer Descriptor. */
+#define XUSBPS_dTD_BUF_SIZE		4096
+
+/**< Maximum size of one RX/TX buffer. */
+#define XUSBPS_dTD_BUF_MAX_SIZE	16*1024
+
+/**< Alignment requirement for Transfer Descriptor buffers. */
+#define XUSBPS_dTD_BUF_ALIGN		4096
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param	BaseAddress is the base address for the USB registers.
+* @param	RegOffset is the register offset to be read.
+*
+* @return	The 32-bit value of the register.
+*
+* @note		C-style signature:
+*		u32 XUsbPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XUsbPs_ReadReg(BaseAddress, RegOffset) \
+				Xil_In32(BaseAddress + (RegOffset))
+
+
+/****************************************************************************/
+/**
+*
+* This macro writes the given register.
+*
+* @param	BaseAddress is the the base address for the USB registers.
+* @param	RegOffset is the register offset to be written.
+* @param	Data is the the 32-bit value to write to the register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XUsbPs_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+ *****************************************************************************/
+#define XUsbPs_WriteReg(BaseAddress, RegOffset, Data) \
+				Xil_Out32(BaseAddress + (RegOffset), (Data))
+
+
+/************************** Function Prototypes ******************************/
+/*
+ * Perform reset operation to the USB PS interface
+ */
+void XUsbPs_ResetHw(u32 BaseAddress);
+/************************** Variable Definitions ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XUSBPS_L_H */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps_intr.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps_intr.c
new file mode 100644
index 000000000..a0e927de0
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps_intr.c
@@ -0,0 +1,476 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/******************************************************************************/
+/**
+ * @file xusbps_intr.c
+ *
+ * This file contains the functions that are related to interrupt processing
+ * for the EPB USB driver.
+ *
+ * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- ----------------------------------------------------------
+ * 1.00a jz  10/10/10 First release
+ * 1.03a nm  09/21/12 Fixed CR#678977. Added proper sequence for setup packet
+ *                    handling.
+ * 

+ ******************************************************************************/
+
+/***************************** Include Files **********************************/
+
+#include "xusbps.h"
+#include "xusbps_endpoint.h"
+
+/************************** Constant Definitions ******************************/
+
+/**************************** Type Definitions ********************************/
+
+/***************** Macros (Inline Functions) Definitions **********************/
+
+/************************** Variable Definitions ******************************/
+
+/************************** Function Prototypes *******************************/
+
+static void XUsbPs_IntrHandleTX(XUsbPs *InstancePtr, u32 EpCompl);
+static void XUsbPs_IntrHandleRX(XUsbPs *InstancePtr, u32 EpCompl);
+static void XUsbPs_IntrHandleReset(XUsbPs *InstancePtr, u32 IrqSts);
+static void XUsbPs_IntrHandleEp0Setup(XUsbPs *InstancePtr);
+
+/*****************************************************************************/
+/**
+* This function is the first-level interrupt handler for the USB core. All USB
+* interrupts will be handled here. Depending on the type of the interrupt,
+* second level interrupt handler may be called. Second level interrupt
+* handlers will be registered by the user using the:
+*    XUsbPs_IntrSetHandler()
+* and/or
+*    XUsbPs_EpSetHandler()
+* functions.
+*
+*
+* @param	HandlerRef is a Reference passed to the interrupt register
+*		function. In our case this will be a pointer to the XUsbPs
+*		instance.
+*
+* @return	None
+*
+* @note		None
+*
+******************************************************************************/
+void XUsbPs_IntrHandler(void *HandlerRef)
+{
+	XUsbPs	*InstancePtr;
+
+	u32	IrqSts;
+
+	Xil_AssertVoid(HandlerRef != NULL);
+
+	InstancePtr = (XUsbPs *) HandlerRef;
+
+	/* Handle controller (non-endpoint) related interrupts. */
+	IrqSts = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_ISR_OFFSET);
+
+	/* Clear the interrupt status register. */
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_ISR_OFFSET, IrqSts);
+
+	/* Nak interrupt, used to respond to host's IN request */
+	if(IrqSts & XUSBPS_IXR_NAK_MASK) {
+		/* Ack the hardware	 */
+		XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+					XUSBPS_EPNAKISR_OFFSET,
+			XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XUSBPS_EPNAKISR_OFFSET));
+	}
+
+
+	/***************************************************************
+	 *
+	 * Handle general interrupts. Endpoint interrupts will be handler
+	 * later.
+	 *
+	 */
+
+	/* RESET interrupt.*/
+	if (IrqSts & XUSBPS_IXR_UR_MASK) {
+		XUsbPs_IntrHandleReset(InstancePtr, IrqSts);
+		return;
+	}
+
+	/* Check if we have a user handler that needs to be called. Note that
+	 * this is the handler for general interrupts. Endpoint interrupts will
+	 * be handled below.
+	 */
+	if ((IrqSts & InstancePtr->HandlerMask) && InstancePtr->HandlerFunc) {
+		(InstancePtr->HandlerFunc)(InstancePtr->HandlerRef, IrqSts);
+	}
+
+
+	/***************************************************************
+	 *
+	 * Handle Endpoint interrupts.
+	 *
+	 */
+	if (IrqSts & XUSBPS_IXR_UI_MASK) {
+		u32	EpStat;
+		u32	EpCompl;
+
+		/* ENDPOINT 0 SETUP PACKET HANDLING
+		 *
+		 * Check if we got a setup packet on endpoint 0. Currently we
+		 * only check for setup packets on endpoint 0 as we would not
+		 * expect setup packets on any other endpoint (even though it
+		 * is possible to send setup packets on other endpoints).
+		 */
+		EpStat = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XUSBPS_EPSTAT_OFFSET);
+		if (EpStat & 0x0001) {
+			/* Handle the setup packet */
+			XUsbPs_IntrHandleEp0Setup(InstancePtr);
+
+			/* Re-Prime the endpoint.
+			 * Endpoint is de-primed if a setup packet comes in.
+	 		 */
+			XUsbPs_EpPrime(InstancePtr, 0, XUSBPS_EP_DIRECTION_OUT);
+		}
+
+		/* Check for RX and TX complete interrupts. */
+		EpCompl = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XUSBPS_EPCOMPL_OFFSET);
+
+
+		/* ACK the complete interrupts. */
+		XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+					XUSBPS_EPCOMPL_OFFSET, EpCompl);
+
+		/* Check OUT (RX) endpoints. */
+		if (EpCompl & XUSBPS_EP_OUT_MASK) {
+			XUsbPs_IntrHandleRX(InstancePtr, EpCompl);
+		}
+
+		/* Check IN (TX) endpoints. */
+		if (EpCompl & XUSBPS_EP_IN_MASK) {
+			XUsbPs_IntrHandleTX(InstancePtr, EpCompl);
+		}
+	}
+}
+
+
+/*****************************************************************************/
+/**
+* This function registers the user callback handler for controller
+* (non-endpoint) interrupts.
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+* @param	CallBackFunc is the Callback function to register.
+*		CallBackFunc may be NULL to clear the entry.
+* @param	CallBackRef is the user data reference passed to the
+*		callback function. CallBackRef may be NULL.
+* @param	Mask is the User interrupt mask. Defines which interrupts
+*		will cause the callback to be called.
+*
+* @return
+*		- XST_SUCCESS: Callback registered successfully.
+*		- XST_FAILURE: Callback could not be registered.
+*
+* @note		None.
+*
+******************************************************************************/
+int XUsbPs_IntrSetHandler(XUsbPs *InstancePtr,
+			   XUsbPs_IntrHandlerFunc CallBackFunc,
+			   void *CallBackRef, u32 Mask)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	InstancePtr->HandlerFunc	= CallBackFunc;
+	InstancePtr->HandlerRef		= CallBackRef;
+	InstancePtr->HandlerMask	= Mask;
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+* This function handles TX buffer interrupts. It is called by the interrupt
+* when a transmit complete interrupt occurs. It returns buffers of completed
+* descriptors to the caller.
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+* @param	EpCompl is the Bit mask of endpoints that caused a transmit
+*		complete interrupt.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void XUsbPs_IntrHandleTX(XUsbPs *InstancePtr, u32 EpCompl)
+{
+	int Index;
+	u32 Mask;
+	int NumEp;
+
+	/* Check all endpoints for TX complete bits.
+	 */
+	Mask	= 0x00010000;
+	NumEp	= InstancePtr->DeviceConfig.NumEndpoints;
+
+	/* Check for every endpoint if its TX complete bit is
+	 * set.
+	 */
+	for (Index = 0; Index < NumEp; Index++, Mask <<= 1) {
+		XUsbPs_EpIn	*Ep;
+
+		if (!(EpCompl & Mask)) {
+			continue;
+		}
+		/* The TX complete bit for this endpoint is
+		 * set. Walk the list of descriptors to see
+		 * which ones are completed.
+		 */
+		Ep = &InstancePtr->DeviceConfig.Ep[Index].In;
+		while (Ep->dTDTail != Ep->dTDHead) {
+
+			XUsbPs_dTDInvalidateCache(Ep->dTDTail);
+
+			/* If the descriptor is not active then the buffer has
+			 * not been sent yet.
+			 */
+			if (XUsbPs_dTDIsActive(Ep->dTDTail)) {
+				break;
+			}
+
+			if (Ep->HandlerFunc) {
+				void *BufPtr;
+
+				BufPtr = (void *) XUsbPs_ReaddTD(Ep->dTDTail,
+							XUSBPS_dTDUSERDATA);
+
+				Ep->HandlerFunc(Ep->HandlerRef, Index,
+						XUSBPS_EP_EVENT_DATA_TX,
+								BufPtr);
+			}
+
+			Ep->dTDTail = XUsbPs_dTDGetNLP(Ep->dTDTail);
+		}
+	}
+}
+
+
+/*****************************************************************************/
+/**
+ * This function handles RX buffer interrupts. It is called by the interrupt
+ * when a receive complete interrupt occurs. It notifies the callback functions
+ * that have been registered with the individual endpoints that data has been
+ * received.
+ *
+ * @param	InstancePtr
+ * 		Pointer to the XUsbPs instance of the controller.
+ *
+ * @param	EpCompl
+ * 		Bit mask of endpoints that caused a receive complete interrupt.
+ * @return
+ *		none
+ *
+ ******************************************************************************/
+static void XUsbPs_IntrHandleRX(XUsbPs *InstancePtr, u32 EpCompl)
+{
+	XUsbPs_EpOut	*Ep;
+	int		Index;
+	u32		Mask;
+	int		NumEp;
+
+	/* Check all endpoints for RX complete bits. */
+	Mask	= 0x00000001;
+	NumEp	= InstancePtr->DeviceConfig.NumEndpoints;
+
+
+	/* Check for every endpoint if its RX complete bit is set.*/
+	for (Index = 0; Index < NumEp; Index++, Mask <<= 1) {
+		int numP = 0;
+
+		if (!(EpCompl & Mask)) {
+			continue;
+		}
+		Ep = &InstancePtr->DeviceConfig.Ep[Index].Out;
+
+		XUsbPs_dTDInvalidateCache(Ep->dTDCurr);
+
+		/* Handle all finished dTDs */
+		while (!XUsbPs_dTDIsActive(Ep->dTDCurr)) {
+			numP += 1;
+			if (Ep->HandlerFunc) {
+				Ep->HandlerFunc(Ep->HandlerRef, Index,
+						XUSBPS_EP_EVENT_DATA_RX, NULL);
+			}
+
+			Ep->dTDCurr = XUsbPs_dTDGetNLP(Ep->dTDCurr);
+			XUsbPs_dTDInvalidateCache(Ep->dTDCurr);
+		}
+		/* Re-Prime the endpoint.*/
+		XUsbPs_EpPrime(InstancePtr, Index, XUSBPS_EP_DIRECTION_OUT);
+	}
+}
+
+
+/*****************************************************************************/
+/**
+* This function handles a RESET interrupt. It will notify the interrupt
+* handler callback of the RESET condition.
+*
+* @param	InstancePtr is pointer to the XUsbPs instance of the controller
+* @param	IrqSts is the Interrupt status register content.
+*		To be passed on to the user.
+*
+* @return	None
+*
+* @Note		None.
+*
+******************************************************************************/
+static void XUsbPs_IntrHandleReset(XUsbPs *InstancePtr, u32 IrqSts)
+{
+	int Timeout;
+
+	/* Clear all setup token semaphores by reading the
+	 * XUSBPS_EPSTAT_OFFSET register and writing its value back to
+	 * itself.
+	 */
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPSTAT_OFFSET,
+		XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_EPSTAT_OFFSET));
+
+	/* Clear all the endpoint complete status bits by reading the
+	 * XUSBPS_EPCOMPL_OFFSET register and writings its value back
+	 * to itself.
+	 */
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XUSBPS_EPCOMPL_OFFSET,
+		XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_EPCOMPL_OFFSET));
+
+	/* Cancel all endpoint prime status by waiting until all bits
+	 * in XUSBPS_EPPRIME_OFFSET are 0 and then writing 0xFFFFFFFF
+	 * to XUSBPS_EPFLUSH_OFFSET.
+	 *
+	 * Avoid hanging here by using a Timeout counter...
+	 */
+	Timeout = XUSBPS_TIMEOUT_COUNTER;
+	while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XUSBPS_EPPRIME_OFFSET) &
+					XUSBPS_EP_ALL_MASK) && --Timeout) {
+		/* NOP */
+	}
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_EPFLUSH_OFFSET, 0xFFFFFFFF);
+
+	/* Make sure that the reset bit in XUSBPS_PORTSCR1_OFFSET is
+	 * still set at this point. If the code gets to this point and
+	 * the reset bit has already been cleared we are in trouble and
+	 * hardware reset is necessary.
+	 */
+	if (!(XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_PORTSCR1_OFFSET) &
+				XUSBPS_PORTSCR_PR_MASK)) {
+		/* Send a notification to the user that a hardware
+		 * RESET is required. At this point we can only hope
+		 * that the user registered an interrupt handler and
+		 * will issue a hardware RESET.
+		 */
+		if (InstancePtr->HandlerFunc) {
+			(InstancePtr->HandlerFunc)(InstancePtr->HandlerRef,
+						   IrqSts);
+		}
+		else {
+			for (;;);
+		}
+
+		/* If we get here there is nothing more to do. The user
+		 * should have reset the core.
+		 */
+		return;
+	}
+
+	/* Check if we have a user handler that needs to be called.
+	 */
+	if (InstancePtr->HandlerFunc) {
+		(InstancePtr->HandlerFunc)(InstancePtr->HandlerRef, IrqSts);
+	}
+
+	/* We are done. After RESET we don't proceed in the interrupt
+	 * handler.
+	 */
+}
+
+
+/*****************************************************************************/
+/**
+* This function handles a Setup Packet interrupt. It will notify the interrupt
+* handler callback of the RESET condition.
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+*
+* @return	None
+*
+* @Note 	None
+*
+******************************************************************************/
+static void XUsbPs_IntrHandleEp0Setup(XUsbPs *InstancePtr)
+{
+
+	XUsbPs_EpOut	*Ep;
+
+	/* Notifiy the user. */
+	Ep = &InstancePtr->DeviceConfig.Ep[0].Out;
+
+	if (Ep->HandlerFunc) {
+		Ep->HandlerFunc(Ep->HandlerRef, 0,
+				XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED, NULL);
+	}
+}
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps_sinit.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps_sinit.c
new file mode 100644
index 000000000..661756652
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_1/src/xusbps_sinit.c
@@ -0,0 +1,105 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-14 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+ *
+ * @file xusbps_sinit.c
+ *
+ * The implementation of the XUsbPs driver's static initialzation
+ * functionality.
+ *
+ * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.00a wgr  10/10/10 First release
+ * 

+ *
+ *****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xusbps.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+extern XUsbPs_Config XUsbPs_ConfigTable[];
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* Looks up the controller configuration based on the unique controller ID. A
+* table contains the configuration info for each controller in the system.
+*
+* @param	DeviceID is the ID of the controller to look up the
+*		configuration for.
+*
+* @return
+*		A pointer to the configuration found or NULL if the specified
+*		controller ID was not found.
+*
+******************************************************************************/
+XUsbPs_Config *XUsbPs_LookupConfig(u16 DeviceID)
+{
+	XUsbPs_Config *CfgPtr = NULL;
+
+	int Index;
+
+	for (Index = 0; Index < XPAR_XUSBPS_NUM_INSTANCES; Index++) {
+		if (XUsbPs_ConfigTable[Index].DeviceID == DeviceID) {
+			CfgPtr = &XUsbPs_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return CfgPtr;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_0/src/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_0/src/Makefile
new file mode 100644
index 000000000..96aeb0c5f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_0/src/Makefile
@@ -0,0 +1,41 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xadcps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling xadcps"
+
+xadcps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xadcps_includes
+
+xadcps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_0/src/xadcps.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_0/src/xadcps.c
new file mode 100644
index 000000000..662b4c1ca
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_0/src/xadcps.c
@@ -0,0 +1,1835 @@
+/******************************************************************************
+*
+* (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps.c
+*
+* This file contains the driver API functions that can be used to access
+* the XADC device.
+*
+* Refer to the xadcps.h header file for more information about this driver.
+*
+* @note 	None.
+*
+* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a ssb    12/22/11 First release based on the XPS/AXI xadc driver
+* 1.01a bss    02/18/13	Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
+*			XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
+*			to fix CR #693371
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xadcps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+
+void XAdcPs_WriteInternalReg(XAdcPs *InstancePtr, u32 RegOffset, u32 Data);
+u32 XAdcPs_ReadInternalReg(XAdcPs *InstancePtr, u32 RegOffset);
+
+
+/************************** Variable Definitions ****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* This function initializes a specific XAdcPs device/instance. This function
+* must be called prior to using the XADC device.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	ConfigPtr points to the XAdcPs device configuration structure.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. If the address translation is not used then the
+*		physical address is passed.
+*		Unexpected errors may occur if the address mapping is changed
+*		after this function is invoked.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*
+* @note		The user needs to first call the XAdcPs_LookupConfig() API
+*		which returns the Configuration structure pointer which is
+*		passed as a parameter to the XAdcPs_CfgInitialize() API.
+*
+******************************************************************************/
+int XAdcPs_CfgInitialize(XAdcPs *InstancePtr, XAdcPs_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+
+	u32 RegValue;
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+
+	/*
+	 * Set the values read from the device config and the base address.
+	 */
+	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+
+	/* Write Unlock value to Device Config Unlock register */
+	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+				XADCPS_UNLK_OFFSET, XADCPS_UNLK_VALUE);
+
+	/* Enable the PS access of xadc and set FIFO thresholds */
+
+	RegValue = XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
+			XADCPS_CFG_OFFSET);
+
+	RegValue = RegValue | XADCPS_CFG_ENABLE_MASK |
+			XADCPS_CFG_CFIFOTH_MASK | XADCPS_CFG_DFIFOTH_MASK;
+
+	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+					XADCPS_CFG_OFFSET, RegValue);
+
+	/* Release xadc from reset */
+
+	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+						XADCPS_MCTL_OFFSET, 0x00);
+
+	/*
+	 * Indicate the instance is now ready to use and
+	 * initialized without error.
+	 */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	return XST_SUCCESS;
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions sets the contents of the Config Register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Data is the 32 bit data to be written to the Register.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_SetConfigRegister(XAdcPs *InstancePtr, u32 Data)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+				XADCPS_CFG_OFFSET, Data);
+
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions reads the contents of the Config Register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	A 32-bit value representing the contents of the Config Register.
+*		Use the XADCPS_SR_*_MASK constants defined in xadcps_hw.h to
+*		interpret the returned value.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetConfigRegister(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Config Register and return the value.
+	 */
+	return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
+				XADCPS_CFG_OFFSET);
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions reads the contents of the Miscellaneous Status Register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	A 32-bit value representing the contents of the Miscellaneous
+*		Status Register. Use the XADCPS_MSTS_*_MASK constants defined
+*		in xadcps_hw.h to interpret the returned value.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetMiscStatus(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Miscellaneous Status Register and return the value.
+	 */
+	return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
+				XADCPS_MSTS_OFFSET);
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions sets the contents of the Miscellaneous Control register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Data is the 32 bit data to be written to the Register.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_SetMiscCtrlRegister(XAdcPs *InstancePtr, u32 Data)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Write to the Miscellaneous control register Register.
+	 */
+	 XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+	 			XADCPS_MCTL_OFFSET, Data);
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions reads the contents of the Miscellaneous control register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	A 32-bit value representing the contents of the Config Register.
+*		Use the XADCPS_SR_*_MASK constants defined in xadcps_hw.h to
+*		interpret the returned value.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetMiscCtrlRegister(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Miscellaneous control register and return the value.
+	 */
+	return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
+				XADCPS_MCTL_OFFSET);
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This function resets the XADC Hard Macro in the device.
+*
+* @param	InstancePtr is a pointer to the Xxadc instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XAdcPs_Reset(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Generate the reset by Control
+	 * register and release from reset
+	 */
+	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+	 			XADCPS_MCTL_OFFSET, 0x10);
+	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+	 			XADCPS_MCTL_OFFSET, 0x00);
+}
+
+
+/****************************************************************************/
+/**
+*
+* Get the ADC converted data for the specified channel.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Channel is the channel number. Use the XADCPS_CH_* defined in
+*		the file xadcps.h.
+*		The valid channels are
+*		- 0 to 6
+*		- 13 to 31
+*
+* @return	A 16-bit value representing the ADC converted data for the
+*		specified channel. The XADC Monitor/ADC device guarantees
+* 		a 10 bit resolution for the ADC converted data and data is the
+*		10 MSB bits of the 16 data read from the device.
+*
+* @note		The channels 7,8,9 are used for calibration of the device and
+*		hence there is no associated data with this channel.
+*
+*****************************************************************************/
+u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel)
+{
+
+	u32 RegData;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((Channel <= XADCPS_CH_VBRAM) ||
+			 ((Channel >= XADCPS_CH_VCCPINT) &&
+			 (Channel <= XADCPS_CH_AUX_MAX)));
+
+	RegData = XAdcPs_ReadInternalReg(InstancePtr,
+						(XADCPS_TEMP_OFFSET +
+						Channel));
+	return (u16) RegData;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the calibration coefficient data for the specified
+* parameter.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	CoeffType specifies the calibration coefficient
+*		to be read. Use XADCPS_CALIB_* constants defined in xadcps.h to
+*		specify the calibration coefficient to be read.
+*
+* @return	A 16-bit value representing the calibration coefficient.
+*		The XADC device guarantees a 10 bit resolution for
+*		the ADC converted data and data is the 10 MSB bits of the 16
+*		data read from the device.
+*
+* @note		None.
+*
+*****************************************************************************/
+u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType)
+{
+	u32 RegData;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(CoeffType <= XADCPS_CALIB_GAIN_ERROR_COEFF);
+
+	/*
+	 * Read the selected calibration coefficient.
+	 */
+	RegData = XAdcPs_ReadInternalReg(InstancePtr,
+					(XADCPS_ADC_A_SUPPLY_CALIB_OFFSET +
+					CoeffType));
+	return (u16) RegData;
+}
+
+/****************************************************************************/
+/**
+*
+* This function reads the Minimum/Maximum measurement for one of the
+* specified parameters. Use XADCPS_MAX_* and XADCPS_MIN_* constants defined in
+* xadcps.h to specify the parameters (Temperature, VccInt, VccAux, VBram,
+* VccPInt, VccPAux and VccPDro).
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	MeasurementType specifies the parameter for which the
+*		Minimum/Maximum measurement has to be read.
+*		Use XADCPS_MAX_* and XADCPS_MIN_* constants defined in xadcps.h to
+*		specify the data to be read.
+*
+* @return	A 16-bit value representing the maximum/minimum measurement for
+*		specified parameter.
+*		The XADC device guarantees a 10 bit resolution for
+*		the ADC converted data and data is the 10 MSB bits of the 16
+*		data read from the device.
+*
+* @note		None.
+*
+*****************************************************************************/
+u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType)
+{
+	u32 RegData;
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((MeasurementType <= XADCPS_MAX_VCCPDRO) ||
+			((MeasurementType >= XADCPS_MIN_VCCPINT) &&
+			(MeasurementType <= XADCPS_MIN_VCCPDRO)))
+
+	/*
+	 * Read and return the specified Minimum/Maximum measurement.
+	 */
+	RegData = XAdcPs_ReadInternalReg(InstancePtr,
+					(XADCPS_MAX_TEMP_OFFSET +
+					MeasurementType));
+	return (u16) RegData;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the number of samples of averaging that is to be done for
+* all the channels in both the single channel mode and sequence mode of
+* operations.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Average is the number of samples of averaging programmed to the
+*		Configuration Register 0. Use the XADCPS_AVG_* definitions defined
+*		in xadcps.h file :
+*		- XADCPS_AVG_0_SAMPLES for no averaging
+*		- XADCPS_AVG_16_SAMPLES for 16 samples of averaging
+*		- XADCPS_AVG_64_SAMPLES for 64 samples of averaging
+*		- XADCPS_AVG_256_SAMPLES for 256 samples of averaging
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average)
+{
+	u32 RegData;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Average <= XADCPS_AVG_256_SAMPLES);
+
+	/*
+	 * Write the averaging value into the Configuration Register 0.
+	 */
+	RegData = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR0_OFFSET) &
+					(~XADCPS_CFR0_AVG_VALID_MASK);
+
+	RegData |=  (((u32) Average << XADCPS_CFR0_AVG_SHIFT));
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
+					RegData);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the number of samples of averaging configured for all
+* the channels in the Configuration Register 0.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	The averaging read from the Configuration Register 0 is
+*		returned. Use the XADCPS_AVG_* bit definitions defined in
+*		xadcps.h file to interpret the returned value :
+*		- XADCPS_AVG_0_SAMPLES means no averaging
+*		- XADCPS_AVG_16_SAMPLES means 16 samples of averaging
+*		- XADCPS_AVG_64_SAMPLES means 64 samples of averaging
+*		- XADCPS_AVG_256_SAMPLES means 256 samples of averaging
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XAdcPs_GetAvg(XAdcPs *InstancePtr)
+{
+	u32 Average;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the averaging value from the Configuration Register 0.
+	 */
+	Average = XAdcPs_ReadInternalReg(InstancePtr,
+			XADCPS_CFR0_OFFSET) & XADCPS_CFR0_AVG_VALID_MASK;
+
+
+	return ((u8) (Average >> XADCPS_CFR0_AVG_SHIFT));
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the given parameters in the Configuration Register 0 in
+* the single channel mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Channel is the channel number for the singel channel mode.
+*		The valid channels are 0 to 5, 8, and 16 to 31.
+*		If the external Mux is used then this specifies the channel
+*		oonnected to the external Mux. Please read the Device Spec
+*		to know which channels are valid.
+* @param 	IncreaseAcqCycles is a boolean parameter which specifies whether
+*		the Acquisition time for the external channels has to be
+*		increased to 10 ADCCLK cycles (specify TRUE) or remain at the
+*		default 4 ADCCLK cycles (specify FALSE). This parameter is
+*		only valid for the external channels.
+* @param 	IsDifferentialMode is a boolean parameter which specifies
+*		unipolar(specify FALSE) or differential mode (specify TRUE) for
+*		the analog inputs. The 	input mode is only valid for the
+*		external channels.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the Configuration Register 0.
+*		- XST_FAILURE if the channel sequencer is enabled or the input
+*		parameters are not valid for the selected channel.
+*
+* @note
+*		- The number of samples for the averaging for all the channels
+*		is set by using the function XAdcPs_SetAvg.
+*		- The calibration of the device is done by doing a ADC
+*		conversion on the calibration channel(channel 8). The input
+*		parameters IncreaseAcqCycles, IsDifferentialMode and
+*		IsEventMode are not valid for this channel
+*
+*
+*****************************************************************************/
+int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
+				u8 Channel,
+				int IncreaseAcqCycles,
+				int IsEventMode,
+				int IsDifferentialMode)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((Channel <= XADCPS_CH_VREFN) ||
+			(Channel == XADCPS_CH_ADC_CALIB) ||
+			((Channel >= XADCPS_CH_AUX_MIN) &&
+			(Channel <= XADCPS_CH_AUX_MAX)));
+	Xil_AssertNonvoid((IncreaseAcqCycles == TRUE) ||
+			(IncreaseAcqCycles == FALSE));
+	Xil_AssertNonvoid((IsEventMode == TRUE) || (IsEventMode == FALSE));
+	Xil_AssertNonvoid((IsDifferentialMode == TRUE) ||
+			(IsDifferentialMode == FALSE));
+
+	/*
+	 * Check if the device is in single channel mode else return failure
+	 */
+	if ((XAdcPs_GetSequencerMode(InstancePtr) !=
+		XADCPS_SEQ_MODE_SINGCHAN)) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Read the Configuration Register 0.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR0_OFFSET) &
+					XADCPS_CFR0_AVG_VALID_MASK;
+
+	/*
+	 * Select the number of acquisition cycles. The acquisition cycles is
+	 * only valid for the external channels.
+	 */
+	if (IncreaseAcqCycles == TRUE) {
+		if (((Channel >= XADCPS_CH_AUX_MIN) &&
+			(Channel <= XADCPS_CH_AUX_MAX)) ||
+			(Channel == XADCPS_CH_VPVN)){
+			RegValue |= XADCPS_CFR0_ACQ_MASK;
+		} else {
+			return XST_FAILURE;
+		}
+
+	}
+
+	/*
+	 * Select the input mode. The input mode is only valid for the
+	 * external channels.
+	 */
+	if (IsDifferentialMode == TRUE) {
+
+		if (((Channel >= XADCPS_CH_AUX_MIN) &&
+			(Channel <= XADCPS_CH_AUX_MAX)) ||
+			(Channel == XADCPS_CH_VPVN)){
+			RegValue |= XADCPS_CFR0_DU_MASK;
+		} else {
+			return XST_FAILURE;
+		}
+	}
+
+	/*
+	 * Select the ADC mode.
+	 */
+	if (IsEventMode == TRUE) {
+		RegValue |= XADCPS_CFR0_EC_MASK;
+	}
+
+	/*
+	 * Write the given values into the Configuration Register 0.
+	 */
+	RegValue |= (Channel & XADCPS_CFR0_CHANNEL_MASK);
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
+				RegValue);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the alarm outputs for the specified alarms in the
+* Configuration Register 1.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	AlmEnableMask is the bit-mask of the alarm outputs to be enabled
+*		in the Configuration Register 1.
+*		Bit positions of 1 will be enabled. Bit positions of 0 will be
+*		disabled. This mask is formed by OR'ing XADCPS_CFR1_ALM_*_MASK and
+*		XADCPS_CFR1_OT_MASK masks defined in xadcps_hw.h.
+*
+* @return	None.
+*
+* @note		The implementation of the alarm enables in the Configuration
+*		register 1 is such that the alarms for bit positions of 1 will
+*		be disabled and alarms for bit positions of 0 will be enabled.
+*		The alarm outputs specified by the AlmEnableMask are negated
+*		before writing to the Configuration Register 1.
+*
+*
+*****************************************************************************/
+void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr, XADCPS_CFR1_OFFSET);
+
+	RegValue &= (u32)~XADCPS_CFR1_ALM_ALL_MASK;
+	RegValue |= (~AlmEnableMask & XADCPS_CFR1_ALM_ALL_MASK);
+
+	/*
+	 * Enable/disables the alarm enables for the specified alarm bits in the
+	 * Configuration Register 1.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET,
+				RegValue);
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the status of the alarm output enables in the
+* Configuration Register 1.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	This is the bit-mask of the enabled alarm outputs in the
+*		Configuration Register 1. Use the masks XADCPS_CFR1_ALM*_* and
+*		XADCPS_CFR1_OT_MASK defined in xadcps_hw.h to interpret the
+*		returned value.
+*		Bit positions of 1 indicate that the alarm output is enabled.
+*		Bit positions of 0 indicate that the alarm output is disabled.
+*
+*
+* @note		The implementation of the alarm enables in the Configuration
+*		register 1 is such that alarms for the bit positions of 1 will
+*		be disabled and alarms for bit positions of 0 will be enabled.
+*		The enabled alarm outputs returned by this function is the
+*		negated value of the the data read from the Configuration
+*		Register 1.
+*
+*****************************************************************************/
+u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the status of alarm output enables from the Configuration
+	 * Register 1.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+			XADCPS_CFR1_OFFSET) & XADCPS_CFR1_ALM_ALL_MASK;
+	return (u16) (~RegValue & XADCPS_CFR1_ALM_ALL_MASK);
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the specified calibration in the Configuration
+* Register 1 :
+*
+* - XADCPS_CFR1_CAL_ADC_OFFSET_MASK : Calibration 0 -ADC offset correction
+* - XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK : Calibration 1 -ADC gain and offset
+*						correction
+* - XADCPS_CFR1_CAL_PS_OFFSET_MASK : Calibration 2 -Power Supply sensor
+*					offset correction
+* - XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK : Calibration 3 -Power Supply sensor
+*						gain and offset correction
+* - XADCPS_CFR1_CAL_DISABLE_MASK : No Calibration
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Calibration is the Calibration to be applied.
+*		Use XADCPS_CFR1_CAL*_* bits defined in xadcps_hw.h.
+*		Multiple calibrations can be enabled at a time by oring the
+*		XADCPS_CFR1_CAL_ADC_* and XADCPS_CFR1_CAL_PS_* bits.
+*		Calibration can be disabled by specifying
+		XADCPS_CFR1_CAL_DISABLE_MASK;
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(((Calibration >= XADCPS_CFR1_CAL_ADC_OFFSET_MASK) &&
+			(Calibration <= XADCPS_CFR1_CAL_VALID_MASK)) ||
+			(Calibration == XADCPS_CFR1_CAL_DISABLE_MASK));
+
+	/*
+	 * Set the specified calibration in the Configuration Register 1.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR1_OFFSET);
+
+	RegValue &= (~ XADCPS_CFR1_CAL_VALID_MASK);
+	RegValue |= (Calibration & XADCPS_CFR1_CAL_VALID_MASK);
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET,
+				RegValue);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function reads the value of the calibration enables from the
+* Configuration Register 1.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	The value of the calibration enables in the Configuration
+*		Register 1 :
+*		- XADCPS_CFR1_CAL_ADC_OFFSET_MASK : ADC offset correction
+*		- XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK : ADC gain and offset
+*				correction
+*		- XADCPS_CFR1_CAL_PS_OFFSET_MASK : Power Supply sensor offset
+*				correction
+*		- XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK : Power Supply sensor
+*				gain and offset correction
+*		- XADCPS_CFR1_CAL_DISABLE_MASK : No Calibration
+*
+* @note		None.
+*
+*****************************************************************************/
+u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the calibration enables from the Configuration Register 1.
+	 */
+	return (u16) XAdcPs_ReadInternalReg(InstancePtr,
+			XADCPS_CFR1_OFFSET) & XADCPS_CFR1_CAL_VALID_MASK;
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the specified Channel Sequencer Mode in the Configuration
+* Register 1 :
+*		- Default safe mode (XADCPS_SEQ_MODE_SAFE)
+*		- One pass through sequence (XADCPS_SEQ_MODE_ONEPASS)
+*		- Continuous channel sequencing (XADCPS_SEQ_MODE_CONTINPASS)
+*		- Single Channel/Sequencer off (XADCPS_SEQ_MODE_SINGCHAN)
+*		- Simulataneous sampling mode (XADCPS_SEQ_MODE_SIMUL_SAMPLING)
+*		- Independent mode (XADCPS_SEQ_MODE_INDEPENDENT)
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	SequencerMode is the sequencer mode to be set.
+*		Use XADCPS_SEQ_MODE_* bits defined in xadcps.h.
+* @return	None.
+*
+* @note		Only one of the modes can be enabled at a time. Please
+*		read the Spec of the XADC for further information about the
+*		sequencer modes.
+*
+*
+*****************************************************************************/
+void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((SequencerMode <= XADCPS_SEQ_MODE_SIMUL_SAMPLING) ||
+			(SequencerMode == XADCPS_SEQ_MODE_INDEPENDENT));
+
+	/*
+	 * Set the specified sequencer mode in the Configuration Register 1.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR1_OFFSET);
+	RegValue &= (~ XADCPS_CFR1_SEQ_VALID_MASK);
+	RegValue |= ((SequencerMode  << XADCPS_CFR1_SEQ_SHIFT) &
+					XADCPS_CFR1_SEQ_VALID_MASK);
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET,
+				RegValue);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the channel sequencer mode from the Configuration
+* Register 1.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	The channel sequencer mode :
+*		- XADCPS_SEQ_MODE_SAFE : Default safe mode
+*		- XADCPS_SEQ_MODE_ONEPASS : One pass through sequence
+*		- XADCPS_SEQ_MODE_CONTINPASS : Continuous channel sequencing
+*		- XADCPS_SEQ_MODE_SINGCHAN : Single channel/Sequencer off
+*		- XADCPS_SEQ_MODE_SIMUL_SAMPLING : Simulataneous sampling mode
+*		- XADCPS_SEQ_MODE_INDEPENDENT : Independent mode
+*
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the channel sequencer mode from the Configuration Register 1.
+	 */
+	return ((u8) ((XAdcPs_ReadInternalReg(InstancePtr,
+			XADCPS_CFR1_OFFSET) & XADCPS_CFR1_SEQ_VALID_MASK) >>
+			XADCPS_CFR1_SEQ_SHIFT));
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the frequency of the ADCCLK by configuring the DCLK to
+* ADCCLK ratio in the Configuration Register #2
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Divisor is clock divisor used to derive ADCCLK from DCLK.
+*		Valid values of the divisor are
+*		 - 0 to 255. Values 0, 1, 2 are all mapped to 2.
+*		Refer to the device specification for more details
+*
+* @return	None.
+*
+* @note		- The ADCCLK is an internal clock used by the ADC and is
+*		  synchronized to the DCLK clock. The ADCCLK is equal to DCLK
+*		  divided by the user selection in the Configuration Register 2.
+*		- There is no Assert on the minimum value of the Divisor.
+*
+*****************************************************************************/
+void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Write the divisor value into the Configuration Register #2.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR2_OFFSET,
+			  Divisor << XADCPS_CFR2_CD_SHIFT);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function gets the ADCCLK divisor from the Configuration Register 2.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	The divisor read from the Configuration Register 2.
+*
+* @note		The ADCCLK is an internal clock used by the ADC and is
+*		synchronized to the DCLK clock. The ADCCLK is equal to DCLK
+*		divided by the user selection in the Configuration Register 2.
+*
+*****************************************************************************/
+u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr)
+{
+	u16 Divisor;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the divisor value from the Configuration Register 2.
+	 */
+	Divisor = (u16) XAdcPs_ReadInternalReg(InstancePtr,
+					 XADCPS_CFR2_OFFSET);
+
+	return (u8) (Divisor >> XADCPS_CFR2_CD_SHIFT);
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the specified channels in the ADC Channel Selection
+* Sequencer Registers. The sequencer must be disabled before writing to these
+* regsiters.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	ChEnableMask is the bit mask of all the channels to be enabled.
+*		Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to specify the Channel
+*		numbers. Bit masks of 1 will be enabled and bit mask of 0 will
+*		be disabled.
+*		The ChEnableMask is a 32 bit mask that is written to the two
+*		16 bit ADC Channel Selection Sequencer Registers.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the ADC Channel Selection Sequencer Registers.
+*		- XST_FAILURE if the channel sequencer is enabled.
+*
+* @note		None
+*
+*****************************************************************************/
+int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The sequencer must be disabled for writing any of these registers
+	 * Return XST_FAILURE if the channel sequencer is enabled.
+	 */
+	if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Enable the specified channels in the ADC Channel Selection Sequencer
+	 * Registers.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ00_OFFSET,
+				(ChEnableMask & XADCPS_SEQ00_CH_VALID_MASK));
+
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ01_OFFSET,
+				(ChEnableMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
+				XADCPS_SEQ01_CH_VALID_MASK);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the channel enable bits status from the ADC Channel
+* Selection Sequencer Registers.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	Gets the channel enable bits. Use XADCPS_SEQ_CH__* defined in
+*		xadcps_hw.h to interpret the Channel numbers. Bit masks of 1
+*		are the channels that are enabled and bit mask of 0 are
+*		the channels that are disabled.
+*
+* @return	None
+*
+* @note		None
+*
+*****************************************************************************/
+u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr)
+{
+	u32 RegValEnable;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 *  Read the channel enable bits for all the channels from the ADC
+	 *  Channel Selection Register.
+	 */
+	RegValEnable = XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ00_OFFSET) &
+				XADCPS_SEQ00_CH_VALID_MASK;
+	RegValEnable |= (XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ01_OFFSET) &
+				XADCPS_SEQ01_CH_VALID_MASK) <<
+				XADCPS_SEQ_CH_AUX_SHIFT;
+
+
+	return RegValEnable;
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the averaging for the specified channels in the ADC
+* Channel Averaging Enable Sequencer Registers. The sequencer must be disabled
+* before writing to these regsiters.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	AvgEnableChMask is the bit mask of all the channels for which
+*		averaging is to be enabled. Use XADCPS_SEQ_CH__* defined in
+*		xadcps_hw.h to specify the Channel numbers. Averaging will be
+*		enabled for bit masks of 1 and disabled for bit mask of 0.
+*		The AvgEnableChMask is a 32 bit mask that is written to the two
+*		16 bit ADC Channel Averaging Enable Sequencer Registers.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the ADC Channel Averaging Enables Sequencer Registers.
+*		- XST_FAILURE if the channel sequencer is enabled.
+*
+* @note		None
+*
+*****************************************************************************/
+int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The sequencer must be disabled for writing any of these registers
+	 * Return XST_FAILURE if the channel sequencer is enabled.
+	 */
+	if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Enable/disable the averaging for the specified channels in the
+	 * ADC Channel Averaging Enables Sequencer Registers.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ02_OFFSET,
+				(AvgEnableChMask & XADCPS_SEQ02_CH_VALID_MASK));
+
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ03_OFFSET,
+				(AvgEnableChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
+				XADCPS_SEQ03_CH_VALID_MASK);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the channels for which the averaging has been enabled
+* in the ADC Channel Averaging Enables Sequencer Registers.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @returns 	The status of averaging (enabled/disabled) for all the channels.
+*		Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to interpret the
+*		Channel numbers. Bit masks of 1 are the channels for which
+*		averaging is enabled and bit mask of 0 are the channels for
+*		averaging is disabled
+*
+* @note		None
+*
+*****************************************************************************/
+u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr)
+{
+	u32 RegValAvg;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the averaging enable status for all the channels from the
+	 * ADC Channel Averaging Enables Sequencer Registers.
+	 */
+	RegValAvg = XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ02_OFFSET) & XADCPS_SEQ02_CH_VALID_MASK;
+	RegValAvg |= (XAdcPs_ReadInternalReg(InstancePtr,
+			XADCPS_SEQ03_OFFSET) & XADCPS_SEQ03_CH_VALID_MASK) <<
+			XADCPS_SEQ_CH_AUX_SHIFT;
+
+	return RegValAvg;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Analog input mode for the specified channels in the ADC
+* Channel Analog-Input Mode Sequencer Registers. The sequencer must be disabled
+* before writing to these regsiters.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	InputModeChMask is the bit mask of all the channels for which
+*		the input mode is differential mode. Use XADCPS_SEQ_CH__* defined
+*		in xadcps_hw.h to specify the channel numbers. Differential
+*		input mode will be set for bit masks of 1 and unipolar input
+*		mode for bit masks of 0.
+*		The InputModeChMask is a 32 bit mask that is written to the two
+*		16 bit ADC Channel Analog-Input Mode Sequencer Registers.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the ADC Channel Analog-Input Mode Sequencer Registers.
+*		- XST_FAILURE if the channel sequencer is enabled.
+*
+* @note		None
+*
+*****************************************************************************/
+int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The sequencer must be disabled for writing any of these registers
+	 * Return XST_FAILURE if the channel sequencer is enabled.
+	 */
+	if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Set the input mode for the specified channels in the ADC Channel
+	 * Analog-Input Mode Sequencer Registers.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ04_OFFSET,
+				(InputModeChMask & XADCPS_SEQ04_CH_VALID_MASK));
+
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ05_OFFSET,
+				(InputModeChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
+				XADCPS_SEQ05_CH_VALID_MASK);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the Analog input mode for all the channels from
+* the ADC Channel Analog-Input Mode Sequencer Registers.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @returns 	The input mode for all the channels.
+*		Use XADCPS_SEQ_CH_* defined in xadcps_hw.h to interpret the
+*		Channel numbers. Bit masks of 1 are the channels for which
+*		input mode is differential and bit mask of 0 are the channels
+*		for which input mode is unipolar.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr)
+{
+	u32 InputMode;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 *  Get the input mode for all the channels from the ADC Channel
+	 * Analog-Input Mode Sequencer Registers.
+	 */
+	InputMode = XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ04_OFFSET) &
+				XADCPS_SEQ04_CH_VALID_MASK;
+	InputMode |= (XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ05_OFFSET) &
+				XADCPS_SEQ05_CH_VALID_MASK) <<
+				XADCPS_SEQ_CH_AUX_SHIFT;
+
+	return InputMode;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the number of Acquisition cycles in the ADC Channel
+* Acquisition Time Sequencer Registers. The sequencer must be disabled
+* before writing to these regsiters.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	AcqCyclesChMask is the bit mask of all the channels for which
+*		the number of acquisition cycles is to be extended.
+*		Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to specify the Channel
+*		numbers. Acquisition cycles will be extended to 10 ADCCLK cycles
+*		for bit masks of 1 and will be the default 4 ADCCLK cycles for
+*		bit masks of 0.
+*		The AcqCyclesChMask is a 32 bit mask that is written to the two
+*		16 bit ADC Channel Acquisition Time Sequencer Registers.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the Channel Sequencer Registers.
+*		- XST_FAILURE if the channel sequencer is enabled.
+*
+* @note		None.
+*
+*****************************************************************************/
+int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The sequencer must be disabled for writing any of these registers
+	 * Return XST_FAILURE if the channel sequencer is enabled.
+	 */
+	if ((XAdcPs_GetSequencerMode(InstancePtr) !=
+			XADCPS_SEQ_MODE_SAFE)) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Set the Acquisition time for the specified channels in the
+	 * ADC Channel Acquisition Time Sequencer Registers.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ06_OFFSET,
+				(AcqCyclesChMask & XADCPS_SEQ06_CH_VALID_MASK));
+
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ07_OFFSET,
+				(AcqCyclesChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
+				XADCPS_SEQ07_CH_VALID_MASK);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the status of acquisition from the ADC Channel Acquisition
+* Time Sequencer Registers.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @returns 	The acquisition time for all the channels.
+*		Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to interpret the
+*		Channel numbers. Bit masks of 1 are the channels for which
+*		acquisition cycles are extended and bit mask of 0 are the
+*		channels for which acquisition cycles are not extended.
+*
+* @note		None
+*
+*****************************************************************************/
+u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr)
+{
+	u32 RegValAcq;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Get the Acquisition cycles for the specified channels from the ADC
+	 * Channel Acquisition Time Sequencer Registers.
+	 */
+	RegValAcq = XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ06_OFFSET) &
+				XADCPS_SEQ06_CH_VALID_MASK;
+	RegValAcq |= (XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ07_OFFSET) &
+				XADCPS_SEQ07_CH_VALID_MASK) <<
+				XADCPS_SEQ_CH_AUX_SHIFT;
+
+	return RegValAcq;
+}
+
+/****************************************************************************/
+/**
+*
+* This functions sets the contents of the given Alarm Threshold Register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	AlarmThrReg is the index of an Alarm Threshold Register to
+*		be set. Use XADCPS_ATR_* constants defined in xadcps.h to
+*		specify the index.
+* @param	Value is the 16-bit threshold value to write into the register.
+*
+* @return	None.
+*
+* @note		Use XAdcPs_SetOverTemp() to set the Over Temperature upper
+*		threshold value.
+*
+*****************************************************************************/
+void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value)
+{
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(AlarmThrReg <= XADCPS_ATR_VCCPDRO_LOWER);
+
+	/*
+	 * Write the value into the specified Alarm Threshold Register.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_ATR_TEMP_UPPER_OFFSET +
+					AlarmThrReg,Value);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the contents of the specified Alarm Threshold Register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	AlarmThrReg is the index of an Alarm Threshold Register
+*		to be read. Use XADCPS_ATR_* constants defined in 	xadcps_hw.h
+*		to specify the index.
+*
+* @return	A 16-bit value representing the contents of the selected Alarm
+*		Threshold Register.
+*
+* @note		None.
+*
+*****************************************************************************/
+u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg)
+{
+	u32 RegData;
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(AlarmThrReg <= XADCPS_ATR_VCCPDRO_LOWER);
+
+	/*
+	 * Read the specified Alarm Threshold Register and return
+	 * the value
+	 */
+	RegData = XAdcPs_ReadInternalReg(InstancePtr,
+				(XADCPS_ATR_TEMP_UPPER_OFFSET + AlarmThrReg));
+
+	return (u16) RegData;
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function enables programming of the powerdown temperature for the
+* OverTemp signal in the OT Powerdown register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr)
+{
+	u16 OtUpper;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the OT upper Alarm Threshold Register.
+	 */
+	OtUpper = XAdcPs_ReadInternalReg(InstancePtr,
+				   XADCPS_ATR_OT_UPPER_OFFSET);
+	OtUpper &= ~(XADCPS_ATR_OT_UPPER_ENB_MASK);
+
+	/*
+	 * Preserve the powerdown value and write OT enable value the into the
+	 * OT Upper Alarm Threshold Register.
+	 */
+	OtUpper |= XADCPS_ATR_OT_UPPER_ENB_VAL;
+	XAdcPs_WriteInternalReg(InstancePtr,
+			  XADCPS_ATR_OT_UPPER_OFFSET, OtUpper);
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables programming of the powerdown temperature for the
+* OverTemp signal in the OT Powerdown register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+*
+*****************************************************************************/
+void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr)
+{
+	u16 OtUpper;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the OT Upper Alarm Threshold Register.
+	 */
+	OtUpper = XAdcPs_ReadInternalReg(InstancePtr,
+					 XADCPS_ATR_OT_UPPER_OFFSET);
+	OtUpper &= ~(XADCPS_ATR_OT_UPPER_ENB_MASK);
+
+	XAdcPs_WriteInternalReg(InstancePtr,
+			  XADCPS_ATR_OT_UPPER_OFFSET, OtUpper);
+}
+
+
+/****************************************************************************/
+/**
+*
+* The function enables the Event mode or Continuous mode in the sequencer mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	IsEventMode is a boolean parameter that specifies continuous
+*		sampling (specify FALSE) or event driven sampling mode (specify
+*		TRUE) for the given channel.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((IsEventMode == TRUE) || (IsEventMode == FALSE));
+
+	/*
+	 * Read the Configuration Register 0.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR0_OFFSET) &
+					(~XADCPS_CFR0_EC_MASK);
+
+	/*
+	 * Set the ADC mode.
+	 */
+	if (IsEventMode == TRUE) {
+		RegValue |= XADCPS_CFR0_EC_MASK;
+	} else {
+		RegValue &= ~XADCPS_CFR0_EC_MASK;
+	}
+
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
+					RegValue);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function returns the sampling mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	The sampling mode
+*		- 0 specifies continuous sampling
+*		- 1 specifies event driven sampling mode
+*
+* @note		None.
+*
+*****************************************************************************/
+int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr)
+{
+	u32 Mode;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the sampling mode from the Configuration Register 0.
+	 */
+	Mode = XAdcPs_ReadInternalReg(InstancePtr,
+				   XADCPS_CFR0_OFFSET) &
+				   XADCPS_CFR0_EC_MASK;
+	if (Mode) {
+
+		return 1;
+	}
+
+	return (0);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function sets the External Mux mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param 	MuxMode specifies whether External Mux is used
+*		- FALSE specifies NO external MUX
+*		- TRUE specifies External Mux is used
+* @param	Channel specifies the channel to be used for the
+*		external Mux. Please read the Device Spec for which
+*		channels are valid for which mode.
+*
+* @return	None.
+*
+* @note		There is no Assert in this function for checking the channel
+*		number if the external Mux is used. The user should provide a
+*		valid channel number.
+*
+*****************************************************************************/
+void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((MuxMode == TRUE) || (MuxMode == FALSE));
+
+	/*
+	 * Read the Configuration Register 0.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR0_OFFSET) &
+					(~XADCPS_CFR0_MUX_MASK);
+	/*
+	 * Select the Mux mode and the channel to be used.
+	 */
+	if (MuxMode == TRUE) {
+		RegValue |= XADCPS_CFR0_MUX_MASK;
+		RegValue |= (Channel & XADCPS_CFR0_CHANNEL_MASK);
+
+	}
+
+	/*
+	 * Write the mux mode into the Configuration Register 0.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
+					RegValue);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function sets the Power Down mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param 	Mode specifies the Power Down Mode
+*		- XADCPS_PD_MODE_NONE specifies NO Power Down (Both ADC A and
+*		ADC B are enabled)
+*		- XADCPS_PD_MODE_ADCB specfies the Power Down of ADC B
+*		- XADCPS_PD_MODE_XADC specifies the Power Down of
+*		both ADC A and ADC B.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Mode < XADCPS_PD_MODE_XADC);
+
+
+	/*
+	 * Read the Configuration Register 2.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR2_OFFSET) &
+					(~XADCPS_CFR2_PD_MASK);
+	/*
+	 * Select the Power Down mode.
+	 */
+	RegValue |= (Mode << XADCPS_CFR2_PD_SHIFT);
+
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR2_OFFSET,
+					RegValue);
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the Power Down mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	Mode specifies the Power Down Mode
+*		- XADCPS_PD_MODE_NONE specifies NO Power Down (Both ADC A and
+*		ADC B are enabled)
+*		- XADCPS_PD_MODE_ADCB specfies the Power Down of ADC B
+*		- XADCPS_PD_MODE_XADC specifies the Power Down of
+*		both ADC A and ADC B.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Power Down Mode.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR2_OFFSET) &
+					(~XADCPS_CFR2_PD_MASK);
+	/*
+	 * Return the Power Down mode.
+	 */
+	return (RegValue >> XADCPS_CFR2_PD_SHIFT);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for writing to XADC Registers using the command FIFO.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	RegOffset is the offset of the XADC register to be written.
+* @param	Data is the data to be written.
+*
+* @return	None.
+*
+* @note		None.
+*
+*
+*****************************************************************************/
+void XAdcPs_WriteInternalReg(XAdcPs *InstancePtr, u32 RegOffset, u32 Data)
+{
+	u32 RegData;
+
+	/*
+	 * Write the Data into the FIFO Register.
+	 */
+	RegData = XAdcPs_FormatWriteData(RegOffset, Data, TRUE);
+
+	XAdcPs_WriteFifo(InstancePtr, RegData);
+
+	/* Read the Read FIFO after any write since for each write
+	 * one location of Read FIFO gets updated
+	 */
+	XAdcPs_ReadFifo(InstancePtr);
+
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function is used for reading from the XADC Registers using the Data FIFO.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	RegOffset is the offset of the XADC register to be read.
+*
+* @return	Data read from the FIFO
+*
+* @note		None.
+*
+*
+*****************************************************************************/
+u32 XAdcPs_ReadInternalReg(XAdcPs *InstancePtr, u32 RegOffset)
+{
+
+	u32 RegData;
+
+	RegData = XAdcPs_FormatWriteData(RegOffset, 0x0, FALSE);
+
+	/* Read cmd to FIFO*/
+	XAdcPs_WriteFifo(InstancePtr, RegData);
+
+	/* Do a Dummy read */
+	RegData = XAdcPs_ReadFifo(InstancePtr);
+
+	/* Do a Dummy write to get the actual read */
+	XAdcPs_WriteFifo(InstancePtr, RegData);
+
+	/* Do the Actual read */
+	RegData = XAdcPs_ReadFifo(InstancePtr);
+
+	return RegData;
+
+}
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_0/src/xadcps.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_0/src/xadcps.h
new file mode 100644
index 000000000..7306f8d94
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_0/src/xadcps.h
@@ -0,0 +1,568 @@
+/******************************************************************************
+*
+* (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps.h
+*
+* The XAdcPs driver supports the Xilinx XADC/ADC device.
+*
+* The XADC/ADC device has the following features:
+*	- 10-bit, 200-KSPS (kilo samples per second)
+*		Analog-to-Digital Converter (ADC)
+*	- Monitoring of on-chip supply voltages and temperature
+*	- 1 dedicated differential analog-input pair and
+*	  16 auxiliary differential analog-input pairs
+*	- Automatic alarms based on user defined limits for the on-chip
+*	  supply voltages and temperature
+*	- Automatic Channel Sequencer, programmable averaging, programmable
+*	  acquisition time for the external inputs, unipolar or differential
+*	  input selection for the external inputs
+*	- Inbuilt Calibration
+*	- Optional interrupt request generation
+*
+*
+* The user should refer to the hardware device specification for detailed
+* information about the device.
+*
+* This header file contains the prototypes of driver functions that can
+* be used to access the XADC/ADC device.
+*
+*
+*  XADC Channel Sequencer Modes 
+*
+* The  XADC Channel Sequencer supports the following operating modes:
+*
+*   -  Default : This is the default mode after power up.
+*		In this mode of operation the XADC operates in
+*		a sequence mode, monitoring the on chip sensors:
+*		Temperature, VCCINT, and VCCAUX.
+*   -  One pass through sequence : In this mode the XADC
+*		converts the channels enabled in the Sequencer Channel Enable
+*		registers for a single pass and then stops.
+*   -  Continuous cycling of sequence : In this mode the XADC
+*		converts the channels enabled in the Sequencer Channel Enable
+*		registers continuously.
+*   -  Single channel mode: In this mode the XADC Channel
+*		Sequencer is disabled and the XADC operates in a
+*		Single Channel Mode.
+*		The XADC can operate either in a Continuous or Event
+*		driven sampling mode in the single channel mode.
+*   -  Simultaneous Sampling Mode: In this mode the XADC Channel
+*		Sequencer will automatically sequence through eight fixed pairs
+*		of auxiliary analog input channels for simulataneous conversion.
+*   -  Independent ADC mode: In this mode the first ADC (A) is used to
+*		is used to implement a fixed monitoring mode similar to the
+*		default mode but the alarm fucntions ar eenabled.
+*		The second ADC (B) is available to be used with external analog
+*		input channels only.
+*
+* Read the XADC spec for more information about the sequencer modes.
+*
+*  Initialization and Configuration 
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the XADC/ADC device.
+*
+* XAdcPs_CfgInitialize() API is used to initialize the XADC/ADC
+* device. The user needs to first call the XAdcPs_LookupConfig() API which
+* returns the Configuration structure pointer which is passed as a parameter to
+* the XAdcPs_CfgInitialize() API.
+*
+*
+* Interrupts
+*
+* The XADC/ADC device supports interrupt driven mode and the default
+* operation mode is polling mode.
+*
+* The interrupt mode is available only if hardware is configured to support
+* interrupts.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* device in interrupt mode.
+*
+*
+*  Virtual Memory 
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+*
+*  Threads 
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+*
+*  Asserts 
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+*
+*  Building the driver 
+*
+* The XAdcPs driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+*  Limitations of the driver 
+*
+* XADC/ADC device can be accessed through the JTAG port and the PLB
+* interface. The driver implementation does not support the simultaneous access
+* of the device by both these interfaces. The user has to care of this situation
+* in the user application code.
+*
+* 


+*
+* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a ssb    12/22/11 First release based on the XPS/AXI xadc driver
+* 1.01a bss    02/18/13	Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
+*			XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
+*			in xadcps.c to fix CR #693371
+* 1.03a bss    11/01/13 Modified xadcps_hw.h to use correct Register offsets
+*			CR#749687
+* 

+*
+*****************************************************************************/
+#ifndef XADCPS_H /* Prevent circular inclusions */
+#define XADCPS_H /* by using protection macros  */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xadcps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**
+ * @name Indexes for the different channels.
+ * @{
+ */
+#define XADCPS_CH_TEMP		0x0  /**< On Chip Temperature */
+#define XADCPS_CH_VCCINT	0x1  /**< VCCINT */
+#define XADCPS_CH_VCCAUX	0x2  /**< VCCAUX */
+#define XADCPS_CH_VPVN		0x3  /**< VP/VN Dedicated analog inputs */
+#define XADCPS_CH_VREFP		0x4  /**< VREFP */
+#define XADCPS_CH_VREFN		0x5  /**< VREFN */
+#define XADCPS_CH_VBRAM		0x6  /**< On-chip VBRAM Data Reg, 7 series */
+#define XADCPS_CH_SUPPLY_CALIB	0x07 /**< Supply Calib Data Reg */
+#define XADCPS_CH_ADC_CALIB	0x08 /**< ADC Offset Channel Reg */
+#define XADCPS_CH_GAINERR_CALIB 0x09 /**< Gain Error Channel Reg  */
+#define XADCPS_CH_VCCPINT	0x0D /**< On-chip PS VCCPINT Channel , Zynq */
+#define XADCPS_CH_VCCPAUX	0x0E /**< On-chip PS VCCPAUX Channel , Zynq */
+#define XADCPS_CH_VCCPDRO	0x0F /**< On-chip PS VCCPDRO Channel , Zynq */
+#define XADCPS_CH_AUX_MIN	 16 /**< Channel number for 1st Aux Channel */
+#define XADCPS_CH_AUX_MAX	 31 /**< Channel number for Last Aux channel */
+
+/*@}*/
+
+
+/**
+ * @name Indexes for reading the Calibration Coefficient Data.
+ * @{
+ */
+#define XADCPS_CALIB_SUPPLY_COEFF     0 /**< Supply Offset Calib Coefficient */
+#define XADCPS_CALIB_ADC_COEFF        1 /**< ADC Offset Calib Coefficient */
+#define XADCPS_CALIB_GAIN_ERROR_COEFF 2 /**< Gain Error Calib Coefficient*/
+/*@}*/
+
+
+/**
+ * @name Indexes for reading the Minimum/Maximum Measurement Data.
+ * @{
+ */
+#define XADCPS_MAX_TEMP		0 /**< Maximum Temperature Data */
+#define XADCPS_MAX_VCCINT	1 /**< Maximum VCCINT Data */
+#define XADCPS_MAX_VCCAUX	2 /**< Maximum VCCAUX Data */
+#define XADCPS_MAX_VBRAM	3 /**< Maximum VBRAM Data */
+#define XADCPS_MIN_TEMP		4 /**< Minimum Temperature Data */
+#define XADCPS_MIN_VCCINT	5 /**< Minimum VCCINT Data */
+#define XADCPS_MIN_VCCAUX	6 /**< Minimum VCCAUX Data */
+#define XADCPS_MIN_VBRAM	7 /**< Minimum VBRAM Data */
+#define XADCPS_MAX_VCCPINT	8 /**< Maximum VCCPINT Register , Zynq */
+#define XADCPS_MAX_VCCPAUX	9 /**< Maximum VCCPAUX Register , Zynq */
+#define XADCPS_MAX_VCCPDRO	0xA /**< Maximum VCCPDRO Register , Zynq */
+#define XADCPS_MIN_VCCPINT	0xC /**< Minimum VCCPINT Register , Zynq */
+#define XADCPS_MIN_VCCPAUX	0xD /**< Minimum VCCPAUX Register , Zynq */
+#define XADCPS_MIN_VCCPDRO	0xE /**< Minimum VCCPDRO Register , Zynq */
+
+/*@}*/
+
+
+/**
+ * @name Alarm Threshold(Limit) Register (ATR) indexes.
+ * @{
+ */
+#define XADCPS_ATR_TEMP_UPPER	 0 /**< High user Temperature */
+#define XADCPS_ATR_VCCINT_UPPER  1 /**< VCCINT high voltage limit register */
+#define XADCPS_ATR_VCCAUX_UPPER  2 /**< VCCAUX high voltage limit register */
+#define XADCPS_ATR_OT_UPPER	 3 /**< VCCAUX high voltage limit register */
+#define XADCPS_ATR_TEMP_LOWER	 4 /**< Upper Over Temperature limit Reg */
+#define XADCPS_ATR_VCCINT_LOWER	 5 /**< VCCINT high voltage limit register */
+#define XADCPS_ATR_VCCAUX_LOWER	 6 /**< VCCAUX low voltage limit register  */
+#define XADCPS_ATR_OT_LOWER	 7 /**< Lower Over Temperature limit */
+#define XADCPS_ATR_VBRAM_UPPER_  8 /**< VRBAM Upper Alarm Reg, 7 Series */
+#define XADCPS_ATR_VCCPINT_UPPER 9 /**< VCCPINT Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VCCPAUX_UPPER 0xA /**< VCCPAUX Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VCCPDRO_UPPER 0xB /**< VCCPDRO Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VBRAM_LOWER	 0xC /**< VRBAM Lower Alarm Reg, 7 Series */
+#define XADCPS_ATR_VCCPINT_LOWER 0xD /**< VCCPINT Lower Alarm Reg , Zynq */
+#define XADCPS_ATR_VCCPAUX_LOWER 0xE /**< VCCPAUX Lower Alarm Reg , Zynq */
+#define XADCPS_ATR_VCCPDRO_LOWER 0xF /**< VCCPDRO Lower Alarm Reg , Zynq */
+
+/*@}*/
+
+
+/**
+ * @name Averaging to be done for the channels.
+ * @{
+ */
+#define XADCPS_AVG_0_SAMPLES	0  /**< No Averaging */
+#define XADCPS_AVG_16_SAMPLES	1  /**< Average 16 samples */
+#define XADCPS_AVG_64_SAMPLES	2  /**< Average 64 samples */
+#define XADCPS_AVG_256_SAMPLES	3  /**< Average 256 samples */
+
+/*@}*/
+
+
+/**
+ * @name Channel Sequencer Modes of operation
+ * @{
+ */
+#define XADCPS_SEQ_MODE_SAFE		0  /**< Default Safe Mode */
+#define XADCPS_SEQ_MODE_ONEPASS		1  /**< Onepass through Sequencer */
+#define XADCPS_SEQ_MODE_CONTINPASS	2  /**< Continuous Cycling Sequencer */
+#define XADCPS_SEQ_MODE_SINGCHAN	3  /**< Single channel -No Sequencing */
+#define XADCPS_SEQ_MODE_SIMUL_SAMPLING	4  /**< Simultaneous sampling */
+#define XADCPS_SEQ_MODE_INDEPENDENT	8  /**< Independent mode */
+
+/*@}*/
+
+
+
+/**
+ * @name Power Down Modes
+ * @{
+ */
+#define XADCPS_PD_MODE_NONE		0  /**< No Power Down  */
+#define XADCPS_PD_MODE_ADCB		1  /**< Power Down ADC B */
+#define XADCPS_PD_MODE_XADC		2  /**< Power Down ADC A and ADC B */
+/*@}*/
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the XADC/ADC
+ * device.
+ */
+typedef struct {
+	u16  DeviceId;		/**< Unique ID of device */
+	u32  BaseAddress;	/**< Device base address */
+} XAdcPs_Config;
+
+
+/**
+ * The driver's instance data. The user is required to allocate a variable
+ * of this type for every XADC/ADC device in the system. A pointer to
+ * a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XAdcPs_Config Config;	/**< XAdcPs_Config of current device */
+	u32  IsReady;		/**< Device is initialized and ready  */
+
+} XAdcPs;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the XADC device is in Event Sampling mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+*		- TRUE if the device is in Event Sampling Mode.
+*		- FALSE if the device is in Continuous Sampling Mode.
+*
+* @note		C-Style signature:
+*		int XAdcPs_IsEventSamplingMode(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_IsEventSamplingModeSet(InstancePtr)			\
+	(((XAdcPs_ReadInternalReg(InstancePtr,	 			\
+			XADCPS_CFR0_OFFSET) & XADCPS_CFR0_EC_MASK) ?	\
+			TRUE : FALSE))
+
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the XADC device is in External Mux mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+*		- TRUE if the device is in External Mux Mode.
+*		- FALSE if the device is NOT in External Mux Mode.
+*
+* @note		C-Style signature:
+*		int XAdcPs_IsExternalMuxMode(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_IsExternalMuxModeSet(InstancePtr)			\
+	(((XAdcPs_ReadInternalReg(InstancePtr,	 			\
+			XADCPS_CFR0_OFFSET) & XADCPS_CFR0_MUX_MASK) ?	\
+			TRUE : FALSE))
+
+/****************************************************************************/
+/**
+*
+* This macro converts XADC Raw Data to Temperature(centigrades).
+*
+* @param	AdcData is the Raw ADC Data from XADC.
+*
+* @return 	The Temperature in centigrades.
+*
+* @note		C-Style signature:
+*		float XAdcPs_RawToTemperature(u32 AdcData);
+*
+*****************************************************************************/
+#define XAdcPs_RawToTemperature(AdcData)				\
+	((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f)
+
+/****************************************************************************/
+/**
+*
+* This macro converts XADC/ADC Raw Data to Voltage(volts).
+*
+* @param	AdcData is the XADC/ADC Raw Data.
+*
+* @return 	The Voltage in volts.
+*
+* @note		C-Style signature:
+*		float XAdcPs_RawToVoltage(u32 AdcData);
+*
+*****************************************************************************/
+#define XAdcPs_RawToVoltage(AdcData) 					\
+	((((float)(AdcData))* (3.0f))/65536.0f)
+
+/****************************************************************************/
+/**
+*
+* This macro converts Temperature in centigrades to XADC/ADC Raw Data.
+*
+* @param	Temperature is the Temperature in centigrades to be
+*		converted to XADC/ADC Raw Data.
+*
+* @return 	The XADC/ADC Raw Data.
+*
+* @note		C-Style signature:
+*		int XAdcPs_TemperatureToRaw(float Temperature);
+*
+*****************************************************************************/
+#define XAdcPs_TemperatureToRaw(Temperature)				\
+	((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f))
+
+/****************************************************************************/
+/**
+*
+* This macro converts Voltage in Volts to XADC/ADC Raw Data.
+*
+* @param	Voltage is the Voltage in volts to be converted to
+*		XADC/ADC Raw Data.
+*
+* @return 	The XADC/ADC Raw Data.
+*
+* @note		C-Style signature:
+*		int XAdcPs_VoltageToRaw(float Voltage);
+*
+*****************************************************************************/
+#define XAdcPs_VoltageToRaw(Voltage)			 		\
+	((int)((Voltage)*65536.0f/3.0f))
+
+
+/****************************************************************************/
+/**
+*
+* This macro is used for writing to the XADC Registers using the
+* command FIFO.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XAdcPs_WriteFifo(XAdcPs *InstancePtr, u32 Data);
+*
+*****************************************************************************/
+#define XAdcPs_WriteFifo(InstancePtr, Data)				\
+	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,		\
+			  XADCPS_CMDFIFO_OFFSET, Data);
+
+
+/****************************************************************************/
+/**
+*
+* This macro is used for reading from the XADC Registers using the
+* data FIFO.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	Data read from the FIFO
+*
+* @note		C-Style signature:
+*		u32 XAdcPs_ReadFifo(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_ReadFifo(InstancePtr)				\
+	XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,	\
+			  XADCPS_RDFIFO_OFFSET);
+
+
+/************************** Function Prototypes *****************************/
+
+
+
+/**
+ * Functions in xadcps_sinit.c
+ */
+XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId);
+
+/**
+ * Functions in xadcps.c
+ */
+int XAdcPs_CfgInitialize(XAdcPs *InstancePtr,
+				XAdcPs_Config *ConfigPtr,
+				u32 EffectiveAddr);
+
+
+u32 XAdcPs_GetStatus(XAdcPs *InstancePtr);
+
+u32 XAdcPs_GetAlarmOutputStatus(XAdcPs *InstancePtr);
+
+void XAdcPs_StartAdcConversion(XAdcPs *InstancePtr);
+
+void XAdcPs_Reset(XAdcPs *InstancePtr);
+
+u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel);
+
+u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType);
+
+u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType);
+
+void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average);
+u8 XAdcPs_GetAvg(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
+				u8 Channel,
+				int IncreaseAcqCycles,
+				int IsEventMode,
+				int IsDifferentialMode);
+
+
+void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask);
+u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr);
+
+void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration);
+u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr);
+
+void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode);
+u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr);
+
+void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor);
+u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask);
+u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask);
+u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask);
+u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask);
+u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr);
+
+void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value);
+u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg);
+
+void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr);
+void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr);
+
+/**
+ * Functions in xadcps_selftest.c
+ */
+int XAdcPs_SelfTest(XAdcPs *InstancePtr);
+
+/**
+ * Functions in xadcps_intr.c
+ */
+void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask);
+void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask);
+u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr);
+
+u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr);
+void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* End of protection macro. */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_0/src/xadcps_g.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_0/src/xadcps_g.c
new file mode 100644
index 000000000..4482c8764
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_0/src/xadcps_g.c
@@ -0,0 +1,31 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSM.
+* Version: 
+* DO NOT EDIT.
+*
+*  v (64-bit)
+SW Build (by ) on 
+Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xadcps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XAdcPs_Config XAdcPs_ConfigTable[] =
+{
+	{
+		XPAR_PS7_XADC_0_DEVICE_ID,
+		XPAR_PS7_XADC_0_BASEADDR
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_0/src/xadcps_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_0/src/xadcps_hw.h
new file mode 100644
index 000000000..101dcb7d7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_0/src/xadcps_hw.h
@@ -0,0 +1,508 @@
+/******************************************************************************
+*
+* (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps_hw.h
+*
+* This header file contains identifiers and basic driver functions (or
+* macros) that can be used to access the XADC device through the Device
+* Config Interface of the Zynq.
+*
+*
+* Refer to the device specification for more information about this driver.
+*
+* @note	 None.
+*
+*
+* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a bss    12/22/11 First release based on the XPS/AXI xadc driver
+* 1.03a bss    11/01/13 Modified macros to use correct Register offsets
+*			CR#749687
+*
+* 

+*
+*****************************************************************************/
+#ifndef XADCPS_HW_H /* Prevent circular inclusions */
+#define XADCPS_HW_H /* by using protection macros  */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**@name Register offsets of XADC in the Device Config
+ *
+ * The following constants provide access to each of the registers of the
+ * XADC device.
+ * @{
+ */
+
+#define XADCPS_CFG_OFFSET	 0x00 /**< Configuration Register */
+#define XADCPS_INT_STS_OFFSET	 0x04 /**< Interrupt Status Register */
+#define XADCPS_INT_MASK_OFFSET	 0x08 /**< Interrupt Mask Register */
+#define XADCPS_MSTS_OFFSET	 0x0C /**< Misc status register */
+#define XADCPS_CMDFIFO_OFFSET	 0x10 /**< Command FIFO Register */
+#define XADCPS_RDFIFO_OFFSET	 0x14 /**< Read FIFO Register */
+#define XADCPS_MCTL_OFFSET	 0x18 /**< Misc control register */
+
+/* @} */
+
+
+
+
+
+/** @name XADC Config Register Bit definitions
+  * @{
+ */
+#define XADCPS_CFG_ENABLE_MASK	 0x80000000 /**< Enable access from PS mask */
+#define XADCPS_CFG_CFIFOTH_MASK  0x00F00000 /**< Command FIFO Threshold mask */
+#define XADCPS_CFG_DFIFOTH_MASK  0x000F0000 /**< Data FIFO Threshold mask */
+#define XADCPS_CFG_WEDGE_MASK	 0x00002000 /**< Write Edge Mask */
+#define XADCPS_CFG_REDGE_MASK	 0x00001000 /**< Read Edge Mask */
+#define XADCPS_CFG_TCKRATE_MASK  0x00000300 /**< Clock freq control */
+#define XADCPS_CFG_IGAP_MASK	 0x0000001F /**< Idle Gap between
+						* successive commands */
+/* @} */
+
+
+/** @name XADC Interrupt Status/Mask Register Bit definitions
+  *
+  * The definitions are same for the Interrupt Status Register and
+  * Interrupt Mask Register. They are defined only once.
+  * @{
+ */
+#define XADCPS_INTX_ALL_MASK   	   0x000003FF /**< Alarm Signals Mask  */
+#define XADCPS_INTX_CFIFO_LTH_MASK 0x00000200 /**< CMD FIFO less than threshold */
+#define XADCPS_INTX_DFIFO_GTH_MASK 0x00000100 /**< Data FIFO greater than threshold */
+#define XADCPS_INTX_OT_MASK	   0x00000080 /**< Over temperature Alarm Status */
+#define XADCPS_INTX_ALM_ALL_MASK   0x0000007F /**< Alarm Signals Mask  */
+#define XADCPS_INTX_ALM6_MASK	   0x00000040 /**< Alarm 6 Mask  */
+#define XADCPS_INTX_ALM5_MASK	   0x00000020 /**< Alarm 5 Mask  */
+#define XADCPS_INTX_ALM4_MASK	   0x00000010 /**< Alarm 4 Mask  */
+#define XADCPS_INTX_ALM3_MASK	   0x00000008 /**< Alarm 3 Mask  */
+#define XADCPS_INTX_ALM2_MASK	   0x00000004 /**< Alarm 2 Mask  */
+#define XADCPS_INTX_ALM1_MASK	   0x00000002 /**< Alarm 1 Mask  */
+#define XADCPS_INTX_ALM0_MASK	   0x00000001 /**< Alarm 0 Mask  */
+
+/* @} */
+
+
+/** @name XADC Miscellaneous Register Bit definitions
+  * @{
+ */
+#define XADCPS_MSTS_CFIFO_LVL_MASK  0x000F0000 /**< Command FIFO Level mask */
+#define XADCPS_MSTS_DFIFO_LVL_MASK  0x0000F000 /**< Data FIFO Level Mask  */
+#define XADCPS_MSTS_CFIFOF_MASK     0x00000800 /**< Command FIFO Full Mask  */
+#define XADCPS_MSTS_CFIFOE_MASK     0x00000400 /**< Command FIFO Empty Mask  */
+#define XADCPS_MSTS_DFIFOF_MASK     0x00000200 /**< Data FIFO Full Mask  */
+#define XADCPS_MSTS_DFIFOE_MASK     0x00000100 /**< Data FIFO Empty Mask  */
+#define XADCPS_MSTS_OT_MASK	    0x00000080 /**< Over Temperature Mask */
+#define XADCPS_MSTS_ALM_MASK	    0x0000007F /**< Alarms Mask  */
+/* @} */
+
+
+/** @name XADC Miscellaneous Control Register Bit definitions
+  * @{
+ */
+#define XADCPS_MCTL_RESET_MASK      0x00000010 /**< Reset XADC */
+#define XADCPS_MCTL_FLUSH_MASK      0x00000001 /**< Flush the FIFOs */
+/* @} */
+
+
+/**@name Internal Register offsets of the XADC
+ *
+ * The following constants provide access to each of the internal registers of
+ * the XADC device.
+ * @{
+ */
+
+/*
+ * XADC Internal Channel Registers
+ */
+#define XADCPS_TEMP_OFFSET		  0x00 /**< On-chip Temperature Reg */
+#define XADCPS_VCCINT_OFFSET		  0x01 /**< On-chip VCCINT Data Reg */
+#define XADCPS_VCCAUX_OFFSET		  0x02 /**< On-chip VCCAUX Data Reg */
+#define XADCPS_VPVN_OFFSET		  0x03 /**< ADC out of VP/VN	   */
+#define XADCPS_VREFP_OFFSET		  0x04 /**< On-chip VREFP Data Reg */
+#define XADCPS_VREFN_OFFSET		  0x05 /**< On-chip VREFN Data Reg */
+#define XADCPS_VBRAM_OFFSET		  0x06 /**< On-chip VBRAM , 7 Series */
+#define XADCPS_ADC_A_SUPPLY_CALIB_OFFSET  0x08 /**< ADC A Supply Offset Reg */
+#define XADCPS_ADC_A_OFFSET_CALIB_OFFSET  0x09 /**< ADC A Offset Data Reg */
+#define XADCPS_ADC_A_GAINERR_CALIB_OFFSET 0x0A /**< ADC A Gain Error Reg  */
+#define XADCPS_VCCPINT_OFFSET		  0x0D /**< On-chip VCCPINT Reg, Zynq */
+#define XADCPS_VCCPAUX_OFFSET		  0x0E /**< On-chip VCCPAUX Reg, Zynq */
+#define XADCPS_VCCPDRO_OFFSET		  0x0F /**< On-chip VCCPDRO Reg, Zynq */
+
+/*
+ * XADC External Channel Registers
+ */
+#define XADCPS_AUX00_OFFSET	0x10 /**< ADC out of VAUXP0/VAUXN0 */
+#define XADCPS_AUX01_OFFSET	0x11 /**< ADC out of VAUXP1/VAUXN1 */
+#define XADCPS_AUX02_OFFSET	0x12 /**< ADC out of VAUXP2/VAUXN2 */
+#define XADCPS_AUX03_OFFSET	0x13 /**< ADC out of VAUXP3/VAUXN3 */
+#define XADCPS_AUX04_OFFSET	0x14 /**< ADC out of VAUXP4/VAUXN4 */
+#define XADCPS_AUX05_OFFSET	0x15 /**< ADC out of VAUXP5/VAUXN5 */
+#define XADCPS_AUX06_OFFSET	0x16 /**< ADC out of VAUXP6/VAUXN6 */
+#define XADCPS_AUX07_OFFSET	0x17 /**< ADC out of VAUXP7/VAUXN7 */
+#define XADCPS_AUX08_OFFSET	0x18 /**< ADC out of VAUXP8/VAUXN8 */
+#define XADCPS_AUX09_OFFSET	0x19 /**< ADC out of VAUXP9/VAUXN9 */
+#define XADCPS_AUX10_OFFSET	0x1A /**< ADC out of VAUXP10/VAUXN10 */
+#define XADCPS_AUX11_OFFSET	0x1B /**< ADC out of VAUXP11/VAUXN11 */
+#define XADCPS_AUX12_OFFSET	0x1C /**< ADC out of VAUXP12/VAUXN12 */
+#define XADCPS_AUX13_OFFSET	0x1D /**< ADC out of VAUXP13/VAUXN13 */
+#define XADCPS_AUX14_OFFSET	0x1E /**< ADC out of VAUXP14/VAUXN14 */
+#define XADCPS_AUX15_OFFSET	0x1F /**< ADC out of VAUXP15/VAUXN15 */
+
+/*
+ * XADC Registers for Maximum/Minimum data captured for the
+ * on chip Temperature/VCCINT/VCCAUX data.
+ */
+#define XADCPS_MAX_TEMP_OFFSET		0x20 /**< Max Temperature Reg */
+#define XADCPS_MAX_VCCINT_OFFSET	0x21 /**< Max VCCINT Register */
+#define XADCPS_MAX_VCCAUX_OFFSET	0x22 /**< Max VCCAUX Register */
+#define XADCPS_MAX_VCCBRAM_OFFSET	0x23 /**< Max BRAM Register, 7 series */
+#define XADCPS_MIN_TEMP_OFFSET		0x24 /**< Min Temperature Reg */
+#define XADCPS_MIN_VCCINT_OFFSET	0x25 /**< Min VCCINT Register */
+#define XADCPS_MIN_VCCAUX_OFFSET	0x26 /**< Min VCCAUX Register */
+#define XADCPS_MIN_VCCBRAM_OFFSET	0x27 /**< Min BRAM Register, 7 series */
+#define XADCPS_MAX_VCCPINT_OFFSET	0x28 /**< Max VCCPINT Register, Zynq */
+#define XADCPS_MAX_VCCPAUX_OFFSET	0x29 /**< Max VCCPAUX Register, Zynq */
+#define XADCPS_MAX_VCCPDRO_OFFSET	0x2A /**< Max VCCPDRO Register, Zynq */
+#define XADCPS_MIN_VCCPINT_OFFSET	0x2C /**< Min VCCPINT Register, Zynq */
+#define XADCPS_MIN_VCCPAUX_OFFSET	0x2D /**< Min VCCPAUX Register, Zynq */
+#define XADCPS_MIN_VCCPDRO_OFFSET	0x2E /**< Min VCCPDRO Register,Zynq */
+ /* Undefined 0x2F to 0x3E */
+#define XADCPS_FLAG_OFFSET		0x3F /**< Flag Register */
+
+/*
+ * XADC Configuration Registers
+ */
+#define XADCPS_CFR0_OFFSET	0x40	/**< Configuration Register 0 */
+#define XADCPS_CFR1_OFFSET	0x41	/**< Configuration Register 1 */
+#define XADCPS_CFR2_OFFSET	0x42	/**< Configuration Register 2 */
+
+/* Test Registers 0x43 to 0x47 */
+
+/*
+ * XADC Sequence Registers
+ */
+#define XADCPS_SEQ00_OFFSET	0x48 /**< Seq Reg 00 Adc Channel Selection */
+#define XADCPS_SEQ01_OFFSET	0x49 /**< Seq Reg 01 Adc Channel Selection */
+#define XADCPS_SEQ02_OFFSET	0x4A /**< Seq Reg 02 Adc Average Enable */
+#define XADCPS_SEQ03_OFFSET	0x4B /**< Seq Reg 03 Adc Average Enable */
+#define XADCPS_SEQ04_OFFSET	0x4C /**< Seq Reg 04 Adc Input Mode Select */
+#define XADCPS_SEQ05_OFFSET	0x4D /**< Seq Reg 05 Adc Input Mode Select */
+#define XADCPS_SEQ06_OFFSET	0x4E /**< Seq Reg 06 Adc Acquisition Select */
+#define XADCPS_SEQ07_OFFSET	0x4F /**< Seq Reg 07 Adc Acquisition Select */
+
+/*
+ * XADC Alarm Threshold/Limit Registers (ATR)
+ */
+#define XADCPS_ATR_TEMP_UPPER_OFFSET	0x50 /**< Temp Upper Alarm Register */
+#define XADCPS_ATR_VCCINT_UPPER_OFFSET	0x51 /**< VCCINT Upper Alarm Reg */
+#define XADCPS_ATR_VCCAUX_UPPER_OFFSET	0x52 /**< VCCAUX Upper Alarm Reg */
+#define XADCPS_ATR_OT_UPPER_OFFSET	0x53 /**< Over Temp Upper Alarm Reg */
+#define XADCPS_ATR_TEMP_LOWER_OFFSET	0x54 /**< Temp Lower Alarm Register */
+#define XADCPS_ATR_VCCINT_LOWER_OFFSET	0x55 /**< VCCINT Lower Alarm Reg */
+#define XADCPS_ATR_VCCAUX_LOWER_OFFSET	0x56 /**< VCCAUX Lower Alarm Reg */
+#define XADCPS_ATR_OT_LOWER_OFFSET	0x57 /**< Over Temp Lower Alarm Reg */
+#define XADCPS_ATR_VBRAM_UPPER_OFFSET	0x58 /**< VBRAM Upper Alarm, 7 series */
+#define XADCPS_ATR_VCCPINT_UPPER_OFFSET	0x59 /**< VCCPINT Upper Alarm, Zynq */
+#define XADCPS_ATR_VCCPAUX_UPPER_OFFSET	0x5A /**< VCCPAUX Upper Alarm, Zynq */
+#define XADCPS_ATR_VCCPDRO_UPPER_OFFSET	0x5B /**< VCCPDRO Upper Alarm, Zynq */
+#define XADCPS_ATR_VBRAM_LOWER_OFFSET	0x5C /**< VRBAM Lower Alarm, 7 Series */
+#define XADCPS_ATR_VCCPINT_LOWER_OFFSET	0x5D /**< VCCPINT Lower Alarm, Zynq */
+#define XADCPS_ATR_VCCPAUX_LOWER_OFFSET	0x5E /**< VCCPAUX Lower Alarm, Zynq */
+#define XADCPS_ATR_VCCPDRO_LOWER_OFFSET	0x5F /**< VCCPDRO Lower Alarm, Zynq */
+
+/* Undefined 0x60 to 0x7F */
+
+/*@}*/
+
+
+
+/**
+ * @name Configuration Register 0 (CFR0) mask(s)
+ * @{
+ */
+#define XADCPS_CFR0_CAL_AVG_MASK	0x8000 /**< Averaging enable Mask */
+#define XADCPS_CFR0_AVG_VALID_MASK	0x3000 /**< Averaging bit Mask */
+#define XADCPS_CFR0_AVG1_MASK		0x0000 /**< No Averaging */
+#define XADCPS_CFR0_AVG16_MASK		0x1000 /**< Average 16 samples */
+#define XADCPS_CFR0_AVG64_MASK	 	0x2000 /**< Average 64 samples */
+#define XADCPS_CFR0_AVG256_MASK 	0x3000 /**< Average 256 samples */
+#define XADCPS_CFR0_AVG_SHIFT	 	12     /**< Averaging bits shift */
+#define XADCPS_CFR0_MUX_MASK	 	0x0800 /**< External Mask Enable */
+#define XADCPS_CFR0_DU_MASK	 	0x0400 /**< Bipolar/Unipolar mode */
+#define XADCPS_CFR0_EC_MASK	 	0x0200 /**< Event driven/
+						 *  Continuous mode selection
+						 */
+#define XADCPS_CFR0_ACQ_MASK	 	0x0100 /**< Add acquisition by 6 ADCCLK */
+#define XADCPS_CFR0_CHANNEL_MASK	0x001F /**< Channel number bit Mask */
+
+/*@}*/
+
+/**
+ * @name Configuration Register 1 (CFR1) mask(s)
+ * @{
+ */
+#define XADCPS_CFR1_SEQ_VALID_MASK	  0xF000 /**< Sequence bit Mask */
+#define XADCPS_CFR1_SEQ_SAFEMODE_MASK	  0x0000 /**< Default Safe Mode */
+#define XADCPS_CFR1_SEQ_ONEPASS_MASK	  0x1000 /**< Onepass through Seq */
+#define XADCPS_CFR1_SEQ_CONTINPASS_MASK	     0x2000 /**< Continuous Cycling Seq */
+#define XADCPS_CFR1_SEQ_SINGCHAN_MASK	     0x3000 /**< Single channel - No Seq */
+#define XADCPS_CFR1_SEQ_SIMUL_SAMPLING_MASK  0x4000 /**< Simulataneous Sampling Mask */
+#define XADCPS_CFR1_SEQ_INDEPENDENT_MASK  0x8000 /**< Independent Mode */
+#define XADCPS_CFR1_SEQ_SHIFT		  12     /**< Sequence bit shift */
+#define XADCPS_CFR1_ALM_VCCPDRO_MASK	  0x0800 /**< Alm 6 - VCCPDRO, Zynq  */
+#define XADCPS_CFR1_ALM_VCCPAUX_MASK	  0x0400 /**< Alm 5 - VCCPAUX, Zynq */
+#define XADCPS_CFR1_ALM_VCCPINT_MASK	  0x0200 /**< Alm 4 - VCCPINT, Zynq */
+#define XADCPS_CFR1_ALM_VBRAM_MASK	  0x0100 /**< Alm 3 - VBRAM, 7 series */
+#define XADCPS_CFR1_CAL_VALID_MASK	  0x00F0 /**< Valid Calibration Mask */
+#define XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK  0x0080 /**< Calibration 3 -Power
+							Supply Gain/Offset
+							Enable */
+#define XADCPS_CFR1_CAL_PS_OFFSET_MASK	  0x0040 /**< Calibration 2 -Power
+							Supply Offset Enable */
+#define XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x0020 /**< Calibration 1 -ADC Gain
+							Offset Enable */
+#define XADCPS_CFR1_CAL_ADC_OFFSET_MASK	 0x0010 /**< Calibration 0 -ADC Offset
+							Enable */
+#define XADCPS_CFR1_CAL_DISABLE_MASK	0x0000 /**< No Calibration */
+#define XADCPS_CFR1_ALM_ALL_MASK	0x0F0F /**< Mask for all alarms */
+#define XADCPS_CFR1_ALM_VCCAUX_MASK	0x0008 /**< Alarm 2 - VCCAUX Enable */
+#define XADCPS_CFR1_ALM_VCCINT_MASK	0x0004 /**< Alarm 1 - VCCINT Enable */
+#define XADCPS_CFR1_ALM_TEMP_MASK	0x0002 /**< Alarm 0 - Temperature */
+#define XADCPS_CFR1_OT_MASK		0x0001 /**< Over Temperature Enable */
+
+/*@}*/
+
+/**
+ * @name Configuration Register 2 (CFR2) mask(s)
+ * @{
+ */
+#define XADCPS_CFR2_CD_VALID_MASK	0xFF00  /**
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a ssb    12/22/11 First release based on the XPS/AXI xadc driver
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xadcps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+
+/****************************************************************************/
+/**
+*
+* This function enables the specified interrupts in the device.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Mask is the bit-mask of the interrupts to be enabled.
+*		Bit positions of 1 will be enabled. Bit positions of 0 will
+*		keep the previous setting. This mask is formed by OR'ing
+*		XADCPS_INTX_* bits defined in xadcps_hw.h.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Disable the specified interrupts in the IPIER.
+	 */
+	RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XADCPS_INT_MASK_OFFSET);
+	RegValue &= ~(Mask & XADCPS_INTX_ALL_MASK);
+	XAdcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XADCPS_INT_MASK_OFFSET,
+			  	RegValue);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function disables the specified interrupts in the device.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Mask is the bit-mask of the interrupts to be disabled.
+*		Bit positions of 1 will be disabled. Bit positions of 0 will
+*		keep the previous setting. This mask is formed by OR'ing
+*		XADCPS_INTX_* bits defined in xadcps_hw.h.
+*
+* @return	None.
+*
+* @note		None
+*
+*****************************************************************************/
+void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Enable the specified interrupts in the IPIER.
+	 */
+	RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XADCPS_INT_MASK_OFFSET);
+	RegValue |= (Mask & XADCPS_INTX_ALL_MASK);
+	XAdcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XADCPS_INT_MASK_OFFSET,
+			  	RegValue);
+}
+/****************************************************************************/
+/**
+*
+* This function returns the enabled interrupts read from the Interrupt Mask
+* Register (IPIER). Use the XADCPS_IPIXR_* constants defined in xadcps_hw.h to
+* interpret the returned value.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	A 32-bit value representing the contents of the I.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Return the value read from the Interrupt Enable Register.
+	 */
+	return (~ XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XADCPS_INT_MASK_OFFSET) & XADCPS_INTX_ALL_MASK);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the interrupt status read from Interrupt Status
+* Register(IPISR). Use the XADCPS_IPIXR_* constants defined in xadcps_hw.h
+* to interpret the returned value.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	A 32-bit value representing the contents of the IPISR.
+*
+* @note		The device must be configured at hardware build time to include
+*		interrupt component for this function to work.
+*
+*****************************************************************************/
+u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Return the value read from the Interrupt Status register.
+	 */
+	return XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XADCPS_INT_STS_OFFSET) & XADCPS_INTX_ALL_MASK;
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears the specified interrupts in the Interrupt Status
+* Register (IPISR).
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Mask is the bit-mask of the interrupts to be cleared.
+*		Bit positions of 1 will be cleared. Bit positions of 0 will not
+* 		change the previous interrupt status. This mask is formed by
+* 		OR'ing XADCPS_IPIXR_* bits which are defined in xadcps_hw.h.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Clear the specified interrupts in the Interrupt Status register.
+	 */
+	RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XADCPS_INT_STS_OFFSET);
+	RegValue &= (Mask & XADCPS_INTX_ALL_MASK);
+	XAdcPs_WriteReg(InstancePtr->Config.BaseAddress, XADCPS_INT_STS_OFFSET,
+			  RegValue);
+
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_0/src/xadcps_selftest.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_0/src/xadcps_selftest.c
new file mode 100644
index 000000000..9a6d97e57
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_0/src/xadcps_selftest.c
@@ -0,0 +1,147 @@
+/******************************************************************************
+*
+* (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xadcps_selftest.c
+*
+* This file contains a diagnostic self test function for the XAdcPs driver.
+* The self test function does a simple read/write test of the Alarm Threshold
+* Register.
+*
+* See xadcps.h for more information.
+*
+* @note	None.
+*
+* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a ssb    12/22/11 First release based on the XPS/AXI xadc driver
+*
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xadcps.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constant defines the test value to be written
+ * to the Alarm Threshold Register
+ */
+#define XADCPS_ATR_TEST_VALUE 		0x55
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Run a self-test on the driver/device. The test
+*	- Resets the device,
+*	- Writes a value into the Alarm Threshold register and reads it back
+*	for comparison.
+*	- Resets the device again.
+*
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+*		- XST_SUCCESS if the value read from the Alarm Threshold
+*		register is the same as the value written.
+*		- XST_FAILURE Otherwise
+*
+* @note		This is a destructive test in that resets of the device are
+*		performed. Refer to the device specification for the
+*		device status after the reset operation.
+*
+******************************************************************************/
+int XAdcPs_SelfTest(XAdcPs *InstancePtr)
+{
+	int Status;
+	u32 RegValue;
+
+	/*
+	 * Assert the argument
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+	/*
+	 * Reset the device to get it back to its default state
+	 */
+	XAdcPs_Reset(InstancePtr);
+
+	/*
+	 * Write a value into the Alarm Threshold registers, read it back, and
+	 * do the comparison
+	 */
+	XAdcPs_SetAlarmThreshold(InstancePtr, XADCPS_ATR_VCCINT_UPPER,
+				  XADCPS_ATR_TEST_VALUE);
+	RegValue = XAdcPs_GetAlarmThreshold(InstancePtr, XADCPS_ATR_VCCINT_UPPER);
+
+	if (RegValue == XADCPS_ATR_TEST_VALUE) {
+		Status = XST_SUCCESS;
+	} else {
+		Status = XST_FAILURE;
+	}
+
+	/*
+	 * Reset the device again to its default state.
+	 */
+	XAdcPs_Reset(InstancePtr);
+	/*
+	 * Return the test result.
+	 */
+	return Status;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_0/src/xadcps_sinit.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_0/src/xadcps_sinit.c
new file mode 100644
index 000000000..3ba9409a2
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_0/src/xadcps_sinit.c
@@ -0,0 +1,109 @@
+/******************************************************************************
+*
+* (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xadcps_sinit.c
+*
+* This file contains the implementation of the XAdcPs driver's static
+* initialization functionality.
+*
+* @note	None.
+*
+* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a ssb    12/22/11 First release based on the XPS/AXI XADC driver
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xadcps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XAdcPs_Config XAdcPs_ConfigTable[];
+
+/*****************************************************************************/
+/**
+*
+* This function looks up the device configuration based on the unique device ID.
+* The table XAdcPs_ConfigTable contains the configuration info for each device
+* in the system.
+*
+* @param	DeviceId contains the ID of the device for which the
+*		device configuration pointer is to be returned.
+*
+* @return
+*		- A pointer to the configuration found.
+*		- NULL if the specified device ID was not found.
+*
+* @note		None.
+*
+******************************************************************************/
+XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId)
+{
+	XAdcPs_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index=0; Index < 1; Index++) {
+		if (XAdcPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XAdcPs_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return CfgPtr;
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/system.mss b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/system.mss
new file mode 100644
index 000000000..ddba8e7e3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/system.mss
@@ -0,0 +1,239 @@
+
+ PARAMETER NAME = C:\E\Dev\workspaces\XilinxSDK\FreeRTOS_Demo\RTOSDemo_bsp\system.mss
+
+ PARAMETER VERSION = 2.2.0
+
+
+BEGIN OS
+ PARAMETER OS_NAME = standalone
+ PARAMETER OS_VER = 4.1
+ PARAMETER PROC_INSTANCE = ps7_cortexa9_0
+ PARAMETER stdin = ps7_uart_1
+ PARAMETER stdout = ps7_uart_1
+END
+
+
+BEGIN PROCESSOR
+ PARAMETER DRIVER_NAME = cpu_cortexa9
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_cortexa9_0
+END
+
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_afi_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_afi_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_afi_2
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_afi_3
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = canps
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_can_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_coresight_comp_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_ddr_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_ddrc_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = devcfg
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = ps7_dev_cfg_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = dmaps
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_dma_ns
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = dmaps
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_dma_s
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = emacps
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_ethernet_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_globaltimer_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = gpiops
+ PARAMETER DRIVER_VER = 2.1
+ PARAMETER HW_INSTANCE = ps7_gpio_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_gpv_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = iicps
+ PARAMETER DRIVER_VER = 2.1
+ PARAMETER HW_INSTANCE = ps7_i2c_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_intc_dist_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_iop_bus_config_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_l2cachec_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_ocmc_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_pl310_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_pmu_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = qspips
+ PARAMETER DRIVER_VER = 3.0
+ PARAMETER HW_INSTANCE = ps7_qspi_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_qspi_linear_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_ram_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_ram_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_scuc_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = scugic
+ PARAMETER DRIVER_VER = 2.1
+ PARAMETER HW_INSTANCE = ps7_scugic_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = scutimer
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_scutimer_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = scuwdt
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_scuwdt_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = sdps
+ PARAMETER DRIVER_VER = 2.1
+ PARAMETER HW_INSTANCE = ps7_sd_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_slcr_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = ttcps
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_ttc_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = uartps
+ PARAMETER DRIVER_VER = 2.1
+ PARAMETER HW_INSTANCE = ps7_uart_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = usbps
+ PARAMETER DRIVER_VER = 2.1
+ PARAMETER HW_INSTANCE = ps7_usb_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = xadcps
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = ps7_xadc_0
+END
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/.project b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/.project
new file mode 100644
index 000000000..67c4c6107
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/.project
@@ -0,0 +1,12 @@
+
+
+	ZC702_hw_platform
+	Created by SDK v2014.2
+	
+	
+	
+	
+	
+		com.xilinx.sdk.hw.HwProject
+	
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init.c
new file mode 100644
index 000000000..97a729459
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init.c
@@ -0,0 +1,12955 @@
+/******************************************************************************
+*
+* (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init.c
+*
+* This file is automatically generated 
+*
+*****************************************************************************/
+
+#include "ps7_init.h"
+
+unsigned long ps7_pll_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x5
+    // .. ==> 0XF8000140[25:20] = 0x00000005U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00500000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. 
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. 
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. 
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF800015C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF800015C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800015C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xe
+    // .. ==> 0XF800015C[13:8] = 0x0000000EU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000E00U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF800015C[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // .. 
+    EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U),
+    // .. CAN0_MUX = 0x0
+    // .. ==> 0XF8000160[5:0] = 0x00000000U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000000U
+    // .. CAN0_REF_SEL = 0x0
+    // .. ==> 0XF8000160[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. CAN1_MUX = 0x0
+    // .. ==> 0XF8000160[21:16] = 0x00000000U
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
+    // .. CAN1_REF_SEL = 0x0
+    // .. ==> 0XF8000160[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. 
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000170[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000180[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000190[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. 
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[16:16] = 0x00000001U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reserved_reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1b
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
+    // .. .. reg_ddrc_t_rfc_min = 0x56
+    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x10
+    // .. .. ==> 0XF8006018[15:10] = 0x00000010U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00004000U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x14
+    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x4
+    // .. .. ==> 0XF8006020[7:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x27087290U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x1d
+    // .. .. ==> 0XF800612C[9:0] = 0x0000001DU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001DU
+    // .. .. reg_phy_gatelvl_init_ratio = 0xf2
+    // .. .. ==> 0XF800612C[19:10] = 0x000000F2U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003C800U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x12
+    // .. .. ==> 0XF8006130[9:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000012U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xd8
+    // .. .. ==> 0XF8006130[19:10] = 0x000000D8U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00036000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0xc
+    // .. .. ==> 0XF8006134[9:0] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000000CU
+    // .. .. reg_phy_gatelvl_init_ratio = 0xde
+    // .. .. ==> 0XF8006134[19:10] = 0x000000DEU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00037800U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x21
+    // .. .. ==> 0XF8006138[9:0] = 0x00000021U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000021U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xee
+    // .. .. ==> 0XF8006138[19:10] = 0x000000EEU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003B800U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d
+    // .. .. ==> 0XF8006154[9:0] = 0x0000009DU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009DU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x92
+    // .. .. ==> 0XF8006158[9:0] = 0x00000092U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000092U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c
+    // .. .. ==> 0XF800615C[9:0] = 0x0000008CU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000008CU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1
+    // .. .. ==> 0XF8006160[9:0] = 0x000000A1U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A1U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x147
+    // .. .. ==> 0XF8006168[10:0] = 0x00000147U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000147U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x12d
+    // .. .. ==> 0XF800616C[10:0] = 0x0000012DU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000012DU
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x133
+    // .. .. ==> 0XF8006170[10:0] = 0x00000133U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000133U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x143
+    // .. .. ==> 0XF8006174[10:0] = 0x00000143U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000143U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xdd
+    // .. .. ==> 0XF800617C[9:0] = 0x000000DDU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DDU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xd2
+    // .. .. ==> 0XF8006180[9:0] = 0x000000D2U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000D2U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xcc
+    // .. .. ==> 0XF8006184[9:0] = 0x000000CCU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000CCU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xe1
+    // .. .. ==> 0XF8006188[9:0] = 0x000000E1U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E1U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U),
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. VREF_EN = 0x1
+    // .. ==> 0XF8000B00[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x0
+    // .. ==> 0XF8000B00[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B00, 0x00000071U ,0x00000001U),
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. reserved_SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. reserved_VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. reserved_REFIO_TEST = 0x3
+    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. reserved_REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reserved_VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reserved_VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reserved_VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reserved_INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reserved_TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. reserved_TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reserved_INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000700[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000700[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000704[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000708[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800070C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000710[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000714[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000718[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800071C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000720[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000724[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000728[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800072C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000730[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000734[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000738[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800073C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800073C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000740[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000740[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000744[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000744[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000748[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000748[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800074C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF800074C[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. 
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000750[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000750[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000754[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000754[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000758[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800075C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000760[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000764[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000768[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800076C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 1
+    // .. ==> 0XF80007B8[7:5] = 0x00000001U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 1
+    // .. ==> 0XF80007BC[7:5] = 0x00000001U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007C8[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007CC[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 15
+    // .. ==> 0XF8000830[5:0] = 0x0000000FU
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000000FU
+    // .. SDIO0_CD_SEL = 0
+    // .. ==> 0XF8000830[21:16] = 0x00000000U
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: TRACE CURRENT PORT SIZE
+    // .. FINISH: TRACE CURRENT PORT SIZE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // .. 
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x3e
+    // .. ==> 0XE0001018[15:0] = 0x0000003EU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
+    // .. 
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. 
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. DIRECTION_0 = 0x2880
+    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: DIR MODE BANK 1
+    // .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. OP_ENABLE_0 = 0x2880
+    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. DIRECTION_0 = 0x2880
+    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: DIR MODE BANK 1
+    // .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. OP_ENABLE_0 = 0x2880
+    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U),
+    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. DIRECTION_0 = 0x2880
+    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
+    // .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. START: OUTPUT ENABLE
+    // .. .. .. OP_ENABLE_0 = 0x2880
+    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
+    // .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. START: OUTPUT ENABLE
+    // .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U),
+    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. FINISH: I2C RESET
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_LVL_INP_EN_0 = 1
+    // .. ==> 0XF8000900[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. USER_LVL_OUT_EN_0 = 1
+    // .. ==> 0XF8000900[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USER_LVL_INP_EN_1 = 1
+    // .. ==> 0XF8000900[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. USER_LVL_OUT_EN_1 = 1
+    // .. ==> 0XF8000900[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. reserved_FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. reserved_FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_3_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_pll_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x5
+    // .. ==> 0XF8000140[25:20] = 0x00000005U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00500000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. 
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. 
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. 
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF800015C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF800015C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800015C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xe
+    // .. ==> 0XF800015C[13:8] = 0x0000000EU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000E00U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF800015C[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // .. 
+    EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U),
+    // .. CAN0_MUX = 0x0
+    // .. ==> 0XF8000160[5:0] = 0x00000000U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000000U
+    // .. CAN0_REF_SEL = 0x0
+    // .. ==> 0XF8000160[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. CAN1_MUX = 0x0
+    // .. ==> 0XF8000160[21:16] = 0x00000000U
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
+    // .. CAN1_REF_SEL = 0x0
+    // .. ==> 0XF8000160[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. 
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000170[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000180[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000190[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. 
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[16:16] = 0x00000001U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1b
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
+    // .. .. reg_ddrc_t_rfc_min = 0x56
+    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x10
+    // .. .. ==> 0XF8006018[15:10] = 0x00000010U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00004000U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x14
+    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x4
+    // .. .. ==> 0XF8006020[7:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x1d
+    // .. .. ==> 0XF800612C[9:0] = 0x0000001DU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001DU
+    // .. .. reg_phy_gatelvl_init_ratio = 0xf2
+    // .. .. ==> 0XF800612C[19:10] = 0x000000F2U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003C800U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x12
+    // .. .. ==> 0XF8006130[9:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000012U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xd8
+    // .. .. ==> 0XF8006130[19:10] = 0x000000D8U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00036000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0xc
+    // .. .. ==> 0XF8006134[9:0] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000000CU
+    // .. .. reg_phy_gatelvl_init_ratio = 0xde
+    // .. .. ==> 0XF8006134[19:10] = 0x000000DEU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00037800U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x21
+    // .. .. ==> 0XF8006138[9:0] = 0x00000021U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000021U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xee
+    // .. .. ==> 0XF8006138[19:10] = 0x000000EEU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003B800U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d
+    // .. .. ==> 0XF8006154[9:0] = 0x0000009DU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009DU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x92
+    // .. .. ==> 0XF8006158[9:0] = 0x00000092U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000092U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c
+    // .. .. ==> 0XF800615C[9:0] = 0x0000008CU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000008CU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1
+    // .. .. ==> 0XF8006160[9:0] = 0x000000A1U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A1U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x147
+    // .. .. ==> 0XF8006168[10:0] = 0x00000147U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000147U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x12d
+    // .. .. ==> 0XF800616C[10:0] = 0x0000012DU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000012DU
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x133
+    // .. .. ==> 0XF8006170[10:0] = 0x00000133U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000133U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x143
+    // .. .. ==> 0XF8006174[10:0] = 0x00000143U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000143U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xdd
+    // .. .. ==> 0XF800617C[9:0] = 0x000000DDU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DDU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xd2
+    // .. .. ==> 0XF8006180[9:0] = 0x000000D2U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000D2U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xcc
+    // .. .. ==> 0XF8006184[9:0] = 0x000000CCU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000CCU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xe1
+    // .. .. ==> 0XF8006188[9:0] = 0x000000E1U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E1U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. VREF_EN = 0x1
+    // .. ==> 0XF8000B00[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. CLK_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. SRSTN_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_TEST = 0x3
+    // .. ==> 0XF8000B6C[11:10] = 0x00000003U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000C00U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000700[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000700[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000704[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000708[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800070C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000710[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000714[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000718[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800071C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000720[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000724[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000728[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800072C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000730[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000734[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000738[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800073C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800073C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000740[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000740[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000744[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000744[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000748[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000748[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800074C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF800074C[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. 
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000750[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000750[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000754[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000754[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000758[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800075C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000760[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000764[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000768[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800076C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 1
+    // .. ==> 0XF80007B8[7:5] = 0x00000001U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 1
+    // .. ==> 0XF80007BC[7:5] = 0x00000001U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007C8[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007CC[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 15
+    // .. ==> 0XF8000830[5:0] = 0x0000000FU
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000000FU
+    // .. SDIO0_CD_SEL = 0
+    // .. ==> 0XF8000830[21:16] = 0x00000000U
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: TRACE CURRENT PORT SIZE
+    // .. FINISH: TRACE CURRENT PORT SIZE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // .. 
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x3e
+    // .. ==> 0XE0001018[15:0] = 0x0000003EU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
+    // .. 
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. IRMODE = 0x0
+    // .. ==> 0XE0001004[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. UCLKEN = 0x0
+    // .. ==> 0XE0001004[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. 
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. DIRECTION_0 = 0x2880
+    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: DIR MODE BANK 1
+    // .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. OP_ENABLE_0 = 0x2880
+    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. DIRECTION_0 = 0x2880
+    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: DIR MODE BANK 1
+    // .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. OP_ENABLE_0 = 0x2880
+    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U),
+    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. DIRECTION_0 = 0x2880
+    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
+    // .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. START: OUTPUT ENABLE
+    // .. .. .. OP_ENABLE_0 = 0x2880
+    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
+    // .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. START: OUTPUT ENABLE
+    // .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U),
+    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. FINISH: I2C RESET
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // .. 
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_2_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_pll_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000110[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x28
+    // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00028000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000200U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0xc
+    // .. .. ==> 0XF8000118[7:4] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x000000C0U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x145
+    // .. .. ==> 0XF8000118[21:12] = 0x00000145U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00145000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x1e
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0001E000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x8
+    // .. ==> 0XF8000140[13:8] = 0x00000008U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000800U
+    // .. DIVISOR1 = 0x5
+    // .. ==> 0XF8000140[25:20] = 0x00000005U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00500000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF800014C[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. 
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF8000150[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF8000150[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000150[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. 
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x14
+    // .. ==> 0XF8000154[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. 
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U),
+    // .. CLKACT0 = 0x1
+    // .. ==> 0XF800015C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. CLKACT1 = 0x0
+    // .. ==> 0XF800015C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800015C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0xe
+    // .. ==> 0XF800015C[13:8] = 0x0000000EU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000E00U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF800015C[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // .. 
+    EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U),
+    // .. CAN0_MUX = 0x0
+    // .. ==> 0XF8000160[5:0] = 0x00000000U
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x00000000U
+    // .. CAN0_REF_SEL = 0x0
+    // .. ==> 0XF8000160[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. CAN1_MUX = 0x0
+    // .. ==> 0XF8000160[21:16] = 0x00000000U
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
+    // .. CAN1_REF_SEL = 0x0
+    // .. ==> 0XF8000160[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000168[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000168[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x5
+    // .. ==> 0XF8000168[13:8] = 0x00000005U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000500U
+    // .. 
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000170[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000170[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000170[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000180[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000180[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000180[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000190[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF8000190[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000190[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U),
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR0 = 0x14
+    // .. ==> 0XF80001A0[13:8] = 0x00000014U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. 
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U),
+    // .. CLK_621_TRUE = 0x1
+    // .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. DMA_CPU_2XCLKACT = 0x1
+    // .. ==> 0XF800012C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. USB0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USB1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. GEM0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[6:6] = 0x00000001U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. GEM1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. SDI0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[10:10] = 0x00000001U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000400U
+    // .. SDI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. SPI0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. SPI1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[15:15] = 0x00000000U
+    // ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. CAN0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[16:16] = 0x00000001U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. CAN1_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. I2C0_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[18:18] = 0x00000001U
+    // ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. I2C1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. UART0_CPU_1XCLKACT = 0x0
+    // .. ==> 0XF800012C[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. UART1_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[21:21] = 0x00000001U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. GPIO_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[22:22] = 0x00000001U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[23:23] = 0x00000001U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. SMC_CPU_1XCLKACT = 0x1
+    // .. ==> 0XF800012C[24:24] = 0x00000001U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1b
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001BU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001BU
+    // .. .. reg_ddrc_t_rfc_min = 0x56
+    // .. .. ==> 0XF8006014[13:6] = 0x00000056U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00001580U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x10
+    // .. .. ==> 0XF8006018[15:10] = 0x00000010U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00004000U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x14
+    // .. .. ==> 0XF8006018[26:22] = 0x00000014U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x05000000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x4
+    // .. .. ==> 0XF8006020[7:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x1d
+    // .. .. ==> 0XF800612C[9:0] = 0x0000001DU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000001DU
+    // .. .. reg_phy_gatelvl_init_ratio = 0xf2
+    // .. .. ==> 0XF800612C[19:10] = 0x000000F2U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003C800U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x12
+    // .. .. ==> 0XF8006130[9:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000012U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xd8
+    // .. .. ==> 0XF8006130[19:10] = 0x000000D8U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00036000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0xc
+    // .. .. ==> 0XF8006134[9:0] = 0x0000000CU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000000CU
+    // .. .. reg_phy_gatelvl_init_ratio = 0xde
+    // .. .. ==> 0XF8006134[19:10] = 0x000000DEU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00037800U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x21
+    // .. .. ==> 0XF8006138[9:0] = 0x00000021U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000021U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xee
+    // .. .. ==> 0XF8006138[19:10] = 0x000000EEU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0003B800U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d
+    // .. .. ==> 0XF8006154[9:0] = 0x0000009DU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000009DU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x92
+    // .. .. ==> 0XF8006158[9:0] = 0x00000092U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000092U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c
+    // .. .. ==> 0XF800615C[9:0] = 0x0000008CU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000008CU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1
+    // .. .. ==> 0XF8006160[9:0] = 0x000000A1U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000A1U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x147
+    // .. .. ==> 0XF8006168[10:0] = 0x00000147U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000147U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x12d
+    // .. .. ==> 0XF800616C[10:0] = 0x0000012DU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000012DU
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x133
+    // .. .. ==> 0XF8006170[10:0] = 0x00000133U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000133U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x143
+    // .. .. ==> 0XF8006174[10:0] = 0x00000143U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000143U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xdd
+    // .. .. ==> 0XF800617C[9:0] = 0x000000DDU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000DDU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xd2
+    // .. .. ==> 0XF8006180[9:0] = 0x000000D2U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000D2U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xcc
+    // .. .. ==> 0XF8006184[9:0] = 0x000000CCU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000CCU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xe1
+    // .. .. ==> 0XF8006188[9:0] = 0x000000E1U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000E1U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. VREF_EN = 0x1
+    // .. ==> 0XF8000B00[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. CLK_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. SRSTN_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B00[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U),
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000700[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000700[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000700[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000704[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000704[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000708[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800070C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000710[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000714[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000718[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800071C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000720[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000724[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000724[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000728[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000728[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000728[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800072C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800072C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800072C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000730[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000730[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000730[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000734[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000734[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000734[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000738[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000738[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF8000738[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800073C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800073C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF800073C[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000740[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000740[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000744[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000744[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000748[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000748[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800074C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF800074C[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. 
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000750[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000750[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000754[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 1
+    // .. ==> 0XF8000754[13:13] = 0x00000001U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000758[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800075C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000760[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000764[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF8000768[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 4
+    // .. ==> 0XF800076C[11:9] = 0x00000004U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000800U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007A8[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007AC[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007B4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007B8[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 1
+    // .. ==> 0XF80007B8[7:5] = 0x00000001U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007B8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 1
+    // .. ==> 0XF80007BC[7:5] = 0x00000001U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000020U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007BC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007C8[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007C8[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 2
+    // .. ==> 0XF80007CC[7:5] = 0x00000002U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000040U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 1
+    // .. ==> 0XF80007CC[12:12] = 0x00000001U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00001000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO0_WP_SEL = 15
+    // .. ==> 0XF8000830[5:0] = 0x0000000FU
+    // ..     ==> MASK : 0x0000003FU    VAL : 0x0000000FU
+    // .. SDIO0_CD_SEL = 0
+    // .. ==> 0XF8000830[21:16] = 0x00000000U
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: TRACE CURRENT PORT SIZE
+    // .. FINISH: TRACE CURRENT PORT SIZE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // .. 
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x3e
+    // .. ==> 0XE0001018[15:0] = 0x0000003EU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
+    // .. 
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. IRMODE = 0x0
+    // .. ==> 0XE0001004[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. UCLKEN = 0x0
+    // .. ==> 0XE0001004[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. 
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. DIRECTION_0 = 0x2880
+    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: DIR MODE BANK 1
+    // .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. OP_ENABLE_0 = 0x2880
+    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. DIRECTION_0 = 0x2880
+    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: DIR MODE BANK 1
+    // .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. OP_ENABLE_0 = 0x2880
+    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U),
+    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. MASK_0_LSW = 0xf7ff
+    // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU
+    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xF7FF0000U
+    // .. .. .. DATA_0_LSW = 0x800
+    // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U
+    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000800U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U),
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. DIRECTION_0 = 0x2880
+    // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U
+    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U),
+    // .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. START: OUTPUT ENABLE
+    // .. .. .. OP_ENABLE_0 = 0x2880
+    // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U
+    // .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00002880U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U),
+    // .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. START: OUTPUT ENABLE
+    // .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U),
+    // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. MASK_0_LSW = 0xdfff
+    // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU
+    // .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xDFFF0000U
+    // .. .. .. DATA_0_LSW = 0x2000
+    // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U
+    // .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00002000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U),
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. FINISH: I2C RESET
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // .. 
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_1_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+#include "xil_io.h"
+#define PS7_MASK_POLL_TIME 100000000
+
+char*
+getPS7MessageInfo(unsigned key) {
+
+  char* err_msg = "";
+  switch (key) {
+    case PS7_INIT_SUCCESS:                  err_msg = "PS7 initialization successful"; break;
+    case PS7_INIT_CORRUPT:                  err_msg = "PS7 init Data Corrupted"; break;
+    case PS7_INIT_TIMEOUT:                  err_msg = "PS7 init mask poll timeout"; break;
+    case PS7_POLL_FAILED_DDR_INIT:          err_msg = "Mask Poll failed for DDR Init"; break;
+    case PS7_POLL_FAILED_DMA:               err_msg = "Mask Poll failed for PLL Init"; break;
+    case PS7_POLL_FAILED_PLL:               err_msg = "Mask Poll failed for DMA done bit"; break;
+    default:                                err_msg = "Undefined error status"; break;
+  }
+  
+  return err_msg;  
+}
+
+unsigned long
+ps7GetSiliconVersion () {
+  // Read PS version from MCTRL register [31:28]
+  unsigned long mask = 0xF0000000;
+  unsigned long *addr = (unsigned long*) 0XF8007080;    
+  unsigned long ps_version = (*addr & mask) >> 28;
+  return ps_version;
+}
+
+void mask_write (unsigned long add , unsigned long  mask, unsigned long val ) {
+        unsigned long *addr = (unsigned long*) add;
+        *addr = ( val & mask ) | ( *addr & ~mask);
+        //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
+}
+
+
+int mask_poll(unsigned long add , unsigned long mask ) {
+        volatile unsigned long *addr = (volatile unsigned long*) add;
+        int i = 0;
+        while (!(*addr & mask)) {
+          if (i == PS7_MASK_POLL_TIME) {
+            return -1;
+          }
+          i++;
+        }
+     return 1;   
+        //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
+}
+
+unsigned long mask_read(unsigned long add , unsigned long mask ) {
+        unsigned long *addr = (unsigned long*) add;
+        unsigned long val = (*addr & mask);
+        //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
+        return val;
+}
+
+
+
+int
+ps7_config(unsigned long * ps7_config_init) 
+{
+    unsigned long *ptr = ps7_config_init;
+
+    unsigned long  opcode;            // current instruction ..
+    unsigned long  args[16];           // no opcode has so many args ...
+    int  numargs;           // number of arguments of this instruction
+    int  j;                 // general purpose index
+
+    volatile unsigned long *addr;         // some variable to make code readable
+    unsigned long  val,mask;              // some variable to make code readable
+
+    int finish = -1 ;           // loop while this is negative !
+    int i = 0;                  // Timeout variable
+    
+    while( finish < 0 ) {
+        numargs = ptr[0] & 0xF;
+        opcode = ptr[0] >> 4;
+
+        for( j = 0 ; j < numargs ; j ++ ) 
+            args[j] = ptr[j+1];
+        ptr += numargs + 1;
+        
+        
+        switch ( opcode ) {
+            
+        case OPCODE_EXIT:
+            finish = PS7_INIT_SUCCESS;
+            break;
+            
+        case OPCODE_CLEAR:
+            addr = (unsigned long*) args[0];
+            *addr = 0;
+            break;
+
+        case OPCODE_WRITE:
+            addr = (unsigned long*) args[0];
+            val = args[1];
+            *addr = val;
+            break;
+
+        case OPCODE_MASKWRITE:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            val = args[2];
+            *addr = ( val & mask ) | ( *addr & ~mask);
+            break;
+
+        case OPCODE_MASKPOLL:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            i = 0;
+            while (!(*addr & mask)) {
+                if (i == PS7_MASK_POLL_TIME) {
+                    finish = PS7_INIT_TIMEOUT;
+                    break;
+                }
+                i++;
+            }
+            break;
+        case OPCODE_MASKDELAY:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            int delay = get_number_of_cycles_for_delay(mask);
+            perf_reset_and_start_timer(); 
+            while ((*addr < delay)) {
+            }
+            break;
+        default:
+            finish = PS7_INIT_CORRUPT;
+            break;
+        }
+    }
+    return finish;
+}
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int
+ps7_post_config() 
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_post_config_1_0);   
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_post_config_2_0);   
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_post_config_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_debug() 
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_debug_1_0);   
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_debug_2_0);   
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_debug_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_init() 
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret;
+  //int pcw_ver = 0;
+
+  if (si_ver == PCW_SILICON_VERSION_1) {
+    ps7_mio_init_data = ps7_mio_init_data_1_0;
+    ps7_pll_init_data = ps7_pll_init_data_1_0;
+    ps7_clock_init_data = ps7_clock_init_data_1_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+    //pcw_ver = 1;
+
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+    ps7_mio_init_data = ps7_mio_init_data_2_0;
+    ps7_pll_init_data = ps7_pll_init_data_2_0;
+    ps7_clock_init_data = ps7_clock_init_data_2_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+    //pcw_ver = 2;
+
+  } else {
+    ps7_mio_init_data = ps7_mio_init_data_3_0;
+    ps7_pll_init_data = ps7_pll_init_data_3_0;
+    ps7_clock_init_data = ps7_clock_init_data_3_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+    //pcw_ver = 3;
+  }
+
+  // MIO init
+  ret = ps7_config (ps7_mio_init_data);  
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // PLL init
+  ret = ps7_config (ps7_pll_init_data); 
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // Clock init
+  ret = ps7_config (ps7_clock_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // DDR init
+  ret = ps7_config (ps7_ddr_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+
+
+  // Peripherals init
+  ret = ps7_config (ps7_peripherals_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+  //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
+  return PS7_INIT_SUCCESS;
+}
+
+
+
+
+/* For delay calculation using global timer */
+
+/* start timer */
+ void perf_start_clock(void)
+{
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
+						      (1 << 3) | // Auto-increment
+						      (0 << 8) // Pre-scale
+	); 
+}
+
+/* stop timer and reset timer count regs */
+ void perf_reset_clock(void)
+{
+	perf_disable_clock();
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
+}
+
+/* Compute mask for given delay in miliseconds*/
+int get_number_of_cycles_for_delay(unsigned int delay) 
+{
+  // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
+  return (APU_FREQ*delay/(2*1000));
+   
+}
+
+/* stop timer */
+ void perf_disable_clock(void)
+{
+	*(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
+}
+
+void perf_reset_and_start_timer() 
+{
+  	    perf_reset_clock();
+	    perf_start_clock();
+}
+
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init.h
new file mode 100644
index 000000000..fa817360a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init.h
@@ -0,0 +1,150 @@
+
+/******************************************************************************
+*
+* (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+*
+* This file contains confidential and proprietary information of Xilinx, Inc.
+* and is protected under U.S. and international copyright and other
+* intellectual property laws.
+*
+* DISCLAIMER
+* This disclaimer is not a license and does not grant any rights to the
+* materials distributed herewith. Except as otherwise provided in a valid
+* license issued to you by Xilinx, and to the maximum extent permitted by
+* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
+* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
+* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
+* and (2) Xilinx shall not be liable (whether in contract or tort, including
+* negligence, or under any other theory of liability) for any loss or damage
+* of any kind or nature related to, arising under or in connection with these
+* materials, including for any direct, or any indirect, special, incidental,
+* or consequential loss or damage (including loss of data, profits, goodwill,
+* or any type of loss or damage suffered as a result of any action brought by
+* a third party) even if such damage or loss was reasonably foreseeable or
+* Xilinx had been advised of the possibility of the same.
+*
+* CRITICAL APPLICATIONS
+* Xilinx products are not designed or intended to be fail-safe, or for use in
+* any application requiring fail-safe performance, such as life-support or
+* safety devices or systems, Class III medical devices, nuclear facilities,
+* applications related to the deployment of airbags, or any other applications
+* that could lead to death, personal injury, or severe property or
+* environmental damage (individually and collectively, "Critical
+* Applications"). Customer assumes the sole risk and liability of any use of
+* Xilinx products in Critical Applications, subject only to applicable laws
+* and regulations governing limitations on product liability.
+*
+* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
+* AT ALL TIMES.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init.h
+*
+* This file can be included in FSBL code
+* to get prototype of ps7_init() function
+* and error codes
+*
+*****************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//typedef unsigned int  u32;
+
+
+/** do we need to make this name more unique ? **/
+//extern u32 ps7_init_data[];
+extern unsigned long  * ps7_ddr_init_data;
+extern unsigned long  * ps7_mio_init_data;
+extern unsigned long  * ps7_pll_init_data;
+extern unsigned long  * ps7_clock_init_data;
+extern unsigned long  * ps7_peripherals_init_data;
+
+
+
+#define OPCODE_EXIT       0U
+#define OPCODE_CLEAR      1U
+#define OPCODE_WRITE      2U
+#define OPCODE_MASKWRITE  3U
+#define OPCODE_MASKPOLL   4U
+#define OPCODE_MASKDELAY  5U
+#define NEW_PS7_ERR_CODE 1
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT()                   ( (OPCODE_EXIT      << 4 ) | 0 )
+#define EMIT_CLEAR(addr)              ( (OPCODE_CLEAR     << 4 ) | 1 ) , addr
+#define EMIT_WRITE(addr,val)          ( (OPCODE_WRITE     << 4 ) | 2 ) , addr, val
+#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
+#define EMIT_MASKPOLL(addr,mask)      ( (OPCODE_MASKPOLL  << 4 ) | 2 ) , addr, mask
+#define EMIT_MASKDELAY(addr,mask)      ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
+
+/* Returns codes  of PS7_Init */
+#define PS7_INIT_SUCCESS   (0)    // 0 is success in good old C
+#define PS7_INIT_CORRUPT   (1)    // 1 the data is corrupted, and slcr reg are in corrupted state now
+#define PS7_INIT_TIMEOUT   (2)    // 2 when a poll operation timed out
+#define PS7_POLL_FAILED_DDR_INIT (3)    // 3 when a poll operation timed out for ddr init
+#define PS7_POLL_FAILED_DMA      (4)    // 4 when a poll operation timed out for dma done bit
+#define PS7_POLL_FAILED_PLL      (5)    // 5 when a poll operation timed out for pll sequence init
+
+
+/* Silicon Versions */
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
+#define PS7_POST_CONFIG
+
+/* Freq of all peripherals */
+
+#define APU_FREQ  666666687
+#define DDR_FREQ  533333374
+#define DCI_FREQ  10158731
+#define QSPI_FREQ  200000000
+#define SMC_FREQ  10000000
+#define ENET0_FREQ  25000000
+#define ENET1_FREQ  10000000
+#define USB0_FREQ  60000000
+#define USB1_FREQ  60000000
+#define SDIO_FREQ  50000000
+#define UART_FREQ  50000000
+#define SPI_FREQ  10000000
+#define I2C_FREQ  111111115
+#define WDT_FREQ  111111115
+#define TTC_FREQ  50000000
+#define CAN_FREQ  23809523
+#define PCAP_FREQ  200000000
+#define TPIU_FREQ  200000000
+#define FPGA0_FREQ  50000000
+#define FPGA1_FREQ  50000000
+#define FPGA2_FREQ  50000000
+#define FPGA3_FREQ  50000000
+
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
+
+int ps7_config( unsigned long*);
+int ps7_init();
+int ps7_post_config();
+int ps7_debug();
+char* getPS7MessageInfo(unsigned key);
+
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer(); 
+int get_number_of_cycles_for_delay(unsigned int delay); 
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init.html b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init.html
new file mode 100644
index 000000000..be0471cc9
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init.html
@@ -0,0 +1,147311 @@
+
+
+
+
+Zynq PS configuration detail
+
+
+
+

+

+
+
  • 
+
    Zynq PS Register Summary Viewer
+
    
+
    • 
+    
+
    
+
    
+
    
+
+
    Zynq PS7 Summary Report
+
    
+    
+
    User Configurations
+
    
+
    
+
+
    MIO Configurations
+
    
+    
+
    
+
+
    CLK Configurations
+
    
+    
+
    
+
+
    DDR Configurations
+
    
+    
+
    
+
+
    SMC Configurations
+
    
+    
+
    
+
    
+
    Select Version:
+
+
    
+
    
+
    Zynq Register View
+
    
+
    
+
+
    MIO Registers
+
    
+    
+
+
    PLL Registers
+
    
+    
+
+
    Clock Registers
+
    
+    
+
+
    DDR Registers
+
    
+    
+
+
    Peripherals Registers
+
    
+    
+
    
+
    This design is targeted for 7z020 board (part number: 7z020clg484-1)
+
+
    
+
    Zynq Design Summary
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Device
+
+7z020
+
    
+SpeedGrade
+
+-1
+
    
+Part
+
+7z020clg484-1
+
    
+Description
+
+Zynq PS Configuration Report with register details
+
    
+Vendor
+
+Xilinx
+
    
+
    MIO Table View
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+MIO Pin
+
+Peripheral
+
+Signal
+
+IO Type
+
+Speed
+
+Pullup
+
+Direction
+
    
+MIO 0
+
+SD 0
+
+cd
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+in
+
    
+MIO 1
+
+Quad SPI Flash
+
+qspi0_ss_b
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+out
+
    
+MIO 2
+
+Quad SPI Flash
+
+qspi0_io[0]
+
+LVCMOS 1.8V
+
+slow
+
+disabled
+
+inout
+
    
+MIO 3
+
+Quad SPI Flash
+
+qspi0_io[1]
+
+LVCMOS 1.8V
+
+slow
+
+disabled
+
+inout
+
    
+MIO 4
+
+Quad SPI Flash
+
+qspi0_io[2]
+
+LVCMOS 1.8V
+
+slow
+
+disabled
+
+inout
+
    
+MIO 5
+
+Quad SPI Flash
+
+qspi0_io[3]
+
+LVCMOS 1.8V
+
+slow
+
+disabled
+
+inout
+
    
+MIO 6
+
+Quad SPI Flash
+
+qspi0_sclk
+
+LVCMOS 1.8V
+
+slow
+
+disabled
+
+out
+
    
+MIO 7
+
+USB Reset
+
+reset
+
+LVCMOS 1.8V
+
+slow
+
+disabled
+
+out
+
    
+MIO 8
+
+Quad SPI Flash
+
+qspi_fbclk
+
+LVCMOS 1.8V
+
+slow
+
+disabled
+
+out
+
    
+MIO 9
+
+GPIO
+
+gpio[9]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 10
+
+GPIO
+
+gpio[10]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 11
+
+ENET Reset
+
+reset
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+out
+
    
+MIO 12
+
+GPIO
+
+gpio[12]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 13
+
+I2C Reset
+
+reset
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+out
+
    
+MIO 14
+
+GPIO
+
+gpio[14]
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 15
+
+SD 0
+
+wp
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+in
+
    
+MIO 16
+
+Enet 0
+
+tx_clk
+
+HSTL 1.8V
+
+slow
+
+disabled
+
+out
+
    
+MIO 17
+
+Enet 0
+
+txd[0]
+
+HSTL 1.8V
+
+slow
+
+disabled
+
+out
+
    
+MIO 18
+
+Enet 0
+
+txd[1]
+
+HSTL 1.8V
+
+slow
+
+disabled
+
+out
+
    
+MIO 19
+
+Enet 0
+
+txd[2]
+
+HSTL 1.8V
+
+slow
+
+disabled
+
+out
+
    
+MIO 20
+
+Enet 0
+
+txd[3]
+
+HSTL 1.8V
+
+slow
+
+disabled
+
+out
+
    
+MIO 21
+
+Enet 0
+
+tx_ctl
+
+HSTL 1.8V
+
+slow
+
+disabled
+
+out
+
    
+MIO 22
+
+Enet 0
+
+rx_clk
+
+HSTL 1.8V
+
+slow
+
+disabled
+
+in
+
    
+MIO 23
+
+Enet 0
+
+rxd[0]
+
+HSTL 1.8V
+
+slow
+
+disabled
+
+in
+
    
+MIO 24
+
+Enet 0
+
+rxd[1]
+
+HSTL 1.8V
+
+slow
+
+disabled
+
+in
+
    
+MIO 25
+
+Enet 0
+
+rxd[2]
+
+HSTL 1.8V
+
+slow
+
+disabled
+
+in
+
    
+MIO 26
+
+Enet 0
+
+rxd[3]
+
+HSTL 1.8V
+
+slow
+
+disabled
+
+in
+
    
+MIO 27
+
+Enet 0
+
+rx_ctl
+
+HSTL 1.8V
+
+slow
+
+disabled
+
+in
+
    
+MIO 28
+
+USB 0
+
+data[4]
+
+LVCMOS 1.8V
+
+slow
+
+disabled
+
+inout
+
    
+MIO 29
+
+USB 0
+
+dir
+
+LVCMOS 1.8V
+
+slow
+
+disabled
+
+in
+
    
+MIO 30
+
+USB 0
+
+stp
+
+LVCMOS 1.8V
+
+slow
+
+disabled
+
+out
+
    
+MIO 31
+
+USB 0
+
+nxt
+
+LVCMOS 1.8V
+
+slow
+
+disabled
+
+in
+
    
+MIO 32
+
+USB 0
+
+data[0]
+
+LVCMOS 1.8V
+
+slow
+
+disabled
+
+inout
+
    
+MIO 33
+
+USB 0
+
+data[1]
+
+LVCMOS 1.8V
+
+slow
+
+disabled
+
+inout
+
    
+MIO 34
+
+USB 0
+
+data[2]
+
+LVCMOS 1.8V
+
+slow
+
+disabled
+
+inout
+
    
+MIO 35
+
+USB 0
+
+data[3]
+
+LVCMOS 1.8V
+
+slow
+
+disabled
+
+inout
+
    
+MIO 36
+
+USB 0
+
+clk
+
+LVCMOS 1.8V
+
+slow
+
+disabled
+
+in
+
    
+MIO 37
+
+USB 0
+
+data[5]
+
+LVCMOS 1.8V
+
+slow
+
+disabled
+
+inout
+
    
+MIO 38
+
+USB 0
+
+data[6]
+
+LVCMOS 1.8V
+
+slow
+
+disabled
+
+inout
+
    
+MIO 39
+
+USB 0
+
+data[7]
+
+LVCMOS 1.8V
+
+slow
+
+disabled
+
+inout
+
    
+MIO 40
+
+SD 0
+
+clk
+
+LVCMOS 1.8V
+
+slow
+
+disabled
+
+inout
+
    
+MIO 41
+
+SD 0
+
+cmd
+
+LVCMOS 1.8V
+
+slow
+
+disabled
+
+inout
+
    
+MIO 42
+
+SD 0
+
+data[0]
+
+LVCMOS 1.8V
+
+slow
+
+disabled
+
+inout
+
    
+MIO 43
+
+SD 0
+
+data[1]
+
+LVCMOS 1.8V
+
+slow
+
+disabled
+
+inout
+
    
+MIO 44
+
+SD 0
+
+data[2]
+
+LVCMOS 1.8V
+
+slow
+
+disabled
+
+inout
+
    
+MIO 45
+
+SD 0
+
+data[3]
+
+LVCMOS 1.8V
+
+slow
+
+disabled
+
+inout
+
    
+MIO 46
+
+CAN 0
+
+rx
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+in
+
    
+MIO 47
+
+CAN 0
+
+tx
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+out
+
    
+MIO 48
+
+UART 1
+
+tx
+
+LVCMOS 1.8V
+
+slow
+
+disabled
+
+out
+
    
+MIO 49
+
+UART 1
+
+rx
+
+LVCMOS 1.8V
+
+slow
+
+disabled
+
+in
+
    
+MIO 50
+
+I2C 0
+
+scl
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 51
+
+I2C 0
+
+sda
+
+LVCMOS 1.8V
+
+slow
+
+enabled
+
+inout
+
    
+MIO 52
+
+Enet 0
+
+mdc
+
+LVCMOS 1.8V
+
+slow
+
+disabled
+
+out
+
    
+MIO 53
+
+Enet 0
+
+mdio
+
+LVCMOS 1.8V
+
+slow
+
+disabled
+
+inout
+
    
+
    DDR Memory information
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Parameter name
+
+Value
+
+Description
+
    
+Enable DDR
+
+1
+
+Enable DDR Controller of Zynq PS
+
    
+Enable DDR
+
+1
+
+Enable DDR Controller of Zynq PS
+
    
+Memory Part
+
+MT41J256M8 HX-15E
+
+
+
    
+DRAM bus width
+
+32 Bit
+
+Select the desired data width. Refer to the Thechnical Reference Manual(TRM) for a detailed list of supported DDR data widths
+
    
+ECC
+
+Disabled
+
+ECC is supported only for data width of 16-bit
+
    
+BURST Length (lppdr only)
+
+8
+
+Select the burst Length. It refers to the amount of data read/written after a read/write command is presented to the controller
+
    
+Internal Vref
+
+1
+
+
+
    
+Operating Frequency (MHz)
+
+533.333333
+
+Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade
+
    
+HIGH temperature
+
+Normal (0-85)
+
+Select the operating temparature
+
    
+DRAM IC bus width
+
+8 Bits
+
+Provide the width of the DRAM chip
+
    
+DRAM Device Capacity
+
+2048 MBits
+
+
+
    
+Speed Bin
+
+DDR3_1066F
+
+Provide the Speed Bin
+
    
+BANK Address Count
+
+3
+
+Defines the bank to which an active an ACTIVE, READ, WRITE, or Precharge Command is being applied
+
    
+ROW Address Count
+
+15
+
+Provide the Row address for ACTIVE commands
+
    
+COLUMN Address Count
+
+10
+
+Provide the Row address for READ/WRITE commands
+
    
+CAS Latency
+
+7
+
+Select the Column Access Strobe (CAS) Latency. It refers to the amount of time it takes for data to appear on the pins of the memory module
+
    
+CAS Write Latency
+
+6
+
+Select the CAS Write Latency
+
    
+RAS to CAS Delay
+
+7
+
+Provide the row address to column address delay time. tRCD is t he time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS)
+
    
+RECHARGE Time
+
+7
+
+Precharge Time (tRP) is the number of clock cycles needed o terminate acces s to an open row of memory, and open access to the next row
+
    
+tRC (ns )
+
+49.5
+
+Provide the Row cycle time tRC (ns)
+
    
+tRASmin ( ns )
+
+36.0
+
+tRASmin (ns) is the minimum number of clock cycles required between an Active command and issuing the Precharge command
+
    
+tFAW
+
+30.0
+
+It restricts the number of activates that can be done within a certain window of time
+
    
+ADDITIVE Latency
+
+0
+
+Provide the Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths
+
    
+Write levelling
+
+1
+
+
+
    
+Read gate
+
+1
+
+
+
    
+Read gate
+
+1
+
+
+
    
+DQS to Clock delay [0] (ns)
+
+0.217
+
+The daly difference of each DQS path delay subtracted from the clock path delay
+
    
+DQS to Clock delay [1] (ns)
+
+0.133
+
+The daly difference of each DQS path delay subtracted from the clock path delay
+
    
+DQS to Clock delay [2] (ns)
+
+0.089
+
+The daly difference of each DQS path delay subtracted from the clock path delay
+
    
+DQS to Clock delay [3] (ns)
+
+0.248
+
+The daly difference of each DQS path delay subtracted from the clock path delay
+
    
+Board delay [0] (ns)
+
+0.537
+
+The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N)
+
    
+Board delay [1] (ns)
+
+0.442
+
+The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N)
+
    
+Board delay [2] (ns)
+
+0.464
+
+The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N)
+
    
+Board delay [3] (ns)
+
+0.521
+
+The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N)
+
    
+
    PS Clocks information
    
+
    PS Reference Clock : 33.333333
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Peripheral
+
+PLL source
+
+Frequency (MHz)
+
    
+CPU 6x Freq (MHz)
+
+ARM PLL
+
+666.666687
+
    
+QSPI Flash Freq (MHz)
+
+IO PLL
+
+200.000000
+
    
+ENET0 Freq (MHz)
+
+IO PLL
+
+25.000000
+
    
+SDIO Freq (MHz)
+
+IO PLL
+
+50.000000
+
    
+UART Freq (MHz)
+
+IO PLL
+
+50.000000
+
    
+CAN Freq (MHz)
+
+IO PLL
+
+23.809523
+
    
+TTC0 CLK0 Freq (MHz)
+
+CPU_1X
+
+111.111115
+
    
+TTC0 CLK1 Freq (MHz)
+
+CPU_1X
+
+111.111115
+
    
+TTC0 CLK2 Freq (MHz)
+
+CPU_1X
+
+111.111115
+
    
+FPGA0 Freq (MHz)
+
+IO PLL
+
+50.000000
+
    
+FPGA1 Freq (MHz)
+
+IO PLL
+
+50.000000
+
    
+FPGA2 Freq (MHz)
+
+IO PLL
+
+50.000000
+
    
+FPGA3 Freq (MHz)
+
+IO PLL
+
+50.000000
+
    
+
    ps7_pll_init_data_3_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+ARM_PLL_CFG
+
+
+0XF8000110
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Configuration
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_CLK_CTRL
+
+
+0XF8000120
+
+32
+
+RW
+
+0x000000
+
+CPU Clock Control
+
    
+
+DDR_PLL_CFG
+
+
+0XF8000114
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Configuration
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_CLK_CTRL
+
+
+0XF8000124
+
+32
+
+RW
+
+0x000000
+
+DDR Clock Control
+
    
+
+IO_PLL_CFG
+
+
+0XF8000118
+
+32
+
+RW
+
+0x000000
+
+IO PLL Configuration
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_pll_init_data_3_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    PLL SLCR REGISTERS
    
+
    ARM PLL INIT
    
+
    Register ( slcr )ARM_PLL_CFG
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CFG
+
+0XF8000110
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RES
+
+7:4
+
+f0
+
+2
+
+20
+
+Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control
+
    
+PLL_CP
+
+11:8
+
+f00
+
+2
+
+200
+
+Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control
+
    
+LOCK_CNT
+
+21:12
+
+3ff000
+
+fa
+
+fa000
+
+Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before syaing locked.
+
    
+ARM_PLL_CFG@0XF8000110
+
+31:0
+
+3ffff0
+
+
+
+fa220
+
+ARM PLL Configuration
+
    
+
    
+
    UPDATE FB_DIV
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_FDIV
+
+18:12
+
+7f000
+
+28
+
+28000
+
+Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+7f000
+
+
+
+28000
+
+ARM PLL Control
+
    
+
    
+
    BY PASS PLL
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+1
+
+10
+
+ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+10
+
+
+
+10
+
+ARM PLL Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+1
+
+1
+
+PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+1
+
+
+
+1
+
+ARM PLL Control
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+0
+
+0
+
+PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+1
+
+
+
+0
+
+ARM PLL Control
+
    
+
    
+
    CHECK PLL STATUS
    
+
    Register ( slcr )PLL_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PLL_STATUS
+
+0XF800010C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+ARM_PLL_LOCK
+
+0:0
+
+1
+
+1
+
+1
+
+ARM PLL lock status: 0: not locked, 1: locked
+
    
+PLL_STATUS@0XF800010C
+
+31:0
+
+1
+
+
+
+1
+
+tobe
+
    
+
    
+
    REMOVE PLL BY PASS
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+0
+
+0
+
+ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+10
+
+
+
+0
+
+ARM PLL Control
+
    
+
    
+
    Register ( slcr )ARM_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_CLK_CTRL
+
+0XF8000120
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select the source used to generate the CPU clock: 0x: ARM PLL 10: DDR PLL 11: IO PLL This field is reset by POR only.
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+2
+
+200
+
+Frequency divisor for the CPU clock source.
+
    
+CPU_6OR4XCLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+CPU_6x4x Clock control: 0: disable, 1: enable
+
    
+CPU_3OR2XCLKACT
+
+25:25
+
+2000000
+
+1
+
+2000000
+
+CPU_3x2x Clock control: 0: disable, 1: enable
+
    
+CPU_2XCLKACT
+
+26:26
+
+4000000
+
+1
+
+4000000
+
+CPU_2x Clock control: 0: disable, 1: enable
+
    
+CPU_1XCLKACT
+
+27:27
+
+8000000
+
+1
+
+8000000
+
+CPU_1x Clock control: 0: disable, 1: enable
+
    
+CPU_PERI_CLKACT
+
+28:28
+
+10000000
+
+1
+
+10000000
+
+Clock active: 0: Clock is disabled 1: Clock is enabled
+
    
+ARM_CLK_CTRL@0XF8000120
+
+31:0
+
+1f003f30
+
+
+
+1f000200
+
+CPU Clock Control
+
    
+
    
+
    DDR PLL INIT
    
+
    Register ( slcr )DDR_PLL_CFG
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CFG
+
+0XF8000114
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RES
+
+7:4
+
+f0
+
+2
+
+20
+
+Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control.
+
    
+PLL_CP
+
+11:8
+
+f00
+
+2
+
+200
+
+Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control.
+
    
+LOCK_CNT
+
+21:12
+
+3ff000
+
+12c
+
+12c000
+
+Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked.
+
    
+DDR_PLL_CFG@0XF8000114
+
+31:0
+
+3ffff0
+
+
+
+12c220
+
+DDR PLL Configuration
+
    
+
    
+
    UPDATE FB_DIV
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_FDIV
+
+18:12
+
+7f000
+
+20
+
+20000
+
+Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL.
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+7f000
+
+
+
+20000
+
+DDR PLL Control
+
    
+
    
+
    BY PASS PLL
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+1
+
+10
+
+DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping.
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+10
+
+
+
+10
+
+DDR PLL Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+1
+
+1
+
+PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+1
+
+
+
+1
+
+DDR PLL Control
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+0
+
+0
+
+PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+1
+
+
+
+0
+
+DDR PLL Control
+
    
+
    
+
    CHECK PLL STATUS
    
+
    Register ( slcr )PLL_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PLL_STATUS
+
+0XF800010C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DDR_PLL_LOCK
+
+1:1
+
+2
+
+1
+
+2
+
+DDR PLL lock status: 0: not locked, 1: locked
+
    
+PLL_STATUS@0XF800010C
+
+31:0
+
+2
+
+
+
+2
+
+tobe
+
    
+
    
+
    REMOVE PLL BY PASS
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+0
+
+0
+
+DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping.
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+10
+
+
+
+0
+
+DDR PLL Control
+
    
+
    
+
    Register ( slcr )DDR_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_CLK_CTRL
+
+0XF8000124
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DDR_3XCLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+DDR_3x Clock control: 0: disable, 1: enable
+
    
+DDR_2XCLKACT
+
+1:1
+
+2
+
+1
+
+2
+
+DDR_2x Clock control: 0: disable, 1: enable
+
    
+DDR_3XCLK_DIVISOR
+
+25:20
+
+3f00000
+
+2
+
+200000
+
+Frequency divisor for the ddr_3x clock
+
    
+DDR_2XCLK_DIVISOR
+
+31:26
+
+fc000000
+
+3
+
+c000000
+
+Frequency divisor for the ddr_2x clock
+
    
+DDR_CLK_CTRL@0XF8000124
+
+31:0
+
+fff00003
+
+
+
+c200003
+
+DDR Clock Control
+
    
+
    
+
    IO PLL INIT
    
+
    Register ( slcr )IO_PLL_CFG
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CFG
+
+0XF8000118
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RES
+
+7:4
+
+f0
+
+c
+
+c0
+
+Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control.
+
    
+PLL_CP
+
+11:8
+
+f00
+
+2
+
+200
+
+Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control.
+
    
+LOCK_CNT
+
+21:12
+
+3ff000
+
+145
+
+145000
+
+Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked.
+
    
+IO_PLL_CFG@0XF8000118
+
+31:0
+
+3ffff0
+
+
+
+1452c0
+
+IO PLL Configuration
+
    
+
    
+
    UPDATE FB_DIV
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_FDIV
+
+18:12
+
+7f000
+
+1e
+
+1e000
+
+Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for programming the PLL.
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+7f000
+
+
+
+1e000
+
+IO PLL Control
+
    
+
    
+
    BY PASS PLL
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+1
+
+10
+
+IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping.
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+10
+
+
+
+10
+
+IO PLL Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+1
+
+1
+
+PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+1
+
+
+
+1
+
+IO PLL Control
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+0
+
+0
+
+PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset)
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+1
+
+
+
+0
+
+IO PLL Control
+
    
+
    
+
    CHECK PLL STATUS
    
+
    Register ( slcr )PLL_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PLL_STATUS
+
+0XF800010C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IO_PLL_LOCK
+
+2:2
+
+4
+
+1
+
+4
+
+IO PLL lock status: 0: not locked, 1: locked
+
    
+PLL_STATUS@0XF800010C
+
+31:0
+
+4
+
+
+
+4
+
+tobe
+
    
+
    
+
    REMOVE PLL BY PASS
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+0
+
+0
+
+IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping.
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+10
+
+
+
+0
+
+IO PLL Control
+
    
+
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_clock_init_data_3_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+DCI_CLK_CTRL
+
+
+0XF8000128
+
+32
+
+RW
+
+0x000000
+
+DCI clock control
+
    
+
+GEM0_RCLK_CTRL
+
+
+0XF8000138
+
+32
+
+RW
+
+0x000000
+
+GigE 0 Rx Clock and Rx Signals Select
+
    
+
+GEM0_CLK_CTRL
+
+
+0XF8000140
+
+32
+
+RW
+
+0x000000
+
+GigE 0 Ref Clock Control
+
    
+
+LQSPI_CLK_CTRL
+
+
+0XF800014C
+
+32
+
+RW
+
+0x000000
+
+Quad SPI Ref Clock Control
+
    
+
+SDIO_CLK_CTRL
+
+
+0XF8000150
+
+32
+
+RW
+
+0x000000
+
+SDIO Ref Clock Control
+
    
+
+UART_CLK_CTRL
+
+
+0XF8000154
+
+32
+
+RW
+
+0x000000
+
+UART Ref Clock Control
+
    
+
+CAN_CLK_CTRL
+
+
+0XF800015C
+
+32
+
+RW
+
+0x000000
+
+CAN Ref Clock Control
+
    
+
+CAN_MIOCLK_CTRL
+
+
+0XF8000160
+
+32
+
+RW
+
+0x000000
+
+CAN MIO Clock Control
+
    
+
+PCAP_CLK_CTRL
+
+
+0XF8000168
+
+32
+
+RW
+
+0x000000
+
+PCAP Clock Control
+
    
+
+FPGA0_CLK_CTRL
+
+
+0XF8000170
+
+32
+
+RW
+
+0x000000
+
+PL Clock 0 Output control
+
    
+
+FPGA1_CLK_CTRL
+
+
+0XF8000180
+
+32
+
+RW
+
+0x000000
+
+PL Clock 1 Output control
+
    
+
+FPGA2_CLK_CTRL
+
+
+0XF8000190
+
+32
+
+RW
+
+0x000000
+
+PL Clock 2 output control
+
    
+
+FPGA3_CLK_CTRL
+
+
+0XF80001A0
+
+32
+
+RW
+
+0x000000
+
+PL Clock 3 output control
+
    
+
+CLK_621_TRUE
+
+
+0XF80001C4
+
+32
+
+RW
+
+0x000000
+
+CPU Clock Ratio Mode select
+
    
+
+APER_CLK_CTRL
+
+
+0XF800012C
+
+32
+
+RW
+
+0x000000
+
+AMBA Peripheral Clock Control
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_clock_init_data_3_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    CLOCK CONTROL SLCR REGISTERS
    
+
    Register ( slcr )DCI_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DCI_CLK_CTRL
+
+0XF8000128
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+DCI clock control - 0: disable, 1: enable
+
    
+DIVISOR0
+
+13:8
+
+3f00
+
+23
+
+2300
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+3
+
+300000
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider
+
    
+DCI_CLK_CTRL@0XF8000128
+
+31:0
+
+3f03f01
+
+
+
+302301
+
+DCI clock control
+
    
+
    
+
    Register ( slcr )GEM0_RCLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+GEM0_RCLK_CTRL
+
+0XF8000138
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Ethernet Controler 0 Rx Clock control 0: disable, 1: enable
+
    
+SRCSEL
+
+4:4
+
+10
+
+0
+
+0
+
+Select the source of the Rx clock, control and data signals: 0: MIO 1: EMIO
+
    
+GEM0_RCLK_CTRL@0XF8000138
+
+31:0
+
+11
+
+
+
+1
+
+GigE 0 Rx Clock and Rx Signals Select
+
    
+
    
+
    Register ( slcr )GEM0_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+GEM0_CLK_CTRL
+
+0XF8000140
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Ethernet Controller 0 Reference Clock control 0: disable, 1: enable
+
    
+SRCSEL
+
+6:4
+
+70
+
+0
+
+0
+
+Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+8
+
+800
+
+First divisor for Ethernet controller 0 source clock.
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+5
+
+500000
+
+Second divisor for Ethernet controller 0 source clock.
+
    
+GEM0_CLK_CTRL@0XF8000140
+
+31:0
+
+3f03f71
+
+
+
+500801
+
+GigE 0 Ref Clock Control
+
    
+
    
+
    Register ( slcr )LQSPI_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LQSPI_CLK_CTRL
+
+0XF800014C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Quad SPI Controller Reference Clock control 0: disable, 1: enable
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+5
+
+500
+
+Divisor for Quad SPI Controller source clock.
+
    
+LQSPI_CLK_CTRL@0XF800014C
+
+31:0
+
+3f31
+
+
+
+501
+
+Quad SPI Ref Clock Control
+
    
+
    
+
    Register ( slcr )SDIO_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SDIO_CLK_CTRL
+
+0XF8000150
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT0
+
+0:0
+
+1
+
+1
+
+1
+
+SDIO Controller 0 Clock control. 0: disable, 1: enable
+
    
+CLKACT1
+
+1:1
+
+2
+
+0
+
+0
+
+SDIO Controller 1 Clock control. 0: disable, 1: enable
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+14
+
+1400
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+SDIO_CLK_CTRL@0XF8000150
+
+31:0
+
+3f33
+
+
+
+1401
+
+SDIO Ref Clock Control
+
    
+
    
+
    Register ( slcr )UART_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+UART_CLK_CTRL
+
+0XF8000154
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT0
+
+0:0
+
+1
+
+0
+
+0
+
+UART 0 Reference clock control. 0: disable, 1: enable
+
    
+CLKACT1
+
+1:1
+
+2
+
+1
+
+2
+
+UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+14
+
+1400
+
+Divisor for UART Controller source clock.
+
    
+UART_CLK_CTRL@0XF8000154
+
+31:0
+
+3f33
+
+
+
+1402
+
+UART Ref Clock Control
+
    
+
    
+
    Register ( slcr )CAN_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CAN_CLK_CTRL
+
+0XF800015C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT0
+
+0:0
+
+1
+
+1
+
+1
+
+CAN 0 Reference Clock active: 0: Clock is disabled 1: Clock is enabled
+
    
+CLKACT1
+
+1:1
+
+2
+
+0
+
+0
+
+CAN 1 Reference Clock active: 0: Clock is disabled 1: Clock is enabled
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.
+
    
+DIVISOR0
+
+13:8
+
+3f00
+
+e
+
+e00
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+3
+
+300000
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider.
+
    
+CAN_CLK_CTRL@0XF800015C
+
+31:0
+
+3f03f33
+
+
+
+300e01
+
+CAN Ref Clock Control
+
    
+
    
+
    Register ( slcr )CAN_MIOCLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CAN_MIOCLK_CTRL
+
+0XF8000160
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CAN0_MUX
+
+5:0
+
+3f
+
+0
+
+0
+
+CAN 0 mux selection for MIO. Setting this to zero will select MIO[0] as the clock source. Only values 0-53 are valid.
+
    
+CAN0_REF_SEL
+
+6:6
+
+40
+
+0
+
+0
+
+CAN 0 Reference Clock selection: 0: From internal PLL 1: From MIO based on the next field
+
    
+CAN1_MUX
+
+21:16
+
+3f0000
+
+0
+
+0
+
+CAN 1 mux selection for MIO. Setting this to zero will select MIO[0] as the clock source. Only values 0-53 are valid.
+
    
+CAN1_REF_SEL
+
+22:22
+
+400000
+
+0
+
+0
+
+CAN 1 Reference Clock selection: 0: From internal PLL. 1: From MIO based on the next field
+
    
+CAN_MIOCLK_CTRL@0XF8000160
+
+31:0
+
+7f007f
+
+
+
+0
+
+CAN MIO Clock Control
+
    
+
    
+
    Register ( slcr )PCAP_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PCAP_CLK_CTRL
+
+0XF8000168
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Clock active: 0: Clock is disabled 1: Clock is enabled
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+5
+
+500
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+PCAP_CLK_CTRL@0XF8000168
+
+31:0
+
+3f31
+
+
+
+501
+
+PCAP Clock Control
+
    
+
    
+
    Register ( slcr )FPGA0_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+FPGA0_CLK_CTRL
+
+0XF8000170
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.
+
    
+DIVISOR0
+
+13:8
+
+3f00
+
+14
+
+1400
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider.
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+1
+
+100000
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide
+
    
+FPGA0_CLK_CTRL@0XF8000170
+
+31:0
+
+3f03f30
+
+
+
+101400
+
+PL Clock 0 Output control
+
    
+
    
+
    Register ( slcr )FPGA1_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+FPGA1_CLK_CTRL
+
+0XF8000180
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.
+
    
+DIVISOR0
+
+13:8
+
+3f00
+
+14
+
+1400
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider.
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+1
+
+100000
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide
+
    
+FPGA1_CLK_CTRL@0XF8000180
+
+31:0
+
+3f03f30
+
+
+
+101400
+
+PL Clock 1 Output control
+
    
+
    
+
    Register ( slcr )FPGA2_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+FPGA2_CLK_CTRL
+
+0XF8000190
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.
+
    
+DIVISOR0
+
+13:8
+
+3f00
+
+14
+
+1400
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider.
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+1
+
+100000
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide
+
    
+FPGA2_CLK_CTRL@0XF8000190
+
+31:0
+
+3f03f30
+
+
+
+101400
+
+PL Clock 2 output control
+
    
+
    
+
    Register ( slcr )FPGA3_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+FPGA3_CLK_CTRL
+
+0XF80001A0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.
+
    
+DIVISOR0
+
+13:8
+
+3f00
+
+14
+
+1400
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider.
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+1
+
+100000
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide
+
    
+FPGA3_CLK_CTRL@0XF80001A0
+
+31:0
+
+3f03f30
+
+
+
+101400
+
+PL Clock 3 output control
+
    
+
    
+
    Register ( slcr )CLK_621_TRUE
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CLK_621_TRUE
+
+0XF80001C4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLK_621_TRUE
+
+0:0
+
+1
+
+1
+
+1
+
+Select the CPU clock ratio: (When this register changes, no access are allowed to OCM.) 0: 4:2:1 1: 6:2:1
+
    
+CLK_621_TRUE@0XF80001C4
+
+31:0
+
+1
+
+
+
+1
+
+CPU Clock Ratio Mode select
+
    
+
    
+
    Register ( slcr )APER_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+APER_CLK_CTRL
+
+0XF800012C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DMA_CPU_2XCLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+DMA controller AMBA Clock control 0: disable, 1: enable
+
    
+USB0_CPU_1XCLKACT
+
+2:2
+
+4
+
+1
+
+4
+
+USB controller 0 AMBA Clock control 0: disable, 1: enable
+
    
+USB1_CPU_1XCLKACT
+
+3:3
+
+8
+
+1
+
+8
+
+USB controller 1 AMBA Clock control 0: disable, 1: enable
+
    
+GEM0_CPU_1XCLKACT
+
+6:6
+
+40
+
+1
+
+40
+
+Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable
+
    
+GEM1_CPU_1XCLKACT
+
+7:7
+
+80
+
+0
+
+0
+
+Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable
+
    
+SDI0_CPU_1XCLKACT
+
+10:10
+
+400
+
+1
+
+400
+
+SDIO controller 0 AMBA Clock 0: disable, 1: enable
+
    
+SDI1_CPU_1XCLKACT
+
+11:11
+
+800
+
+0
+
+0
+
+SDIO controller 1 AMBA Clock control 0: disable, 1: enable
+
    
+SPI0_CPU_1XCLKACT
+
+14:14
+
+4000
+
+0
+
+0
+
+SPI 0 AMBA Clock control 0: disable, 1: enable
+
    
+SPI1_CPU_1XCLKACT
+
+15:15
+
+8000
+
+0
+
+0
+
+SPI 1 AMBA Clock control 0: disable, 1: enable
+
    
+CAN0_CPU_1XCLKACT
+
+16:16
+
+10000
+
+1
+
+10000
+
+CAN 0 AMBA Clock control 0: disable, 1: enable
+
    
+CAN1_CPU_1XCLKACT
+
+17:17
+
+20000
+
+0
+
+0
+
+CAN 1 AMBA Clock control 0: disable, 1: enable
+
    
+I2C0_CPU_1XCLKACT
+
+18:18
+
+40000
+
+1
+
+40000
+
+I2C 0 AMBA Clock control 0: disable, 1: enable
+
    
+I2C1_CPU_1XCLKACT
+
+19:19
+
+80000
+
+1
+
+80000
+
+I2C 1 AMBA Clock control 0: disable, 1: enable
+
    
+UART0_CPU_1XCLKACT
+
+20:20
+
+100000
+
+0
+
+0
+
+UART 0 AMBA Clock control 0: disable, 1: enable
+
    
+UART1_CPU_1XCLKACT
+
+21:21
+
+200000
+
+1
+
+200000
+
+UART 1 AMBA Clock control 0: disable, 1: enable
+
    
+GPIO_CPU_1XCLKACT
+
+22:22
+
+400000
+
+1
+
+400000
+
+GPIO AMBA Clock control 0: disable, 1: enable
+
    
+LQSPI_CPU_1XCLKACT
+
+23:23
+
+800000
+
+1
+
+800000
+
+Quad SPI AMBA Clock control 0: disable, 1: enable
+
    
+SMC_CPU_1XCLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+SMC AMBA Clock control 0: disable, 1: enable
+
    
+APER_CLK_CTRL@0XF800012C
+
+31:0
+
+1ffcccd
+
+
+
+1ed044d
+
+AMBA Peripheral Clock Control
+
    
+
    
+
    THIS SHOULD BE BLANK
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_ddr_init_data_3_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+ddrc_ctrl
+
+
+0XF8006000
+
+32
+
+RW
+
+0x000000
+
+DDRC Control
+
    
+
+Two_rank_cfg
+
+
+0XF8006004
+
+32
+
+RW
+
+0x000000
+
+Two Rank Configuration
+
    
+
+HPR_reg
+
+
+0XF8006008
+
+32
+
+RW
+
+0x000000
+
+HPR Queue control
+
    
+
+LPR_reg
+
+
+0XF800600C
+
+32
+
+RW
+
+0x000000
+
+LPR Queue control
+
    
+
+WR_reg
+
+
+0XF8006010
+
+32
+
+RW
+
+0x000000
+
+WR Queue control
+
    
+
+DRAM_param_reg0
+
+
+0XF8006014
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters 0
+
    
+
+DRAM_param_reg1
+
+
+0XF8006018
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters 1
+
    
+
+DRAM_param_reg2
+
+
+0XF800601C
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters 2
+
    
+
+DRAM_param_reg3
+
+
+0XF8006020
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters 3
+
    
+
+DRAM_param_reg4
+
+
+0XF8006024
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters 4
+
    
+
+DRAM_init_param
+
+
+0XF8006028
+
+32
+
+RW
+
+0x000000
+
+DRAM Initialization Parameters
+
    
+
+DRAM_EMR_reg
+
+
+0XF800602C
+
+32
+
+RW
+
+0x000000
+
+DRAM EMR2, EMR3 access
+
    
+
+DRAM_EMR_MR_reg
+
+
+0XF8006030
+
+32
+
+RW
+
+0x000000
+
+DRAM EMR, MR access
+
    
+
+DRAM_burst8_rdwr
+
+
+0XF8006034
+
+32
+
+RW
+
+0x000000
+
+DRAM Burst 8 read/write
+
    
+
+DRAM_disable_DQ
+
+
+0XF8006038
+
+32
+
+RW
+
+0x000000
+
+DRAM Disable DQ
+
    
+
+DRAM_addr_map_bank
+
+
+0XF800603C
+
+32
+
+RW
+
+0x000000
+
+Row/Column address bits
+
    
+
+DRAM_addr_map_col
+
+
+0XF8006040
+
+32
+
+RW
+
+0x000000
+
+Column address bits
+
    
+
+DRAM_addr_map_row
+
+
+0XF8006044
+
+32
+
+RW
+
+0x000000
+
+Select DRAM row address bits
+
    
+
+DRAM_ODT_reg
+
+
+0XF8006048
+
+32
+
+RW
+
+0x000000
+
+DRAM ODT control
+
    
+
+phy_cmd_timeout_rddata_cpt
+
+
+0XF8006050
+
+32
+
+RW
+
+0x000000
+
+PHY command time out and read data capture FIFO
+
    
+
+DLL_calib
+
+
+0XF8006058
+
+32
+
+RW
+
+0x000000
+
+DLL calibration
+
    
+
+ODT_delay_hold
+
+
+0XF800605C
+
+32
+
+RW
+
+0x000000
+
+ODT delay and ODT hold
+
    
+
+ctrl_reg1
+
+
+0XF8006060
+
+32
+
+RW
+
+0x000000
+
+Controller 1
+
    
+
+ctrl_reg2
+
+
+0XF8006064
+
+32
+
+RW
+
+0x000000
+
+Controller 2
+
    
+
+ctrl_reg3
+
+
+0XF8006068
+
+32
+
+RW
+
+0x000000
+
+Controller 3
+
    
+
+ctrl_reg4
+
+
+0XF800606C
+
+32
+
+RW
+
+0x000000
+
+Controller 4
+
    
+
+ctrl_reg5
+
+
+0XF8006078
+
+32
+
+RW
+
+0x000000
+
+Controller register 5
+
    
+
+ctrl_reg6
+
+
+0XF800607C
+
+32
+
+RW
+
+0x000000
+
+Controller register 6
+
    
+
+CHE_T_ZQ
+
+
+0XF80060A4
+
+32
+
+RW
+
+0x000000
+
+ZQ parameters
+
    
+
+CHE_T_ZQ_Short_Interval_Reg
+
+
+0XF80060A8
+
+32
+
+RW
+
+0x000000
+
+Misc parameters
+
    
+
+deep_pwrdwn_reg
+
+
+0XF80060AC
+
+32
+
+RW
+
+0x000000
+
+Deep powerdown (LPDDR2)
+
    
+
+reg_2c
+
+
+0XF80060B0
+
+32
+
+RW
+
+0x000000
+
+Training control
+
    
+
+reg_2d
+
+
+0XF80060B4
+
+32
+
+RW
+
+0x000000
+
+Misc Debug
+
    
+
+dfi_timing
+
+
+0XF80060B8
+
+32
+
+RW
+
+0x000000
+
+DFI timing
+
    
+
+CHE_ECC_CONTROL_REG_OFFSET
+
+
+0XF80060C4
+
+32
+
+RW
+
+0x000000
+
+ECC error clear
+
    
+
+CHE_ECC_CONTROL_REG_OFFSET
+
+
+0XF80060C4
+
+32
+
+RW
+
+0x000000
+
+ECC error clear
+
    
+
+CHE_CORR_ECC_LOG_REG_OFFSET
+
+
+0XF80060C8
+
+32
+
+RW
+
+0x000000
+
+ECC error correction
+
    
+
+CHE_UNCORR_ECC_LOG_REG_OFFSET
+
+
+0XF80060DC
+
+32
+
+RW
+
+0x000000
+
+ECC unrecoverable error status
+
    
+
+CHE_ECC_STATS_REG_OFFSET
+
+
+0XF80060F0
+
+32
+
+RW
+
+0x000000
+
+ECC error count
+
    
+
+ECC_scrub
+
+
+0XF80060F4
+
+32
+
+RW
+
+0x000000
+
+ECC mode/scrub
+
    
+
+phy_rcvr_enable
+
+
+0XF8006114
+
+32
+
+RW
+
+0x000000
+
+Phy receiver enable register
+
    
+
+PHY_Config
+
+
+0XF8006118
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 0.
+
    
+
+PHY_Config
+
+
+0XF800611C
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 0.
+
    
+
+PHY_Config
+
+
+0XF8006120
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 0.
+
    
+
+PHY_Config
+
+
+0XF8006124
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 0.
+
    
+
+phy_init_ratio
+
+
+0XF800612C
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 0.
+
    
+
+phy_init_ratio
+
+
+0XF8006130
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 0.
+
    
+
+phy_init_ratio
+
+
+0XF8006134
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 0.
+
    
+
+phy_init_ratio
+
+
+0XF8006138
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 0.
+
    
+
+phy_rd_dqs_cfg
+
+
+0XF8006140
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 0.
+
    
+
+phy_rd_dqs_cfg
+
+
+0XF8006144
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 0.
+
    
+
+phy_rd_dqs_cfg
+
+
+0XF8006148
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 0.
+
    
+
+phy_rd_dqs_cfg
+
+
+0XF800614C
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 0.
+
    
+
+phy_wr_dqs_cfg
+
+
+0XF8006154
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 0.
+
    
+
+phy_wr_dqs_cfg
+
+
+0XF8006158
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 0.
+
    
+
+phy_wr_dqs_cfg
+
+
+0XF800615C
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 0.
+
    
+
+phy_wr_dqs_cfg
+
+
+0XF8006160
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 0.
+
    
+
+phy_we_cfg
+
+
+0XF8006168
+
+32
+
+RW
+
+0x000000
+
+PHY FIFO write enable configuration for data slice 0.
+
    
+
+phy_we_cfg
+
+
+0XF800616C
+
+32
+
+RW
+
+0x000000
+
+PHY FIFO write enable configuration for data slice 0.
+
    
+
+phy_we_cfg
+
+
+0XF8006170
+
+32
+
+RW
+
+0x000000
+
+PHY FIFO write enable configuration for data slice 0.
+
    
+
+phy_we_cfg
+
+
+0XF8006174
+
+32
+
+RW
+
+0x000000
+
+PHY FIFO write enable configuration for data slice 0.
+
    
+
+wr_data_slv
+
+
+0XF800617C
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio config for data slice 0.
+
    
+
+wr_data_slv
+
+
+0XF8006180
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio config for data slice 0.
+
    
+
+wr_data_slv
+
+
+0XF8006184
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio config for data slice 0.
+
    
+
+wr_data_slv
+
+
+0XF8006188
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio config for data slice 0.
+
    
+
+reg_64
+
+
+0XF8006190
+
+32
+
+RW
+
+0x000000
+
+Training control 2
+
    
+
+reg_65
+
+
+0XF8006194
+
+32
+
+RW
+
+0x000000
+
+Training control 3
+
    
+
+page_mask
+
+
+0XF8006204
+
+32
+
+RW
+
+0x000000
+
+Page mask
+
    
+
+axi_priority_wr_port
+
+
+0XF8006208
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 0.
+
    
+
+axi_priority_wr_port
+
+
+0XF800620C
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 0.
+
    
+
+axi_priority_wr_port
+
+
+0XF8006210
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 0.
+
    
+
+axi_priority_wr_port
+
+
+0XF8006214
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 0.
+
    
+
+axi_priority_rd_port
+
+
+0XF8006218
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 0.
+
    
+
+axi_priority_rd_port
+
+
+0XF800621C
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 0.
+
    
+
+axi_priority_rd_port
+
+
+0XF8006220
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 0.
+
    
+
+axi_priority_rd_port
+
+
+0XF8006224
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 0.
+
    
+
+lpddr_ctrl0
+
+
+0XF80062A8
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 0
+
    
+
+lpddr_ctrl1
+
+
+0XF80062AC
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 1
+
    
+
+lpddr_ctrl2
+
+
+0XF80062B0
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 2
+
    
+
+lpddr_ctrl3
+
+
+0XF80062B4
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 3
+
    
+
+ddrc_ctrl
+
+
+0XF8006000
+
+32
+
+RW
+
+0x000000
+
+DDRC Control
+
    
+
    
+
    ps7_ddr_init_data_3_0
    
+
+
+
+
+
+
+
+
+
+
    DDR INITIALIZATION
    
+
    LOCK DDR
    
+
    Register ( slcr )ddrc_ctrl
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ddrc_ctrl
+
+0XF8006000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_soft_rstb
+
+0:0
+
+1
+
+0
+
+0
+
+Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated.
+
    
+reg_ddrc_powerdown_en
+
+1:1
+
+2
+
+0
+
+0
+
+Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable
+
    
+reg_ddrc_data_bus_width
+
+3:2
+
+c
+
+0
+
+0
+
+DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved
+
    
+reg_ddrc_burst8_refresh
+
+6:4
+
+70
+
+0
+
+0
+
+Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh
+
    
+reg_ddrc_rdwr_idle_gap
+
+13:7
+
+3f80
+
+1
+
+80
+
+When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.
+
    
+reg_ddrc_dis_rd_bypass
+
+14:14
+
+4000
+
+0
+
+0
+
+Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits.
+
    
+reg_ddrc_dis_act_bypass
+
+15:15
+
+8000
+
+0
+
+0
+
+Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates.
+
    
+reg_ddrc_dis_auto_refresh
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.
+
    
+ddrc_ctrl@0XF8006000
+
+31:0
+
+1ffff
+
+
+
+80
+
+DDRC Control
+
    
+
    
+
    Register ( slcr )Two_rank_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Two_rank_cfg
+
+0XF8006004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_t_rfc_nom_x32
+
+11:0
+
+fff
+
+81
+
+81
+
+tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field.
+
    
+reserved_reg_ddrc_active_ranks
+
+13:12
+
+3000
+
+1
+
+1000
+
+Reserved. Do not modify.
+
    
+reg_ddrc_addrmap_cs_bit0
+
+18:14
+
+7c000
+
+0
+
+0
+
+Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0.
+
    
+Two_rank_cfg@0XF8006004
+
+31:0
+
+7ffff
+
+
+
+1081
+
+Two Rank Configuration
+
    
+
    
+
    Register ( slcr )HPR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+HPR_reg
+
+0XF8006008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_hpr_min_non_critical_x32
+
+10:0
+
+7ff
+
+f
+
+f
+
+Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks).
+
    
+reg_ddrc_hpr_max_starve_x32
+
+21:11
+
+3ff800
+
+f
+
+7800
+
+Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks
+
    
+reg_ddrc_hpr_xact_run_length
+
+25:22
+
+3c00000
+
+f
+
+3c00000
+
+Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available.
+
    
+HPR_reg@0XF8006008
+
+31:0
+
+3ffffff
+
+
+
+3c0780f
+
+HPR Queue control
+
    
+
    
+
    Register ( slcr )LPR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LPR_reg
+
+0XF800600C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_lpr_min_non_critical_x32
+
+10:0
+
+7ff
+
+1
+
+1
+
+Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks
+
    
+reg_ddrc_lpr_max_starve_x32
+
+21:11
+
+3ff800
+
+2
+
+1000
+
+Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks
+
    
+reg_ddrc_lpr_xact_run_length
+
+25:22
+
+3c00000
+
+8
+
+2000000
+
+Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available
+
    
+LPR_reg@0XF800600C
+
+31:0
+
+3ffffff
+
+
+
+2001001
+
+LPR Queue control
+
    
+
    
+
    Register ( slcr )WR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+WR_reg
+
+0XF8006010
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_w_min_non_critical_x32
+
+10:0
+
+7ff
+
+1
+
+1
+
+Number of clock cycles that the WR queue is guaranteed to be non-critical.
+
    
+reg_ddrc_w_xact_run_length
+
+14:11
+
+7800
+
+8
+
+4000
+
+Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available
+
    
+reg_ddrc_w_max_starve_x32
+
+25:15
+
+3ff8000
+
+2
+
+10000
+
+Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY.
+
    
+WR_reg@0XF8006010
+
+31:0
+
+3ffffff
+
+
+
+14001
+
+WR Queue control
+
    
+
    
+
    Register ( slcr )DRAM_param_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg0
+
+0XF8006014
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_t_rc
+
+5:0
+
+3f
+
+1b
+
+1b
+
+tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3.
+
    
+reg_ddrc_t_rfc_min
+
+13:6
+
+3fc0
+
+56
+
+1580
+
+tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field.
+
    
+reg_ddrc_post_selfref_gap_x32
+
+20:14
+
+1fc000
+
+10
+
+40000
+
+Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related
+
    
+DRAM_param_reg0@0XF8006014
+
+31:0
+
+1fffff
+
+
+
+4159b
+
+DRAM Parameters 0
+
    
+
    
+
    Register ( slcr )DRAM_param_reg1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg1
+
+0XF8006018
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_wr2pre
+
+4:0
+
+1f
+
+12
+
+12
+
+Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs.
+
    
+reg_ddrc_powerdown_to_x32
+
+9:5
+
+3e0
+
+6
+
+c0
+
+After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks.
+
    
+reg_ddrc_t_faw
+
+15:10
+
+fc00
+
+10
+
+4000
+
+tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related.
+
    
+reg_ddrc_t_ras_max
+
+21:16
+
+3f0000
+
+24
+
+240000
+
+tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related.
+
    
+reg_ddrc_t_ras_min
+
+26:22
+
+7c00000
+
+14
+
+5000000
+
+tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3.
+
    
+reg_ddrc_t_cke
+
+31:28
+
+f0000000
+
+4
+
+40000000
+
+Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks.
+
    
+DRAM_param_reg1@0XF8006018
+
+31:0
+
+f7ffffff
+
+
+
+452440d2
+
+DRAM Parameters 1
+
    
+
    
+
    Register ( slcr )DRAM_param_reg2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg2
+
+0XF800601C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_write_latency
+
+4:0
+
+1f
+
+5
+
+5
+
+Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. In non-LPDDR mode, the minimum DRAM Write Latency (DDR2) supported is 3. In LPDDR mode, the required DRAM Write Latency of 1 is supported. Since write latency (CWL) min is 3, and DDR2 CWL is CL-1, the min (DDR2) CL supported is 4
+
    
+reg_ddrc_rd2wr
+
+9:5
+
+3e0
+
+7
+
+e0
+
+Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED.
+
    
+reg_ddrc_wr2rd
+
+14:10
+
+7c00
+
+e
+
+3800
+
+Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs.
+
    
+reg_ddrc_t_xp
+
+19:15
+
+f8000
+
+4
+
+20000
+
+tXP: Minimum time after power down exit to any operation. DRAM related.
+
    
+reg_ddrc_pad_pd
+
+22:20
+
+700000
+
+0
+
+0
+
+If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks.
+
    
+reg_ddrc_rd2pre
+
+27:23
+
+f800000
+
+4
+
+2000000
+
+Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related.
+
    
+reg_ddrc_t_rcd
+
+31:28
+
+f0000000
+
+7
+
+70000000
+
+tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related.
+
    
+DRAM_param_reg2@0XF800601C
+
+31:0
+
+ffffffff
+
+
+
+720238e5
+
+DRAM Parameters 2
+
    
+
    
+
    Register ( slcr )DRAM_param_reg3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg3
+
+0XF8006020
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_t_ccd
+
+4:2
+
+1c
+
+4
+
+10
+
+tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related.
+
    
+reg_ddrc_t_rrd
+
+7:5
+
+e0
+
+4
+
+80
+
+tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED
+
    
+reg_ddrc_refresh_margin
+
+11:8
+
+f00
+
+2
+
+200
+
+Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value.
+
    
+reg_ddrc_t_rp
+
+15:12
+
+f000
+
+7
+
+7000
+
+tRP - Minimum time from precharge to activate of same bank. DRAM RELATED
+
    
+reg_ddrc_refresh_to_x32
+
+20:16
+
+1f0000
+
+8
+
+80000
+
+If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field.
+
    
+reg_ddrc_mobile
+
+22:22
+
+400000
+
+0
+
+0
+
+0: DDR2 or DDR3 device. 1: LPDDR2 device.
+
    
+reg_ddrc_en_dfi_dram_clk_disable
+
+23:23
+
+800000
+
+0
+
+0
+
+Enables the assertion of ddrc_dfi_dram_clk_disable. In DDR2/DDR3, only asserted in Self Refresh. In mDDR/LPDDR2, can be asserted in following: - during normal operation (Clock Stop), - in Power Down - in Self Refresh - In Deep Power Down
+
    
+reg_ddrc_read_latency
+
+28:24
+
+1f000000
+
+7
+
+7000000
+
+Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock.
+
    
+reg_phy_mode_ddr1_ddr2
+
+29:29
+
+20000000
+
+1
+
+20000000
+
+unused
+
    
+reg_ddrc_dis_pad_pd
+
+30:30
+
+40000000
+
+0
+
+0
+
+1: disable the pad power down feature 0: Enable the pad power down feature.
+
    
+DRAM_param_reg3@0XF8006020
+
+31:0
+
+7fdffffc
+
+
+
+27087290
+
+DRAM Parameters 3
+
    
+
    
+
    Register ( slcr )DRAM_param_reg4
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg4
+
+0XF8006024
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_en_2t_timing_mode
+
+0:0
+
+1
+
+0
+
+0
+
+1: DDRC will use 2T timing 0: DDRC will use 1T timing
+
    
+reg_ddrc_prefer_write
+
+1:1
+
+2
+
+0
+
+0
+
+1: Bank selector prefers writes over reads
+
    
+reg_ddrc_mr_wr
+
+6:6
+
+40
+
+0
+
+0
+
+A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low.
+
    
+reg_ddrc_mr_addr
+
+8:7
+
+180
+
+0
+
+0
+
+DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3
+
    
+reg_ddrc_mr_data
+
+24:9
+
+1fffe00
+
+0
+
+0
+
+DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0].
+
    
+ddrc_reg_mr_wr_busy
+
+25:25
+
+2000000
+
+0
+
+0
+
+Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress.
+
    
+reg_ddrc_mr_type
+
+26:26
+
+4000000
+
+0
+
+0
+
+Indicates whether the Mode register operation is read or write 0: write 1: read
+
    
+reg_ddrc_mr_rdata_valid
+
+27:27
+
+8000000
+
+0
+
+0
+
+This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9.
+
    
+DRAM_param_reg4@0XF8006024
+
+31:0
+
+fffffc3
+
+
+
+0
+
+DRAM Parameters 4
+
    
+
    
+
    Register ( slcr )DRAM_init_param
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_init_param
+
+0XF8006028
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_final_wait_x32
+
+6:0
+
+7f
+
+7
+
+7
+
+Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3.
+
    
+reg_ddrc_pre_ocd_x32
+
+10:7
+
+780
+
+0
+
+0
+
+Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero.
+
    
+reg_ddrc_t_mrd
+
+13:11
+
+3800
+
+4
+
+2000
+
+tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3.
+
    
+DRAM_init_param@0XF8006028
+
+31:0
+
+3fff
+
+
+
+2007
+
+DRAM Initialization Parameters
+
    
+
    
+
    Register ( slcr )DRAM_EMR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_EMR_reg
+
+0XF800602C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_emr2
+
+15:0
+
+ffff
+
+8
+
+8
+
+DDR2: Value loaded into EMR2 register DDR3: Value loaded into MR2 register LPDDR2: Value loaded into MR3 register
+
    
+reg_ddrc_emr3
+
+31:16
+
+ffff0000
+
+0
+
+0
+
+DDR2: Value loaded into EMR3 register DDR3: Value loaded into MR3 register. Set Bit[2:0] to 3'b000. These bits are set appropriately by the Controller during Read Data eye training and Read DQS gate leveling. LPDDR2: Unused
+
    
+DRAM_EMR_reg@0XF800602C
+
+31:0
+
+ffffffff
+
+
+
+8
+
+DRAM EMR2, EMR3 access
+
    
+
    
+
    Register ( slcr )DRAM_EMR_MR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_EMR_MR_reg
+
+0XF8006030
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_mr
+
+15:0
+
+ffff
+
+930
+
+930
+
+DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register
+
    
+reg_ddrc_emr
+
+31:16
+
+ffff0000
+
+4
+
+40000
+
+DDR2: Value loaded into EMR1register. (Bits[9:7] are for OCD and the setting in this reg is ignored. Controller sets this bits appropriately during initialization DDR3: Value loaded into MR1 register. Set Bit[7] to 0. This bit is set appropriately by the Controller during Write Leveling LPDDR2: Value loaded into MR2 register
+
    
+DRAM_EMR_MR_reg@0XF8006030
+
+31:0
+
+ffffffff
+
+
+
+40930
+
+DRAM EMR, MR access
+
    
+
    
+
    Register ( slcr )DRAM_burst8_rdwr
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_burst8_rdwr
+
+0XF8006034
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_burst_rdwr
+
+3:0
+
+f
+
+4
+
+4
+
+Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved
+
    
+reg_ddrc_pre_cke_x1024
+
+13:4
+
+3ff0
+
+105
+
+1050
+
+Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min)
+
    
+reg_ddrc_post_cke_x1024
+
+25:16
+
+3ff0000
+
+1
+
+10000
+
+Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us.
+
    
+reg_ddrc_burstchop
+
+28:28
+
+10000000
+
+0
+
+0
+
+Feature not supported. When 1, Controller is out in burstchop mode.
+
    
+DRAM_burst8_rdwr@0XF8006034
+
+31:0
+
+13ff3fff
+
+
+
+11054
+
+DRAM Burst 8 read/write
+
    
+
    
+
    Register ( slcr )DRAM_disable_DQ
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_disable_DQ
+
+0XF8006038
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_force_low_pri_n
+
+0:0
+
+1
+
+0
+
+0
+
+Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers.
+
    
+reg_ddrc_dis_dq
+
+1:1
+
+2
+
+0
+
+0
+
+When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field.
+
    
+DRAM_disable_DQ@0XF8006038
+
+31:0
+
+3
+
+
+
+0
+
+DRAM Disable DQ
+
    
+
    
+
    Register ( slcr )DRAM_addr_map_bank
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_addr_map_bank
+
+0XF800603C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_addrmap_bank_b0
+
+3:0
+
+f
+
+7
+
+7
+
+Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_bank_b1
+
+7:4
+
+f0
+
+7
+
+70
+
+Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_bank_b2
+
+11:8
+
+f00
+
+7
+
+700
+
+Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0.
+
    
+reg_ddrc_addrmap_col_b5
+
+15:12
+
+f000
+
+0
+
+0
+
+Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_col_b6
+
+19:16
+
+f0000
+
+0
+
+0
+
+Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.
+
    
+DRAM_addr_map_bank@0XF800603C
+
+31:0
+
+fffff
+
+
+
+777
+
+Row/Column address bits
+
    
+
    
+
    Register ( slcr )DRAM_addr_map_col
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_addr_map_col
+
+0XF8006040
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_addrmap_col_b2
+
+3:0
+
+f
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_col_b3
+
+7:4
+
+f0
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_col_b4
+
+11:8
+
+f00
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_col_b7
+
+15:12
+
+f000
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b8
+
+19:16
+
+f0000
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b9
+
+23:20
+
+f00000
+
+f
+
+f00000
+
+Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b10
+
+27:24
+
+f000000
+
+f
+
+f000000
+
+Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b11
+
+31:28
+
+f0000000
+
+f
+
+f0000000
+
+Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+DRAM_addr_map_col@0XF8006040
+
+31:0
+
+ffffffff
+
+
+
+fff00000
+
+Column address bits
+
    
+
    
+
    Register ( slcr )DRAM_addr_map_row
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_addr_map_row
+
+0XF8006044
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_addrmap_row_b0
+
+3:0
+
+f
+
+6
+
+6
+
+Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field
+
    
+reg_ddrc_addrmap_row_b1
+
+7:4
+
+f0
+
+6
+
+60
+
+Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_row_b2_11
+
+11:8
+
+f00
+
+6
+
+600
+
+Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_row_b12
+
+15:12
+
+f000
+
+6
+
+6000
+
+Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 8, Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0.
+
    
+reg_ddrc_addrmap_row_b13
+
+19:16
+
+f0000
+
+6
+
+60000
+
+Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 7, Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0.
+
    
+reg_ddrc_addrmap_row_b14
+
+23:20
+
+f00000
+
+6
+
+600000
+
+Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 6, Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0.
+
    
+reg_ddrc_addrmap_row_b15
+
+27:24
+
+f000000
+
+f
+
+f000000
+
+Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 5, Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0.
+
    
+DRAM_addr_map_row@0XF8006044
+
+31:0
+
+fffffff
+
+
+
+f666666
+
+Select DRAM row address bits
+
    
+
    
+
    Register ( slcr )DRAM_ODT_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_ODT_reg
+
+0XF8006048
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_local_odt
+
+13:12
+
+3000
+
+0
+
+0
+
+Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage.
+
    
+reg_phy_wr_local_odt
+
+15:14
+
+c000
+
+3
+
+c000
+
+Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS.
+
    
+reg_phy_idle_local_odt
+
+17:16
+
+30000
+
+3
+
+30000
+
+Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle.
+
    
+DRAM_ODT_reg@0XF8006048
+
+31:0
+
+3f000
+
+
+
+3c000
+
+DRAM ODT control
+
    
+
    
+
    Register ( slcr )phy_cmd_timeout_rddata_cpt
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_cmd_timeout_rddata_cpt
+
+0XF8006050
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_cmd_to_data
+
+3:0
+
+f
+
+0
+
+0
+
+Not used in DFI PHY.
+
    
+reg_phy_wr_cmd_to_data
+
+7:4
+
+f0
+
+0
+
+0
+
+Not used in DFI PHY.
+
    
+reg_phy_rdc_we_to_re_delay
+
+11:8
+
+f00
+
+8
+
+800
+
+This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1.
+
    
+reg_phy_rdc_fifo_rst_disable
+
+15:15
+
+8000
+
+0
+
+0
+
+When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty.
+
    
+reg_phy_use_fixed_re
+
+16:16
+
+10000
+
+1
+
+10000
+
+When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH.
+
    
+reg_phy_rdc_fifo_rst_err_cnt_clr
+
+17:17
+
+20000
+
+0
+
+0
+
+Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed.
+
    
+reg_phy_dis_phy_ctrl_rstn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset.
+
    
+reg_phy_clk_stall_level
+
+19:19
+
+80000
+
+0
+
+0
+
+1: stall clock, for DLL aging control
+
    
+reg_phy_gatelvl_num_of_dq0
+
+27:24
+
+f000000
+
+7
+
+7000000
+
+This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.
+
    
+reg_phy_wrlvl_num_of_dq0
+
+31:28
+
+f0000000
+
+7
+
+70000000
+
+This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.
+
    
+phy_cmd_timeout_rddata_cpt@0XF8006050
+
+31:0
+
+ff0f8fff
+
+
+
+77010800
+
+PHY command time out and read data capture FIFO
+
    
+
    
+
    Register ( slcr )DLL_calib
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DLL_calib
+
+0XF8006058
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_dis_dll_calib
+
+16:16
+
+10000
+
+0
+
+0
+
+When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically
+
    
+DLL_calib@0XF8006058
+
+31:0
+
+10000
+
+
+
+0
+
+DLL calibration
+
    
+
    
+
    Register ( slcr )ODT_delay_hold
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ODT_delay_hold
+
+0XF800605C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_rd_odt_delay
+
+3:0
+
+f
+
+3
+
+3
+
+UNUSED
+
    
+reg_ddrc_wr_odt_delay
+
+7:4
+
+f0
+
+0
+
+0
+
+The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2.
+
    
+reg_ddrc_rd_odt_hold
+
+11:8
+
+f00
+
+0
+
+0
+
+Unused
+
    
+reg_ddrc_wr_odt_hold
+
+15:12
+
+f000
+
+5
+
+5000
+
+Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4
+
    
+ODT_delay_hold@0XF800605C
+
+31:0
+
+ffff
+
+
+
+5003
+
+ODT delay and ODT hold
+
    
+
    
+
    Register ( slcr )ctrl_reg1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg1
+
+0XF8006060
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_pageclose
+
+0:0
+
+1
+
+0
+
+0
+
+If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used.
+
    
+reg_ddrc_lpr_num_entries
+
+6:1
+
+7e
+
+1f
+
+3e
+
+Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored.
+
    
+reg_ddrc_auto_pre_en
+
+7:7
+
+80
+
+0
+
+0
+
+When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.)
+
    
+reg_ddrc_refresh_update_level
+
+8:8
+
+100
+
+0
+
+0
+
+Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field.
+
    
+reg_ddrc_dis_wc
+
+9:9
+
+200
+
+0
+
+0
+
+Disable Write Combine: 0: enable 1: disable
+
    
+reg_ddrc_dis_collision_page_opt
+
+10:10
+
+400
+
+0
+
+0
+
+When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word).
+
    
+reg_ddrc_selfref_en
+
+12:12
+
+1000
+
+0
+
+0
+
+If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field.
+
    
+ctrl_reg1@0XF8006060
+
+31:0
+
+17ff
+
+
+
+3e
+
+Controller 1
+
    
+
    
+
    Register ( slcr )ctrl_reg2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg2
+
+0XF8006064
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_go2critical_hysteresis
+
+12:5
+
+1fe0
+
+0
+
+0
+
+Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0.
+
    
+reg_arb_go2critical_en
+
+17:17
+
+20000
+
+1
+
+20000
+
+0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master.
+
    
+ctrl_reg2@0XF8006064
+
+31:0
+
+21fe0
+
+
+
+20000
+
+Controller 2
+
    
+
    
+
    Register ( slcr )ctrl_reg3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg3
+
+0XF8006068
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_wrlvl_ww
+
+7:0
+
+ff
+
+41
+
+41
+
+DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50)
+
    
+reg_ddrc_rdlvl_rr
+
+15:8
+
+ff00
+
+41
+
+4100
+
+DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode.
+
    
+reg_ddrc_dfi_t_wlmrd
+
+25:16
+
+3ff0000
+
+28
+
+280000
+
+DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec.
+
    
+ctrl_reg3@0XF8006068
+
+31:0
+
+3ffffff
+
+
+
+284141
+
+Controller 3
+
    
+
    
+
    Register ( slcr )ctrl_reg4
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg4
+
+0XF800606C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+dfi_t_ctrlupd_interval_min_x1024
+
+7:0
+
+ff
+
+10
+
+10
+
+This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks
+
    
+dfi_t_ctrlupd_interval_max_x1024
+
+15:8
+
+ff00
+
+16
+
+1600
+
+This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks
+
    
+ctrl_reg4@0XF800606C
+
+31:0
+
+ffff
+
+
+
+1610
+
+Controller 4
+
    
+
    
+
    Register ( slcr )ctrl_reg5
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg5
+
+0XF8006078
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_dfi_t_ctrl_delay
+
+3:0
+
+f
+
+1
+
+1
+
+Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value.
+
    
+reg_ddrc_dfi_t_dram_clk_disable
+
+7:4
+
+f0
+
+1
+
+10
+
+Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value.
+
    
+reg_ddrc_dfi_t_dram_clk_enable
+
+11:8
+
+f00
+
+1
+
+100
+
+Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value.
+
    
+reg_ddrc_t_cksre
+
+15:12
+
+f000
+
+6
+
+6000
+
+This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE
+
    
+reg_ddrc_t_cksrx
+
+19:16
+
+f0000
+
+6
+
+60000
+
+This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX
+
    
+reg_ddrc_t_ckesr
+
+25:20
+
+3f00000
+
+4
+
+400000
+
+Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1
+
    
+ctrl_reg5@0XF8006078
+
+31:0
+
+3ffffff
+
+
+
+466111
+
+Controller register 5
+
    
+
    
+
    Register ( slcr )ctrl_reg6
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg6
+
+0XF800607C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_t_ckpde
+
+3:0
+
+f
+
+2
+
+2
+
+This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2.
+
    
+reg_ddrc_t_ckpdx
+
+7:4
+
+f0
+
+2
+
+20
+
+This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2.
+
    
+reg_ddrc_t_ckdpde
+
+11:8
+
+f00
+
+2
+
+200
+
+This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2.
+
    
+reg_ddrc_t_ckdpdx
+
+15:12
+
+f000
+
+2
+
+2000
+
+This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2.
+
    
+reg_ddrc_t_ckcsx
+
+19:16
+
+f0000
+
+3
+
+30000
+
+This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2.
+
    
+ctrl_reg6@0XF800607C
+
+31:0
+
+fffff
+
+
+
+32222
+
+Controller register 6
+
    
+
    
+
    Register ( slcr )CHE_T_ZQ
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_T_ZQ
+
+0XF80060A4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_dis_auto_zq
+
+0:0
+
+1
+
+0
+
+0
+
+1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices.
+
    
+reg_ddrc_ddr3
+
+1:1
+
+2
+
+1
+
+2
+
+Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3.
+
    
+reg_ddrc_t_mod
+
+11:2
+
+ffc
+
+200
+
+800
+
+Mode register set command update delay (minimum d'128)
+
    
+reg_ddrc_t_zq_long_nop
+
+21:12
+
+3ff000
+
+200
+
+200000
+
+DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles.
+
    
+reg_ddrc_t_zq_short_nop
+
+31:22
+
+ffc00000
+
+40
+
+10000000
+
+DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles.
+
    
+CHE_T_ZQ@0XF80060A4
+
+31:0
+
+ffffffff
+
+
+
+10200802
+
+ZQ parameters
+
    
+
    
+
    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_T_ZQ_Short_Interval_Reg
+
+0XF80060A8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+t_zq_short_interval_x1024
+
+19:0
+
+fffff
+
+cb73
+
+cb73
+
+DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles.
+
    
+dram_rstn_x1024
+
+27:20
+
+ff00000
+
+69
+
+6900000
+
+Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only.
+
    
+CHE_T_ZQ_Short_Interval_Reg@0XF80060A8
+
+31:0
+
+fffffff
+
+
+
+690cb73
+
+Misc parameters
+
    
+
    
+
    Register ( slcr )deep_pwrdwn_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+deep_pwrdwn_reg
+
+0XF80060AC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+deeppowerdown_en
+
+0:0
+
+1
+
+0
+
+0
+
+DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field.
+
    
+deeppowerdown_to_x1024
+
+8:1
+
+1fe
+
+ff
+
+1fe
+
+DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only.
+
    
+deep_pwrdwn_reg@0XF80060AC
+
+31:0
+
+1ff
+
+
+
+1fe
+
+Deep powerdown (LPDDR2)
+
    
+
    
+
    Register ( slcr )reg_2c
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_2c
+
+0XF80060B0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+dfi_wrlvl_max_x1024
+
+11:0
+
+fff
+
+fff
+
+fff
+
+Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks
+
    
+dfi_rdlvl_max_x1024
+
+23:12
+
+fff000
+
+fff
+
+fff000
+
+Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks
+
    
+ddrc_reg_twrlvl_max_error
+
+24:24
+
+1000000
+
+0
+
+0
+
+When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3.
+
    
+ddrc_reg_trdlvl_max_error
+
+25:25
+
+2000000
+
+0
+
+0
+
+DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register.
+
    
+reg_ddrc_dfi_wr_level_en
+
+26:26
+
+4000000
+
+1
+
+4000000
+
+0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs
+
    
+reg_ddrc_dfi_rd_dqs_gate_level
+
+27:27
+
+8000000
+
+1
+
+8000000
+
+0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs
+
    
+reg_ddrc_dfi_rd_data_eye_train
+
+28:28
+
+10000000
+
+1
+
+10000000
+
+DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence.
+
    
+reg_2c@0XF80060B0
+
+31:0
+
+1fffffff
+
+
+
+1cffffff
+
+Training control
+
    
+
    
+
    Register ( slcr )reg_2d
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_2d
+
+0XF80060B4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_skip_ocd
+
+9:9
+
+200
+
+1
+
+200
+
+This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported.
+
    
+reg_2d@0XF80060B4
+
+31:0
+
+200
+
+
+
+200
+
+Misc Debug
+
    
+
    
+
    Register ( slcr )dfi_timing
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+dfi_timing
+
+0XF80060B8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_dfi_t_rddata_en
+
+4:0
+
+1f
+
+6
+
+6
+
+Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM.
+
    
+reg_ddrc_dfi_t_ctrlup_min
+
+14:5
+
+7fe0
+
+3
+
+60
+
+Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted.
+
    
+reg_ddrc_dfi_t_ctrlup_max
+
+24:15
+
+1ff8000
+
+40
+
+200000
+
+Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert.
+
    
+dfi_timing@0XF80060B8
+
+31:0
+
+1ffffff
+
+
+
+200066
+
+DFI timing
+
    
+
    
+
    RESET ECC ERROR
    
+
    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_ECC_CONTROL_REG_OFFSET
+
+0XF80060C4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+Clear_Uncorrectable_DRAM_ECC_error
+
+0:0
+
+1
+
+1
+
+1
+
+Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters.
+
    
+Clear_Correctable_DRAM_ECC_error
+
+1:1
+
+2
+
+1
+
+2
+
+Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters.
+
    
+CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4
+
+31:0
+
+3
+
+
+
+3
+
+ECC error clear
+
    
+
    
+
    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_ECC_CONTROL_REG_OFFSET
+
+0XF80060C4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+Clear_Uncorrectable_DRAM_ECC_error
+
+0:0
+
+1
+
+0
+
+0
+
+Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters.
+
    
+Clear_Correctable_DRAM_ECC_error
+
+1:1
+
+2
+
+0
+
+0
+
+Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters.
+
    
+CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4
+
+31:0
+
+3
+
+
+
+0
+
+ECC error clear
+
    
+
    
+
    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_CORR_ECC_LOG_REG_OFFSET
+
+0XF80060C8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CORR_ECC_LOG_VALID
+
+0:0
+
+1
+
+0
+
+0
+
+Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31)
+
    
+ECC_CORRECTED_BIT_NUM
+
+7:1
+
+fe
+
+0
+
+0
+
+Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined.
+
    
+CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8
+
+31:0
+
+ff
+
+
+
+0
+
+ECC error correction
+
    
+
    
+
    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_UNCORR_ECC_LOG_REG_OFFSET
+
+0XF80060DC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNCORR_ECC_LOG_VALID
+
+0:0
+
+1
+
+0
+
+0
+
+Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31).
+
    
+CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC
+
+31:0
+
+1
+
+
+
+0
+
+ECC unrecoverable error status
+
    
+
    
+
    Register ( slcr )CHE_ECC_STATS_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_ECC_STATS_REG_OFFSET
+
+0XF80060F0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+STAT_NUM_CORR_ERR
+
+15:8
+
+ff00
+
+0
+
+0
+
+Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58).
+
    
+STAT_NUM_UNCORR_ERR
+
+7:0
+
+ff
+
+0
+
+0
+
+Returns the number of uncorrectable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58).
+
    
+CHE_ECC_STATS_REG_OFFSET@0XF80060F0
+
+31:0
+
+ffff
+
+
+
+0
+
+ECC error count
+
    
+
    
+
    Register ( slcr )ECC_scrub
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ECC_scrub
+
+0XF80060F4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_ecc_mode
+
+2:0
+
+7
+
+0
+
+0
+
+DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved
+
    
+reg_ddrc_dis_scrub
+
+3:3
+
+8
+
+1
+
+8
+
+0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs
+
    
+ECC_scrub@0XF80060F4
+
+31:0
+
+f
+
+
+
+8
+
+ECC mode/scrub
+
    
+
    
+
    Register ( slcr )phy_rcvr_enable
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rcvr_enable
+
+0XF8006114
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_dif_on
+
+3:0
+
+f
+
+0
+
+0
+
+Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter.
+
    
+reg_phy_dif_off
+
+7:4
+
+f0
+
+0
+
+0
+
+Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used.
+
    
+phy_rcvr_enable@0XF8006114
+
+31:0
+
+ff
+
+
+
+0
+
+Phy receiver enable register
+
    
+
    
+
    Register ( slcr )PHY_Config
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config
+
+0XF8006118
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+reserved
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+reserved
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+reserved
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config@0XF8006118
+
+31:0
+
+7fffffcf
+
+
+
+40000001
+
+PHY configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )PHY_Config
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config
+
+0XF800611C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+reserved
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+reserved
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+reserved
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config@0XF800611C
+
+31:0
+
+7fffffcf
+
+
+
+40000001
+
+PHY configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )PHY_Config
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config
+
+0XF8006120
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+reserved
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+reserved
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+reserved
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config@0XF8006120
+
+31:0
+
+7fffffcf
+
+
+
+40000001
+
+PHY configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )PHY_Config
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config
+
+0XF8006124
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+reserved
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+reserved
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+reserved
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config@0XF8006124
+
+31:0
+
+7fffffcf
+
+
+
+40000001
+
+PHY configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_init_ratio
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio
+
+0XF800612C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+1d
+
+1d
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+f2
+
+3c800
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio@0XF800612C
+
+31:0
+
+fffff
+
+
+
+3c81d
+
+PHY init ratio register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_init_ratio
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio
+
+0XF8006130
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+12
+
+12
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+d8
+
+36000
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio@0XF8006130
+
+31:0
+
+fffff
+
+
+
+36012
+
+PHY init ratio register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_init_ratio
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio
+
+0XF8006134
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+c
+
+c
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+de
+
+37800
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio@0XF8006134
+
+31:0
+
+fffff
+
+
+
+3780c
+
+PHY init ratio register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_init_ratio
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio
+
+0XF8006138
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+21
+
+21
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+ee
+
+3b800
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio@0XF8006138
+
+31:0
+
+fffff
+
+
+
+3b821
+
+PHY init ratio register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg
+
+0XF8006140
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg@0XF8006140
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg
+
+0XF8006144
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg@0XF8006144
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg
+
+0XF8006148
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg@0XF8006148
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg
+
+0XF800614C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg@0XF800614C
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg
+
+0XF8006154
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+9d
+
+9d
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value)
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg@0XF8006154
+
+31:0
+
+fffff
+
+
+
+9d
+
+PHY write DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg
+
+0XF8006158
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+92
+
+92
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value)
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg@0XF8006158
+
+31:0
+
+fffff
+
+
+
+92
+
+PHY write DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg
+
+0XF800615C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+8c
+
+8c
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value)
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg@0XF800615C
+
+31:0
+
+fffff
+
+
+
+8c
+
+PHY write DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg
+
+0XF8006160
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+a1
+
+a1
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value)
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg@0XF8006160
+
+31:0
+
+fffff
+
+
+
+a1
+
+PHY write DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_we_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg
+
+0XF8006168
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+147
+
+147
+
+Ratio value to be used when reg_phy_fifo_we_in_force is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when reg_phy_fifo_we_in_force is set to 1.
+
    
+phy_we_cfg@0XF8006168
+
+31:0
+
+1fffff
+
+
+
+147
+
+PHY FIFO write enable configuration for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_we_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg
+
+0XF800616C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+12d
+
+12d
+
+Ratio value to be used when reg_phy_fifo_we_in_force is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when reg_phy_fifo_we_in_force is set to 1.
+
    
+phy_we_cfg@0XF800616C
+
+31:0
+
+1fffff
+
+
+
+12d
+
+PHY FIFO write enable configuration for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_we_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg
+
+0XF8006170
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+133
+
+133
+
+Ratio value to be used when reg_phy_fifo_we_in_force is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when reg_phy_fifo_we_in_force is set to 1.
+
    
+phy_we_cfg@0XF8006170
+
+31:0
+
+1fffff
+
+
+
+133
+
+PHY FIFO write enable configuration for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_we_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg
+
+0XF8006174
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+143
+
+143
+
+Ratio value to be used when reg_phy_fifo_we_in_force is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when reg_phy_fifo_we_in_force is set to 1.
+
    
+phy_we_cfg@0XF8006174
+
+31:0
+
+1fffff
+
+
+
+143
+
+PHY FIFO write enable configuration for data slice 0.
+
    
+
    
+
    Register ( slcr )wr_data_slv
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv
+
+0XF800617C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+dd
+
+dd
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv@0XF800617C
+
+31:0
+
+fffff
+
+
+
+dd
+
+PHY write data slave ratio config for data slice 0.
+
    
+
    
+
    Register ( slcr )wr_data_slv
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv
+
+0XF8006180
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+d2
+
+d2
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv@0XF8006180
+
+31:0
+
+fffff
+
+
+
+d2
+
+PHY write data slave ratio config for data slice 0.
+
    
+
    
+
    Register ( slcr )wr_data_slv
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv
+
+0XF8006184
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+cc
+
+cc
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv@0XF8006184
+
+31:0
+
+fffff
+
+
+
+cc
+
+PHY write data slave ratio config for data slice 0.
+
    
+
    
+
    Register ( slcr )wr_data_slv
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv
+
+0XF8006188
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+e1
+
+e1
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv@0XF8006188
+
+31:0
+
+fffff
+
+
+
+e1
+
+PHY write data slave ratio config for data slice 0.
+
    
+
    
+
    Register ( slcr )reg_64
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_64
+
+0XF8006190
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_bl2
+
+1:1
+
+2
+
+0
+
+0
+
+Reserved for future Use.
+
    
+reg_phy_at_spd_atpg
+
+2:2
+
+4
+
+0
+
+0
+
+0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0.
+
    
+reg_phy_bist_enable
+
+3:3
+
+8
+
+0
+
+0
+
+Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback.
+
    
+reg_phy_bist_force_err
+
+4:4
+
+10
+
+0
+
+0
+
+This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error.
+
    
+reg_phy_bist_mode
+
+6:5
+
+60
+
+0
+
+0
+
+The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved
+
    
+reg_phy_invert_clkout
+
+7:7
+
+80
+
+1
+
+80
+
+Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on board topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling.
+
    
+reg_phy_sel_logic
+
+9:9
+
+200
+
+0
+
+0
+
+Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms
+
    
+reg_phy_ctrl_slave_ratio
+
+19:10
+
+ffc00
+
+100
+
+40000
+
+Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_ctrl_slave_force
+
+20:20
+
+100000
+
+0
+
+0
+
+0: Use reg_phy_ctrl_slave_ratio for address/command timing slave DLL 1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.
+
    
+reg_phy_ctrl_slave_delay
+
+27:21
+
+fe00000
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18].
+
    
+reg_phy_lpddr
+
+29:29
+
+20000000
+
+0
+
+0
+
+0: DDR2 or DDR3. 1: LPDDR2.
+
    
+reg_phy_cmd_latency
+
+30:30
+
+40000000
+
+0
+
+0
+
+If set to 1, command comes to phy_ctrl through a flop.
+
    
+reg_64@0XF8006190
+
+31:0
+
+6ffffefe
+
+
+
+40080
+
+Training control 2
+
    
+
    
+
    Register ( slcr )reg_65
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_65
+
+0XF8006194
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_rl_delay
+
+4:0
+
+1f
+
+2
+
+2
+
+This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1.
+
    
+reg_phy_rd_rl_delay
+
+9:5
+
+3e0
+
+4
+
+80
+
+This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1.
+
    
+reg_phy_dll_lock_diff
+
+13:10
+
+3c00
+
+f
+
+3c00
+
+The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted
+
    
+reg_phy_use_wr_level
+
+14:14
+
+4000
+
+1
+
+4000
+
+Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure.
+
    
+reg_phy_use_rd_dqs_gate_level
+
+15:15
+
+8000
+
+1
+
+8000
+
+Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure.
+
    
+reg_phy_use_rd_data_eye_level
+
+16:16
+
+10000
+
+1
+
+10000
+
+Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure
+
    
+reg_phy_dis_calib_rst
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs
+
    
+reg_phy_ctrl_slave_delay
+
+19:18
+
+c0000
+
+0
+
+0
+
+If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value
+
    
+reg_65@0XF8006194
+
+31:0
+
+fffff
+
+
+
+1fc82
+
+Training control 3
+
    
+
    
+
    Register ( slcr )page_mask
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+page_mask
+
+0XF8006204
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_page_addr_mask
+
+31:0
+
+ffffffff
+
+0
+
+0
+
+Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match.
+
    
+page_mask@0XF8006204
+
+31:0
+
+ffffffff
+
+
+
+0
+
+Page mask
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port
+
+0XF8006208
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+axi_priority_wr_port@0XF8006208
+
+31:0
+
+703ff
+
+
+
+3ff
+
+AXI Priority control for write port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port
+
+0XF800620C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+axi_priority_wr_port@0XF800620C
+
+31:0
+
+703ff
+
+
+
+3ff
+
+AXI Priority control for write port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port
+
+0XF8006210
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+axi_priority_wr_port@0XF8006210
+
+31:0
+
+703ff
+
+
+
+3ff
+
+AXI Priority control for write port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port
+
+0XF8006214
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+axi_priority_wr_port@0XF8006214
+
+31:0
+
+703ff
+
+
+
+3ff
+
+AXI Priority control for write port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port
+
+0XF8006218
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port@0XF8006218
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port
+
+0XF800621C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port@0XF800621C
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port
+
+0XF8006220
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port@0XF8006220
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port
+
+0XF8006224
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port@0XF8006224
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 0.
+
    
+
    
+
    Register ( slcr )lpddr_ctrl0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl0
+
+0XF80062A8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_lpddr2
+
+0:0
+
+1
+
+0
+
+0
+
+0: DDR2 or DDR3 in use. 1: LPDDR2 in Use.
+
    
+reg_ddrc_derate_enable
+
+2:2
+
+4
+
+0
+
+0
+
+0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. This feature should only be enabled after LPDDR2 initialization is completed
+
    
+reg_ddrc_mr4_margin
+
+11:4
+
+ff0
+
+0
+
+0
+
+UNUSED
+
    
+lpddr_ctrl0@0XF80062A8
+
+31:0
+
+ff5
+
+
+
+0
+
+LPDDR2 Control 0
+
    
+
    
+
    Register ( slcr )lpddr_ctrl1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl1
+
+0XF80062AC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_mr4_read_interval
+
+31:0
+
+ffffffff
+
+0
+
+0
+
+Interval between two MR4 reads, USED to derate the timing parameters.
+
    
+lpddr_ctrl1@0XF80062AC
+
+31:0
+
+ffffffff
+
+
+
+0
+
+LPDDR2 Control 1
+
    
+
    
+
    Register ( slcr )lpddr_ctrl2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl2
+
+0XF80062B0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_min_stable_clock_x1
+
+3:0
+
+f
+
+5
+
+5
+
+Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay.
+
    
+reg_ddrc_idle_after_reset_x32
+
+11:4
+
+ff0
+
+12
+
+120
+
+Idle time after the reset command, tINIT4. Units: 32 clock cycles.
+
    
+reg_ddrc_t_mrw
+
+21:12
+
+3ff000
+
+5
+
+5000
+
+Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5.
+
    
+lpddr_ctrl2@0XF80062B0
+
+31:0
+
+3fffff
+
+
+
+5125
+
+LPDDR2 Control 2
+
    
+
    
+
    Register ( slcr )lpddr_ctrl3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl3
+
+0XF80062B4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_max_auto_init_x1024
+
+7:0
+
+ff
+
+a8
+
+a8
+
+Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us.
+
    
+reg_ddrc_dev_zqinit_x32
+
+17:8
+
+3ff00
+
+12
+
+1200
+
+ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us.
+
    
+lpddr_ctrl3@0XF80062B4
+
+31:0
+
+3ffff
+
+
+
+12a8
+
+LPDDR2 Control 3
+
    
+
    
+
    POLL ON DCI STATUS
    
+
    Register ( slcr )DDRIOB_DCI_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_STATUS
+
+0XF8000B74
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DONE
+
+13:13
+
+2000
+
+1
+
+2000
+
+DCI done signal
+
    
+DDRIOB_DCI_STATUS@0XF8000B74
+
+31:0
+
+2000
+
+
+
+2000
+
+tobe
+
    
+
    
+
    UNLOCK DDR
    
+
    Register ( slcr )ddrc_ctrl
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ddrc_ctrl
+
+0XF8006000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_soft_rstb
+
+0:0
+
+1
+
+1
+
+1
+
+Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated.
+
    
+reg_ddrc_powerdown_en
+
+1:1
+
+2
+
+0
+
+0
+
+Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable
+
    
+reg_ddrc_data_bus_width
+
+3:2
+
+c
+
+0
+
+0
+
+DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved
+
    
+reg_ddrc_burst8_refresh
+
+6:4
+
+70
+
+0
+
+0
+
+Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh
+
    
+reg_ddrc_rdwr_idle_gap
+
+13:7
+
+3f80
+
+1
+
+80
+
+When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.
+
    
+reg_ddrc_dis_rd_bypass
+
+14:14
+
+4000
+
+0
+
+0
+
+Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits.
+
    
+reg_ddrc_dis_act_bypass
+
+15:15
+
+8000
+
+0
+
+0
+
+Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates.
+
    
+reg_ddrc_dis_auto_refresh
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.
+
    
+ddrc_ctrl@0XF8006000
+
+31:0
+
+1ffff
+
+
+
+81
+
+DDRC Control
+
    
+
    
+
    CHECK DDR STATUS
    
+
    Register ( slcr )mode_sts_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+mode_sts_reg
+
+0XF8006054
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+ddrc_reg_operating_mode
+
+2:0
+
+7
+
+1
+
+1
+
+Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Powerdown mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only)
+
    
+mode_sts_reg@0XF8006054
+
+31:0
+
+7
+
+
+
+1
+
+tobe
+
    
+
    
+
+
    
+
    ps7_mio_init_data_3_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+GPIOB_CTRL
+
+
+0XF8000B00
+
+32
+
+RW
+
+0x000000
+
+PS IO Buffer Control
+
    
+
+DDRIOB_ADDR0
+
+
+0XF8000B40
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for A[14:0], CKE and DRST_B
+
    
+
+DDRIOB_ADDR1
+
+
+0XF8000B44
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B
+
    
+
+DDRIOB_DATA0
+
+
+0XF8000B48
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Data 15:0
+
    
+
+DDRIOB_DATA1
+
+
+0XF8000B4C
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Data 31:16
+
    
+
+DDRIOB_DIFF0
+
+
+0XF8000B50
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for DQS 1:0
+
    
+
+DDRIOB_DIFF1
+
+
+0XF8000B54
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for DQS 3:2
+
    
+
+DDRIOB_CLOCK
+
+
+0XF8000B58
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Clock Output
+
    
+
+DDRIOB_DRIVE_SLEW_ADDR
+
+
+0XF8000B5C
+
+32
+
+RW
+
+0x000000
+
+Drive and Slew controls for Address and Command pins of the DDR Interface
+
    
+
+DDRIOB_DRIVE_SLEW_DATA
+
+
+0XF8000B60
+
+32
+
+RW
+
+0x000000
+
+Drive and Slew controls for DQ pins of the DDR Interface
+
    
+
+DDRIOB_DRIVE_SLEW_DIFF
+
+
+0XF8000B64
+
+32
+
+RW
+
+0x000000
+
+Drive and Slew controls for DQS pins of the DDR Interface
+
    
+
+DDRIOB_DRIVE_SLEW_CLOCK
+
+
+0XF8000B68
+
+32
+
+RW
+
+0x000000
+
+Drive and Slew controls for Clock pins of the DDR Interface
+
    
+
+DDRIOB_DDR_CTRL
+
+
+0XF8000B6C
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Buffer Control
+
    
+
+DDRIOB_DCI_CTRL
+
+
+0XF8000B70
+
+32
+
+RW
+
+0x000000
+
+DDR IOB DCI Config
+
    
+
+DDRIOB_DCI_CTRL
+
+
+0XF8000B70
+
+32
+
+RW
+
+0x000000
+
+DDR IOB DCI Config
+
    
+
+DDRIOB_DCI_CTRL
+
+
+0XF8000B70
+
+32
+
+RW
+
+0x000000
+
+DDR IOB DCI Config
+
    
+
+MIO_PIN_00
+
+
+0XF8000700
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 0 Control
+
    
+
+MIO_PIN_01
+
+
+0XF8000704
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 1 Control
+
    
+
+MIO_PIN_02
+
+
+0XF8000708
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 2 Control
+
    
+
+MIO_PIN_03
+
+
+0XF800070C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 3 Control
+
    
+
+MIO_PIN_04
+
+
+0XF8000710
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 4 Control
+
    
+
+MIO_PIN_05
+
+
+0XF8000714
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 5 Control
+
    
+
+MIO_PIN_06
+
+
+0XF8000718
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 6 Control
+
    
+
+MIO_PIN_07
+
+
+0XF800071C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 7 Control
+
    
+
+MIO_PIN_08
+
+
+0XF8000720
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 8 Control
+
    
+
+MIO_PIN_09
+
+
+0XF8000724
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 9 Control
+
    
+
+MIO_PIN_10
+
+
+0XF8000728
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 10 Control
+
    
+
+MIO_PIN_11
+
+
+0XF800072C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 11 Control
+
    
+
+MIO_PIN_12
+
+
+0XF8000730
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 12 Control
+
    
+
+MIO_PIN_13
+
+
+0XF8000734
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 13 Control
+
    
+
+MIO_PIN_14
+
+
+0XF8000738
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 14 Control
+
    
+
+MIO_PIN_15
+
+
+0XF800073C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 15 Control
+
    
+
+MIO_PIN_16
+
+
+0XF8000740
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 16 Control
+
    
+
+MIO_PIN_17
+
+
+0XF8000744
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 17 Control
+
    
+
+MIO_PIN_18
+
+
+0XF8000748
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 18 Control
+
    
+
+MIO_PIN_19
+
+
+0XF800074C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 19 Control
+
    
+
+MIO_PIN_20
+
+
+0XF8000750
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 20 Control
+
    
+
+MIO_PIN_21
+
+
+0XF8000754
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 21 Control
+
    
+
+MIO_PIN_22
+
+
+0XF8000758
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 22 Control
+
    
+
+MIO_PIN_23
+
+
+0XF800075C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 23 Control
+
    
+
+MIO_PIN_24
+
+
+0XF8000760
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 24 Control
+
    
+
+MIO_PIN_25
+
+
+0XF8000764
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 25 Control
+
    
+
+MIO_PIN_26
+
+
+0XF8000768
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 26 Control
+
    
+
+MIO_PIN_27
+
+
+0XF800076C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 27 Control
+
    
+
+MIO_PIN_28
+
+
+0XF8000770
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 28 Control
+
    
+
+MIO_PIN_29
+
+
+0XF8000774
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 29 Control
+
    
+
+MIO_PIN_30
+
+
+0XF8000778
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 30 Control
+
    
+
+MIO_PIN_31
+
+
+0XF800077C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 31 Control
+
    
+
+MIO_PIN_32
+
+
+0XF8000780
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 32 Control
+
    
+
+MIO_PIN_33
+
+
+0XF8000784
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 33 Control
+
    
+
+MIO_PIN_34
+
+
+0XF8000788
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 34 Control
+
    
+
+MIO_PIN_35
+
+
+0XF800078C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 35 Control
+
    
+
+MIO_PIN_36
+
+
+0XF8000790
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 36 Control
+
    
+
+MIO_PIN_37
+
+
+0XF8000794
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 37 Control
+
    
+
+MIO_PIN_38
+
+
+0XF8000798
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 38 Control
+
    
+
+MIO_PIN_39
+
+
+0XF800079C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 39 Control
+
    
+
+MIO_PIN_40
+
+
+0XF80007A0
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 40 Control
+
    
+
+MIO_PIN_41
+
+
+0XF80007A4
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 41 Control
+
    
+
+MIO_PIN_42
+
+
+0XF80007A8
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 42 Control
+
    
+
+MIO_PIN_43
+
+
+0XF80007AC
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 43 Control
+
    
+
+MIO_PIN_44
+
+
+0XF80007B0
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 44 Control
+
    
+
+MIO_PIN_45
+
+
+0XF80007B4
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 45 Control
+
    
+
+MIO_PIN_46
+
+
+0XF80007B8
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 46 Control
+
    
+
+MIO_PIN_47
+
+
+0XF80007BC
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 47 Control
+
    
+
+MIO_PIN_48
+
+
+0XF80007C0
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 48 Control
+
    
+
+MIO_PIN_49
+
+
+0XF80007C4
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 49 Control
+
    
+
+MIO_PIN_50
+
+
+0XF80007C8
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 50 Control
+
    
+
+MIO_PIN_51
+
+
+0XF80007CC
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 51 Control
+
    
+
+MIO_PIN_52
+
+
+0XF80007D0
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 52 Control
+
    
+
+MIO_PIN_53
+
+
+0XF80007D4
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 53 Control
+
    
+
+SD0_WP_CD_SEL
+
+
+0XF8000830
+
+32
+
+RW
+
+0x000000
+
+SDIO 0 WP CD select
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_mio_init_data_3_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    OCM REMAPPING
    
+
    Register ( slcr )GPIOB_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+GPIOB_CTRL
+
+0XF8000B00
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+VREF_EN
+
+0:0
+
+1
+
+1
+
+1
+
+Enables VREF internal generator
+
    
+VREF_SEL
+
+6:4
+
+70
+
+0
+
+0
+
+Specifies GPIO VREF Selection 000 - VREF = Disabled 001 - VREF = 0.9V 010 - VREF = test only - 1.8V 100 - VREF = test only - 1.25V Other values reserved
+
    
+GPIOB_CTRL@0XF8000B00
+
+31:0
+
+71
+
+
+
+1
+
+PS IO Buffer Control
+
    
+
    
+
    DDRIOB SETTINGS
    
+
    Register ( slcr )DDRIOB_ADDR0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_ADDR0
+
+0XF8000B40
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+0
+
+0
+
+Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE_B
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enable: 0: disable 1: enable
+
    
+TERM_EN
+
+4:4
+
+10
+
+0
+
+0
+
+Tri State Termination Enable: 0: disable 1: enable
+
    
+DCI_TYPE
+
+6:5
+
+60
+
+0
+
+0
+
+DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_ADDR0@0XF8000B40
+
+31:0
+
+fff
+
+
+
+600
+
+DDR IOB Config for A[14:0], CKE and DRST_B
+
    
+
    
+
    Register ( slcr )DDRIOB_ADDR1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_ADDR1
+
+0XF8000B44
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+0
+
+0
+
+Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE_B
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enable: 0: disable 1: enable
+
    
+TERM_EN
+
+4:4
+
+10
+
+0
+
+0
+
+Tri State Termination Enable: 0: disable 1: enable
+
    
+DCI_TYPE
+
+6:5
+
+60
+
+0
+
+0
+
+DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_ADDR1@0XF8000B44
+
+31:0
+
+fff
+
+
+
+600
+
+DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B
+
    
+
    
+
    Register ( slcr )DDRIOB_DATA0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA0
+
+0XF8000B48
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+1
+
+2
+
+Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE_B
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enable: 0: disable 1: enable
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enable: 0: disable 1: enable
+
    
+DCI_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_DATA0@0XF8000B48
+
+31:0
+
+fff
+
+
+
+672
+
+DDR IOB Config for Data 15:0
+
    
+
    
+
    Register ( slcr )DDRIOB_DATA1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA1
+
+0XF8000B4C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+1
+
+2
+
+Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE_B
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enable: 0: disable 1: enable
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enable: 0: disable 1: enable
+
    
+DCI_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_DATA1@0XF8000B4C
+
+31:0
+
+fff
+
+
+
+672
+
+DDR IOB Config for Data 31:16
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF0
+
+0XF8000B50
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+2
+
+4
+
+Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE_B
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enable: 0: disable 1: enable
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enable: 0: disable 1: enable
+
    
+DCI_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_DIFF0@0XF8000B50
+
+31:0
+
+fff
+
+
+
+674
+
+DDR IOB Config for DQS 1:0
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF1
+
+0XF8000B54
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+2
+
+4
+
+Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE_B
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enable: 0: disable 1: enable
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enable: 0: disable 1: enable
+
    
+DCI_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_DIFF1@0XF8000B54
+
+31:0
+
+fff
+
+
+
+674
+
+DDR IOB Config for DQS 3:2
+
    
+
    
+
    Register ( slcr )DDRIOB_CLOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_CLOCK
+
+0XF8000B58
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+0
+
+0
+
+Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE_B
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enable: 0: disable 1: enable
+
    
+TERM_EN
+
+4:4
+
+10
+
+0
+
+0
+
+Tri State Termination Enable: 0: disable 1: enable
+
    
+DCI_TYPE
+
+6:5
+
+60
+
+0
+
+0
+
+DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_CLOCK@0XF8000B58
+
+31:0
+
+fff
+
+
+
+600
+
+DDR IOB Config for Clock Output
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_ADDR
+
+0XF8000B5C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+Reserved. Do not modify.
+
    
+reserved_DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+Reserved. Do not modify.
+
    
+reserved_SLEW_P
+
+18:14
+
+7c000
+
+3
+
+c000
+
+Reserved. Do not modify.
+
    
+reserved_SLEW_N
+
+23:19
+
+f80000
+
+3
+
+180000
+
+Reserved. Do not modify.
+
    
+reserved_GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C
+
+31:0
+
+ffffffff
+
+
+
+18c61c
+
+Drive and Slew controls for Address and Command pins of the DDR Interface
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_DATA
+
+0XF8000B60
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+Reserved. Do not modify.
+
    
+reserved_DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+Reserved. Do not modify.
+
    
+reserved_SLEW_P
+
+18:14
+
+7c000
+
+6
+
+18000
+
+Reserved. Do not modify.
+
    
+reserved_SLEW_N
+
+23:19
+
+f80000
+
+1f
+
+f80000
+
+Reserved. Do not modify.
+
    
+reserved_GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+DDRIOB_DRIVE_SLEW_DATA@0XF8000B60
+
+31:0
+
+ffffffff
+
+
+
+f9861c
+
+Drive and Slew controls for DQ pins of the DDR Interface
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_DIFF
+
+0XF8000B64
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+Reserved. Do not modify.
+
    
+reserved_DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+Reserved. Do not modify.
+
    
+reserved_SLEW_P
+
+18:14
+
+7c000
+
+6
+
+18000
+
+Reserved. Do not modify.
+
    
+reserved_SLEW_N
+
+23:19
+
+f80000
+
+1f
+
+f80000
+
+Reserved. Do not modify.
+
    
+reserved_GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64
+
+31:0
+
+ffffffff
+
+
+
+f9861c
+
+Drive and Slew controls for DQS pins of the DDR Interface
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_CLOCK
+
+0XF8000B68
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+Reserved. Do not modify.
+
    
+reserved_DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+Reserved. Do not modify.
+
    
+reserved_SLEW_P
+
+18:14
+
+7c000
+
+6
+
+18000
+
+Reserved. Do not modify.
+
    
+reserved_SLEW_N
+
+23:19
+
+f80000
+
+1f
+
+f80000
+
+Reserved. Do not modify.
+
    
+reserved_GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68
+
+31:0
+
+ffffffff
+
+
+
+f9861c
+
+Drive and Slew controls for Clock pins of the DDR Interface
+
    
+
    
+
    Register ( slcr )DDRIOB_DDR_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DDR_CTRL
+
+0XF8000B6C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+VREF_INT_EN
+
+0:0
+
+1
+
+1
+
+1
+
+Enables VREF internal generator
+
    
+VREF_SEL
+
+4:1
+
+1e
+
+4
+
+8
+
+Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO
+
    
+VREF_EXT_EN
+
+6:5
+
+60
+
+0
+
+0
+
+Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1x: Enable External VREF for upper 16 bits
+
    
+reserved_VREF_PULLUP_EN
+
+8:7
+
+180
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+REFIO_EN
+
+9:9
+
+200
+
+1
+
+200
+
+Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio
+
    
+reserved_REFIO_TEST
+
+11:10
+
+c00
+
+3
+
+c00
+
+Reserved. Do not modify.
+
    
+reserved_REFIO_PULLUP_EN
+
+12:12
+
+1000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_DRST_B_PULLUP_EN
+
+13:13
+
+2000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_CKE_PULLUP_EN
+
+14:14
+
+4000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+DDRIOB_DDR_CTRL@0XF8000B6C
+
+31:0
+
+7fff
+
+
+
+e09
+
+DDR IOB Buffer Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )DDRIOB_DCI_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_CTRL
+
+0XF8000B70
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+RESET
+
+0:0
+
+1
+
+1
+
+1
+
+At least toggle once to initialize flops in DCI system
+
    
+DDRIOB_DCI_CTRL@0XF8000B70
+
+31:0
+
+1
+
+
+
+1
+
+DDR IOB DCI Config
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )DDRIOB_DCI_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_CTRL
+
+0XF8000B70
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+RESET
+
+0:0
+
+1
+
+0
+
+0
+
+At least toggle once to initialize flops in DCI system
+
    
+reserved_VRN_OUT
+
+5:5
+
+20
+
+1
+
+20
+
+Reserved. Do not modify.
+
    
+DDRIOB_DCI_CTRL@0XF8000B70
+
+31:0
+
+21
+
+
+
+20
+
+DDR IOB DCI Config
+
    
+
    
+
    Register ( slcr )DDRIOB_DCI_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_CTRL
+
+0XF8000B70
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+RESET
+
+0:0
+
+1
+
+1
+
+1
+
+At least toggle once to initialize flops in DCI system
+
    
+ENABLE
+
+1:1
+
+2
+
+1
+
+2
+
+DCI System Enable. Set to 1 if any IOs in DDR IO Bank use DCI Termination. DDR2, DDR3 and LPDDR2 (Silicon Revision 2.0+) configurations require this bit set to 1
+
    
+reserved_VRP_TRI
+
+2:2
+
+4
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_VRN_TRI
+
+3:3
+
+8
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_VRP_OUT
+
+4:4
+
+10
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_VRN_OUT
+
+5:5
+
+20
+
+1
+
+20
+
+Reserved. Do not modify.
+
    
+NREF_OPT1
+
+7:6
+
+c0
+
+0
+
+0
+
+DCI Calibration. Use the values in the Calibration Table.
+
    
+NREF_OPT2
+
+10:8
+
+700
+
+0
+
+0
+
+DCI Calibration. Use the values in the Calibration Table.
+
    
+NREF_OPT4
+
+13:11
+
+3800
+
+1
+
+800
+
+DCI Calibration. Use the values in the Calibration Table.
+
    
+PREF_OPT1
+
+15:14
+
+c000
+
+0
+
+0
+
+DCI Calibration. Use the values in the Calibration Table.
+
    
+PREF_OPT2
+
+19:17
+
+e0000
+
+0
+
+0
+
+DCI Calibration. Use the values in the Calibration Table.
+
    
+UPDATE_CONTROL
+
+20:20
+
+100000
+
+0
+
+0
+
+DCI Update Mode. Use the values in the Calibration Table.
+
    
+reserved_INIT_COMPLETE
+
+21:21
+
+200000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_TST_CLK
+
+22:22
+
+400000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_TST_HLN
+
+23:23
+
+800000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_TST_HLP
+
+24:24
+
+1000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_TST_RST
+
+25:25
+
+2000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_INT_DCI_EN
+
+26:26
+
+4000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+DDRIOB_DCI_CTRL@0XF8000B70
+
+31:0
+
+7feffff
+
+
+
+823
+
+DDR IOB DCI Config
+
    
+
    
+
    MIO PROGRAMMING
    
+
    Register ( slcr )MIO_PIN_00
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_00
+
+0XF8000700
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Tri-state enable, active high. 0: disable 1: enable
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Enables Pullup on IO Buffer pin 0: disable 1: enable
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable
+
    
+MIO_PIN_00@0XF8000700
+
+31:0
+
+3f01
+
+
+
+1201
+
+MIO Pin 0 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_01
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_01
+
+0XF8000704
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: reserved
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_01@0XF8000704
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Pin 1 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_02
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_02
+
+0XF8000708
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_02@0XF8000708
+
+31:0
+
+3fff
+
+
+
+202
+
+MIO Pin 2 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_03
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_03
+
+0XF800070C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_03@0XF800070C
+
+31:0
+
+3fff
+
+
+
+202
+
+MIO Pin 3 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_04
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_04
+
+0XF8000710
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_04@0XF8000710
+
+31:0
+
+3fff
+
+
+
+202
+
+MIO Pin 4 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_05
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_05
+
+0XF8000714
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_05@0XF8000714
+
+31:0
+
+3fff
+
+
+
+202
+
+MIO Pin 5 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_06
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_06
+
+0XF8000718
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_06@0XF8000718
+
+31:0
+
+3fff
+
+
+
+202
+
+MIO Pin 6 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_07
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_07
+
+0XF800071C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B, Output 10: NAND Flash CLE_B, Output 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 7 (bank 0), Output-only others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_07@0XF800071C
+
+31:0
+
+3fff
+
+
+
+200
+
+MIO Pin 7 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_08
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_08
+
+0XF8000720
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_08@0XF8000720
+
+31:0
+
+3fff
+
+
+
+202
+
+MIO Pin 8 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_09
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_09
+
+0XF8000724
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6, Input/Output 10: NAND Flash IO Bit 4, Input/Output 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 9 (bank 0), Input/Output 001: CAN 1 Rx, Input 010 to 110: reserved 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_09@0XF8000724
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 9 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_10
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_10
+
+0XF8000728
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_10@0XF8000728
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 10 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_11
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_11
+
+0XF800072C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_11@0XF800072C
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 11 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_12
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_12
+
+0XF8000730
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2, Input/Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait, Input 10: NAND Flash IO Bit 7, Input/Output 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 12 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_12@0XF8000730
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 12 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_13
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_13
+
+0XF8000734
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3, Input/Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5, Input/Output 10: NAND Flash IO Bit 3, Input/Output 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 13 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_13@0XF8000734
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 13 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_14
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_14
+
+0XF8000738
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_14@0XF8000738
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 14 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_15
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_15
+
+0XF800073C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_15@0XF800073C
+
+31:0
+
+3f01
+
+
+
+1201
+
+MIO Pin 15 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_16
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_16
+
+0XF8000740
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1, Output 10: NAND Flash IO Bit 8, Input/Output 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 16 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+1
+
+2000
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_16@0XF8000740
+
+31:0
+
+3fff
+
+
+
+2802
+
+MIO Pin 16 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_17
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_17
+
+0XF8000744
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2, Output 10: NAND Flash IO Bit 9, Input/Output 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 17 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110 TTC 1 Clock, Input 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+1
+
+2000
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_17@0XF8000744
+
+31:0
+
+3fff
+
+
+
+2802
+
+MIO Pin 17 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_18
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_18
+
+0XF8000748
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3, Output 10: NAND Flash IO Bit 10, Input/Output 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 18 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+1
+
+2000
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_18@0XF8000748
+
+31:0
+
+3fff
+
+
+
+2802
+
+MIO Pin 18 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_19
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_19
+
+0XF800074C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+1
+
+2000
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_19@0XF800074C
+
+31:0
+
+3fff
+
+
+
+2802
+
+MIO Pin 19 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_20
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_20
+
+0XF8000750
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: reserved
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+1
+
+2000
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_20@0XF8000750
+
+31:0
+
+3fff
+
+
+
+2802
+
+MIO Pin 20 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_21
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_21
+
+0XF8000754
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: reserved
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6, Output 10: NAND Flash IO Bit 13, Input/Output 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 21 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+1
+
+2000
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_21@0XF8000754
+
+31:0
+
+3fff
+
+
+
+2802
+
+MIO Pin 21 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_22
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_22
+
+0XF8000758
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_22@0XF8000758
+
+31:0
+
+3fff
+
+
+
+803
+
+MIO Pin 22 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_23
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_23
+
+0XF800075C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_23@0XF800075C
+
+31:0
+
+3fff
+
+
+
+803
+
+MIO Pin 23 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_24
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_24
+
+0XF8000760
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_24@0XF8000760
+
+31:0
+
+3fff
+
+
+
+803
+
+MIO Pin 24 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_25
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_25
+
+0XF8000764
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_25@0XF8000764
+
+31:0
+
+3fff
+
+
+
+803
+
+MIO Pin 25 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_26
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_26
+
+0XF8000768
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_26@0XF8000768
+
+31:0
+
+3fff
+
+
+
+803
+
+MIO Pin 26 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_27
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_27
+
+0XF800076C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_27@0XF800076C
+
+31:0
+
+3fff
+
+
+
+803
+
+MIO Pin 27 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_28
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_28
+
+0XF8000770
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13, Output 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 28 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_28@0XF8000770
+
+31:0
+
+3fff
+
+
+
+204
+
+MIO Pin 28 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_29
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_29
+
+0XF8000774
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction, Input
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14, Output 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 29 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_29@0XF8000774
+
+31:0
+
+3fff
+
+
+
+205
+
+MIO Pin 29 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_30
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_30
+
+0XF8000778
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15, Output 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 30 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_30@0XF8000778
+
+31:0
+
+3fff
+
+
+
+204
+
+MIO Pin 30 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_31
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_31
+
+0XF800077C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next, Input
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16, Output 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 31 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_31@0XF800077C
+
+31:0
+
+3fff
+
+
+
+205
+
+MIO Pin 31 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_32
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_32
+
+0XF8000780
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17, Output 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 32 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_32@0XF8000780
+
+31:0
+
+3fff
+
+
+
+204
+
+MIO Pin 32 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_33
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_33
+
+0XF8000784
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control, Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18, Output 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 33 (Bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_33@0XF8000784
+
+31:0
+
+3fff
+
+
+
+204
+
+MIO Pin 33 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_34
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_34
+
+0XF8000788
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock, Input
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19, Output 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 34 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 110: reserved 111: UART 0 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_34@0XF8000788
+
+31:0
+
+3fff
+
+
+
+204
+
+MIO Pin 34 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_35
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_35
+
+0XF800078C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0, Input
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20, Output 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 35 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_35@0XF800078C
+
+31:0
+
+3fff
+
+
+
+204
+
+MIO Pin 35 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_36
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_36
+
+0XF8000790
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21, Output 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 36 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Clock, Input/Output 110: reserved 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_36@0XF8000790
+
+31:0
+
+3fff
+
+
+
+205
+
+MIO Pin 36 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_37
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_37
+
+0XF8000794
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 2, Input
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22, Output 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 37 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_37@0XF8000794
+
+31:0
+
+3fff
+
+
+
+204
+
+MIO Pin 37 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_38
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_38
+
+0XF8000798
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3, Input
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23, Output 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 38 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_38@0XF8000798
+
+31:0
+
+3fff
+
+
+
+204
+
+MIO Pin 38 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_39
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_39
+
+0XF800079C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control, Input
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24, Output 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 39 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_39@0XF800079C
+
+31:0
+
+3fff
+
+
+
+204
+
+MIO Pin 39 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_40
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_40
+
+0XF80007A0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_40@0XF80007A0
+
+31:0
+
+3fff
+
+
+
+280
+
+MIO Pin 40 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_41
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_41
+
+0XF80007A4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_41@0XF80007A4
+
+31:0
+
+3fff
+
+
+
+280
+
+MIO Pin 41 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_42
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_42
+
+0XF80007A8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_42@0XF80007A8
+
+31:0
+
+3fff
+
+
+
+280
+
+MIO Pin 42 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_43
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_43
+
+0XF80007AC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_43@0XF80007AC
+
+31:0
+
+3fff
+
+
+
+280
+
+MIO Pin 43 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_44
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_44
+
+0XF80007B0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_44@0XF80007B0
+
+31:0
+
+3fff
+
+
+
+280
+
+MIO Pin 44 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_45
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_45
+
+0XF80007B4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_45@0XF80007B4
+
+31:0
+
+3fff
+
+
+
+280
+
+MIO Pin 45 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_46
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_46
+
+0XF80007B8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+1
+
+20
+
+Level 3 Mux Select 000: GPIO 46 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_46@0XF80007B8
+
+31:0
+
+3fff
+
+
+
+1221
+
+MIO Pin 46 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_47
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_47
+
+0XF80007BC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 3, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+1
+
+20
+
+Level 3 Mux Select 000: GPIO 47 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_47@0XF80007BC
+
+31:0
+
+3fff
+
+
+
+1220
+
+MIO Pin 47 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_48
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_48
+
+0XF80007C0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+7
+
+e0
+
+Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_48@0XF80007C0
+
+31:0
+
+3fff
+
+
+
+2e0
+
+MIO Pin 48 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_49
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_49
+
+0XF80007C4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+7
+
+e0
+
+Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_49@0XF80007C4
+
+31:0
+
+3fff
+
+
+
+2e1
+
+MIO Pin 49 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_50
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_50
+
+0XF80007C8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+2
+
+40
+
+Level 3 Mux Select 000: GPIO 50 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_50@0XF80007C8
+
+31:0
+
+3fff
+
+
+
+1240
+
+MIO Pin 50 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_51
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_51
+
+0XF80007CC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7, Input/Output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+2
+
+40
+
+Level 3 Mux Select 000: GPIO 51 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_51@0XF80007CC
+
+31:0
+
+3fff
+
+
+
+1240
+
+MIO Pin 51 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_52
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_52
+
+0XF80007D0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: reserved
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_52@0XF80007D0
+
+31:0
+
+3fff
+
+
+
+280
+
+MIO Pin 52 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_53
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_53
+
+0XF80007D4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: reserved
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULLUP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_53@0XF80007D4
+
+31:0
+
+3fff
+
+
+
+280
+
+MIO Pin 53 Control
+
    
+
    
+
    Register ( slcr )SD0_WP_CD_SEL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SD0_WP_CD_SEL
+
+0XF8000830
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SDIO0_WP_SEL
+
+5:0
+
+3f
+
+f
+
+f
+
+SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input
+
    
+SDIO0_CD_SEL
+
+21:16
+
+3f0000
+
+0
+
+0
+
+SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input
+
    
+SD0_WP_CD_SEL@0XF8000830
+
+31:0
+
+3f003f
+
+
+
+f
+
+SDIO 0 WP CD select
+
    
+
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_peripherals_init_data_3_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+DDRIOB_DATA0
+
+
+0XF8000B48
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Data 15:0
+
    
+
+DDRIOB_DATA1
+
+
+0XF8000B4C
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Data 31:16
+
    
+
+DDRIOB_DIFF0
+
+
+0XF8000B50
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for DQS 1:0
+
    
+
+DDRIOB_DIFF1
+
+
+0XF8000B54
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for DQS 3:2
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
+Baud_rate_divider_reg0
+
+
+0XE0001034
+
+32
+
+RW
+
+0x000000
+
+Baud Rate Divider Register
+
    
+
+Baud_rate_gen_reg0
+
+
+0XE0001018
+
+32
+
+RW
+
+0x000000
+
+Baud Rate Generator Register.
+
    
+
+Control_reg0
+
+
+0XE0001000
+
+32
+
+RW
+
+0x000000
+
+UART Control Register
+
    
+
+mode_reg0
+
+
+0XE0001004
+
+32
+
+RW
+
+0x000000
+
+UART Mode Register
+
    
+
+Config_reg
+
+
+0XE000D000
+
+32
+
+RW
+
+0x000000
+
+SPI configuration register
+
    
+
+CTRL
+
+
+0XF8007000
+
+32
+
+RW
+
+0x000000
+
+Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.
+
    
+
+DIRM_0
+
+
+0XE000A204
+
+32
+
+RW
+
+0x000000
+
+Direction mode (GPIO Bank0, MIO)
+
    
+
+MASK_DATA_0_LSW
+
+
+0XE000A000
+
+32
+
+RW
+
+0x000000
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
+OEN_0
+
+
+0XE000A208
+
+32
+
+RW
+
+0x000000
+
+Output enable (GPIO Bank0, MIO)
+
    
+
+MASK_DATA_0_LSW
+
+
+0XE000A000
+
+32
+
+RW
+
+0x000000
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
+MASK_DATA_0_LSW
+
+
+0XE000A000
+
+32
+
+RW
+
+0x000000
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
+DIRM_0
+
+
+0XE000A204
+
+32
+
+RW
+
+0x000000
+
+Direction mode (GPIO Bank0, MIO)
+
    
+
+MASK_DATA_0_LSW
+
+
+0XE000A000
+
+32
+
+RW
+
+0x000000
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
+OEN_0
+
+
+0XE000A208
+
+32
+
+RW
+
+0x000000
+
+Output enable (GPIO Bank0, MIO)
+
    
+
+MASK_DATA_0_LSW
+
+
+0XE000A000
+
+32
+
+RW
+
+0x000000
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
+MASK_DATA_0_LSW
+
+
+0XE000A000
+
+32
+
+RW
+
+0x000000
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
+DIRM_0
+
+
+0XE000A204
+
+32
+
+RW
+
+0x000000
+
+Direction mode (GPIO Bank0, MIO)
+
    
+
+MASK_DATA_0_LSW
+
+
+0XE000A000
+
+32
+
+RW
+
+0x000000
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
+OEN_0
+
+
+0XE000A208
+
+32
+
+RW
+
+0x000000
+
+Output enable (GPIO Bank0, MIO)
+
    
+
+MASK_DATA_0_LSW
+
+
+0XE000A000
+
+32
+
+RW
+
+0x000000
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
+MASK_DATA_0_LSW
+
+
+0XE000A000
+
+32
+
+RW
+
+0x000000
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
    
+
    ps7_peripherals_init_data_3_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    DDR TERM/IBUF_DISABLE_MODE SETTINGS
    
+
    Register ( slcr )DDRIOB_DATA0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA0
+
+0XF8000B48
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.
+
    
+DDRIOB_DATA0@0XF8000B48
+
+31:0
+
+180
+
+
+
+180
+
+DDR IOB Config for Data 15:0
+
    
+
    
+
    Register ( slcr )DDRIOB_DATA1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA1
+
+0XF8000B4C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.
+
    
+DDRIOB_DATA1@0XF8000B4C
+
+31:0
+
+180
+
+
+
+180
+
+DDR IOB Config for Data 31:16
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF0
+
+0XF8000B50
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.
+
    
+DDRIOB_DIFF0@0XF8000B50
+
+31:0
+
+180
+
+
+
+180
+
+DDR IOB Config for DQS 1:0
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF1
+
+0XF8000B54
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes.
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes.
+
    
+DDRIOB_DIFF1@0XF8000B54
+
+31:0
+
+180
+
+
+
+180
+
+DDR IOB Config for DQS 3:2
+
    
+
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
    SRAM/NOR SET OPMODE
    
+
    TRACE CURRENT PORT SIZE
    
+
    UART REGISTERS
    
+
    Register ( slcr )Baud_rate_divider_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Baud_rate_divider_reg0
+
+0XE0001034
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+BDIV
+
+7:0
+
+ff
+
+6
+
+6
+
+Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
+
    
+Baud_rate_divider_reg0@0XE0001034
+
+31:0
+
+ff
+
+
+
+6
+
+Baud Rate Divider Register
+
    
+
    
+
    Register ( slcr )Baud_rate_gen_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Baud_rate_gen_reg0
+
+0XE0001018
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CD
+
+15:0
+
+ffff
+
+3e
+
+3e
+
+Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
+
    
+Baud_rate_gen_reg0@0XE0001018
+
+31:0
+
+ffff
+
+
+
+3e
+
+Baud Rate Generator Register.
+
    
+
    
+
    Register ( slcr )Control_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Control_reg0
+
+0XE0001000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+STPBRK
+
+8:8
+
+100
+
+0
+
+0
+
+Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK.
+
    
+STTBRK
+
+7:7
+
+80
+
+0
+
+0
+
+Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.
+
    
+RSTTO
+
+6:6
+
+40
+
+0
+
+0
+
+Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed.
+
    
+TXDIS
+
+5:5
+
+20
+
+0
+
+0
+
+Transmit disable: 0: enable transmitter 1: disable transmitter
+
    
+TXEN
+
+4:4
+
+10
+
+1
+
+10
+
+Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.
+
    
+RXDIS
+
+3:3
+
+8
+
+0
+
+0
+
+Receive disable: 0: enable 1: disable, regardless of the value of RXEN
+
    
+RXEN
+
+2:2
+
+4
+
+1
+
+4
+
+Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.
+
    
+TXRES
+
+1:1
+
+2
+
+1
+
+2
+
+Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed.
+
    
+RXRES
+
+0:0
+
+1
+
+1
+
+1
+
+Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed.
+
    
+Control_reg0@0XE0001000
+
+31:0
+
+1ff
+
+
+
+17
+
+UART Control Register
+
    
+
    
+
    Register ( slcr )mode_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+mode_reg0
+
+0XE0001004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CHMODE
+
+9:8
+
+300
+
+0
+
+0
+
+Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback
+
    
+NBSTOP
+
+7:6
+
+c0
+
+0
+
+0
+
+Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved
+
    
+PAR
+
+5:3
+
+38
+
+4
+
+20
+
+Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity
+
    
+CHRL
+
+2:1
+
+6
+
+0
+
+0
+
+Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits
+
    
+CLKS
+
+0:0
+
+1
+
+0
+
+0
+
+Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8
+
    
+mode_reg0@0XE0001004
+
+31:0
+
+3ff
+
+
+
+20
+
+UART Mode Register
+
    
+
    
+
    QSPI REGISTERS
    
+
    Register ( slcr )Config_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Config_reg
+
+0XE000D000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+Holdb_dr
+
+19:19
+
+80000
+
+1
+
+80000
+
+If set, Holdb and WPn pins are actively driven by the qspi controller in 1-bit and 2-bit modes . If not set, then external pull up is required on HOLDb and WPn pins . Note that this bit doesn't affect the quad(4-bit) mode as Controller always drives these pins in quad mode. It is highly recommended to set this bit always(irrespective of mode of operation) while using QSPI
+
    
+Config_reg@0XE000D000
+
+31:0
+
+80000
+
+
+
+80000
+
+SPI configuration register
+
    
+
    
+
    PL POWER ON RESET REGISTERS
    
+
    Register ( slcr )CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CTRL
+
+0XF8007000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PCFG_POR_CNT_4K
+
+29:29
+
+20000000
+
+0
+
+0
+
+This register controls which POR timer the PL will use for power-up. 0 - Use 64k timer 1 - Use 4k timer
+
    
+CTRL@0XF8007000
+
+31:0
+
+20000000
+
+
+
+0
+
+Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.
+
    
+
    
+
    SMC TIMING CALCULATION REGISTER UPDATE
    
+
    NAND SET CYCLE
    
+
    OPMODE
    
+
    DIRECT COMMAND
    
+
    SRAM/NOR CS0 SET CYCLE
    
+
    DIRECT COMMAND
    
+
    NOR CS0 BASE ADDRESS
    
+
    SRAM/NOR CS1 SET CYCLE
    
+
    DIRECT COMMAND
    
+
    NOR CS1 BASE ADDRESS
    
+
    USB RESET
    
+
    DIR MODE BANK 0
    
+
    Register ( slcr )DIRM_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DIRM_0
+
+0XE000A204
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DIRECTION_0
+
+31:0
+
+ffffffff
+
+2880
+
+2880
+
+Direction mode 0: input 1: output Each bit configures the corresponding pin within the 32-bit bank NOTE: bits[8:7] of bank0 cannot be used as inputs. The DIRM bits can be set to 0, but reading DATA_RO does not reflect the input value. See the GPIO chapter for more information.
+
    
+DIRM_0@0XE000A204
+
+31:0
+
+ffffffff
+
+
+
+2880
+
+Direction mode (GPIO Bank0, MIO)
+
    
+
    
+
    DIR MODE BANK 1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    Register ( slcr )MASK_DATA_0_LSW
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASK_DATA_0_LSW
+
+0XE000A000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+MASK_0_LSW
+
+31:16
+
+ffff0000
+
+ff7f
+
+ff7f0000
+
+On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's.
+
    
+DATA_0_LSW
+
+15:0
+
+ffff
+
+80
+
+80
+
+On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin.
+
    
+MASK_DATA_0_LSW@0XE000A000
+
+31:0
+
+ffffffff
+
+
+
+ff7f0080
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE BANK 0
    
+
    Register ( slcr )OEN_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+OEN_0
+
+0XE000A208
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+OP_ENABLE_0
+
+31:0
+
+ffffffff
+
+2880
+
+2880
+
+Output enables 0: disabled 1: enabled Each bit configures the corresponding pin within the 32-bit bank
+
    
+OEN_0@0XE000A208
+
+31:0
+
+ffffffff
+
+
+
+2880
+
+Output enable (GPIO Bank0, MIO)
+
    
+
    
+
    OUTPUT ENABLE BANK 1
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    Register ( slcr )MASK_DATA_0_LSW
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASK_DATA_0_LSW
+
+0XE000A000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+MASK_0_LSW
+
+31:16
+
+ffff0000
+
+ff7f
+
+ff7f0000
+
+On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's.
+
    
+DATA_0_LSW
+
+15:0
+
+ffff
+
+0
+
+0
+
+On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin.
+
    
+MASK_DATA_0_LSW@0XE000A000
+
+31:0
+
+ffffffff
+
+
+
+ff7f0000
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    Register ( slcr )MASK_DATA_0_LSW
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASK_DATA_0_LSW
+
+0XE000A000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+MASK_0_LSW
+
+31:16
+
+ffff0000
+
+ff7f
+
+ff7f0000
+
+On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's.
+
    
+DATA_0_LSW
+
+15:0
+
+ffff
+
+80
+
+80
+
+On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin.
+
    
+MASK_DATA_0_LSW@0XE000A000
+
+31:0
+
+ffffffff
+
+
+
+ff7f0080
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    ENET RESET
    
+
    DIR MODE BANK 0
    
+
    Register ( slcr )DIRM_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DIRM_0
+
+0XE000A204
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DIRECTION_0
+
+31:0
+
+ffffffff
+
+2880
+
+2880
+
+Direction mode 0: input 1: output Each bit configures the corresponding pin within the 32-bit bank NOTE: bits[8:7] of bank0 cannot be used as inputs. The DIRM bits can be set to 0, but reading DATA_RO does not reflect the input value. See the GPIO chapter for more information.
+
    
+DIRM_0@0XE000A204
+
+31:0
+
+ffffffff
+
+
+
+2880
+
+Direction mode (GPIO Bank0, MIO)
+
    
+
    
+
    DIR MODE BANK 1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    Register ( slcr )MASK_DATA_0_LSW
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASK_DATA_0_LSW
+
+0XE000A000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+MASK_0_LSW
+
+31:16
+
+ffff0000
+
+f7ff
+
+f7ff0000
+
+On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's.
+
    
+DATA_0_LSW
+
+15:0
+
+ffff
+
+800
+
+800
+
+On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin.
+
    
+MASK_DATA_0_LSW@0XE000A000
+
+31:0
+
+ffffffff
+
+
+
+f7ff0800
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE BANK 0
    
+
    Register ( slcr )OEN_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+OEN_0
+
+0XE000A208
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+OP_ENABLE_0
+
+31:0
+
+ffffffff
+
+2880
+
+2880
+
+Output enables 0: disabled 1: enabled Each bit configures the corresponding pin within the 32-bit bank
+
    
+OEN_0@0XE000A208
+
+31:0
+
+ffffffff
+
+
+
+2880
+
+Output enable (GPIO Bank0, MIO)
+
    
+
    
+
    OUTPUT ENABLE BANK 1
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    Register ( slcr )MASK_DATA_0_LSW
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASK_DATA_0_LSW
+
+0XE000A000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+MASK_0_LSW
+
+31:16
+
+ffff0000
+
+f7ff
+
+f7ff0000
+
+On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's.
+
    
+DATA_0_LSW
+
+15:0
+
+ffff
+
+0
+
+0
+
+On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin.
+
    
+MASK_DATA_0_LSW@0XE000A000
+
+31:0
+
+ffffffff
+
+
+
+f7ff0000
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    Register ( slcr )MASK_DATA_0_LSW
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASK_DATA_0_LSW
+
+0XE000A000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+MASK_0_LSW
+
+31:16
+
+ffff0000
+
+f7ff
+
+f7ff0000
+
+On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's.
+
    
+DATA_0_LSW
+
+15:0
+
+ffff
+
+800
+
+800
+
+On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin.
+
    
+MASK_DATA_0_LSW@0XE000A000
+
+31:0
+
+ffffffff
+
+
+
+f7ff0800
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    I2C RESET
    
+
    DIR MODE GPIO BANK0
    
+
    Register ( slcr )DIRM_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DIRM_0
+
+0XE000A204
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DIRECTION_0
+
+31:0
+
+ffffffff
+
+2880
+
+2880
+
+Direction mode 0: input 1: output Each bit configures the corresponding pin within the 32-bit bank NOTE: bits[8:7] of bank0 cannot be used as inputs. The DIRM bits can be set to 0, but reading DATA_RO does not reflect the input value. See the GPIO chapter for more information.
+
    
+DIRM_0@0XE000A204
+
+31:0
+
+ffffffff
+
+
+
+2880
+
+Direction mode (GPIO Bank0, MIO)
+
    
+
    
+
    DIR MODE GPIO BANK1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    Register ( slcr )MASK_DATA_0_LSW
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASK_DATA_0_LSW
+
+0XE000A000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+MASK_0_LSW
+
+31:16
+
+ffff0000
+
+dfff
+
+dfff0000
+
+On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's.
+
    
+DATA_0_LSW
+
+15:0
+
+ffff
+
+2000
+
+2000
+
+On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin.
+
    
+MASK_DATA_0_LSW@0XE000A000
+
+31:0
+
+ffffffff
+
+
+
+dfff2000
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE
    
+
    Register ( slcr )OEN_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+OEN_0
+
+0XE000A208
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+OP_ENABLE_0
+
+31:0
+
+ffffffff
+
+2880
+
+2880
+
+Output enables 0: disabled 1: enabled Each bit configures the corresponding pin within the 32-bit bank
+
    
+OEN_0@0XE000A208
+
+31:0
+
+ffffffff
+
+
+
+2880
+
+Output enable (GPIO Bank0, MIO)
+
    
+
    
+
    OUTPUT ENABLE
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    Register ( slcr )MASK_DATA_0_LSW
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASK_DATA_0_LSW
+
+0XE000A000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+MASK_0_LSW
+
+31:16
+
+ffff0000
+
+dfff
+
+dfff0000
+
+On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's.
+
    
+DATA_0_LSW
+
+15:0
+
+ffff
+
+0
+
+0
+
+On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin.
+
    
+MASK_DATA_0_LSW@0XE000A000
+
+31:0
+
+ffffffff
+
+
+
+dfff0000
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    Register ( slcr )MASK_DATA_0_LSW
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASK_DATA_0_LSW
+
+0XE000A000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+MASK_0_LSW
+
+31:16
+
+ffff0000
+
+dfff
+
+dfff0000
+
+On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's.
+
    
+DATA_0_LSW
+
+15:0
+
+ffff
+
+2000
+
+2000
+
+On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin.
+
    
+MASK_DATA_0_LSW@0XE000A000
+
+31:0
+
+ffffffff
+
+
+
+dfff2000
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
+
    
+
    ps7_post_config_3_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+LVL_SHFTR_EN
+
+
+0XF8000900
+
+32
+
+RW
+
+0x000000
+
+Level Shifters Enable
+
    
+
+FPGA_RST_CTRL
+
+
+0XF8000240
+
+32
+
+RW
+
+0x000000
+
+FPGA Software Reset Control
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_post_config_3_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    ENABLING LEVEL SHIFTER
    
+
    Register ( slcr )LVL_SHFTR_EN
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LVL_SHFTR_EN
+
+0XF8000900
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+USER_LVL_INP_EN_0
+
+3:3
+
+8
+
+1
+
+8
+
+Level shifter enable to drive signals from PL to PS
+
    
+USER_LVL_OUT_EN_0
+
+2:2
+
+4
+
+1
+
+4
+
+Level shifter enable to drive signals from PS to PL
+
    
+USER_LVL_INP_EN_1
+
+1:1
+
+2
+
+1
+
+2
+
+Level shifter enable to drive signals from PL to PS
+
    
+USER_LVL_OUT_EN_1
+
+0:0
+
+1
+
+1
+
+1
+
+Level shifter enable to drive signals from PS to PL
+
    
+LVL_SHFTR_EN@0XF8000900
+
+31:0
+
+f
+
+
+
+f
+
+Level Shifters Enable
+
    
+
    
+
    FPGA RESETS TO 0
    
+
    Register ( slcr )FPGA_RST_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+FPGA_RST_CTRL
+
+0XF8000240
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_3
+
+31:25
+
+fe000000
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is zero.
+
    
+reserved_FPGA_ACP_RST
+
+24:24
+
+1000000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_FPGA_AXDS3_RST
+
+23:23
+
+800000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_FPGA_AXDS2_RST
+
+22:22
+
+400000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_FPGA_AXDS1_RST
+
+21:21
+
+200000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_FPGA_AXDS0_RST
+
+20:20
+
+100000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_2
+
+19:18
+
+c0000
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is zero.
+
    
+reserved_FSSW1_FPGA_RST
+
+17:17
+
+20000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_FSSW0_FPGA_RST
+
+16:16
+
+10000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_1
+
+15:14
+
+c000
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is zero.
+
    
+reserved_FPGA_FMSW1_RST
+
+13:13
+
+2000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_FPGA_FMSW0_RST
+
+12:12
+
+1000
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_FPGA_DMA3_RST
+
+11:11
+
+800
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_FPGA_DMA2_RST
+
+10:10
+
+400
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_FPGA_DMA1_RST
+
+9:9
+
+200
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved_FPGA_DMA0_RST
+
+8:8
+
+100
+
+0
+
+0
+
+Reserved. Do not modify.
+
    
+reserved
+
+7:4
+
+f0
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is zero.
+
    
+FPGA3_OUT_RST
+
+3:3
+
+8
+
+0
+
+0
+
+PL Reset 3 (FCLKRESETN3 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN3 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state)
+
    
+FPGA2_OUT_RST
+
+2:2
+
+4
+
+0
+
+0
+
+PL Reset 2 (FCLKRESETN2 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN2 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state)
+
    
+FPGA1_OUT_RST
+
+1:1
+
+2
+
+0
+
+0
+
+PL Reset 1 (FCLKRESETN1 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN1 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state)
+
    
+FPGA0_OUT_RST
+
+0:0
+
+1
+
+0
+
+0
+
+PL Reset 0 (FCLKRESETN0 output signal). Refer to the PS7 wrapper in EDK for possible signal inversion. Logic level on the FCLKRESETN0 signal: 0: De-assert reset (High logic level). 1: Assert Reset (Low logic state)
+
    
+FPGA_RST_CTRL@0XF8000240
+
+31:0
+
+ffffffff
+
+
+
+0
+
+FPGA Software Reset Control
+
    
+
    
+
    AFI REGISTERS
    
+
    AFI0 REGISTERS
    
+
    AFI1 REGISTERS
    
+
    AFI2 REGISTERS
    
+
    AFI3 REGISTERS
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_debug_3_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+LAR
+
+
+0XF8898FB0
+
+32
+
+WO
+
+0x000000
+
+Lock Access Register
+
    
+
+LAR
+
+
+0XF8899FB0
+
+32
+
+WO
+
+0x000000
+
+Lock Access Register
+
    
+
+LAR
+
+
+0XF8809FB0
+
+32
+
+WO
+
+0x000000
+
+Lock Access Register
+
    
+
    
+
    ps7_debug_3_0
    
+
+
+
+
+
+
+
+
+
+
    CROSS TRIGGER CONFIGURATIONS
    
+
    UNLOCKING CTI REGISTERS
    
+
    Register ( slcr )LAR
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LAR
+
+0XF8898FB0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+KEY
+
+31:0
+
+ffffffff
+
+c5acce55
+
+c5acce55
+
+Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
+
    
+LAR@0XF8898FB0
+
+31:0
+
+ffffffff
+
+
+
+c5acce55
+
+Lock Access Register
+
    
+
    
+
    Register ( slcr )LAR
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LAR
+
+0XF8899FB0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+KEY
+
+31:0
+
+ffffffff
+
+c5acce55
+
+c5acce55
+
+Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
+
    
+LAR@0XF8899FB0
+
+31:0
+
+ffffffff
+
+
+
+c5acce55
+
+Lock Access Register
+
    
+
    
+
    Register ( slcr )LAR
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LAR
+
+0XF8809FB0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+KEY
+
+31:0
+
+ffffffff
+
+c5acce55
+
+c5acce55
+
+Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
+
    
+LAR@0XF8809FB0
+
+31:0
+
+ffffffff
+
+
+
+c5acce55
+
+Lock Access Register
+
    
+
    
+
    ENABLING CTI MODULES AND CHANNELS
    
+
    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
    
+
+
    
+
+
+
+
+
    ps7_pll_init_data_2_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+ARM_PLL_CFG
+
+
+0XF8000110
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Configuration
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_CLK_CTRL
+
+
+0XF8000120
+
+32
+
+RW
+
+0x000000
+
+CPU Clock Control
+
    
+
+DDR_PLL_CFG
+
+
+0XF8000114
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Configuration
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_CLK_CTRL
+
+
+0XF8000124
+
+32
+
+RW
+
+0x000000
+
+DDR Clock Control
+
    
+
+IO_PLL_CFG
+
+
+0XF8000118
+
+32
+
+RW
+
+0x000000
+
+IO PLL Configuration
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_pll_init_data_2_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    PLL SLCR REGISTERS
    
+
    ARM PLL INIT
    
+
    Register ( slcr )ARM_PLL_CFG
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CFG
+
+0XF8000110
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RES
+
+7:4
+
+f0
+
+2
+
+20
+
+Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control
+
    
+PLL_CP
+
+11:8
+
+f00
+
+2
+
+200
+
+Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control
+
    
+LOCK_CNT
+
+21:12
+
+3ff000
+
+fa
+
+fa000
+
+Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked.
+
    
+ARM_PLL_CFG@0XF8000110
+
+31:0
+
+3ffff0
+
+
+
+fa220
+
+ARM PLL Configuration
+
    
+
    
+
    UPDATE FB_DIV
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_FDIV
+
+18:12
+
+7f000
+
+28
+
+28000
+
+Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+7f000
+
+
+
+28000
+
+ARM PLL Control
+
    
+
    
+
    BY PASS PLL
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+1
+
+10
+
+ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+10
+
+
+
+10
+
+ARM PLL Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+1
+
+1
+
+Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+1
+
+
+
+1
+
+ARM PLL Control
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+0
+
+0
+
+Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+1
+
+
+
+0
+
+ARM PLL Control
+
    
+
    
+
    CHECK PLL STATUS
    
+
    Register ( slcr )PLL_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PLL_STATUS
+
+0XF800010C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+ARM_PLL_LOCK
+
+0:0
+
+1
+
+1
+
+1
+
+ARM PLL lock status: 0: not locked, 1: locked
+
    
+PLL_STATUS@0XF800010C
+
+31:0
+
+1
+
+
+
+1
+
+tobe
+
    
+
    
+
    REMOVE PLL BY PASS
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+0
+
+0
+
+ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+10
+
+
+
+0
+
+ARM PLL Control
+
    
+
    
+
    Register ( slcr )ARM_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_CLK_CTRL
+
+0XF8000120
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select the source used to generate the CPU clock: 0x: CPU PLL 10: divided DDR PLL 11: IO PLL
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+2
+
+200
+
+Frequency divisor for the CPU clock source.
+
    
+CPU_6OR4XCLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+CPU_6x4x Clock control: 0: disable, 1: enable
+
    
+CPU_3OR2XCLKACT
+
+25:25
+
+2000000
+
+1
+
+2000000
+
+CPU_3x2x Clock control: 0: disable, 1: enable
+
    
+CPU_2XCLKACT
+
+26:26
+
+4000000
+
+1
+
+4000000
+
+CPU_2x Clock control: 0: disable, 1: enable
+
    
+CPU_1XCLKACT
+
+27:27
+
+8000000
+
+1
+
+8000000
+
+CPU_1x Clock control: 0: disable, 1: enable
+
    
+CPU_PERI_CLKACT
+
+28:28
+
+10000000
+
+1
+
+10000000
+
+Clock active: 0: Clock is disabled 1: Clock is enabled
+
    
+ARM_CLK_CTRL@0XF8000120
+
+31:0
+
+1f003f30
+
+
+
+1f000200
+
+CPU Clock Control
+
    
+
    
+
    DDR PLL INIT
    
+
    Register ( slcr )DDR_PLL_CFG
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CFG
+
+0XF8000114
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RES
+
+7:4
+
+f0
+
+2
+
+20
+
+Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control.
+
    
+PLL_CP
+
+11:8
+
+f00
+
+2
+
+200
+
+Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control.
+
    
+LOCK_CNT
+
+21:12
+
+3ff000
+
+12c
+
+12c000
+
+Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked.
+
    
+DDR_PLL_CFG@0XF8000114
+
+31:0
+
+3ffff0
+
+
+
+12c220
+
+DDR PLL Configuration
+
    
+
    
+
    UPDATE FB_DIV
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_FDIV
+
+18:12
+
+7f000
+
+20
+
+20000
+
+Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state.
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+7f000
+
+
+
+20000
+
+DDR PLL Control
+
    
+
    
+
    BY PASS PLL
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+1
+
+10
+
+Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+10
+
+
+
+10
+
+DDR PLL Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+1
+
+1
+
+Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using.
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+1
+
+
+
+1
+
+DDR PLL Control
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+0
+
+0
+
+Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using.
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+1
+
+
+
+0
+
+DDR PLL Control
+
    
+
    
+
    CHECK PLL STATUS
    
+
    Register ( slcr )PLL_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PLL_STATUS
+
+0XF800010C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DDR_PLL_LOCK
+
+1:1
+
+2
+
+1
+
+2
+
+DDR PLL lock status: 0: not locked, 1: locked
+
    
+PLL_STATUS@0XF800010C
+
+31:0
+
+2
+
+
+
+2
+
+tobe
+
    
+
    
+
    REMOVE PLL BY PASS
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+0
+
+0
+
+Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+10
+
+
+
+0
+
+DDR PLL Control
+
    
+
    
+
    Register ( slcr )DDR_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_CLK_CTRL
+
+0XF8000124
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DDR_3XCLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+DDR_3x Clock control: 0: disable, 1: enable
+
    
+DDR_2XCLKACT
+
+1:1
+
+2
+
+1
+
+2
+
+DDR_2x Clock control: 0: disable, 1: enable
+
    
+DDR_3XCLK_DIVISOR
+
+25:20
+
+3f00000
+
+2
+
+200000
+
+Frequency divisor for the ddr_3x clock
+
    
+DDR_2XCLK_DIVISOR
+
+31:26
+
+fc000000
+
+3
+
+c000000
+
+Frequency divisor for the ddr_2x clock
+
    
+DDR_CLK_CTRL@0XF8000124
+
+31:0
+
+fff00003
+
+
+
+c200003
+
+DDR Clock Control
+
    
+
    
+
    IO PLL INIT
    
+
    Register ( slcr )IO_PLL_CFG
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CFG
+
+0XF8000118
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RES
+
+7:4
+
+f0
+
+c
+
+c0
+
+Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control.
+
    
+PLL_CP
+
+11:8
+
+f00
+
+2
+
+200
+
+Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control.
+
    
+LOCK_CNT
+
+21:12
+
+3ff000
+
+145
+
+145000
+
+Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked.
+
    
+IO_PLL_CFG@0XF8000118
+
+31:0
+
+3ffff0
+
+
+
+1452c0
+
+IO PLL Configuration
+
    
+
    
+
    UPDATE FB_DIV
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_FDIV
+
+18:12
+
+7f000
+
+1e
+
+1e000
+
+Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state.
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+7f000
+
+
+
+1e000
+
+IO PLL Control
+
    
+
    
+
    BY PASS PLL
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+1
+
+10
+
+Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+10
+
+
+
+10
+
+IO PLL Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+1
+
+1
+
+Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using.
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+1
+
+
+
+1
+
+IO PLL Control
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+0
+
+0
+
+Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using.
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+1
+
+
+
+0
+
+IO PLL Control
+
    
+
    
+
    CHECK PLL STATUS
    
+
    Register ( slcr )PLL_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PLL_STATUS
+
+0XF800010C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IO_PLL_LOCK
+
+2:2
+
+4
+
+1
+
+4
+
+IO PLL lock status: 0: not locked, 1: locked
+
    
+PLL_STATUS@0XF800010C
+
+31:0
+
+4
+
+
+
+4
+
+tobe
+
    
+
    
+
    REMOVE PLL BY PASS
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+0
+
+0
+
+Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+10
+
+
+
+0
+
+IO PLL Control
+
    
+
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_clock_init_data_2_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+DCI_CLK_CTRL
+
+
+0XF8000128
+
+32
+
+RW
+
+0x000000
+
+DCI clock control
+
    
+
+GEM0_RCLK_CTRL
+
+
+0XF8000138
+
+32
+
+RW
+
+0x000000
+
+GigE 0 Rx Clock Control
+
    
+
+GEM0_CLK_CTRL
+
+
+0XF8000140
+
+32
+
+RW
+
+0x000000
+
+GigE 0 Ref Clock Control
+
    
+
+LQSPI_CLK_CTRL
+
+
+0XF800014C
+
+32
+
+RW
+
+0x000000
+
+Quad SPI Ref Clock Control
+
    
+
+SDIO_CLK_CTRL
+
+
+0XF8000150
+
+32
+
+RW
+
+0x000000
+
+SDIO Ref Clock Control
+
    
+
+UART_CLK_CTRL
+
+
+0XF8000154
+
+32
+
+RW
+
+0x000000
+
+UART Ref Clock Control
+
    
+
+CAN_CLK_CTRL
+
+
+0XF800015C
+
+32
+
+RW
+
+0x000000
+
+CAN Ref Clock Control
+
    
+
+CAN_MIOCLK_CTRL
+
+
+0XF8000160
+
+32
+
+RW
+
+0x000000
+
+CAN MIO Clock Control
+
    
+
+PCAP_CLK_CTRL
+
+
+0XF8000168
+
+32
+
+RW
+
+0x000000
+
+PCAP Clock Control
+
    
+
+FPGA0_CLK_CTRL
+
+
+0XF8000170
+
+32
+
+RW
+
+0x000000
+
+PL Clock 0 Output control
+
    
+
+FPGA1_CLK_CTRL
+
+
+0XF8000180
+
+32
+
+RW
+
+0x000000
+
+PL Clock 1 Output control
+
    
+
+FPGA2_CLK_CTRL
+
+
+0XF8000190
+
+32
+
+RW
+
+0x000000
+
+PL Clock 2 output control
+
    
+
+FPGA3_CLK_CTRL
+
+
+0XF80001A0
+
+32
+
+RW
+
+0x000000
+
+PL Clock 3 output control
+
    
+
+CLK_621_TRUE
+
+
+0XF80001C4
+
+32
+
+RW
+
+0x000000
+
+CPU Clock Ratio Mode select
+
    
+
+APER_CLK_CTRL
+
+
+0XF800012C
+
+32
+
+RW
+
+0x000000
+
+AMBA Peripheral Clock Control
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_clock_init_data_2_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    CLOCK CONTROL SLCR REGISTERS
    
+
    Register ( slcr )DCI_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DCI_CLK_CTRL
+
+0XF8000128
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+DCI clock control - 0: disable, 1: enable
+
    
+DIVISOR0
+
+13:8
+
+3f00
+
+23
+
+2300
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+3
+
+300000
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider
+
    
+DCI_CLK_CTRL@0XF8000128
+
+31:0
+
+3f03f01
+
+
+
+302301
+
+DCI clock control
+
    
+
    
+
    Register ( slcr )GEM0_RCLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+GEM0_RCLK_CTRL
+
+0XF8000138
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Ethernet Controler 0 Rx Clock control 0: disable, 1: enable
+
    
+SRCSEL
+
+4:4
+
+10
+
+0
+
+0
+
+Select the source to generate the Rx clock: 0: MIO Rx clock, 1: EMIO Rx clock
+
    
+GEM0_RCLK_CTRL@0XF8000138
+
+31:0
+
+11
+
+
+
+1
+
+GigE 0 Rx Clock Control
+
    
+
    
+
    Register ( slcr )GEM0_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+GEM0_CLK_CTRL
+
+0XF8000140
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Ethernet Controller 0 Reference Clock control 0: disable, 1: enable
+
    
+SRCSEL
+
+6:4
+
+70
+
+0
+
+0
+
+Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+8
+
+800
+
+First divisor for Ethernet controller 0 source clock.
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+5
+
+500000
+
+Second divisor for Ethernet controller 0 source clock.
+
    
+GEM0_CLK_CTRL@0XF8000140
+
+31:0
+
+3f03f71
+
+
+
+500801
+
+GigE 0 Ref Clock Control
+
    
+
    
+
    Register ( slcr )LQSPI_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LQSPI_CLK_CTRL
+
+0XF800014C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Quad SPI Controller Reference Clock control 0: disable, 1: enable
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+5
+
+500
+
+Divisor for Quad SPI Controller source clock.
+
    
+LQSPI_CLK_CTRL@0XF800014C
+
+31:0
+
+3f31
+
+
+
+501
+
+Quad SPI Ref Clock Control
+
    
+
    
+
    Register ( slcr )SDIO_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SDIO_CLK_CTRL
+
+0XF8000150
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT0
+
+0:0
+
+1
+
+1
+
+1
+
+SDIO Controller 0 Clock control. 0: disable, 1: enable
+
    
+CLKACT1
+
+1:1
+
+2
+
+0
+
+0
+
+SDIO Controller 1 Clock control. 0: disable, 1: enable
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+14
+
+1400
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+SDIO_CLK_CTRL@0XF8000150
+
+31:0
+
+3f33
+
+
+
+1401
+
+SDIO Ref Clock Control
+
    
+
    
+
    Register ( slcr )UART_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+UART_CLK_CTRL
+
+0XF8000154
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT0
+
+0:0
+
+1
+
+0
+
+0
+
+UART 0 Reference clock control. 0: disable, 1: enable
+
    
+CLKACT1
+
+1:1
+
+2
+
+1
+
+2
+
+UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+14
+
+1400
+
+Divisor for UART Controller source clock.
+
    
+UART_CLK_CTRL@0XF8000154
+
+31:0
+
+3f33
+
+
+
+1402
+
+UART Ref Clock Control
+
    
+
    
+
    Register ( slcr )CAN_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CAN_CLK_CTRL
+
+0XF800015C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT0
+
+0:0
+
+1
+
+1
+
+1
+
+CAN 0 Reference Clock active: 0: Clock is disabled 1: Clock is enabled
+
    
+CLKACT1
+
+1:1
+
+2
+
+0
+
+0
+
+CAN 1 Reference Clock active: 0: Clock is disabled 1: Clock is enabled
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.
+
    
+DIVISOR0
+
+13:8
+
+3f00
+
+e
+
+e00
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+3
+
+300000
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider.
+
    
+CAN_CLK_CTRL@0XF800015C
+
+31:0
+
+3f03f33
+
+
+
+300e01
+
+CAN Ref Clock Control
+
    
+
    
+
    Register ( slcr )CAN_MIOCLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CAN_MIOCLK_CTRL
+
+0XF8000160
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CAN0_MUX
+
+5:0
+
+3f
+
+0
+
+0
+
+CAN 0 mux selection for MIO. Setting this to zero will select MIO[0] as the clock source. Only values 0-53 are valid.
+
    
+CAN0_REF_SEL
+
+6:6
+
+40
+
+0
+
+0
+
+CAN 0 Reference Clock selection: 0: From internal PLL 1: From MIO based on the next field
+
    
+CAN1_MUX
+
+21:16
+
+3f0000
+
+0
+
+0
+
+CAN 1 mux selection for MIO. Setting this to zero will select MIO[0] as the clock source. Only values 0-53 are valid.
+
    
+CAN1_REF_SEL
+
+22:22
+
+400000
+
+0
+
+0
+
+CAN 1 Reference Clock selection: 0: From internal PLL. 1: From MIO based on the next field
+
    
+CAN_MIOCLK_CTRL@0XF8000160
+
+31:0
+
+7f007f
+
+
+
+0
+
+CAN MIO Clock Control
+
    
+
    
+
    Register ( slcr )PCAP_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PCAP_CLK_CTRL
+
+0XF8000168
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Clock active: 0: Clock is disabled 1: Clock is enabled
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+5
+
+500
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+PCAP_CLK_CTRL@0XF8000168
+
+31:0
+
+3f31
+
+
+
+501
+
+PCAP Clock Control
+
    
+
    
+
    Register ( slcr )FPGA0_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+FPGA0_CLK_CTRL
+
+0XF8000170
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.
+
    
+DIVISOR0
+
+13:8
+
+3f00
+
+14
+
+1400
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider.
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+1
+
+100000
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide
+
    
+FPGA0_CLK_CTRL@0XF8000170
+
+31:0
+
+3f03f30
+
+
+
+101400
+
+PL Clock 0 Output control
+
    
+
    
+
    Register ( slcr )FPGA1_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+FPGA1_CLK_CTRL
+
+0XF8000180
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.
+
    
+DIVISOR0
+
+13:8
+
+3f00
+
+14
+
+1400
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider.
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+1
+
+100000
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide
+
    
+FPGA1_CLK_CTRL@0XF8000180
+
+31:0
+
+3f03f30
+
+
+
+101400
+
+PL Clock 1 Output control
+
    
+
    
+
    Register ( slcr )FPGA2_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+FPGA2_CLK_CTRL
+
+0XF8000190
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.
+
    
+DIVISOR0
+
+13:8
+
+3f00
+
+14
+
+1400
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider.
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+1
+
+100000
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide
+
    
+FPGA2_CLK_CTRL@0XF8000190
+
+31:0
+
+3f03f30
+
+
+
+101400
+
+PL Clock 2 output control
+
    
+
    
+
    Register ( slcr )FPGA3_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+FPGA3_CLK_CTRL
+
+0XF80001A0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL.
+
    
+DIVISOR0
+
+13:8
+
+3f00
+
+14
+
+1400
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider.
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+1
+
+100000
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide
+
    
+FPGA3_CLK_CTRL@0XF80001A0
+
+31:0
+
+3f03f30
+
+
+
+101400
+
+PL Clock 3 output control
+
    
+
    
+
    Register ( slcr )CLK_621_TRUE
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CLK_621_TRUE
+
+0XF80001C4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLK_621_TRUE
+
+0:0
+
+1
+
+1
+
+1
+
+Select the CPU clock ration: 0: 4:2:1 1: 6:2:1
+
    
+CLK_621_TRUE@0XF80001C4
+
+31:0
+
+1
+
+
+
+1
+
+CPU Clock Ratio Mode select
+
    
+
    
+
    Register ( slcr )APER_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+APER_CLK_CTRL
+
+0XF800012C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DMA_CPU_2XCLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+DMA controller AMBA Clock control 0: disable, 1: enable
+
    
+USB0_CPU_1XCLKACT
+
+2:2
+
+4
+
+1
+
+4
+
+USB controller 0 AMBA Clock control 0: disable, 1: enable
+
    
+USB1_CPU_1XCLKACT
+
+3:3
+
+8
+
+1
+
+8
+
+USB controller 1 AMBA Clock control 0: disable, 1: enable
+
    
+GEM0_CPU_1XCLKACT
+
+6:6
+
+40
+
+1
+
+40
+
+Gigabit Ethernet 0 AMBA Clock control 0: disable, 1: enable
+
    
+GEM1_CPU_1XCLKACT
+
+7:7
+
+80
+
+0
+
+0
+
+Gigabit Ethernet 1 AMBA Clock control 0: disable, 1: enable
+
    
+SDI0_CPU_1XCLKACT
+
+10:10
+
+400
+
+1
+
+400
+
+SDIO controller 0 AMBA Clock 0: disable, 1: enable
+
    
+SDI1_CPU_1XCLKACT
+
+11:11
+
+800
+
+0
+
+0
+
+SDIO controller 1 AMBA Clock control 0: disable, 1: enable
+
    
+SPI0_CPU_1XCLKACT
+
+14:14
+
+4000
+
+0
+
+0
+
+SPI 0 AMBA Clock control 0: disable, 1: enable
+
    
+SPI1_CPU_1XCLKACT
+
+15:15
+
+8000
+
+0
+
+0
+
+SPI 1 AMBA Clock control 0: disable, 1: enable
+
    
+CAN0_CPU_1XCLKACT
+
+16:16
+
+10000
+
+1
+
+10000
+
+CAN 0 AMBA Clock control 0: disable, 1: enable
+
    
+CAN1_CPU_1XCLKACT
+
+17:17
+
+20000
+
+0
+
+0
+
+CAN 1 AMBA Clock control 0: disable, 1: enable
+
    
+I2C0_CPU_1XCLKACT
+
+18:18
+
+40000
+
+1
+
+40000
+
+I2C 0 AMBA Clock control 0: disable, 1: enable
+
    
+I2C1_CPU_1XCLKACT
+
+19:19
+
+80000
+
+1
+
+80000
+
+I2C 1 AMBA Clock control 0: disable, 1: enable
+
    
+UART0_CPU_1XCLKACT
+
+20:20
+
+100000
+
+0
+
+0
+
+UART 0 AMBA Clock control 0: disable, 1: enable
+
    
+UART1_CPU_1XCLKACT
+
+21:21
+
+200000
+
+1
+
+200000
+
+UART 1 AMBA Clock control 0: disable, 1: enable
+
    
+GPIO_CPU_1XCLKACT
+
+22:22
+
+400000
+
+1
+
+400000
+
+GPIO AMBA Clock control 0: disable, 1: enable
+
    
+LQSPI_CPU_1XCLKACT
+
+23:23
+
+800000
+
+1
+
+800000
+
+Quad SPI AMBA Clock control 0: disable, 1: enable
+
    
+SMC_CPU_1XCLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+SMC AMBA Clock control 0: disable, 1: enable
+
    
+APER_CLK_CTRL@0XF800012C
+
+31:0
+
+1ffcccd
+
+
+
+1ed044d
+
+AMBA Peripheral Clock Control
+
    
+
    
+
    THIS SHOULD BE BLANK
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_ddr_init_data_2_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+ddrc_ctrl
+
+
+0XF8006000
+
+32
+
+RW
+
+0x000000
+
+DDRC Control
+
    
+
+Two_rank_cfg
+
+
+0XF8006004
+
+32
+
+RW
+
+0x000000
+
+Two Rank Configuration
+
    
+
+HPR_reg
+
+
+0XF8006008
+
+32
+
+RW
+
+0x000000
+
+HPR Queue control
+
    
+
+LPR_reg
+
+
+0XF800600C
+
+32
+
+RW
+
+0x000000
+
+LPR Queue control
+
    
+
+WR_reg
+
+
+0XF8006010
+
+32
+
+RW
+
+0x000000
+
+WR Queue control
+
    
+
+DRAM_param_reg0
+
+
+0XF8006014
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters 0
+
    
+
+DRAM_param_reg1
+
+
+0XF8006018
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters 1
+
    
+
+DRAM_param_reg2
+
+
+0XF800601C
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters 2
+
    
+
+DRAM_param_reg3
+
+
+0XF8006020
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters 3
+
    
+
+DRAM_param_reg4
+
+
+0XF8006024
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters 4
+
    
+
+DRAM_init_param
+
+
+0XF8006028
+
+32
+
+RW
+
+0x000000
+
+DRAM Initialization Parameters
+
    
+
+DRAM_EMR_reg
+
+
+0XF800602C
+
+32
+
+RW
+
+0x000000
+
+DRAM EMR2, EMR3 access
+
    
+
+DRAM_EMR_MR_reg
+
+
+0XF8006030
+
+32
+
+RW
+
+0x000000
+
+DRAM EMR, MR access
+
    
+
+DRAM_burst8_rdwr
+
+
+0XF8006034
+
+32
+
+RW
+
+0x000000
+
+DRAM Burst 8 read/write
+
    
+
+DRAM_disable_DQ
+
+
+0XF8006038
+
+32
+
+RW
+
+0x000000
+
+DRAM Disable DQ
+
    
+
+DRAM_addr_map_bank
+
+
+0XF800603C
+
+32
+
+RW
+
+0x000000
+
+Row/Column address bits
+
    
+
+DRAM_addr_map_col
+
+
+0XF8006040
+
+32
+
+RW
+
+0x000000
+
+Column address bits
+
    
+
+DRAM_addr_map_row
+
+
+0XF8006044
+
+32
+
+RW
+
+0x000000
+
+Select DRAM row address bits
+
    
+
+DRAM_ODT_reg
+
+
+0XF8006048
+
+32
+
+RW
+
+0x000000
+
+DRAM ODT control
+
    
+
+phy_cmd_timeout_rddata_cpt
+
+
+0XF8006050
+
+32
+
+RW
+
+0x000000
+
+PHY command time out and read data capture FIFO
+
    
+
+DLL_calib
+
+
+0XF8006058
+
+32
+
+RW
+
+0x000000
+
+DLL calibration
+
    
+
+ODT_delay_hold
+
+
+0XF800605C
+
+32
+
+RW
+
+0x000000
+
+ODT delay and ODT hold
+
    
+
+ctrl_reg1
+
+
+0XF8006060
+
+32
+
+RW
+
+0x000000
+
+Controller 1
+
    
+
+ctrl_reg2
+
+
+0XF8006064
+
+32
+
+RW
+
+0x000000
+
+Controller 2
+
    
+
+ctrl_reg3
+
+
+0XF8006068
+
+32
+
+RW
+
+0x000000
+
+Controller 3
+
    
+
+ctrl_reg4
+
+
+0XF800606C
+
+32
+
+RW
+
+0x000000
+
+Controller 4
+
    
+
+ctrl_reg5
+
+
+0XF8006078
+
+32
+
+RW
+
+0x000000
+
+Controller register 5
+
    
+
+ctrl_reg6
+
+
+0XF800607C
+
+32
+
+RW
+
+0x000000
+
+Controller register 6
+
    
+
+CHE_REFRESH_TIMER01
+
+
+0XF80060A0
+
+32
+
+RW
+
+0x000000
+
+CHE_REFRESH_TIMER01
+
    
+
+CHE_T_ZQ
+
+
+0XF80060A4
+
+32
+
+RW
+
+0x000000
+
+ZQ parameters
+
    
+
+CHE_T_ZQ_Short_Interval_Reg
+
+
+0XF80060A8
+
+32
+
+RW
+
+0x000000
+
+Misc parameters
+
    
+
+deep_pwrdwn_reg
+
+
+0XF80060AC
+
+32
+
+RW
+
+0x000000
+
+Deep powerdown (LPDDR2)
+
    
+
+reg_2c
+
+
+0XF80060B0
+
+32
+
+RW
+
+0x000000
+
+Training control
+
    
+
+reg_2d
+
+
+0XF80060B4
+
+32
+
+RW
+
+0x000000
+
+Misc Debug
+
    
+
+dfi_timing
+
+
+0XF80060B8
+
+32
+
+RW
+
+0x000000
+
+DFI timing
+
    
+
+CHE_ECC_CONTROL_REG_OFFSET
+
+
+0XF80060C4
+
+32
+
+RW
+
+0x000000
+
+ECC error clear
+
    
+
+CHE_ECC_CONTROL_REG_OFFSET
+
+
+0XF80060C4
+
+32
+
+RW
+
+0x000000
+
+ECC error clear
+
    
+
+CHE_CORR_ECC_LOG_REG_OFFSET
+
+
+0XF80060C8
+
+32
+
+RW
+
+0x000000
+
+ECC error correction
+
    
+
+CHE_UNCORR_ECC_LOG_REG_OFFSET
+
+
+0XF80060DC
+
+32
+
+RW
+
+0x000000
+
+ECC unrecoverable error status
+
    
+
+CHE_ECC_STATS_REG_OFFSET
+
+
+0XF80060F0
+
+32
+
+RW
+
+0x000000
+
+ECC error count
+
    
+
+ECC_scrub
+
+
+0XF80060F4
+
+32
+
+RW
+
+0x000000
+
+ECC mode/scrub
+
    
+
+phy_rcvr_enable
+
+
+0XF8006114
+
+32
+
+RW
+
+0x000000
+
+Phy receiver enable register
+
    
+
+PHY_Config0
+
+
+0XF8006118
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 0.
+
    
+
+PHY_Config1
+
+
+0XF800611C
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 1.
+
    
+
+PHY_Config2
+
+
+0XF8006120
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 2.
+
    
+
+PHY_Config3
+
+
+0XF8006124
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 3.
+
    
+
+phy_init_ratio0
+
+
+0XF800612C
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 0.
+
    
+
+phy_init_ratio1
+
+
+0XF8006130
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 1.
+
    
+
+phy_init_ratio2
+
+
+0XF8006134
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 2.
+
    
+
+phy_init_ratio3
+
+
+0XF8006138
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 3.
+
    
+
+phy_rd_dqs_cfg0
+
+
+0XF8006140
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 0.
+
    
+
+phy_rd_dqs_cfg1
+
+
+0XF8006144
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 1.
+
    
+
+phy_rd_dqs_cfg2
+
+
+0XF8006148
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 2.
+
    
+
+phy_rd_dqs_cfg3
+
+
+0XF800614C
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 3.
+
    
+
+phy_wr_dqs_cfg0
+
+
+0XF8006154
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 0.
+
    
+
+phy_wr_dqs_cfg1
+
+
+0XF8006158
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 1.
+
    
+
+phy_wr_dqs_cfg2
+
+
+0XF800615C
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 2.
+
    
+
+phy_wr_dqs_cfg3
+
+
+0XF8006160
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 3.
+
    
+
+phy_we_cfg0
+
+
+0XF8006168
+
+32
+
+RW
+
+0x000000
+
+PHY FIFO write enable configuration for data slice 0.
+
    
+
+phy_we_cfg1
+
+
+0XF800616C
+
+32
+
+RW
+
+0x000000
+
+PHY FIFO write enable configuration for data slice 1.
+
    
+
+phy_we_cfg2
+
+
+0XF8006170
+
+32
+
+RW
+
+0x000000
+
+PHY FIFO write enable configuration for data slice 2.
+
    
+
+phy_we_cfg3
+
+
+0XF8006174
+
+32
+
+RW
+
+0x000000
+
+PHY FIFO write enable configuration for data slice 3.
+
    
+
+wr_data_slv0
+
+
+0XF800617C
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio config for data slice 0.
+
    
+
+wr_data_slv1
+
+
+0XF8006180
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio config for data slice 1.
+
    
+
+wr_data_slv2
+
+
+0XF8006184
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio config for data slice 2.
+
    
+
+wr_data_slv3
+
+
+0XF8006188
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio config for data slice 3.
+
    
+
+reg_64
+
+
+0XF8006190
+
+32
+
+RW
+
+0x000000
+
+Training control 2
+
    
+
+reg_65
+
+
+0XF8006194
+
+32
+
+RW
+
+0x000000
+
+Training control 3
+
    
+
+page_mask
+
+
+0XF8006204
+
+32
+
+RW
+
+0x000000
+
+Page mask
+
    
+
+axi_priority_wr_port0
+
+
+0XF8006208
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 0.
+
    
+
+axi_priority_wr_port1
+
+
+0XF800620C
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 1.
+
    
+
+axi_priority_wr_port2
+
+
+0XF8006210
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 2.
+
    
+
+axi_priority_wr_port3
+
+
+0XF8006214
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 3.
+
    
+
+axi_priority_rd_port0
+
+
+0XF8006218
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 0.
+
    
+
+axi_priority_rd_port1
+
+
+0XF800621C
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 1.
+
    
+
+axi_priority_rd_port2
+
+
+0XF8006220
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 2.
+
    
+
+axi_priority_rd_port3
+
+
+0XF8006224
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 3.
+
    
+
+lpddr_ctrl0
+
+
+0XF80062A8
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 0
+
    
+
+lpddr_ctrl1
+
+
+0XF80062AC
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 1
+
    
+
+lpddr_ctrl2
+
+
+0XF80062B0
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 2
+
    
+
+lpddr_ctrl3
+
+
+0XF80062B4
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 3
+
    
+
+ddrc_ctrl
+
+
+0XF8006000
+
+32
+
+RW
+
+0x000000
+
+DDRC Control
+
    
+
    
+
    ps7_ddr_init_data_2_0
    
+
+
+
+
+
+
+
+
+
+
    DDR INITIALIZATION
    
+
    LOCK DDR
    
+
    Register ( slcr )ddrc_ctrl
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ddrc_ctrl
+
+0XF8006000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_soft_rstb
+
+0:0
+
+1
+
+0
+
+0
+
+Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated.
+
    
+reg_ddrc_powerdown_en
+
+1:1
+
+2
+
+0
+
+0
+
+Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable
+
    
+reg_ddrc_data_bus_width
+
+3:2
+
+c
+
+0
+
+0
+
+DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved
+
    
+reg_ddrc_burst8_refresh
+
+6:4
+
+70
+
+0
+
+0
+
+Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh
+
    
+reg_ddrc_rdwr_idle_gap
+
+13:7
+
+3f80
+
+1
+
+80
+
+When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.
+
    
+reg_ddrc_dis_rd_bypass
+
+14:14
+
+4000
+
+0
+
+0
+
+Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits.
+
    
+reg_ddrc_dis_act_bypass
+
+15:15
+
+8000
+
+0
+
+0
+
+Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates.
+
    
+reg_ddrc_dis_auto_refresh
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.
+
    
+ddrc_ctrl@0XF8006000
+
+31:0
+
+1ffff
+
+
+
+80
+
+DDRC Control
+
    
+
    
+
    Register ( slcr )Two_rank_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Two_rank_cfg
+
+0XF8006004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_t_rfc_nom_x32
+
+11:0
+
+fff
+
+81
+
+81
+
+tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field.
+
    
+reg_ddrc_active_ranks
+
+13:12
+
+3000
+
+1
+
+1000
+
+Rank configuration: 01: One Rank of DDR 11: Two Ranks of DDR Others: reserved
+
    
+reg_ddrc_addrmap_cs_bit0
+
+18:14
+
+7c000
+
+0
+
+0
+
+Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0.
+
    
+reg_ddrc_wr_odt_block
+
+20:19
+
+180000
+
+1
+
+80000
+
+Block read/write scheduling cycle count when Write requires changing ODT settings 00: 1 cycle 01: 2 cycles 10: 3 cycles others: reserved
+
    
+reg_ddrc_diff_rank_rd_2cycle_gap
+
+21:21
+
+200000
+
+0
+
+0
+
+Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0: schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1: schedule 2 cycle gap for the same
+
    
+reg_ddrc_addrmap_cs_bit1
+
+26:22
+
+7c00000
+
+0
+
+0
+
+Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0.
+
    
+reg_ddrc_addrmap_open_bank
+
+27:27
+
+8000000
+
+0
+
+0
+
+Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map to Open Bank mode
+
    
+reg_ddrc_addrmap_4bank_ram
+
+28:28
+
+10000000
+
+0
+
+0
+
+Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map for 4 Bank RAMs
+
    
+Two_rank_cfg@0XF8006004
+
+31:0
+
+1fffffff
+
+
+
+81081
+
+Two Rank Configuration
+
    
+
    
+
    Register ( slcr )HPR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+HPR_reg
+
+0XF8006008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_hpr_min_non_critical_x32
+
+10:0
+
+7ff
+
+f
+
+f
+
+Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks).
+
    
+reg_ddrc_hpr_max_starve_x32
+
+21:11
+
+3ff800
+
+f
+
+7800
+
+Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks
+
    
+reg_ddrc_hpr_xact_run_length
+
+25:22
+
+3c00000
+
+f
+
+3c00000
+
+Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available.
+
    
+HPR_reg@0XF8006008
+
+31:0
+
+3ffffff
+
+
+
+3c0780f
+
+HPR Queue control
+
    
+
    
+
    Register ( slcr )LPR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LPR_reg
+
+0XF800600C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_lpr_min_non_critical_x32
+
+10:0
+
+7ff
+
+1
+
+1
+
+Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks
+
    
+reg_ddrc_lpr_max_starve_x32
+
+21:11
+
+3ff800
+
+2
+
+1000
+
+Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks
+
    
+reg_ddrc_lpr_xact_run_length
+
+25:22
+
+3c00000
+
+8
+
+2000000
+
+Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available
+
    
+LPR_reg@0XF800600C
+
+31:0
+
+3ffffff
+
+
+
+2001001
+
+LPR Queue control
+
    
+
    
+
    Register ( slcr )WR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+WR_reg
+
+0XF8006010
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_w_min_non_critical_x32
+
+10:0
+
+7ff
+
+1
+
+1
+
+Number of clock cycles that the WR queue is guaranteed to be non-critical.
+
    
+reg_ddrc_w_xact_run_length
+
+14:11
+
+7800
+
+8
+
+4000
+
+Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available
+
    
+reg_ddrc_w_max_starve_x32
+
+25:15
+
+3ff8000
+
+2
+
+10000
+
+Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY.
+
    
+WR_reg@0XF8006010
+
+31:0
+
+3ffffff
+
+
+
+14001
+
+WR Queue control
+
    
+
    
+
    Register ( slcr )DRAM_param_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg0
+
+0XF8006014
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_t_rc
+
+5:0
+
+3f
+
+1b
+
+1b
+
+tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3.
+
    
+reg_ddrc_t_rfc_min
+
+13:6
+
+3fc0
+
+56
+
+1580
+
+tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field.
+
    
+reg_ddrc_post_selfref_gap_x32
+
+20:14
+
+1fc000
+
+10
+
+40000
+
+Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related
+
    
+DRAM_param_reg0@0XF8006014
+
+31:0
+
+1fffff
+
+
+
+4159b
+
+DRAM Parameters 0
+
    
+
    
+
    Register ( slcr )DRAM_param_reg1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg1
+
+0XF8006018
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_wr2pre
+
+4:0
+
+1f
+
+12
+
+12
+
+Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs.
+
    
+reg_ddrc_powerdown_to_x32
+
+9:5
+
+3e0
+
+6
+
+c0
+
+After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks.
+
    
+reg_ddrc_t_faw
+
+15:10
+
+fc00
+
+10
+
+4000
+
+tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related.
+
    
+reg_ddrc_t_ras_max
+
+21:16
+
+3f0000
+
+24
+
+240000
+
+tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related.
+
    
+reg_ddrc_t_ras_min
+
+26:22
+
+7c00000
+
+14
+
+5000000
+
+tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3.
+
    
+reg_ddrc_t_cke
+
+31:28
+
+f0000000
+
+4
+
+40000000
+
+Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks.
+
    
+DRAM_param_reg1@0XF8006018
+
+31:0
+
+f7ffffff
+
+
+
+452440d2
+
+DRAM Parameters 1
+
    
+
    
+
    Register ( slcr )DRAM_param_reg2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg2
+
+0XF800601C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_write_latency
+
+4:0
+
+1f
+
+5
+
+5
+
+Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related.
+
    
+reg_ddrc_rd2wr
+
+9:5
+
+3e0
+
+7
+
+e0
+
+Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED.
+
    
+reg_ddrc_wr2rd
+
+14:10
+
+7c00
+
+e
+
+3800
+
+Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs.
+
    
+reg_ddrc_t_xp
+
+19:15
+
+f8000
+
+4
+
+20000
+
+tXP: Minimum time after power down exit to any operation. DRAM related.
+
    
+reg_ddrc_pad_pd
+
+22:20
+
+700000
+
+0
+
+0
+
+If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks.
+
    
+reg_ddrc_rd2pre
+
+27:23
+
+f800000
+
+4
+
+2000000
+
+Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related.
+
    
+reg_ddrc_t_rcd
+
+31:28
+
+f0000000
+
+7
+
+70000000
+
+tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related.
+
    
+DRAM_param_reg2@0XF800601C
+
+31:0
+
+ffffffff
+
+
+
+720238e5
+
+DRAM Parameters 2
+
    
+
    
+
    Register ( slcr )DRAM_param_reg3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg3
+
+0XF8006020
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_t_ccd
+
+4:2
+
+1c
+
+4
+
+10
+
+tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related.
+
    
+reg_ddrc_t_rrd
+
+7:5
+
+e0
+
+4
+
+80
+
+tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED
+
    
+reg_ddrc_refresh_margin
+
+11:8
+
+f00
+
+2
+
+200
+
+Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value.
+
    
+reg_ddrc_t_rp
+
+15:12
+
+f000
+
+7
+
+7000
+
+tRP - Minimum time from precharge to activate of same bank. DRAM RELATED
+
    
+reg_ddrc_refresh_to_x32
+
+20:16
+
+1f0000
+
+8
+
+80000
+
+If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field.
+
    
+reg_ddrc_sdram
+
+21:21
+
+200000
+
+1
+
+200000
+
+1: sdram device 0: non-sdram device
+
    
+reg_ddrc_mobile
+
+22:22
+
+400000
+
+0
+
+0
+
+0: DDR2 or DDR3 device. 1: LPDDR2 device.
+
    
+reg_ddrc_clock_stop_en
+
+23:23
+
+800000
+
+0
+
+0
+
+DDR2 and DDR3: not used. LPDDR2: 0: stop_clk will never be asserted. 1: enable the assertion of stop_clk to the PHY whenever a clock is not required
+
    
+reg_ddrc_read_latency
+
+28:24
+
+1f000000
+
+7
+
+7000000
+
+Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock.
+
    
+reg_phy_mode_ddr1_ddr2
+
+29:29
+
+20000000
+
+1
+
+20000000
+
+unused
+
    
+reg_ddrc_dis_pad_pd
+
+30:30
+
+40000000
+
+0
+
+0
+
+1: disable the pad power down feature 0: Enable the pad power down feature.
+
    
+reg_ddrc_loopback
+
+31:31
+
+80000000
+
+0
+
+0
+
+unused
+
    
+DRAM_param_reg3@0XF8006020
+
+31:0
+
+fffffffc
+
+
+
+27287290
+
+DRAM Parameters 3
+
    
+
    
+
    Register ( slcr )DRAM_param_reg4
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg4
+
+0XF8006024
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_en_2t_timing_mode
+
+0:0
+
+1
+
+0
+
+0
+
+1: DDRC will use 2T timing 0: DDRC will use 1T timing
+
    
+reg_ddrc_prefer_write
+
+1:1
+
+2
+
+0
+
+0
+
+1: Bank selector prefers writes over reads
+
    
+reg_ddrc_max_rank_rd
+
+5:2
+
+3c
+
+f
+
+3c
+
+Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY.
+
    
+reg_ddrc_mr_wr
+
+6:6
+
+40
+
+0
+
+0
+
+A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low.
+
    
+reg_ddrc_mr_addr
+
+8:7
+
+180
+
+0
+
+0
+
+DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3
+
    
+reg_ddrc_mr_data
+
+24:9
+
+1fffe00
+
+0
+
+0
+
+DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0].
+
    
+ddrc_reg_mr_wr_busy
+
+25:25
+
+2000000
+
+0
+
+0
+
+Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress.
+
    
+reg_ddrc_mr_type
+
+26:26
+
+4000000
+
+0
+
+0
+
+Indicates whether the Mode register operation is read or write 0: write 1: read
+
    
+reg_ddrc_mr_rdata_valid
+
+27:27
+
+8000000
+
+0
+
+0
+
+This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9.
+
    
+DRAM_param_reg4@0XF8006024
+
+31:0
+
+fffffff
+
+
+
+3c
+
+DRAM Parameters 4
+
    
+
    
+
    Register ( slcr )DRAM_init_param
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_init_param
+
+0XF8006028
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_final_wait_x32
+
+6:0
+
+7f
+
+7
+
+7
+
+Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3.
+
    
+reg_ddrc_pre_ocd_x32
+
+10:7
+
+780
+
+0
+
+0
+
+Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero.
+
    
+reg_ddrc_t_mrd
+
+13:11
+
+3800
+
+4
+
+2000
+
+tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3.
+
    
+DRAM_init_param@0XF8006028
+
+31:0
+
+3fff
+
+
+
+2007
+
+DRAM Initialization Parameters
+
    
+
    
+
    Register ( slcr )DRAM_EMR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_EMR_reg
+
+0XF800602C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_emr2
+
+15:0
+
+ffff
+
+8
+
+8
+
+DDR2 and DDR3: Value written into the DRAM EMR2 register. LPDDR2: Value written into the DRAM MR3 register.
+
    
+reg_ddrc_emr3
+
+31:16
+
+ffff0000
+
+0
+
+0
+
+DDR2 and DDR3: Value written into the DRAM EMR3 register. LPDDR2: not used.
+
    
+DRAM_EMR_reg@0XF800602C
+
+31:0
+
+ffffffff
+
+
+
+8
+
+DRAM EMR2, EMR3 access
+
    
+
    
+
    Register ( slcr )DRAM_EMR_MR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_EMR_MR_reg
+
+0XF8006030
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_mr
+
+15:0
+
+ffff
+
+930
+
+930
+
+DDR2 and DDR3: Value written into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. LPDDR2: Value written into the DRAM MR1 register
+
    
+reg_ddrc_emr
+
+31:16
+
+ffff0000
+
+4
+
+40000
+
+DDR2 and DDR3: Value written into the DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. LPDDR2: Value written into the DRAM MR2 register.
+
    
+DRAM_EMR_MR_reg@0XF8006030
+
+31:0
+
+ffffffff
+
+
+
+40930
+
+DRAM EMR, MR access
+
    
+
    
+
    Register ( slcr )DRAM_burst8_rdwr
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_burst8_rdwr
+
+0XF8006034
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_burst_rdwr
+
+3:0
+
+f
+
+4
+
+4
+
+Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved
+
    
+reg_ddrc_pre_cke_x1024
+
+13:4
+
+3ff0
+
+105
+
+1050
+
+Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min)
+
    
+reg_ddrc_post_cke_x1024
+
+25:16
+
+3ff0000
+
+1
+
+10000
+
+Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us.
+
    
+reg_ddrc_burstchop
+
+28:28
+
+10000000
+
+0
+
+0
+
+Feature not supported. When 1, Controller is out in burstchop mode.
+
    
+DRAM_burst8_rdwr@0XF8006034
+
+31:0
+
+13ff3fff
+
+
+
+11054
+
+DRAM Burst 8 read/write
+
    
+
    
+
    Register ( slcr )DRAM_disable_DQ
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_disable_DQ
+
+0XF8006038
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_force_low_pri_n
+
+0:0
+
+1
+
+0
+
+0
+
+Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers.
+
    
+reg_ddrc_dis_dq
+
+1:1
+
+2
+
+0
+
+0
+
+When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field.
+
    
+reg_phy_debug_mode
+
+6:6
+
+40
+
+0
+
+0
+
+Not Applicable in this PHY.
+
    
+reg_phy_wr_level_start
+
+7:7
+
+80
+
+0
+
+0
+
+Not Applicable in this PHY.
+
    
+reg_phy_rd_level_start
+
+8:8
+
+100
+
+0
+
+0
+
+Not Applicable in this PHY.
+
    
+reg_phy_dq0_wait_t
+
+12:9
+
+1e00
+
+0
+
+0
+
+Not Applicable in this PHY.
+
    
+DRAM_disable_DQ@0XF8006038
+
+31:0
+
+1fc3
+
+
+
+0
+
+DRAM Disable DQ
+
    
+
    
+
    Register ( slcr )DRAM_addr_map_bank
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_addr_map_bank
+
+0XF800603C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_addrmap_bank_b0
+
+3:0
+
+f
+
+7
+
+7
+
+Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_bank_b1
+
+7:4
+
+f0
+
+7
+
+70
+
+Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_bank_b2
+
+11:8
+
+f00
+
+7
+
+700
+
+Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0.
+
    
+reg_ddrc_addrmap_col_b5
+
+15:12
+
+f000
+
+0
+
+0
+
+Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9
+
    
+reg_ddrc_addrmap_col_b6
+
+19:16
+
+f0000
+
+0
+
+0
+
+Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9
+
    
+DRAM_addr_map_bank@0XF800603C
+
+31:0
+
+fffff
+
+
+
+777
+
+Row/Column address bits
+
    
+
    
+
    Register ( slcr )DRAM_addr_map_col
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_addr_map_col
+
+0XF8006040
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_addrmap_col_b2
+
+3:0
+
+f
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_col_b3
+
+7:4
+
+f0
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_col_b4
+
+11:8
+
+f00
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_col_b7
+
+15:12
+
+f000
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b8
+
+19:16
+
+f0000
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b9
+
+23:20
+
+f00000
+
+f
+
+f00000
+
+Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b10
+
+27:24
+
+f000000
+
+f
+
+f000000
+
+Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b11
+
+31:28
+
+f0000000
+
+f
+
+f0000000
+
+Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+DRAM_addr_map_col@0XF8006040
+
+31:0
+
+ffffffff
+
+
+
+fff00000
+
+Column address bits
+
    
+
    
+
    Register ( slcr )DRAM_addr_map_row
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_addr_map_row
+
+0XF8006044
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_addrmap_row_b0
+
+3:0
+
+f
+
+6
+
+6
+
+Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field
+
    
+reg_ddrc_addrmap_row_b1
+
+7:4
+
+f0
+
+6
+
+60
+
+Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_row_b2_11
+
+11:8
+
+f00
+
+6
+
+600
+
+Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_row_b12
+
+15:12
+
+f000
+
+6
+
+6000
+
+Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0.
+
    
+reg_ddrc_addrmap_row_b13
+
+19:16
+
+f0000
+
+6
+
+60000
+
+Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0.
+
    
+reg_ddrc_addrmap_row_b14
+
+23:20
+
+f00000
+
+6
+
+600000
+
+Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0.
+
    
+reg_ddrc_addrmap_row_b15
+
+27:24
+
+f000000
+
+f
+
+f000000
+
+Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0.
+
    
+DRAM_addr_map_row@0XF8006044
+
+31:0
+
+fffffff
+
+
+
+f666666
+
+Select DRAM row address bits
+
    
+
    
+
    Register ( slcr )DRAM_ODT_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_ODT_reg
+
+0XF8006048
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_rank0_rd_odt
+
+2:0
+
+7
+
+0
+
+0
+
+Unused. [1:0] - Indicates which remote ODTs must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during reads to rank 0.
+
    
+reg_ddrc_rank0_wr_odt
+
+5:3
+
+38
+
+1
+
+8
+
+[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during writes to rank 0.
+
    
+reg_ddrc_rank1_rd_odt
+
+8:6
+
+1c0
+
+1
+
+40
+
+Unused
+
    
+reg_ddrc_rank1_wr_odt
+
+11:9
+
+e00
+
+1
+
+200
+
+Unused
+
    
+reg_phy_rd_local_odt
+
+13:12
+
+3000
+
+0
+
+0
+
+Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage.
+
    
+reg_phy_wr_local_odt
+
+15:14
+
+c000
+
+3
+
+c000
+
+Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS.
+
    
+reg_phy_idle_local_odt
+
+17:16
+
+30000
+
+3
+
+30000
+
+Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle.
+
    
+reg_ddrc_rank2_rd_odt
+
+20:18
+
+1c0000
+
+0
+
+0
+
+Unused
+
    
+reg_ddrc_rank2_wr_odt
+
+23:21
+
+e00000
+
+0
+
+0
+
+Unused
+
    
+reg_ddrc_rank3_rd_odt
+
+26:24
+
+7000000
+
+0
+
+0
+
+Unused
+
    
+reg_ddrc_rank3_wr_odt
+
+29:27
+
+38000000
+
+0
+
+0
+
+Unused
+
    
+DRAM_ODT_reg@0XF8006048
+
+31:0
+
+3fffffff
+
+
+
+3c248
+
+DRAM ODT control
+
    
+
    
+
    Register ( slcr )phy_cmd_timeout_rddata_cpt
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_cmd_timeout_rddata_cpt
+
+0XF8006050
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_cmd_to_data
+
+3:0
+
+f
+
+0
+
+0
+
+Not used in DFI PHY.
+
    
+reg_phy_wr_cmd_to_data
+
+7:4
+
+f0
+
+0
+
+0
+
+Not used in DFI PHY.
+
    
+reg_phy_rdc_we_to_re_delay
+
+11:8
+
+f00
+
+8
+
+800
+
+This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1.
+
    
+reg_phy_rdc_fifo_rst_disable
+
+15:15
+
+8000
+
+0
+
+0
+
+When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty.
+
    
+reg_phy_use_fixed_re
+
+16:16
+
+10000
+
+1
+
+10000
+
+When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH.
+
    
+reg_phy_rdc_fifo_rst_err_cnt_clr
+
+17:17
+
+20000
+
+0
+
+0
+
+Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed.
+
    
+reg_phy_dis_phy_ctrl_rstn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset.
+
    
+reg_phy_clk_stall_level
+
+19:19
+
+80000
+
+0
+
+0
+
+1: stall clock, for DLL aging control
+
    
+reg_phy_gatelvl_num_of_dq0
+
+27:24
+
+f000000
+
+7
+
+7000000
+
+This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.
+
    
+reg_phy_wrlvl_num_of_dq0
+
+31:28
+
+f0000000
+
+7
+
+70000000
+
+This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.
+
    
+phy_cmd_timeout_rddata_cpt@0XF8006050
+
+31:0
+
+ff0f8fff
+
+
+
+77010800
+
+PHY command time out and read data capture FIFO
+
    
+
    
+
    Register ( slcr )DLL_calib
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DLL_calib
+
+0XF8006058
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_dll_calib_to_min_x1024
+
+7:0
+
+ff
+
+1
+
+1
+
+Unused in DFI Controller.
+
    
+reg_ddrc_dll_calib_to_max_x1024
+
+15:8
+
+ff00
+
+1
+
+100
+
+Unused in DFI Controller.
+
    
+reg_ddrc_dis_dll_calib
+
+16:16
+
+10000
+
+0
+
+0
+
+When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically
+
    
+DLL_calib@0XF8006058
+
+31:0
+
+1ffff
+
+
+
+101
+
+DLL calibration
+
    
+
    
+
    Register ( slcr )ODT_delay_hold
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ODT_delay_hold
+
+0XF800605C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_rd_odt_delay
+
+3:0
+
+f
+
+3
+
+3
+
+UNUSED
+
    
+reg_ddrc_wr_odt_delay
+
+7:4
+
+f0
+
+0
+
+0
+
+The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2.
+
    
+reg_ddrc_rd_odt_hold
+
+11:8
+
+f00
+
+0
+
+0
+
+Unused
+
    
+reg_ddrc_wr_odt_hold
+
+15:12
+
+f000
+
+5
+
+5000
+
+Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4
+
    
+ODT_delay_hold@0XF800605C
+
+31:0
+
+ffff
+
+
+
+5003
+
+ODT delay and ODT hold
+
    
+
    
+
    Register ( slcr )ctrl_reg1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg1
+
+0XF8006060
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_pageclose
+
+0:0
+
+1
+
+0
+
+0
+
+If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used.
+
    
+reg_ddrc_lpr_num_entries
+
+6:1
+
+7e
+
+1f
+
+3e
+
+Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored.
+
    
+reg_ddrc_auto_pre_en
+
+7:7
+
+80
+
+0
+
+0
+
+When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.)
+
    
+reg_ddrc_refresh_update_level
+
+8:8
+
+100
+
+0
+
+0
+
+Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field.
+
    
+reg_ddrc_dis_wc
+
+9:9
+
+200
+
+0
+
+0
+
+Disable Write Combine: 0: enable 1: disable
+
    
+reg_ddrc_dis_collision_page_opt
+
+10:10
+
+400
+
+0
+
+0
+
+When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word).
+
    
+reg_ddrc_selfref_en
+
+12:12
+
+1000
+
+0
+
+0
+
+If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field.
+
    
+ctrl_reg1@0XF8006060
+
+31:0
+
+17ff
+
+
+
+3e
+
+Controller 1
+
    
+
    
+
    Register ( slcr )ctrl_reg2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg2
+
+0XF8006064
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_go2critical_hysteresis
+
+12:5
+
+1fe0
+
+0
+
+0
+
+Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0.
+
    
+reg_arb_go2critical_en
+
+17:17
+
+20000
+
+1
+
+20000
+
+0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master.
+
    
+ctrl_reg2@0XF8006064
+
+31:0
+
+21fe0
+
+
+
+20000
+
+Controller 2
+
    
+
    
+
    Register ( slcr )ctrl_reg3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg3
+
+0XF8006068
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_wrlvl_ww
+
+7:0
+
+ff
+
+41
+
+41
+
+DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50)
+
    
+reg_ddrc_rdlvl_rr
+
+15:8
+
+ff00
+
+41
+
+4100
+
+DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode.
+
    
+reg_ddrc_dfi_t_wlmrd
+
+25:16
+
+3ff0000
+
+28
+
+280000
+
+DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec.
+
    
+ctrl_reg3@0XF8006068
+
+31:0
+
+3ffffff
+
+
+
+284141
+
+Controller 3
+
    
+
    
+
    Register ( slcr )ctrl_reg4
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg4
+
+0XF800606C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+dfi_t_ctrlupd_interval_min_x1024
+
+7:0
+
+ff
+
+10
+
+10
+
+This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks
+
    
+dfi_t_ctrlupd_interval_max_x1024
+
+15:8
+
+ff00
+
+16
+
+1600
+
+This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks
+
    
+ctrl_reg4@0XF800606C
+
+31:0
+
+ffff
+
+
+
+1610
+
+Controller 4
+
    
+
    
+
    Register ( slcr )ctrl_reg5
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg5
+
+0XF8006078
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_dfi_t_ctrl_delay
+
+3:0
+
+f
+
+1
+
+1
+
+Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value.
+
    
+reg_ddrc_dfi_t_dram_clk_disable
+
+7:4
+
+f0
+
+1
+
+10
+
+Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value.
+
    
+reg_ddrc_dfi_t_dram_clk_enable
+
+11:8
+
+f00
+
+1
+
+100
+
+Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value.
+
    
+reg_ddrc_t_cksre
+
+15:12
+
+f000
+
+6
+
+6000
+
+This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE
+
    
+reg_ddrc_t_cksrx
+
+19:16
+
+f0000
+
+6
+
+60000
+
+This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX
+
    
+reg_ddrc_t_ckesr
+
+25:20
+
+3f00000
+
+4
+
+400000
+
+Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1
+
    
+ctrl_reg5@0XF8006078
+
+31:0
+
+3ffffff
+
+
+
+466111
+
+Controller register 5
+
    
+
    
+
    Register ( slcr )ctrl_reg6
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg6
+
+0XF800607C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_t_ckpde
+
+3:0
+
+f
+
+2
+
+2
+
+This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2.
+
    
+reg_ddrc_t_ckpdx
+
+7:4
+
+f0
+
+2
+
+20
+
+This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2.
+
    
+reg_ddrc_t_ckdpde
+
+11:8
+
+f00
+
+2
+
+200
+
+This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2.
+
    
+reg_ddrc_t_ckdpdx
+
+15:12
+
+f000
+
+2
+
+2000
+
+This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2.
+
    
+reg_ddrc_t_ckcsx
+
+19:16
+
+f0000
+
+3
+
+30000
+
+This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2.
+
    
+ctrl_reg6@0XF800607C
+
+31:0
+
+fffff
+
+
+
+32222
+
+Controller register 6
+
    
+
    
+
    Register ( slcr )CHE_REFRESH_TIMER01
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_REFRESH_TIMER01
+
+0XF80060A0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+refresh_timer0_start_value_x32
+
+11:0
+
+fff
+
+0
+
+0
+
+Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY.
+
    
+refresh_timer1_start_value_x32
+
+23:12
+
+fff000
+
+8
+
+8000
+
+Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY.
+
    
+CHE_REFRESH_TIMER01@0XF80060A0
+
+31:0
+
+ffffff
+
+
+
+8000
+
+CHE_REFRESH_TIMER01
+
    
+
    
+
    Register ( slcr )CHE_T_ZQ
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_T_ZQ
+
+0XF80060A4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_dis_auto_zq
+
+0:0
+
+1
+
+0
+
+0
+
+1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices.
+
    
+reg_ddrc_ddr3
+
+1:1
+
+2
+
+1
+
+2
+
+Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3.
+
    
+reg_ddrc_t_mod
+
+11:2
+
+ffc
+
+200
+
+800
+
+Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns)
+
    
+reg_ddrc_t_zq_long_nop
+
+21:12
+
+3ff000
+
+200
+
+200000
+
+DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles.
+
    
+reg_ddrc_t_zq_short_nop
+
+31:22
+
+ffc00000
+
+40
+
+10000000
+
+DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles.
+
    
+CHE_T_ZQ@0XF80060A4
+
+31:0
+
+ffffffff
+
+
+
+10200802
+
+ZQ parameters
+
    
+
    
+
    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_T_ZQ_Short_Interval_Reg
+
+0XF80060A8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+t_zq_short_interval_x1024
+
+19:0
+
+fffff
+
+cb73
+
+cb73
+
+DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles.
+
    
+dram_rstn_x1024
+
+27:20
+
+ff00000
+
+69
+
+6900000
+
+Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only.
+
    
+CHE_T_ZQ_Short_Interval_Reg@0XF80060A8
+
+31:0
+
+fffffff
+
+
+
+690cb73
+
+Misc parameters
+
    
+
    
+
    Register ( slcr )deep_pwrdwn_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+deep_pwrdwn_reg
+
+0XF80060AC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+deeppowerdown_en
+
+0:0
+
+1
+
+0
+
+0
+
+DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field.
+
    
+deeppowerdown_to_x1024
+
+8:1
+
+1fe
+
+ff
+
+1fe
+
+DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only.
+
    
+deep_pwrdwn_reg@0XF80060AC
+
+31:0
+
+1ff
+
+
+
+1fe
+
+Deep powerdown (LPDDR2)
+
    
+
    
+
    Register ( slcr )reg_2c
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_2c
+
+0XF80060B0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+dfi_wrlvl_max_x1024
+
+11:0
+
+fff
+
+fff
+
+fff
+
+Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks
+
    
+dfi_rdlvl_max_x1024
+
+23:12
+
+fff000
+
+fff
+
+fff000
+
+Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks
+
    
+ddrc_reg_twrlvl_max_error
+
+24:24
+
+1000000
+
+0
+
+0
+
+When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3.
+
    
+ddrc_reg_trdlvl_max_error
+
+25:25
+
+2000000
+
+0
+
+0
+
+DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register.
+
    
+reg_ddrc_dfi_wr_level_en
+
+26:26
+
+4000000
+
+1
+
+4000000
+
+0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs
+
    
+reg_ddrc_dfi_rd_dqs_gate_level
+
+27:27
+
+8000000
+
+1
+
+8000000
+
+0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs
+
    
+reg_ddrc_dfi_rd_data_eye_train
+
+28:28
+
+10000000
+
+1
+
+10000000
+
+DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence.
+
    
+reg_2c@0XF80060B0
+
+31:0
+
+1fffffff
+
+
+
+1cffffff
+
+Training control
+
    
+
    
+
    Register ( slcr )reg_2d
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_2d
+
+0XF80060B4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_2t_delay
+
+8:0
+
+1ff
+
+0
+
+0
+
+Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature.
+
    
+reg_ddrc_skip_ocd
+
+9:9
+
+200
+
+1
+
+200
+
+This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported.
+
    
+reg_ddrc_dis_pre_bypass
+
+10:10
+
+400
+
+0
+
+0
+
+Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY.
+
    
+reg_2d@0XF80060B4
+
+31:0
+
+7ff
+
+
+
+200
+
+Misc Debug
+
    
+
    
+
    Register ( slcr )dfi_timing
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+dfi_timing
+
+0XF80060B8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_dfi_t_rddata_en
+
+4:0
+
+1f
+
+6
+
+6
+
+Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM.
+
    
+reg_ddrc_dfi_t_ctrlup_min
+
+14:5
+
+7fe0
+
+3
+
+60
+
+Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted.
+
    
+reg_ddrc_dfi_t_ctrlup_max
+
+24:15
+
+1ff8000
+
+40
+
+200000
+
+Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert.
+
    
+dfi_timing@0XF80060B8
+
+31:0
+
+1ffffff
+
+
+
+200066
+
+DFI timing
+
    
+
    
+
    RESET ECC ERROR
    
+
    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_ECC_CONTROL_REG_OFFSET
+
+0XF80060C4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+Clear_Uncorrectable_DRAM_ECC_error
+
+0:0
+
+1
+
+1
+
+1
+
+Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters.
+
    
+Clear_Correctable_DRAM_ECC_error
+
+1:1
+
+2
+
+1
+
+2
+
+Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters.
+
    
+CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4
+
+31:0
+
+3
+
+
+
+3
+
+ECC error clear
+
    
+
    
+
    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_ECC_CONTROL_REG_OFFSET
+
+0XF80060C4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+Clear_Uncorrectable_DRAM_ECC_error
+
+0:0
+
+1
+
+0
+
+0
+
+Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters.
+
    
+Clear_Correctable_DRAM_ECC_error
+
+1:1
+
+2
+
+0
+
+0
+
+Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters.
+
    
+CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4
+
+31:0
+
+3
+
+
+
+0
+
+ECC error clear
+
    
+
    
+
    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_CORR_ECC_LOG_REG_OFFSET
+
+0XF80060C8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CORR_ECC_LOG_VALID
+
+0:0
+
+1
+
+0
+
+0
+
+Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31)
+
    
+ECC_CORRECTED_BIT_NUM
+
+7:1
+
+fe
+
+0
+
+0
+
+Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined.
+
    
+CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8
+
+31:0
+
+ff
+
+
+
+0
+
+ECC error correction
+
    
+
    
+
    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_UNCORR_ECC_LOG_REG_OFFSET
+
+0XF80060DC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNCORR_ECC_LOG_VALID
+
+0:0
+
+1
+
+0
+
+0
+
+Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31).
+
    
+CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC
+
+31:0
+
+1
+
+
+
+0
+
+ECC unrecoverable error status
+
    
+
    
+
    Register ( slcr )CHE_ECC_STATS_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_ECC_STATS_REG_OFFSET
+
+0XF80060F0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+STAT_NUM_CORR_ERR
+
+15:8
+
+ff00
+
+0
+
+0
+
+Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58).
+
    
+STAT_NUM_UNCORR_ERR
+
+7:0
+
+ff
+
+0
+
+0
+
+Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58).
+
    
+CHE_ECC_STATS_REG_OFFSET@0XF80060F0
+
+31:0
+
+ffff
+
+
+
+0
+
+ECC error count
+
    
+
    
+
    Register ( slcr )ECC_scrub
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ECC_scrub
+
+0XF80060F4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_ecc_mode
+
+2:0
+
+7
+
+0
+
+0
+
+DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved
+
    
+reg_ddrc_dis_scrub
+
+3:3
+
+8
+
+1
+
+8
+
+0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs
+
    
+ECC_scrub@0XF80060F4
+
+31:0
+
+f
+
+
+
+8
+
+ECC mode/scrub
+
    
+
    
+
    Register ( slcr )phy_rcvr_enable
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rcvr_enable
+
+0XF8006114
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_dif_on
+
+3:0
+
+f
+
+0
+
+0
+
+Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter.
+
    
+reg_phy_dif_off
+
+7:4
+
+f0
+
+0
+
+0
+
+Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used.
+
    
+phy_rcvr_enable@0XF8006114
+
+31:0
+
+ff
+
+
+
+0
+
+Phy receiver enable register
+
    
+
    
+
    Register ( slcr )PHY_Config0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config0
+
+0XF8006118
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+reserved
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+reserved
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+reserved
+
    
+reg_phy_board_lpbk_tx
+
+4:4
+
+10
+
+0
+
+0
+
+External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_board_lpbk_rx
+
+5:5
+
+20
+
+0
+
+0
+
+External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config0@0XF8006118
+
+31:0
+
+7fffffff
+
+
+
+40000001
+
+PHY configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )PHY_Config1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config1
+
+0XF800611C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+reserved
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+reserved
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+reserved
+
    
+reg_phy_board_lpbk_tx
+
+4:4
+
+10
+
+0
+
+0
+
+External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_board_lpbk_rx
+
+5:5
+
+20
+
+0
+
+0
+
+External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config1@0XF800611C
+
+31:0
+
+7fffffff
+
+
+
+40000001
+
+PHY configuration register for data slice 1.
+
    
+
    
+
    Register ( slcr )PHY_Config2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config2
+
+0XF8006120
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+reserved
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+reserved
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+reserved
+
    
+reg_phy_board_lpbk_tx
+
+4:4
+
+10
+
+0
+
+0
+
+External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_board_lpbk_rx
+
+5:5
+
+20
+
+0
+
+0
+
+External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+reserved
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+reserved
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+reserved
+
    
+reg_phy_board_lpbk_tx
+
+4:4
+
+10
+
+0
+
+0
+
+External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_board_lpbk_rx
+
+5:5
+
+20
+
+0
+
+0
+
+External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config2@0XF8006120
+
+31:0
+
+7fffffff
+
+
+
+40000001
+
+PHY configuration register for data slice 2.
+
    
+
    
+
    Register ( slcr )PHY_Config3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config3
+
+0XF8006124
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+reserved
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+reserved
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+reserved
+
    
+reg_phy_board_lpbk_tx
+
+4:4
+
+10
+
+0
+
+0
+
+External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_board_lpbk_rx
+
+5:5
+
+20
+
+0
+
+0
+
+External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config3@0XF8006124
+
+31:0
+
+7fffffff
+
+
+
+40000001
+
+PHY configuration register for data slice 3.
+
    
+
    
+
    Register ( slcr )phy_init_ratio0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio0
+
+0XF800612C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+1d
+
+1d
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+f2
+
+3c800
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio0@0XF800612C
+
+31:0
+
+fffff
+
+
+
+3c81d
+
+PHY init ratio register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_init_ratio1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio1
+
+0XF8006130
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+12
+
+12
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+d8
+
+36000
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio1@0XF8006130
+
+31:0
+
+fffff
+
+
+
+36012
+
+PHY init ratio register for data slice 1.
+
    
+
    
+
    Register ( slcr )phy_init_ratio2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio2
+
+0XF8006134
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+c
+
+c
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+de
+
+37800
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio2@0XF8006134
+
+31:0
+
+fffff
+
+
+
+3780c
+
+PHY init ratio register for data slice 2.
+
    
+
    
+
    Register ( slcr )phy_init_ratio3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio3
+
+0XF8006138
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+21
+
+21
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+ee
+
+3b800
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio3@0XF8006138
+
+31:0
+
+fffff
+
+
+
+3b821
+
+PHY init ratio register for data slice 3.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg0
+
+0XF8006140
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg0@0XF8006140
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg1
+
+0XF8006144
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg1@0XF8006144
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 1.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg2
+
+0XF8006148
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg2@0XF8006148
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 2.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg3
+
+0XF800614C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg3@0XF800614C
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 3.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg0
+
+0XF8006154
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+9d
+
+9d
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg0@0XF8006154
+
+31:0
+
+fffff
+
+
+
+9d
+
+PHY write DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg1
+
+0XF8006158
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+92
+
+92
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg1@0XF8006158
+
+31:0
+
+fffff
+
+
+
+92
+
+PHY write DQS configuration register for data slice 1.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg2
+
+0XF800615C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+8c
+
+8c
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg2@0XF800615C
+
+31:0
+
+fffff
+
+
+
+8c
+
+PHY write DQS configuration register for data slice 2.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg3
+
+0XF8006160
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+a1
+
+a1
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg3@0XF8006160
+
+31:0
+
+fffff
+
+
+
+a1
+
+PHY write DQS configuration register for data slice 3.
+
    
+
    
+
    Register ( slcr )phy_we_cfg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg0
+
+0XF8006168
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+147
+
+147
+
+Ratio value to be used when fifo_we_X_force_mode is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.
+
    
+phy_we_cfg0@0XF8006168
+
+31:0
+
+1fffff
+
+
+
+147
+
+PHY FIFO write enable configuration for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_we_cfg1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg1
+
+0XF800616C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+12d
+
+12d
+
+Ratio value to be used when fifo_we_X_force_mode is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.
+
    
+phy_we_cfg1@0XF800616C
+
+31:0
+
+1fffff
+
+
+
+12d
+
+PHY FIFO write enable configuration for data slice 1.
+
    
+
    
+
    Register ( slcr )phy_we_cfg2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg2
+
+0XF8006170
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+133
+
+133
+
+Ratio value to be used when fifo_we_X_force_mode is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.
+
    
+phy_we_cfg2@0XF8006170
+
+31:0
+
+1fffff
+
+
+
+133
+
+PHY FIFO write enable configuration for data slice 2.
+
    
+
    
+
    Register ( slcr )phy_we_cfg3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg3
+
+0XF8006174
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+143
+
+143
+
+Ratio value to be used when fifo_we_X_force_mode is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.
+
    
+phy_we_cfg3@0XF8006174
+
+31:0
+
+1fffff
+
+
+
+143
+
+PHY FIFO write enable configuration for data slice 3.
+
    
+
    
+
    Register ( slcr )wr_data_slv0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv0
+
+0XF800617C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+dd
+
+dd
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv0@0XF800617C
+
+31:0
+
+fffff
+
+
+
+dd
+
+PHY write data slave ratio config for data slice 0.
+
    
+
    
+
    Register ( slcr )wr_data_slv1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv1
+
+0XF8006180
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+d2
+
+d2
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv1@0XF8006180
+
+31:0
+
+fffff
+
+
+
+d2
+
+PHY write data slave ratio config for data slice 1.
+
    
+
    
+
    Register ( slcr )wr_data_slv2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv2
+
+0XF8006184
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+cc
+
+cc
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv2@0XF8006184
+
+31:0
+
+fffff
+
+
+
+cc
+
+PHY write data slave ratio config for data slice 2.
+
    
+
    
+
    Register ( slcr )wr_data_slv3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv3
+
+0XF8006188
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+e1
+
+e1
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv3@0XF8006188
+
+31:0
+
+fffff
+
+
+
+e1
+
+PHY write data slave ratio config for data slice 3.
+
    
+
    
+
    Register ( slcr )reg_64
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_64
+
+0XF8006190
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_loopback
+
+0:0
+
+1
+
+0
+
+0
+
+Loopback testing. 1: enable, 0: disable
+
    
+reg_phy_bl2
+
+1:1
+
+2
+
+0
+
+0
+
+Reserved for future Use.
+
    
+reg_phy_at_spd_atpg
+
+2:2
+
+4
+
+0
+
+0
+
+0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0.
+
    
+reg_phy_bist_enable
+
+3:3
+
+8
+
+0
+
+0
+
+Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback.
+
    
+reg_phy_bist_force_err
+
+4:4
+
+10
+
+0
+
+0
+
+This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error.
+
    
+reg_phy_bist_mode
+
+6:5
+
+60
+
+0
+
+0
+
+The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved
+
    
+reg_phy_invert_clkout
+
+7:7
+
+80
+
+1
+
+80
+
+Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling.
+
    
+reg_phy_all_dq_mpr_rd_resp
+
+8:8
+
+100
+
+0
+
+0
+
+0: (default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) 1: assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.)
+
    
+reg_phy_sel_logic
+
+9:9
+
+200
+
+0
+
+0
+
+Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms
+
    
+reg_phy_ctrl_slave_ratio
+
+19:10
+
+ffc00
+
+100
+
+40000
+
+Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_ctrl_slave_force
+
+20:20
+
+100000
+
+0
+
+0
+
+1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.
+
    
+reg_phy_ctrl_slave_delay
+
+27:21
+
+fe00000
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18].
+
    
+reg_phy_use_rank0_delays
+
+28:28
+
+10000000
+
+1
+
+10000000
+
+Delay selection 0: Each Rank uses its own delay 1: Rank 0 delays are used for all ranks
+
    
+reg_phy_lpddr
+
+29:29
+
+20000000
+
+0
+
+0
+
+0: DDR2 or DDR3. 1: LPDDR2.
+
    
+reg_phy_cmd_latency
+
+30:30
+
+40000000
+
+0
+
+0
+
+If set to 1, command comes to phy_ctrl through a flop.
+
    
+reg_phy_int_lpbk
+
+31:31
+
+80000000
+
+0
+
+0
+
+1: enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0.
+
    
+reg_64@0XF8006190
+
+31:0
+
+ffffffff
+
+
+
+10040080
+
+Training control 2
+
    
+
    
+
    Register ( slcr )reg_65
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_65
+
+0XF8006194
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_rl_delay
+
+4:0
+
+1f
+
+2
+
+2
+
+This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1.
+
    
+reg_phy_rd_rl_delay
+
+9:5
+
+3e0
+
+4
+
+80
+
+This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1.
+
    
+reg_phy_dll_lock_diff
+
+13:10
+
+3c00
+
+f
+
+3c00
+
+The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted
+
    
+reg_phy_use_wr_level
+
+14:14
+
+4000
+
+1
+
+4000
+
+Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure.
+
    
+reg_phy_use_rd_dqs_gate_level
+
+15:15
+
+8000
+
+1
+
+8000
+
+Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure.
+
    
+reg_phy_use_rd_data_eye_level
+
+16:16
+
+10000
+
+1
+
+10000
+
+Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure
+
    
+reg_phy_dis_calib_rst
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs
+
    
+reg_phy_ctrl_slave_delay
+
+19:18
+
+c0000
+
+0
+
+0
+
+If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value
+
    
+reg_65@0XF8006194
+
+31:0
+
+fffff
+
+
+
+1fc82
+
+Training control 3
+
    
+
    
+
    Register ( slcr )page_mask
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+page_mask
+
+0XF8006204
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_page_addr_mask
+
+31:0
+
+ffffffff
+
+0
+
+0
+
+Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match.
+
    
+page_mask@0XF8006204
+
+31:0
+
+ffffffff
+
+
+
+0
+
+Page mask
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port0
+
+0XF8006208
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_dis_rmw_portn
+
+19:19
+
+80000
+
+1
+
+80000
+
+FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.
+
    
+axi_priority_wr_port0@0XF8006208
+
+31:0
+
+f03ff
+
+
+
+803ff
+
+AXI Priority control for write port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port1
+
+0XF800620C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_dis_rmw_portn
+
+19:19
+
+80000
+
+1
+
+80000
+
+FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.
+
    
+axi_priority_wr_port1@0XF800620C
+
+31:0
+
+f03ff
+
+
+
+803ff
+
+AXI Priority control for write port 1.
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port2
+
+0XF8006210
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_dis_rmw_portn
+
+19:19
+
+80000
+
+1
+
+80000
+
+FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.
+
    
+axi_priority_wr_port2@0XF8006210
+
+31:0
+
+f03ff
+
+
+
+803ff
+
+AXI Priority control for write port 2.
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port3
+
+0XF8006214
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_dis_rmw_portn
+
+19:19
+
+80000
+
+1
+
+80000
+
+FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.
+
    
+axi_priority_wr_port3@0XF8006214
+
+31:0
+
+f03ff
+
+
+
+803ff
+
+AXI Priority control for write port 3.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port0
+
+0XF8006218
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port0@0XF8006218
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port1
+
+0XF800621C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port1@0XF800621C
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 1.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port2
+
+0XF8006220
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port2@0XF8006220
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 2.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port3
+
+0XF8006224
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port3@0XF8006224
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 3.
+
    
+
    
+
    Register ( slcr )lpddr_ctrl0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl0
+
+0XF80062A8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_lpddr2
+
+0:0
+
+1
+
+0
+
+0
+
+0: DDR2 or DDR3 in use. 1: LPDDR2 in Use.
+
    
+reg_ddrc_per_bank_refresh
+
+1:1
+
+2
+
+0
+
+0
+
+0:All bank refresh Per bank refresh allows traffic to flow to other banks. 1:Per bank refresh Per bank refresh is not supported on all LPDDR2 devices.
+
    
+reg_ddrc_derate_enable
+
+2:2
+
+4
+
+0
+
+0
+
+0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value.
+
    
+reg_ddrc_mr4_margin
+
+11:4
+
+ff0
+
+0
+
+0
+
+UNUSED
+
    
+lpddr_ctrl0@0XF80062A8
+
+31:0
+
+ff7
+
+
+
+0
+
+LPDDR2 Control 0
+
    
+
    
+
    Register ( slcr )lpddr_ctrl1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl1
+
+0XF80062AC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_mr4_read_interval
+
+31:0
+
+ffffffff
+
+0
+
+0
+
+Interval between two MR4 reads, USED to derate the timing parameters.
+
    
+lpddr_ctrl1@0XF80062AC
+
+31:0
+
+ffffffff
+
+
+
+0
+
+LPDDR2 Control 1
+
    
+
    
+
    Register ( slcr )lpddr_ctrl2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl2
+
+0XF80062B0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_min_stable_clock_x1
+
+3:0
+
+f
+
+5
+
+5
+
+Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay.
+
    
+reg_ddrc_idle_after_reset_x32
+
+11:4
+
+ff0
+
+12
+
+120
+
+Idle time after the reset command, tINIT4. Units: 32 clock cycles.
+
    
+reg_ddrc_t_mrw
+
+21:12
+
+3ff000
+
+5
+
+5000
+
+Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5.
+
    
+lpddr_ctrl2@0XF80062B0
+
+31:0
+
+3fffff
+
+
+
+5125
+
+LPDDR2 Control 2
+
    
+
    
+
    Register ( slcr )lpddr_ctrl3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl3
+
+0XF80062B4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_max_auto_init_x1024
+
+7:0
+
+ff
+
+a8
+
+a8
+
+Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us.
+
    
+reg_ddrc_dev_zqinit_x32
+
+17:8
+
+3ff00
+
+12
+
+1200
+
+ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us.
+
    
+lpddr_ctrl3@0XF80062B4
+
+31:0
+
+3ffff
+
+
+
+12a8
+
+LPDDR2 Control 3
+
    
+
    
+
    POLL ON DCI STATUS
    
+
    Register ( slcr )DDRIOB_DCI_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_STATUS
+
+0XF8000B74
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DONE
+
+13:13
+
+2000
+
+1
+
+2000
+
+DCI done signal
+
    
+DDRIOB_DCI_STATUS@0XF8000B74
+
+31:0
+
+2000
+
+
+
+2000
+
+tobe
+
    
+
    
+
    UNLOCK DDR
    
+
    Register ( slcr )ddrc_ctrl
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ddrc_ctrl
+
+0XF8006000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_soft_rstb
+
+0:0
+
+1
+
+1
+
+1
+
+Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated.
+
    
+reg_ddrc_powerdown_en
+
+1:1
+
+2
+
+0
+
+0
+
+Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable
+
    
+reg_ddrc_data_bus_width
+
+3:2
+
+c
+
+0
+
+0
+
+DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved
+
    
+reg_ddrc_burst8_refresh
+
+6:4
+
+70
+
+0
+
+0
+
+Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh
+
    
+reg_ddrc_rdwr_idle_gap
+
+13:7
+
+3f80
+
+1
+
+80
+
+When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.
+
    
+reg_ddrc_dis_rd_bypass
+
+14:14
+
+4000
+
+0
+
+0
+
+Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits.
+
    
+reg_ddrc_dis_act_bypass
+
+15:15
+
+8000
+
+0
+
+0
+
+Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates.
+
    
+reg_ddrc_dis_auto_refresh
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.
+
    
+ddrc_ctrl@0XF8006000
+
+31:0
+
+1ffff
+
+
+
+81
+
+DDRC Control
+
    
+
    
+
    CHECK DDR STATUS
    
+
    Register ( slcr )mode_sts_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+mode_sts_reg
+
+0XF8006054
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+ddrc_reg_operating_mode
+
+2:0
+
+7
+
+1
+
+1
+
+Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Power-down mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only)
+
    
+mode_sts_reg@0XF8006054
+
+31:0
+
+7
+
+
+
+1
+
+tobe
+
    
+
    
+
+
    
+
    ps7_mio_init_data_2_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+GPIOB_CTRL
+
+
+0XF8000B00
+
+32
+
+RW
+
+0x000000
+
+PS IO Buffer Control
+
    
+
+DDRIOB_ADDR0
+
+
+0XF8000B40
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Address 0
+
    
+
+DDRIOB_ADDR1
+
+
+0XF8000B44
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Address 1
+
    
+
+DDRIOB_DATA0
+
+
+0XF8000B48
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Data 15:0
+
    
+
+DDRIOB_DATA1
+
+
+0XF8000B4C
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Data 31:16
+
    
+
+DDRIOB_DIFF0
+
+
+0XF8000B50
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for DQS 1:0
+
    
+
+DDRIOB_DIFF1
+
+
+0XF8000B54
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for DQS 3:2
+
    
+
+DDRIOB_CLOCK
+
+
+0XF8000B58
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Clock Output
+
    
+
+DDRIOB_DRIVE_SLEW_ADDR
+
+
+0XF8000B5C
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Slew for Address
+
    
+
+DDRIOB_DRIVE_SLEW_DATA
+
+
+0XF8000B60
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Slew for Data
+
    
+
+DDRIOB_DRIVE_SLEW_DIFF
+
+
+0XF8000B64
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Slew for Diff
+
    
+
+DDRIOB_DRIVE_SLEW_CLOCK
+
+
+0XF8000B68
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Slew for Clock
+
    
+
+DDRIOB_DDR_CTRL
+
+
+0XF8000B6C
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Buffer Control
+
    
+
+DDRIOB_DCI_CTRL
+
+
+0XF8000B70
+
+32
+
+RW
+
+0x000000
+
+DDRIOB DCI configuration
+
    
+
+DDRIOB_DCI_CTRL
+
+
+0XF8000B70
+
+32
+
+RW
+
+0x000000
+
+DDRIOB DCI configuration
+
    
+
+DDRIOB_DCI_CTRL
+
+
+0XF8000B70
+
+32
+
+RW
+
+0x000000
+
+DDRIOB DCI configuration
+
    
+
+MIO_PIN_00
+
+
+0XF8000700
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 0 Control
+
    
+
+MIO_PIN_01
+
+
+0XF8000704
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 1 Control
+
    
+
+MIO_PIN_02
+
+
+0XF8000708
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 2 Control
+
    
+
+MIO_PIN_03
+
+
+0XF800070C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 3 Control
+
    
+
+MIO_PIN_04
+
+
+0XF8000710
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 4 Control
+
    
+
+MIO_PIN_05
+
+
+0XF8000714
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 5 Control
+
    
+
+MIO_PIN_06
+
+
+0XF8000718
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 6 Control
+
    
+
+MIO_PIN_07
+
+
+0XF800071C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 7 Control
+
    
+
+MIO_PIN_08
+
+
+0XF8000720
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 8 Control
+
    
+
+MIO_PIN_09
+
+
+0XF8000724
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 9 Control
+
    
+
+MIO_PIN_10
+
+
+0XF8000728
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 10 Control
+
    
+
+MIO_PIN_11
+
+
+0XF800072C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 11 Control
+
    
+
+MIO_PIN_12
+
+
+0XF8000730
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 12 Control
+
    
+
+MIO_PIN_13
+
+
+0XF8000734
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 13 Control
+
    
+
+MIO_PIN_14
+
+
+0XF8000738
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 14 Control
+
    
+
+MIO_PIN_15
+
+
+0XF800073C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 15 Control
+
    
+
+MIO_PIN_16
+
+
+0XF8000740
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 16 Control
+
    
+
+MIO_PIN_17
+
+
+0XF8000744
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 17 Control
+
    
+
+MIO_PIN_18
+
+
+0XF8000748
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 18 Control
+
    
+
+MIO_PIN_19
+
+
+0XF800074C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 19 Control
+
    
+
+MIO_PIN_20
+
+
+0XF8000750
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 20 Control
+
    
+
+MIO_PIN_21
+
+
+0XF8000754
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 21 Control
+
    
+
+MIO_PIN_22
+
+
+0XF8000758
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 22 Control
+
    
+
+MIO_PIN_23
+
+
+0XF800075C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 23 Control
+
    
+
+MIO_PIN_24
+
+
+0XF8000760
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 24 Control
+
    
+
+MIO_PIN_25
+
+
+0XF8000764
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 25 Control
+
    
+
+MIO_PIN_26
+
+
+0XF8000768
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 26 Control
+
    
+
+MIO_PIN_27
+
+
+0XF800076C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 27 Control
+
    
+
+MIO_PIN_28
+
+
+0XF8000770
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 28 Control
+
    
+
+MIO_PIN_29
+
+
+0XF8000774
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 29 Control
+
    
+
+MIO_PIN_30
+
+
+0XF8000778
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 30 Control
+
    
+
+MIO_PIN_31
+
+
+0XF800077C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 31 Control
+
    
+
+MIO_PIN_32
+
+
+0XF8000780
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 32 Control
+
    
+
+MIO_PIN_33
+
+
+0XF8000784
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 33 Control
+
    
+
+MIO_PIN_34
+
+
+0XF8000788
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 34 Control
+
    
+
+MIO_PIN_35
+
+
+0XF800078C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 35 Control
+
    
+
+MIO_PIN_36
+
+
+0XF8000790
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 36 Control
+
    
+
+MIO_PIN_37
+
+
+0XF8000794
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 37 Control
+
    
+
+MIO_PIN_38
+
+
+0XF8000798
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 38 Control
+
    
+
+MIO_PIN_39
+
+
+0XF800079C
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 39 Control
+
    
+
+MIO_PIN_40
+
+
+0XF80007A0
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 40 Control
+
    
+
+MIO_PIN_41
+
+
+0XF80007A4
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 41 Control
+
    
+
+MIO_PIN_42
+
+
+0XF80007A8
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 42 Control
+
    
+
+MIO_PIN_43
+
+
+0XF80007AC
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 43 Control
+
    
+
+MIO_PIN_44
+
+
+0XF80007B0
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 44 Control
+
    
+
+MIO_PIN_45
+
+
+0XF80007B4
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 45 Control
+
    
+
+MIO_PIN_46
+
+
+0XF80007B8
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 46 Control
+
    
+
+MIO_PIN_47
+
+
+0XF80007BC
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 47 Control
+
    
+
+MIO_PIN_48
+
+
+0XF80007C0
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 48 Control
+
    
+
+MIO_PIN_49
+
+
+0XF80007C4
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 49 Control
+
    
+
+MIO_PIN_50
+
+
+0XF80007C8
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 50 Control
+
    
+
+MIO_PIN_51
+
+
+0XF80007CC
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 51 Control
+
    
+
+MIO_PIN_52
+
+
+0XF80007D0
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 52 Control
+
    
+
+MIO_PIN_53
+
+
+0XF80007D4
+
+32
+
+RW
+
+0x000000
+
+MIO Pin 53 Control
+
    
+
+SD0_WP_CD_SEL
+
+
+0XF8000830
+
+32
+
+RW
+
+0x000000
+
+SDIO 0 WP CD select
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_mio_init_data_2_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    OCM REMAPPING
    
+
    Register ( slcr )GPIOB_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+GPIOB_CTRL
+
+0XF8000B00
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+VREF_EN
+
+0:0
+
+1
+
+1
+
+1
+
+Enables VREF internal generator
+
    
+VREF_PULLUP_EN
+
+1:1
+
+2
+
+0
+
+0
+
+Enables internal pullup. 0 - no pullup. 1 - pullup.
+
    
+CLK_PULLUP_EN
+
+8:8
+
+100
+
+0
+
+0
+
+Enables internal pullup. 0: no pullup. 1: pullup.
+
    
+SRSTN_PULLUP_EN
+
+9:9
+
+200
+
+0
+
+0
+
+Enables internal pullup. 0: no pullup. 1: pullup.
+
    
+GPIOB_CTRL@0XF8000B00
+
+31:0
+
+303
+
+
+
+1
+
+PS IO Buffer Control
+
    
+
    
+
    DDRIOB SETTINGS
    
+
    Register ( slcr )DDRIOB_ADDR0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_ADDR0
+
+0XF8000B40
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+0
+
+0
+
+Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+0
+
+0
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+0
+
+0
+
+DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_ADDR0@0XF8000B40
+
+31:0
+
+fff
+
+
+
+600
+
+DDR IOB Config for Address 0
+
    
+
    
+
    Register ( slcr )DDRIOB_ADDR1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_ADDR1
+
+0XF8000B44
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+0
+
+0
+
+Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+0
+
+0
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+0
+
+0
+
+DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_ADDR1@0XF8000B44
+
+31:0
+
+fff
+
+
+
+600
+
+DDR IOB Config for Address 1
+
    
+
    
+
    Register ( slcr )DDRIOB_DATA0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA0
+
+0XF8000B48
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+1
+
+2
+
+Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_DATA0@0XF8000B48
+
+31:0
+
+fff
+
+
+
+672
+
+DDR IOB Config for Data 15:0
+
    
+
    
+
    Register ( slcr )DDRIOB_DATA1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA1
+
+0XF8000B4C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+1
+
+2
+
+Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_DATA1@0XF8000B4C
+
+31:0
+
+fff
+
+
+
+672
+
+DDR IOB Config for Data 31:16
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF0
+
+0XF8000B50
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+2
+
+4
+
+Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_DIFF0@0XF8000B50
+
+31:0
+
+fff
+
+
+
+674
+
+DDR IOB Config for DQS 1:0
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF1
+
+0XF8000B54
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+2
+
+4
+
+Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_DIFF1@0XF8000B54
+
+31:0
+
+fff
+
+
+
+674
+
+DDR IOB Config for DQS 3:2
+
    
+
    
+
    Register ( slcr )DDRIOB_CLOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_CLOCK
+
+0XF8000B58
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+0
+
+0
+
+Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+0
+
+0
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+0
+
+0
+
+DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0: no pullup 1: pullup enabled
+
    
+DDRIOB_CLOCK@0XF8000B58
+
+31:0
+
+fff
+
+
+
+600
+
+DDR IOB Config for Clock Output
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_ADDR
+
+0XF8000B5C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+DDRIO drive strength for the P devices
+
    
+DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+DDRIO drive strength for the N devices
+
    
+SLEW_P
+
+18:14
+
+7c000
+
+3
+
+c000
+
+DDRIO slew rate for the P devices
+
    
+SLEW_N
+
+23:19
+
+f80000
+
+3
+
+180000
+
+DDRIO slew rate for the N devices
+
    
+GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Test Control 000: Normal Operation 001 to 111: Test Mode
+
    
+RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Program the rterm
+
    
+DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C
+
+31:0
+
+ffffffff
+
+
+
+18c61c
+
+DDR IOB Slew for Address
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_DATA
+
+0XF8000B60
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+DDRIO drive strength for the P devices
+
    
+DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+DDRIO drive strength for the N devices
+
    
+SLEW_P
+
+18:14
+
+7c000
+
+6
+
+18000
+
+DDRIO slew rate for the P devices
+
    
+SLEW_N
+
+23:19
+
+f80000
+
+1f
+
+f80000
+
+DDRIO slew rate for the N devices
+
    
+GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Test Control 000: Normal Operation 001 to 111: Test Mode
+
    
+RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Program the rterm
+
    
+DDRIOB_DRIVE_SLEW_DATA@0XF8000B60
+
+31:0
+
+ffffffff
+
+
+
+f9861c
+
+DDR IOB Slew for Data
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_DIFF
+
+0XF8000B64
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+DDRIO drive strength for the P devices
+
    
+DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+DDRIO drive strength for the N devices
+
    
+SLEW_P
+
+18:14
+
+7c000
+
+6
+
+18000
+
+DDRIO slew rate for the P devices
+
    
+SLEW_N
+
+23:19
+
+f80000
+
+1f
+
+f80000
+
+DDRIO slew rate for the N devices
+
    
+GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Test Control 000: Normal Operation 001 to 111: Test Mode
+
    
+RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Program the rterm
+
    
+DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64
+
+31:0
+
+ffffffff
+
+
+
+f9861c
+
+DDR IOB Slew for Diff
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_CLOCK
+
+0XF8000B68
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+DDRIO drive strength for the P devices
+
    
+DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+DDRIO drive strength for the N devices
+
    
+SLEW_P
+
+18:14
+
+7c000
+
+6
+
+18000
+
+DDRIO slew rate for the P devices
+
    
+SLEW_N
+
+23:19
+
+f80000
+
+1f
+
+f80000
+
+DDRIO slew rate for the N devices
+
    
+GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Test Control 000: Normal Operation 001 to 111: Test Mode
+
    
+RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Program the rterm
+
    
+DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68
+
+31:0
+
+ffffffff
+
+
+
+f9861c
+
+DDR IOB Slew for Clock
+
    
+
    
+
    Register ( slcr )DDRIOB_DDR_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DDR_CTRL
+
+0XF8000B6C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+VREF_INT_EN
+
+0:0
+
+1
+
+1
+
+1
+
+Enables VREF internal generator
+
    
+VREF_SEL
+
+4:1
+
+1e
+
+4
+
+8
+
+Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO
+
    
+VREF_EXT_EN
+
+6:5
+
+60
+
+0
+
+0
+
+Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1X: Enable External VREF for upper 16 bits
+
    
+VREF_PULLUP_EN
+
+8:7
+
+180
+
+0
+
+0
+
+Enables VREF pull-up resistors x0: Disable VREF pull-up for lower 16 bits x1: Enable VREF pull-up for lower 16 bits 0x: Disable VREF pull-up for upper 16 bits 1x: Enable VREF pull-up for upper 16 bits
+
    
+REFIO_EN
+
+9:9
+
+200
+
+1
+
+200
+
+Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio
+
    
+REFIO_TEST
+
+11:10
+
+c00
+
+3
+
+c00
+
+Enable test mode for VRP and VRN: 00: VRP/VRN test mode not used 11: VRP/VRN test mode enabled using vref based receiver. VRP/VRN control is set using the VRN_OUT, VRP_OUT, VRN_TRI, VRP_TRI fields in the DDRIOB_DCI_CTRL register
+
    
+REFIO_PULLUP_EN
+
+12:12
+
+1000
+
+0
+
+0
+
+Enables VRP,VRN pull-up resistors 0: no pull-up 1: enable pull-up
+
    
+DRST_B_PULLUP_EN
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables pull-up resistors 0: no pull-up 1: enable pull-up
+
    
+CKE_PULLUP_EN
+
+14:14
+
+4000
+
+0
+
+0
+
+Enables pull-up resistors 0: no pull-up 1: enable pull-up
+
    
+DDRIOB_DDR_CTRL@0XF8000B6C
+
+31:0
+
+7fff
+
+
+
+e09
+
+DDR IOB Buffer Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )DDRIOB_DCI_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_CTRL
+
+0XF8000B70
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+RESET
+
+0:0
+
+1
+
+1
+
+1
+
+At least toggle once to initialise flops in DCI system
+
    
+VRN_OUT
+
+5:5
+
+20
+
+1
+
+20
+
+VRN output value
+
    
+DDRIOB_DCI_CTRL@0XF8000B70
+
+31:0
+
+21
+
+
+
+21
+
+DDRIOB DCI configuration
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )DDRIOB_DCI_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_CTRL
+
+0XF8000B70
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+RESET
+
+0:0
+
+1
+
+0
+
+0
+
+At least toggle once to initialise flops in DCI system
+
    
+VRN_OUT
+
+5:5
+
+20
+
+1
+
+20
+
+VRN output value
+
    
+DDRIOB_DCI_CTRL@0XF8000B70
+
+31:0
+
+21
+
+
+
+20
+
+DDRIOB DCI configuration
+
    
+
    
+
    Register ( slcr )DDRIOB_DCI_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_CTRL
+
+0XF8000B70
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+RESET
+
+0:0
+
+1
+
+1
+
+1
+
+At least toggle once to initialise flops in DCI system
+
    
+ENABLE
+
+1:1
+
+2
+
+1
+
+2
+
+1 if any iob's use a terminate type, or if dci test block used
+
    
+VRP_TRI
+
+2:2
+
+4
+
+0
+
+0
+
+VRP tristate value
+
    
+VRN_TRI
+
+3:3
+
+8
+
+0
+
+0
+
+VRN tristate value
+
    
+VRP_OUT
+
+4:4
+
+10
+
+0
+
+0
+
+VRP output value
+
    
+VRN_OUT
+
+5:5
+
+20
+
+1
+
+20
+
+VRN output value
+
    
+NREF_OPT1
+
+7:6
+
+c0
+
+0
+
+0
+
+Reserved
+
    
+NREF_OPT2
+
+10:8
+
+700
+
+0
+
+0
+
+Reserved
+
    
+NREF_OPT4
+
+13:11
+
+3800
+
+1
+
+800
+
+Reserved
+
    
+PREF_OPT1
+
+16:14
+
+1c000
+
+0
+
+0
+
+Reserved
+
    
+PREF_OPT2
+
+19:17
+
+e0000
+
+0
+
+0
+
+Reserved
+
    
+UPDATE_CONTROL
+
+20:20
+
+100000
+
+0
+
+0
+
+DCI Update
+
    
+INIT_COMPLETE
+
+21:21
+
+200000
+
+0
+
+0
+
+test Internal to IO bank
+
    
+TST_CLK
+
+22:22
+
+400000
+
+0
+
+0
+
+Emulate DCI clock
+
    
+TST_HLN
+
+23:23
+
+800000
+
+0
+
+0
+
+Emulate comparator output (VRN)
+
    
+TST_HLP
+
+24:24
+
+1000000
+
+0
+
+0
+
+Emulate comparator output (VRP)
+
    
+TST_RST
+
+25:25
+
+2000000
+
+0
+
+0
+
+Emulate Reset
+
    
+INT_DCI_EN
+
+26:26
+
+4000000
+
+0
+
+0
+
+Need explanation here
+
    
+DDRIOB_DCI_CTRL@0XF8000B70
+
+31:0
+
+7ffffff
+
+
+
+823
+
+DDRIOB DCI configuration
+
    
+
    
+
    MIO PROGRAMMING
    
+
    Register ( slcr )MIO_PIN_00
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_00
+
+0XF8000700
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Tri-state enable, active high. 0: disable 1: enable
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Enables pull-up on IO Buffer pin 0: disable 1: enable
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable
+
    
+MIO_PIN_00@0XF8000700
+
+31:0
+
+3f01
+
+
+
+1201
+
+MIO Pin 0 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_01
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_01
+
+0XF8000704
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: reserved
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_01@0XF8000704
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Pin 1 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_02
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_02
+
+0XF8000708
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_02@0XF8000708
+
+31:0
+
+3fff
+
+
+
+202
+
+MIO Pin 2 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_03
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_03
+
+0XF800070C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_03@0XF800070C
+
+31:0
+
+3fff
+
+
+
+202
+
+MIO Pin 3 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_04
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_04
+
+0XF8000710
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_04@0XF8000710
+
+31:0
+
+3fff
+
+
+
+202
+
+MIO Pin 4 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_05
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_05
+
+0XF8000714
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_05@0XF8000714
+
+31:0
+
+3fff
+
+
+
+202
+
+MIO Pin 5 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_06
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_06
+
+0XF8000718
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_06@0XF8000718
+
+31:0
+
+3fff
+
+
+
+202
+
+MIO Pin 6 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_07
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_07
+
+0XF800071C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B 10: NAND Flash CLE_B 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 7 Output-only (bank 0) others: reserved
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_07@0XF800071C
+
+31:0
+
+3fff
+
+
+
+200
+
+MIO Pin 7 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_08
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_08
+
+0XF8000720
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_08@0XF8000720
+
+31:0
+
+3fff
+
+
+
+202
+
+MIO Pin 8 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_09
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_09
+
+0XF8000724
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock Output
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6 10: NAND Flash IO Bit 4 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 9 (bank 0) 001: CAN 1 Rx 010 to 110: reserved 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_09@0XF8000724
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 9 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_10
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_10
+
+0XF8000728
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7 10: NAND Flash IO Bit 5 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 10 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_10@0XF8000728
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 10 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_11
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_11
+
+0XF800072C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_11@0XF800072C
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 11 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_12
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_12
+
+0XF8000730
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait 10: NAND Flash IO Bit 7 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 12 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_12@0XF8000730
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 12 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_13
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_13
+
+0XF8000734
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5 10: NAND Flash IO Bit 3 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 13 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_13@0XF8000734
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 13 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_14
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_14
+
+0XF8000738
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_14@0XF8000738
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Pin 14 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_15
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_15
+
+0XF800073C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_15@0XF800073C
+
+31:0
+
+3f01
+
+
+
+1201
+
+MIO Pin 15 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_16
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_16
+
+0XF8000740
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1 10: NAND Flash IO Bit 8 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 16 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Output 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+1
+
+2000
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_16@0XF8000740
+
+31:0
+
+3fff
+
+
+
+2802
+
+MIO Pin 16 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_17
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_17
+
+0XF8000744
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2 10: NAND Flash IO Bit 9 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 17 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110 TTC 1 Clock Input 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+1
+
+2000
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_17@0XF8000744
+
+31:0
+
+3fff
+
+
+
+2802
+
+MIO Pin 17 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_18
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_18
+
+0XF8000748
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3 10: NAND Flash IO Bit 10 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 18 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+1
+
+2000
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_18@0XF8000748
+
+31:0
+
+3fff
+
+
+
+2802
+
+MIO Pin 18 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_19
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_19
+
+0XF800074C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4 10: NAND Flash IO Bit 11 111: SDIO 1 Power Control Output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 19 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 Output 110: TTC 0 Clock Input 111: UART 0 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+1
+
+2000
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_19@0XF800074C
+
+31:0
+
+3fff
+
+
+
+2802
+
+MIO Pin 19 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_20
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_20
+
+0XF8000750
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: reserved
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5 10: NAND Flash IO Bit 12 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 20 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+1
+
+2000
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_20@0XF8000750
+
+31:0
+
+3fff
+
+
+
+2802
+
+MIO Pin 20 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_21
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_21
+
+0XF8000754
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: reserved
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6 10: NAND Flash IO Bit 13 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 21 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+1
+
+2000
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_21@0XF8000754
+
+31:0
+
+3fff
+
+
+
+2802
+
+MIO Pin 21 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_22
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_22
+
+0XF8000758
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7 10: NAND Flash IO Bit 14 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 22 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_22@0XF8000758
+
+31:0
+
+3fff
+
+
+
+803
+
+MIO Pin 22 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_23
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_23
+
+0XF800075C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8 10: NAND Flash IO Bit 15 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 23 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_23@0XF800075C
+
+31:0
+
+3fff
+
+
+
+803
+
+MIO Pin 23 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_24
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_24
+
+0XF8000760
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 24 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 serial clock 110: reserved 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_24@0XF8000760
+
+31:0
+
+3fff
+
+
+
+803
+
+MIO Pin 24 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_25
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_25
+
+0XF8000764
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 25 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_25@0XF8000764
+
+31:0
+
+3fff
+
+
+
+803
+
+MIO Pin 25 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_26
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_26
+
+0XF8000768
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 26 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_26@0XF8000768
+
+31:0
+
+3fff
+
+
+
+803
+
+MIO Pin 26 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_27
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_27
+
+0XF800076C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 27 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_27@0XF800076C
+
+31:0
+
+3fff
+
+
+
+803
+
+MIO Pin 27 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_28
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_28
+
+0XF8000770
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 28 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_28@0XF8000770
+
+31:0
+
+3fff
+
+
+
+204
+
+MIO Pin 28 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_29
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_29
+
+0XF8000774
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 29 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_29@0XF8000774
+
+31:0
+
+3fff
+
+
+
+205
+
+MIO Pin 29 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_30
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_30
+
+0XF8000778
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 30 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_30@0XF8000778
+
+31:0
+
+3fff
+
+
+
+204
+
+MIO Pin 30 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_31
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_31
+
+0XF800077C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 31 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_31@0XF800077C
+
+31:0
+
+3fff
+
+
+
+205
+
+MIO Pin 31 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_32
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_32
+
+0XF8000780
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 32 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_32@0XF8000780
+
+31:0
+
+3fff
+
+
+
+204
+
+MIO Pin 32 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_33
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_33
+
+0XF8000784
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 33 (Bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_33@0XF8000784
+
+31:0
+
+3fff
+
+
+
+204
+
+MIO Pin 33 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_34
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_34
+
+0XF8000788
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 34 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 110: reserved 111: UART 0 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_34@0XF8000788
+
+31:0
+
+3fff
+
+
+
+204
+
+MIO Pin 34 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_35
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_35
+
+0XF800078C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 35 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 Command 110: reserved 111: UART 0 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_35@0XF800078C
+
+31:0
+
+3fff
+
+
+
+204
+
+MIO Pin 35 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_36
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_36
+
+0XF8000790
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 36 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Clock 110: reserved 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_36@0XF8000790
+
+31:0
+
+3fff
+
+
+
+205
+
+MIO Pin 36 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_37
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_37
+
+0XF8000794
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 37 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS+H2129 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_37@0XF8000794
+
+31:0
+
+3fff
+
+
+
+204
+
+MIO Pin 37 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_38
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_38
+
+0XF8000798
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 38 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock In 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_38@0XF8000798
+
+31:0
+
+3fff
+
+
+
+204
+
+MIO Pin 38 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_39
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_39
+
+0XF800079C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 000: GPIO 39 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_39@0XF800079C
+
+31:0
+
+3fff
+
+
+
+204
+
+MIO Pin 39 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_40
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_40
+
+0XF80007A0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 40 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_40@0XF80007A0
+
+31:0
+
+3fff
+
+
+
+280
+
+MIO Pin 40 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_41
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_41
+
+0XF80007A4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 41 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_41@0XF80007A4
+
+31:0
+
+3fff
+
+
+
+280
+
+MIO Pin 41 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_42
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_42
+
+0XF80007A8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 42 (bank 1) 001: CAN 0 Rx 010: I2C0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Data Bit 0 110: TTC 0 Wave Out 111: UART 0 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_42@0XF80007A8
+
+31:0
+
+3fff
+
+
+
+280
+
+MIO Pin 42 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_43
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_43
+
+0XF80007AC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 43 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_43@0XF80007AC
+
+31:0
+
+3fff
+
+
+
+280
+
+MIO Pin 43 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_44
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_44
+
+0XF80007B0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 44 (bank 1) 001: CAN 1 Tx 010: I2C Serial Clock 011: reserved 100 SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_44@0XF80007B0
+
+31:0
+
+3fff
+
+
+
+280
+
+MIO Pin 44 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_45
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_45
+
+0XF80007B4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 45 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 Data Bit 3 110: reserved 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_45@0XF80007B4
+
+31:0
+
+3fff
+
+
+
+280
+
+MIO Pin 45 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_46
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_46
+
+0XF80007B8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+1
+
+20
+
+Level 3 Mux Select 000: GPIO 46 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_46@0XF80007B8
+
+31:0
+
+3fff
+
+
+
+1221
+
+MIO Pin 46 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_47
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_47
+
+0XF80007BC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 3
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+1
+
+20
+
+Level 3 Mux Select 000: GPIO 47 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_47@0XF80007BC
+
+31:0
+
+3fff
+
+
+
+1220
+
+MIO Pin 47 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_48
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_48
+
+0XF80007C0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+7
+
+e0
+
+Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_48@0XF80007C0
+
+31:0
+
+3fff
+
+
+
+2e0
+
+MIO Pin 48 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_49
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_49
+
+0XF80007C4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+7
+
+e0
+
+Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_49@0XF80007C4
+
+31:0
+
+3fff
+
+
+
+2e1
+
+MIO Pin 49 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_50
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_50
+
+0XF80007C8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+2
+
+40
+
+Level 3 Mux Select 000: GPIO 50 (bank 1) 001: Can 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_50@0XF80007C8
+
+31:0
+
+3fff
+
+
+
+1240
+
+MIO Pin 50 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_51
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_51
+
+0XF80007CC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+2
+
+40
+
+Level 3 Mux Select 000: GPIO 51 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Output 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_51@0XF80007CC
+
+31:0
+
+3fff
+
+
+
+1240
+
+MIO Pin 51 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_52
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_52
+
+0XF80007D0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: reserved
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_52@0XF80007D0
+
+31:0
+
+3fff
+
+
+
+280
+
+MIO Pin 52 Control
+
    
+
    
+
    Register ( slcr )MIO_PIN_53
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_53
+
+0XF80007D4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[TRI_ENABLE]
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0: Level 1 Mux 1: reserved
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0: Level 2 Mux 1: reserved
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[Speed]
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Operates the same as MIO_PIN_00[IO_Type]
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[PULL_UP]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Operates the same as MIO_PIN_00[DisableRcvr]
+
    
+MIO_PIN_53@0XF80007D4
+
+31:0
+
+3fff
+
+
+
+280
+
+MIO Pin 53 Control
+
    
+
    
+
    Register ( slcr )SD0_WP_CD_SEL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SD0_WP_CD_SEL
+
+0XF8000830
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SDIO0_WP_SEL
+
+5:0
+
+3f
+
+f
+
+f
+
+SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input
+
    
+SDIO0_CD_SEL
+
+21:16
+
+3f0000
+
+0
+
+0
+
+SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input
+
    
+SD0_WP_CD_SEL@0XF8000830
+
+31:0
+
+3f003f
+
+
+
+f
+
+SDIO 0 WP CD select
+
    
+
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_peripherals_init_data_2_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+DDRIOB_DATA0
+
+
+0XF8000B48
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Data 15:0
+
    
+
+DDRIOB_DATA1
+
+
+0XF8000B4C
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for Data 31:16
+
    
+
+DDRIOB_DIFF0
+
+
+0XF8000B50
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for DQS 1:0
+
    
+
+DDRIOB_DIFF1
+
+
+0XF8000B54
+
+32
+
+RW
+
+0x000000
+
+DDR IOB Config for DQS 3:2
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
+Baud_rate_divider_reg0
+
+
+0XE0001034
+
+32
+
+RW
+
+0x000000
+
+baud rate divider register
+
    
+
+Baud_rate_gen_reg0
+
+
+0XE0001018
+
+32
+
+RW
+
+0x000000
+
+Baud rate divider register.
+
    
+
+Control_reg0
+
+
+0XE0001000
+
+32
+
+RW
+
+0x000000
+
+UART Control register
+
    
+
+mode_reg0
+
+
+0XE0001004
+
+32
+
+RW
+
+0x000000
+
+UART Mode register
+
    
+
+Config_reg
+
+
+0XE000D000
+
+32
+
+RW
+
+0x000000
+
+SPI configuration register
+
    
+
+CTRL
+
+
+0XF8007000
+
+32
+
+RW
+
+0x000000
+
+Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.
+
    
+
+DIRM_0
+
+
+0XE000A204
+
+32
+
+RW
+
+0x000000
+
+Direction mode (GPIO Bank0, MIO)
+
    
+
+MASK_DATA_0_LSW
+
+
+0XE000A000
+
+32
+
+RW
+
+0x000000
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
+OEN_0
+
+
+0XE000A208
+
+32
+
+RW
+
+0x000000
+
+Output enable (GPIO Bank0, MIO)
+
    
+
+MASK_DATA_0_LSW
+
+
+0XE000A000
+
+32
+
+RW
+
+0x000000
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
+MASK_DATA_0_LSW
+
+
+0XE000A000
+
+32
+
+RW
+
+0x000000
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
+DIRM_0
+
+
+0XE000A204
+
+32
+
+RW
+
+0x000000
+
+Direction mode (GPIO Bank0, MIO)
+
    
+
+MASK_DATA_0_LSW
+
+
+0XE000A000
+
+32
+
+RW
+
+0x000000
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
+OEN_0
+
+
+0XE000A208
+
+32
+
+RW
+
+0x000000
+
+Output enable (GPIO Bank0, MIO)
+
    
+
+MASK_DATA_0_LSW
+
+
+0XE000A000
+
+32
+
+RW
+
+0x000000
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
+MASK_DATA_0_LSW
+
+
+0XE000A000
+
+32
+
+RW
+
+0x000000
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
+DIRM_0
+
+
+0XE000A204
+
+32
+
+RW
+
+0x000000
+
+Direction mode (GPIO Bank0, MIO)
+
    
+
+MASK_DATA_0_LSW
+
+
+0XE000A000
+
+32
+
+RW
+
+0x000000
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
+OEN_0
+
+
+0XE000A208
+
+32
+
+RW
+
+0x000000
+
+Output enable (GPIO Bank0, MIO)
+
    
+
+MASK_DATA_0_LSW
+
+
+0XE000A000
+
+32
+
+RW
+
+0x000000
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
+MASK_DATA_0_LSW
+
+
+0XE000A000
+
+32
+
+RW
+
+0x000000
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
    
+
    ps7_peripherals_init_data_2_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    DDR TERM/IBUF_DISABLE_MODE SETTINGS
    
+
    Register ( slcr )DDRIOB_DATA0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA0
+
+0XF8000B48
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination
+
    
+DDRIOB_DATA0@0XF8000B48
+
+31:0
+
+180
+
+
+
+180
+
+DDR IOB Config for Data 15:0
+
    
+
    
+
    Register ( slcr )DDRIOB_DATA1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA1
+
+0XF8000B4C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination
+
    
+DDRIOB_DATA1@0XF8000B4C
+
+31:0
+
+180
+
+
+
+180
+
+DDR IOB Config for Data 31:16
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF0
+
+0XF8000B50
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination
+
    
+DDRIOB_DIFF0@0XF8000B50
+
+31:0
+
+180
+
+
+
+180
+
+DDR IOB Config for DQS 1:0
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF1
+
+0XF8000B54
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination
+
    
+DDRIOB_DIFF1@0XF8000B54
+
+31:0
+
+180
+
+
+
+180
+
+DDR IOB Config for DQS 3:2
+
    
+
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
    SRAM/NOR SET OPMODE
    
+
    TRACE CURRENT PORT SIZE
    
+
    UART REGISTERS
    
+
    Register ( slcr )Baud_rate_divider_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Baud_rate_divider_reg0
+
+0XE0001034
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+BDIV
+
+7:0
+
+ff
+
+6
+
+6
+
+Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
+
    
+Baud_rate_divider_reg0@0XE0001034
+
+31:0
+
+ff
+
+
+
+6
+
+baud rate divider register
+
    
+
    
+
    Register ( slcr )Baud_rate_gen_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Baud_rate_gen_reg0
+
+0XE0001018
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CD
+
+15:0
+
+ffff
+
+3e
+
+3e
+
+Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass 2 - 65535: baud_sample value
+
    
+Baud_rate_gen_reg0@0XE0001018
+
+31:0
+
+ffff
+
+
+
+3e
+
+Baud rate divider register.
+
    
+
    
+
    Register ( slcr )Control_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Control_reg0
+
+0XE0001000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+STPBRK
+
+8:8
+
+100
+
+0
+
+0
+
+Stop transmitter break: 0: start break transmission, 1: stop break transmission.
+
    
+STTBRK
+
+7:7
+
+80
+
+0
+
+0
+
+Start transmitter break: 0: 1: start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high.
+
    
+RSTTO
+
+6:6
+
+40
+
+0
+
+0
+
+Restart receiver timeout counter: 0: receiver timeout counter disabled, 1: receiver timeout counter is restarted.
+
    
+TXDIS
+
+5:5
+
+20
+
+0
+
+0
+
+Transmit disable: 0: enable transmitter, 0: disable transmitter
+
    
+TXEN
+
+4:4
+
+10
+
+1
+
+10
+
+Transmit enable: 0: disable transmitter, 1: enable transmitter, provided the TXDIS field is set to 0.
+
    
+RXDIS
+
+3:3
+
+8
+
+0
+
+0
+
+Receive disable: 0: disable, 1: enable
+
    
+RXEN
+
+2:2
+
+4
+
+1
+
+4
+
+Receive enable: 0: disable, 1: enable. When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.
+
    
+TXRES
+
+1:1
+
+2
+
+1
+
+2
+
+Software reset for Tx data path: 0: 1: transmitter logic is reset and all pending transmitter data is discarded self clear
+
    
+RXRES
+
+0:0
+
+1
+
+1
+
+1
+
+Software reset for Rx data path: 0: 1: receiver logic is reset and all pending receiver data is discarded self clear
+
    
+Control_reg0@0XE0001000
+
+31:0
+
+1ff
+
+
+
+17
+
+UART Control register
+
    
+
    
+
    Register ( slcr )mode_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+mode_reg0
+
+0XE0001004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IRMODE
+
+11:11
+
+800
+
+0
+
+0
+
+Enable IrDA mode: 0: Default UART mode 1: Enable IrDA mode
+
    
+UCLKEN
+
+10:10
+
+400
+
+0
+
+0
+
+External uart_clk source select: 0: APB clock, pclk 1: a user-defined clock
+
    
+CHMODE
+
+9:8
+
+300
+
+0
+
+0
+
+Channel mode: 00: normal 01: automatic cho 10: local loopback 11: remote loopback
+
    
+NBSTOP
+
+7:6
+
+c0
+
+0
+
+0
+
+Number of stop bits: 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved
+
    
+PAR
+
+5:3
+
+38
+
+4
+
+20
+
+Parity type select: 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity
+
    
+CHRL
+
+2:1
+
+6
+
+0
+
+0
+
+Character length select: 11: 6 bits 10: 7 bits 0x: 8 bits
+
    
+CLKS
+
+0:0
+
+1
+
+0
+
+0
+
+Clock source select: 0: clock source is uart_clk 1: clock source is uart_clk/8
+
    
+mode_reg0@0XE0001004
+
+31:0
+
+fff
+
+
+
+20
+
+UART Mode register
+
    
+
    
+
    QSPI REGISTERS
    
+
    Register ( slcr )Config_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Config_reg
+
+0XE000D000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+Holdb_dr
+
+19:19
+
+80000
+
+1
+
+80000
+
+Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode.
+
    
+Config_reg@0XE000D000
+
+31:0
+
+80000
+
+
+
+80000
+
+SPI configuration register
+
    
+
    
+
    PL POWER ON RESET REGISTERS
    
+
    Register ( slcr )CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CTRL
+
+0XF8007000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PCFG_POR_CNT_4K
+
+29:29
+
+20000000
+
+0
+
+0
+
+This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer
+
    
+CTRL@0XF8007000
+
+31:0
+
+20000000
+
+
+
+0
+
+Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.
+
    
+
    
+
    SMC TIMING CALCULATION REGISTER UPDATE
    
+
    NAND SET CYCLE
    
+
    OPMODE
    
+
    DIRECT COMMAND
    
+
    SRAM/NOR CS0 SET CYCLE
    
+
    DIRECT COMMAND
    
+
    NOR CS0 BASE ADDRESS
    
+
    SRAM/NOR CS1 SET CYCLE
    
+
    DIRECT COMMAND
    
+
    NOR CS1 BASE ADDRESS
    
+
    USB RESET
    
+
    DIR MODE BANK 0
    
+
    Register ( slcr )DIRM_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DIRM_0
+
+0XE000A204
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DIRECTION_0
+
+31:0
+
+ffffffff
+
+2880
+
+2880
+
+Direction mode 0: input 1: output Each bit configures the corresponding pin within the 32-bit bank NOTE: bits[8:7] of bank0 cannot be used as inputs. The DIRM bits can be set to 0, but reading DATA_RO does not reflect the input value. See the GPIO chapter for more information.
+
    
+DIRM_0@0XE000A204
+
+31:0
+
+ffffffff
+
+
+
+2880
+
+Direction mode (GPIO Bank0, MIO)
+
    
+
    
+
    DIR MODE BANK 1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    Register ( slcr )MASK_DATA_0_LSW
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASK_DATA_0_LSW
+
+0XE000A000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+MASK_0_LSW
+
+31:16
+
+ffff0000
+
+ff7f
+
+ff7f0000
+
+On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's.
+
    
+DATA_0_LSW
+
+15:0
+
+ffff
+
+80
+
+80
+
+On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin.
+
    
+MASK_DATA_0_LSW@0XE000A000
+
+31:0
+
+ffffffff
+
+
+
+ff7f0080
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE BANK 0
    
+
    Register ( slcr )OEN_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+OEN_0
+
+0XE000A208
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+OP_ENABLE_0
+
+31:0
+
+ffffffff
+
+2880
+
+2880
+
+Output enables 0: disabled 1: enabled Each bit configures the corresponding pin within the 32-bit bank
+
    
+OEN_0@0XE000A208
+
+31:0
+
+ffffffff
+
+
+
+2880
+
+Output enable (GPIO Bank0, MIO)
+
    
+
    
+
    OUTPUT ENABLE BANK 1
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    Register ( slcr )MASK_DATA_0_LSW
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASK_DATA_0_LSW
+
+0XE000A000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+MASK_0_LSW
+
+31:16
+
+ffff0000
+
+ff7f
+
+ff7f0000
+
+On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's.
+
    
+DATA_0_LSW
+
+15:0
+
+ffff
+
+0
+
+0
+
+On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin.
+
    
+MASK_DATA_0_LSW@0XE000A000
+
+31:0
+
+ffffffff
+
+
+
+ff7f0000
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    Register ( slcr )MASK_DATA_0_LSW
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASK_DATA_0_LSW
+
+0XE000A000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+MASK_0_LSW
+
+31:16
+
+ffff0000
+
+ff7f
+
+ff7f0000
+
+On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's.
+
    
+DATA_0_LSW
+
+15:0
+
+ffff
+
+80
+
+80
+
+On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin.
+
    
+MASK_DATA_0_LSW@0XE000A000
+
+31:0
+
+ffffffff
+
+
+
+ff7f0080
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    ENET RESET
    
+
    DIR MODE BANK 0
    
+
    Register ( slcr )DIRM_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DIRM_0
+
+0XE000A204
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DIRECTION_0
+
+31:0
+
+ffffffff
+
+2880
+
+2880
+
+Direction mode 0: input 1: output Each bit configures the corresponding pin within the 32-bit bank NOTE: bits[8:7] of bank0 cannot be used as inputs. The DIRM bits can be set to 0, but reading DATA_RO does not reflect the input value. See the GPIO chapter for more information.
+
    
+DIRM_0@0XE000A204
+
+31:0
+
+ffffffff
+
+
+
+2880
+
+Direction mode (GPIO Bank0, MIO)
+
    
+
    
+
    DIR MODE BANK 1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    Register ( slcr )MASK_DATA_0_LSW
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASK_DATA_0_LSW
+
+0XE000A000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+MASK_0_LSW
+
+31:16
+
+ffff0000
+
+f7ff
+
+f7ff0000
+
+On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's.
+
    
+DATA_0_LSW
+
+15:0
+
+ffff
+
+800
+
+800
+
+On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin.
+
    
+MASK_DATA_0_LSW@0XE000A000
+
+31:0
+
+ffffffff
+
+
+
+f7ff0800
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE BANK 0
    
+
    Register ( slcr )OEN_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+OEN_0
+
+0XE000A208
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+OP_ENABLE_0
+
+31:0
+
+ffffffff
+
+2880
+
+2880
+
+Output enables 0: disabled 1: enabled Each bit configures the corresponding pin within the 32-bit bank
+
    
+OEN_0@0XE000A208
+
+31:0
+
+ffffffff
+
+
+
+2880
+
+Output enable (GPIO Bank0, MIO)
+
    
+
    
+
    OUTPUT ENABLE BANK 1
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    Register ( slcr )MASK_DATA_0_LSW
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASK_DATA_0_LSW
+
+0XE000A000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+MASK_0_LSW
+
+31:16
+
+ffff0000
+
+f7ff
+
+f7ff0000
+
+On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's.
+
    
+DATA_0_LSW
+
+15:0
+
+ffff
+
+0
+
+0
+
+On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin.
+
    
+MASK_DATA_0_LSW@0XE000A000
+
+31:0
+
+ffffffff
+
+
+
+f7ff0000
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    Register ( slcr )MASK_DATA_0_LSW
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASK_DATA_0_LSW
+
+0XE000A000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+MASK_0_LSW
+
+31:16
+
+ffff0000
+
+f7ff
+
+f7ff0000
+
+On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's.
+
    
+DATA_0_LSW
+
+15:0
+
+ffff
+
+800
+
+800
+
+On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin.
+
    
+MASK_DATA_0_LSW@0XE000A000
+
+31:0
+
+ffffffff
+
+
+
+f7ff0800
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    I2C RESET
    
+
    DIR MODE GPIO BANK0
    
+
    Register ( slcr )DIRM_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DIRM_0
+
+0XE000A204
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DIRECTION_0
+
+31:0
+
+ffffffff
+
+2880
+
+2880
+
+Direction mode 0: input 1: output Each bit configures the corresponding pin within the 32-bit bank NOTE: bits[8:7] of bank0 cannot be used as inputs. The DIRM bits can be set to 0, but reading DATA_RO does not reflect the input value. See the GPIO chapter for more information.
+
    
+DIRM_0@0XE000A204
+
+31:0
+
+ffffffff
+
+
+
+2880
+
+Direction mode (GPIO Bank0, MIO)
+
    
+
    
+
    DIR MODE GPIO BANK1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    Register ( slcr )MASK_DATA_0_LSW
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASK_DATA_0_LSW
+
+0XE000A000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+MASK_0_LSW
+
+31:16
+
+ffff0000
+
+dfff
+
+dfff0000
+
+On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's.
+
    
+DATA_0_LSW
+
+15:0
+
+ffff
+
+2000
+
+2000
+
+On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin.
+
    
+MASK_DATA_0_LSW@0XE000A000
+
+31:0
+
+ffffffff
+
+
+
+dfff2000
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE
    
+
    Register ( slcr )OEN_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+OEN_0
+
+0XE000A208
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+OP_ENABLE_0
+
+31:0
+
+ffffffff
+
+2880
+
+2880
+
+Output enables 0: disabled 1: enabled Each bit configures the corresponding pin within the 32-bit bank
+
    
+OEN_0@0XE000A208
+
+31:0
+
+ffffffff
+
+
+
+2880
+
+Output enable (GPIO Bank0, MIO)
+
    
+
    
+
    OUTPUT ENABLE
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    Register ( slcr )MASK_DATA_0_LSW
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASK_DATA_0_LSW
+
+0XE000A000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+MASK_0_LSW
+
+31:16
+
+ffff0000
+
+dfff
+
+dfff0000
+
+On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's.
+
    
+DATA_0_LSW
+
+15:0
+
+ffff
+
+0
+
+0
+
+On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin.
+
    
+MASK_DATA_0_LSW@0XE000A000
+
+31:0
+
+ffffffff
+
+
+
+dfff0000
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    Register ( slcr )MASK_DATA_0_LSW
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASK_DATA_0_LSW
+
+0XE000A000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+MASK_0_LSW
+
+31:16
+
+ffff0000
+
+dfff
+
+dfff0000
+
+On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's.
+
    
+DATA_0_LSW
+
+15:0
+
+ffff
+
+2000
+
+2000
+
+On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin.
+
    
+MASK_DATA_0_LSW@0XE000A000
+
+31:0
+
+ffffffff
+
+
+
+dfff2000
+
+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits)
+
    
+
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
+
    
+
    ps7_post_config_2_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+LVL_SHFTR_EN
+
+
+0XF8000900
+
+32
+
+RW
+
+0x000000
+
+Level Shifters Enable
+
    
+
+FPGA_RST_CTRL
+
+
+0XF8000240
+
+32
+
+RW
+
+0x000000
+
+FPGA Software Reset Control
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_post_config_2_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    ENABLING LEVEL SHIFTER
    
+
    Register ( slcr )LVL_SHFTR_EN
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LVL_SHFTR_EN
+
+0XF8000900
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+USER_INP_ICT_EN_0
+
+1:0
+
+3
+
+3
+
+3
+
+Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0].
+
    
+USER_INP_ICT_EN_1
+
+3:2
+
+c
+
+3
+
+c
+
+Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0].
+
    
+LVL_SHFTR_EN@0XF8000900
+
+31:0
+
+f
+
+
+
+f
+
+Level Shifters Enable
+
    
+
    
+
    FPGA RESETS TO 0
    
+
    Register ( slcr )FPGA_RST_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+FPGA_RST_CTRL
+
+0XF8000240
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_3
+
+31:25
+
+fe000000
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is zero.
+
    
+FPGA_ACP_RST
+
+24:24
+
+1000000
+
+0
+
+0
+
+FPGA ACP port soft reset: 0: No reset 1: ACP AXI interface reset output asserted
+
    
+FPGA_AXDS3_RST
+
+23:23
+
+800000
+
+0
+
+0
+
+AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0: No reset 1: AXDS3AXI interface reset output asserted
+
    
+FPGA_AXDS2_RST
+
+22:22
+
+400000
+
+0
+
+0
+
+AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0: No reset 1: AXDS2 AXI interface reset output asserted
+
    
+FPGA_AXDS1_RST
+
+21:21
+
+200000
+
+0
+
+0
+
+AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0: No reset 1: AXDS1 AXI interface reset output asserted
+
    
+FPGA_AXDS0_RST
+
+20:20
+
+100000
+
+0
+
+0
+
+AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0: No reset 1: AXDS0 AXI interface reset output asserted
+
    
+reserved_2
+
+19:18
+
+c0000
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is zero.
+
    
+FSSW1_FPGA_RST
+
+17:17
+
+20000
+
+0
+
+0
+
+General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0: No reset 1: FPGA slave interface 1 reset is asserted
+
    
+FSSW0_FPGA_RST
+
+16:16
+
+10000
+
+0
+
+0
+
+General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0: No reset 1: FPGA slave interface 0 reset is asserted
+
    
+reserved_1
+
+15:14
+
+c000
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is zero.
+
    
+FPGA_FMSW1_RST
+
+13:13
+
+2000
+
+0
+
+0
+
+General purpose FPGA master interface: 1: soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0: No reset 1: FPGA master interface 1 reset is asserted
+
    
+FPGA_FMSW0_RST
+
+12:12
+
+1000
+
+0
+
+0
+
+General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0: No reset 1: FPGA master interface 0 reset is asserted.
+
    
+FPGA_DMA3_RST
+
+11:11
+
+800
+
+0
+
+0
+
+FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 3 peripheral request reset output asserted
+
    
+FPGA_DMA2_RST
+
+10:10
+
+400
+
+0
+
+0
+
+FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 2 peripheral request reset output asserted
+
    
+FPGA_DMA1_RST
+
+9:9
+
+200
+
+0
+
+0
+
+FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 1 peripheral request reset output asserted
+
    
+FPGA_DMA0_RST
+
+8:8
+
+100
+
+0
+
+0
+
+FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 0 peripheral request reset output asserted
+
    
+reserved
+
+7:4
+
+f0
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is zero.
+
    
+FPGA3_OUT_RST
+
+3:3
+
+8
+
+0
+
+0
+
+FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0: No reset 1: FPGA 3 top level reset output asserted
+
    
+FPGA2_OUT_RST
+
+2:2
+
+4
+
+0
+
+0
+
+FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0: No reset 1: FPGA 2 top level reset output asserted
+
    
+FPGA1_OUT_RST
+
+1:1
+
+2
+
+0
+
+0
+
+FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0: No reset 1: FPGA 1 top level reset output asserted
+
    
+FPGA0_OUT_RST
+
+0:0
+
+1
+
+0
+
+0
+
+FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0: No reset 1: FPGA 0 top level reset output asserted
+
    
+FPGA_RST_CTRL@0XF8000240
+
+31:0
+
+ffffffff
+
+
+
+0
+
+FPGA Software Reset Control
+
    
+
    
+
    AFI REGISTERS
    
+
    AFI0 REGISTERS
    
+
    AFI1 REGISTERS
    
+
    AFI2 REGISTERS
    
+
    AFI3 REGISTERS
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_debug_2_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+LAR
+
+
+0XF8898FB0
+
+32
+
+WO
+
+0x000000
+
+Lock Access Register
+
    
+
+LAR
+
+
+0XF8899FB0
+
+32
+
+WO
+
+0x000000
+
+Lock Access Register
+
    
+
+LAR
+
+
+0XF8809FB0
+
+32
+
+WO
+
+0x000000
+
+Lock Access Register
+
    
+
    
+
    ps7_debug_2_0
    
+
+
+
+
+
+
+
+
+
+
    CROSS TRIGGER CONFIGURATIONS
    
+
    UNLOCKING CTI REGISTERS
    
+
    Register ( slcr )LAR
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LAR
+
+0XF8898FB0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+KEY
+
+31:0
+
+ffffffff
+
+c5acce55
+
+c5acce55
+
+Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
+
    
+LAR@0XF8898FB0
+
+31:0
+
+ffffffff
+
+
+
+c5acce55
+
+Lock Access Register
+
    
+
    
+
    Register ( slcr )LAR
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LAR
+
+0XF8899FB0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+KEY
+
+31:0
+
+ffffffff
+
+c5acce55
+
+c5acce55
+
+Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
+
    
+LAR@0XF8899FB0
+
+31:0
+
+ffffffff
+
+
+
+c5acce55
+
+Lock Access Register
+
    
+
    
+
    Register ( slcr )LAR
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LAR
+
+0XF8809FB0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+KEY
+
+31:0
+
+ffffffff
+
+c5acce55
+
+c5acce55
+
+Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
+
    
+LAR@0XF8809FB0
+
+31:0
+
+ffffffff
+
+
+
+c5acce55
+
+Lock Access Register
+
    
+
    
+
    ENABLING CTI MODULES AND CHANNELS
    
+
    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
    
+
+
    
+
+
+
+
+
    ps7_pll_init_data_1_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+ARM_PLL_CFG
+
+
+0XF8000110
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Configuration
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_PLL_CTRL
+
+
+0XF8000100
+
+32
+
+RW
+
+0x000000
+
+ARM PLL Control
+
    
+
+ARM_CLK_CTRL
+
+
+0XF8000120
+
+32
+
+RW
+
+0x000000
+
+CORTEX A9 Clock Control
+
    
+
+DDR_PLL_CFG
+
+
+0XF8000114
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Configuration
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_PLL_CTRL
+
+
+0XF8000104
+
+32
+
+RW
+
+0x000000
+
+DDR PLL Control
+
    
+
+DDR_CLK_CTRL
+
+
+0XF8000124
+
+32
+
+RW
+
+0x000000
+
+DDR Clock Control
+
    
+
+IO_PLL_CFG
+
+
+0XF8000118
+
+32
+
+RW
+
+0x000000
+
+IO PLL Configuration
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+IO_PLL_CTRL
+
+
+0XF8000108
+
+32
+
+RW
+
+0x000000
+
+IO PLL Control
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_pll_init_data_1_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    PLL SLCR REGISTERS
    
+
    ARM PLL INIT
    
+
    Register ( slcr )ARM_PLL_CFG
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CFG
+
+0XF8000110
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RES
+
+7:4
+
+f0
+
+2
+
+20
+
+Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control
+
    
+PLL_CP
+
+11:8
+
+f00
+
+2
+
+200
+
+Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control
+
    
+LOCK_CNT
+
+21:12
+
+3ff000
+
+fa
+
+fa000
+
+Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked.
+
    
+ARM_PLL_CFG@0XF8000110
+
+31:0
+
+3ffff0
+
+
+
+fa220
+
+ARM PLL Configuration
+
    
+
    
+
    UPDATE FB_DIV
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_FDIV
+
+18:12
+
+7f000
+
+28
+
+28000
+
+Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+7f000
+
+
+
+28000
+
+ARM PLL Control
+
    
+
    
+
    BY PASS PLL
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+1
+
+10
+
+Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+10
+
+
+
+10
+
+ARM PLL Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+1
+
+1
+
+Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+1
+
+
+
+1
+
+ARM PLL Control
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+0
+
+0
+
+Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+1
+
+
+
+0
+
+ARM PLL Control
+
    
+
    
+
    CHECK PLL STATUS
    
+
    Register ( slcr )PLL_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PLL_STATUS
+
+0XF800010C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+ARM_PLL_LOCK
+
+0:0
+
+1
+
+1
+
+1
+
+ARM PLL lock status. 0 - ARM PLL out of lock. 1 - ARM PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used.
+
    
+PLL_STATUS@0XF800010C
+
+31:0
+
+1
+
+
+
+1
+
+tobe
+
    
+
    
+
    REMOVE PLL BY PASS
    
+
    Register ( slcr )ARM_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_PLL_CTRL
+
+0XF8000100
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+0
+
+0
+
+Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed.
+
    
+ARM_PLL_CTRL@0XF8000100
+
+31:0
+
+10
+
+
+
+0
+
+ARM PLL Control
+
    
+
    
+
    Register ( slcr )ARM_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ARM_CLK_CTRL
+
+0XF8000120
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Selects the source used to generate the clock. 0x - Source for generated clock is CPU PLL. 10 - Source for generated clock is DDR divided clock. 11 - Source for generated clock is IO PLL
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+2
+
+200
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+CPU_6OR4XCLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+CPU_3OR2XCLKACT
+
+25:25
+
+2000000
+
+1
+
+2000000
+
+Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+CPU_2XCLKACT
+
+26:26
+
+4000000
+
+1
+
+4000000
+
+Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+CPU_1XCLKACT
+
+27:27
+
+8000000
+
+1
+
+8000000
+
+Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+CPU_PERI_CLKACT
+
+28:28
+
+10000000
+
+1
+
+10000000
+
+Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+ARM_CLK_CTRL@0XF8000120
+
+31:0
+
+1f003f30
+
+
+
+1f000200
+
+CORTEX A9 Clock Control
+
    
+
    
+
    DDR PLL INIT
    
+
    Register ( slcr )DDR_PLL_CFG
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CFG
+
+0XF8000114
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RES
+
+7:4
+
+f0
+
+2
+
+20
+
+Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control
+
    
+PLL_CP
+
+11:8
+
+f00
+
+2
+
+200
+
+Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control
+
    
+LOCK_CNT
+
+21:12
+
+3ff000
+
+12c
+
+12c000
+
+Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked.
+
    
+DDR_PLL_CFG@0XF8000114
+
+31:0
+
+3ffff0
+
+
+
+12c220
+
+DDR PLL Configuration
+
    
+
    
+
    UPDATE FB_DIV
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_FDIV
+
+18:12
+
+7f000
+
+20
+
+20000
+
+Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state.
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+7f000
+
+
+
+20000
+
+DDR PLL Control
+
    
+
    
+
    BY PASS PLL
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+1
+
+10
+
+Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+10
+
+
+
+10
+
+DDR PLL Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+1
+
+1
+
+Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+1
+
+
+
+1
+
+DDR PLL Control
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+0
+
+0
+
+Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+1
+
+
+
+0
+
+DDR PLL Control
+
    
+
    
+
    CHECK PLL STATUS
    
+
    Register ( slcr )PLL_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PLL_STATUS
+
+0XF800010C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DDR_PLL_LOCK
+
+1:1
+
+2
+
+1
+
+2
+
+DDR PLL lock status. 0 - DDR PLL out of lock. 1 - DDR PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used.
+
    
+PLL_STATUS@0XF800010C
+
+31:0
+
+2
+
+
+
+2
+
+tobe
+
    
+
    
+
    REMOVE PLL BY PASS
    
+
    Register ( slcr )DDR_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_PLL_CTRL
+
+0XF8000104
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+0
+
+0
+
+Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed
+
    
+DDR_PLL_CTRL@0XF8000104
+
+31:0
+
+10
+
+
+
+0
+
+DDR PLL Control
+
    
+
    
+
    Register ( slcr )DDR_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDR_CLK_CTRL
+
+0XF8000124
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DDR_3XCLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+DDR_2XCLKACT
+
+1:1
+
+2
+
+1
+
+2
+
+Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+DDR_3XCLK_DIVISOR
+
+25:20
+
+3f00000
+
+2
+
+200000
+
+Divisor value for the ddr_3xclk
+
    
+DDR_2XCLK_DIVISOR
+
+31:26
+
+fc000000
+
+3
+
+c000000
+
+Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk)
+
    
+DDR_CLK_CTRL@0XF8000124
+
+31:0
+
+fff00003
+
+
+
+c200003
+
+DDR Clock Control
+
    
+
    
+
    IO PLL INIT
    
+
    Register ( slcr )IO_PLL_CFG
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CFG
+
+0XF8000118
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RES
+
+7:4
+
+f0
+
+c
+
+c0
+
+Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control
+
    
+PLL_CP
+
+11:8
+
+f00
+
+2
+
+200
+
+Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control
+
    
+LOCK_CNT
+
+21:12
+
+3ff000
+
+145
+
+145000
+
+Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked.
+
    
+IO_PLL_CFG@0XF8000118
+
+31:0
+
+3ffff0
+
+
+
+1452c0
+
+IO PLL Configuration
+
    
+
    
+
    UPDATE FB_DIV
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_FDIV
+
+18:12
+
+7f000
+
+1e
+
+1e000
+
+Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state.
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+7f000
+
+
+
+1e000
+
+IO PLL Control
+
    
+
    
+
    BY PASS PLL
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+1
+
+10
+
+Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+10
+
+
+
+10
+
+IO PLL Control
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+1
+
+1
+
+Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+1
+
+
+
+1
+
+IO PLL Control
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_RESET
+
+0:0
+
+1
+
+0
+
+0
+
+Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using.
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+1
+
+
+
+0
+
+IO PLL Control
+
    
+
    
+
    CHECK PLL STATUS
    
+
    Register ( slcr )PLL_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PLL_STATUS
+
+0XF800010C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IO_PLL_LOCK
+
+2:2
+
+4
+
+1
+
+4
+
+IO PLL lock status. 0 - IO PLL out of lock. 1 - IO PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used.
+
    
+PLL_STATUS@0XF800010C
+
+31:0
+
+4
+
+
+
+4
+
+tobe
+
    
+
    
+
    REMOVE PLL BY PASS
    
+
    Register ( slcr )IO_PLL_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+IO_PLL_CTRL
+
+0XF8000108
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PLL_BYPASS_FORCE
+
+4:4
+
+10
+
+0
+
+0
+
+Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed
+
    
+IO_PLL_CTRL@0XF8000108
+
+31:0
+
+10
+
+
+
+0
+
+IO PLL Control
+
    
+
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_clock_init_data_1_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+DCI_CLK_CTRL
+
+
+0XF8000128
+
+32
+
+RW
+
+0x000000
+
+DCI clock control
+
    
+
+GEM0_RCLK_CTRL
+
+
+0XF8000138
+
+32
+
+RW
+
+0x000000
+
+Gigabit Ethernet MAC 0 RX Clock Control
+
    
+
+GEM0_CLK_CTRL
+
+
+0XF8000140
+
+32
+
+RW
+
+0x000000
+
+Gigabit Ethernet MAC 0 Ref Clock Control
+
    
+
+LQSPI_CLK_CTRL
+
+
+0XF800014C
+
+32
+
+RW
+
+0x000000
+
+Linear Quad-SPI Reference Clock Control
+
    
+
+SDIO_CLK_CTRL
+
+
+0XF8000150
+
+32
+
+RW
+
+0x000000
+
+SDIO Reference Clock Control
+
    
+
+UART_CLK_CTRL
+
+
+0XF8000154
+
+32
+
+RW
+
+0x000000
+
+UART Reference Clock Control
+
    
+
+CAN_CLK_CTRL
+
+
+0XF800015C
+
+32
+
+RW
+
+0x000000
+
+CAN Reference Clock Control
+
    
+
+CAN_MIOCLK_CTRL
+
+
+0XF8000160
+
+32
+
+RW
+
+0x000000
+
+CAN MIO Clock Control
+
    
+
+PCAP_CLK_CTRL
+
+
+0XF8000168
+
+32
+
+RW
+
+0x000000
+
+PCAP 2X Clock Contol
+
    
+
+FPGA0_CLK_CTRL
+
+
+0XF8000170
+
+32
+
+RW
+
+0x000000
+
+FPGA 0 Output Clock Control
+
    
+
+FPGA1_CLK_CTRL
+
+
+0XF8000180
+
+32
+
+RW
+
+0x000000
+
+FPGA 1 Output Clock Control
+
    
+
+FPGA2_CLK_CTRL
+
+
+0XF8000190
+
+32
+
+RW
+
+0x000000
+
+FPGA 2 Output Clock Control
+
    
+
+FPGA3_CLK_CTRL
+
+
+0XF80001A0
+
+32
+
+RW
+
+0x000000
+
+FPGA 3 Output Clock Control
+
    
+
+CLK_621_TRUE
+
+
+0XF80001C4
+
+32
+
+RW
+
+0x000000
+
+6:2:1 ratio clock, if set
+
    
+
+APER_CLK_CTRL
+
+
+0XF800012C
+
+32
+
+RW
+
+0x000000
+
+AMBA Peripheral Clock Control
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_clock_init_data_1_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    CLOCK CONTROL SLCR REGISTERS
    
+
    Register ( slcr )DCI_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DCI_CLK_CTRL
+
+0XF8000128
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+DIVISOR0
+
+13:8
+
+3f00
+
+23
+
+2300
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+3
+
+300000
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider
+
    
+DCI_CLK_CTRL@0XF8000128
+
+31:0
+
+3f03f01
+
+
+
+302301
+
+DCI clock control
+
    
+
    
+
    Register ( slcr )GEM0_RCLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+GEM0_RCLK_CTRL
+
+0XF8000138
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+SRCSEL
+
+4:4
+
+10
+
+0
+
+0
+
+Selects the source used to generate the clock. 0 - Source for generated clock is GEM 0 MIO RX clock. 1 - Source for generated clock is GEM 0 FMIO RX clock.
+
    
+GEM0_RCLK_CTRL@0XF8000138
+
+31:0
+
+11
+
+
+
+1
+
+Gigabit Ethernet MAC 0 RX Clock Control
+
    
+
    
+
    Register ( slcr )GEM0_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+GEM0_CLK_CTRL
+
+0XF8000140
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+SRCSEL
+
+6:4
+
+70
+
+0
+
+0
+
+Selects the source used to generate the clock. 1xx - Source for generated clock is Ethernet 0 FMIO clock. 00x - Source for generated clock is IO PLL. 010 - Source for generated clock is ARM PLL. 011 - Source for generated clock is DDR PLL
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+8
+
+800
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+5
+
+500000
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider
+
    
+GEM0_CLK_CTRL@0XF8000140
+
+31:0
+
+3f03f71
+
+
+
+500801
+
+Gigabit Ethernet MAC 0 Ref Clock Control
+
    
+
    
+
    Register ( slcr )LQSPI_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LQSPI_CLK_CTRL
+
+0XF800014C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL.
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+5
+
+500
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+LQSPI_CLK_CTRL@0XF800014C
+
+31:0
+
+3f31
+
+
+
+501
+
+Linear Quad-SPI Reference Clock Control
+
    
+
    
+
    Register ( slcr )SDIO_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SDIO_CLK_CTRL
+
+0XF8000150
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT0
+
+0:0
+
+1
+
+1
+
+1
+
+SDIO 0 Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+CLKACT1
+
+1:1
+
+2
+
+0
+
+0
+
+SDIO 1 Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL.
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+14
+
+1400
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+SDIO_CLK_CTRL@0XF8000150
+
+31:0
+
+3f33
+
+
+
+1401
+
+SDIO Reference Clock Control
+
    
+
    
+
    Register ( slcr )UART_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+UART_CLK_CTRL
+
+0XF8000154
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT0
+
+0:0
+
+1
+
+0
+
+0
+
+UART 0 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+CLKACT1
+
+1:1
+
+2
+
+1
+
+2
+
+UART 1 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL.
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+14
+
+1400
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+UART_CLK_CTRL@0XF8000154
+
+31:0
+
+3f33
+
+
+
+1402
+
+UART Reference Clock Control
+
    
+
    
+
    Register ( slcr )CAN_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CAN_CLK_CTRL
+
+0XF800015C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT0
+
+0:0
+
+1
+
+1
+
+1
+
+CAN 0 Reference Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+CLKACT1
+
+1:1
+
+2
+
+0
+
+0
+
+CAN 1 Reference Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL.
+
    
+DIVISOR0
+
+13:8
+
+3f00
+
+e
+
+e00
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+3
+
+300000
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider
+
    
+CAN_CLK_CTRL@0XF800015C
+
+31:0
+
+3f03f33
+
+
+
+300e01
+
+CAN Reference Clock Control
+
    
+
    
+
    Register ( slcr )CAN_MIOCLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CAN_MIOCLK_CTRL
+
+0XF8000160
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CAN0_MUX
+
+5:0
+
+3f
+
+0
+
+0
+
+CAN0 mux selection for MIO. Setting this to zero will select MIO[0] as the clock source. Only values 0-53 are valid.
+
    
+CAN0_REF_SEL
+
+6:6
+
+40
+
+0
+
+0
+
+CAN 0 Reference Clock selection. 0 - From internal PLL. 1 - From MIO based on the next field
+
    
+CAN1_MUX
+
+21:16
+
+3f0000
+
+0
+
+0
+
+CAN1 mux selection for MIO. Setting this to zero will select MIO[0] as the clock source. Only values 0-53 are valid.
+
    
+CAN1_REF_SEL
+
+22:22
+
+400000
+
+0
+
+0
+
+CAN1 Reference Clock selection. 0 - From internal PLL. 1 - From MIO based on the next field
+
    
+CAN_MIOCLK_CTRL@0XF8000160
+
+31:0
+
+7f007f
+
+
+
+0
+
+CAN MIO Clock Control
+
    
+
    
+
    Register ( slcr )PCAP_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PCAP_CLK_CTRL
+
+0XF8000168
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+Clock active 0 - Clock is disabled 1 - Clock is enabled
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL
+
    
+DIVISOR
+
+13:8
+
+3f00
+
+5
+
+500
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency.
+
    
+PCAP_CLK_CTRL@0XF8000168
+
+31:0
+
+3f31
+
+
+
+501
+
+PCAP 2X Clock Contol
+
    
+
    
+
    Register ( slcr )FPGA0_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+FPGA0_CLK_CTRL
+
+0XF8000170
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL.
+
    
+DIVISOR0
+
+13:8
+
+3f00
+
+14
+
+1400
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+1
+
+100000
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider
+
    
+FPGA0_CLK_CTRL@0XF8000170
+
+31:0
+
+3f03f30
+
+
+
+101400
+
+FPGA 0 Output Clock Control
+
    
+
    
+
    Register ( slcr )FPGA1_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+FPGA1_CLK_CTRL
+
+0XF8000180
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL.
+
    
+DIVISOR0
+
+13:8
+
+3f00
+
+14
+
+1400
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+1
+
+100000
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider
+
    
+FPGA1_CLK_CTRL@0XF8000180
+
+31:0
+
+3f03f30
+
+
+
+101400
+
+FPGA 1 Output Clock Control
+
    
+
    
+
    Register ( slcr )FPGA2_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+FPGA2_CLK_CTRL
+
+0XF8000190
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL.
+
    
+DIVISOR0
+
+13:8
+
+3f00
+
+14
+
+1400
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+1
+
+100000
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider
+
    
+FPGA2_CLK_CTRL@0XF8000190
+
+31:0
+
+3f03f30
+
+
+
+101400
+
+FPGA 2 Output Clock Control
+
    
+
    
+
    Register ( slcr )FPGA3_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+FPGA3_CLK_CTRL
+
+0XF80001A0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SRCSEL
+
+5:4
+
+30
+
+0
+
+0
+
+Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL.
+
    
+DIVISOR0
+
+13:8
+
+3f00
+
+14
+
+1400
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider
+
    
+DIVISOR1
+
+25:20
+
+3f00000
+
+1
+
+100000
+
+Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider
+
    
+FPGA3_CLK_CTRL@0XF80001A0
+
+31:0
+
+3f03f30
+
+
+
+101400
+
+FPGA 3 Output Clock Control
+
    
+
    
+
    Register ( slcr )CLK_621_TRUE
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CLK_621_TRUE
+
+0XF80001C4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CLK_621_TRUE
+
+0:0
+
+1
+
+1
+
+1
+
+Enable the 6:2:1 mode. 1 for 6:3:2:1. 0 for 4:2:2:1.
+
    
+CLK_621_TRUE@0XF80001C4
+
+31:0
+
+1
+
+
+
+1
+
+6:2:1 ratio clock, if set
+
    
+
    
+
    Register ( slcr )APER_CLK_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+APER_CLK_CTRL
+
+0XF800012C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DMA_CPU_2XCLKACT
+
+0:0
+
+1
+
+1
+
+1
+
+DMA 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+USB0_CPU_1XCLKACT
+
+2:2
+
+4
+
+1
+
+4
+
+USB 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+USB1_CPU_1XCLKACT
+
+3:3
+
+8
+
+1
+
+8
+
+USB 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+GEM0_CPU_1XCLKACT
+
+6:6
+
+40
+
+1
+
+40
+
+Gigabit Ethernet MAC 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+GEM1_CPU_1XCLKACT
+
+7:7
+
+80
+
+0
+
+0
+
+Gigabit Ethernet MAC 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+SDI0_CPU_1XCLKACT
+
+10:10
+
+400
+
+1
+
+400
+
+SDIO0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+SDI1_CPU_1XCLKACT
+
+11:11
+
+800
+
+0
+
+0
+
+SDIO 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+SPI0_CPU_1XCLKACT
+
+14:14
+
+4000
+
+0
+
+0
+
+SPI 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+SPI1_CPU_1XCLKACT
+
+15:15
+
+8000
+
+0
+
+0
+
+SPI 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+CAN0_CPU_1XCLKACT
+
+16:16
+
+10000
+
+1
+
+10000
+
+CAN 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+CAN1_CPU_1XCLKACT
+
+17:17
+
+20000
+
+0
+
+0
+
+CAN 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+I2C0_CPU_1XCLKACT
+
+18:18
+
+40000
+
+1
+
+40000
+
+I2C 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+I2C1_CPU_1XCLKACT
+
+19:19
+
+80000
+
+1
+
+80000
+
+I2C 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+UART0_CPU_1XCLKACT
+
+20:20
+
+100000
+
+0
+
+0
+
+UART 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+UART1_CPU_1XCLKACT
+
+21:21
+
+200000
+
+1
+
+200000
+
+UART 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+GPIO_CPU_1XCLKACT
+
+22:22
+
+400000
+
+1
+
+400000
+
+GPIO AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+LQSPI_CPU_1XCLKACT
+
+23:23
+
+800000
+
+1
+
+800000
+
+LQSPI AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+SMC_CPU_1XCLKACT
+
+24:24
+
+1000000
+
+1
+
+1000000
+
+SMC AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled.
+
    
+APER_CLK_CTRL@0XF800012C
+
+31:0
+
+1ffcccd
+
+
+
+1ed044d
+
+AMBA Peripheral Clock Control
+
    
+
    
+
    THIS SHOULD BE BLANK
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_ddr_init_data_1_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+ddrc_ctrl
+
+
+0XF8006000
+
+32
+
+RW
+
+0x000000
+
+DDRC Control Register
+
    
+
+Two_rank_cfg
+
+
+0XF8006004
+
+32
+
+RW
+
+0x000000
+
+Two rank configuration register
+
    
+
+HPR_reg
+
+
+0XF8006008
+
+32
+
+RW
+
+0x000000
+
+HPR Queue control register
+
    
+
+LPR_reg
+
+
+0XF800600C
+
+32
+
+RW
+
+0x000000
+
+LPR Queue control register
+
    
+
+WR_reg
+
+
+0XF8006010
+
+32
+
+RW
+
+0x000000
+
+WR Queue control register
+
    
+
+DRAM_param_reg0
+
+
+0XF8006014
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters register 0
+
    
+
+DRAM_param_reg1
+
+
+0XF8006018
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters register 1
+
    
+
+DRAM_param_reg2
+
+
+0XF800601C
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters register 2
+
    
+
+DRAM_param_reg3
+
+
+0XF8006020
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters register 3
+
    
+
+DRAM_param_reg4
+
+
+0XF8006024
+
+32
+
+RW
+
+0x000000
+
+DRAM Parameters register 4
+
    
+
+DRAM_init_param
+
+
+0XF8006028
+
+32
+
+RW
+
+0x000000
+
+DRAM initialization parameters register
+
    
+
+DRAM_EMR_reg
+
+
+0XF800602C
+
+32
+
+RW
+
+0x000000
+
+DRAM EMR2, EMR3 access register
+
    
+
+DRAM_EMR_MR_reg
+
+
+0XF8006030
+
+32
+
+RW
+
+0x000000
+
+DRAM EMR, MR access register
+
    
+
+DRAM_burst8_rdwr
+
+
+0XF8006034
+
+32
+
+RW
+
+0x000000
+
+DRAM burst 8 read/write register
+
    
+
+DRAM_disable_DQ
+
+
+0XF8006038
+
+32
+
+RW
+
+0x000000
+
+DRAM Disable DQ register
+
    
+
+DRAM_addr_map_bank
+
+
+0XF800603C
+
+32
+
+RW
+
+0x000000
+
+Selects the address bits used as DRAM bank address bits
+
    
+
+DRAM_addr_map_col
+
+
+0XF8006040
+
+32
+
+RW
+
+0x000000
+
+Selects the address bits used as DRAM column address bits
+
    
+
+DRAM_addr_map_row
+
+
+0XF8006044
+
+32
+
+RW
+
+0x000000
+
+Selects the address bits used as DRAM row address bits
+
    
+
+DRAM_ODT_reg
+
+
+0XF8006048
+
+32
+
+RW
+
+0x000000
+
+DRAM ODT register
+
    
+
+phy_cmd_timeout_rddata_cpt
+
+
+0XF8006050
+
+32
+
+RW
+
+0x000000
+
+PHY command time out and read data capture FIFO register
+
    
+
+DLL_calib
+
+
+0XF8006058
+
+32
+
+RW
+
+0x000000
+
+DLL calibration register
+
    
+
+ODT_delay_hold
+
+
+0XF800605C
+
+32
+
+RW
+
+0x000000
+
+ODT delay and ODT hold register
+
    
+
+ctrl_reg1
+
+
+0XF8006060
+
+32
+
+RW
+
+0x000000
+
+Controller register 1
+
    
+
+ctrl_reg2
+
+
+0XF8006064
+
+32
+
+RW
+
+0x000000
+
+Controller register 2
+
    
+
+ctrl_reg3
+
+
+0XF8006068
+
+32
+
+RW
+
+0x000000
+
+Controller register 3
+
    
+
+ctrl_reg4
+
+
+0XF800606C
+
+32
+
+RW
+
+0x000000
+
+Controller register 4
+
    
+
+CHE_REFRESH_TIMER01
+
+
+0XF80060A0
+
+32
+
+RW
+
+0x000000
+
+CHE_REFRESH_TIMER01
+
    
+
+CHE_T_ZQ
+
+
+0XF80060A4
+
+32
+
+RW
+
+0x000000
+
+ZQ parameters register
+
    
+
+CHE_T_ZQ_Short_Interval_Reg
+
+
+0XF80060A8
+
+32
+
+RW
+
+0x000000
+
+Misc parameters register
+
    
+
+deep_pwrdwn_reg
+
+
+0XF80060AC
+
+32
+
+RW
+
+0x000000
+
+Deep powerdown register
+
    
+
+reg_2c
+
+
+0XF80060B0
+
+32
+
+RW
+
+0x000000
+
+Training control register
+
    
+
+reg_2d
+
+
+0XF80060B4
+
+32
+
+RW
+
+0x000000
+
+Misc Debug register
+
    
+
+dfi_timing
+
+
+0XF80060B8
+
+32
+
+RW
+
+0x000000
+
+DFI timing register
+
    
+
+CHE_ECC_CONTROL_REG_OFFSET
+
+
+0XF80060C4
+
+32
+
+RW
+
+0x000000
+
+ECC error clear register
+
    
+
+CHE_ECC_CONTROL_REG_OFFSET
+
+
+0XF80060C4
+
+32
+
+RW
+
+0x000000
+
+ECC error clear register
+
    
+
+CHE_CORR_ECC_LOG_REG_OFFSET
+
+
+0XF80060C8
+
+32
+
+RW
+
+0x000000
+
+ECC error correction register
+
    
+
+CHE_UNCORR_ECC_LOG_REG_OFFSET
+
+
+0XF80060DC
+
+32
+
+RW
+
+0x000000
+
+ECC unrecoverable error status register
+
    
+
+CHE_ECC_STATS_REG_OFFSET
+
+
+0XF80060F0
+
+32
+
+RW
+
+0x000000
+
+ECC error count register
+
    
+
+ECC_scrub
+
+
+0XF80060F4
+
+32
+
+RW
+
+0x000000
+
+ECC mode/scrub register
+
    
+
+phy_rcvr_enable
+
+
+0XF8006114
+
+32
+
+RW
+
+0x000000
+
+Phy receiver enable register
+
    
+
+PHY_Config
+
+
+0XF8006118
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 0.
+
    
+
+PHY_Config
+
+
+0XF800611C
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 0.
+
    
+
+PHY_Config
+
+
+0XF8006120
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 0.
+
    
+
+PHY_Config
+
+
+0XF8006124
+
+32
+
+RW
+
+0x000000
+
+PHY configuration register for data slice 0.
+
    
+
+phy_init_ratio
+
+
+0XF800612C
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 0.
+
    
+
+phy_init_ratio
+
+
+0XF8006130
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 0.
+
    
+
+phy_init_ratio
+
+
+0XF8006134
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 0.
+
    
+
+phy_init_ratio
+
+
+0XF8006138
+
+32
+
+RW
+
+0x000000
+
+PHY init ratio register for data slice 0.
+
    
+
+phy_rd_dqs_cfg
+
+
+0XF8006140
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 0.
+
    
+
+phy_rd_dqs_cfg
+
+
+0XF8006144
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 0.
+
    
+
+phy_rd_dqs_cfg
+
+
+0XF8006148
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 0.
+
    
+
+phy_rd_dqs_cfg
+
+
+0XF800614C
+
+32
+
+RW
+
+0x000000
+
+PHY read DQS configuration register for data slice 0.
+
    
+
+phy_wr_dqs_cfg
+
+
+0XF8006154
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 0.
+
    
+
+phy_wr_dqs_cfg
+
+
+0XF8006158
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 0.
+
    
+
+phy_wr_dqs_cfg
+
+
+0XF800615C
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 0.
+
    
+
+phy_wr_dqs_cfg
+
+
+0XF8006160
+
+32
+
+RW
+
+0x000000
+
+PHY write DQS configuration register for data slice 0.
+
    
+
+phy_we_cfg
+
+
+0XF8006168
+
+32
+
+RW
+
+0x000000
+
+PHY fifo write enable configuration register for data slice 0.
+
    
+
+phy_we_cfg
+
+
+0XF800616C
+
+32
+
+RW
+
+0x000000
+
+PHY fifo write enable configuration register for data slice 0.
+
    
+
+phy_we_cfg
+
+
+0XF8006170
+
+32
+
+RW
+
+0x000000
+
+PHY fifo write enable configuration register for data slice 0.
+
    
+
+phy_we_cfg
+
+
+0XF8006174
+
+32
+
+RW
+
+0x000000
+
+PHY fifo write enable configuration register for data slice 0.
+
    
+
+wr_data_slv
+
+
+0XF800617C
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio configuration register for data slice 0.
+
    
+
+wr_data_slv
+
+
+0XF8006180
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio configuration register for data slice 0.
+
    
+
+wr_data_slv
+
+
+0XF8006184
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio configuration register for data slice 0.
+
    
+
+wr_data_slv
+
+
+0XF8006188
+
+32
+
+RW
+
+0x000000
+
+PHY write data slave ratio configuration register for data slice 0.
+
    
+
+reg_64
+
+
+0XF8006190
+
+32
+
+RW
+
+0x000000
+
+Training control register (2)
+
    
+
+reg_65
+
+
+0XF8006194
+
+32
+
+RW
+
+0x000000
+
+Training control register (3)
+
    
+
+page_mask
+
+
+0XF8006204
+
+32
+
+RW
+
+0x000000
+
+Page mask register
+
    
+
+axi_priority_wr_port
+
+
+0XF8006208
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 0.
+
    
+
+axi_priority_wr_port
+
+
+0XF800620C
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 0.
+
    
+
+axi_priority_wr_port
+
+
+0XF8006210
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 0.
+
    
+
+axi_priority_wr_port
+
+
+0XF8006214
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for write port 0.
+
    
+
+axi_priority_rd_port
+
+
+0XF8006218
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 0.
+
    
+
+axi_priority_rd_port
+
+
+0XF800621C
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 0.
+
    
+
+axi_priority_rd_port
+
+
+0XF8006220
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 0.
+
    
+
+axi_priority_rd_port
+
+
+0XF8006224
+
+32
+
+RW
+
+0x000000
+
+AXI Priority control for read port 0.
+
    
+
+lpddr_ctrl0
+
+
+0XF80062A8
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 0 Register
+
    
+
+lpddr_ctrl1
+
+
+0XF80062AC
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 1 Register
+
    
+
+lpddr_ctrl2
+
+
+0XF80062B0
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 2 Register
+
    
+
+lpddr_ctrl3
+
+
+0XF80062B4
+
+32
+
+RW
+
+0x000000
+
+LPDDR2 Control 3 Register
+
    
+
+ddrc_ctrl
+
+
+0XF8006000
+
+32
+
+RW
+
+0x000000
+
+DDRC Control Register
+
    
+
    
+
    ps7_ddr_init_data_1_0
    
+
+
+
+
+
+
+
+
+
+
    DDR INITIALIZATION
    
+
    LOCK DDR
    
+
    Register ( slcr )ddrc_ctrl
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ddrc_ctrl
+
+0XF8006000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_soft_rstb
+
+0:0
+
+1
+
+0
+
+0
+
+Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed.
+
    
+reg_ddrc_powerdown_en
+
+1:1
+
+2
+
+0
+
+0
+
+Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation.
+
    
+reg_ddrc_data_bus_width
+
+3:2
+
+c
+
+0
+
+0
+
+DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved
+
    
+reg_ddrc_burst8_refresh
+
+6:4
+
+70
+
+0
+
+0
+
+Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh
+
    
+reg_ddrc_rdwr_idle_gap
+
+13:7
+
+3f80
+
+1
+
+80
+
+When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.
+
    
+reg_ddrc_dis_rd_bypass
+
+14:14
+
+4000
+
+0
+
+0
+
+Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits.
+
    
+reg_ddrc_dis_act_bypass
+
+15:15
+
+8000
+
+0
+
+0
+
+Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates.
+
    
+reg_ddrc_dis_auto_refresh
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.
+
    
+ddrc_ctrl@0XF8006000
+
+31:0
+
+1ffff
+
+
+
+80
+
+DDRC Control Register
+
    
+
    
+
    Register ( slcr )Two_rank_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Two_rank_cfg
+
+0XF8006004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_t_rfc_nom_x32
+
+11:0
+
+fff
+
+81
+
+81
+
+tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM RELATED. Default value is set for DDR3.
+
    
+reg_ddrc_active_ranks
+
+13:12
+
+3000
+
+1
+
+1000
+
+Only present for multi-rank configurations. Each bit represents one rank. 1=populated; 0=unpopulated 01 = One Rank 11 = Two Ranks Others = Reserved
+
    
+reg_ddrc_addrmap_cs_bit0
+
+18:14
+
+7c000
+
+0
+
+0
+
+Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0.
+
    
+reg_ddrc_wr_odt_block
+
+20:19
+
+180000
+
+1
+
+80000
+
+00 = block read/write scheduling for 1-cycle when Write requires changing ODT settings 01 = block read/write scheduling for 2 cycles when Write requires changing ODT settings 10 = block read/write scheduling for 3 cycles when Write requires changing ODT settings 11 = Reserved
+
    
+reg_ddrc_diff_rank_rd_2cycle_gap
+
+21:21
+
+200000
+
+0
+
+0
+
+Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0 = schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1 = schedule 2 cycle gap for the same
+
    
+reg_ddrc_addrmap_cs_bit1
+
+26:22
+
+7c00000
+
+0
+
+0
+
+Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0.
+
    
+reg_ddrc_addrmap_open_bank
+
+27:27
+
+8000000
+
+0
+
+0
+
+Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map to Open Bank mode
+
    
+reg_ddrc_addrmap_4bank_ram
+
+28:28
+
+10000000
+
+0
+
+0
+
+Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map for 4 Bank RAMs
+
    
+Two_rank_cfg@0XF8006004
+
+31:0
+
+1fffffff
+
+
+
+81081
+
+Two rank configuration register
+
    
+
    
+
    Register ( slcr )HPR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+HPR_reg
+
+0XF8006008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_hpr_min_non_critical_x32
+
+10:0
+
+7ff
+
+f
+
+f
+
+Number of clocks that the HPR queue is guaranteed to be non-critical. Unit: 32 clocks
+
    
+reg_ddrc_hpr_max_starve_x32
+
+21:11
+
+3ff800
+
+f
+
+7800
+
+Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks
+
    
+reg_ddrc_hpr_xact_run_length
+
+25:22
+
+3c00000
+
+f
+
+3c00000
+
+Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available.
+
    
+HPR_reg@0XF8006008
+
+31:0
+
+3ffffff
+
+
+
+3c0780f
+
+HPR Queue control register
+
    
+
    
+
    Register ( slcr )LPR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LPR_reg
+
+0XF800600C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_lpr_min_non_critical_x32
+
+10:0
+
+7ff
+
+1
+
+1
+
+Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks
+
    
+reg_ddrc_lpr_max_starve_x32
+
+21:11
+
+3ff800
+
+2
+
+1000
+
+Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks
+
    
+reg_ddrc_lpr_xact_run_length
+
+25:22
+
+3c00000
+
+8
+
+2000000
+
+Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available
+
    
+LPR_reg@0XF800600C
+
+31:0
+
+3ffffff
+
+
+
+2001001
+
+LPR Queue control register
+
    
+
    
+
    Register ( slcr )WR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+WR_reg
+
+0XF8006010
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_w_min_non_critical_x32
+
+10:0
+
+7ff
+
+1
+
+1
+
+Number of clock cycles that the WR queue is guaranteed to be non-critical.
+
    
+reg_ddrc_w_xact_run_length
+
+14:11
+
+7800
+
+8
+
+4000
+
+Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available
+
    
+reg_ddrc_w_max_starve_x32
+
+25:15
+
+3ff8000
+
+2
+
+10000
+
+Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY.
+
    
+WR_reg@0XF8006010
+
+31:0
+
+3ffffff
+
+
+
+14001
+
+WR Queue control register
+
    
+
    
+
    Register ( slcr )DRAM_param_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg0
+
+0XF8006014
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_t_rc
+
+5:0
+
+3f
+
+1b
+
+1b
+
+tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM RELATED. Default value is set for DDR3.
+
    
+reg_ddrc_t_rfc_min
+
+13:6
+
+3fc0
+
+56
+
+1580
+
+tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns). DRAM RELATED. Default value is set for DDR3.
+
    
+reg_ddrc_post_selfref_gap_x32
+
+20:14
+
+1fc000
+
+10
+
+40000
+
+Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks DRAM RELATED
+
    
+DRAM_param_reg0@0XF8006014
+
+31:0
+
+1fffff
+
+
+
+4159b
+
+DRAM Parameters register 0
+
    
+
    
+
    Register ( slcr )DRAM_param_reg1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg1
+
+0XF8006018
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_wr2pre
+
+4:0
+
+1f
+
+12
+
+12
+
+Minimum time between write and precharge to same bank Non-LPDDR2 -> WL + BL/2 + tWR LPDDR2 -> WL + BL/2 + tWR + 1 Unit: Clocks where, WL = write latency. BL = burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs.
+
    
+reg_ddrc_powerdown_to_x32
+
+9:5
+
+3e0
+
+6
+
+c0
+
+After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks.
+
    
+reg_ddrc_t_faw
+
+15:10
+
+fc00
+
+10
+
+4000
+
+tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks DRAM RELATED.
+
    
+reg_ddrc_t_ras_max
+
+21:16
+
+3f0000
+
+24
+
+240000
+
+tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM RELATED.
+
    
+reg_ddrc_t_ras_min
+
+26:22
+
+7c00000
+
+14
+
+5000000
+
+tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns). Unit: clocks DRAM RELATED. Default value is set for DDR3.
+
    
+reg_ddrc_t_cke
+
+31:28
+
+f0000000
+
+4
+
+40000000
+
+Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. LPDDR2 mode: Set this to the larger of tCKE or tCKESR. Non-LPDDR2 designs: Set this to tCKE value. Unit: clocks.
+
    
+DRAM_param_reg1@0XF8006018
+
+31:0
+
+f7ffffff
+
+
+
+452440d2
+
+DRAM Parameters register 1
+
    
+
    
+
    Register ( slcr )DRAM_param_reg2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg2
+
+0XF800601C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_write_latency
+
+4:0
+
+1f
+
+5
+
+5
+
+Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2/3 -> WL -1 LPDDR -> 1 LPDDR2 ->WL Where WL = Write Latency of DRAM DRAM RELATED.
+
    
+reg_ddrc_rd2wr
+
+9:5
+
+3e0
+
+7
+
+e0
+
+Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. non-LPDDR2 -> RL + BL/2 + 2 - WL LPDDR2 -> RL + BL/2 + RU(tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED.
+
    
+reg_ddrc_wr2rd
+
+14:10
+
+7c00
+
+e
+
+3800
+
+Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. non-LPDDR2 -> WL + tWTR + BL/2 LPDDR2 -> WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL = Write latency, BL = burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs.
+
    
+reg_ddrc_t_xp
+
+19:15
+
+f8000
+
+4
+
+20000
+
+tXP: Minimum time after power down exit to any operation. DRAM RELATED.
+
    
+reg_ddrc_pad_pd
+
+22:20
+
+700000
+
+0
+
+0
+
+If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks.
+
    
+reg_ddrc_rd2pre
+
+27:23
+
+f800000
+
+4
+
+2000000
+
+Minimum time from read to precharge of same bank DDR2 -> AL + BL/2 + max(tRTP, 2) - 2 DDR3 -> AL + max (tRTP, 4) mDDR -> BL/2 LPDDR2 -> BL/2 + tRTP - 1 AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED
+
    
+reg_ddrc_t_rcd
+
+31:28
+
+f0000000
+
+7
+
+70000000
+
+tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency DRAM RELATED
+
    
+DRAM_param_reg2@0XF800601C
+
+31:0
+
+ffffffff
+
+
+
+720238e5
+
+DRAM Parameters register 2
+
    
+
    
+
    Register ( slcr )DRAM_param_reg3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg3
+
+0XF8006020
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_t_ccd
+
+4:2
+
+1c
+
+4
+
+10
+
+tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1 DRAM RELATED
+
    
+reg_ddrc_t_rrd
+
+7:5
+
+e0
+
+4
+
+80
+
+tRRD - Minimum time between activates from bank a to bank b. (spec: 10ns or less) DRAM RELATED
+
    
+reg_ddrc_refresh_margin
+
+11:8
+
+f00
+
+2
+
+200
+
+Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value.
+
    
+reg_ddrc_t_rp
+
+15:12
+
+f000
+
+7
+
+7000
+
+tRP - Minimum time from precharge to activate of same bank. DRAM RELATED
+
    
+reg_ddrc_refresh_to_x32
+
+20:16
+
+1f0000
+
+8
+
+80000
+
+If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller.
+
    
+reg_ddrc_sdram
+
+21:21
+
+200000
+
+1
+
+200000
+
+1 = sdram device 0 = non-sdram device
+
    
+reg_ddrc_mobile
+
+22:22
+
+400000
+
+0
+
+0
+
+1= mobile/LPDDR DRAM device in use. 0=non-mobile DRAM device in use.
+
    
+reg_ddrc_clock_stop_en
+
+23:23
+
+800000
+
+0
+
+0
+
+1=enable the assertion of stop_clk to the PHY whenever a clock is not required by LPDDR/ LPDDR2. 0=stop_clk will never be asserted. Note: This is only present for implementations supporting LPDDR/LPDDR2 devices.
+
    
+reg_ddrc_read_latency
+
+28:24
+
+1f000000
+
+7
+
+7000000
+
+Set to RL. Time from Read command to Read data on DRAM interface. Unit: clocks This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. RL = Read Latency of DRAM Note: This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped.
+
    
+reg_phy_mode_ddr1_ddr2
+
+29:29
+
+20000000
+
+1
+
+20000000
+
+unused
+
    
+reg_ddrc_dis_pad_pd
+
+30:30
+
+40000000
+
+0
+
+0
+
+1 = disable the pad power down feature 0 = Enable the pad power down feature.
+
    
+reg_ddrc_loopback
+
+31:31
+
+80000000
+
+0
+
+0
+
+unused
+
    
+DRAM_param_reg3@0XF8006020
+
+31:0
+
+fffffffc
+
+
+
+27287290
+
+DRAM Parameters register 3
+
    
+
    
+
    Register ( slcr )DRAM_param_reg4
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_param_reg4
+
+0XF8006024
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_en_2t_timing_mode
+
+0:0
+
+1
+
+0
+
+0
+
+1 = DDRC will use 2T timing 0 = DDRC will use 1T timing
+
    
+reg_ddrc_prefer_write
+
+1:1
+
+2
+
+0
+
+0
+
+1 = Bank selector prefers writes over reads
+
    
+reg_ddrc_max_rank_rd
+
+5:2
+
+3c
+
+f
+
+3c
+
+Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY.
+
    
+reg_ddrc_mr_wr
+
+6:6
+
+40
+
+0
+
+0
+
+A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and 'ddrc_reg_mr_wr_busy' is detected low.
+
    
+reg_ddrc_mr_addr
+
+8:7
+
+180
+
+0
+
+0
+
+Mode register address - for non-LPDDR2 modes. This register is don't care in LPDDR2 mode 00 = MR0 01 = MR1 10 = MR2 11 = MR3
+
    
+reg_ddrc_mr_data
+
+24:9
+
+1fffe00
+
+0
+
+0
+
+Mode register write data - for non-LPDDR2 modes. For LPDDR2, these 16-bits are interpreted as Writes: \'7bMR Addr[7:0], MR Data[7:0]\'7d. Reads: \'7bMR Addr[7:0], Don't Care[7:0]\'7d
+
    
+ddrc_reg_mr_wr_busy
+
+25:25
+
+2000000
+
+0
+
+0
+
+Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 1 = Indicates that mode register write / read operation is in progress. 0 = Indicates that the core can initiate a mode register write / read operation.
+
    
+reg_ddrc_mr_type
+
+26:26
+
+4000000
+
+0
+
+0
+
+Indicates whether the Mode register operation is read or write 1 = read 0 = write
+
    
+reg_ddrc_mr_rdata_valid
+
+27:27
+
+8000000
+
+0
+
+0
+
+This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 1'b0 by default. This bit will be cleared (1'b0), whenever a Mode Register Read command is issued. This bit will be set to 1'b1, when the Mode Register Read Data is written to register 0xA9.
+
    
+DRAM_param_reg4@0XF8006024
+
+31:0
+
+fffffff
+
+
+
+3c
+
+DRAM Parameters register 4
+
    
+
    
+
    Register ( slcr )DRAM_init_param
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_init_param
+
+0XF8006028
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_final_wait_x32
+
+6:0
+
+7f
+
+7
+
+7
+
+Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3.
+
    
+reg_ddrc_pre_ocd_x32
+
+10:7
+
+780
+
+0
+
+0
+
+Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero.
+
    
+reg_ddrc_t_mrd
+
+13:11
+
+3800
+
+4
+
+2000
+
+tMRD - Cycles between Load Mode commands DRAM RELATED Default value is set for DDR3.
+
    
+DRAM_init_param@0XF8006028
+
+31:0
+
+3fff
+
+
+
+2007
+
+DRAM initialization parameters register
+
    
+
    
+
    Register ( slcr )DRAM_EMR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_EMR_reg
+
+0XF800602C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_emr2
+
+15:0
+
+ffff
+
+8
+
+8
+
+Non LPDDR2- Value to be loaded into DRAM EMR2 registers. For LPDDR2 - Value to Write to the MR3 register
+
    
+reg_ddrc_emr3
+
+31:16
+
+ffff0000
+
+0
+
+0
+
+Non LPDDR2- Value to be loaded into DRAM EMR3 registers. Used in non-LPDDR2 designs only.
+
    
+DRAM_EMR_reg@0XF800602C
+
+31:0
+
+ffffffff
+
+
+
+8
+
+DRAM EMR2, EMR3 access register
+
    
+
    
+
    Register ( slcr )DRAM_EMR_MR_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_EMR_MR_reg
+
+0XF8006030
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_mr
+
+15:0
+
+ffff
+
+930
+
+930
+
+Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register
+
    
+reg_ddrc_emr
+
+31:16
+
+ffff0000
+
+4
+
+40000
+
+Non LPDDR2-Value to be loaded into DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. For LPDDR2 - Value to Write to the MR2 register
+
    
+DRAM_EMR_MR_reg@0XF8006030
+
+31:0
+
+ffffffff
+
+
+
+40930
+
+DRAM EMR, MR access register
+
    
+
    
+
    Register ( slcr )DRAM_burst8_rdwr
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_burst8_rdwr
+
+0XF8006034
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_burst_rdwr
+
+3:0
+
+f
+
+4
+
+4
+
+This controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. In LPDDR and LPDDR2, Burst length of 16 is supported only in Half Bus Width mode. Every input read/write command has 4 cycles of data associated with it and that is not enough data for doing Burst Length16 in Full Bus Width mode. 0010 - Burst length of 4 0100 - Burst length of 8 1000 - Burst length of 16 (only supported for LPDDR AND LPDDR2) All other values are reserved
+
    
+reg_ddrc_pre_cke_x1024
+
+13:4
+
+3ff0
+
+105
+
+1050
+
+Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min)
+
    
+reg_ddrc_post_cke_x1024
+
+25:16
+
+3ff0000
+
+1
+
+10000
+
+Cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us.
+
    
+reg_ddrc_burstchop
+
+28:28
+
+10000000
+
+0
+
+0
+
+Feature not supported. When 1, Controller is out in burstchop mode.
+
    
+DRAM_burst8_rdwr@0XF8006034
+
+31:0
+
+13ff3fff
+
+
+
+11054
+
+DRAM burst 8 read/write register
+
    
+
    
+
    Register ( slcr )DRAM_disable_DQ
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_disable_DQ
+
+0XF8006038
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_force_low_pri_n
+
+0:0
+
+1
+
+0
+
+0
+
+Active Low signal. When asserted (0), all incoming transactions will be forced to low priority. Forcing the incoming transactions to low priority implicitly turns OFF Bypass. Otherwise, HPR is allowed if enabled in the AXI priority read registers.
+
    
+reg_ddrc_dis_dq
+
+1:1
+
+2
+
+0
+
+0
+
+When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. This bit is intended to be switched on-the-fly
+
    
+reg_phy_debug_mode
+
+6:6
+
+40
+
+0
+
+0
+
+Not Applicable in this PHY.
+
    
+reg_phy_wr_level_start
+
+7:7
+
+80
+
+0
+
+0
+
+Not Applicable in this PHY.
+
    
+reg_phy_rd_level_start
+
+8:8
+
+100
+
+0
+
+0
+
+Not Applicable in this PHY.
+
    
+reg_phy_dq0_wait_t
+
+12:9
+
+1e00
+
+0
+
+0
+
+Not Applicable in this PHY.
+
    
+DRAM_disable_DQ@0XF8006038
+
+31:0
+
+1fc3
+
+
+
+0
+
+DRAM Disable DQ register
+
    
+
    
+
    Register ( slcr )DRAM_addr_map_bank
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_addr_map_bank
+
+0XF800603C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_addrmap_bank_b0
+
+3:0
+
+f
+
+7
+
+7
+
+Selects the address bits used as bank address bit 0. Valid Range: 0 to 14 Internal Base: 5 The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_bank_b1
+
+7:4
+
+f0
+
+7
+
+70
+
+Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_bank_b2
+
+11:8
+
+f00
+
+7
+
+700
+
+Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0.
+
    
+reg_ddrc_addrmap_col_b5
+
+15:12
+
+f000
+
+0
+
+0
+
+Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9
+
    
+reg_ddrc_addrmap_col_b6
+
+19:16
+
+f0000
+
+0
+
+0
+
+Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9
+
    
+DRAM_addr_map_bank@0XF800603C
+
+31:0
+
+fffff
+
+
+
+777
+
+Selects the address bits used as DRAM bank address bits
+
    
+
    
+
    Register ( slcr )DRAM_addr_map_col
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_addr_map_col
+
+0XF8006040
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_addrmap_col_b2
+
+3:0
+
+f
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_col_b3
+
+7:4
+
+f0
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_col_b4
+
+11:8
+
+f00
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_col_b7
+
+15:12
+
+f000
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b8
+
+19:16
+
+f0000
+
+0
+
+0
+
+Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b9
+
+23:20
+
+f00000
+
+f
+
+f00000
+
+Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b10
+
+27:24
+
+f000000
+
+f
+
+f000000
+
+Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+reg_ddrc_addrmap_col_b11
+
+31:28
+
+f0000000
+
+f
+
+f0000000
+
+Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used.
+
    
+DRAM_addr_map_col@0XF8006040
+
+31:0
+
+ffffffff
+
+
+
+fff00000
+
+Selects the address bits used as DRAM column address bits
+
    
+
    
+
    Register ( slcr )DRAM_addr_map_row
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_addr_map_row
+
+0XF8006044
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_addrmap_row_b0
+
+3:0
+
+f
+
+6
+
+6
+
+Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field
+
    
+reg_ddrc_addrmap_row_b1
+
+7:4
+
+f0
+
+6
+
+60
+
+Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_row_b2_11
+
+11:8
+
+f00
+
+6
+
+600
+
+Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field.
+
    
+reg_ddrc_addrmap_row_b12
+
+15:12
+
+f000
+
+6
+
+6000
+
+Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0.
+
    
+reg_ddrc_addrmap_row_b13
+
+19:16
+
+f0000
+
+6
+
+60000
+
+Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0.
+
    
+reg_ddrc_addrmap_row_b14
+
+23:20
+
+f00000
+
+6
+
+600000
+
+Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0.
+
    
+reg_ddrc_addrmap_row_b15
+
+27:24
+
+f000000
+
+f
+
+f000000
+
+Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0.
+
    
+DRAM_addr_map_row@0XF8006044
+
+31:0
+
+fffffff
+
+
+
+f666666
+
+Selects the address bits used as DRAM row address bits
+
    
+
    
+
    Register ( slcr )DRAM_ODT_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DRAM_ODT_reg
+
+0XF8006048
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_rank0_rd_odt
+
+2:0
+
+7
+
+0
+
+0
+
+Unused. [1:0] - Indicates which remote ODT's must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during reads to rank 0.
+
    
+reg_ddrc_rank0_wr_odt
+
+5:3
+
+38
+
+1
+
+8
+
+[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during writes to rank 0.
+
    
+reg_ddrc_rank1_rd_odt
+
+8:6
+
+1c0
+
+1
+
+40
+
+Unused
+
    
+reg_ddrc_rank1_wr_odt
+
+11:9
+
+e00
+
+1
+
+200
+
+Unused
+
    
+reg_phy_rd_local_odt
+
+13:12
+
+3000
+
+0
+
+0
+
+Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage.
+
    
+reg_phy_wr_local_odt
+
+15:14
+
+c000
+
+3
+
+c000
+
+Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS.
+
    
+reg_phy_idle_local_odt
+
+17:16
+
+30000
+
+3
+
+30000
+
+Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle.
+
    
+reg_ddrc_rank2_rd_odt
+
+20:18
+
+1c0000
+
+0
+
+0
+
+Unused
+
    
+reg_ddrc_rank2_wr_odt
+
+23:21
+
+e00000
+
+0
+
+0
+
+Unused
+
    
+reg_ddrc_rank3_rd_odt
+
+26:24
+
+7000000
+
+0
+
+0
+
+Unused
+
    
+reg_ddrc_rank3_wr_odt
+
+29:27
+
+38000000
+
+0
+
+0
+
+Unused
+
    
+DRAM_ODT_reg@0XF8006048
+
+31:0
+
+3fffffff
+
+
+
+3c248
+
+DRAM ODT register
+
    
+
    
+
    Register ( slcr )phy_cmd_timeout_rddata_cpt
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_cmd_timeout_rddata_cpt
+
+0XF8006050
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_cmd_to_data
+
+3:0
+
+f
+
+0
+
+0
+
+Not used in DFI PHY.
+
    
+reg_phy_wr_cmd_to_data
+
+7:4
+
+f0
+
+0
+
+0
+
+Not used in DFI PHY.
+
    
+reg_phy_rdc_we_to_re_delay
+
+11:8
+
+f00
+
+8
+
+800
+
+This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1.
+
    
+reg_phy_rdc_fifo_rst_disable
+
+15:15
+
+8000
+
+0
+
+0
+
+When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty.
+
    
+reg_phy_use_fixed_re
+
+16:16
+
+10000
+
+1
+
+10000
+
+When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH.
+
    
+reg_phy_rdc_fifo_rst_err_cnt_clr
+
+17:17
+
+20000
+
+0
+
+0
+
+Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed.
+
    
+reg_phy_dis_phy_ctrl_rstn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset.
+
    
+reg_phy_clk_stall_level
+
+19:19
+
+80000
+
+0
+
+0
+
+1 = stall clock, for DLL aging control
+
    
+reg_phy_gatelvl_num_of_dq0
+
+27:24
+
+f000000
+
+7
+
+7000000
+
+This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.
+
    
+reg_phy_wrlvl_num_of_dq0
+
+31:28
+
+f0000000
+
+7
+
+70000000
+
+This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer.
+
    
+phy_cmd_timeout_rddata_cpt@0XF8006050
+
+31:0
+
+ff0f8fff
+
+
+
+77010800
+
+PHY command time out and read data capture FIFO register
+
    
+
    
+
    Register ( slcr )DLL_calib
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DLL_calib
+
+0XF8006058
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_dll_calib_to_min_x1024
+
+7:0
+
+ff
+
+1
+
+1
+
+Unused in DFI Controller.
+
    
+reg_ddrc_dll_calib_to_max_x1024
+
+15:8
+
+ff00
+
+1
+
+100
+
+Unused in DFI Controller.
+
    
+reg_ddrc_dis_dll_calib
+
+16:16
+
+10000
+
+0
+
+0
+
+When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically
+
    
+DLL_calib@0XF8006058
+
+31:0
+
+1ffff
+
+
+
+101
+
+DLL calibration register
+
    
+
    
+
    Register ( slcr )ODT_delay_hold
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ODT_delay_hold
+
+0XF800605C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_rd_odt_delay
+
+3:0
+
+f
+
+3
+
+3
+
+UNUSED
+
    
+reg_ddrc_wr_odt_delay
+
+7:4
+
+f0
+
+0
+
+0
+
+The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable for LPDDR and LPDDR2 modes.
+
    
+reg_ddrc_rd_odt_hold
+
+11:8
+
+f00
+
+0
+
+0
+
+Unused
+
    
+reg_ddrc_wr_odt_hold
+
+15:12
+
+f000
+
+5
+
+5000
+
+Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4
+
    
+ODT_delay_hold@0XF800605C
+
+31:0
+
+ffff
+
+
+
+5003
+
+ODT delay and ODT hold register
+
    
+
    
+
    Register ( slcr )ctrl_reg1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg1
+
+0XF8006060
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_pageclose
+
+0:0
+
+1
+
+0
+
+0
+
+If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used.
+
    
+reg_ddrc_lpr_num_entries
+
+6:1
+
+7e
+
+1f
+
+3e
+
+Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored.
+
    
+reg_ddrc_auto_pre_en
+
+7:7
+
+80
+
+0
+
+0
+
+When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.)
+
    
+reg_ddrc_refresh_update_level
+
+8:8
+
+100
+
+0
+
+0
+
+Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially.
+
    
+reg_ddrc_dis_wc
+
+9:9
+
+200
+
+0
+
+0
+
+When 1, disable Write Combine
+
    
+reg_ddrc_dis_collision_page_opt
+
+10:10
+
+400
+
+0
+
+0
+
+When this is set to '0', auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word).
+
    
+reg_ddrc_selfref_en
+
+12:12
+
+1000
+
+0
+
+0
+
+If 1, then the controller will put the DRAM into self refresh when the transaction store is empty.
+
    
+ctrl_reg1@0XF8006060
+
+31:0
+
+17ff
+
+
+
+3e
+
+Controller register 1
+
    
+
    
+
    Register ( slcr )ctrl_reg2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg2
+
+0XF8006064
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_go2critical_hysteresis
+
+12:5
+
+1fe0
+
+0
+
+0
+
+Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0.
+
    
+reg_arb_go2critical_en
+
+17:17
+
+20000
+
+1
+
+20000
+
+1 - Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on 'urgent' input coming from AXI master. 0 - Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 1'b0.
+
    
+ctrl_reg2@0XF8006064
+
+31:0
+
+21fe0
+
+
+
+20000
+
+Controller register 2
+
    
+
    
+
    Register ( slcr )ctrl_reg3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg3
+
+0XF8006068
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_wrlvl_ww
+
+7:0
+
+ff
+
+41
+
+41
+
+Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) Only present in designs that support DDR3 and LPDDR2 devices.
+
    
+reg_ddrc_rdlvl_rr
+
+15:8
+
+ff00
+
+41
+
+4100
+
+Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Only present in designs that support DDR3 devices
+
    
+reg_ddrc_dfi_t_wlmrd
+
+25:16
+
+3ff0000
+
+28
+
+280000
+
+First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. Only present in designs that support DDR3 devices.
+
    
+ctrl_reg3@0XF8006068
+
+31:0
+
+3ffffff
+
+
+
+284141
+
+Controller register 3
+
    
+
    
+
    Register ( slcr )ctrl_reg4
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ctrl_reg4
+
+0XF800606C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+dfi_t_ctrlupd_interval_min_x1024
+
+7:0
+
+ff
+
+10
+
+10
+
+This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks
+
    
+dfi_t_ctrlupd_interval_max_x1024
+
+15:8
+
+ff00
+
+16
+
+1600
+
+This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks
+
    
+ctrl_reg4@0XF800606C
+
+31:0
+
+ffff
+
+
+
+1610
+
+Controller register 4
+
    
+
    
+
    Register ( slcr )CHE_REFRESH_TIMER01
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_REFRESH_TIMER01
+
+0XF80060A0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+refresh_timer0_start_value_x32
+
+11:0
+
+fff
+
+0
+
+0
+
+Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY.
+
    
+refresh_timer1_start_value_x32
+
+23:12
+
+fff000
+
+8
+
+8000
+
+Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY.
+
    
+CHE_REFRESH_TIMER01@0XF80060A0
+
+31:0
+
+ffffff
+
+
+
+8000
+
+CHE_REFRESH_TIMER01
+
    
+
    
+
    Register ( slcr )CHE_T_ZQ
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_T_ZQ
+
+0XF80060A4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_dis_auto_zq
+
+0:0
+
+1
+
+0
+
+0
+
+1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices.
+
    
+reg_ddrc_ddr3
+
+1:1
+
+2
+
+1
+
+2
+
+Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3.
+
    
+reg_ddrc_t_mod
+
+11:2
+
+ffc
+
+200
+
+800
+
+Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns)
+
    
+reg_ddrc_t_zq_long_nop
+
+21:12
+
+3ff000
+
+200
+
+200000
+
+Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices.
+
    
+reg_ddrc_t_zq_short_nop
+
+31:22
+
+ffc00000
+
+40
+
+10000000
+
+Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices.
+
    
+CHE_T_ZQ@0XF80060A4
+
+31:0
+
+ffffffff
+
+
+
+10200802
+
+ZQ parameters register
+
    
+
    
+
    Register ( slcr )CHE_T_ZQ_Short_Interval_Reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_T_ZQ_Short_Interval_Reg
+
+0XF80060A8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+t_zq_short_interval_x1024
+
+19:0
+
+fffff
+
+cb73
+
+cb73
+
+Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices.
+
    
+dram_rstn_x1024
+
+27:20
+
+ff00000
+
+69
+
+6900000
+
+Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only.
+
    
+CHE_T_ZQ_Short_Interval_Reg@0XF80060A8
+
+31:0
+
+fffffff
+
+
+
+690cb73
+
+Misc parameters register
+
    
+
    
+
    Register ( slcr )deep_pwrdwn_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+deep_pwrdwn_reg
+
+0XF80060AC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+deeppowerdown_en
+
+0:0
+
+1
+
+0
+
+0
+
+1 - Controller puts the DRAM into Deep Powerdown mode when the transaction store is empty. 0 - Brings Controller out of Deep Powerdown mode Present only in designs configured to support LPDDR or LPDDR2 FOR PERFORMANCE ONLY.
+
    
+deeppowerdown_to_x1024
+
+8:1
+
+1fe
+
+ff
+
+1fe
+
+Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY.
+
    
+deep_pwrdwn_reg@0XF80060AC
+
+31:0
+
+1ff
+
+
+
+1fe
+
+Deep powerdown register
+
    
+
    
+
    Register ( slcr )reg_2c
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_2c
+
+0XF80060B0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+dfi_wrlvl_max_x1024
+
+11:0
+
+fff
+
+fff
+
+fff
+
+Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks
+
    
+dfi_rdlvl_max_x1024
+
+23:12
+
+fff000
+
+fff
+
+fff000
+
+Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks
+
    
+ddrc_reg_twrlvl_max_error
+
+24:24
+
+1000000
+
+0
+
+0
+
+When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3.
+
    
+ddrc_reg_trdlvl_max_error
+
+25:25
+
+2000000
+
+0
+
+0
+
+When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3 or LPDDR2 devices.
+
    
+reg_ddrc_dfi_wr_level_en
+
+26:26
+
+4000000
+
+1
+
+4000000
+
+1 = Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0 = Write leveling disabled.
+
    
+reg_ddrc_dfi_rd_dqs_gate_level
+
+27:27
+
+8000000
+
+1
+
+8000000
+
+1 = Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0= Read DQS gate leveling is disabled.
+
    
+reg_ddrc_dfi_rd_data_eye_train
+
+28:28
+
+10000000
+
+1
+
+10000000
+
+1 = Read Data Eye training mode has been enabled as part of init sequence. Only present in designs that support DDR3 or LPDDR2 devices.
+
    
+reg_2c@0XF80060B0
+
+31:0
+
+1fffffff
+
+
+
+1cffffff
+
+Training control register
+
    
+
    
+
    Register ( slcr )reg_2d
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_2d
+
+0XF80060B4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_2t_delay
+
+8:0
+
+1ff
+
+0
+
+0
+
+Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature.
+
    
+reg_ddrc_skip_ocd
+
+9:9
+
+200
+
+1
+
+200
+
+This register must be kept at 1'b1. 1'b0 is NOT supported. 1 - Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0 - Not supported.
+
    
+reg_ddrc_dis_pre_bypass
+
+10:10
+
+400
+
+0
+
+0
+
+Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY.
+
    
+reg_2d@0XF80060B4
+
+31:0
+
+7ff
+
+
+
+200
+
+Misc Debug register
+
    
+
    
+
    Register ( slcr )dfi_timing
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+dfi_timing
+
+0XF80060B8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_dfi_t_rddata_en
+
+4:0
+
+1f
+
+6
+
+6
+
+Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. Non-LPDDR -> RL-1 LPDDR -> RL Where RL is read latency of DRAM.
+
    
+reg_ddrc_dfi_t_ctrlup_min
+
+14:5
+
+7fe0
+
+3
+
+60
+
+Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted.
+
    
+reg_ddrc_dfi_t_ctrlup_max
+
+24:15
+
+1ff8000
+
+40
+
+200000
+
+Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert.
+
    
+dfi_timing@0XF80060B8
+
+31:0
+
+1ffffff
+
+
+
+200066
+
+DFI timing register
+
    
+
    
+
    RESET ECC ERROR
    
+
    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_ECC_CONTROL_REG_OFFSET
+
+0XF80060C4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+Clear_Uncorrectable_DRAM_ECC_error
+
+0:0
+
+1
+
+1
+
+1
+
+Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters.
+
    
+Clear_Correctable_DRAM_ECC_error
+
+1:1
+
+2
+
+1
+
+2
+
+Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters.
+
    
+CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4
+
+31:0
+
+3
+
+
+
+3
+
+ECC error clear register
+
    
+
    
+
    Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_ECC_CONTROL_REG_OFFSET
+
+0XF80060C4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+Clear_Uncorrectable_DRAM_ECC_error
+
+0:0
+
+1
+
+0
+
+0
+
+Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters.
+
    
+Clear_Correctable_DRAM_ECC_error
+
+1:1
+
+2
+
+0
+
+0
+
+Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters.
+
    
+CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4
+
+31:0
+
+3
+
+
+
+0
+
+ECC error clear register
+
    
+
    
+
    Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_CORR_ECC_LOG_REG_OFFSET
+
+0XF80060C8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CORR_ECC_LOG_VALID
+
+0:0
+
+1
+
+0
+
+0
+
+Set to '1' when a correctable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x31)
+
    
+ECC_CORRECTED_BIT_NUM
+
+7:1
+
+fe
+
+0
+
+0
+
+Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined.
+
    
+CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8
+
+31:0
+
+ff
+
+
+
+0
+
+ECC error correction register
+
    
+
    
+
    Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_UNCORR_ECC_LOG_REG_OFFSET
+
+0XF80060DC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNCORR_ECC_LOG_VALID
+
+0:0
+
+1
+
+0
+
+0
+
+Set to '1' when an uncorrectable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x31).
+
    
+CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC
+
+31:0
+
+1
+
+
+
+0
+
+ECC unrecoverable error status register
+
    
+
    
+
    Register ( slcr )CHE_ECC_STATS_REG_OFFSET
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CHE_ECC_STATS_REG_OFFSET
+
+0XF80060F0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+STAT_NUM_CORR_ERR
+
+15:8
+
+ff00
+
+0
+
+0
+
+Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x58).
+
    
+STAT_NUM_UNCORR_ERR
+
+7:0
+
+ff
+
+0
+
+0
+
+Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x58).
+
    
+CHE_ECC_STATS_REG_OFFSET@0XF80060F0
+
+31:0
+
+ffff
+
+
+
+0
+
+ECC error count register
+
    
+
    
+
    Register ( slcr )ECC_scrub
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ECC_scrub
+
+0XF80060F4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_ecc_mode
+
+2:0
+
+7
+
+0
+
+0
+
+DRAM ECC Mode. The only valid values that works for this project are 3'b000 (No ECC) and 3'b100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 3'b100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 - No ECC, 001 - Reserved 010 - Parity 011 - Reserved 100 - SEC/DED over 1-beat 101 - SEC/DED over multiple beats 110 - Device Correction 111 - Reserved
+
    
+reg_ddrc_dis_scrub
+
+3:3
+
+8
+
+1
+
+8
+
+This feature is NOT supported. Only default value works. 1 - Disable ECC scrubs 0 - Enable ECC scrubs Valid only when reg_ddrc_ecc_mode = 3'b100.
+
    
+ECC_scrub@0XF80060F4
+
+31:0
+
+f
+
+
+
+8
+
+ECC mode/scrub register
+
    
+
    
+
    Register ( slcr )phy_rcvr_enable
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rcvr_enable
+
+0XF8006114
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_dif_on
+
+3:0
+
+f
+
+0
+
+0
+
+Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter.
+
    
+reg_phy_dif_off
+
+7:4
+
+f0
+
+0
+
+0
+
+Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used.
+
    
+phy_rcvr_enable@0XF8006114
+
+31:0
+
+ff
+
+
+
+0
+
+Phy receiver enable register
+
    
+
    
+
    Register ( slcr )PHY_Config
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config
+
+0XF8006118
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_board_lpbk_tx
+
+4:4
+
+10
+
+0
+
+0
+
+External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_board_lpbk_rx
+
+5:5
+
+20
+
+0
+
+0
+
+External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config@0XF8006118
+
+31:0
+
+7fffffff
+
+
+
+40000001
+
+PHY configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )PHY_Config
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config
+
+0XF800611C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_board_lpbk_tx
+
+4:4
+
+10
+
+0
+
+0
+
+External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_board_lpbk_rx
+
+5:5
+
+20
+
+0
+
+0
+
+External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config@0XF800611C
+
+31:0
+
+7fffffff
+
+
+
+40000001
+
+PHY configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )PHY_Config
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config
+
+0XF8006120
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_board_lpbk_tx
+
+4:4
+
+10
+
+0
+
+0
+
+External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_board_lpbk_rx
+
+5:5
+
+20
+
+0
+
+0
+
+External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config@0XF8006120
+
+31:0
+
+7fffffff
+
+
+
+40000001
+
+PHY configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )PHY_Config
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+PHY_Config
+
+0XF8006124
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_data_slice_in_use
+
+0:0
+
+1
+
+1
+
+1
+
+Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled.
+
    
+reg_phy_rdlvl_inc_mode
+
+1:1
+
+2
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_gatelvl_inc_mode
+
+2:2
+
+4
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_wrlvl_inc_mode
+
+3:3
+
+8
+
+0
+
+0
+
+RESERVED
+
    
+reg_phy_board_lpbk_tx
+
+4:4
+
+10
+
+0
+
+0
+
+External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_board_lpbk_rx
+
+5:5
+
+20
+
+0
+
+0
+
+External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode.
+
    
+reg_phy_bist_shift_dq
+
+14:6
+
+7fc0
+
+0
+
+0
+
+Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift.
+
    
+reg_phy_bist_err_clr
+
+23:15
+
+ff8000
+
+0
+
+0
+
+Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect
+
    
+reg_phy_dq_offset
+
+30:24
+
+7f000000
+
+40
+
+40000000
+
+Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice.
+
    
+PHY_Config@0XF8006124
+
+31:0
+
+7fffffff
+
+
+
+40000001
+
+PHY configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_init_ratio
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio
+
+0XF800612C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+1d
+
+1d
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+f2
+
+3c800
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio@0XF800612C
+
+31:0
+
+fffff
+
+
+
+3c81d
+
+PHY init ratio register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_init_ratio
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio
+
+0XF8006130
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+12
+
+12
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+d8
+
+36000
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio@0XF8006130
+
+31:0
+
+fffff
+
+
+
+36012
+
+PHY init ratio register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_init_ratio
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio
+
+0XF8006134
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+c
+
+c
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+de
+
+37800
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio@0XF8006134
+
+31:0
+
+fffff
+
+
+
+3780c
+
+PHY init ratio register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_init_ratio
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_init_ratio
+
+0XF8006138
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wrlvl_init_ratio
+
+9:0
+
+3ff
+
+21
+
+21
+
+The user programmable init ratio used by Write Leveling FSM
+
    
+reg_phy_gatelvl_init_ratio
+
+19:10
+
+ffc00
+
+ee
+
+3b800
+
+The user programmable init ratio used Gate Leveling FSM
+
    
+phy_init_ratio@0XF8006138
+
+31:0
+
+fffff
+
+
+
+3b821
+
+PHY init ratio register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg
+
+0XF8006140
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg@0XF8006140
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg
+
+0XF8006144
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg@0XF8006144
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg
+
+0XF8006148
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg@0XF8006148
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_rd_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_rd_dqs_cfg
+
+0XF800614C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_rd_dqs_slave_ratio
+
+9:0
+
+3ff
+
+35
+
+35
+
+Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications
+
    
+reg_phy_rd_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus.
+
    
+reg_phy_rd_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value.
+
    
+phy_rd_dqs_cfg@0XF800614C
+
+31:0
+
+fffff
+
+
+
+35
+
+PHY read DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg
+
+0XF8006154
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+9d
+
+9d
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg@0XF8006154
+
+31:0
+
+fffff
+
+
+
+9d
+
+PHY write DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg
+
+0XF8006158
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+92
+
+92
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg@0XF8006158
+
+31:0
+
+fffff
+
+
+
+92
+
+PHY write DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg
+
+0XF800615C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+8c
+
+8c
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg@0XF800615C
+
+31:0
+
+fffff
+
+
+
+8c
+
+PHY write DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_wr_dqs_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_wr_dqs_cfg
+
+0XF8006160
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_dqs_slave_ratio
+
+9:0
+
+3ff
+
+a1
+
+a1
+
+Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_dqs_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus.
+
    
+reg_phy_wr_dqs_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value.
+
    
+phy_wr_dqs_cfg@0XF8006160
+
+31:0
+
+fffff
+
+
+
+a1
+
+PHY write DQS configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_we_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg
+
+0XF8006168
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+147
+
+147
+
+Ratio value to be used when fifo_we_X_force_mode is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.
+
    
+phy_we_cfg@0XF8006168
+
+31:0
+
+1fffff
+
+
+
+147
+
+PHY fifo write enable configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_we_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg
+
+0XF800616C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+12d
+
+12d
+
+Ratio value to be used when fifo_we_X_force_mode is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.
+
    
+phy_we_cfg@0XF800616C
+
+31:0
+
+1fffff
+
+
+
+12d
+
+PHY fifo write enable configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_we_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg
+
+0XF8006170
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+133
+
+133
+
+Ratio value to be used when fifo_we_X_force_mode is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.
+
    
+phy_we_cfg@0XF8006170
+
+31:0
+
+1fffff
+
+
+
+133
+
+PHY fifo write enable configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )phy_we_cfg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+phy_we_cfg
+
+0XF8006174
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_fifo_we_slave_ratio
+
+10:0
+
+7ff
+
+143
+
+143
+
+Ratio value to be used when fifo_we_X_force_mode is set to 0.
+
    
+reg_phy_fifo_we_in_force
+
+11:11
+
+800
+
+0
+
+0
+
+1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus.
+
    
+reg_phy_fifo_we_in_delay
+
+20:12
+
+1ff000
+
+0
+
+0
+
+Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported.
+
    
+phy_we_cfg@0XF8006174
+
+31:0
+
+1fffff
+
+
+
+143
+
+PHY fifo write enable configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )wr_data_slv
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv
+
+0XF800617C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+dd
+
+dd
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv@0XF800617C
+
+31:0
+
+fffff
+
+
+
+dd
+
+PHY write data slave ratio configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )wr_data_slv
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv
+
+0XF8006180
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+d2
+
+d2
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv@0XF8006180
+
+31:0
+
+fffff
+
+
+
+d2
+
+PHY write data slave ratio configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )wr_data_slv
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv
+
+0XF8006184
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+cc
+
+cc
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv@0XF8006184
+
+31:0
+
+fffff
+
+
+
+cc
+
+PHY write data slave ratio configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )wr_data_slv
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+wr_data_slv
+
+0XF8006188
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_data_slave_ratio
+
+9:0
+
+3ff
+
+e1
+
+e1
+
+Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_wr_data_slave_force
+
+10:10
+
+400
+
+0
+
+0
+
+1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus.
+
    
+reg_phy_wr_data_slave_delay
+
+19:11
+
+ff800
+
+0
+
+0
+
+If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value.
+
    
+wr_data_slv@0XF8006188
+
+31:0
+
+fffff
+
+
+
+e1
+
+PHY write data slave ratio configuration register for data slice 0.
+
    
+
    
+
    Register ( slcr )reg_64
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_64
+
+0XF8006190
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_loopback
+
+0:0
+
+1
+
+0
+
+0
+
+Loopback testing. 1: enable, 0: disable
+
    
+reg_phy_bl2
+
+1:1
+
+2
+
+0
+
+0
+
+Reserved for future Use.
+
    
+reg_phy_at_spd_atpg
+
+2:2
+
+4
+
+0
+
+0
+
+1 = run scan test at full clock speed but with less coverage 0 = run scan test at slow clock speed but with high coverage During normal function mode, this port must be set 0.
+
    
+reg_phy_bist_enable
+
+3:3
+
+8
+
+0
+
+0
+
+Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback.
+
    
+reg_phy_bist_force_err
+
+4:4
+
+10
+
+0
+
+0
+
+This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error.
+
    
+reg_phy_bist_mode
+
+6:5
+
+60
+
+0
+
+0
+
+The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 2'b00: constant pattern (0 repeated on each DQ bit) 2'b01: low freq pattern (00001111 repeated on each DQ bit) 2'b10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested
+
    
+reg_phy_invert_clkout
+
+7:7
+
+80
+
+1
+
+80
+
+Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling.
+
    
+reg_phy_all_dq_mpr_rd_resp
+
+8:8
+
+100
+
+0
+
+0
+
+1=assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) 0=(default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.)
+
    
+reg_phy_sel_logic
+
+9:9
+
+200
+
+0
+
+0
+
+Selects one of the two read leveling algorithms.'b0 = Select algorithm # 1'b1 = Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms
+
    
+reg_phy_ctrl_slave_ratio
+
+19:10
+
+ffc00
+
+100
+
+40000
+
+Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
+
    
+reg_phy_ctrl_slave_force
+
+20:20
+
+100000
+
+0
+
+0
+
+1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus.
+
    
+reg_phy_ctrl_slave_delay
+
+27:21
+
+fe00000
+
+0
+
+0
+
+If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18].
+
    
+reg_phy_use_rank0_delays
+
+28:28
+
+10000000
+
+1
+
+10000000
+
+Delay selection 1- Rank 0 delays are used for all ranks 0- Each Rank uses its own delay
+
    
+reg_phy_lpddr
+
+29:29
+
+20000000
+
+0
+
+0
+
+1= mobile/LPDDR DRAM device in use. 0=non-LPDDR DRAM device in use.
+
    
+reg_phy_cmd_latency
+
+30:30
+
+40000000
+
+0
+
+0
+
+If set to 1, command comes to phy_ctrl through a flop.
+
    
+reg_phy_int_lpbk
+
+31:31
+
+80000000
+
+0
+
+0
+
+1=enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0.
+
    
+reg_64@0XF8006190
+
+31:0
+
+ffffffff
+
+
+
+10040080
+
+Training control register (2)
+
    
+
    
+
    Register ( slcr )reg_65
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+reg_65
+
+0XF8006194
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_phy_wr_rl_delay
+
+4:0
+
+1f
+
+2
+
+2
+
+This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1.
+
    
+reg_phy_rd_rl_delay
+
+9:5
+
+3e0
+
+4
+
+80
+
+This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1.
+
    
+reg_phy_dll_lock_diff
+
+13:10
+
+3c00
+
+f
+
+3c00
+
+The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted
+
    
+reg_phy_use_wr_level
+
+14:14
+
+4000
+
+1
+
+4000
+
+Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure.
+
    
+reg_phy_use_rd_dqs_gate_level
+
+15:15
+
+8000
+
+1
+
+8000
+
+Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure.
+
    
+reg_phy_use_rd_data_eye_level
+
+16:16
+
+10000
+
+1
+
+10000
+
+Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure
+
    
+reg_phy_dis_calib_rst
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs
+
    
+reg_phy_ctrl_slave_delay
+
+19:18
+
+c0000
+
+0
+
+0
+
+If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value
+
    
+reg_65@0XF8006194
+
+31:0
+
+fffff
+
+
+
+1fc82
+
+Training control register (3)
+
    
+
    
+
    Register ( slcr )page_mask
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+page_mask
+
+0XF8006204
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_page_addr_mask
+
+31:0
+
+ffffffff
+
+0
+
+0
+
+This register must be set based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match.
+
    
+page_mask@0XF8006204
+
+31:0
+
+ffffffff
+
+
+
+0
+
+Page mask register
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port
+
+0XF8006208
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_dis_rmw_portn
+
+19:19
+
+80000
+
+1
+
+80000
+
+FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.
+
    
+axi_priority_wr_port@0XF8006208
+
+31:0
+
+f03ff
+
+
+
+803ff
+
+AXI Priority control for write port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port
+
+0XF800620C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_dis_rmw_portn
+
+19:19
+
+80000
+
+1
+
+80000
+
+FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.
+
    
+axi_priority_wr_port@0XF800620C
+
+31:0
+
+f03ff
+
+
+
+803ff
+
+AXI Priority control for write port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port
+
+0XF8006210
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_dis_rmw_portn
+
+19:19
+
+80000
+
+1
+
+80000
+
+FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.
+
    
+axi_priority_wr_port@0XF8006210
+
+31:0
+
+f03ff
+
+
+
+803ff
+
+AXI Priority control for write port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_wr_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_wr_port
+
+0XF8006214
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_wr_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_wr_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Write Port.
+
    
+reg_arb_disable_urgent_wr_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Write Port.
+
    
+reg_arb_dis_page_match_wr_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_dis_rmw_portn
+
+19:19
+
+80000
+
+1
+
+80000
+
+FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW.
+
    
+axi_priority_wr_port@0XF8006214
+
+31:0
+
+f03ff
+
+
+
+803ff
+
+AXI Priority control for write port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port
+
+0XF8006218
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port@0XF8006218
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port
+
+0XF800621C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port@0XF800621C
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port
+
+0XF8006220
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port@0XF8006220
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 0.
+
    
+
    
+
    Register ( slcr )axi_priority_rd_port
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+axi_priority_rd_port
+
+0XF8006224
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_arb_pri_rd_portn
+
+9:0
+
+3ff
+
+3ff
+
+3ff
+
+Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1.
+
    
+reg_arb_disable_aging_rd_portn
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable aging for this Read Port.
+
    
+reg_arb_disable_urgent_rd_portn
+
+17:17
+
+20000
+
+0
+
+0
+
+Disable urgent for this Read Port.
+
    
+reg_arb_dis_page_match_rd_portn
+
+18:18
+
+40000
+
+0
+
+0
+
+Disable the page match feature.
+
    
+reg_arb_set_hpr_rd_portn
+
+19:19
+
+80000
+
+0
+
+0
+
+Enable reads to be generated as HPR for this Read Port.
+
    
+axi_priority_rd_port@0XF8006224
+
+31:0
+
+f03ff
+
+
+
+3ff
+
+AXI Priority control for read port 0.
+
    
+
    
+
    Register ( slcr )lpddr_ctrl0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl0
+
+0XF80062A8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_lpddr2
+
+0:0
+
+1
+
+0
+
+0
+
+1=LPDDR2 DRAM device in Use. 0=non-LPDDR2 device in use Present only in designs configured to support LPDDR2.
+
    
+reg_ddrc_per_bank_refresh
+
+1:1
+
+2
+
+0
+
+0
+
+1:Per bank refresh 0:All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported on all LPDDR2 devices. Present only in designs configured to support LPDDR2.
+
    
+reg_ddrc_derate_enable
+
+2:2
+
+4
+
+0
+
+0
+
+0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. Present only in designs configured to support LPDDR2.
+
    
+reg_ddrc_mr4_margin
+
+11:4
+
+ff0
+
+0
+
+0
+
+UNUSED
+
    
+lpddr_ctrl0@0XF80062A8
+
+31:0
+
+ff7
+
+
+
+0
+
+LPDDR2 Control 0 Register
+
    
+
    
+
    Register ( slcr )lpddr_ctrl1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl1
+
+0XF80062AC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_mr4_read_interval
+
+31:0
+
+ffffffff
+
+0
+
+0
+
+Interval between two MR4 reads, USED to derate the timing parameters. Present only in designs configured to support LPDDR2.
+
    
+lpddr_ctrl1@0XF80062AC
+
+31:0
+
+ffffffff
+
+
+
+0
+
+LPDDR2 Control 1 Register
+
    
+
    
+
    Register ( slcr )lpddr_ctrl2
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl2
+
+0XF80062B0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_min_stable_clock_x1
+
+3:0
+
+f
+
+5
+
+5
+
+Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay.
+
    
+reg_ddrc_idle_after_reset_x32
+
+11:4
+
+ff0
+
+12
+
+120
+
+Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles.
+
    
+reg_ddrc_t_mrw
+
+21:12
+
+3ff000
+
+5
+
+5000
+
+Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5.
+
    
+lpddr_ctrl2@0XF80062B0
+
+31:0
+
+3fffff
+
+
+
+5125
+
+LPDDR2 Control 2 Register
+
    
+
    
+
    Register ( slcr )lpddr_ctrl3
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+lpddr_ctrl3
+
+0XF80062B4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_max_auto_init_x1024
+
+7:0
+
+ff
+
+a8
+
+a8
+
+Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us.
+
    
+reg_ddrc_dev_zqinit_x32
+
+17:8
+
+3ff00
+
+12
+
+1200
+
+ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us.
+
    
+lpddr_ctrl3@0XF80062B4
+
+31:0
+
+3ffff
+
+
+
+12a8
+
+LPDDR2 Control 3 Register
+
    
+
    
+
    POLL ON DCI STATUS
    
+
    Register ( slcr )DDRIOB_DCI_STATUS
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_STATUS
+
+0XF8000B74
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DONE
+
+13:13
+
+2000
+
+1
+
+2000
+
+DCI done signal
+
    
+DDRIOB_DCI_STATUS@0XF8000B74
+
+31:0
+
+2000
+
+
+
+2000
+
+tobe
+
    
+
    
+
    UNLOCK DDR
    
+
    Register ( slcr )ddrc_ctrl
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+ddrc_ctrl
+
+0XF8006000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reg_ddrc_soft_rstb
+
+0:0
+
+1
+
+1
+
+1
+
+Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed.
+
    
+reg_ddrc_powerdown_en
+
+1:1
+
+2
+
+0
+
+0
+
+Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation.
+
    
+reg_ddrc_data_bus_width
+
+3:2
+
+c
+
+0
+
+0
+
+DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved
+
    
+reg_ddrc_burst8_refresh
+
+6:4
+
+70
+
+0
+
+0
+
+Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh
+
    
+reg_ddrc_rdwr_idle_gap
+
+13:7
+
+3f80
+
+1
+
+80
+
+When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed.
+
    
+reg_ddrc_dis_rd_bypass
+
+14:14
+
+4000
+
+0
+
+0
+
+Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits.
+
    
+reg_ddrc_dis_act_bypass
+
+15:15
+
+8000
+
+0
+
+0
+
+Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates.
+
    
+reg_ddrc_dis_auto_refresh
+
+16:16
+
+10000
+
+0
+
+0
+
+Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller.
+
    
+ddrc_ctrl@0XF8006000
+
+31:0
+
+1ffff
+
+
+
+81
+
+DDRC Control Register
+
    
+
    
+
    CHECK DDR STATUS
    
+
    Register ( slcr )mode_sts_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+mode_sts_reg
+
+0XF8006054
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+ddrc_reg_operating_mode
+
+2:0
+
+7
+
+1
+
+1
+
+Gives the status of the controller. 0 = DDRC Init 1 = Normal operation 2 = Power-down mode 3 = Self-refresh mode 4 and above = deep power down mode (LPDDR2 only)
+
    
+mode_sts_reg@0XF8006054
+
+31:0
+
+7
+
+
+
+1
+
+tobe
+
    
+
    
+
+
    
+
    ps7_mio_init_data_1_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+GPIOB_CTRL
+
+
+0XF8000B00
+
+32
+
+RW
+
+0x000000
+
+GPIOB control
+
    
+
+DDRIOB_ADDR0
+
+
+0XF8000B40
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Address 0 Configuartion Register
+
    
+
+DDRIOB_ADDR1
+
+
+0XF8000B44
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Address 1 Configuration Register
+
    
+
+DDRIOB_DATA0
+
+
+0XF8000B48
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Data 0 Configuration Register
+
    
+
+DDRIOB_DATA1
+
+
+0XF8000B4C
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Data 1 Configuration Register
+
    
+
+DDRIOB_DIFF0
+
+
+0XF8000B50
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Differential DQS 0 Configuration Register
+
    
+
+DDRIOB_DIFF1
+
+
+0XF8000B54
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Differential DQS 1 Configuration Register
+
    
+
+DDRIOB_CLOCK
+
+
+0XF8000B58
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Differential Clock Configuration Register
+
    
+
+DDRIOB_DRIVE_SLEW_ADDR
+
+
+0XF8000B5C
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Drive Slew Address Register
+
    
+
+DDRIOB_DRIVE_SLEW_DATA
+
+
+0XF8000B60
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Drive Slew Data Register
+
    
+
+DDRIOB_DRIVE_SLEW_DIFF
+
+
+0XF8000B64
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Drive Slew Differential Strobe Register
+
    
+
+DDRIOB_DRIVE_SLEW_CLOCK
+
+
+0XF8000B68
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Drive Slew Clcok Register
+
    
+
+DDRIOB_DDR_CTRL
+
+
+0XF8000B6C
+
+32
+
+RW
+
+0x000000
+
+DDRIOB DDR Control Register
+
    
+
+DDRIOB_DCI_CTRL
+
+
+0XF8000B70
+
+32
+
+RW
+
+0x000000
+
+DDRIOB DCI configuration
+
    
+
+DDRIOB_DCI_CTRL
+
+
+0XF8000B70
+
+32
+
+RW
+
+0x000000
+
+DDRIOB DCI configuration
+
    
+
+DDRIOB_DCI_CTRL
+
+
+0XF8000B70
+
+32
+
+RW
+
+0x000000
+
+DDRIOB DCI configuration
+
    
+
+MIO_PIN_00
+
+
+0XF8000700
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 0
+
    
+
+MIO_PIN_01
+
+
+0XF8000704
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 1
+
    
+
+MIO_PIN_02
+
+
+0XF8000708
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 2
+
    
+
+MIO_PIN_03
+
+
+0XF800070C
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 3
+
    
+
+MIO_PIN_04
+
+
+0XF8000710
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 4
+
    
+
+MIO_PIN_05
+
+
+0XF8000714
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 5
+
    
+
+MIO_PIN_06
+
+
+0XF8000718
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 6
+
    
+
+MIO_PIN_07
+
+
+0XF800071C
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 7
+
    
+
+MIO_PIN_08
+
+
+0XF8000720
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 8
+
    
+
+MIO_PIN_09
+
+
+0XF8000724
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 9
+
    
+
+MIO_PIN_10
+
+
+0XF8000728
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 10
+
    
+
+MIO_PIN_11
+
+
+0XF800072C
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 11
+
    
+
+MIO_PIN_12
+
+
+0XF8000730
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 12
+
    
+
+MIO_PIN_13
+
+
+0XF8000734
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 13
+
    
+
+MIO_PIN_14
+
+
+0XF8000738
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 14
+
    
+
+MIO_PIN_15
+
+
+0XF800073C
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 15
+
    
+
+MIO_PIN_16
+
+
+0XF8000740
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 16
+
    
+
+MIO_PIN_17
+
+
+0XF8000744
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 17
+
    
+
+MIO_PIN_18
+
+
+0XF8000748
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 18
+
    
+
+MIO_PIN_19
+
+
+0XF800074C
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 19
+
    
+
+MIO_PIN_20
+
+
+0XF8000750
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 20
+
    
+
+MIO_PIN_21
+
+
+0XF8000754
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 21
+
    
+
+MIO_PIN_22
+
+
+0XF8000758
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 22
+
    
+
+MIO_PIN_23
+
+
+0XF800075C
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 23
+
    
+
+MIO_PIN_24
+
+
+0XF8000760
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 24
+
    
+
+MIO_PIN_25
+
+
+0XF8000764
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 25
+
    
+
+MIO_PIN_26
+
+
+0XF8000768
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 26
+
    
+
+MIO_PIN_27
+
+
+0XF800076C
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 27
+
    
+
+MIO_PIN_28
+
+
+0XF8000770
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 28
+
    
+
+MIO_PIN_29
+
+
+0XF8000774
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 29
+
    
+
+MIO_PIN_30
+
+
+0XF8000778
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 30
+
    
+
+MIO_PIN_31
+
+
+0XF800077C
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 31
+
    
+
+MIO_PIN_32
+
+
+0XF8000780
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 32
+
    
+
+MIO_PIN_33
+
+
+0XF8000784
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 33
+
    
+
+MIO_PIN_34
+
+
+0XF8000788
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 34
+
    
+
+MIO_PIN_35
+
+
+0XF800078C
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 35
+
    
+
+MIO_PIN_36
+
+
+0XF8000790
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 36
+
    
+
+MIO_PIN_37
+
+
+0XF8000794
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 37
+
    
+
+MIO_PIN_38
+
+
+0XF8000798
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 38
+
    
+
+MIO_PIN_39
+
+
+0XF800079C
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 39
+
    
+
+MIO_PIN_40
+
+
+0XF80007A0
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 40
+
    
+
+MIO_PIN_41
+
+
+0XF80007A4
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 41
+
    
+
+MIO_PIN_42
+
+
+0XF80007A8
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 42
+
    
+
+MIO_PIN_43
+
+
+0XF80007AC
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 43
+
    
+
+MIO_PIN_44
+
+
+0XF80007B0
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 44
+
    
+
+MIO_PIN_45
+
+
+0XF80007B4
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 45
+
    
+
+MIO_PIN_46
+
+
+0XF80007B8
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 46
+
    
+
+MIO_PIN_47
+
+
+0XF80007BC
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 47
+
    
+
+MIO_PIN_48
+
+
+0XF80007C0
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 48
+
    
+
+MIO_PIN_49
+
+
+0XF80007C4
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 49
+
    
+
+MIO_PIN_50
+
+
+0XF80007C8
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 50
+
    
+
+MIO_PIN_51
+
+
+0XF80007CC
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 51
+
    
+
+MIO_PIN_52
+
+
+0XF80007D0
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 52
+
    
+
+MIO_PIN_53
+
+
+0XF80007D4
+
+32
+
+RW
+
+0x000000
+
+MIO Control for Pin 53
+
    
+
+SD0_WP_CD_SEL
+
+
+0XF8000830
+
+32
+
+RW
+
+0x000000
+
+SDIO 0 WP CD select register
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_mio_init_data_1_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    OCM REMAPPING
    
+
    Register ( slcr )GPIOB_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+GPIOB_CTRL
+
+0XF8000B00
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+VREF_EN
+
+0:0
+
+1
+
+1
+
+1
+
+Enables VREF internal generator
+
    
+VREF_PULLUP_EN
+
+1:1
+
+2
+
+0
+
+0
+
+Enables internal pullup. 0 - no pullup. 1 - pullup.
+
    
+CLK_PULLUP_EN
+
+8:8
+
+100
+
+0
+
+0
+
+Enables internal pullup. 0 - no pullup. 1 - pullup.
+
    
+SRSTN_PULLUP_EN
+
+9:9
+
+200
+
+0
+
+0
+
+Enables internal pullup. 0 - no pullup. 1 - pullup.
+
    
+GPIOB_CTRL@0XF8000B00
+
+31:0
+
+303
+
+
+
+1
+
+GPIOB control
+
    
+
    
+
    DDRIOB SETTINGS
    
+
    Register ( slcr )DDRIOB_ADDR0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_ADDR0
+
+0XF8000B40
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+0
+
+0
+
+Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+0
+
+0
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+0
+
+0
+
+DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0 - no pullup 1 - pullup enabled
+
    
+DDRIOB_ADDR0@0XF8000B40
+
+31:0
+
+fff
+
+
+
+600
+
+DDRIOB Address 0 Configuartion Register
+
    
+
    
+
    Register ( slcr )DDRIOB_ADDR1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_ADDR1
+
+0XF8000B44
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+0
+
+0
+
+Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+0
+
+0
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+0
+
+0
+
+DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0 - no pullup 1 - pullup enabled
+
    
+DDRIOB_ADDR1@0XF8000B44
+
+31:0
+
+fff
+
+
+
+600
+
+DDRIOB Address 1 Configuration Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DATA0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA0
+
+0XF8000B48
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+1
+
+2
+
+Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0 - no pullup 1 - pullup enabled
+
    
+DDRIOB_DATA0@0XF8000B48
+
+31:0
+
+fff
+
+
+
+672
+
+DDRIOB Data 0 Configuration Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DATA1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA1
+
+0XF8000B4C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+1
+
+2
+
+Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0 - no pullup 1 - pullup enabled
+
    
+DDRIOB_DATA1@0XF8000B4C
+
+31:0
+
+fff
+
+
+
+672
+
+DDRIOB Data 1 Configuration Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF0
+
+0XF8000B50
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+2
+
+4
+
+Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0 - no pullup 1 - pullup enabled
+
    
+DDRIOB_DIFF0@0XF8000B50
+
+31:0
+
+fff
+
+
+
+674
+
+DDRIOB Differential DQS 0 Configuration Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF1
+
+0XF8000B54
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+2
+
+4
+
+Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+1
+
+10
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+3
+
+60
+
+DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0 - no pullup 1 - pullup enabled
+
    
+DDRIOB_DIFF1@0XF8000B54
+
+31:0
+
+fff
+
+
+
+674
+
+DDRIOB Differential DQS 1 Configuration Register
+
    
+
    
+
    Register ( slcr )DDRIOB_CLOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_CLOCK
+
+0XF8000B58
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+INP_POWER
+
+0:0
+
+1
+
+0
+
+0
+
+Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode.
+
    
+INP_TYPE
+
+2:1
+
+6
+
+0
+
+0
+
+Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever.
+
    
+DCI_UPDATE
+
+3:3
+
+8
+
+0
+
+0
+
+DCI Update Enabled 0 - disabled 1 - enabled
+
    
+TERM_EN
+
+4:4
+
+10
+
+0
+
+0
+
+Tri State Termination Enabled 0 - disabled 1 - enabled
+
    
+DCR_TYPE
+
+6:5
+
+60
+
+0
+
+0
+
+DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI)
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+0
+
+0
+
+Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+0
+
+0
+
+Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination
+
    
+OUTPUT_EN
+
+10:9
+
+600
+
+3
+
+600
+
+Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf
+
    
+PULLUP_EN
+
+11:11
+
+800
+
+0
+
+0
+
+enables pullup on output 0 - no pullup 1 - pullup enabled
+
    
+DDRIOB_CLOCK@0XF8000B58
+
+31:0
+
+fff
+
+
+
+600
+
+DDRIOB Differential Clock Configuration Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_ADDR
+
+0XF8000B5C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+Programs the DDRIO drive strength for the P devices
+
    
+DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+Programs the DDRIO drive strength for the N devices
+
    
+SLEW_P
+
+18:14
+
+7c000
+
+3
+
+c000
+
+Programs the DDRIO slew rate for the P devices
+
    
+SLEW_N
+
+23:19
+
+f80000
+
+3
+
+180000
+
+Programs the DDRIO slew rate for the N devices
+
    
+GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Test Control 000 - Normal Operation 001 : 111 - Test Mode
+
    
+RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Program the rterm
+
    
+DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C
+
+31:0
+
+ffffffff
+
+
+
+18c61c
+
+DDRIOB Drive Slew Address Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_DATA
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_DATA
+
+0XF8000B60
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+Programs the DDRIO drive strength for the P devices
+
    
+DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+Programs the DDRIO drive strength for the N devices
+
    
+SLEW_P
+
+18:14
+
+7c000
+
+6
+
+18000
+
+Programs the DDRIO slew rate for the P devices
+
    
+SLEW_N
+
+23:19
+
+f80000
+
+1f
+
+f80000
+
+Programs the DDRIO slew rate for the N devices
+
    
+GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Test Control 000 - Normal Operation 001 : 111 - Test Mode
+
    
+RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Program the rterm
+
    
+DDRIOB_DRIVE_SLEW_DATA@0XF8000B60
+
+31:0
+
+ffffffff
+
+
+
+f9861c
+
+DDRIOB Drive Slew Data Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_DIFF
+
+0XF8000B64
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+Programs the DDRIO drive strength for the P devices
+
    
+DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+Programs the DDRIO drive strength for the N devices
+
    
+SLEW_P
+
+18:14
+
+7c000
+
+6
+
+18000
+
+Programs the DDRIO slew rate for the P devices
+
    
+SLEW_N
+
+23:19
+
+f80000
+
+1f
+
+f80000
+
+Programs the DDRIO slew rate for the N devices
+
    
+GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Test Control 000 - Normal Operation 001 : 111 - Test Mode
+
    
+RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Program the rterm
+
    
+DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64
+
+31:0
+
+ffffffff
+
+
+
+f9861c
+
+DDRIOB Drive Slew Differential Strobe Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DRIVE_SLEW_CLOCK
+
+0XF8000B68
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DRIVE_P
+
+6:0
+
+7f
+
+1c
+
+1c
+
+Programs the DDRIO drive strength for the P devices
+
    
+DRIVE_N
+
+13:7
+
+3f80
+
+c
+
+600
+
+Programs the DDRIO drive strength for the N devices
+
    
+SLEW_P
+
+18:14
+
+7c000
+
+6
+
+18000
+
+Programs the DDRIO slew rate for the P devices
+
    
+SLEW_N
+
+23:19
+
+f80000
+
+1f
+
+f80000
+
+Programs the DDRIO slew rate for the N devices
+
    
+GTL
+
+26:24
+
+7000000
+
+0
+
+0
+
+Test Control 000 - Normal Operation 001 : 111 - Test Mode
+
    
+RTERM
+
+31:27
+
+f8000000
+
+0
+
+0
+
+Program the rterm
+
    
+DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68
+
+31:0
+
+ffffffff
+
+
+
+f9861c
+
+DDRIOB Drive Slew Clcok Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DDR_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DDR_CTRL
+
+0XF8000B6C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+VREF_INT_EN
+
+0:0
+
+1
+
+1
+
+1
+
+Enables VREF internal generator
+
    
+VREF_SEL
+
+4:1
+
+1e
+
+4
+
+8
+
+Specifies DDR IOB Vref generator output 0001 - VREF = 0.6V for LPDDR2 with 1.2V IO 0010 - VREF = 0.675V for LPDDR3 1.35 V IO 0100 - VREF = 0.75V for DDR3 with 1.5V IO 1000 - VREF = 0.90V for DDR2 with 1.8V IO
+
    
+VREF_EXT_EN
+
+6:5
+
+60
+
+0
+
+0
+
+Enables External VREF input X0 - Disable External VREF for lower 16 bits X1 - Enable External VREF for lower 16 bits 0X - Disable External VREF for upper 16 bits 1X - Enable External VREF for upper 16 bits
+
    
+VREF_PULLUP_EN
+
+8:7
+
+180
+
+0
+
+0
+
+Enables VREF pull-up resistors X0 - Disable VREF pull-up for lower 16 bits X1 - Enable VREF pull-up for lower 16 bits 0X - Disable VREF pull-up for upper 16 bits 1X - Enable VREF pull-up for upper 16 bits
+
    
+REFIO_EN
+
+9:9
+
+200
+
+1
+
+200
+
+Enables VRP,VRN 0 - VRP/VRN not used 1 - VRP/VRN used as refio
+
    
+REFIO_PULLUP_EN
+
+12:12
+
+1000
+
+0
+
+0
+
+Enables VRP,VRN pull-up resistors 0 -no pull-up 1 - enable pull-up resistors
+
    
+DRST_B_PULLUP_EN
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors
+
    
+CKE_PULLUP_EN
+
+14:14
+
+4000
+
+0
+
+0
+
+Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors
+
    
+DDRIOB_DDR_CTRL@0XF8000B6C
+
+31:0
+
+73ff
+
+
+
+209
+
+DDRIOB DDR Control Register
+
    
+
    
+
    ASSERT RESET
    
+
    Register ( slcr )DDRIOB_DCI_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_CTRL
+
+0XF8000B70
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+RESET
+
+0:0
+
+1
+
+1
+
+1
+
+At least toggle once to initialise flops in DCI system
+
    
+VRN_OUT
+
+5:5
+
+20
+
+1
+
+20
+
+VRN output value
+
    
+DDRIOB_DCI_CTRL@0XF8000B70
+
+31:0
+
+21
+
+
+
+21
+
+DDRIOB DCI configuration
+
    
+
    
+
    DEASSERT RESET
    
+
    Register ( slcr )DDRIOB_DCI_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_CTRL
+
+0XF8000B70
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+RESET
+
+0:0
+
+1
+
+0
+
+0
+
+At least toggle once to initialise flops in DCI system
+
    
+VRN_OUT
+
+5:5
+
+20
+
+1
+
+20
+
+VRN output value
+
    
+DDRIOB_DCI_CTRL@0XF8000B70
+
+31:0
+
+21
+
+
+
+20
+
+DDRIOB DCI configuration
+
    
+
    
+
    Register ( slcr )DDRIOB_DCI_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DCI_CTRL
+
+0XF8000B70
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+RESET
+
+0:0
+
+1
+
+1
+
+1
+
+At least toggle once to initialise flops in DCI system
+
    
+ENABLE
+
+1:1
+
+2
+
+1
+
+2
+
+1 if any iob's use a terminate type, or if dci test block used
+
    
+VRP_TRI
+
+2:2
+
+4
+
+0
+
+0
+
+VRP tristate value
+
    
+VRN_TRI
+
+3:3
+
+8
+
+0
+
+0
+
+VRN tristate value
+
    
+VRP_OUT
+
+4:4
+
+10
+
+0
+
+0
+
+VRP output value
+
    
+VRN_OUT
+
+5:5
+
+20
+
+1
+
+20
+
+VRN output value
+
    
+NREF_OPT1
+
+7:6
+
+c0
+
+0
+
+0
+
+Reserved
+
    
+NREF_OPT2
+
+10:8
+
+700
+
+0
+
+0
+
+Reserved
+
    
+NREF_OPT4
+
+13:11
+
+3800
+
+1
+
+800
+
+Reserved
+
    
+PREF_OPT1
+
+16:14
+
+1c000
+
+0
+
+0
+
+Reserved
+
    
+PREF_OPT2
+
+19:17
+
+e0000
+
+0
+
+0
+
+Reserved
+
    
+UPDATE_CONTROL
+
+20:20
+
+100000
+
+0
+
+0
+
+DCI Update
+
    
+INIT_COMPLETE
+
+21:21
+
+200000
+
+0
+
+0
+
+test Internal to IO bank
+
    
+TST_CLK
+
+22:22
+
+400000
+
+0
+
+0
+
+Emulate DCI clock
+
    
+TST_HLN
+
+23:23
+
+800000
+
+0
+
+0
+
+Emulate comparator output (VRN)
+
    
+TST_HLP
+
+24:24
+
+1000000
+
+0
+
+0
+
+Emulate comparator output (VRP)
+
    
+TST_RST
+
+25:25
+
+2000000
+
+0
+
+0
+
+Emulate Reset
+
    
+INT_DCI_EN
+
+26:26
+
+4000000
+
+0
+
+0
+
+Need explanation here
+
    
+DDRIOB_DCI_CTRL@0XF8000B70
+
+31:0
+
+7ffffff
+
+
+
+823
+
+DDRIOB DCI configuration
+
    
+
    
+
    MIO PROGRAMMING
    
+
    Register ( slcr )MIO_PIN_00
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_00
+
+0XF8000700
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Tri-state enable, active high.
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_00@0XF8000700
+
+31:0
+
+3f01
+
+
+
+1201
+
+MIO Control for Pin 0
+
    
+
    
+
    Register ( slcr )MIO_PIN_01
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_01
+
+0XF8000704
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_01@0XF8000704
+
+31:0
+
+3fff
+
+
+
+1202
+
+MIO Control for Pin 1
+
    
+
    
+
    Register ( slcr )MIO_PIN_02
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_02
+
+0XF8000708
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_02@0XF8000708
+
+31:0
+
+3fff
+
+
+
+202
+
+MIO Control for Pin 2
+
    
+
    
+
    Register ( slcr )MIO_PIN_03
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_03
+
+0XF800070C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_03@0XF800070C
+
+31:0
+
+3fff
+
+
+
+202
+
+MIO Control for Pin 3
+
    
+
    
+
    Register ( slcr )MIO_PIN_04
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_04
+
+0XF8000710
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_04@0XF8000710
+
+31:0
+
+3fff
+
+
+
+202
+
+MIO Control for Pin 4
+
    
+
    
+
    Register ( slcr )MIO_PIN_05
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_05
+
+0XF8000714
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_05@0XF8000714
+
+31:0
+
+3fff
+
+
+
+202
+
+MIO Control for Pin 5
+
    
+
    
+
    Register ( slcr )MIO_PIN_06
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_06
+
+0XF8000718
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_06@0XF8000718
+
+31:0
+
+3fff
+
+
+
+202
+
+MIO Control for Pin 6
+
    
+
    
+
    Register ( slcr )MIO_PIN_07
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_07
+
+0XF800071C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[13]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_oe_b- (SRAM Output enable) 2= nand, Output, smc_nand_cle- (NAND Command Latch Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[0]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_07@0XF800071C
+
+31:0
+
+3fff
+
+
+
+200
+
+MIO Control for Pin 7
+
    
+
    
+
    Register ( slcr )MIO_PIN_08
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_08
+
+0XF8000720
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1]
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_08@0XF8000720
+
+31:0
+
+3fff
+
+
+
+202
+
+MIO Control for Pin 8
+
    
+
    
+
    Register ( slcr )MIO_PIN_09
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_09
+
+0XF8000724
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[15]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[6]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[6]- (SRAM Data) 2= nand, Input, smc_nand_data_in[4]- (NAND Data Bus) = nand, Output, smc_nand_data_out[4]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_09@0XF8000724
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 9
+
    
+
    
+
    Register ( slcr )MIO_PIN_10
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_10
+
+0XF8000728
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[7]- (SRAM Data) 2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus) = nand, Output, smc_nand_data_out[5]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_10@0XF8000728
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 10
+
    
+
    
+
    Register ( slcr )MIO_PIN_11
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_11
+
+0XF800072C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_11@0XF800072C
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 11
+
    
+
    
+
    Register ( slcr )MIO_PIN_12
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_12
+
+0XF8000730
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper Databus)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_wait- (SRAM Wait State indicator) 2= nand, Input, smc_nand_data_in[7]- (NAND Data Bus) = nand, Output, smc_nand_data_out[7]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_12@0XF8000730
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 12
+
    
+
    
+
    Register ( slcr )MIO_PIN_13
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_13
+
+0XF8000734
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper Databus)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[5]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[5]- (SRAM Data) 2= nand, Input, smc_nand_data_in[3]- (NAND Data Bus) = nand, Output, smc_nand_data_out[3]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_13@0XF8000734
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 13
+
    
+
    
+
    Register ( slcr )MIO_PIN_14
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_14
+
+0XF8000738
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_14@0XF8000738
+
+31:0
+
+3fff
+
+
+
+1200
+
+MIO Control for Pin 14
+
    
+
    
+
    Register ( slcr )MIO_PIN_15
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_15
+
+0XF800073C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Tri-state enable, active high.
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_15@0XF800073C
+
+31:0
+
+3f01
+
+
+
+1201
+
+MIO Control for Pin 15
+
    
+
    
+
    Register ( slcr )MIO_PIN_16
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_16
+
+0XF8000740
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[4]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[1]- (SRAM Address) 2= nand, Input, smc_nand_data_in[8]- (NAND Data Bus) = nand, Output, smc_nand_data_out[8]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+1
+
+2000
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_16@0XF8000740
+
+31:0
+
+3fff
+
+
+
+2802
+
+MIO Control for Pin 16
+
    
+
    
+
    Register ( slcr )MIO_PIN_17
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_17
+
+0XF8000744
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[5]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[2]- (SRAM Address) 2= nand, Input, smc_nand_data_in[9]- (NAND Data Bus) = nand, Output, smc_nand_data_out[9]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+1
+
+2000
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_17@0XF8000744
+
+31:0
+
+3fff
+
+
+
+2802
+
+MIO Control for Pin 17
+
    
+
    
+
    Register ( slcr )MIO_PIN_18
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_18
+
+0XF8000748
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[6]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[3]- (SRAM Address) 2= nand, Input, smc_nand_data_in[10]- (NAND Data Bus) = nand, Output, smc_nand_data_out[10]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+1
+
+2000
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_18@0XF8000748
+
+31:0
+
+3fff
+
+
+
+2802
+
+MIO Control for Pin 18
+
    
+
    
+
    Register ( slcr )MIO_PIN_19
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_19
+
+0XF800074C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[7]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[4]- (SRAM Address) 2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus) = nand, Output, smc_nand_data_out[11]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+1
+
+2000
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_19@0XF800074C
+
+31:0
+
+3fff
+
+
+
+2802
+
+MIO Control for Pin 19
+
    
+
    
+
    Register ( slcr )MIO_PIN_20
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_20
+
+0XF8000750
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[5]- (SRAM Address) 2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus) = nand, Output, smc_nand_data_out[12]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+1
+
+2000
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_20@0XF8000750
+
+31:0
+
+3fff
+
+
+
+2802
+
+MIO Control for Pin 20
+
    
+
    
+
    Register ( slcr )MIO_PIN_21
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_21
+
+0XF8000754
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[6]- (SRAM Address) 2= nand, Input, smc_nand_data_in[13]- (NAND Data Bus) = nand, Output, smc_nand_data_out[13]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+1
+
+2000
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_21@0XF8000754
+
+31:0
+
+3fff
+
+
+
+2802
+
+MIO Control for Pin 21
+
    
+
    
+
    Register ( slcr )MIO_PIN_22
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_22
+
+0XF8000758
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[7]- (SRAM Address) 2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus) = nand, Output, smc_nand_data_out[14]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_22@0XF8000758
+
+31:0
+
+3fff
+
+
+
+803
+
+MIO Control for Pin 22
+
    
+
    
+
    Register ( slcr )MIO_PIN_23
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_23
+
+0XF800075C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[8]- (SRAM Address) 2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus) = nand, Output, smc_nand_data_out[15]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_23@0XF800075C
+
+31:0
+
+3fff
+
+
+
+803
+
+MIO Control for Pin 23
+
    
+
    
+
    Register ( slcr )MIO_PIN_24
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_24
+
+0XF8000760
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[9]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_24@0XF8000760
+
+31:0
+
+3fff
+
+
+
+803
+
+MIO Control for Pin 24
+
    
+
    
+
    Register ( slcr )MIO_PIN_25
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_25
+
+0XF8000764
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[10]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_25@0XF8000764
+
+31:0
+
+3fff
+
+
+
+803
+
+MIO Control for Pin 25
+
    
+
    
+
    Register ( slcr )MIO_PIN_26
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_26
+
+0XF8000768
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[11]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_26@0XF8000768
+
+31:0
+
+3fff
+
+
+
+803
+
+MIO Control for Pin 26
+
    
+
    
+
    Register ( slcr )MIO_PIN_27
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_27
+
+0XF800076C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+1
+
+2
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control )
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[12]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+4
+
+800
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_27@0XF800076C
+
+31:0
+
+3fff
+
+
+
+803
+
+MIO Control for Pin 27
+
    
+
    
+
    Register ( slcr )MIO_PIN_28
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_28
+
+0XF8000770
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[13]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[28]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[28]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_28@0XF8000770
+
+31:0
+
+3fff
+
+
+
+204
+
+MIO Control for Pin 28
+
    
+
    
+
    Register ( slcr )MIO_PIN_29
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_29
+
+0XF8000774
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[14]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[29]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[29]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_29@0XF8000774
+
+31:0
+
+3fff
+
+
+
+205
+
+MIO Control for Pin 29
+
    
+
    
+
    Register ( slcr )MIO_PIN_30
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_30
+
+0XF8000778
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[15]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[30]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[30]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_30@0XF8000778
+
+31:0
+
+3fff
+
+
+
+204
+
+MIO Control for Pin 30
+
    
+
    
+
    Register ( slcr )MIO_PIN_31
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_31
+
+0XF800077C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[16]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[31]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[31]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_31@0XF800077C
+
+31:0
+
+3fff
+
+
+
+205
+
+MIO Control for Pin 31
+
    
+
    
+
    Register ( slcr )MIO_PIN_32
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_32
+
+0XF8000780
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[17]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_32@0XF8000780
+
+31:0
+
+3fff
+
+
+
+204
+
+MIO Control for Pin 32
+
    
+
    
+
    Register ( slcr )MIO_PIN_33
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_33
+
+0XF8000784
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[18]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_33@0XF8000784
+
+31:0
+
+3fff
+
+
+
+204
+
+MIO Control for Pin 33
+
    
+
    
+
    Register ( slcr )MIO_PIN_34
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_34
+
+0XF8000788
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[19]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_34@0XF8000788
+
+31:0
+
+3fff
+
+
+
+204
+
+MIO Control for Pin 34
+
    
+
    
+
    Register ( slcr )MIO_PIN_35
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_35
+
+0XF800078C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[20]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_35@0XF800078C
+
+31:0
+
+3fff
+
+
+
+204
+
+MIO Control for Pin 35
+
    
+
    
+
    Register ( slcr )MIO_PIN_36
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_36
+
+0XF8000790
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_xcvr_clk_in- (ULPI clock) 1= usb0, Output, usb0_xcvr_clk_out- (ULPI clock)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[21]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_36@0XF8000790
+
+31:0
+
+3fff
+
+
+
+205
+
+MIO Control for Pin 36
+
    
+
    
+
    Register ( slcr )MIO_PIN_37
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_37
+
+0XF8000794
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[22]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_37@0XF8000794
+
+31:0
+
+3fff
+
+
+
+204
+
+MIO Control for Pin 37
+
    
+
    
+
    Register ( slcr )MIO_PIN_38
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_38
+
+0XF8000798
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[23]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_38@0XF8000798
+
+31:0
+
+3fff
+
+
+
+204
+
+MIO Control for Pin 38
+
    
+
    
+
    Register ( slcr )MIO_PIN_39
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_39
+
+0XF800079C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )
+
    
+L1_SEL
+
+2:2
+
+4
+
+1
+
+4
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[24]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+0
+
+0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_39@0XF800079C
+
+31:0
+
+3fff
+
+
+
+204
+
+MIO Control for Pin 39
+
    
+
    
+
    Register ( slcr )MIO_PIN_40
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_40
+
+0XF80007A0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_40@0XF80007A0
+
+31:0
+
+3fff
+
+
+
+280
+
+MIO Control for Pin 40
+
    
+
    
+
    Register ( slcr )MIO_PIN_41
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_41
+
+0XF80007A4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_41@0XF80007A4
+
+31:0
+
+3fff
+
+
+
+280
+
+MIO Control for Pin 41
+
    
+
    
+
    Register ( slcr )MIO_PIN_42
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_42
+
+0XF80007A8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_42@0XF80007A8
+
+31:0
+
+3fff
+
+
+
+280
+
+MIO Control for Pin 42
+
    
+
    
+
    Register ( slcr )MIO_PIN_43
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_43
+
+0XF80007AC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_43@0XF80007AC
+
+31:0
+
+3fff
+
+
+
+280
+
+MIO Control for Pin 43
+
    
+
    
+
    Register ( slcr )MIO_PIN_44
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_44
+
+0XF80007B0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_44@0XF80007B0
+
+31:0
+
+3fff
+
+
+
+280
+
+MIO Control for Pin 44
+
    
+
    
+
    Register ( slcr )MIO_PIN_45
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_45
+
+0XF80007B4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_45@0XF80007B4
+
+31:0
+
+3fff
+
+
+
+280
+
+MIO Control for Pin 45
+
    
+
    
+
    Register ( slcr )MIO_PIN_46
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_46
+
+0XF80007B8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+1
+
+20
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_46@0XF80007B8
+
+31:0
+
+3fff
+
+
+
+1221
+
+MIO Control for Pin 46
+
    
+
    
+
    Register ( slcr )MIO_PIN_47
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_47
+
+0XF80007BC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+1
+
+20
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_47@0XF80007BC
+
+31:0
+
+3fff
+
+
+
+1220
+
+MIO Control for Pin 47
+
    
+
    
+
    Register ( slcr )MIO_PIN_48
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_48
+
+0XF80007C0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+7
+
+e0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_48@0XF80007C0
+
+31:0
+
+3fff
+
+
+
+2e0
+
+MIO Control for Pin 48
+
    
+
    
+
    Register ( slcr )MIO_PIN_49
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_49
+
+0XF80007C4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+1
+
+1
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+7
+
+e0
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_49@0XF80007C4
+
+31:0
+
+3fff
+
+
+
+2e1
+
+MIO Control for Pin 49
+
    
+
    
+
    Register ( slcr )MIO_PIN_50
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_50
+
+0XF80007C8
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+2
+
+40
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_50@0XF80007C8
+
+31:0
+
+3fff
+
+
+
+1240
+
+MIO Control for Pin 50
+
    
+
    
+
    Register ( slcr )MIO_PIN_51
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_51
+
+0XF80007CC
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data bus)
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+2
+
+40
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+1
+
+1000
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_51@0XF80007CC
+
+31:0
+
+3fff
+
+
+
+1240
+
+MIO Control for Pin 51
+
    
+
    
+
    Register ( slcr )MIO_PIN_52
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_52
+
+0XF80007D0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_52@0XF80007D0
+
+31:0
+
+3fff
+
+
+
+280
+
+MIO Control for Pin 52
+
    
+
    
+
    Register ( slcr )MIO_PIN_53
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MIO_PIN_53
+
+0XF80007D4
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+TRI_ENABLE
+
+0:0
+
+1
+
+0
+
+0
+
+Tri-state enable, active high.
+
    
+L0_SEL
+
+1:1
+
+2
+
+0
+
+0
+
+Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+
    
+L1_SEL
+
+2:2
+
+4
+
+0
+
+0
+
+Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+
    
+L2_SEL
+
+4:3
+
+18
+
+0
+
+0
+
+Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power)
+
    
+L3_SEL
+
+7:5
+
+e0
+
+4
+
+80
+
+Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input)
+
    
+Speed
+
+8:8
+
+100
+
+0
+
+0
+
+Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS
+
    
+IO_Type
+
+11:9
+
+e00
+
+1
+
+200
+
+Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33
+
    
+PULLUP
+
+12:12
+
+1000
+
+0
+
+0
+
+Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled
+
    
+DisableRcvr
+
+13:13
+
+2000
+
+0
+
+0
+
+Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled
+
    
+MIO_PIN_53@0XF80007D4
+
+31:0
+
+3fff
+
+
+
+280
+
+MIO Control for Pin 53
+
    
+
    
+
    Register ( slcr )SD0_WP_CD_SEL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SD0_WP_CD_SEL
+
+0XF8000830
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+SDIO0_WP_SEL
+
+5:0
+
+3f
+
+f
+
+f
+
+SDIO0 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source
+
    
+SDIO0_CD_SEL
+
+21:16
+
+3f0000
+
+0
+
+0
+
+SDIO0 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source
+
    
+SD0_WP_CD_SEL@0XF8000830
+
+31:0
+
+3f003f
+
+
+
+f
+
+SDIO 0 WP CD select register
+
    
+
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_peripherals_init_data_1_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+DDRIOB_DATA0
+
+
+0XF8000B48
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Data 0 Configuration Register
+
    
+
+DDRIOB_DATA1
+
+
+0XF8000B4C
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Data 1 Configuration Register
+
    
+
+DDRIOB_DIFF0
+
+
+0XF8000B50
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Differential DQS 0 Configuration Register
+
    
+
+DDRIOB_DIFF1
+
+
+0XF8000B54
+
+32
+
+RW
+
+0x000000
+
+DDRIOB Differential DQS 1 Configuration Register
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
+Baud_rate_divider_reg0
+
+
+0XE0001034
+
+32
+
+RW
+
+0x000000
+
+baud rate divider register
+
    
+
+Baud_rate_gen_reg0
+
+
+0XE0001018
+
+32
+
+RW
+
+0x000000
+
+Baud rate divider register
+
    
+
+Control_reg0
+
+
+0XE0001000
+
+32
+
+RW
+
+0x000000
+
+UART Control register
+
    
+
+mode_reg0
+
+
+0XE0001004
+
+32
+
+RW
+
+0x000000
+
+UART Mode register
+
    
+
+Config_reg
+
+
+0XE000D000
+
+32
+
+RW
+
+0x000000
+
+SPI configuration register
+
    
+
+CTRL
+
+
+0XF8007000
+
+32
+
+RW
+
+0x000000
+
+Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.
+
    
+
+DIRM_0
+
+
+0XE000A204
+
+32
+
+RW
+
+0x000000
+
+Direction mode configuration register: Configures bank 0 for direction mode, either input or output
+
    
+
+MASK_DATA_0_LSW
+
+
+0XE000A000
+
+32
+
+RW
+
+0x000000
+
+Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins
+
    
+
+OEN_0
+
+
+0XE000A208
+
+32
+
+RW
+
+0x000000
+
+Output enable register: Configures the output enables of bank 0
+
    
+
+MASK_DATA_0_LSW
+
+
+0XE000A000
+
+32
+
+RW
+
+0x000000
+
+Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins
+
    
+
+MASK_DATA_0_LSW
+
+
+0XE000A000
+
+32
+
+RW
+
+0x000000
+
+Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins
+
    
+
+DIRM_0
+
+
+0XE000A204
+
+32
+
+RW
+
+0x000000
+
+Direction mode configuration register: Configures bank 0 for direction mode, either input or output
+
    
+
+MASK_DATA_0_LSW
+
+
+0XE000A000
+
+32
+
+RW
+
+0x000000
+
+Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins
+
    
+
+OEN_0
+
+
+0XE000A208
+
+32
+
+RW
+
+0x000000
+
+Output enable register: Configures the output enables of bank 0
+
    
+
+MASK_DATA_0_LSW
+
+
+0XE000A000
+
+32
+
+RW
+
+0x000000
+
+Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins
+
    
+
+MASK_DATA_0_LSW
+
+
+0XE000A000
+
+32
+
+RW
+
+0x000000
+
+Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins
+
    
+
+DIRM_0
+
+
+0XE000A204
+
+32
+
+RW
+
+0x000000
+
+Direction mode configuration register: Configures bank 0 for direction mode, either input or output
+
    
+
+MASK_DATA_0_LSW
+
+
+0XE000A000
+
+32
+
+RW
+
+0x000000
+
+Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins
+
    
+
+OEN_0
+
+
+0XE000A208
+
+32
+
+RW
+
+0x000000
+
+Output enable register: Configures the output enables of bank 0
+
    
+
+MASK_DATA_0_LSW
+
+
+0XE000A000
+
+32
+
+RW
+
+0x000000
+
+Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins
+
    
+
+MASK_DATA_0_LSW
+
+
+0XE000A000
+
+32
+
+RW
+
+0x000000
+
+Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins
+
    
+
    
+
    ps7_peripherals_init_data_1_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    DDR TERM/IBUF_DISABLE_MODE SETTINGS
    
+
    Register ( slcr )DDRIOB_DATA0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA0
+
+0XF8000B48
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination
+
    
+DDRIOB_DATA0@0XF8000B48
+
+31:0
+
+180
+
+
+
+180
+
+DDRIOB Data 0 Configuration Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DATA1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DATA1
+
+0XF8000B4C
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination
+
    
+DDRIOB_DATA1@0XF8000B4C
+
+31:0
+
+180
+
+
+
+180
+
+DDRIOB Data 1 Configuration Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF0
+
+0XF8000B50
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination
+
    
+DDRIOB_DIFF0@0XF8000B50
+
+31:0
+
+180
+
+
+
+180
+
+DDRIOB Differential DQS 0 Configuration Register
+
    
+
    
+
    Register ( slcr )DDRIOB_DIFF1
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DDRIOB_DIFF1
+
+0XF8000B54
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IBUF_DISABLE_MODE
+
+7:7
+
+80
+
+1
+
+80
+
+Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable
+
    
+TERM_DISABLE_MODE
+
+8:8
+
+100
+
+1
+
+100
+
+Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination
+
    
+DDRIOB_DIFF1@0XF8000B54
+
+31:0
+
+180
+
+
+
+180
+
+DDRIOB Differential DQS 1 Configuration Register
+
    
+
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
    SRAM/NOR SET OPMODE
    
+
    TRACE CURRENT PORT SIZE
    
+
    UART REGISTERS
    
+
    Register ( slcr )Baud_rate_divider_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Baud_rate_divider_reg0
+
+0XE0001034
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+BDIV
+
+7:0
+
+ff
+
+6
+
+6
+
+Baud rate divider value 0 - 3: ignored 4 - 255: Baud rate
+
    
+Baud_rate_divider_reg0@0XE0001034
+
+31:0
+
+ff
+
+
+
+6
+
+baud rate divider register
+
    
+
    
+
    Register ( slcr )Baud_rate_gen_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Baud_rate_gen_reg0
+
+0XE0001018
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+CD
+
+15:0
+
+ffff
+
+3e
+
+3e
+
+Baud Rate Clock Divisor Value 0 = Disables baud_sample 1 = Clock divisor bypass 2 - 65535 = baud_sample value
+
    
+Baud_rate_gen_reg0@0XE0001018
+
+31:0
+
+ffff
+
+
+
+3e
+
+Baud rate divider register
+
    
+
    
+
    Register ( slcr )Control_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Control_reg0
+
+0XE0001000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+STPBRK
+
+8:8
+
+100
+
+0
+
+0
+
+Stop transmitter break. 1 = stop transmission of the break.
+
    
+STTBRK
+
+7:7
+
+80
+
+0
+
+0
+
+Start transmitter break 1 = start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high.
+
    
+RSTTO
+
+6:6
+
+40
+
+0
+
+0
+
+Restart receiver timeout counter 1 = receiver timeout counter is restarted
+
    
+TXDIS
+
+5:5
+
+20
+
+0
+
+0
+
+Transmit disable. 1, the transmitter is disabled
+
    
+TXEN
+
+4:4
+
+10
+
+1
+
+10
+
+Transmit enable. 1, the transmitter is enabled, provided the TXDIS field is set to 0.
+
    
+RXDIS
+
+3:3
+
+8
+
+0
+
+0
+
+Receive disable. 1= receiver is enabled
+
    
+RXEN
+
+2:2
+
+4
+
+1
+
+4
+
+Receive enable. 1=the receiver logic is enabled, provided RXDIS field is set to 0
+
    
+TXRES
+
+1:1
+
+2
+
+1
+
+2
+
+Software reset for TX data path. 1=the transmitter logic is reset and all pending transmitter data is discarded self clear
+
    
+RXRES
+
+0:0
+
+1
+
+1
+
+1
+
+Software reset for RX data path 1=receiver logic is reset and all pending receiver data is discarded self clear
+
    
+Control_reg0@0XE0001000
+
+31:0
+
+1ff
+
+
+
+17
+
+UART Control register
+
    
+
    
+
    Register ( slcr )mode_reg0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+mode_reg0
+
+0XE0001004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+IRMODE
+
+11:11
+
+800
+
+0
+
+0
+
+Enable IrDA mode 0 : Default UART mode 1 : Enable IrDA mode
+
    
+UCLKEN
+
+10:10
+
+400
+
+0
+
+0
+
+External uart_clk source select 0 : APB clock, pclk 1 : a user-defined clock
+
    
+CHMODE
+
+9:8
+
+300
+
+0
+
+0
+
+Channel mode 00 = normal 01 = automatic cho 10 = local loopback 11 = remote loopback
+
    
+NBSTOP
+
+7:6
+
+c0
+
+0
+
+0
+
+Number of stop bits 00 = 1 stop bit 01 = 1.5 stop bits 10 = 2 stop bits 11 = reserved
+
    
+PAR
+
+5:3
+
+38
+
+4
+
+20
+
+Parity type select. 000 = even parity 001 = odd parity 010 = forced to 0 parity (space) 011 = forced to 1 parity (mark) 1xx = no parity
+
    
+CHRL
+
+2:1
+
+6
+
+0
+
+0
+
+Character length select 11 = 6 bits 10 = 7 bits 01 / 00 = 8 bits
+
    
+CLKS
+
+0:0
+
+1
+
+0
+
+0
+
+clock source select 1 = clock source is uart_clk/8 0 = clock source is uart_clk
+
    
+mode_reg0@0XE0001004
+
+31:0
+
+fff
+
+
+
+20
+
+UART Mode register
+
    
+
    
+
    QSPI REGISTERS
    
+
    Register ( slcr )Config_reg
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+Config_reg
+
+0XE000D000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+Holdb_dr
+
+19:19
+
+80000
+
+1
+
+80000
+
+Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode.
+
    
+Config_reg@0XE000D000
+
+31:0
+
+80000
+
+
+
+80000
+
+SPI configuration register
+
    
+
    
+
    PL POWER ON RESET REGISTERS
    
+
    Register ( slcr )CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+CTRL
+
+0XF8007000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+PCFG_POR_CNT_4K
+
+29:29
+
+20000000
+
+0
+
+0
+
+This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer
+
    
+CTRL@0XF8007000
+
+31:0
+
+20000000
+
+
+
+0
+
+Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004.
+
    
+
    
+
    SMC TIMING CALCULATION REGISTER UPDATE
    
+
    NAND SET CYCLE
    
+
    OPMODE
    
+
    DIRECT COMMAND
    
+
    SRAM/NOR CS0 SET CYCLE
    
+
    DIRECT COMMAND
    
+
    NOR CS0 BASE ADDRESS
    
+
    SRAM/NOR CS1 SET CYCLE
    
+
    DIRECT COMMAND
    
+
    NOR CS1 BASE ADDRESS
    
+
    USB RESET
    
+
    DIR MODE BANK 0
    
+
    Register ( slcr )DIRM_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DIRM_0
+
+0XE000A204
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DIRECTION_0
+
+31:0
+
+ffffffff
+
+2880
+
+2880
+
+Direction mode for bank 0 0 = input 1 = output Each bit configures the corresponding pin within the 32-bit bank
+
    
+DIRM_0@0XE000A204
+
+31:0
+
+ffffffff
+
+
+
+2880
+
+Direction mode configuration register: Configures bank 0 for direction mode, either input or output
+
    
+
    
+
    DIR MODE BANK 1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    Register ( slcr )MASK_DATA_0_LSW
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASK_DATA_0_LSW
+
+0XE000A000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+MASK_0_LSW
+
+31:16
+
+ffff0000
+
+ff7f
+
+ff7f0000
+
+Mask values to be applied on writes to the corresponding GPIO pins 0 = pin value is updated 1 = pin is masked Each bit controls the corresponding pin within the 16-bit half-bank Write Only, Read back as zero
+
    
+DATA_0_LSW
+
+15:0
+
+ffff
+
+80
+
+80
+
+Data values read from or written to the corresponding GPIO pins Each bit controls the corresponding pin within the 16-bit half-bank Note: Bit[6], bit[7] default value = 0
+
    
+MASK_DATA_0_LSW@0XE000A000
+
+31:0
+
+ffffffff
+
+
+
+ff7f0080
+
+Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins
+
    
+
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE BANK 0
    
+
    Register ( slcr )OEN_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+OEN_0
+
+0XE000A208
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+OP_ENABLE_0
+
+31:0
+
+ffffffff
+
+2880
+
+2880
+
+Output enables for bank 0 0 = disabled 1 = enabled Each bit configures the corresponding pin within the 32-bit bank
+
    
+OEN_0@0XE000A208
+
+31:0
+
+ffffffff
+
+
+
+2880
+
+Output enable register: Configures the output enables of bank 0
+
    
+
    
+
    OUTPUT ENABLE BANK 1
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    Register ( slcr )MASK_DATA_0_LSW
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASK_DATA_0_LSW
+
+0XE000A000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+MASK_0_LSW
+
+31:16
+
+ffff0000
+
+ff7f
+
+ff7f0000
+
+Mask values to be applied on writes to the corresponding GPIO pins 0 = pin value is updated 1 = pin is masked Each bit controls the corresponding pin within the 16-bit half-bank Write Only, Read back as zero
+
    
+DATA_0_LSW
+
+15:0
+
+ffff
+
+0
+
+0
+
+Data values read from or written to the corresponding GPIO pins Each bit controls the corresponding pin within the 16-bit half-bank Note: Bit[6], bit[7] default value = 0
+
    
+MASK_DATA_0_LSW@0XE000A000
+
+31:0
+
+ffffffff
+
+
+
+ff7f0000
+
+Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins
+
    
+
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    Register ( slcr )MASK_DATA_0_LSW
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASK_DATA_0_LSW
+
+0XE000A000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+MASK_0_LSW
+
+31:16
+
+ffff0000
+
+ff7f
+
+ff7f0000
+
+Mask values to be applied on writes to the corresponding GPIO pins 0 = pin value is updated 1 = pin is masked Each bit controls the corresponding pin within the 16-bit half-bank Write Only, Read back as zero
+
    
+DATA_0_LSW
+
+15:0
+
+ffff
+
+80
+
+80
+
+Data values read from or written to the corresponding GPIO pins Each bit controls the corresponding pin within the 16-bit half-bank Note: Bit[6], bit[7] default value = 0
+
    
+MASK_DATA_0_LSW@0XE000A000
+
+31:0
+
+ffffffff
+
+
+
+ff7f0080
+
+Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins
+
    
+
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    ENET RESET
    
+
    DIR MODE BANK 0
    
+
    Register ( slcr )DIRM_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DIRM_0
+
+0XE000A204
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DIRECTION_0
+
+31:0
+
+ffffffff
+
+2880
+
+2880
+
+Direction mode for bank 0 0 = input 1 = output Each bit configures the corresponding pin within the 32-bit bank
+
    
+DIRM_0@0XE000A204
+
+31:0
+
+ffffffff
+
+
+
+2880
+
+Direction mode configuration register: Configures bank 0 for direction mode, either input or output
+
    
+
    
+
    DIR MODE BANK 1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    Register ( slcr )MASK_DATA_0_LSW
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASK_DATA_0_LSW
+
+0XE000A000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+MASK_0_LSW
+
+31:16
+
+ffff0000
+
+f7ff
+
+f7ff0000
+
+Mask values to be applied on writes to the corresponding GPIO pins 0 = pin value is updated 1 = pin is masked Each bit controls the corresponding pin within the 16-bit half-bank Write Only, Read back as zero
+
    
+DATA_0_LSW
+
+15:0
+
+ffff
+
+800
+
+800
+
+Data values read from or written to the corresponding GPIO pins Each bit controls the corresponding pin within the 16-bit half-bank Note: Bit[6], bit[7] default value = 0
+
    
+MASK_DATA_0_LSW@0XE000A000
+
+31:0
+
+ffffffff
+
+
+
+f7ff0800
+
+Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins
+
    
+
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE BANK 0
    
+
    Register ( slcr )OEN_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+OEN_0
+
+0XE000A208
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+OP_ENABLE_0
+
+31:0
+
+ffffffff
+
+2880
+
+2880
+
+Output enables for bank 0 0 = disabled 1 = enabled Each bit configures the corresponding pin within the 32-bit bank
+
    
+OEN_0@0XE000A208
+
+31:0
+
+ffffffff
+
+
+
+2880
+
+Output enable register: Configures the output enables of bank 0
+
    
+
    
+
    OUTPUT ENABLE BANK 1
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    Register ( slcr )MASK_DATA_0_LSW
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASK_DATA_0_LSW
+
+0XE000A000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+MASK_0_LSW
+
+31:16
+
+ffff0000
+
+f7ff
+
+f7ff0000
+
+Mask values to be applied on writes to the corresponding GPIO pins 0 = pin value is updated 1 = pin is masked Each bit controls the corresponding pin within the 16-bit half-bank Write Only, Read back as zero
+
    
+DATA_0_LSW
+
+15:0
+
+ffff
+
+0
+
+0
+
+Data values read from or written to the corresponding GPIO pins Each bit controls the corresponding pin within the 16-bit half-bank Note: Bit[6], bit[7] default value = 0
+
    
+MASK_DATA_0_LSW@0XE000A000
+
+31:0
+
+ffffffff
+
+
+
+f7ff0000
+
+Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins
+
    
+
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    Register ( slcr )MASK_DATA_0_LSW
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASK_DATA_0_LSW
+
+0XE000A000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+MASK_0_LSW
+
+31:16
+
+ffff0000
+
+f7ff
+
+f7ff0000
+
+Mask values to be applied on writes to the corresponding GPIO pins 0 = pin value is updated 1 = pin is masked Each bit controls the corresponding pin within the 16-bit half-bank Write Only, Read back as zero
+
    
+DATA_0_LSW
+
+15:0
+
+ffff
+
+800
+
+800
+
+Data values read from or written to the corresponding GPIO pins Each bit controls the corresponding pin within the 16-bit half-bank Note: Bit[6], bit[7] default value = 0
+
    
+MASK_DATA_0_LSW@0XE000A000
+
+31:0
+
+ffffffff
+
+
+
+f7ff0800
+
+Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins
+
    
+
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    I2C RESET
    
+
    DIR MODE GPIO BANK0
    
+
    Register ( slcr )DIRM_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+DIRM_0
+
+0XE000A204
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+DIRECTION_0
+
+31:0
+
+ffffffff
+
+2880
+
+2880
+
+Direction mode for bank 0 0 = input 1 = output Each bit configures the corresponding pin within the 32-bit bank
+
    
+DIRM_0@0XE000A204
+
+31:0
+
+ffffffff
+
+
+
+2880
+
+Direction mode configuration register: Configures bank 0 for direction mode, either input or output
+
    
+
    
+
    DIR MODE GPIO BANK1
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    Register ( slcr )MASK_DATA_0_LSW
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASK_DATA_0_LSW
+
+0XE000A000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+MASK_0_LSW
+
+31:16
+
+ffff0000
+
+dfff
+
+dfff0000
+
+Mask values to be applied on writes to the corresponding GPIO pins 0 = pin value is updated 1 = pin is masked Each bit controls the corresponding pin within the 16-bit half-bank Write Only, Read back as zero
+
    
+DATA_0_LSW
+
+15:0
+
+ffff
+
+2000
+
+2000
+
+Data values read from or written to the corresponding GPIO pins Each bit controls the corresponding pin within the 16-bit half-bank Note: Bit[6], bit[7] default value = 0
+
    
+MASK_DATA_0_LSW@0XE000A000
+
+31:0
+
+ffffffff
+
+
+
+dfff2000
+
+Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins
+
    
+
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
    OUTPUT ENABLE
    
+
    Register ( slcr )OEN_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+OEN_0
+
+0XE000A208
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+OP_ENABLE_0
+
+31:0
+
+ffffffff
+
+2880
+
+2880
+
+Output enables for bank 0 0 = disabled 1 = enabled Each bit configures the corresponding pin within the 32-bit bank
+
    
+OEN_0@0XE000A208
+
+31:0
+
+ffffffff
+
+
+
+2880
+
+Output enable register: Configures the output enables of bank 0
+
    
+
    
+
    OUTPUT ENABLE
    
+
    MASK_DATA_0_LSW LOW BANK [15:0]
    
+
    Register ( slcr )MASK_DATA_0_LSW
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASK_DATA_0_LSW
+
+0XE000A000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+MASK_0_LSW
+
+31:16
+
+ffff0000
+
+dfff
+
+dfff0000
+
+Mask values to be applied on writes to the corresponding GPIO pins 0 = pin value is updated 1 = pin is masked Each bit controls the corresponding pin within the 16-bit half-bank Write Only, Read back as zero
+
    
+DATA_0_LSW
+
+15:0
+
+ffff
+
+0
+
+0
+
+Data values read from or written to the corresponding GPIO pins Each bit controls the corresponding pin within the 16-bit half-bank Note: Bit[6], bit[7] default value = 0
+
    
+MASK_DATA_0_LSW@0XE000A000
+
+31:0
+
+ffffffff
+
+
+
+dfff0000
+
+Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins
+
    
+
    
+
    MASK_DATA_0_MSW LOW BANK [31:16]
    
+
    MASK_DATA_1_LSW LOW BANK [47:32]
    
+
    MASK_DATA_1_MSW LOW BANK [53:48]
    
+
    ADD 1 MS DELAY
    
+
    MASK_DATA_0_LSW HIGH BANK [15:0]
    
+
    Register ( slcr )MASK_DATA_0_LSW
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+MASK_DATA_0_LSW
+
+0XE000A000
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+MASK_0_LSW
+
+31:16
+
+ffff0000
+
+dfff
+
+dfff0000
+
+Mask values to be applied on writes to the corresponding GPIO pins 0 = pin value is updated 1 = pin is masked Each bit controls the corresponding pin within the 16-bit half-bank Write Only, Read back as zero
+
    
+DATA_0_LSW
+
+15:0
+
+ffff
+
+2000
+
+2000
+
+Data values read from or written to the corresponding GPIO pins Each bit controls the corresponding pin within the 16-bit half-bank Note: Bit[6], bit[7] default value = 0
+
    
+MASK_DATA_0_LSW@0XE000A000
+
+31:0
+
+ffffffff
+
+
+
+dfff2000
+
+Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins
+
    
+
    
+
    MASK_DATA_0_MSW HIGH BANK [31:16]
    
+
    MASK_DATA_1_LSW HIGH BANK [47:32]
    
+
    MASK_DATA_1_MSW HIGH BANK [53:48]
    
+
+
    
+
    ps7_post_config_1_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+SLCR_UNLOCK
+
+
+0XF8000008
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Unlock
+
    
+
+LVL_SHFTR_EN
+
+
+0XF8000900
+
+32
+
+RW
+
+0x000000
+
+Level Shifters Enable
+
    
+
+FPGA_RST_CTRL
+
+
+0XF8000240
+
+32
+
+RW
+
+0x000000
+
+FPGA Software Reset Control
+
    
+
+SLCR_LOCK
+
+
+0XF8000004
+
+32
+
+WO
+
+0x000000
+
+SLCR Write Protection Lock
+
    
+
    
+
    ps7_post_config_1_0
    
+
+
+
+
+
+
+
+
+
+
    SLCR SETTINGS
    
+
    Register ( slcr )SLCR_UNLOCK
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_UNLOCK
+
+0XF8000008
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+UNLOCK_KEY
+
+15:0
+
+ffff
+
+df0d
+
+df0d
+
+When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero.
+
    
+SLCR_UNLOCK@0XF8000008
+
+31:0
+
+ffff
+
+
+
+df0d
+
+SLCR Write Protection Unlock
+
    
+
    
+
    ENABLING LEVEL SHIFTER
    
+
    Register ( slcr )LVL_SHFTR_EN
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LVL_SHFTR_EN
+
+0XF8000900
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+USER_INP_ICT_EN_0
+
+1:0
+
+3
+
+3
+
+3
+
+Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0].
+
    
+USER_INP_ICT_EN_1
+
+3:2
+
+c
+
+3
+
+c
+
+Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0].
+
    
+LVL_SHFTR_EN@0XF8000900
+
+31:0
+
+f
+
+
+
+f
+
+Level Shifters Enable
+
    
+
    
+
    FPGA RESETS TO 0
    
+
    Register ( slcr )FPGA_RST_CTRL
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+FPGA_RST_CTRL
+
+0XF8000240
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+reserved_3
+
+31:25
+
+fe000000
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is always zero.
+
    
+FPGA_ACP_RST
+
+24:24
+
+1000000
+
+0
+
+0
+
+FPGA ACP port soft reset. 0 - No reset. 1 - ACP AXI interface reset output asserted.
+
    
+FPGA_AXDS3_RST
+
+23:23
+
+800000
+
+0
+
+0
+
+AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS3AXI interface reset output asserted.
+
    
+FPGA_AXDS2_RST
+
+22:22
+
+400000
+
+0
+
+0
+
+AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS2 AXI interface reset output asserted.
+
    
+FPGA_AXDS1_RST
+
+21:21
+
+200000
+
+0
+
+0
+
+AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS1 AXI interface reset output asserted.
+
    
+FPGA_AXDS0_RST
+
+20:20
+
+100000
+
+0
+
+0
+
+AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS0 AXI interface reset output asserted.
+
    
+reserved_2
+
+19:18
+
+c0000
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is always zero.
+
    
+FSSW1_FPGA_RST
+
+17:17
+
+20000
+
+0
+
+0
+
+General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 1 reset is asserted.
+
    
+FSSW0_FPGA_RST
+
+16:16
+
+10000
+
+0
+
+0
+
+General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 0 reset is asserted.
+
    
+reserved_1
+
+15:14
+
+c000
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is always zero.
+
    
+FPGA_FMSW1_RST
+
+13:13
+
+2000
+
+0
+
+0
+
+General purpose FPGA master interface 1 soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0 - No reset. 1 - FPGA master interface 1 reset is asserted.
+
    
+FPGA_FMSW0_RST
+
+12:12
+
+1000
+
+0
+
+0
+
+General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0 - No reset. 1 - FPGA master interface 0 reset is asserted.
+
    
+FPGA_DMA3_RST
+
+11:11
+
+800
+
+0
+
+0
+
+FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 3 peripheral request reset output asserted.
+
    
+FPGA_DMA2_RST
+
+10:10
+
+400
+
+0
+
+0
+
+FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 2 peripheral request reset output asserted.
+
    
+FPGA_DMA1_RST
+
+9:9
+
+200
+
+0
+
+0
+
+FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 1 peripheral request reset output asserted.
+
    
+FPGA_DMA0_RST
+
+8:8
+
+100
+
+0
+
+0
+
+FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 0 peripheral request reset output asserted.
+
    
+reserved
+
+7:4
+
+f0
+
+0
+
+0
+
+Reserved. Writes are ignored, read data is always zero.
+
    
+FPGA3_OUT_RST
+
+3:3
+
+8
+
+0
+
+0
+
+FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0 - No reset. 1 - FPGA 3 top level reset output asserted.
+
    
+FPGA2_OUT_RST
+
+2:2
+
+4
+
+0
+
+0
+
+FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0 - No reset. 1 - FPGA 2 top level reset output asserted.
+
    
+FPGA1_OUT_RST
+
+1:1
+
+2
+
+0
+
+0
+
+FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0 - No reset. 1 - FPGA 1 top level reset output asserted.
+
    
+FPGA0_OUT_RST
+
+0:0
+
+1
+
+0
+
+0
+
+FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0 - No reset. 1 - FPGA 0 top level reset output asserted.
+
    
+FPGA_RST_CTRL@0XF8000240
+
+31:0
+
+ffffffff
+
+
+
+0
+
+FPGA Software Reset Control
+
    
+
    
+
    AFI REGISTERS
    
+
    AFI0 REGISTERS
    
+
    AFI1 REGISTERS
    
+
    AFI2 REGISTERS
    
+
    AFI3 REGISTERS
    
+
    LOCK IT BACK
    
+
    Register ( slcr )SLCR_LOCK
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+SLCR_LOCK
+
+0XF8000004
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+LOCK_KEY
+
+15:0
+
+ffff
+
+767b
+
+767b
+
+When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero.
+
    
+SLCR_LOCK@0XF8000004
+
+31:0
+
+ffff
+
+
+
+767b
+
+SLCR Write Protection Lock
+
    
+
    
+
+
    
+
    ps7_debug_1_0
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+LAR
+
+
+0XF8898FB0
+
+32
+
+WO
+
+0x000000
+
+Lock Access Register
+
    
+
+LAR
+
+
+0XF8899FB0
+
+32
+
+WO
+
+0x000000
+
+Lock Access Register
+
    
+
+LAR
+
+
+0XF8809FB0
+
+32
+
+WO
+
+0x000000
+
+Lock Access Register
+
    
+
    
+
    ps7_debug_1_0
    
+
+
+
+
+
+
+
+
+
+
    CROSS TRIGGER CONFIGURATIONS
    
+
    UNLOCKING CTI REGISTERS
    
+
    Register ( slcr )LAR
    
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LAR
+
+0XF8898FB0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+KEY
+
+31:0
+
+ffffffff
+
+c5acce55
+
+c5acce55
+
+Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
+
    
+LAR@0XF8898FB0
+
+31:0
+
+ffffffff
+
+
+
+c5acce55
+
+Lock Access Register
+
    
+
    
+
    Register ( slcr )LAR
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LAR
+
+0XF8899FB0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+KEY
+
+31:0
+
+ffffffff
+
+c5acce55
+
+c5acce55
+
+Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
+
    
+LAR@0XF8899FB0
+
+31:0
+
+ffffffff
+
+
+
+c5acce55
+
+Lock Access Register
+
    
+
    
+
    Register ( slcr )LAR
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Register Name
+
+Address
+
+Width
+
+Type
+
+Reset Value
+
+Description
+
    
+LAR
+
+0XF8809FB0
+
+32
+
+rw
+
+0x00000000
+
+--
+
    
+
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    
+Field Name
+
+Bits
+
+Mask
+
+Value
+
+Shifted Value
+
+Description
+
    
+KEY
+
+31:0
+
+ffffffff
+
+c5acce55
+
+c5acce55
+
+Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31.
+
    
+LAR@0XF8809FB0
+
+31:0
+
+ffffffff
+
+
+
+c5acce55
+
+Lock Access Register
+
    
+
    
+
    ENABLING CTI MODULES AND CHANNELS
    
+
    MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
    
+
+
    
+
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init.tcl b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init.tcl
new file mode 100644
index 000000000..22b3b691f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init.tcl
@@ -0,0 +1,887 @@
+proc ps7_pll_init_data_3_0 {} {
+    mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
+    mask_write 0XF8000110 0x003FFFF0 0x000FA220
+    mask_write 0XF8000100 0x0007F000 0x00028000
+    mask_write 0XF8000100 0x00000010 0x00000010
+    mask_write 0XF8000100 0x00000001 0x00000001
+    mask_write 0XF8000100 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000001
+    mask_write 0XF8000100 0x00000010 0x00000000
+    mask_write 0XF8000120 0x1F003F30 0x1F000200
+    mask_write 0XF8000114 0x003FFFF0 0x0012C220
+    mask_write 0XF8000104 0x0007F000 0x00020000
+    mask_write 0XF8000104 0x00000010 0x00000010
+    mask_write 0XF8000104 0x00000001 0x00000001
+    mask_write 0XF8000104 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000002
+    mask_write 0XF8000104 0x00000010 0x00000000
+    mask_write 0XF8000124 0xFFF00003 0x0C200003
+    mask_write 0XF8000118 0x003FFFF0 0x001452C0
+    mask_write 0XF8000108 0x0007F000 0x0001E000
+    mask_write 0XF8000108 0x00000010 0x00000010
+    mask_write 0XF8000108 0x00000001 0x00000001
+    mask_write 0XF8000108 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000004
+    mask_write 0XF8000108 0x00000010 0x00000000
+    mask_write 0XF8000004 0x0000FFFF 0x0000767B
+}
+proc ps7_clock_init_data_3_0 {} {
+    mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
+    mask_write 0XF8000128 0x03F03F01 0x00302301
+    mask_write 0XF8000138 0x00000011 0x00000001
+    mask_write 0XF8000140 0x03F03F71 0x00500801
+    mask_write 0XF800014C 0x00003F31 0x00000501
+    mask_write 0XF8000150 0x00003F33 0x00001401
+    mask_write 0XF8000154 0x00003F33 0x00001402
+    mask_write 0XF800015C 0x03F03F33 0x00300E01
+    mask_write 0XF8000160 0x007F007F 0x00000000
+    mask_write 0XF8000168 0x00003F31 0x00000501
+    mask_write 0XF8000170 0x03F03F30 0x00101400
+    mask_write 0XF8000180 0x03F03F30 0x00101400
+    mask_write 0XF8000190 0x03F03F30 0x00101400
+    mask_write 0XF80001A0 0x03F03F30 0x00101400
+    mask_write 0XF80001C4 0x00000001 0x00000001
+    mask_write 0XF800012C 0x01FFCCCD 0x01ED044D
+    mask_write 0XF8000004 0x0000FFFF 0x0000767B
+}
+proc ps7_ddr_init_data_3_0 {} {
+    mask_write 0XF8006000 0x0001FFFF 0x00000080
+    mask_write 0XF8006004 0x0007FFFF 0x00001081
+    mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
+    mask_write 0XF800600C 0x03FFFFFF 0x02001001
+    mask_write 0XF8006010 0x03FFFFFF 0x00014001
+    mask_write 0XF8006014 0x001FFFFF 0x0004159B
+    mask_write 0XF8006018 0xF7FFFFFF 0x452440D2
+    mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
+    mask_write 0XF8006020 0x7FDFFFFC 0x27087290
+    mask_write 0XF8006024 0x0FFFFFC3 0x00000000
+    mask_write 0XF8006028 0x00003FFF 0x00002007
+    mask_write 0XF800602C 0xFFFFFFFF 0x00000008
+    mask_write 0XF8006030 0xFFFFFFFF 0x00040930
+    mask_write 0XF8006034 0x13FF3FFF 0x00011054
+    mask_write 0XF8006038 0x00000003 0x00000000
+    mask_write 0XF800603C 0x000FFFFF 0x00000777
+    mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
+    mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
+    mask_write 0XF8006048 0x0003F000 0x0003C000
+    mask_write 0XF8006050 0xFF0F8FFF 0x77010800
+    mask_write 0XF8006058 0x00010000 0x00000000
+    mask_write 0XF800605C 0x0000FFFF 0x00005003
+    mask_write 0XF8006060 0x000017FF 0x0000003E
+    mask_write 0XF8006064 0x00021FE0 0x00020000
+    mask_write 0XF8006068 0x03FFFFFF 0x00284141
+    mask_write 0XF800606C 0x0000FFFF 0x00001610
+    mask_write 0XF8006078 0x03FFFFFF 0x00466111
+    mask_write 0XF800607C 0x000FFFFF 0x00032222
+    mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
+    mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
+    mask_write 0XF80060AC 0x000001FF 0x000001FE
+    mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
+    mask_write 0XF80060B4 0x00000200 0x00000200
+    mask_write 0XF80060B8 0x01FFFFFF 0x00200066
+    mask_write 0XF80060C4 0x00000003 0x00000003
+    mask_write 0XF80060C4 0x00000003 0x00000000
+    mask_write 0XF80060C8 0x000000FF 0x00000000
+    mask_write 0XF80060DC 0x00000001 0x00000000
+    mask_write 0XF80060F0 0x0000FFFF 0x00000000
+    mask_write 0XF80060F4 0x0000000F 0x00000008
+    mask_write 0XF8006114 0x000000FF 0x00000000
+    mask_write 0XF8006118 0x7FFFFFCF 0x40000001
+    mask_write 0XF800611C 0x7FFFFFCF 0x40000001
+    mask_write 0XF8006120 0x7FFFFFCF 0x40000001
+    mask_write 0XF8006124 0x7FFFFFCF 0x40000001
+    mask_write 0XF800612C 0x000FFFFF 0x0003C81D
+    mask_write 0XF8006130 0x000FFFFF 0x00036012
+    mask_write 0XF8006134 0x000FFFFF 0x0003780C
+    mask_write 0XF8006138 0x000FFFFF 0x0003B821
+    mask_write 0XF8006140 0x000FFFFF 0x00000035
+    mask_write 0XF8006144 0x000FFFFF 0x00000035
+    mask_write 0XF8006148 0x000FFFFF 0x00000035
+    mask_write 0XF800614C 0x000FFFFF 0x00000035
+    mask_write 0XF8006154 0x000FFFFF 0x0000009D
+    mask_write 0XF8006158 0x000FFFFF 0x00000092
+    mask_write 0XF800615C 0x000FFFFF 0x0000008C
+    mask_write 0XF8006160 0x000FFFFF 0x000000A1
+    mask_write 0XF8006168 0x001FFFFF 0x00000147
+    mask_write 0XF800616C 0x001FFFFF 0x0000012D
+    mask_write 0XF8006170 0x001FFFFF 0x00000133
+    mask_write 0XF8006174 0x001FFFFF 0x00000143
+    mask_write 0XF800617C 0x000FFFFF 0x000000DD
+    mask_write 0XF8006180 0x000FFFFF 0x000000D2
+    mask_write 0XF8006184 0x000FFFFF 0x000000CC
+    mask_write 0XF8006188 0x000FFFFF 0x000000E1
+    mask_write 0XF8006190 0x6FFFFEFE 0x00040080
+    mask_write 0XF8006194 0x000FFFFF 0x0001FC82
+    mask_write 0XF8006204 0xFFFFFFFF 0x00000000
+    mask_write 0XF8006208 0x000703FF 0x000003FF
+    mask_write 0XF800620C 0x000703FF 0x000003FF
+    mask_write 0XF8006210 0x000703FF 0x000003FF
+    mask_write 0XF8006214 0x000703FF 0x000003FF
+    mask_write 0XF8006218 0x000F03FF 0x000003FF
+    mask_write 0XF800621C 0x000F03FF 0x000003FF
+    mask_write 0XF8006220 0x000F03FF 0x000003FF
+    mask_write 0XF8006224 0x000F03FF 0x000003FF
+    mask_write 0XF80062A8 0x00000FF5 0x00000000
+    mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
+    mask_write 0XF80062B0 0x003FFFFF 0x00005125
+    mask_write 0XF80062B4 0x0003FFFF 0x000012A8
+    mask_poll 0XF8000B74 0x00002000
+    mask_write 0XF8006000 0x0001FFFF 0x00000081
+    mask_poll 0XF8006054 0x00000007
+}
+proc ps7_mio_init_data_3_0 {} {
+    mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
+    mask_write 0XF8000B00 0x00000071 0x00000001
+    mask_write 0XF8000B40 0x00000FFF 0x00000600
+    mask_write 0XF8000B44 0x00000FFF 0x00000600
+    mask_write 0XF8000B48 0x00000FFF 0x00000672
+    mask_write 0XF8000B4C 0x00000FFF 0x00000672
+    mask_write 0XF8000B50 0x00000FFF 0x00000674
+    mask_write 0XF8000B54 0x00000FFF 0x00000674
+    mask_write 0XF8000B58 0x00000FFF 0x00000600
+    mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
+    mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B6C 0x00007FFF 0x00000E09
+    mask_write 0XF8000B70 0x00000001 0x00000001
+    mask_write 0XF8000B70 0x00000021 0x00000020
+    mask_write 0XF8000B70 0x07FEFFFF 0x00000823
+    mask_write 0XF8000700 0x00003F01 0x00001201
+    mask_write 0XF8000704 0x00003FFF 0x00001202
+    mask_write 0XF8000708 0x00003FFF 0x00000202
+    mask_write 0XF800070C 0x00003FFF 0x00000202
+    mask_write 0XF8000710 0x00003FFF 0x00000202
+    mask_write 0XF8000714 0x00003FFF 0x00000202
+    mask_write 0XF8000718 0x00003FFF 0x00000202
+    mask_write 0XF800071C 0x00003FFF 0x00000200
+    mask_write 0XF8000720 0x00003FFF 0x00000202
+    mask_write 0XF8000724 0x00003FFF 0x00001200
+    mask_write 0XF8000728 0x00003FFF 0x00001200
+    mask_write 0XF800072C 0x00003FFF 0x00001200
+    mask_write 0XF8000730 0x00003FFF 0x00001200
+    mask_write 0XF8000734 0x00003FFF 0x00001200
+    mask_write 0XF8000738 0x00003FFF 0x00001200
+    mask_write 0XF800073C 0x00003F01 0x00001201
+    mask_write 0XF8000740 0x00003FFF 0x00002802
+    mask_write 0XF8000744 0x00003FFF 0x00002802
+    mask_write 0XF8000748 0x00003FFF 0x00002802
+    mask_write 0XF800074C 0x00003FFF 0x00002802
+    mask_write 0XF8000750 0x00003FFF 0x00002802
+    mask_write 0XF8000754 0x00003FFF 0x00002802
+    mask_write 0XF8000758 0x00003FFF 0x00000803
+    mask_write 0XF800075C 0x00003FFF 0x00000803
+    mask_write 0XF8000760 0x00003FFF 0x00000803
+    mask_write 0XF8000764 0x00003FFF 0x00000803
+    mask_write 0XF8000768 0x00003FFF 0x00000803
+    mask_write 0XF800076C 0x00003FFF 0x00000803
+    mask_write 0XF8000770 0x00003FFF 0x00000204
+    mask_write 0XF8000774 0x00003FFF 0x00000205
+    mask_write 0XF8000778 0x00003FFF 0x00000204
+    mask_write 0XF800077C 0x00003FFF 0x00000205
+    mask_write 0XF8000780 0x00003FFF 0x00000204
+    mask_write 0XF8000784 0x00003FFF 0x00000204
+    mask_write 0XF8000788 0x00003FFF 0x00000204
+    mask_write 0XF800078C 0x00003FFF 0x00000204
+    mask_write 0XF8000790 0x00003FFF 0x00000205
+    mask_write 0XF8000794 0x00003FFF 0x00000204
+    mask_write 0XF8000798 0x00003FFF 0x00000204
+    mask_write 0XF800079C 0x00003FFF 0x00000204
+    mask_write 0XF80007A0 0x00003FFF 0x00000280
+    mask_write 0XF80007A4 0x00003FFF 0x00000280
+    mask_write 0XF80007A8 0x00003FFF 0x00000280
+    mask_write 0XF80007AC 0x00003FFF 0x00000280
+    mask_write 0XF80007B0 0x00003FFF 0x00000280
+    mask_write 0XF80007B4 0x00003FFF 0x00000280
+    mask_write 0XF80007B8 0x00003FFF 0x00001221
+    mask_write 0XF80007BC 0x00003FFF 0x00001220
+    mask_write 0XF80007C0 0x00003FFF 0x000002E0
+    mask_write 0XF80007C4 0x00003FFF 0x000002E1
+    mask_write 0XF80007C8 0x00003FFF 0x00001240
+    mask_write 0XF80007CC 0x00003FFF 0x00001240
+    mask_write 0XF80007D0 0x00003FFF 0x00000280
+    mask_write 0XF80007D4 0x00003FFF 0x00000280
+    mask_write 0XF8000830 0x003F003F 0x0000000F
+    mask_write 0XF8000004 0x0000FFFF 0x0000767B
+}
+proc ps7_peripherals_init_data_3_0 {} {
+    mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
+    mask_write 0XF8000B48 0x00000180 0x00000180
+    mask_write 0XF8000B4C 0x00000180 0x00000180
+    mask_write 0XF8000B50 0x00000180 0x00000180
+    mask_write 0XF8000B54 0x00000180 0x00000180
+    mask_write 0XF8000004 0x0000FFFF 0x0000767B
+    mask_write 0XE0001034 0x000000FF 0x00000006
+    mask_write 0XE0001018 0x0000FFFF 0x0000003E
+    mask_write 0XE0001000 0x000001FF 0x00000017
+    mask_write 0XE0001004 0x000003FF 0x00000020
+    mask_write 0XE000D000 0x00080000 0x00080000
+    mask_write 0XF8007000 0x20000000 0x00000000
+    mask_write 0XE000A204 0xFFFFFFFF 0x00002880
+    mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080
+    mask_write 0XE000A208 0xFFFFFFFF 0x00002880
+    mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0000
+    mask_delay 0XF8F00200 1
+    mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080
+    mask_write 0XE000A204 0xFFFFFFFF 0x00002880
+    mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0800
+    mask_write 0XE000A208 0xFFFFFFFF 0x00002880
+    mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0000
+    mask_delay 0XF8F00200 1
+    mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0800
+    mask_write 0XE000A204 0xFFFFFFFF 0x00002880
+    mask_write 0XE000A000 0xFFFFFFFF 0xDFFF2000
+    mask_write 0XE000A208 0xFFFFFFFF 0x00002880
+    mask_write 0XE000A000 0xFFFFFFFF 0xDFFF0000
+    mask_delay 0XF8F00200 1
+    mask_write 0XE000A000 0xFFFFFFFF 0xDFFF2000
+}
+proc ps7_post_config_3_0 {} {
+    mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
+    mask_write 0XF8000900 0x0000000F 0x0000000F
+    mask_write 0XF8000240 0xFFFFFFFF 0x00000000
+    mask_write 0XF8000004 0x0000FFFF 0x0000767B
+}
+proc ps7_debug_3_0 {} {
+    mask_write 0XF8898FB0 0xFFFFFFFF 0xC5ACCE55
+    mask_write 0XF8899FB0 0xFFFFFFFF 0xC5ACCE55
+    mask_write 0XF8809FB0 0xFFFFFFFF 0xC5ACCE55
+}
+proc ps7_pll_init_data_2_0 {} {
+    mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
+    mask_write 0XF8000110 0x003FFFF0 0x000FA220
+    mask_write 0XF8000100 0x0007F000 0x00028000
+    mask_write 0XF8000100 0x00000010 0x00000010
+    mask_write 0XF8000100 0x00000001 0x00000001
+    mask_write 0XF8000100 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000001
+    mask_write 0XF8000100 0x00000010 0x00000000
+    mask_write 0XF8000120 0x1F003F30 0x1F000200
+    mask_write 0XF8000114 0x003FFFF0 0x0012C220
+    mask_write 0XF8000104 0x0007F000 0x00020000
+    mask_write 0XF8000104 0x00000010 0x00000010
+    mask_write 0XF8000104 0x00000001 0x00000001
+    mask_write 0XF8000104 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000002
+    mask_write 0XF8000104 0x00000010 0x00000000
+    mask_write 0XF8000124 0xFFF00003 0x0C200003
+    mask_write 0XF8000118 0x003FFFF0 0x001452C0
+    mask_write 0XF8000108 0x0007F000 0x0001E000
+    mask_write 0XF8000108 0x00000010 0x00000010
+    mask_write 0XF8000108 0x00000001 0x00000001
+    mask_write 0XF8000108 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000004
+    mask_write 0XF8000108 0x00000010 0x00000000
+    mask_write 0XF8000004 0x0000FFFF 0x0000767B
+}
+proc ps7_clock_init_data_2_0 {} {
+    mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
+    mask_write 0XF8000128 0x03F03F01 0x00302301
+    mask_write 0XF8000138 0x00000011 0x00000001
+    mask_write 0XF8000140 0x03F03F71 0x00500801
+    mask_write 0XF800014C 0x00003F31 0x00000501
+    mask_write 0XF8000150 0x00003F33 0x00001401
+    mask_write 0XF8000154 0x00003F33 0x00001402
+    mask_write 0XF800015C 0x03F03F33 0x00300E01
+    mask_write 0XF8000160 0x007F007F 0x00000000
+    mask_write 0XF8000168 0x00003F31 0x00000501
+    mask_write 0XF8000170 0x03F03F30 0x00101400
+    mask_write 0XF8000180 0x03F03F30 0x00101400
+    mask_write 0XF8000190 0x03F03F30 0x00101400
+    mask_write 0XF80001A0 0x03F03F30 0x00101400
+    mask_write 0XF80001C4 0x00000001 0x00000001
+    mask_write 0XF800012C 0x01FFCCCD 0x01ED044D
+    mask_write 0XF8000004 0x0000FFFF 0x0000767B
+}
+proc ps7_ddr_init_data_2_0 {} {
+    mask_write 0XF8006000 0x0001FFFF 0x00000080
+    mask_write 0XF8006004 0x1FFFFFFF 0x00081081
+    mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
+    mask_write 0XF800600C 0x03FFFFFF 0x02001001
+    mask_write 0XF8006010 0x03FFFFFF 0x00014001
+    mask_write 0XF8006014 0x001FFFFF 0x0004159B
+    mask_write 0XF8006018 0xF7FFFFFF 0x452440D2
+    mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
+    mask_write 0XF8006020 0xFFFFFFFC 0x27287290
+    mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
+    mask_write 0XF8006028 0x00003FFF 0x00002007
+    mask_write 0XF800602C 0xFFFFFFFF 0x00000008
+    mask_write 0XF8006030 0xFFFFFFFF 0x00040930
+    mask_write 0XF8006034 0x13FF3FFF 0x00011054
+    mask_write 0XF8006038 0x00001FC3 0x00000000
+    mask_write 0XF800603C 0x000FFFFF 0x00000777
+    mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
+    mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
+    mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
+    mask_write 0XF8006050 0xFF0F8FFF 0x77010800
+    mask_write 0XF8006058 0x0001FFFF 0x00000101
+    mask_write 0XF800605C 0x0000FFFF 0x00005003
+    mask_write 0XF8006060 0x000017FF 0x0000003E
+    mask_write 0XF8006064 0x00021FE0 0x00020000
+    mask_write 0XF8006068 0x03FFFFFF 0x00284141
+    mask_write 0XF800606C 0x0000FFFF 0x00001610
+    mask_write 0XF8006078 0x03FFFFFF 0x00466111
+    mask_write 0XF800607C 0x000FFFFF 0x00032222
+    mask_write 0XF80060A0 0x00FFFFFF 0x00008000
+    mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
+    mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
+    mask_write 0XF80060AC 0x000001FF 0x000001FE
+    mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
+    mask_write 0XF80060B4 0x000007FF 0x00000200
+    mask_write 0XF80060B8 0x01FFFFFF 0x00200066
+    mask_write 0XF80060C4 0x00000003 0x00000003
+    mask_write 0XF80060C4 0x00000003 0x00000000
+    mask_write 0XF80060C8 0x000000FF 0x00000000
+    mask_write 0XF80060DC 0x00000001 0x00000000
+    mask_write 0XF80060F0 0x0000FFFF 0x00000000
+    mask_write 0XF80060F4 0x0000000F 0x00000008
+    mask_write 0XF8006114 0x000000FF 0x00000000
+    mask_write 0XF8006118 0x7FFFFFFF 0x40000001
+    mask_write 0XF800611C 0x7FFFFFFF 0x40000001
+    mask_write 0XF8006120 0x7FFFFFFF 0x40000001
+    mask_write 0XF8006124 0x7FFFFFFF 0x40000001
+    mask_write 0XF800612C 0x000FFFFF 0x0003C81D
+    mask_write 0XF8006130 0x000FFFFF 0x00036012
+    mask_write 0XF8006134 0x000FFFFF 0x0003780C
+    mask_write 0XF8006138 0x000FFFFF 0x0003B821
+    mask_write 0XF8006140 0x000FFFFF 0x00000035
+    mask_write 0XF8006144 0x000FFFFF 0x00000035
+    mask_write 0XF8006148 0x000FFFFF 0x00000035
+    mask_write 0XF800614C 0x000FFFFF 0x00000035
+    mask_write 0XF8006154 0x000FFFFF 0x0000009D
+    mask_write 0XF8006158 0x000FFFFF 0x00000092
+    mask_write 0XF800615C 0x000FFFFF 0x0000008C
+    mask_write 0XF8006160 0x000FFFFF 0x000000A1
+    mask_write 0XF8006168 0x001FFFFF 0x00000147
+    mask_write 0XF800616C 0x001FFFFF 0x0000012D
+    mask_write 0XF8006170 0x001FFFFF 0x00000133
+    mask_write 0XF8006174 0x001FFFFF 0x00000143
+    mask_write 0XF800617C 0x000FFFFF 0x000000DD
+    mask_write 0XF8006180 0x000FFFFF 0x000000D2
+    mask_write 0XF8006184 0x000FFFFF 0x000000CC
+    mask_write 0XF8006188 0x000FFFFF 0x000000E1
+    mask_write 0XF8006190 0xFFFFFFFF 0x10040080
+    mask_write 0XF8006194 0x000FFFFF 0x0001FC82
+    mask_write 0XF8006204 0xFFFFFFFF 0x00000000
+    mask_write 0XF8006208 0x000F03FF 0x000803FF
+    mask_write 0XF800620C 0x000F03FF 0x000803FF
+    mask_write 0XF8006210 0x000F03FF 0x000803FF
+    mask_write 0XF8006214 0x000F03FF 0x000803FF
+    mask_write 0XF8006218 0x000F03FF 0x000003FF
+    mask_write 0XF800621C 0x000F03FF 0x000003FF
+    mask_write 0XF8006220 0x000F03FF 0x000003FF
+    mask_write 0XF8006224 0x000F03FF 0x000003FF
+    mask_write 0XF80062A8 0x00000FF7 0x00000000
+    mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
+    mask_write 0XF80062B0 0x003FFFFF 0x00005125
+    mask_write 0XF80062B4 0x0003FFFF 0x000012A8
+    mask_poll 0XF8000B74 0x00002000
+    mask_write 0XF8006000 0x0001FFFF 0x00000081
+    mask_poll 0XF8006054 0x00000007
+}
+proc ps7_mio_init_data_2_0 {} {
+    mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
+    mask_write 0XF8000B00 0x00000303 0x00000001
+    mask_write 0XF8000B40 0x00000FFF 0x00000600
+    mask_write 0XF8000B44 0x00000FFF 0x00000600
+    mask_write 0XF8000B48 0x00000FFF 0x00000672
+    mask_write 0XF8000B4C 0x00000FFF 0x00000672
+    mask_write 0XF8000B50 0x00000FFF 0x00000674
+    mask_write 0XF8000B54 0x00000FFF 0x00000674
+    mask_write 0XF8000B58 0x00000FFF 0x00000600
+    mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
+    mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B6C 0x00007FFF 0x00000E09
+    mask_write 0XF8000B70 0x00000021 0x00000021
+    mask_write 0XF8000B70 0x00000021 0x00000020
+    mask_write 0XF8000B70 0x07FFFFFF 0x00000823
+    mask_write 0XF8000700 0x00003F01 0x00001201
+    mask_write 0XF8000704 0x00003FFF 0x00001202
+    mask_write 0XF8000708 0x00003FFF 0x00000202
+    mask_write 0XF800070C 0x00003FFF 0x00000202
+    mask_write 0XF8000710 0x00003FFF 0x00000202
+    mask_write 0XF8000714 0x00003FFF 0x00000202
+    mask_write 0XF8000718 0x00003FFF 0x00000202
+    mask_write 0XF800071C 0x00003FFF 0x00000200
+    mask_write 0XF8000720 0x00003FFF 0x00000202
+    mask_write 0XF8000724 0x00003FFF 0x00001200
+    mask_write 0XF8000728 0x00003FFF 0x00001200
+    mask_write 0XF800072C 0x00003FFF 0x00001200
+    mask_write 0XF8000730 0x00003FFF 0x00001200
+    mask_write 0XF8000734 0x00003FFF 0x00001200
+    mask_write 0XF8000738 0x00003FFF 0x00001200
+    mask_write 0XF800073C 0x00003F01 0x00001201
+    mask_write 0XF8000740 0x00003FFF 0x00002802
+    mask_write 0XF8000744 0x00003FFF 0x00002802
+    mask_write 0XF8000748 0x00003FFF 0x00002802
+    mask_write 0XF800074C 0x00003FFF 0x00002802
+    mask_write 0XF8000750 0x00003FFF 0x00002802
+    mask_write 0XF8000754 0x00003FFF 0x00002802
+    mask_write 0XF8000758 0x00003FFF 0x00000803
+    mask_write 0XF800075C 0x00003FFF 0x00000803
+    mask_write 0XF8000760 0x00003FFF 0x00000803
+    mask_write 0XF8000764 0x00003FFF 0x00000803
+    mask_write 0XF8000768 0x00003FFF 0x00000803
+    mask_write 0XF800076C 0x00003FFF 0x00000803
+    mask_write 0XF8000770 0x00003FFF 0x00000204
+    mask_write 0XF8000774 0x00003FFF 0x00000205
+    mask_write 0XF8000778 0x00003FFF 0x00000204
+    mask_write 0XF800077C 0x00003FFF 0x00000205
+    mask_write 0XF8000780 0x00003FFF 0x00000204
+    mask_write 0XF8000784 0x00003FFF 0x00000204
+    mask_write 0XF8000788 0x00003FFF 0x00000204
+    mask_write 0XF800078C 0x00003FFF 0x00000204
+    mask_write 0XF8000790 0x00003FFF 0x00000205
+    mask_write 0XF8000794 0x00003FFF 0x00000204
+    mask_write 0XF8000798 0x00003FFF 0x00000204
+    mask_write 0XF800079C 0x00003FFF 0x00000204
+    mask_write 0XF80007A0 0x00003FFF 0x00000280
+    mask_write 0XF80007A4 0x00003FFF 0x00000280
+    mask_write 0XF80007A8 0x00003FFF 0x00000280
+    mask_write 0XF80007AC 0x00003FFF 0x00000280
+    mask_write 0XF80007B0 0x00003FFF 0x00000280
+    mask_write 0XF80007B4 0x00003FFF 0x00000280
+    mask_write 0XF80007B8 0x00003FFF 0x00001221
+    mask_write 0XF80007BC 0x00003FFF 0x00001220
+    mask_write 0XF80007C0 0x00003FFF 0x000002E0
+    mask_write 0XF80007C4 0x00003FFF 0x000002E1
+    mask_write 0XF80007C8 0x00003FFF 0x00001240
+    mask_write 0XF80007CC 0x00003FFF 0x00001240
+    mask_write 0XF80007D0 0x00003FFF 0x00000280
+    mask_write 0XF80007D4 0x00003FFF 0x00000280
+    mask_write 0XF8000830 0x003F003F 0x0000000F
+    mask_write 0XF8000004 0x0000FFFF 0x0000767B
+}
+proc ps7_peripherals_init_data_2_0 {} {
+    mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
+    mask_write 0XF8000B48 0x00000180 0x00000180
+    mask_write 0XF8000B4C 0x00000180 0x00000180
+    mask_write 0XF8000B50 0x00000180 0x00000180
+    mask_write 0XF8000B54 0x00000180 0x00000180
+    mask_write 0XF8000004 0x0000FFFF 0x0000767B
+    mask_write 0XE0001034 0x000000FF 0x00000006
+    mask_write 0XE0001018 0x0000FFFF 0x0000003E
+    mask_write 0XE0001000 0x000001FF 0x00000017
+    mask_write 0XE0001004 0x00000FFF 0x00000020
+    mask_write 0XE000D000 0x00080000 0x00080000
+    mask_write 0XF8007000 0x20000000 0x00000000
+    mask_write 0XE000A204 0xFFFFFFFF 0x00002880
+    mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080
+    mask_write 0XE000A208 0xFFFFFFFF 0x00002880
+    mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0000
+    mask_delay 0XF8F00200 1
+    mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080
+    mask_write 0XE000A204 0xFFFFFFFF 0x00002880
+    mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0800
+    mask_write 0XE000A208 0xFFFFFFFF 0x00002880
+    mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0000
+    mask_delay 0XF8F00200 1
+    mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0800
+    mask_write 0XE000A204 0xFFFFFFFF 0x00002880
+    mask_write 0XE000A000 0xFFFFFFFF 0xDFFF2000
+    mask_write 0XE000A208 0xFFFFFFFF 0x00002880
+    mask_write 0XE000A000 0xFFFFFFFF 0xDFFF0000
+    mask_delay 0XF8F00200 1
+    mask_write 0XE000A000 0xFFFFFFFF 0xDFFF2000
+}
+proc ps7_post_config_2_0 {} {
+    mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
+    mask_write 0XF8000900 0x0000000F 0x0000000F
+    mask_write 0XF8000240 0xFFFFFFFF 0x00000000
+    mask_write 0XF8000004 0x0000FFFF 0x0000767B
+}
+proc ps7_debug_2_0 {} {
+    mask_write 0XF8898FB0 0xFFFFFFFF 0xC5ACCE55
+    mask_write 0XF8899FB0 0xFFFFFFFF 0xC5ACCE55
+    mask_write 0XF8809FB0 0xFFFFFFFF 0xC5ACCE55
+}
+proc ps7_pll_init_data_1_0 {} {
+    mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
+    mask_write 0XF8000110 0x003FFFF0 0x000FA220
+    mask_write 0XF8000100 0x0007F000 0x00028000
+    mask_write 0XF8000100 0x00000010 0x00000010
+    mask_write 0XF8000100 0x00000001 0x00000001
+    mask_write 0XF8000100 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000001
+    mask_write 0XF8000100 0x00000010 0x00000000
+    mask_write 0XF8000120 0x1F003F30 0x1F000200
+    mask_write 0XF8000114 0x003FFFF0 0x0012C220
+    mask_write 0XF8000104 0x0007F000 0x00020000
+    mask_write 0XF8000104 0x00000010 0x00000010
+    mask_write 0XF8000104 0x00000001 0x00000001
+    mask_write 0XF8000104 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000002
+    mask_write 0XF8000104 0x00000010 0x00000000
+    mask_write 0XF8000124 0xFFF00003 0x0C200003
+    mask_write 0XF8000118 0x003FFFF0 0x001452C0
+    mask_write 0XF8000108 0x0007F000 0x0001E000
+    mask_write 0XF8000108 0x00000010 0x00000010
+    mask_write 0XF8000108 0x00000001 0x00000001
+    mask_write 0XF8000108 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000004
+    mask_write 0XF8000108 0x00000010 0x00000000
+    mask_write 0XF8000004 0x0000FFFF 0x0000767B
+}
+proc ps7_clock_init_data_1_0 {} {
+    mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
+    mask_write 0XF8000128 0x03F03F01 0x00302301
+    mask_write 0XF8000138 0x00000011 0x00000001
+    mask_write 0XF8000140 0x03F03F71 0x00500801
+    mask_write 0XF800014C 0x00003F31 0x00000501
+    mask_write 0XF8000150 0x00003F33 0x00001401
+    mask_write 0XF8000154 0x00003F33 0x00001402
+    mask_write 0XF800015C 0x03F03F33 0x00300E01
+    mask_write 0XF8000160 0x007F007F 0x00000000
+    mask_write 0XF8000168 0x00003F31 0x00000501
+    mask_write 0XF8000170 0x03F03F30 0x00101400
+    mask_write 0XF8000180 0x03F03F30 0x00101400
+    mask_write 0XF8000190 0x03F03F30 0x00101400
+    mask_write 0XF80001A0 0x03F03F30 0x00101400
+    mask_write 0XF80001C4 0x00000001 0x00000001
+    mask_write 0XF800012C 0x01FFCCCD 0x01ED044D
+    mask_write 0XF8000004 0x0000FFFF 0x0000767B
+}
+proc ps7_ddr_init_data_1_0 {} {
+    mask_write 0XF8006000 0x0001FFFF 0x00000080
+    mask_write 0XF8006004 0x1FFFFFFF 0x00081081
+    mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
+    mask_write 0XF800600C 0x03FFFFFF 0x02001001
+    mask_write 0XF8006010 0x03FFFFFF 0x00014001
+    mask_write 0XF8006014 0x001FFFFF 0x0004159B
+    mask_write 0XF8006018 0xF7FFFFFF 0x452440D2
+    mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
+    mask_write 0XF8006020 0xFFFFFFFC 0x27287290
+    mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
+    mask_write 0XF8006028 0x00003FFF 0x00002007
+    mask_write 0XF800602C 0xFFFFFFFF 0x00000008
+    mask_write 0XF8006030 0xFFFFFFFF 0x00040930
+    mask_write 0XF8006034 0x13FF3FFF 0x00011054
+    mask_write 0XF8006038 0x00001FC3 0x00000000
+    mask_write 0XF800603C 0x000FFFFF 0x00000777
+    mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
+    mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
+    mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
+    mask_write 0XF8006050 0xFF0F8FFF 0x77010800
+    mask_write 0XF8006058 0x0001FFFF 0x00000101
+    mask_write 0XF800605C 0x0000FFFF 0x00005003
+    mask_write 0XF8006060 0x000017FF 0x0000003E
+    mask_write 0XF8006064 0x00021FE0 0x00020000
+    mask_write 0XF8006068 0x03FFFFFF 0x00284141
+    mask_write 0XF800606C 0x0000FFFF 0x00001610
+    mask_write 0XF80060A0 0x00FFFFFF 0x00008000
+    mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
+    mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
+    mask_write 0XF80060AC 0x000001FF 0x000001FE
+    mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
+    mask_write 0XF80060B4 0x000007FF 0x00000200
+    mask_write 0XF80060B8 0x01FFFFFF 0x00200066
+    mask_write 0XF80060C4 0x00000003 0x00000003
+    mask_write 0XF80060C4 0x00000003 0x00000000
+    mask_write 0XF80060C8 0x000000FF 0x00000000
+    mask_write 0XF80060DC 0x00000001 0x00000000
+    mask_write 0XF80060F0 0x0000FFFF 0x00000000
+    mask_write 0XF80060F4 0x0000000F 0x00000008
+    mask_write 0XF8006114 0x000000FF 0x00000000
+    mask_write 0XF8006118 0x7FFFFFFF 0x40000001
+    mask_write 0XF800611C 0x7FFFFFFF 0x40000001
+    mask_write 0XF8006120 0x7FFFFFFF 0x40000001
+    mask_write 0XF8006124 0x7FFFFFFF 0x40000001
+    mask_write 0XF800612C 0x000FFFFF 0x0003C81D
+    mask_write 0XF8006130 0x000FFFFF 0x00036012
+    mask_write 0XF8006134 0x000FFFFF 0x0003780C
+    mask_write 0XF8006138 0x000FFFFF 0x0003B821
+    mask_write 0XF8006140 0x000FFFFF 0x00000035
+    mask_write 0XF8006144 0x000FFFFF 0x00000035
+    mask_write 0XF8006148 0x000FFFFF 0x00000035
+    mask_write 0XF800614C 0x000FFFFF 0x00000035
+    mask_write 0XF8006154 0x000FFFFF 0x0000009D
+    mask_write 0XF8006158 0x000FFFFF 0x00000092
+    mask_write 0XF800615C 0x000FFFFF 0x0000008C
+    mask_write 0XF8006160 0x000FFFFF 0x000000A1
+    mask_write 0XF8006168 0x001FFFFF 0x00000147
+    mask_write 0XF800616C 0x001FFFFF 0x0000012D
+    mask_write 0XF8006170 0x001FFFFF 0x00000133
+    mask_write 0XF8006174 0x001FFFFF 0x00000143
+    mask_write 0XF800617C 0x000FFFFF 0x000000DD
+    mask_write 0XF8006180 0x000FFFFF 0x000000D2
+    mask_write 0XF8006184 0x000FFFFF 0x000000CC
+    mask_write 0XF8006188 0x000FFFFF 0x000000E1
+    mask_write 0XF8006190 0xFFFFFFFF 0x10040080
+    mask_write 0XF8006194 0x000FFFFF 0x0001FC82
+    mask_write 0XF8006204 0xFFFFFFFF 0x00000000
+    mask_write 0XF8006208 0x000F03FF 0x000803FF
+    mask_write 0XF800620C 0x000F03FF 0x000803FF
+    mask_write 0XF8006210 0x000F03FF 0x000803FF
+    mask_write 0XF8006214 0x000F03FF 0x000803FF
+    mask_write 0XF8006218 0x000F03FF 0x000003FF
+    mask_write 0XF800621C 0x000F03FF 0x000003FF
+    mask_write 0XF8006220 0x000F03FF 0x000003FF
+    mask_write 0XF8006224 0x000F03FF 0x000003FF
+    mask_write 0XF80062A8 0x00000FF7 0x00000000
+    mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
+    mask_write 0XF80062B0 0x003FFFFF 0x00005125
+    mask_write 0XF80062B4 0x0003FFFF 0x000012A8
+    mask_poll 0XF8000B74 0x00002000
+    mask_write 0XF8006000 0x0001FFFF 0x00000081
+    mask_poll 0XF8006054 0x00000007
+}
+proc ps7_mio_init_data_1_0 {} {
+    mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
+    mask_write 0XF8000B00 0x00000303 0x00000001
+    mask_write 0XF8000B40 0x00000FFF 0x00000600
+    mask_write 0XF8000B44 0x00000FFF 0x00000600
+    mask_write 0XF8000B48 0x00000FFF 0x00000672
+    mask_write 0XF8000B4C 0x00000FFF 0x00000672
+    mask_write 0XF8000B50 0x00000FFF 0x00000674
+    mask_write 0XF8000B54 0x00000FFF 0x00000674
+    mask_write 0XF8000B58 0x00000FFF 0x00000600
+    mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
+    mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B6C 0x000073FF 0x00000209
+    mask_write 0XF8000B70 0x00000021 0x00000021
+    mask_write 0XF8000B70 0x00000021 0x00000020
+    mask_write 0XF8000B70 0x07FFFFFF 0x00000823
+    mask_write 0XF8000700 0x00003F01 0x00001201
+    mask_write 0XF8000704 0x00003FFF 0x00001202
+    mask_write 0XF8000708 0x00003FFF 0x00000202
+    mask_write 0XF800070C 0x00003FFF 0x00000202
+    mask_write 0XF8000710 0x00003FFF 0x00000202
+    mask_write 0XF8000714 0x00003FFF 0x00000202
+    mask_write 0XF8000718 0x00003FFF 0x00000202
+    mask_write 0XF800071C 0x00003FFF 0x00000200
+    mask_write 0XF8000720 0x00003FFF 0x00000202
+    mask_write 0XF8000724 0x00003FFF 0x00001200
+    mask_write 0XF8000728 0x00003FFF 0x00001200
+    mask_write 0XF800072C 0x00003FFF 0x00001200
+    mask_write 0XF8000730 0x00003FFF 0x00001200
+    mask_write 0XF8000734 0x00003FFF 0x00001200
+    mask_write 0XF8000738 0x00003FFF 0x00001200
+    mask_write 0XF800073C 0x00003F01 0x00001201
+    mask_write 0XF8000740 0x00003FFF 0x00002802
+    mask_write 0XF8000744 0x00003FFF 0x00002802
+    mask_write 0XF8000748 0x00003FFF 0x00002802
+    mask_write 0XF800074C 0x00003FFF 0x00002802
+    mask_write 0XF8000750 0x00003FFF 0x00002802
+    mask_write 0XF8000754 0x00003FFF 0x00002802
+    mask_write 0XF8000758 0x00003FFF 0x00000803
+    mask_write 0XF800075C 0x00003FFF 0x00000803
+    mask_write 0XF8000760 0x00003FFF 0x00000803
+    mask_write 0XF8000764 0x00003FFF 0x00000803
+    mask_write 0XF8000768 0x00003FFF 0x00000803
+    mask_write 0XF800076C 0x00003FFF 0x00000803
+    mask_write 0XF8000770 0x00003FFF 0x00000204
+    mask_write 0XF8000774 0x00003FFF 0x00000205
+    mask_write 0XF8000778 0x00003FFF 0x00000204
+    mask_write 0XF800077C 0x00003FFF 0x00000205
+    mask_write 0XF8000780 0x00003FFF 0x00000204
+    mask_write 0XF8000784 0x00003FFF 0x00000204
+    mask_write 0XF8000788 0x00003FFF 0x00000204
+    mask_write 0XF800078C 0x00003FFF 0x00000204
+    mask_write 0XF8000790 0x00003FFF 0x00000205
+    mask_write 0XF8000794 0x00003FFF 0x00000204
+    mask_write 0XF8000798 0x00003FFF 0x00000204
+    mask_write 0XF800079C 0x00003FFF 0x00000204
+    mask_write 0XF80007A0 0x00003FFF 0x00000280
+    mask_write 0XF80007A4 0x00003FFF 0x00000280
+    mask_write 0XF80007A8 0x00003FFF 0x00000280
+    mask_write 0XF80007AC 0x00003FFF 0x00000280
+    mask_write 0XF80007B0 0x00003FFF 0x00000280
+    mask_write 0XF80007B4 0x00003FFF 0x00000280
+    mask_write 0XF80007B8 0x00003FFF 0x00001221
+    mask_write 0XF80007BC 0x00003FFF 0x00001220
+    mask_write 0XF80007C0 0x00003FFF 0x000002E0
+    mask_write 0XF80007C4 0x00003FFF 0x000002E1
+    mask_write 0XF80007C8 0x00003FFF 0x00001240
+    mask_write 0XF80007CC 0x00003FFF 0x00001240
+    mask_write 0XF80007D0 0x00003FFF 0x00000280
+    mask_write 0XF80007D4 0x00003FFF 0x00000280
+    mask_write 0XF8000830 0x003F003F 0x0000000F
+    mask_write 0XF8000004 0x0000FFFF 0x0000767B
+}
+proc ps7_peripherals_init_data_1_0 {} {
+    mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
+    mask_write 0XF8000B48 0x00000180 0x00000180
+    mask_write 0XF8000B4C 0x00000180 0x00000180
+    mask_write 0XF8000B50 0x00000180 0x00000180
+    mask_write 0XF8000B54 0x00000180 0x00000180
+    mask_write 0XF8000004 0x0000FFFF 0x0000767B
+    mask_write 0XE0001034 0x000000FF 0x00000006
+    mask_write 0XE0001018 0x0000FFFF 0x0000003E
+    mask_write 0XE0001000 0x000001FF 0x00000017
+    mask_write 0XE0001004 0x00000FFF 0x00000020
+    mask_write 0XE000D000 0x00080000 0x00080000
+    mask_write 0XF8007000 0x20000000 0x00000000
+    mask_write 0XE000A204 0xFFFFFFFF 0x00002880
+    mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080
+    mask_write 0XE000A208 0xFFFFFFFF 0x00002880
+    mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0000
+    mask_delay 0XF8F00200 1
+    mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080
+    mask_write 0XE000A204 0xFFFFFFFF 0x00002880
+    mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0800
+    mask_write 0XE000A208 0xFFFFFFFF 0x00002880
+    mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0000
+    mask_delay 0XF8F00200 1
+    mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0800
+    mask_write 0XE000A204 0xFFFFFFFF 0x00002880
+    mask_write 0XE000A000 0xFFFFFFFF 0xDFFF2000
+    mask_write 0XE000A208 0xFFFFFFFF 0x00002880
+    mask_write 0XE000A000 0xFFFFFFFF 0xDFFF0000
+    mask_delay 0XF8F00200 1
+    mask_write 0XE000A000 0xFFFFFFFF 0xDFFF2000
+}
+proc ps7_post_config_1_0 {} {
+    mask_write 0XF8000008 0x0000FFFF 0x0000DF0D
+    mask_write 0XF8000900 0x0000000F 0x0000000F
+    mask_write 0XF8000240 0xFFFFFFFF 0x00000000
+    mask_write 0XF8000004 0x0000FFFF 0x0000767B
+}
+proc ps7_debug_1_0 {} {
+    mask_write 0XF8898FB0 0xFFFFFFFF 0xC5ACCE55
+    mask_write 0XF8899FB0 0xFFFFFFFF 0xC5ACCE55
+    mask_write 0XF8809FB0 0xFFFFFFFF 0xC5ACCE55
+}
+set PCW_SILICON_VER_1_0 "0x0"
+set PCW_SILICON_VER_2_0 "0x1"
+set PCW_SILICON_VER_3_0 "0x2"
+set APU_FREQ  666666666
+
+
+
+proc mask_poll { addr mask } {
+    set count 1
+    set curval "0x[string range [mrd $addr] end-8 end]"
+    set maskedval [expr {$curval & $mask}]
+    while { $maskedval == 0 } {
+        set curval "0x[string range [mrd $addr] end-8 end]"
+        set maskedval [expr {$curval & $mask}]
+        set count [ expr { $count + 1 } ]
+        if { $count == 100000000 } {
+          puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
+          break
+        }
+    }
+}
+
+
+
+proc mask_delay { addr val } {
+    set delay  [ get_number_of_cycles_for_delay $val ]
+    perf_reset_and_start_timer
+    set curval "0x[string range [mrd $addr] end-8 end]"
+    set maskedval [expr {$curval < $delay}]
+    while { $maskedval == 1 } {
+        set curval "0x[string range [mrd $addr] end-8 end]"
+        set maskedval [expr {$curval < $delay}]
+    }
+    perf_reset_clock 
+}
+
+proc ps_version { } {
+    set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
+    set mask_sil_ver "0x[expr {$si_ver >> 28}]"
+    return $mask_sil_ver;
+}
+
+proc ps7_post_config {} {
+    variable PCW_SILICON_VER_1_0
+    variable PCW_SILICON_VER_2_0
+    variable PCW_SILICON_VER_3_0
+    set sil_ver [ps_version]
+
+    if { $sil_ver == $PCW_SILICON_VER_1_0} {
+        ps7_post_config_1_0   
+    } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
+        ps7_post_config_2_0   
+    } else {
+        ps7_post_config_3_0   
+    }
+}
+
+proc ps7_debug {} {
+    variable PCW_SILICON_VER_1_0
+    variable PCW_SILICON_VER_2_0
+    variable PCW_SILICON_VER_3_0
+    set sil_ver [ps_version]
+
+    if { $sil_ver == $PCW_SILICON_VER_1_0} {
+        ps7_debug_1_0   
+    } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
+        ps7_debug_2_0   
+    } else {
+        ps7_debug_3_0   
+    }
+}
+
+proc ps7_init {} {
+    variable PCW_SILICON_VER_1_0
+    variable PCW_SILICON_VER_2_0
+    variable PCW_SILICON_VER_3_0
+    set sil_ver [ps_version]
+
+    if { $sil_ver == $PCW_SILICON_VER_1_0} {
+            ps7_mio_init_data_1_0
+            ps7_pll_init_data_1_0
+            ps7_clock_init_data_1_0
+            ps7_ddr_init_data_1_0
+            ps7_peripherals_init_data_1_0
+            #puts "PCW Silicon Version : 1.0"
+    } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
+            ps7_mio_init_data_2_0
+            ps7_pll_init_data_2_0
+            ps7_clock_init_data_2_0
+            ps7_ddr_init_data_2_0
+            ps7_peripherals_init_data_2_0
+            #puts "PCW Silicon Version : 2.0"
+    } else {
+            ps7_mio_init_data_3_0
+            ps7_pll_init_data_3_0
+            ps7_clock_init_data_3_0
+            ps7_ddr_init_data_3_0
+            ps7_peripherals_init_data_3_0
+            #puts "PCW Silicon Version : 3.0"
+    }
+}
+
+
+# For delay calculation using global timer 
+
+# start timer 
+ proc perf_start_clock { } {
+
+    #writing SCU_GLOBAL_TIMER_CONTROL register
+
+    mask_write 0xF8F00208 0x00000109 0x00000009
+}
+
+# stop timer and reset timer count regs 
+ proc perf_reset_clock { } {
+	perf_disable_clock
+    mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
+    mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
+}
+
+# Compute mask for given delay in miliseconds
+proc get_number_of_cycles_for_delay { delay } {
+
+  # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
+  variable APU_FREQ
+  return [ expr ($delay * $APU_FREQ /(2 * 1000))]
+}
+
+
+# stop timer 
+proc perf_disable_clock {} {
+    mask_write 0xF8F00208 0xFFFFFFFF 0x00000000 
+}
+
+proc perf_reset_and_start_timer {} {
+  	    perf_reset_clock 
+	    perf_start_clock 
+}
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/system.xml b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/system.xml
new file mode 100644
index 000000000..3a27714b1
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/system.xml
@@ -0,0 +1,7184 @@
+
+
+
+  
+
+  
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+    
+  
+
+  
+    
+      
+        
+        
+        
+      
+      
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+            
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+        
+          
+            
+          
+        
+        
+          
+            
+            
+          
+        
+        
+          
+            
+            
+          
+        
+        
+          
+            
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+        
+        
+      
+      
+        
+          
+            
+          
+        
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+      
+      
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+        
+      
+      
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+        
+        
+        
+      
+      
+        
+          
+            
+          
+        
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+      
+      
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+        
+        
+        
+      
+      
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+      
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+      
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      
+        
+        
+        
+        
+        
+        
+      
+      
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+      
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+      
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+    
+    
+      
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+      
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+      
+        
+          
+            
+          
+        
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+        
+      
+      
+        
+          
+            
+          
+        
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+        
+        
+        
+        
+      
+      
+        
+          
+            
+          
+        
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+        
+        
+        
+      
+      
+        
+          
+            
+          
+        
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+        
+      
+      
+        
+          
+            
+          
+        
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+      
+        
+          
+            
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+        
+        
+      
+      
+        
+          
+            
+          
+        
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+        
+      
+      
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+      
+      
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+      
+      
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+      
+      
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+      
+      
+        
+          
+            
+          
+        
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+      
+      
+        
+          
+            
+          
+        
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+        
+      
+      
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+      
+      
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+      
+      
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+      
+      
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+        
+        
+        
+      
+      
+        
+        
+        
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+      
+      
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+      
+      
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+      
+      
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+        
+      
+      
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+      
+      
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+      
+      
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+      
+      
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+      
+      
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+    
+      
+        
+        
+        
+      
+      
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+        
+          
+            
+          
+        
+      
+      
+        
+          
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+    
+    
+  
+
+  
+
+
-- 
2.39.2