From 5fd911e4d2fe8d365a5a3ed051538cd57c2550d2 Mon Sep 17 00:00:00 2001 From: rtel Date: Wed, 23 Sep 2015 12:16:10 +0000 Subject: [PATCH] FreeRTOS source: + Added Renesas RXv2 port for IAR. Demo apps: + Demo/Rename the CORTEX_R4F_T_GCC_IAR_ARM directory to just Rename the CORTEX_R4F_T_GCC_IAR. + Add IAR project for the RX113. + Add RX231 e2studio projects for the RX231. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2380 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- .../.HardwareDebuglinker | 0 .../.Releaselinker | 0 .../.cproject | 0 .../.info | 0 .../.project | 0 .../Dependency_Scan_Preferences.prefs | 0 .../Project_Generation_Prefrences.prefs | 0 .../.settings/language.settings.xml | 0 .../RTOSDemo HardwareDebug.jlink | 0 .../RTOSDemo HardwareDebug.launch | 87 + .../Demo/CORTEX_R4F_RZ_T_GCC_IAR/RTOSDemo.ewd | 2741 + .../Demo/CORTEX_R4F_RZ_T_GCC_IAR/RTOSDemo.ewp | 2095 + .../Demo/CORTEX_R4F_RZ_T_GCC_IAR/RTOSDemo.eww | 10 + .../System/GCC/GNU_LINKER_ATCM.ld | 0 .../System/GCC/asm/loader_init.asm | 0 .../System/GCC/asm/start.asm | 0 .../System/GCC/asm/vector.asm | 0 .../System/GCC/inc/ascii.h | 0 .../System/GCC/inc/compiler_settings.h | 0 .../System/GCC/inc/gnu_io.h | 0 .../System/GCC/inc/lcd_pmod.h | 0 .../System/GCC/inc/logo_data.h | 0 .../System/GCC/inc/r_atcm_init.h | 0 .../System/GCC/inc/r_bsc.h | 0 .../System/GCC/inc/r_ram_init.h | 0 .../System/GCC/inc/r_reset.h | 0 .../System/GCC/inc/r_system.h | 0 .../System/GCC/inc/r_typedefs.h | 0 .../System/GCC/inc/siochar.h | 0 .../System/GCC/src/loader_init2.c | 0 .../System/GCC/src/r_atcm_init.c | 0 .../System/GCC/src/r_ram_init.c | 0 .../System/GCC/src/r_reset.c | 0 .../System/IAR/Interrupt_Entry_Stubs.asm | 0 .../System/IAR/RZT1_init_RAM.mac | 0 .../System/IAR/RZ_T1_init.icf | 0 .../System/IAR/inc/r_atcm_init.h | 0 .../System/IAR/inc/r_bsc.h | 0 .../System/IAR/inc/r_cpg.h | 0 .../System/IAR/inc/r_ecm.h | 0 .../System/IAR/inc/r_icu_init.h | 0 .../System/IAR/inc/r_mpc.h | 0 .../System/IAR/inc/r_port.h | 0 .../System/IAR/inc/r_ram_init.h | 0 .../System/IAR/inc/r_reset.h | 0 .../System/IAR/inc/r_system.h | 0 .../System/IAR/inc/r_typedefs.h | 0 .../System/IAR/src/RZ_T1_init.icf | 0 .../System/IAR/src/exit.c | 0 .../System/IAR/src/loader_init.asm | 0 .../System/IAR/src/loader_init2.c | 0 .../System/IAR/src/r_atcm_init.c | 0 .../System/IAR/src/r_cpg.c | 0 .../System/IAR/src/r_ecm.c | 0 .../System/IAR/src/r_icu_init.c | 0 .../System/IAR/src/r_ram_init.c | 0 .../System/IAR/src/r_reset.c | 0 .../System/IAR/src/vector.asm | 0 .../makefile.init | 0 .../settings/RTOSDemo.Debug.cspy.bat | 40 + .../settings/RTOSDemo.Debug.driver.xcl | 43 + .../settings/RTOSDemo.Debug.general.xcl | 15 + .../settings/RTOSDemo.crun | 16 + .../settings/RTOSDemo.dbgdt | 277 + .../settings/RTOSDemo.dni | 112 + .../settings/RTOSDemo.wsdt | 89 + .../settings/RTOSDemo.wspos | 2 + .../src/Blinky_Demo/main_blinky.c | 0 .../src/FreeRTOSConfig.h | 0 .../src/FreeRTOS_tick_config.c | 0 .../src/Full_Demo/IntQueueTimer.c | 0 .../src/Full_Demo/IntQueueTimer.h | 0 .../src/Full_Demo/main_full.c | 0 .../src/Full_Demo/reg_test_GCC.S | 0 .../src/Full_Demo/reg_test_IAR.asm | 0 .../src/cg_src/iodefine.h | 0 .../src/cg_src/r_cg_cgc.c | 0 .../src/cg_src/r_cg_cgc.h | 0 .../src/cg_src/r_cg_cgc_user.c | 0 .../src/cg_src/r_cg_cmt.h | 0 .../src/cg_src/r_cg_cmt_user.c | 0 .../src/cg_src/r_cg_icu.c | 0 .../src/cg_src/r_cg_icu.h | 0 .../src/cg_src/r_cg_icu_user.c | 0 .../src/cg_src/r_cg_interrupthandlers.h | 0 .../src/cg_src/r_cg_intprg.c | 0 .../src/cg_src/r_cg_macrodriver.h | 0 .../src/cg_src/r_cg_mpc.c | 0 .../src/cg_src/r_cg_mpc.h | 0 .../src/cg_src/r_cg_port.c | 0 .../src/cg_src/r_cg_port.h | 0 .../src/cg_src/r_cg_port_user.c | 0 .../src/cg_src/r_cg_rspi.c | 0 .../src/cg_src/r_cg_rspi.h | 0 .../src/cg_src/r_cg_rspi_user.c | 0 .../src/cg_src/r_cg_systeminit.c | 0 .../src/cg_src/r_cg_tpu.c | 0 .../src/cg_src/r_cg_tpu.h | 0 .../src/cg_src/r_cg_tpu_user.c | 0 .../src/cg_src/r_cg_userdefine.h | 0 .../src/main.c | 0 .../nbproject/Makefile-default.mk | 208 +- .../nbproject/Makefile-genesis.properties | 4 +- .../nbproject/configurations.xml | 2 +- .../nbproject/private/private.xml | 13 +- .../Demo/RX113-RSK_GCC_e2studio_IAR/.cproject | 11 +- .../Demo/RX113-RSK_GCC_e2studio_IAR/.project | 11 +- .../.settings/language.settings.xml | 2 +- .../RX113-RSK_GCC_e2studio_IAR/RTOSDemo.ewd | 771 + .../RX113-RSK_GCC_e2studio_IAR/RTOSDemo.ewp | 2044 + .../RX113-RSK_GCC_e2studio_IAR/RTOSDemo.eww | 10 + .../settings/RTOSDemo.Debug.cspy.bat | 40 + .../settings/RTOSDemo.Debug.driver.xcl | 39 + .../settings/RTOSDemo.Debug.general.xcl | 11 + .../settings/RTOSDemo.dbgdt | 244 + .../settings/RTOSDemo.dni | 250 + .../settings/RTOSDemo.wsdt | 77 + .../settings/RTOSDemo.wspos | 2 + .../src/FreeRTOSConfig.h | 10 +- .../src/Full_Demo/IntQueueTimer.c | 57 +- .../Full_Demo/{RegTest.S => RegTest_GCC.S} | 0 .../src/Full_Demo/RegTest_IAR.s | 269 + .../src/PriorityDefinitions.h | 86 + .../src/cg_src/r_cg_macrodriver.h | 8 +- .../RX113-RSK_GCC_e2studio_IAR/src/main.c | 23 +- .../.HardwareDebuglinker | 148 + .../.cproject | 161 + .../RX200_RX231-RSK_GCC_e2studio_IAR/.info | 7 + .../RX200_RX231-RSK_GCC_e2studio_IAR/.project | 232 + .../.settings/CodeGenerator/cgproject.cgp | 184968 +++++++++++++++ .../CodeGenerator/cgprojectDatas.datas | 3 + .../Dependency_Scan_Preferences.prefs | 4 + .../Project_Generation_Prefrences.prefs | 24 + .../.settings/language.settings.xml | 13 + .../RTOSDemo HardwareDebug.launch} | 49 +- .../custom.bat} | 0 .../RX200_RX231-RSK_GCC_e2studio_IAR/main.c | 5 + .../makefile.init | 5 + .../src/Blinky_Demo/main_blinky.c | 230 + .../src/FreeRTOSConfig.h | 182 + .../src/Main_Full/IntQueueTimer.c | 187 + .../src/Main_Full/IntQueueTimer.h | 78 + .../src/Main_Full/RegTest_GCC.S | 235 + .../src/Main_Full/main_full.c | 499 + .../src/Renesas_Code/interrupt_handlers.c | 554 + .../src/Renesas_Code/interrupt_handlers.h | 839 + .../src/Renesas_Code/typedefine.h | 28 + .../src/Renesas_Code/vector_table.c | 632 + .../src/cg_src/r_cg_cgc.c | 115 + .../src/cg_src/r_cg_cgc.h | 227 + .../src/cg_src/r_cg_cgc_user.c | 52 + .../src/cg_src/r_cg_hardware_setup.c | 92 + .../src/cg_src/r_cg_interrupt_handlers.h | 72 + .../src/cg_src/r_cg_macrodriver.h | 98 + .../src/cg_src/r_cg_main.c | 90 + .../src/cg_src/r_cg_reset_program.asm | 195 + .../src/cg_src/r_cg_userdefine.h | 37 + .../src/cg_src/r_cg_vector_table.c | 467 + .../src/iodefine.h | 22195 ++ .../src/main.c | 251 + .../.HardwareDebuglinker | 35 + .../.cproject | 157 + .../RX200_RX231-RSK_Renesas_e2studio/.info | 6 + .../RX200_RX231-RSK_Renesas_e2studio/.project | 232 + .../.settings/CodeGenerator/cgproject.cgp | 182288 ++++++++++++++ .../CodeGenerator/cgprojectDatas.datas | 3 + .../Dependency_Scan_Preferences.prefs | 4 + .../Project_Generation_Prefrences.prefs | 54 + .../RTOSDemo HardwareDebug.launch | 101 + .../custom.bat | 0 .../makefile.init | 8 + .../src/Blinky_Demo/main_blinky.c | 230 + .../src/FreeRTOSConfig.h | 182 + .../src/Full_Demo/IntQueueTimer.c | 162 + .../src/Full_Demo/IntQueueTimer.h | 78 + .../src/Full_Demo/main_full.c | 668 + .../src/Renesas_Code/stacksct.h | 13 + .../src/Renesas_Code/typedefine.h | 42 + .../src/Renesas_Code/vect.h | 849 + .../src/cg_src/r_cg_cgc.c | 115 + .../src/cg_src/r_cg_cgc.h | 227 + .../src/cg_src/r_cg_cgc_user.c | 52 + .../src/cg_src/r_cg_dbsct.c | 84 + .../src/cg_src/r_cg_hardware_setup.c | 87 + .../src/cg_src/r_cg_intprg.c | 99 + .../src/cg_src/r_cg_macrodriver.h | 100 + .../src/cg_src/r_cg_main.c | 90 + .../src/cg_src/r_cg_resetprg.c | 94 + .../src/cg_src/r_cg_sbrk.c | 86 + .../src/cg_src/r_cg_sbrk.h | 48 + .../src/cg_src/r_cg_stacksct.h | 50 + .../src/cg_src/r_cg_userdefine.h | 38 + .../src/cg_src/r_cg_vect.h | 79 + .../src/cg_src/r_cg_vecttbl.c | 130 + .../src/iodefine.h | 12985 + .../src/main.c | 251 + .../.cproject | 8 +- .../RX700_RX71M_RSK_GCC_e2studio_IAR/.project | 18 + .../.settings/language.settings.xml | 2 +- .../RTOSDemo.ewd | 771 + .../RTOSDemo.ewp | 2050 + .../RTOSDemo.eww | 10 + .../settings/RTOSDemo.Debug.cspy.bat | 40 + .../settings/RTOSDemo.Debug.driver.xcl | 37 + .../settings/RTOSDemo.Debug.general.xcl | 11 + .../settings/RTOSDemo.dbgdt | 244 + .../settings/RTOSDemo.dni | 250 + .../settings/RTOSDemo.wsdt | 77 + .../settings/RTOSDemo.wspos | 2 + .../src/FreeRTOSConfig.h | 11 +- .../src/Full_Demo/IntQueueTimer.c | 85 +- .../Full_Demo/{RegTest.S => RegTest_GCC.S} | 0 .../src/Full_Demo/RegTest_IAR.s | 304 + .../src/PriorityDefinitions.h | 86 + .../src/cg_src/r_cg_macrodriver.h | 18 +- .../src/cg_src/r_cg_sci.c | 12 +- .../src/cg_src/r_cg_sci_user_iar.c | 241 + .../src/main.c | 17 + .../src/FreeRTOSConfig.h | 2 +- .../Source/portable/IAR/RX100/portmacro.h | 5 + FreeRTOS/Source/portable/IAR/RXv2/port.c | 244 + FreeRTOS/Source/portable/IAR/RXv2/port_asm.s | 242 + FreeRTOS/Source/portable/IAR/RXv2/portmacro.h | 186 + FreeRTOS/Source/portable/MemMang/heap_4.c | 2 +- FreeRTOS/Source/tasks.c | 1 - 225 files changed, 427176 insertions(+), 220 deletions(-) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/.HardwareDebuglinker (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/.Releaselinker (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/.cproject (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/.info (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/.project (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/.settings/Dependency_Scan_Preferences.prefs (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/.settings/Project_Generation_Prefrences.prefs (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/.settings/language.settings.xml (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/RTOSDemo HardwareDebug.jlink (100%) create mode 100644 FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/RTOSDemo HardwareDebug.launch create mode 100644 FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/RTOSDemo.ewd create mode 100644 FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/RTOSDemo.ewp create mode 100644 FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/RTOSDemo.eww rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/GCC/GNU_LINKER_ATCM.ld (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/GCC/asm/loader_init.asm (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/GCC/asm/start.asm (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/GCC/asm/vector.asm (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/GCC/inc/ascii.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/GCC/inc/compiler_settings.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/GCC/inc/gnu_io.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/GCC/inc/lcd_pmod.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/GCC/inc/logo_data.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/GCC/inc/r_atcm_init.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/GCC/inc/r_bsc.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/GCC/inc/r_ram_init.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/GCC/inc/r_reset.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/GCC/inc/r_system.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/GCC/inc/r_typedefs.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/GCC/inc/siochar.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/GCC/src/loader_init2.c (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/GCC/src/r_atcm_init.c (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/GCC/src/r_ram_init.c (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/GCC/src/r_reset.c (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/IAR/Interrupt_Entry_Stubs.asm (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/IAR/RZT1_init_RAM.mac (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/IAR/RZ_T1_init.icf (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/IAR/inc/r_atcm_init.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/IAR/inc/r_bsc.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/IAR/inc/r_cpg.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/IAR/inc/r_ecm.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/IAR/inc/r_icu_init.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/IAR/inc/r_mpc.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/IAR/inc/r_port.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/IAR/inc/r_ram_init.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/IAR/inc/r_reset.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/IAR/inc/r_system.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/IAR/inc/r_typedefs.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/IAR/src/RZ_T1_init.icf (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/IAR/src/exit.c (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/IAR/src/loader_init.asm (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/IAR/src/loader_init2.c (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/IAR/src/r_atcm_init.c (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/IAR/src/r_cpg.c (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/IAR/src/r_ecm.c (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/IAR/src/r_icu_init.c (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/IAR/src/r_ram_init.c (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/IAR/src/r_reset.c (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/System/IAR/src/vector.asm (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/makefile.init (100%) create mode 100644 FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.Debug.cspy.bat create mode 100644 FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.Debug.driver.xcl create mode 100644 FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.Debug.general.xcl create mode 100644 FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.crun create mode 100644 FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.dbgdt create mode 100644 FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.dni create mode 100644 FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.wsdt create mode 100644 FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.wspos rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/src/Blinky_Demo/main_blinky.c (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/src/FreeRTOSConfig.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/src/FreeRTOS_tick_config.c (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/src/Full_Demo/IntQueueTimer.c (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/src/Full_Demo/IntQueueTimer.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/src/Full_Demo/main_full.c (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/src/Full_Demo/reg_test_GCC.S (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/src/Full_Demo/reg_test_IAR.asm (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/src/cg_src/iodefine.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/src/cg_src/r_cg_cgc.c (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/src/cg_src/r_cg_cgc.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/src/cg_src/r_cg_cgc_user.c (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/src/cg_src/r_cg_cmt.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/src/cg_src/r_cg_cmt_user.c (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/src/cg_src/r_cg_icu.c (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/src/cg_src/r_cg_icu.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/src/cg_src/r_cg_icu_user.c (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/src/cg_src/r_cg_interrupthandlers.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/src/cg_src/r_cg_intprg.c (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/src/cg_src/r_cg_macrodriver.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/src/cg_src/r_cg_mpc.c (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/src/cg_src/r_cg_mpc.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/src/cg_src/r_cg_port.c (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/src/cg_src/r_cg_port.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/src/cg_src/r_cg_port_user.c (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/src/cg_src/r_cg_rspi.c (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/src/cg_src/r_cg_rspi.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/src/cg_src/r_cg_rspi_user.c (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/src/cg_src/r_cg_systeminit.c (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/src/cg_src/r_cg_tpu.c (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/src/cg_src/r_cg_tpu.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/src/cg_src/r_cg_tpu_user.c (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/src/cg_src/r_cg_userdefine.h (100%) rename FreeRTOS/Demo/{CORTEX_R4F_RZ_T_GCC_IAR_ARM => CORTEX_R4F_RZ_T_GCC_IAR}/src/main.c (100%) create mode 100644 FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/RTOSDemo.ewd create mode 100644 FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/RTOSDemo.ewp create mode 100644 FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/RTOSDemo.eww create mode 100644 FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.cspy.bat create mode 100644 FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.driver.xcl create mode 100644 FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.general.xcl create mode 100644 FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.dbgdt create mode 100644 FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.dni create mode 100644 FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.wsdt create mode 100644 FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.wspos rename FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/{RegTest.S => RegTest_GCC.S} (100%) create mode 100644 FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest_IAR.s create mode 100644 FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/PriorityDefinitions.h create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.HardwareDebuglinker create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.cproject create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.info create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.project create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.settings/CodeGenerator/cgproject.cgp create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.settings/CodeGenerator/cgprojectDatas.datas create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.settings/Dependency_Scan_Preferences.prefs create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.settings/Project_Generation_Prefrences.prefs create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.settings/language.settings.xml rename FreeRTOS/Demo/{RX100-RSK_GCC_e2studio/RTOSDemo_GCC.launch => RX200_RX231-RSK_GCC_e2studio_IAR/RTOSDemo HardwareDebug.launch} (65%) rename FreeRTOS/Demo/{RX700_RX71M_RSK_GCC_e2studio_IAR/RTOSDemo/.settings/CodeGenerator/cgprojectDatas.datas => RX200_RX231-RSK_GCC_e2studio_IAR/custom.bat} (100%) create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/main.c create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/makefile.init create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Blinky_Demo/main_blinky.c create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Main_Full/IntQueueTimer.c create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Main_Full/IntQueueTimer.h create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Main_Full/RegTest_GCC.S create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Main_Full/main_full.c create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Renesas_Code/interrupt_handlers.c create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Renesas_Code/interrupt_handlers.h create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Renesas_Code/typedefine.h create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Renesas_Code/vector_table.c create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc.c create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc.h create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc_user.c create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_hardware_setup.c create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_interrupt_handlers.h create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_macrodriver.h create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_main.c create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_reset_program.asm create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_userdefine.h create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_vector_table.c create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/iodefine.h create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/main.c create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.HardwareDebuglinker create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.cproject create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.info create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.project create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.settings/CodeGenerator/cgproject.cgp create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.settings/CodeGenerator/cgprojectDatas.datas create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.settings/Dependency_Scan_Preferences.prefs create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.settings/Project_Generation_Prefrences.prefs create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/RTOSDemo HardwareDebug.launch create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/custom.bat create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/makefile.init create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Blinky_Demo/main_blinky.c create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/FreeRTOSConfig.h create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.c create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.h create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Full_Demo/main_full.c create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Renesas_Code/stacksct.h create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Renesas_Code/typedefine.h create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Renesas_Code/vect.h create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_cgc.c create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_cgc.h create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_cgc_user.c create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_dbsct.c create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_hardware_setup.c create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_intprg.c create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_macrodriver.h create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_main.c create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_resetprg.c create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_sbrk.c create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_sbrk.h create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_stacksct.h create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_userdefine.h create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_vect.h create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_vecttbl.c create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/iodefine.h create mode 100644 FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/main.c create mode 100644 FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/RTOSDemo.ewd create mode 100644 FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/RTOSDemo.ewp create mode 100644 FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/RTOSDemo.eww create mode 100644 FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.cspy.bat create mode 100644 FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.driver.xcl create mode 100644 FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.general.xcl create mode 100644 FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.dbgdt create mode 100644 FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.dni create mode 100644 FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.wsdt create mode 100644 FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.wspos rename FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/{RegTest.S => RegTest_GCC.S} (100%) create mode 100644 FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest_IAR.s create mode 100644 FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/PriorityDefinitions.h create mode 100644 FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sci_user_iar.c create mode 100644 FreeRTOS/Source/portable/IAR/RXv2/port.c create mode 100644 FreeRTOS/Source/portable/IAR/RXv2/port_asm.s create mode 100644 FreeRTOS/Source/portable/IAR/RXv2/portmacro.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.HardwareDebuglinker b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.HardwareDebuglinker similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.HardwareDebuglinker rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.HardwareDebuglinker diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.Releaselinker b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.Releaselinker similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.Releaselinker rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.Releaselinker diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.cproject b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.cproject similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.cproject rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.cproject diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.info b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.info similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.info rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.info diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.project b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.project similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.project rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.project diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.settings/Dependency_Scan_Preferences.prefs b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.settings/Dependency_Scan_Preferences.prefs similarity index 100% rename from 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HardwareDebug.jlink b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/RTOSDemo HardwareDebug.jlink similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/RTOSDemo HardwareDebug.jlink rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/RTOSDemo HardwareDebug.jlink diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/RTOSDemo HardwareDebug.launch b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/RTOSDemo HardwareDebug.launch new file mode 100644 index 000000000..f652b92fd --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/RTOSDemo HardwareDebug.launch @@ -0,0 +1,87 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/RTOSDemo.ewd b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/RTOSDemo.ewd new file mode 100644 index 000000000..18d232e4a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/RTOSDemo.ewd @@ -0,0 +1,2741 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$PROJ_DIR$\System\IAR\src\r_reset.c + + + $PROJ_DIR$\System\IAR\src\vector.asm + + + + $PROJ_DIR$\src\FreeRTOS_tick_config.c + + + $PROJ_DIR$\src\FreeRTOSConfig.h + + + $PROJ_DIR$\System\IAR\Interrupt_Entry_Stubs.asm + + + $PROJ_DIR$\src\main.c + + + $PROJ_DIR$\src\cg_src\r_cg_cgc.c + + + $PROJ_DIR$\src\cg_src\r_cg_mpc.c + + + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/RTOSDemo.eww b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/RTOSDemo.eww new file mode 100644 index 000000000..239a9381e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/RTOSDemo.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\RTOSDemo.ewp + + + + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/GNU_LINKER_ATCM.ld b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/GNU_LINKER_ATCM.ld similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/GNU_LINKER_ATCM.ld rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/GNU_LINKER_ATCM.ld diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/asm/loader_init.asm b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/asm/loader_init.asm similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/asm/loader_init.asm rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/asm/loader_init.asm diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/asm/start.asm b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/asm/start.asm similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/asm/start.asm rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/asm/start.asm diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/asm/vector.asm b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/asm/vector.asm similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/asm/vector.asm rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/asm/vector.asm diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/ascii.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/ascii.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/ascii.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/ascii.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/compiler_settings.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/compiler_settings.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/compiler_settings.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/compiler_settings.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/gnu_io.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/gnu_io.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/gnu_io.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/gnu_io.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/lcd_pmod.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/lcd_pmod.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/lcd_pmod.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/lcd_pmod.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/logo_data.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/logo_data.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/logo_data.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/logo_data.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_atcm_init.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/r_atcm_init.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_atcm_init.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/r_atcm_init.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_bsc.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/r_bsc.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_bsc.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/r_bsc.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_ram_init.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/r_ram_init.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_ram_init.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/r_ram_init.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_reset.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/r_reset.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_reset.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/r_reset.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_system.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/r_system.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_system.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/r_system.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_typedefs.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/r_typedefs.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_typedefs.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/r_typedefs.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/siochar.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/siochar.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/siochar.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/siochar.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/src/loader_init2.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/src/loader_init2.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/src/loader_init2.c rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/src/loader_init2.c diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/src/r_atcm_init.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/src/r_atcm_init.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/src/r_atcm_init.c rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/src/r_atcm_init.c diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/src/r_ram_init.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/src/r_ram_init.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/src/r_ram_init.c rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/src/r_ram_init.c diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/src/r_reset.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/src/r_reset.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/src/r_reset.c rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/src/r_reset.c diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/Interrupt_Entry_Stubs.asm b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/Interrupt_Entry_Stubs.asm similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/Interrupt_Entry_Stubs.asm rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/Interrupt_Entry_Stubs.asm diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/RZT1_init_RAM.mac b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/RZT1_init_RAM.mac similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/RZT1_init_RAM.mac rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/RZT1_init_RAM.mac diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/RZ_T1_init.icf b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/RZ_T1_init.icf similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/RZ_T1_init.icf rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/RZ_T1_init.icf diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_atcm_init.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_atcm_init.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_atcm_init.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_atcm_init.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_bsc.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_bsc.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_bsc.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_bsc.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_cpg.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_cpg.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_cpg.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_cpg.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_ecm.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_ecm.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_ecm.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_ecm.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_icu_init.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_icu_init.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_icu_init.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_icu_init.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_mpc.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_mpc.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_mpc.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_mpc.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_port.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_port.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_port.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_port.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_ram_init.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_ram_init.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_ram_init.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_ram_init.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_reset.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_reset.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_reset.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_reset.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_system.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_system.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_system.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_system.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_typedefs.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_typedefs.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_typedefs.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_typedefs.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/RZ_T1_init.icf b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/RZ_T1_init.icf similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/RZ_T1_init.icf rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/RZ_T1_init.icf diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/exit.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/exit.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/exit.c rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/exit.c diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/loader_init.asm b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/loader_init.asm similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/loader_init.asm rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/loader_init.asm diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/loader_init2.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/loader_init2.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/loader_init2.c rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/loader_init2.c diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_atcm_init.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/r_atcm_init.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_atcm_init.c rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/r_atcm_init.c diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_cpg.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/r_cpg.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_cpg.c rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/r_cpg.c diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_ecm.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/r_ecm.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_ecm.c rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/r_ecm.c diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_icu_init.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/r_icu_init.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_icu_init.c rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/r_icu_init.c diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_ram_init.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/r_ram_init.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_ram_init.c rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/r_ram_init.c diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_reset.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/r_reset.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_reset.c rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/r_reset.c diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/vector.asm b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/vector.asm similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/vector.asm rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/vector.asm diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/makefile.init b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/makefile.init similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/makefile.init rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/makefile.init diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.Debug.cspy.bat b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.Debug.cspy.bat new file mode 100644 index 000000000..82e077d1c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%1" == "" goto debugFile + +@echo on + +"C:\DevTools\IAR Systems\Embedded Workbench 7.2\common\bin\cspybat" -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_R4F_RZ_T_GCC_IAR\settings\RTOSDemo.Debug.general.xcl" --backend -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_R4F_RZ_T_GCC_IAR\settings\RTOSDemo.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\DevTools\IAR Systems\Embedded Workbench 7.2\common\bin\cspybat" -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_R4F_RZ_T_GCC_IAR\settings\RTOSDemo.Debug.general.xcl" "--debug_file=%1" --backend -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_R4F_RZ_T_GCC_IAR\settings\RTOSDemo.Debug.driver.xcl" + +@echo off +:end \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.Debug.driver.xcl b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.Debug.driver.xcl new file mode 100644 index 000000000..4ac5dda39 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.Debug.driver.xcl @@ -0,0 +1,43 @@ + -B + +"--endian=little" + +"--cpu=Cortex-R4F" + +"--fpu=VFPv3" + +"-p" + +"C:\DevTools\IAR Systems\Embedded Workbench 7.2\arm\CONFIG\debugger\Renesas\R7S910018_R4F.ddf" + +"--drv_verify_download" + +"--semihosting=none" + +"--device=R7S910018_R4F" + +"--multicore_nr_of_cores=1" + +"--jet_standard_reset=7,0,0" + +"--reset_style=\"0,-,0,Disabled__no_reset_\"" + +"--reset_style=\"1,-,0,Software\"" + +"--reset_style=\"2,-,0,Hardware\"" + +"--reset_style=\"7,ResetAndStopAtUser,1,Reset_and_halt_after_bootloader\"" + +"--drv_restore_breakpoints=_main" + +"--drv_catch_exceptions=0x01a" + +"--jet_board_cfg=C:\DevTools\IAR Systems\Embedded Workbench 7.2\arm\config\debugger\Renesas\RZT1.ProbeConfig" + +"--drv_trace_size=8388608" + +"--board_file=C:\DevTools\IAR Systems\Embedded Workbench 7.2\arm\config\flashloader\" + + + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.Debug.general.xcl b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.Debug.general.xcl new file mode 100644 index 000000000..12fbca4ad --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.Debug.general.xcl @@ -0,0 +1,15 @@ +"C:\DevTools\IAR Systems\Embedded Workbench 7.2\arm\bin\armproc.dll" + +"C:\DevTools\IAR Systems\Embedded Workbench 7.2\arm\bin\armJET.dll" + +"C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_R4F_RZ_T_GCC_IAR\Debug\Exe\c.out" + +--plugin "C:\DevTools\IAR Systems\Embedded Workbench 7.2\arm\bin\armbat.dll" + +--device_macro "C:\DevTools\IAR Systems\Embedded Workbench 7.2\arm\config\debugger\Renesas\Trace_RZT1.dmac" + +--macro "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_R4F_RZ_T_GCC_IAR\System\IAR\RZT1_init_RAM.mac" + + + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.crun b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.crun new file mode 100644 index 000000000..5bb5acca4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.crun @@ -0,0 +1,16 @@ + + + + 1 + + + * + * + * + 0 + 1 + + + + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.dbgdt b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.dbgdt new file mode 100644 index 000000000..01a951688 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.dbgdt @@ -0,0 +1,277 @@ + + + + + + + 20 + 1622 + + + 20 + 1216 + 324 + 81 + + + + 194 + 27 + 27 + 27 + + + + + Disassembly + _I0 + + + 500 + 20 + + + + 2 + 0 + 0 + + + 1 + 1 + + + + 3 + 0 + 0 + + + + Breakpoint + _I0 + + + 500 + 35 + + + + + 2 + 0 + 0 + + + + + + + + + TabID-31370-17793 + Debug Log + Debug-Log + + + + TabID-30847-17802 + Build + Build + + + + 0 + + + + + TabID-9350-17796 + Workspace + Workspace + + + RTOSDemo + RTOSDemo/FreeRTOS_Source + RTOSDemo/Full_Demo + + + + + 0 + + + + + + TextEditor + $WS_DIR$\src\main.c + 0 + 0 + 0 + 0 + 0 + 128 + 6721 + 6721 + + 0 + + TextEditor + $WS_DIR$\src\Full_Demo\IntQueueTimer.c + 0 + 0 + 0 + 0 + 0 + 81 + 4886 + 4912 + + + TextEditor + $WS_DIR$\System\IAR\Interrupt_Entry_Stubs.asm + 0 + 0 + 0 + 0 + 0 + 66 + 4185 + 4185 + + + TextEditor + $WS_DIR$\..\..\Source\portable\IAR\ARM_CRx_No_GIC\port.c + 0 + 0 + 0 + 0 + 0 + 245 + 11320 + 11320 + + + TextEditor + $WS_DIR$\src\Full_Demo\reg_test_IAR.asm + 0 + 0 + 0 + 0 + 0 + 123 + 5555 + 5555 + + + TextEditor + $WS_DIR$\..\Common\Minimal\TimerDemo.c + 0 + 0 + 0 + 0 + 0 + 242 + 12612 + 12612 + + + TextEditor + $WS_DIR$\..\..\Source\tasks.c + 0 + 0 + 0 + 0 + 0 + 202 + 11920 + 11930 + + + 0 + + + 1000000 + 1000000 + + + 1 + + + + + + + iaridepm.enu1 + + + debuggergui.enu1 + + + + + + + armjet.enu1 + + + + + + + + + + -2 + -2 + 718 + 268 + -2 + -2 + 200 + 200 + 119048 + 203252 + 160714 + 731707 + + + + + + + + + + + + + + + + -2 + -2 + 198 + 1682 + -2 + -2 + 1684 + 200 + 1002381 + 203252 + 119048 + 203252 + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.dni b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.dni new file mode 100644 index 000000000..d7aa2b822 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.dni @@ -0,0 +1,112 @@ +[InterruptLog] +LogEnabled=0 +GraphEnabled=0 +ShowTimeLog=1 +SumEnabled=0 +ShowTimeSum=1 +SumSortOrder=0 +[DataLog] +LogEnabled=0 +GraphEnabled=0 +ShowTimeLog=1 +SumEnabled=0 +ShowTimeSum=1 +[Stack] +FillEnabled=0 +OverflowWarningsEnabled=1 +WarningThreshold=90 +SpWarningsEnabled=1 +WarnLogOnly=1 +UseTrigger=1 +TriggerName=main +LimitSize=0 +ByteLimit=50 +[Interrupts] +Enabled=1 +[MemConfig] +Base=1 +Manual=0 +Ddf=1 +TypeViol=0 +Stop=1 +[Trace1] +Enabled=0 +ShowSource=1 +[Simulator] +Freq=10000000 +MultiCoreRunAll=1 +[PlDriver] +MemConfigValue=C:\DevTools\IAR Systems\Embedded Workbench 7.2\arm\CONFIG\debugger\Renesas\R7S910018_R4F.ddf +FirstRun=0 +[Jet] +DisableInterrupts=0 +MultiCoreRunAll=0 +JetConnSerialNo=73866 +JetConnFoundProbes= +OnlineReset=Software +PrevWtdReset=Reset and halt after bootloader +[ArmDriver] +EnableCache=1 +[DebugChecksum] +Checksum=479945930 +[Exceptions] +StopOnUncaught=_ 0 +StopOnThrow=_ 0 +[CallStack] +ShowArgs=0 +[Disassembly] +MixedMode=1 +[SWOManager] +SamplingDivider=8192 +OverrideClock=0 +CpuClock=7274605 +SwoClock=7340141 +DataLogMode=0 +ItmPortsEnabled=63 +ItmTermIOPorts=1 +ItmLogPorts=0 +ItmLogFile=$PROJ_DIR$\ITM.log +PowerForcePC=1 +PowerConnectPC=1 +[Trace2] +Enabled=0 +ShowSource=0 +[SWOTraceWindow] +ForcedPcSampling=0 +ForcedInterruptLogs=0 +ForcedItmLogs=0 +EventCPI=0 +EventEXC=0 +EventFOLD=0 +EventLSU=0 +EventSLEEP=0 +[PowerLog] +Title_0=ITrgPwr +Symbol_0=0 4 1 +LogEnabled=0 +GraphEnabled=0 +ShowTimeLog=1 +LiveEnabled=0 +LiveFile=PowerLogLive.log +[CallStackLog] +Enabled=0 +[CallStackStripe] +ShowTiming=1 +[PowerProbe] +Frequency=10000 +Probe0=ITrgPwr +ProbeSetup0=2 1 1 2 0 0 +[Log file] +LoggingEnabled=_ 0 +LogFile=_ "" +Category=_ 0 +[TermIOLog] +LoggingEnabled=_ 0 +LogFile=_ "" +[Disassemble mode] +mode=0 +[Breakpoints2] +Count=0 +[Aliases] +Count=0 +SuppressDialog=0 diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.wsdt b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.wsdt new file mode 100644 index 000000000..ce2aca9bc --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.wsdt @@ -0,0 +1,89 @@ + + + + + + RTOSDemo/Debug + + + + + + + + + 222272727 + + + + + 201622 + + + + + + 20121632481 + + + 497 + 82 + 746 + 331 + + + + + + + + + TabID-31096-4084 + Workspace + Workspace + + + RTOSDemoRTOSDemo/Full_DemoRTOSDemo/Full_Demo/Common Demo Tasks + + + + 0 + + + TabID-12820-6268 + Debug Log + Debug-Log + + + + TabID-23359-8322 + Build + Build + + + + TabID-12571-20119 + Find in Files + Find-in-Files + + + + + 1 + + + + + + TextEditor$WS_DIR$\src\main.c00000128672167210TextEditor$WS_DIR$\src\Full_Demo\IntQueueTimer.c000008148864912TextEditor$WS_DIR$\System\IAR\Interrupt_Entry_Stubs.asm000006641854185TextEditor$WS_DIR$\..\..\Source\portable\IAR\ARM_CRx_No_GIC\port.c000002451132011320TextEditor$WS_DIR$\src\Full_Demo\reg_test_IAR.asm0000012355555555TextEditor$WS_DIR$\..\Common\Minimal\TimerDemo.c000002421261212612TextEditor$WS_DIR$\..\..\Source\tasks.c0000020211920119300100000010000001 + + + + + + + iaridepm.enu1-2-2619312-2-2200200119048203252186905631098-2-23211682-2-216843231002381328252119048203252 + + + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.wspos b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.wspos new file mode 100644 index 000000000..ecdc2c482 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.wspos @@ -0,0 +1,2 @@ +[MainWindow] +WindowPlacement=_ 519 0 1619 872 3 diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Blinky_Demo/main_blinky.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Blinky_Demo/main_blinky.c rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Blinky_Demo/main_blinky.c diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/FreeRTOSConfig.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/FreeRTOSConfig.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/FreeRTOSConfig.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/FreeRTOS_tick_config.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/FreeRTOS_tick_config.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/FreeRTOS_tick_config.c rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/FreeRTOS_tick_config.c diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/IntQueueTimer.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/IntQueueTimer.c rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/IntQueueTimer.c diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/IntQueueTimer.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/IntQueueTimer.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/IntQueueTimer.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/main_full.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/main_full.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/main_full.c rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/main_full.c diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/reg_test_GCC.S b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/reg_test_GCC.S similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/reg_test_GCC.S rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/reg_test_GCC.S diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/reg_test_IAR.asm b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/reg_test_IAR.asm similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/reg_test_IAR.asm rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/reg_test_IAR.asm diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/iodefine.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/iodefine.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/iodefine.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/iodefine.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cgc.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_cgc.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cgc.c rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_cgc.c diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cgc.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_cgc.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cgc.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_cgc.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cgc_user.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_cgc_user.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cgc_user.c rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_cgc_user.c diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cmt.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_cmt.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cmt.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_cmt.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cmt_user.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_cmt_user.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cmt_user.c rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_cmt_user.c diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_icu.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_icu.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_icu.c rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_icu.c diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_icu.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_icu.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_icu.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_icu.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_icu_user.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_icu_user.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_icu_user.c rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_icu_user.c diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_interrupthandlers.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_interrupthandlers.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_interrupthandlers.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_interrupthandlers.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_intprg.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_intprg.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_intprg.c rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_intprg.c diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_macrodriver.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_macrodriver.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_macrodriver.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_macrodriver.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_mpc.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_mpc.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_mpc.c rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_mpc.c diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_mpc.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_mpc.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_mpc.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_mpc.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_port.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_port.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_port.c rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_port.c diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_port.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_port.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_port.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_port.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_port_user.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_port_user.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_port_user.c rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_port_user.c diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_rspi.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_rspi.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_rspi.c rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_rspi.c diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_rspi.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_rspi.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_rspi.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_rspi.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_rspi_user.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_rspi_user.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_rspi_user.c rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_rspi_user.c diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_systeminit.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_systeminit.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_systeminit.c rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_systeminit.c diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_tpu.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_tpu.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_tpu.c rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_tpu.c diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_tpu.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_tpu.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_tpu.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_tpu.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_tpu_user.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_tpu_user.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_tpu_user.c rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_tpu_user.c diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_userdefine.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_userdefine.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_userdefine.h rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_userdefine.h diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/main.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/main.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/main.c rename to FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/main.c diff --git a/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/Makefile-default.mk b/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/Makefile-default.mk index c852fc32f..4a62422e9 100644 --- a/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/Makefile-default.mk +++ b/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/Makefile-default.mk @@ -462,626 +462,626 @@ ${OBJECTDIR}/_ext/1477011893/main_blinky.o: ../src/Blinky_Demo/main_blinky.c nb @${MKDIR} "${OBJECTDIR}/_ext/1477011893" @${RM} ${OBJECTDIR}/_ext/1477011893/main_blinky.o.d @${RM} ${OBJECTDIR}/_ext/1477011893/main_blinky.o - @${FIXDEPS} "${OBJECTDIR}/_ext/1477011893/main_blinky.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1477011893/main_blinky.o.d" -o ${OBJECTDIR}/_ext/1477011893/main_blinky.o ../src/Blinky_Demo/main_blinky.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/1477011893/main_blinky.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1477011893/main_blinky.o.d" -o ${OBJECTDIR}/_ext/1477011893/main_blinky.o ../src/Blinky_Demo/main_blinky.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/1884096877/heap_2.o: ../../../Source/portable/MemMang/heap_2.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/1884096877" @${RM} ${OBJECTDIR}/_ext/1884096877/heap_2.o.d @${RM} ${OBJECTDIR}/_ext/1884096877/heap_2.o - @${FIXDEPS} "${OBJECTDIR}/_ext/1884096877/heap_2.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1884096877/heap_2.o.d" -o ${OBJECTDIR}/_ext/1884096877/heap_2.o ../../../Source/portable/MemMang/heap_2.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/1884096877/heap_2.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1884096877/heap_2.o.d" -o ${OBJECTDIR}/_ext/1884096877/heap_2.o ../../../Source/portable/MemMang/heap_2.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/582319769/port.o: ../../../Source/portable/MPLAB/PIC32MEC14xx/port.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/582319769" @${RM} ${OBJECTDIR}/_ext/582319769/port.o.d @${RM} ${OBJECTDIR}/_ext/582319769/port.o - @${FIXDEPS} "${OBJECTDIR}/_ext/582319769/port.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/582319769/port.o.d" -o ${OBJECTDIR}/_ext/582319769/port.o ../../../Source/portable/MPLAB/PIC32MEC14xx/port.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/582319769/port.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/582319769/port.o.d" -o ${OBJECTDIR}/_ext/582319769/port.o ../../../Source/portable/MPLAB/PIC32MEC14xx/port.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/449926602/event_groups.o: ../../../Source/event_groups.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/449926602" @${RM} ${OBJECTDIR}/_ext/449926602/event_groups.o.d @${RM} ${OBJECTDIR}/_ext/449926602/event_groups.o - @${FIXDEPS} "${OBJECTDIR}/_ext/449926602/event_groups.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/449926602/event_groups.o.d" -o ${OBJECTDIR}/_ext/449926602/event_groups.o ../../../Source/event_groups.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/449926602/event_groups.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/449926602/event_groups.o.d" -o ${OBJECTDIR}/_ext/449926602/event_groups.o ../../../Source/event_groups.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/449926602/list.o: ../../../Source/list.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/449926602" @${RM} ${OBJECTDIR}/_ext/449926602/list.o.d @${RM} ${OBJECTDIR}/_ext/449926602/list.o - @${FIXDEPS} "${OBJECTDIR}/_ext/449926602/list.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/449926602/list.o.d" -o ${OBJECTDIR}/_ext/449926602/list.o ../../../Source/list.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/449926602/list.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/449926602/list.o.d" -o ${OBJECTDIR}/_ext/449926602/list.o ../../../Source/list.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/449926602/queue.o: ../../../Source/queue.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/449926602" @${RM} ${OBJECTDIR}/_ext/449926602/queue.o.d @${RM} ${OBJECTDIR}/_ext/449926602/queue.o - @${FIXDEPS} "${OBJECTDIR}/_ext/449926602/queue.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/449926602/queue.o.d" -o ${OBJECTDIR}/_ext/449926602/queue.o ../../../Source/queue.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/449926602/queue.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/449926602/queue.o.d" -o ${OBJECTDIR}/_ext/449926602/queue.o ../../../Source/queue.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/449926602/tasks.o: ../../../Source/tasks.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/449926602" @${RM} ${OBJECTDIR}/_ext/449926602/tasks.o.d @${RM} ${OBJECTDIR}/_ext/449926602/tasks.o - @${FIXDEPS} "${OBJECTDIR}/_ext/449926602/tasks.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/449926602/tasks.o.d" -o ${OBJECTDIR}/_ext/449926602/tasks.o ../../../Source/tasks.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/449926602/tasks.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/449926602/tasks.o.d" -o ${OBJECTDIR}/_ext/449926602/tasks.o ../../../Source/tasks.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/449926602/timers.o: ../../../Source/timers.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/449926602" @${RM} ${OBJECTDIR}/_ext/449926602/timers.o.d @${RM} ${OBJECTDIR}/_ext/449926602/timers.o - @${FIXDEPS} "${OBJECTDIR}/_ext/449926602/timers.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/449926602/timers.o.d" -o ${OBJECTDIR}/_ext/449926602/timers.o ../../../Source/timers.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/449926602/timers.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/449926602/timers.o.d" -o ${OBJECTDIR}/_ext/449926602/timers.o ../../../Source/timers.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/1163846883/blocktim.o: ../../Common/Minimal/blocktim.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/1163846883" @${RM} ${OBJECTDIR}/_ext/1163846883/blocktim.o.d @${RM} ${OBJECTDIR}/_ext/1163846883/blocktim.o - @${FIXDEPS} "${OBJECTDIR}/_ext/1163846883/blocktim.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1163846883/blocktim.o.d" -o ${OBJECTDIR}/_ext/1163846883/blocktim.o ../../Common/Minimal/blocktim.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/1163846883/blocktim.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" 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../src/MEC14xx/interrupts/girq25.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/1662639563" @${RM} ${OBJECTDIR}/_ext/1662639563/girq25.o.d @${RM} ${OBJECTDIR}/_ext/1662639563/girq25.o - @${FIXDEPS} "${OBJECTDIR}/_ext/1662639563/girq25.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1662639563/girq25.o.d" -o ${OBJECTDIR}/_ext/1662639563/girq25.o ../src/MEC14xx/interrupts/girq25.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/1662639563/girq25.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1662639563/girq25.o.d" -o ${OBJECTDIR}/_ext/1662639563/girq25.o ../src/MEC14xx/interrupts/girq25.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/1662639563/girq26.o: ../src/MEC14xx/interrupts/girq26.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/1662639563" @${RM} ${OBJECTDIR}/_ext/1662639563/girq26.o.d @${RM} ${OBJECTDIR}/_ext/1662639563/girq26.o - @${FIXDEPS} "${OBJECTDIR}/_ext/1662639563/girq26.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1662639563/girq26.o.d" -o ${OBJECTDIR}/_ext/1662639563/girq26.o ../src/MEC14xx/interrupts/girq26.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/1662639563/girq26.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1662639563/girq26.o.d" -o ${OBJECTDIR}/_ext/1662639563/girq26.o ../src/MEC14xx/interrupts/girq26.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/1662639563/girqs.o: ../src/MEC14xx/interrupts/girqs.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/1662639563" @${RM} ${OBJECTDIR}/_ext/1662639563/girqs.o.d @${RM} ${OBJECTDIR}/_ext/1662639563/girqs.o - @${FIXDEPS} "${OBJECTDIR}/_ext/1662639563/girqs.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1662639563/girqs.o.d" -o ${OBJECTDIR}/_ext/1662639563/girqs.o ../src/MEC14xx/interrupts/girqs.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/1662639563/girqs.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1662639563/girqs.o.d" -o ${OBJECTDIR}/_ext/1662639563/girqs.o ../src/MEC14xx/interrupts/girqs.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/1068550557/default-on-bootstrap.o: ../src/MEC14xx/startup/MPLAB/default-on-bootstrap.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/1068550557" @${RM} ${OBJECTDIR}/_ext/1068550557/default-on-bootstrap.o.d @${RM} ${OBJECTDIR}/_ext/1068550557/default-on-bootstrap.o - @${FIXDEPS} "${OBJECTDIR}/_ext/1068550557/default-on-bootstrap.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1068550557/default-on-bootstrap.o.d" -o ${OBJECTDIR}/_ext/1068550557/default-on-bootstrap.o ../src/MEC14xx/startup/MPLAB/default-on-bootstrap.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/1068550557/default-on-bootstrap.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1068550557/default-on-bootstrap.o.d" -o ${OBJECTDIR}/_ext/1068550557/default-on-bootstrap.o ../src/MEC14xx/startup/MPLAB/default-on-bootstrap.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/1068550557/on_reset.o: ../src/MEC14xx/startup/MPLAB/on_reset.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/1068550557" @${RM} ${OBJECTDIR}/_ext/1068550557/on_reset.o.d @${RM} ${OBJECTDIR}/_ext/1068550557/on_reset.o - @${FIXDEPS} "${OBJECTDIR}/_ext/1068550557/on_reset.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1068550557/on_reset.o.d" -o ${OBJECTDIR}/_ext/1068550557/on_reset.o ../src/MEC14xx/startup/MPLAB/on_reset.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/1068550557/on_reset.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1068550557/on_reset.o.d" -o ${OBJECTDIR}/_ext/1068550557/on_reset.o ../src/MEC14xx/startup/MPLAB/on_reset.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/1376193940/mec14xx_bbled.o: ../src/MEC14xx/mec14xx_bbled.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/1376193940" @${RM} ${OBJECTDIR}/_ext/1376193940/mec14xx_bbled.o.d @${RM} ${OBJECTDIR}/_ext/1376193940/mec14xx_bbled.o - @${FIXDEPS} "${OBJECTDIR}/_ext/1376193940/mec14xx_bbled.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1376193940/mec14xx_bbled.o.d" -o ${OBJECTDIR}/_ext/1376193940/mec14xx_bbled.o ../src/MEC14xx/mec14xx_bbled.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/1376193940/mec14xx_bbled.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1376193940/mec14xx_bbled.o.d" -o ${OBJECTDIR}/_ext/1376193940/mec14xx_bbled.o ../src/MEC14xx/mec14xx_bbled.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/1376193940/mec14xx_gpio.o: ../src/MEC14xx/mec14xx_gpio.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/1376193940" @${RM} ${OBJECTDIR}/_ext/1376193940/mec14xx_gpio.o.d @${RM} ${OBJECTDIR}/_ext/1376193940/mec14xx_gpio.o - @${FIXDEPS} "${OBJECTDIR}/_ext/1376193940/mec14xx_gpio.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1376193940/mec14xx_gpio.o.d" -o ${OBJECTDIR}/_ext/1376193940/mec14xx_gpio.o ../src/MEC14xx/mec14xx_gpio.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/1376193940/mec14xx_gpio.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1376193940/mec14xx_gpio.o.d" -o ${OBJECTDIR}/_ext/1376193940/mec14xx_gpio.o ../src/MEC14xx/mec14xx_gpio.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/1376193940/mec14xx_jtvic.o: ../src/MEC14xx/mec14xx_jtvic.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/1376193940" @${RM} ${OBJECTDIR}/_ext/1376193940/mec14xx_jtvic.o.d @${RM} ${OBJECTDIR}/_ext/1376193940/mec14xx_jtvic.o - @${FIXDEPS} "${OBJECTDIR}/_ext/1376193940/mec14xx_jtvic.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1376193940/mec14xx_jtvic.o.d" -o ${OBJECTDIR}/_ext/1376193940/mec14xx_jtvic.o ../src/MEC14xx/mec14xx_jtvic.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/1376193940/mec14xx_jtvic.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1376193940/mec14xx_jtvic.o.d" -o ${OBJECTDIR}/_ext/1376193940/mec14xx_jtvic.o ../src/MEC14xx/mec14xx_jtvic.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/1376193940/mec14xx_system.o: ../src/MEC14xx/mec14xx_system.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/1376193940" @${RM} ${OBJECTDIR}/_ext/1376193940/mec14xx_system.o.d @${RM} ${OBJECTDIR}/_ext/1376193940/mec14xx_system.o - @${FIXDEPS} "${OBJECTDIR}/_ext/1376193940/mec14xx_system.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1376193940/mec14xx_system.o.d" -o ${OBJECTDIR}/_ext/1376193940/mec14xx_system.o ../src/MEC14xx/mec14xx_system.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/1376193940/mec14xx_system.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1376193940/mec14xx_system.o.d" -o ${OBJECTDIR}/_ext/1376193940/mec14xx_system.o ../src/MEC14xx/mec14xx_system.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/1376193940/mec14xx_tfdp.o: ../src/MEC14xx/mec14xx_tfdp.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/1376193940" @${RM} ${OBJECTDIR}/_ext/1376193940/mec14xx_tfdp.o.d @${RM} ${OBJECTDIR}/_ext/1376193940/mec14xx_tfdp.o - @${FIXDEPS} "${OBJECTDIR}/_ext/1376193940/mec14xx_tfdp.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1376193940/mec14xx_tfdp.o.d" -o ${OBJECTDIR}/_ext/1376193940/mec14xx_tfdp.o ../src/MEC14xx/mec14xx_tfdp.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/1376193940/mec14xx_tfdp.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1376193940/mec14xx_tfdp.o.d" -o ${OBJECTDIR}/_ext/1376193940/mec14xx_tfdp.o ../src/MEC14xx/mec14xx_tfdp.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/1376193940/mec14xx_timers.o: ../src/MEC14xx/mec14xx_timers.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/1376193940" @${RM} ${OBJECTDIR}/_ext/1376193940/mec14xx_timers.o.d @${RM} ${OBJECTDIR}/_ext/1376193940/mec14xx_timers.o - @${FIXDEPS} "${OBJECTDIR}/_ext/1376193940/mec14xx_timers.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1376193940/mec14xx_timers.o.d" -o ${OBJECTDIR}/_ext/1376193940/mec14xx_timers.o ../src/MEC14xx/mec14xx_timers.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/1376193940/mec14xx_timers.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1376193940/mec14xx_timers.o.d" -o ${OBJECTDIR}/_ext/1376193940/mec14xx_timers.o ../src/MEC14xx/mec14xx_timers.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/1360937237/main.o: ../src/main.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/1360937237" @${RM} ${OBJECTDIR}/_ext/1360937237/main.o.d @${RM} ${OBJECTDIR}/_ext/1360937237/main.o - @${FIXDEPS} "${OBJECTDIR}/_ext/1360937237/main.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1360937237/main.o.d" -o ${OBJECTDIR}/_ext/1360937237/main.o ../src/main.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/1360937237/main.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1360937237/main.o.d" -o ${OBJECTDIR}/_ext/1360937237/main.o ../src/main.c -D__DEBUG -Wall -Wextra endif diff --git a/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/Makefile-genesis.properties b/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/Makefile-genesis.properties index 9ae1d91ed..cad03b61e 100644 --- a/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/Makefile-genesis.properties +++ b/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/Makefile-genesis.properties @@ -1,8 +1,8 @@ # -#Sat Sep 12 19:52:29 BST 2015 +#Sun Sep 13 08:07:29 BST 2015 default.com-microchip-mplab-nbide-toolchainXC32-XC32LanguageToolchain.md5=a29d9df60dd9a7849837c8f5ca17a004 default.languagetoolchain.dir=C\:\\DevTools\\Microchip\\xc32\\v1.33\\bin -configurations-xml=1488628682f58c9c6bf4eb01175324a8 +configurations-xml=30deb6920812925f770c8a369802918a com-microchip-mplab-nbide-embedded-makeproject-MakeProject.md5=47805b5596804b87cda41e61096929be default.languagetoolchain.version=1.33 host.platform=windows diff --git a/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/configurations.xml b/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/configurations.xml index 6e1f4aff7..83135a2b9 100644 --- a/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/configurations.xml +++ b/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/configurations.xml @@ -244,7 +244,7 @@ - + diff --git a/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/private/private.xml b/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/private/private.xml index 2cb574f8d..d9ec1062e 100644 --- a/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/private/private.xml +++ b/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/private/private.xml @@ -16,15 +16,12 @@ file:/C:/Users/m91145/Documents/OS%20IDE%20Specialist%20Team/FreeRTOS%20MEC%20Port/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/IntQueueTimer_isr.S - file:/C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/startup/MPLAB/default-on-bootstrap.c - file:/C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Source/tasks.c - file:/C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/startup/MPLAB/crt0.S - file:/C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Source/list.c - file:/C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/startup/MPLAB/on_reset.c - file:/C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/startup/MPLAB/crti.S file:/C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/main.c - file:/C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/startup/MPLAB/crtn.S - file:/C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/Blinky_Demo/main_blinky.c + file:/C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/FreeRTOSConfig.h + file:/C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/port.c + file:/C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Source/tasks.c + file:/C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/main_full.c + file:/C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/timertest.c diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.cproject b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.cproject index 017cce7d2..29d7efc14 100644 --- a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.cproject +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.cproject @@ -99,8 +99,11 @@ + + + - + @@ -114,6 +117,10 @@ - + + + + + diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.project b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.project index 40109d0cb..2aaee4c2d 100644 --- a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.project +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.project @@ -42,6 +42,15 @@ + + 1442930329366 + + 10 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-settings + + 1442848178229 src/FreeRTOS_Source @@ -226,7 +235,7 @@ FREERTOS_ROOT - $%7BPARENT-4-PROJECT_LOC%7D + $%7BPARENT-3-PROJECT_LOC%7D diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.settings/language.settings.xml b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.settings/language.settings.xml index 9db58ebe7..77df28c89 100644 --- a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.settings/language.settings.xml +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.settings/language.settings.xml @@ -3,7 +3,7 @@ - + diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/RTOSDemo.ewd b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/RTOSDemo.ewd new file mode 100644 index 000000000..3ef1570c0 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/RTOSDemo.ewd @@ -0,0 +1,771 @@ + + + + 2 + + Debug + + RX + + 1 + + C-SPY + 3 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RXEMUE20 + 4 + + 4 + 1 + 1 + + + + + + + + + + + + + + + RXE2LITE + 1 + + 0 + 1 + 1 + + + + + + + + + + + + + + + RXJLINK + 4 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + SIMRX + 1 + + 1 + 1 + 1 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXRxPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + RX + + 0 + + C-SPY + 3 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RXEMUE20 + 4 + + 4 + 1 + 0 + + + + + + + + + + + + + + + RXE2LITE + 1 + + 0 + 1 + 0 + + + + + + + + + + + + + + + RXJLINK + 4 + + 5 + 1 + 0 + + + + + + + + + + + + + + + + + + SIMRX + 1 + + 1 + 1 + 0 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXRxPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/RTOSDemo.ewp b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/RTOSDemo.ewp new file mode 100644 index 000000000..5cda01ab9 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/RTOSDemo.ewp @@ -0,0 +1,2044 @@ + + + + 2 + + Debug + + RX + + 1 + + General + 6 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCRX + 8 + + 17 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARX + 6 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 1 + + 0 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 4 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 1 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + RX + + 0 + + General + 6 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCRX + 8 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARX + 6 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 1 + + 0 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 4 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 1 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Blinky_Demo + + $PROJ_DIR$\src\Blinky_Demo\main_blinky.c + + + + cg_src + + $PROJ_DIR$\src\cg_src\r_cg_cgc.c + + + $PROJ_DIR$\src\cg_src\r_cg_hardware_setup.c + + + $PROJ_DIR$\src\cg_src\r_cg_port.c + + + $PROJ_DIR$\src\cg_src\r_cg_sci.c + + + + FreeRTOS_Source + + portable + + MemMang + + $PROJ_DIR$\..\..\Source\portable\MemMang\heap_4.c + + + + $PROJ_DIR$\..\..\Source\portable\IAR\RX100\port.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\RX100\port_asm.s + + + + $PROJ_DIR$\..\..\Source\event_groups.c + + + $PROJ_DIR$\..\..\Source\list.c + + + $PROJ_DIR$\..\..\Source\queue.c + + + $PROJ_DIR$\..\..\Source\tasks.c + + + $PROJ_DIR$\..\..\Source\timers.c + + + + Full_Demo + + Standard_Demo_Tasks + + $PROJ_DIR$\..\Common\Minimal\BlockQ.c + + + $PROJ_DIR$\..\Common\Minimal\blocktim.c + + + $PROJ_DIR$\..\Common\Minimal\countsem.c + + + $PROJ_DIR$\..\Common\Minimal\death.c + + + $PROJ_DIR$\..\Common\Minimal\dynamic.c + + + $PROJ_DIR$\..\Common\Minimal\EventGroupsDemo.c + + + $PROJ_DIR$\..\Common\Minimal\flop.c + + + $PROJ_DIR$\..\Common\Minimal\GenQTest.c + + + $PROJ_DIR$\..\Common\Minimal\IntQueue.c + + + $PROJ_DIR$\..\Common\Minimal\IntSemTest.c + + + $PROJ_DIR$\..\Common\Minimal\QueueOverwrite.c + + + $PROJ_DIR$\..\Common\Minimal\recmutex.c + + + $PROJ_DIR$\..\Common\Minimal\semtest.c + + + $PROJ_DIR$\..\Common\Minimal\TaskNotify.c + + + $PROJ_DIR$\..\Common\Minimal\TimerDemo.c + + + + $PROJ_DIR$\src\Full_Demo\IntQueueTimer.c + + + $PROJ_DIR$\src\Full_Demo\main_full.c + + + $PROJ_DIR$\src\Full_Demo\RegTest_IAR.s + + + + $PROJ_DIR$\src\FreeRTOSConfig.h + + + $PROJ_DIR$\src\main.c + + + $PROJ_DIR$\src\rskrx113def.h + + + + diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/RTOSDemo.eww b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/RTOSDemo.eww new file mode 100644 index 000000000..239a9381e --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/RTOSDemo.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\RTOSDemo.ewp + + + + + diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.cspy.bat b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.cspy.bat new file mode 100644 index 000000000..000a07c7c --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%1" == "" goto debugFile + +@echo on + +"C:\DevTools\IAR Systems\Embedded Workbench 7.2\common\bin\cspybat" -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\RX113-RSK_GCC_e2studio_IAR\settings\RTOSDemo.Debug.general.xcl" --backend -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\RX113-RSK_GCC_e2studio_IAR\settings\RTOSDemo.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\DevTools\IAR Systems\Embedded Workbench 7.2\common\bin\cspybat" -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\RX113-RSK_GCC_e2studio_IAR\settings\RTOSDemo.Debug.general.xcl" "--debug_file=%1" --backend -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\RX113-RSK_GCC_e2studio_IAR\settings\RTOSDemo.Debug.driver.xcl" + +@echo off +:end \ No newline at end of file diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.driver.xcl b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.driver.xcl new file mode 100644 index 000000000..048724e75 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.driver.xcl @@ -0,0 +1,39 @@ + -B + +"-p" + +"C:\DevTools\IAR Systems\Embedded Workbench 7.2\rx\config\debugger\ior5f51138.ddf" + +"--endian" + +"l" + +"--double" + +"64" + +"--core" + +"rxv1" + +"--int" + +"32" + +"--no_fpu" + +"-d" + +"emue20" + +"--drv_mode" + +"debugging" + +"--drv_communication" + +"USB" + + + + diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.general.xcl b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.general.xcl new file mode 100644 index 000000000..0d8b5cdf6 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.general.xcl @@ -0,0 +1,11 @@ +"C:\DevTools\IAR Systems\Embedded Workbench 7.2\rx\bin\rxproc.dll" + +"C:\DevTools\IAR Systems\Embedded Workbench 7.2\rx\bin\rxe1e20.dll" + +"C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\RX113-RSK_GCC_e2studio_IAR\Debug\Exe\RTOSDemo.out" + +--plugin "C:\DevTools\IAR Systems\Embedded Workbench 7.2\rx\bin\rxbat.dll" + + + + diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.dbgdt b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.dbgdt new file mode 100644 index 000000000..4f7e51010 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.dbgdt @@ -0,0 +1,244 @@ + + + + + + + 20 + 1622 + + + 20 + 1216 + 324 + 81 + + + + 255 + 27 + 27 + 27 + + + + + Disassembly + _I0 + + + 500 + 20 + + + + 2 + 0 + 0 + + + 1 + 1 + + + + 2 + 0 + 0 + + + + + + + + + TabID-6594-3339 + Debug Log + Debug-Log + + + + TabID-6072-3348 + Build + Build + + + + 0 + + + + + TabID-17343-3342 + Workspace + Workspace + + + RTOSDemo + + + + + 0 + + + + + + TextEditor + $WS_DIR$\src\main.c + 0 + 0 + 0 + 0 + 0 + 66 + 5312 + 5312 + + + TextEditor + $WS_DIR$\src\Full_Demo\RegTest_IAR.s + 0 + 0 + 0 + 0 + 0 + 144 + 5881 + 5881 + + + TextEditor + $WS_DIR$\..\Common\Minimal\flop.c + 0 + 0 + 0 + 0 + 0 + 126 + 6956 + 6956 + + + TextEditor + $WS_DIR$\..\Common\Minimal\TimerDemo.c + 0 + 0 + 0 + 0 + 0 + 242 + 12612 + 12612 + + + TextEditor + $WS_DIR$\..\Common\Minimal\IntQueue.c + 0 + 0 + 0 + 0 + 0 + 381 + 0 + 0 + + + TextEditor + $WS_DIR$\src\Full_Demo\IntQueueTimer.c + 0 + 0 + 0 + 0 + 0 + 154 + 7349 + 7349 + + 5 + + 0 + + + 1000000 + 1000000 + + + 1 + + + + + + + iaridepm.enu1 + + + + + + + debuggergui.enu1 + + + + + + + + + + -2 + -2 + 718 + 329 + -2 + -2 + 200 + 200 + 119048 + 203252 + 197024 + 731707 + + + + + + + + + + + + + + + + -2 + -2 + 198 + 1682 + -2 + -2 + 1684 + 200 + 1002381 + 203252 + 119048 + 203252 + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.dni b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.dni new file mode 100644 index 000000000..faba72123 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.dni @@ -0,0 +1,250 @@ +[DebugChecksum] +Checksum=-126027898 +[CodeCoverage] +Enabled=_ 0 +[Stack] +FillEnabled=0 +OverflowWarningsEnabled=1 +WarningThreshold=90 +SpWarningsEnabled=1 +WarnLogOnly=1 +UseTrigger=1 +TriggerName=main +LimitSize=0 +ByteLimit=50 +[CallStack] +ShowArgs=0 +[Disassembly] +MixedMode=1 +[E1/E20] +BlockBits=15 +B0=1,0 +B1=1,1024 +B2=1,2048 +B3=1,3072 +StartEnabled=0 +StartSymbol= +StopEnabled=0 +StopSymbol= +RecordingCondition=0 +TraceMode=0 +TraceOutput=0 +TraceType=0 +TraceCapacity=0 +TraceRestart=0 +TraceTimeStamp=0 +TraceTimestampDivision=0 +TraceDataTransfer=1 +TraceStackOperation=1 +TraceStringOperation=1 +TraceArithmeticalOperation=1 +TraceLogicalOperation=1 +TraceBitOperation=1 +TraceFPU=1 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+ExtMemCondAccess_040=0 +ExtMemEndian_041=0 +ExtMemCondAccess_041=0 +ExtMemEndian_042=0 +ExtMemCondAccess_042=0 +ExtMemEndian_043=0 +ExtMemCondAccess_043=0 +ExtMemEndian_044=0 +ExtMemCondAccess_044=0 +ExtMemEndian_045=0 +ExtMemCondAccess_045=0 +ExtMemEndian_046=0 +ExtMemCondAccess_046=0 +ExtMemEndian_047=0 +ExtMemCondAccess_047=0 +ExtMemEndian_048=0 +ExtMemCondAccess_048=0 +ExtMemEndian_049=0 +ExtMemCondAccess_049=0 +ExtMemEndian_050=0 +ExtMemCondAccess_050=0 +ExtMemEndian_051=0 +ExtMemCondAccess_051=0 +ExtMemEndian_052=0 +ExtMemCondAccess_052=0 +ExtMemEndian_053=0 +ExtMemCondAccess_053=0 +ExtMemEndian_054=0 +ExtMemCondAccess_054=0 +InputClock=25.000000 +ICLK=240.000000 +AllowClkSrcChange=0 +WorkRamStart=4096 +ComunicationSelect=0 +UseExtal=1 +JtagClock=10 +FINE=2000000 +EraseFlash=1,0 +DebugFlags=0,0 +EmulatorMode=0 +PowerTargetFromEmulator=1 +Voltage=0 +UseExtFlashFile_0=0 +ExtFlashFile_0= +EraseExtFlashBeforeDownload_0=0 +UseExtFlashFile_1=0 +ExtFlashFile_1= +EraseExtFlashBeforeDownload_1=0 +UseExtFlashFile_2=0 +ExtFlashFile_2= +EraseExtFlashBeforeDownload_2=0 +UseExtFlashFile_3=0 +ExtFlashFile_3= +EraseExtFlashBeforeDownload_3=0 +NeedInitExtMem=0 +NeedInit=0 +[CallStackLog] +Enabled=0 +[CallStackStripe] +ShowTiming=1 +[InterruptLog] +LogEnabled=0 +GraphEnabled=0 +ShowTimeLog=1 +SumEnabled=0 +ShowTimeSum=1 +SumSortOrder=0 +[DataLog] +LogEnabled=0 +GraphEnabled=0 +ShowTimeLog=1 +SumEnabled=0 +ShowTimeSum=1 +[Breakpoints2] +Count=0 +[Interrupts] +Enabled=1 +[MemoryMap] +Enabled=0 +Base=0 +UseAuto=0 +TypeViolation=1 +UnspecRange=1 +ActionState=1 +[Simulator] +Freq=98000000 +[DataSample] +LogEnabled=0 +GraphEnabled=0 +ShowTimeLog=1 +[DriverProfiling] +Enabled=0 +Mode=1 +Graph=0 +Symbiont=0 +Exclusions= +[Log file] +LoggingEnabled=_ 0 +LogFile=_ "" +Category=_ 0 +[TermIOLog] +LoggingEnabled=_ 0 +LogFile=_ "" +[Breakpoints] +Count=0 +[Monitor Execution] +Leave target running=0 +Release target=0 +[Trace1] +Enabled=0 +ShowSource=1 +[Aliases] +Count=0 +SuppressDialog=0 diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.wsdt b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.wsdt new file mode 100644 index 000000000..26fa889f3 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.wsdt @@ -0,0 +1,77 @@ + + + + + + RTOSDemo/Debug + + + + + + + + + 310272727 + + + + + + + 20121632481 + + + 20 + 1622 + + + + + + + + + TabID-13537-752 + Workspace + Workspace + + + RTOSDemoRTOSDemo/Blinky_DemoRTOSDemo/FreeRTOS_SourceRTOSDemo/FreeRTOS_Source/portableRTOSDemo/Full_DemoRTOSDemo/Full_Demo/Standard_Demo_TasksRTOSDemo/cg_src + + + + 0 + + + TabID-29660-3316 + Build + Build + + + + TabID-19897-23353 + Debug Log + Debug-Log + + + + + 0 + + + + + + TextEditor$WS_DIR$\src\main.c000008351065106TextEditor$WS_DIR$\..\..\Source\tasks.c0000012964934349343TextEditor$WS_DIR$\..\Common\Minimal\IntQueue.c000003351674016740TextEditor$WS_DIR$\..\..\Source\portable\IAR\RX100\port.c0000000030100000010000001 + + + + + + + iaridepm.enu1-2-2627400-2-2200200119048203252239286639228-2-23131682-2-216843151002381320122119048203252 + + + + diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.wspos b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.wspos new file mode 100644 index 000000000..ecdc2c482 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.wspos @@ -0,0 +1,2 @@ +[MainWindow] +WindowPlacement=_ 519 0 1619 872 3 diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h index cca782733..50f3250c9 100644 --- a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h @@ -71,8 +71,14 @@ #ifndef FREERTOS_CONFIG_H #define FREERTOS_CONFIG_H -/* Hardware specifics. */ -#include "iodefine.h" +#ifdef __ICCRX__ + #include + #include +#endif + +#ifdef __GNUC__ + #include "iodefine.h" +#endif /*----------------------------------------------------------- * Application specific definitions. diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c index e6f42a206..5fc16a555 100644 --- a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c @@ -81,12 +81,6 @@ #include "IntQueueTimer.h" #include "IntQueue.h" -/* Hardware specifics. */ -#include "iodefine.h" - -void vIntQTimerISR0( void ) __attribute__ ((interrupt)); -void vIntQTimerISR1( void ) __attribute__ ((interrupt)); - #define tmrTIMER_0_1_FREQUENCY ( 2000UL ) #define tmrTIMER_2_3_FREQUENCY ( 2111UL ) @@ -98,7 +92,7 @@ void vInitialiseTimerForIntQueueTest( void ) /* Give write access. */ SYSTEM.PRCR.WORD = 0xa502; - /* Cascade two 8bit timer channels to generate the interrupts. + /* Cascade two 8bit timer channels to generate the interrupts. 8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are utilised for this test. */ @@ -121,11 +115,11 @@ void vInitialiseTimerForIntQueueTest( void ) /* 16 bit operation ( count from timer 1,2 ). */ TMR0.TCCR.BIT.CSS = 3; TMR2.TCCR.BIT.CSS = 3; - + /* Use PCLK as the input. */ TMR1.TCCR.BIT.CSS = 1; TMR3.TCCR.BIT.CSS = 1; - + /* Divide PCLK by 8. */ TMR1.TCCR.BIT.CKS = 2; TMR3.TCCR.BIT.CKS = 2; @@ -148,25 +142,46 @@ void vInitialiseTimerForIntQueueTest( void ) } /*-----------------------------------------------------------*/ -/* On vector 128. */ -void vIntQTimerISR0( void ) -{ - /* Enable interrupts to allow interrupt nesting. */ - __asm volatile( "setpsw i" ); +#ifdef __GNUC__ + + void vIntQTimerISR0( void ) __attribute__ ((interrupt)); + void vIntQTimerISR1( void ) __attribute__ ((interrupt)); + + void vIntQTimerISR0( void ) + { + /* Enable interrupts to allow interrupt nesting. */ + __asm volatile( "setpsw i" ); + + portYIELD_FROM_ISR( xFirstTimerHandler() ); + } + /*-----------------------------------------------------------*/ + void vIntQTimerISR1( void ) + { + /* Enable interrupts to allow interrupt nesting. */ + __asm volatile( "setpsw i" ); + + portYIELD_FROM_ISR( xSecondTimerHandler() ); + } + +#endif /* __GNUC__ */ + +#ifdef __ICCRX__ + +#pragma vector = VECT_TMR0_CMIA0 +__interrupt void vT0_1InterruptHandler( void ) +{ + __enable_interrupt(); portYIELD_FROM_ISR( xFirstTimerHandler() ); } /*-----------------------------------------------------------*/ -/* On vector 129. */ -void vIntQTimerISR1( void ) +#pragma vector = VECT_TMR2_CMIA2 +__interrupt void vT2_3InterruptHandler( void ) { - /* Enable interrupts to allow interrupt nesting. */ - __asm volatile( "setpsw i" ); - + __enable_interrupt(); portYIELD_FROM_ISR( xSecondTimerHandler() ); } - - +#endif /* __ICCRX__ */ diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest.S b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest_GCC.S similarity index 100% rename from FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest.S rename to FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest_GCC.S diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest_IAR.s b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest_IAR.s new file mode 100644 index 000000000..b5e790f4d --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest_IAR.s @@ -0,0 +1,269 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + PUBLIC _vRegTest1Implementation + PUBLIC _vRegTest2Implementation + + EXTERN _ulRegTest1CycleCount + EXTERN _ulRegTest2CycleCount + + RSEG CODE:CODE(4) + +_vRegTest1Implementation: + + /* Set each register to a known value. */ + MOV.L #0x33333333, R15 + MVTACHI R15 + MOV.L #0x44444444, R15 + MVTACLO R15 + MOV.L #1, R1 + MOV.L #2, R2 + MOV.L #3, R3 + MOV.L #4, R4 + MOV.L #5, R5 + MOV.L #6, R6 + MOV.L #7, R7 + MOV.L #8, R8 + MOV.L #9, R9 + MOV.L #10, R10 + MOV.L #11, R11 + MOV.L #12, R12 + MOV.L #13, R13 + MOV.L #14, R14 + MOV.L #15, R15 + + /* Loop, checking each iteration that each register still contains the + expected value. */ + TestLoop1: + + /* Push the registers that are going to get clobbered. */ + PUSHM R14-R15 + + /* Increment the loop counter to show this task is still getting CPU + time. */ + MOV.L #_ulRegTest1CycleCount, R14 + MOV.L [ R14 ], R15 + ADD #1, R15 + MOV.L R15, [ R14 ] + + /* Yield to extend the text coverage. Set the bit in the ITU SWINTR + register. */ + MOV.L #1, R14 + MOV.L #0872E0H, R15 + MOV.B R14, [R15] + NOP + NOP + + /* Check the accumulator value. */ + MVFACHI R15 + CMP #0x33333333, R15 + BNE RegTest2Error + MVFACMI R15 + CMP #0x33334444, R15 + BNE RegTest2Error + + /* Restore the clobbered registers. */ + POPM R14-R15 + + /* Now compare each register to ensure it still contains the value that + was set before this loop was entered. */ + CMP #1, R1 + BNE RegTest1Error + CMP #2, R2 + BNE RegTest1Error + CMP #3, R3 + BNE RegTest1Error + CMP #4, R4 + BNE RegTest1Error + CMP #5, R5 + BNE RegTest1Error + CMP #6, R6 + BNE RegTest1Error + CMP #7, R7 + BNE RegTest1Error + CMP #8, R8 + BNE RegTest1Error + CMP #9, R9 + BNE RegTest1Error + CMP #10, R10 + BNE RegTest1Error + CMP #11, R11 + BNE RegTest1Error + CMP #12, R12 + BNE RegTest1Error + CMP #13, R13 + BNE RegTest1Error + CMP #14, R14 + BNE RegTest1Error + CMP #15, R15 + BNE RegTest1Error + + /* All comparisons passed, start a new iteration of this loop. */ + BRA TestLoop1 + + /* A compare failed, just loop here so the loop counter stops + incrementing causing the check timer to indicate the error. */ + RegTest1Error: + BRA RegTest1Error + +/*-----------------------------------------------------------*/ + +_vRegTest2Implementation: + + /* Set each register to a known value. */ + MOV.L #0x11111111, R15 + MVTACHI R15 + MOV.L #0x22222222, R15 + MVTACLO R15 + MOV.L #100, R1 + MOV.L #200, R2 + MOV.L #300, R3 + MOV.L #400, R4 + MOV.L #500, R5 + MOV.L #600, R6 + MOV.L #700, R7 + MOV.L #800, R8 + MOV.L #900, R9 + MOV.L #1000, R10 + MOV.L #1001, R11 + MOV.L #1002, R12 + MOV.L #1003, R13 + MOV.L #1004, R14 + MOV.L #1005, R15 + + /* Loop, checking each iteration that each register still contains the + expected value. */ + TestLoop2: + + /* Push the registers that are going to get clobbered. */ + PUSHM R14-R15 + + /* Increment the loop counter to show this task is still getting CPU + time. */ + MOV.L #_ulRegTest2CycleCount, R14 + MOV.L [ R14 ], R15 + ADD #1, R15 + MOV.L R15, [ R14 ] + + /* Check the accumulator value. */ + MVFACHI R15 + CMP #0x11111111, R15 + BNE RegTest2Error + MVFACMI R15 + CMP #0x11112222, R15 + BNE RegTest2Error + + /* Restore the clobbered registers. */ + POPM R14-R15 + + /* Now compare each register to ensure it still contains the value that + was set before this loop was entered. */ + CMP #100, R1 + BNE RegTest2Error + CMP #200, R2 + BNE RegTest2Error + CMP #300, R3 + BNE RegTest2Error + CMP #400, R4 + BNE RegTest2Error + CMP #500, R5 + BNE RegTest2Error + CMP #600, R6 + BNE RegTest2Error + CMP #700, R7 + BNE RegTest2Error + CMP #800, R8 + BNE RegTest2Error + CMP #900, R9 + BNE RegTest2Error + CMP #1000, R10 + BNE RegTest2Error + CMP #1001, R11 + BNE RegTest2Error + CMP #1002, R12 + BNE RegTest2Error + CMP #1003, R13 + BNE RegTest2Error + CMP #1004, R14 + BNE RegTest2Error + CMP #1005, R15 + BNE RegTest2Error + + /* All comparisons passed, start a new iteration of this loop. */ + BRA TestLoop2 + + /* A compare failed, just loop here so the loop counter stops + incrementing causing the check timer to indicate the error. */ + RegTest2Error: + BRA RegTest2Error + +/*-----------------------------------------------------------*/ + + END + diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/PriorityDefinitions.h b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/PriorityDefinitions.h new file mode 100644 index 000000000..1516a0753 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/PriorityDefinitions.h @@ -0,0 +1,86 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef PRIORITY_DEFINITIONS_H +#define PRIORITY_DEFINITIONS_H + +#ifndef __IASMRX__ + #error This file is only intended to be included from the FreeRTOS IAR port layer assembly file. +#endif + +/* The interrupt priority used by the kernel itself for the tick interrupt and +the pended interrupt. This would normally be the lowest priority. */ +#define configKERNEL_INTERRUPT_PRIORITY 1 + +/* The maximum interrupt priority from which FreeRTOS API calls can be made. +Interrupts that use a priority above this will not be effected by anything the +kernel is doing. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +#endif /* PRIORITY_DEFINITIONS_H */ diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_macrodriver.h b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_macrodriver.h index 370d54947..0de90f97e 100644 --- a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_macrodriver.h +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_macrodriver.h @@ -2,15 +2,15 @@ * DISCLAIMER * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. * No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all -* applicable laws, including copyright laws. +* applicable laws, including copyright laws. * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY * LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, * INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR * ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability -* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer * @@ -75,7 +75,7 @@ typedef enum { Typedef definitions ***********************************************************************************************************************/ #ifndef __TYPEDEF__ - #ifndef _STD_USING_INT_TYPES + #if !defined( _STD_USING_INT_TYPES ) && !defined( _STDINT ) #define _SYS_INT_TYPES_H #ifndef _STD_USING_BIT_TYPES #ifndef __int8_t_defined diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/main.c b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/main.c index 4e39c6d07..9c0497643 100644 --- a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/main.c +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/main.c @@ -95,11 +95,10 @@ #include #include "r_cg_macrodriver.h" #include "r_cg_sci.h" -#include "r_rsk_async.h" /* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, or 0 to run the more comprehensive test and demo application. */ -#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1 /*-----------------------------------------------------------*/ @@ -253,6 +252,26 @@ const uint32_t ulEnableRegisterWrite = 0xA50BUL, ulDisableRegisterWrite = 0xA500 /* Reneable register protection. */ SYSTEM.PRCR.WORD = ulDisableRegisterWrite; } +/*-----------------------------------------------------------*/ + +#ifdef __ICCRX__ + + #include + + /* Called from the C start up code when compiled with IAR. */ + #pragma diag_suppress = Pm011 + int __low_level_init(void) + #pragma diag_default = Pm011 + { + extern void R_Systeminit( void ); + + __disable_interrupt(); + R_Systeminit(); + + return (int)(1U); + } + +#endif /* __ICCRX__ */ diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.HardwareDebuglinker b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.HardwareDebuglinker new file mode 100644 index 000000000..8174ece4b --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.HardwareDebuglinker @@ -0,0 +1,148 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.cproject b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.cproject new file mode 100644 index 000000000..8f22596ce --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.cproject @@ -0,0 +1,161 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.info b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.info new file mode 100644 index 000000000..209c49b60 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.info @@ -0,0 +1,7 @@ +TOOL_CHAIN=KPIT GNURX-ELF Toolchain +VERSION=v15.01 +TC_INSTALL=C:\Program Files (x86)\KPIT\GNURXv15.01-ELF\rx-elf\rx-elf\ +GCC_STRING=4.8-GNURX_v15.01 +VERSION_IDE= +E2STUDIO_VERSION=4.0.2.008 +ACTIVE_CONFIGURATION=HardwareDebug \ No newline at end of file diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.project b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.project new file mode 100644 index 000000000..7708d21e5 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.project @@ -0,0 +1,232 @@ + + + RTOSDemo + + + + + + com.renesas.cdt.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + com.renesas.cdt.core.kpitcnature + com.renesas.cdt.core.kpitccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + src/FreeRTOS_Source + 2 + FREERTOS_ROOT/FreeRTOS/Source + + + src/Main_Full/Standard_Demo_Tasks + 2 + FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal + + + src/Main_Full/Standard_Demo_Tasks/include + 2 + FREERTOS_ROOT/FreeRTOS/Demo/Common/include + + + + + 1442956878652 + src/FreeRTOS_Source + 6 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-croutine.c + + + + 1442956966430 + src/FreeRTOS_Source/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-MemMang + + + + 1442956966454 + src/FreeRTOS_Source/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-GCC + + + + 1442958159158 + src/Main_Full/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-BlockQ.c + + + + 1442958159162 + src/Main_Full/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-blocktim.c + + + + 1442958159166 + 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src/FreeRTOS_Source/portable/MemMang + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-heap_4.c + + + + + + FREERTOS_ROOT + $%7BPARENT-3-PROJECT_LOC%7D + + + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.settings/CodeGenerator/cgproject.cgp b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.settings/CodeGenerator/cgproject.cgp new file mode 100644 index 000000000..e35cf4b0a --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.settings/CodeGenerator/cgproject.cgp @@ -0,0 +1,184968 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+com.renesas.cdt.rx.HardwareDebug.Compiler.option.genCodeForRX610=false +com.renesas.cdt.rx.HardwareDebug.Compiler.option.genCodeForRX64M=true +com.renesas.cdt.rx.HardwareDebug.Compiler.option.generateRXas100output=false +com.renesas.cdt.rx.HardwareDebug.Compiler.option.macroDefines=__RX_LITTLE_ENDIAN__\=1; +com.renesas.cdt.rx.HardwareDebug.Compiler.option.make64bitDouble=false +com.renesas.cdt.rx.HardwareDebug.Linker.option.archiveLibraryFiles=${BuildArtifactFileBaseName};gcc; +com.renesas.cdt.rx.HardwareDebug.Linker.option.archiveSearchDirectories="${CONFIGDIR}";"${TCINSTALL}/lib/gcc/rx-elf/${GCC_VERSION}"; +com.renesas.cdt.rx.HardwareDebug.Linker.option.archiveSearchDirectories.1977851385="${CONFIGDIR}";"${TCINSTALL}/lib/gcc/rx-elf/${GCC_VERSION}"; +eclipse.preferences.version=1 diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.settings/language.settings.xml b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.settings/language.settings.xml new file mode 100644 index 000000000..3ab9b783c --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.settings/language.settings.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo_GCC.launch b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/RTOSDemo HardwareDebug.launch similarity index 65% rename from FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo_GCC.launch rename to FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/RTOSDemo HardwareDebug.launch index 6bbe77a1a..34d053165 100644 --- a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo_GCC.launch +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/RTOSDemo HardwareDebug.launch @@ -3,30 +3,48 @@ - + + - + - + - + + + + + + + + - + + + + + - + + + + + + + @@ -36,13 +54,15 @@ + + - + @@ -50,29 +70,32 @@ - + - + - + + - - + + + - + + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/RTOSDemo/.settings/CodeGenerator/cgprojectDatas.datas b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/custom.bat similarity index 100% rename from FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/RTOSDemo/.settings/CodeGenerator/cgprojectDatas.datas rename to FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/custom.bat diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/main.c b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/main.c new file mode 100644 index 000000000..56ce5a2c9 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/main.c @@ -0,0 +1,5 @@ + +int main( void ) +{ + return 0; +} diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/makefile.init b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/makefile.init new file mode 100644 index 000000000..0835091e2 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/makefile.init @@ -0,0 +1,5 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +PATH := $(PATH):C:\PROGRA~2\KPIT\GNURXV~1.01-\rx-elf\rx-elf\bin;C:\PROGRA~2\KPIT\GNURXV~1.01-\rx-elf\rx-elf\libexec\gcc\rx-elf\4.8-GNURX_v15.01 \ No newline at end of file diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Blinky_Demo/main_blinky.c new file mode 100644 index 000000000..0a919d156 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Blinky_Demo/main_blinky.c @@ -0,0 +1,230 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky style + * project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select + * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY + * in main.c. This file implements the simply blinky style version. + * + * NOTE 2: This file only contains the source code that is specific to the + * basic demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware are defined in main.c. + ****************************************************************************** + * + * main_blinky() creates one queue, and two tasks. It then starts the + * scheduler. + * + * The Queue Send Task: + * The queue send task is implemented by the prvQueueSendTask() function in + * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly + * block for 200 milliseconds, before sending the value 100 to the queue that + * was created within main_blinky(). Once the value is sent, the task loops + * back around to block for another 200 milliseconds...and so on. + * + * The Queue Receive Task: + * The queue receive task is implemented by the prvQueueReceiveTask() function + * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly + * blocks on attempts to read data from the queue that was created within + * main_blinky(). When data is received, the task checks the value of the + * data, and if the value equals the expected 100, toggles an LED. The 'block + * time' parameter passed to the queue receive function specifies that the + * task should be held in the Blocked state indefinitely to wait for data to + * be available on the queue. The queue receive task will only leave the + * Blocked state when the queue send task writes to the queue. As the queue + * send task writes to the queue every 200 milliseconds, the queue receive + * task leaves the Blocked state every 200 milliseconds, and therefore toggles + * the LED every 200 milliseconds. + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Priorities at which the tasks are created. */ +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The rate at which data is sent to the queue. The 200ms value is converted +to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) + +/* The number of items the queue can hold. This is 1 as the receive task +will remove items as they are added, meaning the send task should always find +the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) + +/*-----------------------------------------------------------*/ + +/* + * Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in + * main.c. + */ +void main_blinky( void ); + +/* + * The tasks as described in the comments at the top of this file. + */ +static void prvQueueReceiveTask( void *pvParameters ); +static void prvQueueSendTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The queue used by both tasks. */ +static QueueHandle_t xQueue = NULL; + +/*-----------------------------------------------------------*/ + +void main_blinky( void ) +{ + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + NULL, /* The parameter passed to the task - not used in this case. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ + + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was either insufficient FreeRTOS heap memory available for the idle + and/or timer tasks to be created, or vTaskStartScheduler() was called from + User mode. See the memory management section on the FreeRTOS web site for + more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + mode from which main() is called is set in the C start up code and must be + a privileged mode (not user mode). */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvQueueSendTask( void *pvParameters ) +{ +TickType_t xNextWakeTime; +const unsigned long ulValueToSend = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Place this task in the blocked state until it is time to run again. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + toggle the LED. 0 is used as the block time so the sending operation + will not block - it shouldn't need to block as the queue should always + be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } +} +/*-----------------------------------------------------------*/ + +static void prvQueueReceiveTask( void *pvParameters ) +{ +unsigned long ulReceivedValue; +const unsigned long ulExpectedValue = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + for( ;; ) + { + /* Wait until something arrives in the queue - this task will block + indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + is it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == ulExpectedValue ) + { +//_RB_ LED0 = !LED0; + ulReceivedValue = 0U; + } + } +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h new file mode 100644 index 000000000..f0c3446bf --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h @@ -0,0 +1,182 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/* Renesas hardware definition header. */ +#include "iodefine.h" + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 1 +#define configCPU_CLOCK_HZ ( 52000000UL ) /*_RB_ guess*/ +#define configPERIPHERAL_CLOCK_HZ ( 26000000UL ) /*_RB_ guess*/ +#define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 140 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 40 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 12 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_CO_ROUTINES 0 +#define configUSE_MUTEXES 1 +#define configGENERATE_RUN_TIME_STATS 0 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 0 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_QUEUE_SETS 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configMAX_PRIORITIES ( 7 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE ) + +/* The interrupt priority used by the kernel itself for the tick interrupt and +the pended interrupt. This would normally be the lowest priority. */ +#define configKERNEL_INTERRUPT_PRIORITY 1 + +/* The maximum interrupt priority from which FreeRTOS API calls can be made. +Interrupts that use a priority above this will not be effected by anything the +kernel is doing. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +/* The peripheral used to generate the tick interrupt is configured as part of +the application code. This constant should be set to the vector number of the +peripheral chosen. As supplied this is CMT0. */ +#define configTICK_VECTOR _CMT0_CMI0 + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTimerPendFunctionCall 1 + +void vAssertCalled( void ); +#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } + +/* Override some of the priorities set in the common demo tasks. This is +required to ensure flase positive timing errors are not reported. */ +#define bktPRIMARY_PRIORITY ( configMAX_PRIORITIES - 3 ) +#define bktSECONDARY_PRIORITY ( configMAX_PRIORITIES - 4 ) +#define intqHIGHER_PRIORITY ( configMAX_PRIORITIES - 3 ) + + +/*----------------------------------------------------------- + * Ethernet configuration. + *-----------------------------------------------------------*/ + +/* MAC address configuration. */ +#define configMAC_ADDR0 0x00 +#define configMAC_ADDR1 0x12 +#define configMAC_ADDR2 0x13 +#define configMAC_ADDR3 0x10 +#define configMAC_ADDR4 0x15 +#define configMAC_ADDR5 0x11 + +/* IP address configuration. */ +#define configIP_ADDR0 192 +#define configIP_ADDR1 168 +#define configIP_ADDR2 0 +#define configIP_ADDR3 200 + +/* Netmask configuration. */ +#define configNET_MASK0 255 +#define configNET_MASK1 255 +#define configNET_MASK2 255 +#define configNET_MASK3 0 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Main_Full/IntQueueTimer.c b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Main_Full/IntQueueTimer.c new file mode 100644 index 000000000..5fc16a555 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Main_Full/IntQueueTimer.c @@ -0,0 +1,187 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * This file contains the non-portable and therefore RX62N specific parts of + * the IntQueue standard demo task - namely the configuration of the timers + * that generate the interrupts and the interrupt entry points. + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo includes. */ +#include "IntQueueTimer.h" +#include "IntQueue.h" + +#define tmrTIMER_0_1_FREQUENCY ( 2000UL ) +#define tmrTIMER_2_3_FREQUENCY ( 2111UL ) + +void vInitialiseTimerForIntQueueTest( void ) +{ + /* Ensure interrupts do not start until full configuration is complete. */ + portENTER_CRITICAL(); + { + /* Give write access. */ + SYSTEM.PRCR.WORD = 0xa502; + + /* Cascade two 8bit timer channels to generate the interrupts. + 8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are + utilised for this test. */ + + /* Enable the timers. */ + SYSTEM.MSTPCRA.BIT.MSTPA5 = 0; + SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; + + /* Enable compare match A interrupt request. */ + TMR0.TCR.BIT.CMIEA = 1; + TMR2.TCR.BIT.CMIEA = 1; + + /* Clear the timer on compare match A. */ + TMR0.TCR.BIT.CCLR = 1; + TMR2.TCR.BIT.CCLR = 1; + + /* Set the compare match value. */ + TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 ); + TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 ); + + /* 16 bit operation ( count from timer 1,2 ). */ + TMR0.TCCR.BIT.CSS = 3; + TMR2.TCCR.BIT.CSS = 3; + + /* Use PCLK as the input. */ + TMR1.TCCR.BIT.CSS = 1; + TMR3.TCCR.BIT.CSS = 1; + + /* Divide PCLK by 8. */ + TMR1.TCCR.BIT.CKS = 2; + TMR3.TCCR.BIT.CKS = 2; + + /* Enable TMR 0, 2 interrupts. */ + TMR0.TCR.BIT.CMIEA = 1; + TMR2.TCR.BIT.CMIEA = 1; + + /* Set interrupt priority and enable. */ + IPR( TMR0, CMIA0 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1; + IR( TMR0, CMIA0 ) = 0U; + IEN( TMR0, CMIA0 ) = 1U; + + /* Do the same for TMR2, but to vector 129. */ + IPR( TMR2, CMIA2 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 2; + IR( TMR2, CMIA2 ) = 0U; + IEN( TMR2, CMIA2 ) = 1U; + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +#ifdef __GNUC__ + + void vIntQTimerISR0( void ) __attribute__ ((interrupt)); + void vIntQTimerISR1( void ) __attribute__ ((interrupt)); + + void vIntQTimerISR0( void ) + { + /* Enable interrupts to allow interrupt nesting. */ + __asm volatile( "setpsw i" ); + + portYIELD_FROM_ISR( xFirstTimerHandler() ); + } + /*-----------------------------------------------------------*/ + + void vIntQTimerISR1( void ) + { + /* Enable interrupts to allow interrupt nesting. */ + __asm volatile( "setpsw i" ); + + portYIELD_FROM_ISR( xSecondTimerHandler() ); + } + +#endif /* __GNUC__ */ + +#ifdef __ICCRX__ + +#pragma vector = VECT_TMR0_CMIA0 +__interrupt void vT0_1InterruptHandler( void ) +{ + __enable_interrupt(); + portYIELD_FROM_ISR( xFirstTimerHandler() ); +} +/*-----------------------------------------------------------*/ + +#pragma vector = VECT_TMR2_CMIA2 +__interrupt void vT2_3InterruptHandler( void ) +{ + __enable_interrupt(); + portYIELD_FROM_ISR( xSecondTimerHandler() ); +} + +#endif /* __ICCRX__ */ + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Main_Full/IntQueueTimer.h b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Main_Full/IntQueueTimer.h new file mode 100644 index 000000000..fcf9f8c1f --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Main_Full/IntQueueTimer.h @@ -0,0 +1,78 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef INT_QUEUE_TIMER_H +#define INT_QUEUE_TIMER_H + +void vInitialiseTimerForIntQueueTest( void ); +portBASE_TYPE xTimer0Handler( void ); +portBASE_TYPE xTimer1Handler( void ); + +#endif + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Main_Full/RegTest_GCC.S b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Main_Full/RegTest_GCC.S new file mode 100644 index 000000000..0d8d1e4cf --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Main_Full/RegTest_GCC.S @@ -0,0 +1,235 @@ +;/* +; FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. +; All rights reserved +; +; VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. +; +; *************************************************************************** +; * * +; * FreeRTOS provides completely free yet professionally developed, * +; * robust, strictly quality controlled, supported, and cross * +; * platform software that has become a de facto standard. * +; * * +; * Help yourself get started quickly and support the FreeRTOS * +; * project by purchasing a FreeRTOS tutorial book, reference * +; * manual, or both from: http://www.FreeRTOS.org/Documentation * +; * * +; * Thank you! * +; * * +; *************************************************************************** +; +; This file is part of the FreeRTOS distribution. +; +; FreeRTOS is free software; you can redistribute it and/or modify it under +; the terms of the GNU General Public License (version 2) as published by the +; Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. +; +; >>! NOTE: The modification to the GPL is included to allow you to distribute +; >>! a combined work that includes FreeRTOS without being obliged to provide +; >>! the source code for proprietary components outside of the FreeRTOS +; >>! kernel. +; +; FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY +; WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +; FOR A PARTICULAR PURPOSE. Full license text is available from the following +; link: http://www.freertos.org/a00114.html +; +; 1 tab == 4 spaces! +; +; *************************************************************************** +; * * +; * Having a problem? Start by reading the FAQ "My application does * +; * not run, what could be wrong?" * +; * * +; * http://www.FreeRTOS.org/FAQHelp.html * +; * * +; *************************************************************************** +; +; http://www.FreeRTOS.org - Documentation, books, training, latest versions, +; license and Real Time Engineers Ltd. contact details.; +; +; http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, +; including FreeRTOS+Trace - an indispensable productivity tool, a DOS +; compatible FAT file system, and our tiny thread aware UDP/IP stack. +; +; http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High +; Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS +; licenses offer ticketed support, indemnification and middleware. +; +; http://www.SafeRTOS.com - High Integrity Systems also provide a safety +; engineered and independently SIL3 certified version for use in safety and +; mission critical applications that require provable dependability. +; +; 1 tab == 4 spaces! +;*/ + + .global _vRegTest1Implementation + .global _vRegTest2Implementation + + .extern _ulRegTest1LoopCounter + .extern _ulRegTest2LoopCounter + + .text + + +;/* This function is explained in the comments at the top of main.c. */ +_vRegTest1Implementation: + + ; Put a known value in each register. + MOV.L #1, R1 + MOV.L #2, R2 + MOV.L #3, R3 + MOV.L #4, R4 + MOV.L #5, R5 + MOV.L #6, R6 + MOV.L #7, R7 + MOV.L #8, R8 + MOV.L #9, R9 + MOV.L #10, R10 + MOV.L #11, R11 + MOV.L #12, R12 + MOV.L #13, R13 + MOV.L #14, R14 + MOV.L #15, R15 + + ; Loop, checking each itteration that each register still contains the + ; expected value. +TestLoop1: + + ; Push the registers that are going to get clobbered. + PUSHM R14-R15 + + ; Increment the loop counter to show this task is still getting CPU time. + MOV.L #_ulRegTest1LoopCounter, R14 + MOV.L [ R14 ], R15 + ADD #1, R15 + MOV.L R15, [ R14 ] + + ; Yield to extend the text coverage. Set the bit in the ITU SWINTR register. + MOV.L #1, R14 + MOV.L #0872E0H, R15 + MOV.B R14, [R15] + NOP + NOP + + ; Restore the clobbered registers. + POPM R14-R15 + + ; Now compare each register to ensure it still contains the value that was + ; set before this loop was entered. + CMP #1, R1 + BNE RegTest1Error + CMP #2, R2 + BNE RegTest1Error + CMP #3, R3 + BNE RegTest1Error + CMP #4, R4 + BNE RegTest1Error + CMP #5, R5 + BNE RegTest1Error + CMP #6, R6 + BNE RegTest1Error + CMP #7, R7 + BNE RegTest1Error + CMP #8, R8 + BNE RegTest1Error + CMP #9, R9 + BNE RegTest1Error + CMP #10, R10 + BNE RegTest1Error + CMP #11, R11 + BNE RegTest1Error + CMP #12, R12 + BNE RegTest1Error + CMP #13, R13 + BNE RegTest1Error + CMP #14, R14 + BNE RegTest1Error + CMP #15, R15 + BNE RegTest1Error + + ; All comparisons passed, start a new itteratio of this loop. + BRA TestLoop1 + +RegTest1Error: + ; A compare failed, just loop here so the loop counter stops incrementing + ; causing the check task to indicate the error. + BRA RegTest1Error +;/*-----------------------------------------------------------*/ + +;/* This function is explained in the comments at the top of main.c. */ +_vRegTest2Implementation: + + ; Put a known value in each register. + MOV.L #10, R1 + MOV.L #20, R2 + MOV.L #30, R3 + MOV.L #40, R4 + MOV.L #50, R5 + MOV.L #60, R6 + MOV.L #70, R7 + MOV.L #80, R8 + MOV.L #90, R9 + MOV.L #100, R10 + MOV.L #110, R11 + MOV.L #120, R12 + MOV.L #130, R13 + MOV.L #140, R14 + MOV.L #150, R15 + + ; Loop, checking on each itteration that each register still contains the + ; expected value. +TestLoop2: + + ; Push the registers that are going to get clobbered. + PUSHM R14-R15 + + ; Increment the loop counter to show this task is still getting CPU time. + MOV.L #_ulRegTest2LoopCounter, R14 + MOV.L [ R14 ], R15 + ADD #1, R15 + MOV.L R15, [ R14 ] + + ; Restore the clobbered registers. + POPM R14-R15 + + CMP #10, R1 + BNE RegTest2Error + CMP #20, R2 + BNE RegTest2Error + CMP #30, R3 + BNE RegTest2Error + CMP #40, R4 + BNE RegTest2Error + CMP #50, R5 + BNE RegTest2Error + CMP #60, R6 + BNE RegTest2Error + CMP #70, R7 + BNE RegTest2Error + CMP #80, R8 + BNE RegTest2Error + CMP #90, R9 + BNE RegTest2Error + CMP #100, R10 + BNE RegTest2Error + CMP #110, R11 + BNE RegTest2Error + CMP #120, R12 + BNE RegTest2Error + CMP #130, R13 + BNE RegTest2Error + CMP #140, R14 + BNE RegTest2Error + CMP #150, R15 + BNE RegTest2Error + + ; All comparisons passed, start a new itteratio of this loop. + BRA TestLoop2 + +RegTest2Error: + ; A compare failed, just loop here so the loop counter stops incrementing + ; - causing the check task to indicate the error. + BRA RegTest2Error + + .END diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Main_Full/main_full.c b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Main_Full/main_full.c new file mode 100644 index 000000000..8aec86bc7 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Main_Full/main_full.c @@ -0,0 +1,499 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky + * style project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to + * select between the two. See the notes on using + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY in main.c. This file implements the + * comprehensive version. + * + * NOTE 2: This file only contains the source code that is specific to the + * full demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware, are defined in main.c. + * + ****************************************************************************** + * + * main_full() creates all the demo application tasks and software timers, then + * starts the scheduler. The web documentation provides more details of the + * standard demo application tasks, which provide no particular functionality, + * but do provide a good example of how to use the FreeRTOS API. + * + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "Reg test" tasks - These fill both the core and floating point registers with + * known values, then check that each register maintains its expected value for + * the lifetime of the task. Each task uses a different set of values. The reg + * test tasks execute with a very low priority, so get preempted very + * frequently. A register containing an unexpected value is indicative of an + * error in the context switching mechanism. + * + * "Check" task - The check task period is initially set to three seconds. The + * task checks that all the standard demo tasks, and the register check tasks, + * are not only still executing, but are executing without reporting any errors. + * If the check task discovers that a task has either stalled, or reported an + * error, then it changes its own execution period from the initial three + * seconds, to just 200ms. The check task also toggles an LED each time it is + * called. This provides a visual indication of the system status: If the LED + * toggles every three seconds, then no issues have been discovered. If the LED + * toggles every 200ms, then an issue has been discovered with at least one + * task. + */ + +/* Standard includes. */ +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "semphr.h" + +/* Standard demo application includes. */ +#include "flop.h" +#include "semtest.h" +#include "dynamic.h" +#include "BlockQ.h" +#include "blocktim.h" +#include "countsem.h" +#include "GenQTest.h" +#include "recmutex.h" +#include "death.h" +#include "partest.h" +#include "comtest2.h" +#include "serial.h" +#include "TimerDemo.h" +#include "QueueOverwrite.h" +#include "IntQueue.h" +#include "EventGroupsDemo.h" +#include "TaskNotify.h" +#include "IntSemTest.h" + +/* Priorities for the demo application tasks. */ +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) +#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3UL ) +#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY ) + +/* The priority used by the UART command console task. */ +#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) + +/* A block time of zero simply means "don't block". */ +#define mainDONT_BLOCK ( 0UL ) + +/* The period after which the check timer will expire, in ms, provided no errors +have been reported by any of the standard demo tasks. ms are converted to the +equivalent in ticks using the portTICK_PERIOD_MS constant. */ +#define mainNO_ERROR_CHECK_TASK_PERIOD ( 3000UL / portTICK_PERIOD_MS ) + +/* The period at which the check timer will expire, in ms, if an error has been +reported in one of the standard demo tasks. ms are converted to the equivalent +in ticks using the portTICK_PERIOD_MS constant. */ +#define mainERROR_CHECK_TASK_PERIOD ( 200UL / portTICK_PERIOD_MS ) + +/* Parameters that are passed into the register check tasks solely for the +purpose of ensuring parameters are passed into tasks correctly. */ +#define mainREG_TEST_1_PARAMETER ( ( void * ) 0x12121212UL ) +#define mainREG_TEST_2_PARAMETER ( ( void * ) 0x12345678UL ) + +/* The base period used by the timer test tasks. */ +#define mainTIMER_TEST_PERIOD ( 50 ) + +/*-----------------------------------------------------------*/ + +/* + * Entry point for the comprehensive demo (as opposed to the simple blinky + * demo). + */ +void main_full( void ); + +/* + * The full demo includes some functionality called from the tick hook. + */ +void vFullDemoTickHook( void ); + + /* + * The check task, as described at the top of this file. + */ +static void prvCheckTask( void *pvParameters ); + +/* + * Register check tasks, and the tasks used to write over and check the contents + * of the registers, as described at the top of this file. The nature of these + * files necessitates that they are written in assembly, but the entry points + * are kept in the C file for the convenience of checking the task parameter. + */ +static void prvRegTest1Task( void *pvParameters ); +static void prvRegTest2Task( void *pvParameters ); +void vRegTest1Implementation( void ); +void vRegTest2Implementation( void ); + +/* + * A high priority task that does nothing other than execute at a pseudo random + * time to ensure the other test tasks don't just execute in a repeating + * pattern. + */ +static void prvPseudoRandomiser( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The following two variables are used to communicate the status of the +register check tasks to the check task. If the variables keep incrementing, +then the register check tasks have not discovered any errors. If a variable +stops incrementing, then an error has been found. */ +volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; + +/* String for display in the web server. It is set to an error message if the +check task detects an error. */ +const char *pcStatusMessage = "All tasks running without error"; +/*-----------------------------------------------------------*/ + +void main_full( void ) +{ + /* Start all the other standard demo/test tasks. They have no particular + functionality, but do demonstrate how to use the FreeRTOS API and test the + kernel port. */ + vStartInterruptQueueTasks(); + vStartDynamicPriorityTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vCreateBlockTimeTasks(); + vStartCountingSemaphoreTasks(); + vStartGenericQueueTasks( tskIDLE_PRIORITY ); + vStartRecursiveMutexTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartMathTasks( mainFLOP_TASK_PRIORITY ); + vStartTimerDemoTask( mainTIMER_TEST_PERIOD ); + vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY ); + vStartEventGroupTasks(); + vStartTaskNotifyTask(); + vStartInterruptSemaphoreTasks(); + + /* Create the register check tasks, as described at the top of this file */ + xTaskCreate( prvRegTest1Task, "RegTst1", configMINIMAL_STACK_SIZE, mainREG_TEST_1_PARAMETER, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvRegTest2Task, "RegTst2", configMINIMAL_STACK_SIZE, mainREG_TEST_2_PARAMETER, tskIDLE_PRIORITY, NULL ); + + /* Create the task that just adds a little random behaviour. */ + xTaskCreate( prvPseudoRandomiser, "Rnd", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL ); + + /* Create the task that performs the 'check' functionality, as described at + the top of this file. */ + xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* The set of tasks created by the following function call have to be + created last as they keep account of the number of tasks they expect to see + running. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was either insufficient FreeRTOS heap memory available for the idle + and/or timer tasks to be created, or vTaskStartScheduler() was called from + User mode. See the memory management section on the FreeRTOS web site for + more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + mode from which main() is called is set in the C start up code and must be + a privileged mode (not user mode). */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvCheckTask( void *pvParameters ) +{ +TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD; +TickType_t xLastExecutionTime; +static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; +unsigned long ulErrorFound = pdFALSE; + + /* Just to stop compiler warnings. */ + ( void ) pvParameters; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. The onboard LED is toggled on each iteration. + If an error is detected then the delay period is decreased from + mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the + effect of increasing the rate at which the onboard LED toggles, and in so + doing gives visual feedback of the system status. */ + for( ;; ) + { + /* Delay until it is time to execute again. */ + vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod ); + + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none have detected an error. */ + if( xAreIntQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 0UL; + } + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 1UL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 2UL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 3UL; + } + + if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 4UL; + } + + if ( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 5UL; + } + + if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 6UL; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 7UL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 8UL; + } + + if( xAreTimerDemoTasksStillRunning( ( TickType_t ) mainNO_ERROR_CHECK_TASK_PERIOD ) != pdPASS ) + { + ulErrorFound |= 1UL << 9UL; + } + + if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 10UL; + } + + if( xIsQueueOverwriteTaskStillRunning() != pdPASS ) + { + ulErrorFound |= 1UL << 11UL; + } + + if( xAreEventGroupTasksStillRunning() != pdPASS ) + { + ulErrorFound |= 1UL << 12UL; + } + + if( xAreTaskNotificationTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 13UL; + } + + if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 14UL; + } + + /* Check that the register test 1 task is still running. */ + if( ulLastRegTest1Value == ulRegTest1LoopCounter ) + { + ulErrorFound |= 1UL << 15UL; + } + ulLastRegTest1Value = ulRegTest1LoopCounter; + + /* Check that the register test 2 task is still running. */ + if( ulLastRegTest2Value == ulRegTest2LoopCounter ) + { + ulErrorFound |= 1UL << 16UL; + } + ulLastRegTest2Value = ulRegTest2LoopCounter; + + /* Toggle the check LED to give an indication of the system status. If + the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then + everything is ok. A faster toggle indicates an error. */ +//_RB_ LED0 = !LED0; + + if( ulErrorFound != pdFALSE ) + { + /* An error has been detected in one of the tasks - flash the LED + at a higher frequency to give visible feedback that something has + gone wrong (it might just be that the loop back connector required + by the comtest tasks has not been fitted). */ + xDelayPeriod = mainERROR_CHECK_TASK_PERIOD; + pcStatusMessage = "Error found in at least one task."; + } + } +} +/*-----------------------------------------------------------*/ + +static void prvPseudoRandomiser( void *pvParameters ) +{ +const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL, ulMinDelay = ( 35 / portTICK_PERIOD_MS ); +volatile uint32_t ulNextRand = ( uint32_t ) &pvParameters, ulValue; + + /* This task does nothing other than ensure there is a little bit of + disruption in the scheduling pattern of the other tasks. Normally this is + done by generating interrupts at pseudo random times. */ + for( ;; ) + { + ulNextRand = ( ulMultiplier * ulNextRand ) + ulIncrement; + ulValue = ( ulNextRand >> 16UL ) & 0xffUL; + + if( ulValue < ulMinDelay ) + { + ulValue = ulMinDelay; + } + + vTaskDelay( ulValue ); + + while( ulValue > 0 ) + { + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + + ulValue--; + } + } +} +/*-----------------------------------------------------------*/ + +void vFullDemoTickHook( void ) +{ + /* The full demo includes a software timer demo/test that requires + prodding periodically from the tick interrupt. */ + vTimerPeriodicISRTests(); + + /* Call the periodic queue overwrite from ISR demo. */ + vQueueOverwritePeriodicISRDemo(); + + /* Call the periodic event group from ISR demo. */ + vPeriodicEventGroupsProcessing(); + + /* Use task notifications from an interrupt. */ + xNotifyTaskFromISR(); + + /* Use mutexes from interrupts. */ + vInterruptSemaphorePeriodicTest(); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +static void prvRegTest1Task( void *pvParameters ) +{ + if( pvParameters != mainREG_TEST_1_PARAMETER ) + { + /* The parameter did not contain the expected value. */ + for( ;; ) + { + /* Stop the tick interrupt so its obvious something has gone wrong. */ + taskDISABLE_INTERRUPTS(); + } + } + + /* This is an inline asm function that never returns. */ + vRegTest1Implementation(); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +static void prvRegTest2Task( void *pvParameters ) +{ + if( pvParameters != mainREG_TEST_2_PARAMETER ) + { + /* The parameter did not contain the expected value. */ + for( ;; ) + { + /* Stop the tick interrupt so its obvious something has gone wrong. */ + taskDISABLE_INTERRUPTS(); + } + } + + /* This is an inline asm function that never returns. */ + vRegTest2Implementation(); +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Renesas_Code/interrupt_handlers.c b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Renesas_Code/interrupt_handlers.c new file mode 100644 index 000000000..42c93041f --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Renesas_Code/interrupt_handlers.c @@ -0,0 +1,554 @@ +/***************************************************************/ +/* */ +/* PROJECT NAME : RTOSDemo */ +/* FILE : interrupt_handlers.c */ +/* DESCRIPTION : Interrupt Handler */ +/* CPU SERIES : RX200 */ +/* CPU TYPE : RX231 */ +/* */ +/* This file is generated by e2 studio. */ +/* */ +/***************************************************************/ + + + + +/************************************************************************/ +/* File Version: V1.00 */ +/* History : 0.50 (2014-09-18) [Hardware Manual Revision : 0.50] */ +/* : 1.00 (2015-05-18) [Hardware Manual Revision : 1.00] */ +/* Date Modified: 21/07/2015 */ +/************************************************************************/ + +#include "interrupt_handlers.h" + +// INT_Exception(Supervisor Instruction) +void INT_Excep_SuperVisorInst(void){/* brk(); */} + +// INT_Exception(Access Instruction) +void INT_Excep_AccessInst(void){/* brk(); */} + +// INT_Exception(Undefined Instruction) +void INT_Excep_UndefinedInst(void){/* brk(); */} + +// INT_Exception(Floating Point) +void INT_Excep_FloatingPoint(void){/* brk(); */} + +// INT_NMI +void INT_NonMaskableInterrupt(void){/* brk(); */} + +// INT_Dummy +void INT_Dummy(void){/* brk(); */} + +// BRK +void INT_Excep_BRK(void){ /* wait(); */ } + +// BSC BUSERR +void INT_Excep_BSC_BUSERR(void){/* brk(); */} + +// FCU FRDYI +void INT_Excep_FCU_FRDYI(void){/* brk(); */} + +// ICU SWINT +void INT_Excep_ICU_SWINT(void){/* brk(); */} + +// CMT0 CMI0 +void INT_Excep_CMT0_CMI0(void){/* brk(); */} + +// CMT1 CMI1 +void INT_Excep_CMT1_CMI1(void){/* brk(); */} + +// CMT2 CMI2 +void INT_Excep_CMT2_CMI2(void){/* brk(); */} + +// CMT3 CMI3 +void INT_Excep_CMT3_CMI3(void){/* brk(); */} + +// CAC FERRF +void INT_Excep_CAC_FERRF(void){/* brk(); */} + +// CAC MENDF +void INT_Excep_CAC_MENDF(void){/* brk(); */} + +// CAC OVFF +void INT_Excep_CAC_OVFF(void){/* brk(); */} + +// USB0 D0FIFO0 +void INT_Excep_USB0_D0FIFO0(void){/* brk(); */} + +// USB0 D1FIFO0 +void INT_Excep_USB0_D1FIFO0(void){/* brk(); */} + +// USB0 USBI0 +void INT_Excep_USB0_USBI0(void){/* brk(); */} + +// SDHI SBFAI +void INT_Excep_SDHI_SBFAI(void){/* brk(); */} + +// SDHI CDETI +void INT_Excep_SDHI_CDETI(void){/* brk(); */} + +// SDHI CACI +void INT_Excep_SDHI_CACI(void){/* brk(); */} + +// SDHI SDACI +void INT_Excep_SDHI_SDACI(void){/* brk(); */} + +// RSPI0 SPEI0 +void INT_Excep_RSPI0_SPEI0(void){/* brk(); */} + +// RSPI0 SPRI0 +void INT_Excep_RSPI0_SPRI0(void){/* brk(); */} + +// RSPI0 SPTI0 +void INT_Excep_RSPI0_SPTI0(void){/* brk(); */} + +// RSPI0 SPII0 +void INT_Excep_RSPI0_SPII0(void){/* brk(); */} + +// RSCAN COMFRXINT +void INT_Excep_RSCAN_COMFRXINT(void){/* brk(); */} + +// RSCAN RXFINT +void INT_Excep_RSCAN_RXFINT(void){/* brk(); */} + +// RSCAN TXINT +void INT_Excep_RSCAN_TXINT(void){/* brk(); */} + +// RSCAN CHERRINT +void INT_Excep_RSCAN_CHERRINT(void){/* brk(); */} + +// RSCAN GLERRINT +void INT_Excep_RSCAN_GLERRINT(void){/* brk(); */} + +// DOC DOPCF +void INT_Excep_DOC_DOPCF(void){/* brk(); */} + +// CMPB CMPB0 +void INT_Excep_CMPB_CMPB0(void){/* brk(); */} + +// CMPB CMPB1 +void INT_Excep_CMPB_CMPB1(void){/* brk(); */} + +// CTSU CTSUWR +void INT_Excep_CTSU_CTSUWR(void){/* brk(); */} + +// CTSU CTSURD +void INT_Excep_CTSU_CTSURD(void){/* brk(); */} + +// CTSU CTSUFN +void INT_Excep_CTSU_CTSUFN(void){/* brk(); */} + +// RTC CUP +void INT_Excep_RTC_CUP(void){/* brk(); */} + +// ICU IRQ0 +void INT_Excep_ICU_IRQ0(void){/* brk(); */} + +// ICU IRQ1 +void INT_Excep_ICU_IRQ1(void){/* brk(); */} + +// ICU IRQ2 +void INT_Excep_ICU_IRQ2(void){/* brk(); */} + +// ICU IRQ3 +void INT_Excep_ICU_IRQ3(void){/* brk(); */} + +// ICU IRQ4 +void INT_Excep_ICU_IRQ4(void){/* brk(); */} + +// ICU IRQ5 +void INT_Excep_ICU_IRQ5(void){/* brk(); */} + +// ICU IRQ6 +void INT_Excep_ICU_IRQ6(void){/* brk(); */} + +// ICU IRQ7 +void INT_Excep_ICU_IRQ7(void){/* brk(); */} + +// ELC ELSR8I +void INT_Excep_ELC_ELSR8I(void){/* brk(); */} + +// LVD LVD1 +void INT_Excep_LVD_LVD1(void){/* brk(); */} + +// LVD LVD2 +void INT_Excep_LVD_LVD2(void){/* brk(); */} + +// CMPA CMPA1 +//void INT_Excep_CMPA_CMPA1(void){/* brk(); */} + +// CMPA CMPA2 +//void INT_Excep_CMPA_CMPA2(void){/* brk(); */} + +// USB0 USBR0 +void INT_Excep_USB0_USBR0(void){/* brk(); */} + +// VBATT VBTLVDI +void INT_Excep_VBATT_VBTLVDI(void){/* brk(); */} + +// RTC ALM +void INT_Excep_RTC_ALM(void){/* brk(); */} + +// RTC PRD +void INT_Excep_RTC_PRD(void){/* brk(); */} + +// S12AD S12ADI0 +void INT_Excep_S12AD_S12ADI0(void){/* brk(); */} + +// S12AD GBADI +void INT_Excep_S12AD_GBADI(void){/* brk(); */} + +// CMPB1 CMPB2 +void INT_Excep_CMPB1_CMPB2(void){/* brk(); */} + +// CMPB1 CMPB3 +void INT_Excep_CMPB1_CMPB3(void){/* brk(); */} + +// ELC ELSR18I +void INT_Excep_ELC_ELSR18I(void){/* brk(); */} + +// ELC ELSR19I +void INT_Excep_ELC_ELSR19I(void){/* brk(); */} + +// SSI0 SSIF0 +void INT_Excep_SSI0_SSIF0(void){/* brk(); */} + +// SSI0 SSIRXI0 +void INT_Excep_SSI0_SSIRXI0(void){/* brk(); */} + +// SSI0 SSITXI0 +void INT_Excep_SSI0_SSITXI0(void){/* brk(); */} + +// SECURITY RD +void INT_Excep_SECURITY_RD(void){/* brk(); */} + +// SECURITY WR +void INT_Excep_SECURITY_WR(void){/* brk(); */} + +// SECURITY ERR +void INT_Excep_SECURITY_ERR(void){/* brk(); */} + +// MTU0 TGIA0 +void INT_Excep_MTU0_TGIA0(void){/* brk(); */} + +// MTU0 TGIB0 +void INT_Excep_MTU0_TGIB0(void){/* brk(); */} + +// MTU0 TGIC0 +void INT_Excep_MTU0_TGIC0(void){/* brk(); */} + +// MTU0 TGID0 +void INT_Excep_MTU0_TGID0(void){/* brk(); */} + +// MTU0 TCIV0 +void INT_Excep_MTU0_TCIV0(void){/* brk(); */} + +// MTU0 TGIE0 +void INT_Excep_MTU0_TGIE0(void){/* brk(); */} + +// MTU0 TGIF0 +void INT_Excep_MTU0_TGIF0(void){/* brk(); */} + +// MTU1 TGIA1 +void INT_Excep_MTU1_TGIA1(void){/* brk(); */} + +// MTU1 TGIB1 +void INT_Excep_MTU1_TGIB1(void){/* brk(); */} + +// MTU1 TCIV1 +void INT_Excep_MTU1_TCIV1(void){/* brk(); */} + +// MTU1 TCIU1 +void INT_Excep_MTU1_TCIU1(void){/* brk(); */} + +// MTU2 TGIA2 +void INT_Excep_MTU2_TGIA2(void){/* brk(); */} + +// MTU2 TGIB2 +void INT_Excep_MTU2_TGIB2(void){/* brk(); */} + +// MTU2 TCIV2 +void INT_Excep_MTU2_TCIV2(void){/* brk(); */} + +// MTU2 TCIU2 +void INT_Excep_MTU2_TCIU2(void){/* brk(); */} + +// MTU3 TGIA3 +void INT_Excep_MTU3_TGIA3(void){/* brk(); */} + +// MTU3 TGIB3 +void INT_Excep_MTU3_TGIB3(void){/* brk(); */} + +// MTU3 TGIC3 +void INT_Excep_MTU3_TGIC3(void){/* brk(); */} + +// MTU3 TGID3 +void INT_Excep_MTU3_TGID3(void){/* brk(); */} + +// MTU3 TCIV3 +void INT_Excep_MTU3_TCIV3(void){/* brk(); */} + +// MTU4 TGIA4 +void INT_Excep_MTU4_TGIA4(void){/* brk(); */} + +// MTU4 TGIB4 +void INT_Excep_MTU4_TGIB4(void){/* brk(); */} + +// MTU4 TGIC4 +void INT_Excep_MTU4_TGIC4(void){/* brk(); */} + +// MTU4 TGID4 +void INT_Excep_MTU4_TGID4(void){/* brk(); */} + +// MTU4 TCIV4 +void INT_Excep_MTU4_TCIV4(void){/* brk(); */} + +// MTU5 TGIU5 +void INT_Excep_MTU5_TGIU5(void){/* brk(); */} + +// MTU5 TGIV5 +void INT_Excep_MTU5_TGIV5(void){/* brk(); */} + +// MTU5 TGIW5 +void INT_Excep_MTU5_TGIW5(void){/* brk(); */} + +// TPU0 TGI0A +void INT_Excep_TPU0_TGI0A(void){/* brk(); */} + +// TPU0 TGI0B +void INT_Excep_TPU0_TGI0B(void){/* brk(); */} + +// TPU0 TGI0C +void INT_Excep_TPU0_TGI0C(void){/* brk(); */} + +// TPU0 TGI0D +void INT_Excep_TPU0_TGI0D(void){/* brk(); */} + +// TPU0 TCI0V +void INT_Excep_TPU0_TCI0V(void){/* brk(); */} + +// TPU1 TGI1A +void INT_Excep_TPU1_TGI1A(void){/* brk(); */} + +// TPU1 TGI1B +void INT_Excep_TPU1_TGI1B(void){/* brk(); */} + +// TPU1 TCI1V +void INT_Excep_TPU1_TCI1V(void){/* brk(); */} + +// TPU1 TCI1U +void INT_Excep_TPU1_TCI1U(void){/* brk(); */} + +// TPU2 TGI2A +void INT_Excep_TPU2_TGI2A(void){/* brk(); */} + +// TPU2 TGI2B +void INT_Excep_TPU2_TGI2B(void){/* brk(); */} + +// TPU2 TCI2V +void INT_Excep_TPU2_TCI2V(void){/* brk(); */} + +// TPU2 TCI2U +void INT_Excep_TPU2_TCI2U(void){/* brk(); */} + +// TPU3 TGI3A +void INT_Excep_TPU3_TGI3A(void){/* brk(); */} + +// TPU3 TGI3B +void INT_Excep_TPU3_TGI3B(void){/* brk(); */} + +// TPU3 TGI3C +void INT_Excep_TPU3_TGI3C(void){/* brk(); */} + +// TPU3 TGI3D +void INT_Excep_TPU3_TGI3D(void){/* brk(); */} + +// TPU3 TCI3V +void INT_Excep_TPU3_TCI3V(void){/* brk(); */} + +// TPU4 TGI4A +void INT_Excep_TPU4_TGI4A(void){/* brk(); */} + +// TPU4 TGI4B +void INT_Excep_TPU4_TGI4B(void){/* brk(); */} + +// TPU4 TCI4V +void INT_Excep_TPU4_TCI4V(void){/* brk(); */} + +// TPU4 TCI4U +void INT_Excep_TPU4_TCI4U(void){/* brk(); */} + +// TPU5 TGI5A +void INT_Excep_TPU5_TGI5A(void){/* brk(); */} + +// TPU5 TGI5B +void INT_Excep_TPU5_TGI5B(void){/* brk(); */} + +// TPU5 TCI5V +void INT_Excep_TPU5_TCI5V(void){/* brk(); */} + +// TPU5 TCI5U +void INT_Excep_TPU5_TCI5U(void){/* brk(); */} + +// POE OEI1 +void INT_Excep_POE_OEI1(void){/* brk(); */} + +// POE OEI2 +void INT_Excep_POE_OEI2(void){/* brk(); */} + +// TMR0 CMIA0 +void INT_Excep_TMR0_CMIA0(void){/* brk(); */} + +// TMR0 CMIB0 +void INT_Excep_TMR0_CMIB0(void){/* brk(); */} + +// TMR0 OVI0 +void INT_Excep_TMR0_OVI0(void){/* brk(); */} + +// TMR1 CMIA1 +void INT_Excep_TMR1_CMIA1(void){/* brk(); */} + +// TMR1 CMIB1 +void INT_Excep_TMR1_CMIB1(void){/* brk(); */} + +// TMR1 OVI1 +void INT_Excep_TMR1_OVI1(void){/* brk(); */} + +// TMR2 CMIA2 +void INT_Excep_TMR2_CMIA2(void){/* brk(); */} + +// TMR2 CMIB2 +void INT_Excep_TMR2_CMIB2(void){/* brk(); */} + +// TMR2 OVI2 +void INT_Excep_TMR2_OVI2(void){/* brk(); */} + +// TMR3 CMIA3 +void INT_Excep_TMR3_CMIA3(void){/* brk(); */} + +// TMR3 CMIB3 +void INT_Excep_TMR3_CMIB3(void){/* brk(); */} + +// TMR3 OVI3 +void INT_Excep_TMR3_OVI3(void){/* brk(); */} + +// DMAC DMAC0I +void INT_Excep_DMAC_DMAC0I(void){/* brk(); */} + +// DMAC DMAC1I +void INT_Excep_DMAC_DMAC1I(void){/* brk(); */} + +// DMAC DMAC2I +void INT_Excep_DMAC_DMAC2I(void){/* brk(); */} + +// DMAC DMAC3I +void INT_Excep_DMAC_DMAC3I(void){/* brk(); */} + +// SCI0 ERI0 +void INT_Excep_SCI0_ERI0(void){/* brk(); */} + +// SCI0 RXI0 +void INT_Excep_SCI0_RXI0(void){/* brk(); */} + +// SCI0 TXI0 +void INT_Excep_SCI0_TXI0(void){/* brk(); */} + +// SCI0 TEI0 +void INT_Excep_SCI0_TEI0(void){/* brk(); */} + +// SCI1 ERI1 +void INT_Excep_SCI1_ERI1(void){/* brk(); */} + +// SCI1 RXI1 +void INT_Excep_SCI1_RXI1(void){/* brk(); */} + +// SCI1 TXI1 +void INT_Excep_SCI1_TXI1(void){/* brk(); */} + +// SCI1 TEI1 +void INT_Excep_SCI1_TEI1(void){/* brk(); */} + +// SCI5 ERI5 +void INT_Excep_SCI5_ERI5(void){/* brk(); */} + +// SCI5 RXI5 +void INT_Excep_SCI5_RXI5(void){/* brk(); */} + +// SCI5 TXI5 +void INT_Excep_SCI5_TXI5(void){/* brk(); */} + +// SCI5 TEI5 +void INT_Excep_SCI5_TEI5(void){/* brk(); */} + +// SCI6 ERI6 +void INT_Excep_SCI6_ERI6(void){/* brk(); */} + +// SCI6 RXI6 +void INT_Excep_SCI6_RXI6(void){/* brk(); */} + +// SCI6 TXI6 +void INT_Excep_SCI6_TXI6(void){/* brk(); */} + +// SCI6 TEI6 +void INT_Excep_SCI6_TEI6(void){/* brk(); */} + +// SCI8 ERI8 +void INT_Excep_SCI8_ERI8(void){/* brk(); */} + +// SCI8 RXI8 +void INT_Excep_SCI8_RXI8(void){/* brk(); */} + +// SCI8 TXI8 +void INT_Excep_SCI8_TXI8(void){/* brk(); */} + +// SCI8 TEI8 +void INT_Excep_SCI8_TEI8(void){/* brk(); */} + +// SCI9 ERI9 +void INT_Excep_SCI9_ERI9(void){/* brk(); */} + +// SCI9 RXI9 +void INT_Excep_SCI9_RXI9(void){/* brk(); */} + +// SCI9 TXI9 +void INT_Excep_SCI9_TXI9(void){/* brk(); */} + +// SCI9 TEI9 +void INT_Excep_SCI9_TEI9(void){/* brk(); */} + +// SCI12 ERI12 +void INT_Excep_SCI12_ERI12(void){/* brk(); */} + +// SCI12 RXI12 +void INT_Excep_SCI12_RXI12(void){/* brk(); */} + +// SCI12 TXI12 +void INT_Excep_SCI12_TXI12(void){/* brk(); */} + +// SCI12 TEI12 +void INT_Excep_SCI12_TEI12(void){/* brk(); */} + +// SCI12 SCIX0 +void INT_Excep_SCI12_SCIX0(void){/* brk(); */} + +// SCI12 SCIX1 +void INT_Excep_SCI12_SCIX1(void){/* brk(); */} + +// SCI12 SCIX2 +void INT_Excep_SCI12_SCIX2(void){/* brk(); */} + +// SCI12 SCIX3 +void INT_Excep_SCI12_SCIX3(void){/* brk(); */} + +// RIIC0 EEI0 +void INT_Excep_RIIC0_EEI0(void){/* brk(); */} + +// RIIC0 RXI0 +void INT_Excep_RIIC0_RXI0(void){/* brk(); */} + +// RIIC0 TXI0 +void INT_Excep_RIIC0_TXI0(void){/* brk(); */} + +// RIIC0 TEI0 +void INT_Excep_RIIC0_TEI0(void){/* brk(); */} diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Renesas_Code/interrupt_handlers.h b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Renesas_Code/interrupt_handlers.h new file mode 100644 index 000000000..ae7bda441 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Renesas_Code/interrupt_handlers.h @@ -0,0 +1,839 @@ +/***************************************************************/ +/* */ +/* PROJECT NAME : RTOSDemo */ +/* FILE : interrupt_handlers.h */ +/* DESCRIPTION : Interrupt Handler Declarations */ +/* CPU SERIES : RX200 */ +/* CPU TYPE : RX231 */ +/* */ +/* This file is generated by e2 studio. */ +/* */ +/***************************************************************/ + + + + +/************************************************************************/ +/* File Version : V1.00 */ +/* History : 0.50 (2014-09-18) [Hardware Manual Revision : 0.50] */ +/* : 1.00 (2015-05-18) [Hardware Manual Revision : 1.00] */ +/* Date Modified: 21/07/2015 */ +/************************************************************************/ + +#ifndef INTERRUPT_HANDLERS_H +#define INTERRUPT_HANDLERS_H + +// INT_Exception(Supervisor Instruction) + +void INT_Excep_SuperVisorInst(void) __attribute__ ((interrupt)); + +// INT_Exception(Access Instruction) + +void INT_Excep_AccessInst(void) __attribute__ ((interrupt)); + +// INT_Exception(Undefined Instruction) + +void INT_Excep_UndefinedInst(void) __attribute__ ((interrupt)); + +// INT_Exception(Floating Point) + +void INT_Excep_FloatingPoint(void) __attribute__ ((interrupt)); + +// INT_NMI + +void INT_NonMaskableInterrupt(void) __attribute__ ((interrupt)); + +// INT_Dummy + +void INT_Dummy(void) __attribute__ ((interrupt)); + +// BRK + +void INT_Excep_BRK(void) __attribute__ ((interrupt)); + +// vector 1 reserved +// vector 2 reserved +// vector 3 reserved +// vector 4 reserved +// vector 5 reserved +// vector 6 reserved +// vector 7 reserved +// vector 8 reserved +// vector 9 reserved +// vector 10 reserved +// vector 11 reserved +// vector 12 reserved +// vector 13 reserved +// vector 14 reserved +// vector 15 reserved + +// BSC BUSERR + +void INT_Excep_BSC_BUSERR(void) __attribute__ ((interrupt)); + +// vector 17 reserved +// vector 18 reserved +// vector 19 reserved +// vector 20 reserved +// vector 21 reserved +// vector 22 reserved + +// FCU FRDYI + +void INT_Excep_FCU_FRDYI(void) __attribute__ ((interrupt)); + +// vector 24 reserved +// vector 25 reserved +// vector 26 reserved + +// ICU SWINT + +void INT_Excep_ICU_SWINT(void) __attribute__ ((interrupt)); + +// CMT0 CMI0 + +void INT_Excep_CMT0_CMI0(void) __attribute__ ((interrupt)); + +// CMT1 CMI1 + +void INT_Excep_CMT1_CMI1(void) __attribute__ ((interrupt)); + +// CMT2 CMI2 + +void INT_Excep_CMT2_CMI2(void) __attribute__ ((interrupt)); + +// CMT3 CMI3 + +void INT_Excep_CMT3_CMI3(void) __attribute__ ((interrupt)); + +// CAC FERRF + +void INT_Excep_CAC_FERRF(void) __attribute__ ((interrupt)); + +// CAC MENDF + +void INT_Excep_CAC_MENDF(void) __attribute__ ((interrupt)); + +// CAC OVFF + +void INT_Excep_CAC_OVFF(void) __attribute__ ((interrupt)); + +// vector 35 reserved + +// USB0 D0FIFO0 + +void INT_Excep_USB0_D0FIFO0(void) __attribute__ ((interrupt)); + +// USB0 D1FIFO0 + +void INT_Excep_USB0_D1FIFO0(void) __attribute__ ((interrupt)); + +// USB0 USBI0 + +void INT_Excep_USB0_USBI0(void) __attribute__ ((interrupt)); + +// vector 39 reserved + +// SDHI SBFAI + +void INT_Excep_SDHI_SBFAI(void) __attribute__ ((interrupt)); + +// SDHI CDETI + +void INT_Excep_SDHI_CDETI(void) __attribute__ ((interrupt)); + +// SDHI CACI + +void INT_Excep_SDHI_CACI(void) __attribute__ ((interrupt)); + +// SDHI SDACI + +void INT_Excep_SDHI_SDACI(void) __attribute__ ((interrupt)); + +// RSPI0 SPEI0 + +void INT_Excep_RSPI0_SPEI0(void) __attribute__ ((interrupt)); + +// RSPI0 SPRI0 + +void INT_Excep_RSPI0_SPRI0(void) __attribute__ ((interrupt)); + +// RSPI0 SPTI0 + +void INT_Excep_RSPI0_SPTI0(void) __attribute__ ((interrupt)); + +// RSPI0 SPII0 + +void INT_Excep_RSPI0_SPII0(void) __attribute__ ((interrupt)); + +// vector 48 reserved +// vector 49 reserved +// vector 50 reserved +// vector 51 reserved + +// RSCAN COMFRXINT + +void INT_Excep_RSCAN_COMFRXINT(void) __attribute__ ((interrupt)); + +// RSCAN RXFINT + +void INT_Excep_RSCAN_RXFINT(void) __attribute__ ((interrupt)); + +// RSCAN TXINT + +void INT_Excep_RSCAN_TXINT(void) __attribute__ ((interrupt)); + +// RSCAN CHERRINT + +void INT_Excep_RSCAN_CHERRINT(void) __attribute__ ((interrupt)); + +// RSCAN GLERRINT + +void INT_Excep_RSCAN_GLERRINT(void) __attribute__ ((interrupt)); + +// DOC DOPCF + +void INT_Excep_DOC_DOPCF(void) __attribute__ ((interrupt)); + +// CMPB CMPB0 + +void INT_Excep_CMPB_CMPB0(void) __attribute__ ((interrupt)); + +// CMPB CMPB1 + +void INT_Excep_CMPB_CMPB1(void) __attribute__ ((interrupt)); + +// CTSU CTSUWR + +void INT_Excep_CTSU_CTSUWR(void) __attribute__ ((interrupt)); + +// CTSU CTSURD + +void INT_Excep_CTSU_CTSURD(void) __attribute__ ((interrupt)); + +// CTSU CTSUFN + +void INT_Excep_CTSU_CTSUFN(void) __attribute__ ((interrupt)); + +// RTC CUP + +void INT_Excep_RTC_CUP(void) __attribute__ ((interrupt)); + +// ICU IRQ0 + +void INT_Excep_ICU_IRQ0(void) __attribute__ ((interrupt)); + +// ICU IRQ1 + +void INT_Excep_ICU_IRQ1(void) __attribute__ ((interrupt)); + +// ICU IRQ2 + +void INT_Excep_ICU_IRQ2(void) __attribute__ ((interrupt)); + +// ICU IRQ3 + +void INT_Excep_ICU_IRQ3(void) __attribute__ ((interrupt)); + +// ICU IRQ4 + +void INT_Excep_ICU_IRQ4(void) __attribute__ ((interrupt)); + +// ICU IRQ5 + +void INT_Excep_ICU_IRQ5(void) __attribute__ ((interrupt)); + +// ICU IRQ6 + +void INT_Excep_ICU_IRQ6(void) __attribute__ ((interrupt)); + +// ICU IRQ7 + +void INT_Excep_ICU_IRQ7(void) __attribute__ ((interrupt)); + +// vector 72 reserved +// vector 73 reserved +// vector 74 reserved +// vector 75 reserved +// vector 76 reserved +// vector 77 reserved +// vector 78 reserved +// vector 79 reserved + +// ELC ELSR8I + +void INT_Excep_ELC_ELSR8I(void) __attribute__ ((interrupt)); + +// vector 81 reserved +// vector 82 reserved +// vector 83 reserved +// vector 84 reserved +// vector 85 reserved +// vector 86 reserved +// vector 87 reserved + +// LVD LVD1 + +void INT_Excep_LVD_LVD1(void) __attribute__ ((interrupt)); + +// LVD LVD2 + +void INT_Excep_LVD_LVD2(void) __attribute__ ((interrupt)); + +// CMPA CMPA1 + +//void INT_Excep_CMPA_CMPA1(void) __attribute__ ((interrupt)); + +// CMPA CMPA2 + +//void INT_Excep_CMPA_CMPA2(void) __attribute__ ((interrupt)); + +// USB0 USBR0 + +void INT_Excep_USB0_USBR0(void) __attribute__ ((interrupt)); + +// VBATT VBTLVDI + +void INT_Excep_VBATT_VBTLVDI(void) __attribute__ ((interrupt)); + +// RTC ALM + +void INT_Excep_RTC_ALM(void) __attribute__ ((interrupt)); + +// RTC PRD + +void INT_Excep_RTC_PRD(void) __attribute__ ((interrupt)); + +// vector 94 reserved +// vector 95 reserved +// vector 96 reserved +// vector 97 reserved +// vector 98 reserved +// vector 99 reserved +// vector 100 reserved +// vector 101 reserved + +// S12AD S12ADI0 + +void INT_Excep_S12AD_S12ADI0(void) __attribute__ ((interrupt)); + +// S12AD GBADI + +void INT_Excep_S12AD_GBADI(void) __attribute__ ((interrupt)); + +// CMPB1 CMPB2 + +void INT_Excep_CMPB1_CMPB2(void) __attribute__ ((interrupt)); + +// CMPB1 CMPB3 + +void INT_Excep_CMPB1_CMPB3(void) __attribute__ ((interrupt)); + +// ELC ELSR18I + +void INT_Excep_ELC_ELSR18I(void) __attribute__ ((interrupt)); + +// ELC ELSR19I + +void INT_Excep_ELC_ELSR19I(void) __attribute__ ((interrupt)); + +// SSI0 SSIF0 + +void INT_Excep_SSI0_SSIF0(void) __attribute__ ((interrupt)); + +// SSI0 SSIRXI0 + +void INT_Excep_SSI0_SSIRXI0(void) __attribute__ ((interrupt)); + +// SSI0 SSITXI0 + +void INT_Excep_SSI0_SSITXI0(void) __attribute__ ((interrupt)); + +// SECURITY RD + +void INT_Excep_SECURITY_RD(void) __attribute__ ((interrupt)); + +// SECURITY WR + +void INT_Excep_SECURITY_WR(void) __attribute__ ((interrupt)); + +// SECURITY ERR + +void INT_Excep_SECURITY_ERR(void) __attribute__ ((interrupt)); + +// MTU0 TGIA0 + +void INT_Excep_MTU0_TGIA0(void) __attribute__ ((interrupt)); + +// MTU0 TGIB0 + +void INT_Excep_MTU0_TGIB0(void) __attribute__ ((interrupt)); + +// MTU0 TGIC0 + +void INT_Excep_MTU0_TGIC0(void) __attribute__ ((interrupt)); + +// MTU0 TGID0 + +void INT_Excep_MTU0_TGID0(void) __attribute__ ((interrupt)); + +// MTU0 TCIV0 + +void INT_Excep_MTU0_TCIV0(void) __attribute__ ((interrupt)); + +// MTU0 TGIE0 + +void INT_Excep_MTU0_TGIE0(void) __attribute__ ((interrupt)); + +// MTU0 TGIF0 + +void INT_Excep_MTU0_TGIF0(void) __attribute__ ((interrupt)); + +// MTU1 TGIA1 + +void INT_Excep_MTU1_TGIA1(void) __attribute__ ((interrupt)); + +// MTU1 TGIB1 + +void INT_Excep_MTU1_TGIB1(void) __attribute__ ((interrupt)); + +// MTU1 TCIV1 + +void INT_Excep_MTU1_TCIV1(void) __attribute__ ((interrupt)); + +// MTU1 TCIU1 + +void INT_Excep_MTU1_TCIU1(void) __attribute__ ((interrupt)); + +// MTU2 TGIA2 + +void INT_Excep_MTU2_TGIA2(void) __attribute__ ((interrupt)); + +// MTU2 TGIB2 + +void INT_Excep_MTU2_TGIB2(void) __attribute__ ((interrupt)); + +// MTU2 TCIV2 + +void INT_Excep_MTU2_TCIV2(void) __attribute__ ((interrupt)); + +// MTU2 TCIU2 + +void INT_Excep_MTU2_TCIU2(void) __attribute__ ((interrupt)); + +// MTU3 TGIA3 + +void INT_Excep_MTU3_TGIA3(void) __attribute__ ((interrupt)); + +// MTU3 TGIB3 + +void INT_Excep_MTU3_TGIB3(void) __attribute__ ((interrupt)); + +// MTU3 TGIC3 + +void INT_Excep_MTU3_TGIC3(void) __attribute__ ((interrupt)); + +// MTU3 TGID3 + +void INT_Excep_MTU3_TGID3(void) __attribute__ ((interrupt)); + +// MTU3 TCIV3 + +void INT_Excep_MTU3_TCIV3(void) __attribute__ ((interrupt)); + +// MTU4 TGIA4 + +void INT_Excep_MTU4_TGIA4(void) __attribute__ ((interrupt)); + +// MTU4 TGIB4 + +void INT_Excep_MTU4_TGIB4(void) __attribute__ ((interrupt)); + +// MTU4 TGIC4 + +void INT_Excep_MTU4_TGIC4(void) __attribute__ ((interrupt)); + +// MTU4 TGID4 + +void INT_Excep_MTU4_TGID4(void) __attribute__ ((interrupt)); + +// MTU4 TCIV4 + +void INT_Excep_MTU4_TCIV4(void) __attribute__ ((interrupt)); + +// MTU5 TGIU5 + +void INT_Excep_MTU5_TGIU5(void) __attribute__ ((interrupt)); + +// MTU5 TGIV5 + +void INT_Excep_MTU5_TGIV5(void) __attribute__ ((interrupt)); + +// MTU5 TGIW5 + +void INT_Excep_MTU5_TGIW5(void) __attribute__ ((interrupt)); + +// TPU0 TGI0A + +void INT_Excep_TPU0_TGI0A(void) __attribute__ ((interrupt)); + +// TPU0 TGI0B + +void INT_Excep_TPU0_TGI0B(void) __attribute__ ((interrupt)); + +// TPU0 TGI0C + +void INT_Excep_TPU0_TGI0C(void) __attribute__ ((interrupt)); + +// TPU0 TGI0D + +void INT_Excep_TPU0_TGI0D(void) __attribute__ ((interrupt)); + +// TPU0 TCI0V + +void INT_Excep_TPU0_TCI0V(void) __attribute__ ((interrupt)); + +// TPU1 TGI1A + +void INT_Excep_TPU1_TGI1A(void) __attribute__ ((interrupt)); + +// TPU1 TGI1B + +void INT_Excep_TPU1_TGI1B(void) __attribute__ ((interrupt)); + +// TPU1 TCI1V + +void INT_Excep_TPU1_TCI1V(void) __attribute__ ((interrupt)); + +// TPU1 TCI1U + +void INT_Excep_TPU1_TCI1U(void) __attribute__ ((interrupt)); + +// TPU2 TGI2A + +void INT_Excep_TPU2_TGI2A(void) __attribute__ ((interrupt)); + +// TPU2 TGI2B + +void INT_Excep_TPU2_TGI2B(void) __attribute__ ((interrupt)); + +// TPU2 TCI2V + +void INT_Excep_TPU2_TCI2V(void) __attribute__ ((interrupt)); + +// TPU2 TCI2U + +void INT_Excep_TPU2_TCI2U(void) __attribute__ ((interrupt)); + +// TPU3 TGI3A + +void INT_Excep_TPU3_TGI3A(void) __attribute__ ((interrupt)); + +// TPU3 TGI3B + +void INT_Excep_TPU3_TGI3B(void) __attribute__ ((interrupt)); + +// TPU3 TGI3C + +void INT_Excep_TPU3_TGI3C(void) __attribute__ ((interrupt)); + +// TPU3 TGI3D + +void INT_Excep_TPU3_TGI3D(void) __attribute__ ((interrupt)); + +// TPU3 TCI3V + +void INT_Excep_TPU3_TCI3V(void) __attribute__ ((interrupt)); + +// TPU4 TGI4A + +void INT_Excep_TPU4_TGI4A(void) __attribute__ ((interrupt)); + +// TPU4 TGI4B + +void INT_Excep_TPU4_TGI4B(void) __attribute__ ((interrupt)); + +// TPU4 TCI4V + +void INT_Excep_TPU4_TCI4V(void) __attribute__ ((interrupt)); + +// TPU4 TCI4U + +void INT_Excep_TPU4_TCI4U(void) __attribute__ ((interrupt)); + +// TPU5 TGI5A + +void INT_Excep_TPU5_TGI5A(void) __attribute__ ((interrupt)); + +// TPU5 TGI5B + +void INT_Excep_TPU5_TGI5B(void) __attribute__ ((interrupt)); + +// TPU5 TCI5V + +void INT_Excep_TPU5_TCI5V(void) __attribute__ ((interrupt)); + +// TPU5 TCI5U + +void INT_Excep_TPU5_TCI5U(void) __attribute__ ((interrupt)); + +// vector 168 reserved +// vector 169 reserved + +// POE OEI1 + +void INT_Excep_POE_OEI1(void) __attribute__ ((interrupt)); + +// POE OEI2 + +void INT_Excep_POE_OEI2(void) __attribute__ ((interrupt)); + +// vector 172 reserved +// vector 173 reserved + +// TMR0 CMIA0 + +void INT_Excep_TMR0_CMIA0(void) __attribute__ ((interrupt)); + +// TMR0 CMIB0 + +void INT_Excep_TMR0_CMIB0(void) __attribute__ ((interrupt)); + +// TMR0 OVI0 + +void INT_Excep_TMR0_OVI0(void) __attribute__ ((interrupt)); + +// TMR1 CMIA1 + +void INT_Excep_TMR1_CMIA1(void) __attribute__ ((interrupt)); + +// TMR1 CMIB1 + +void INT_Excep_TMR1_CMIB1(void) __attribute__ ((interrupt)); + +// TMR1 OVI1 + +void INT_Excep_TMR1_OVI1(void) __attribute__ ((interrupt)); + +// TMR2 CMIA2 + +void INT_Excep_TMR2_CMIA2(void) __attribute__ ((interrupt)); + +// TMR2 CMIB2 + +void INT_Excep_TMR2_CMIB2(void) __attribute__ ((interrupt)); + +// TMR2 OVI2 + +void INT_Excep_TMR2_OVI2(void) __attribute__ ((interrupt)); + +// TMR3 CMIA3 + +void INT_Excep_TMR3_CMIA3(void) __attribute__ ((interrupt)); + +// TMR3 CMIB3 + +void INT_Excep_TMR3_CMIB3(void) __attribute__ ((interrupt)); + +// TMR3 OVI3 + +void INT_Excep_TMR3_OVI3(void) __attribute__ ((interrupt)); + +// vector 186 reserved +// vector 187 reserved +// vector 188 reserved +// vector 189 reserved +// vector 190 reserved +// vector 191 reserved +// vector 192 reserved +// vector 193 reserved +// vector 194 reserved +// vector 195 reserved +// vector 196 reserved +// vector 197 reserved + +// DMAC DMAC0I + +void INT_Excep_DMAC_DMAC0I(void) __attribute__ ((interrupt)); + +// DMAC DMAC1I + +void INT_Excep_DMAC_DMAC1I(void) __attribute__ ((interrupt)); + +// DMAC DMAC2I + +void INT_Excep_DMAC_DMAC2I(void) __attribute__ ((interrupt)); + +// DMAC DMAC3I + +void INT_Excep_DMAC_DMAC3I(void) __attribute__ ((interrupt)); + +// vector 202 reserved +// vector 203 reserved +// vector 204 reserved +// vector 205 reserved +// vector 206 reserved +// vector 207 reserved +// vector 208 reserved +// vector 209 reserved +// vector 210 reserved +// vector 211 reserved +// vector 212 reserved +// vector 213 reserved + +// SCI0 ERI0 + +void INT_Excep_SCI0_ERI0(void) __attribute__ ((interrupt)); + +// SCI0 RXI0 + +void INT_Excep_SCI0_RXI0(void) __attribute__ ((interrupt)); + +// SCI0 TXI0 + +void INT_Excep_SCI0_TXI0(void) __attribute__ ((interrupt)); + +// SCI0 TEI0 + +void INT_Excep_SCI0_TEI0(void) __attribute__ ((interrupt)); + +// SCI1 ERI1 + +void INT_Excep_SCI1_ERI1(void) __attribute__ ((interrupt)); + +// SCI1 RXI1 + +void INT_Excep_SCI1_RXI1(void) __attribute__ ((interrupt)); + +// SCI1 TXI1 + +void INT_Excep_SCI1_TXI1(void) __attribute__ ((interrupt)); + +// SCI1 TEI1 + +void INT_Excep_SCI1_TEI1(void) __attribute__ ((interrupt)); + +// SCI5 ERI5 + +void INT_Excep_SCI5_ERI5(void) __attribute__ ((interrupt)); + +// SCI5 RXI5 + +void INT_Excep_SCI5_RXI5(void) __attribute__ ((interrupt)); + +// SCI5 TXI5 + +void INT_Excep_SCI5_TXI5(void) __attribute__ ((interrupt)); + +// SCI5 TEI5 + +void INT_Excep_SCI5_TEI5(void) __attribute__ ((interrupt)); + +// SCI6 ERI6 + +void INT_Excep_SCI6_ERI6(void) __attribute__ ((interrupt)); + +// SCI6 RXI6 + +void INT_Excep_SCI6_RXI6(void) __attribute__ ((interrupt)); + +// SCI6 TXI6 + +void INT_Excep_SCI6_TXI6(void) __attribute__ ((interrupt)); + +// SCI6 TEI6 + +void INT_Excep_SCI6_TEI6(void) __attribute__ ((interrupt)); + +// SCI8 ERI8 + +void INT_Excep_SCI8_ERI8(void) __attribute__ ((interrupt)); + +// SCI8 RXI8 + +void INT_Excep_SCI8_RXI8(void) __attribute__ ((interrupt)); + +// SCI8 TXI8 + +void INT_Excep_SCI8_TXI8(void) __attribute__ ((interrupt)); + +// SCI8 TEI8 + +void INT_Excep_SCI8_TEI8(void) __attribute__ ((interrupt)); + +// SCI9 ERI9 + +void INT_Excep_SCI9_ERI9(void) __attribute__ ((interrupt)); + +// SCI9 RXI9 + +void INT_Excep_SCI9_RXI9(void) __attribute__ ((interrupt)); + +// SCI9 TXI9 + +void INT_Excep_SCI9_TXI9(void) __attribute__ ((interrupt)); + +// SCI9 TEI9 + +void INT_Excep_SCI9_TEI9(void) __attribute__ ((interrupt)); + +// SCI12 ERI12 + +void INT_Excep_SCI12_ERI12(void) __attribute__ ((interrupt)); + +// SCI12 RXI12 + +void INT_Excep_SCI12_RXI12(void) __attribute__ ((interrupt)); + +// SCI12 TXI12 + +void INT_Excep_SCI12_TXI12(void) __attribute__ ((interrupt)); + +// SCI12 TEI12 + +void INT_Excep_SCI12_TEI12(void) __attribute__ ((interrupt)); + +// SCI12 SCIX0 + +void INT_Excep_SCI12_SCIX0(void) __attribute__ ((interrupt)); + +// SCI12 SCIX1 + +void INT_Excep_SCI12_SCIX1(void) __attribute__ ((interrupt)); + +// SCI12 SCIX2 + +void INT_Excep_SCI12_SCIX2(void) __attribute__ ((interrupt)); + +// SCI12 SCIX3 + +void INT_Excep_SCI12_SCIX3(void) __attribute__ ((interrupt)); + +// RIIC0 EEI0 + +void INT_Excep_RIIC0_EEI0(void) __attribute__ ((interrupt)); + +// RIIC0 RXI0 + +void INT_Excep_RIIC0_RXI0(void) __attribute__ ((interrupt)); + +// RIIC0 TXI0 + +void INT_Excep_RIIC0_TXI0(void) __attribute__ ((interrupt)); + +// RIIC0 TEI0 + +void INT_Excep_RIIC0_TEI0(void) __attribute__ ((interrupt)); + +// vector 250 reserved +// vector 251 reserved +// vector 252 reserved +// vector 253 reserved +// vector 254 reserved +// vector 255 reserved + +//;<> +//;Power On Reset PC +extern void PowerON_Reset(void) __attribute__ ((interrupt)); +//;<> +#endif diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Renesas_Code/typedefine.h b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Renesas_Code/typedefine.h new file mode 100644 index 000000000..5aa146beb --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Renesas_Code/typedefine.h @@ -0,0 +1,28 @@ +/***************************************************************/ +/* */ +/* PROJECT NAME : RTOSDemo */ +/* FILE : typedefine.h */ +/* DESCRIPTION : Aliases of Integer Type */ +/* CPU SERIES : RX200 */ +/* CPU TYPE : RX231 */ +/* */ +/* This file is generated by e2 studio. */ +/* */ +/***************************************************************/ + + +/************************************************************************/ +/* File Version: V1.00 */ +/* Date Generated: 08/07/2013 */ +/************************************************************************/ + +typedef signed char _SBYTE; +typedef unsigned char _UBYTE; +typedef signed short _SWORD; +typedef unsigned short _UWORD; +typedef signed int _SINT; +typedef unsigned int _UINT; +typedef signed long _SDWORD; +typedef unsigned long _UDWORD; +typedef signed long long _SQWORD; +typedef unsigned long long _UQWORD; diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Renesas_Code/vector_table.c b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Renesas_Code/vector_table.c new file mode 100644 index 000000000..01520e4ba --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Renesas_Code/vector_table.c @@ -0,0 +1,632 @@ +/***************************************************************/ +/* */ +/* PROJECT NAME : RTOSDemo */ +/* FILE : vector_table.c */ +/* DESCRIPTION : Vector Table */ +/* CPU SERIES : RX200 */ +/* CPU TYPE : RX231 */ +/* */ +/* This file is generated by e2 studio. */ +/* */ +/***************************************************************/ + + + + +/************************************************************************/ +/* File Version : V1.00 */ +/* History: 0.50 (2014-09-05) [Hardware Manual Revision : 0.50] */ +/* 0.51 (2014-10-01) [Hardware Manual Revision : 0.50] */ +/* Date Modified: 03/07/2015 */ +/************************************************************************/ + + +#include "interrupt_handlers.h" + +typedef void (*fp) (void); +extern void PowerON_Reset (void); +extern void stack (void); +extern void vTickISR( void ); +extern void vSoftwareInterruptISR( void ); +extern void vIntQTimerISR0( void ); +extern void vIntQTimerISR1( void ); + + +#define EXVECT_SECT __attribute__ ((section (".exvectors"))) + +const void *ExceptVectors[] EXVECT_SECT = { +//;0xffffff80 MDES Endian Select Register +#ifdef __RX_LITTLE_ENDIAN__ +(fp)0xffffffff, +#endif +#ifdef __RX_BIG_ENDIAN__ +(fp)0xfffffff8, +#endif +//;0xffffff84 Reserved + (fp)0, +//;0xffffff88 OFS1 Option byte setting + (fp)0xFFFFFFFF, +//;0xffffff8C OFS0 + (fp)0xFFFFFFFF, +//;0xffffff90 Reserved + (fp)0, +//;0xffffff94 Reserved + (fp)0, +//;0xffffff98 Reserved + (fp)0, +//;0xffffff9C Reserved + (fp)0, +//;0xffffffA0 Reserved + (fp)0xFFFFFFFF, +//;0xffffffA4 Reserved + (fp)0xFFFFFFFF, +//;0xffffffA8 Reserved + (fp)0xFFFFFFFF, +//;0xffffffAC Reserved + (fp)0xFFFFFFFF, +//;0xffffffB0 Reserved + (fp)0, +//;0xffffffB4 Reserved + (fp)0, +//;0xffffffB8 Reserved + (fp)0, +//;0xffffffBC Reserved + (fp)0, +//;0xffffffC0 Reserved + (fp)0, +//;0xffffffC4 Reserved + (fp)0, +//;0xffffffC8 Reserved + (fp)0, +//;0xffffffCC Reserved + (fp)0, +//;0xffffffd0 Exception(Supervisor Instruction) + INT_Excep_SuperVisorInst, +//;0xffffffd4 Exception(Access Instruction) + INT_Excep_AccessInst, +//;0xffffffd8 Reserved + (fp)0, +//;0xffffffdc Exception(Undefined Instruction) + INT_Excep_UndefinedInst, +//;0xffffffe0 Reserved + (fp)0, +//;0xffffffe4 Exception(Floating Point) + INT_Excep_FloatingPoint, +//;0xffffffe8 Reserved + (fp)0, +//;0xffffffec Reserved + (fp)0, +//;0xfffffff0 Reserved + (fp)0, +//;0xfffffff4 Reserved + (fp)0, +//;0xfffffff8 NMI + INT_NonMaskableInterrupt, +}; + +#define FVECT_SECT __attribute__ ((section (".fvectors"))) + +const void *HardwareVectors[] FVECT_SECT = { +//;0xfffffffc RESET +//;<> +//;Power On Reset PC + /*(void*)*/ PowerON_Reset +//;<> +}; + +#define RVECT_SECT __attribute__ ((section (".rvectors"))) + +const fp RelocatableVectors[] RVECT_SECT = { +//;0x0000 Reserved + (fp)0, +//;0x0004 Reserved + (fp)0, +//;0x0008 Reserved + (fp)0, +//;0x000C Reserved + (fp)0, +//;0x0010 Reserved + (fp)0, +//;0x0014 Reserved + (fp)0, +//;0x0018 Reserved + (fp)0, +//;0x001C Reserved + (fp)0, +//;0x0020 Reserved + (fp)0, +//;0x0024 Reserved + (fp)0, +//;0x0028 Reserved + (fp)0, +//;0x002C Reserved + (fp)0, +//;0x0030 Reserved + (fp)0, +//;0x0034 Reserved + (fp)0, +//;0x0038 Reserved + (fp)0, +//;0x003C Reserved + (fp)0, +//;0x0040 BSC_BUSERR + (fp)INT_Excep_BSC_BUSERR, +//;0x0044 Reserved + (fp)0, +//;0x0048 Reserved + (fp)0, +//;0x004C Reserved + (fp)0, +//;0x0050 Reserved + (fp)0, +//;0x0054 Reserved + (fp)0, +//;0x0058 Reserved + (fp)0, +//;0x005C FCU_FRDYI + (fp)INT_Excep_FCU_FRDYI, +//;0x0060 Reserved + (fp)0, +//;0x0064 Reserved + (fp)0, +//;0x0068 Reserved + (fp)0, +//;0x006C ICU_SWINT + (fp)vSoftwareInterruptISR, +//;0x0070 CMT0_CMI0 + (fp)vTickISR, +//;0x0074 CMT1_CMI1 + (fp)INT_Excep_CMT1_CMI1, +//;0x0078 CMT2_CMI2 + (fp)INT_Excep_CMT2_CMI2, +//;0x007C CMT3_CMI3 + (fp)INT_Excep_CMT3_CMI3, +//;0x0080 CAC_FERRF + (fp)INT_Excep_CAC_FERRF, +//;0x0084 CAC_MENDF + (fp)INT_Excep_CAC_MENDF, +//;0x0088 CAC_OVFF + (fp)INT_Excep_CAC_OVFF, +//;0x008C Reserved + (fp)0, +//;0x0090 USB0_D0FIFO0 + (fp)INT_Excep_USB0_D0FIFO0, +//;0x0094 USB0_D1FIFO0 + (fp)INT_Excep_USB0_D1FIFO0, +//;0x0098 USB0_USBI0 + (fp)INT_Excep_USB0_USBI0, +//;0x009C Reserved + (fp)0, +//;0x00A0 SDHI_SBFAI + (fp)INT_Excep_SDHI_SBFAI, +//;0x00A4 SDHI_CDETI + (fp)INT_Excep_SDHI_CDETI, +//;0x00A8 SDHI_CACI + (fp)INT_Excep_SDHI_CACI, +//;0x00AC SDHI_SDACI + (fp)INT_Excep_SDHI_SDACI, +//;0x00B0 RSPI0_SPEI0 + (fp)INT_Excep_RSPI0_SPEI0, +//;0x00B4 RSPI0_SPRI0 + (fp)INT_Excep_RSPI0_SPRI0, +//;0x00B8 RSPI0_SPTI0 + (fp)INT_Excep_RSPI0_SPTI0, +//;0x00BC RSPI0_SPII0 + (fp)INT_Excep_RSPI0_SPII0, +//;0x00C0 Reserved + (fp)0, +//;0x00C4 Reserved + (fp)0, +//;0x00C8 Reserved + (fp)0, +//;0x00CC Reserved + (fp)0, +//;0x00D0 CAN_COMFRXINT + (fp)INT_Excep_RSCAN_COMFRXINT, +//;0x00D4 CAN_RXFINT + (fp)INT_Excep_RSCAN_RXFINT, +//;0x00D8 CAN_TXINT + (fp)INT_Excep_RSCAN_TXINT, +//;0x00DC CAN_CHERRINT + (fp)INT_Excep_RSCAN_CHERRINT, +//;0x00E0 CAN_GLERRINT + (fp)INT_Excep_RSCAN_GLERRINT, +//;0x00E4 DOC_DOPCF + (fp)INT_Excep_DOC_DOPCF, +//;0x00E8 CMPB_CMPB0 + (fp)INT_Excep_CMPB_CMPB0, +//;0x00EC CMPB_CMPB1 + (fp)INT_Excep_CMPB_CMPB1, +//;0x00F0 CTSU_CTSUWR + (fp)INT_Excep_CTSU_CTSUWR, +//;0x00F4 CTSU_CTSURD + (fp)INT_Excep_CTSU_CTSURD, +//;0x00F8 CTSU_CTSUFN + (fp)INT_Excep_CTSU_CTSUFN, +//;0x00FC RTC_CUP + (fp)INT_Excep_RTC_CUP, +//;0x0100 ICU_IRQ0 + (fp)INT_Excep_ICU_IRQ0, +//;0x0104 ICU_IRQ1 + (fp)INT_Excep_ICU_IRQ1, +//;0x0108 ICU_IRQ2 + (fp)INT_Excep_ICU_IRQ2, +//;0x010C ICU_IRQ3 + (fp)INT_Excep_ICU_IRQ3, +//;0x0110 ICU_IRQ4 + (fp)INT_Excep_ICU_IRQ4, +//;0x0114 ICU_IRQ5 + (fp)INT_Excep_ICU_IRQ5, +//;0x0118 ICU_IRQ6 + (fp)INT_Excep_ICU_IRQ6, +//;0x011C ICU_IRQ7 + (fp)INT_Excep_ICU_IRQ7, +//;0x0120 Reserved + (fp)0, +//;0x0124 Reserved + (fp)0, +//;0x0128 Reserved + (fp)0, +//;0x012C Reserved + (fp)0, +//;0x0130 Reserved + (fp)0, +//;0x0134 Reserved + (fp)0, +//;0x0138 Reserved + (fp)0, +//;0x013C Reserved + (fp)0, +//;0x0140 ELC_ELSR8I + (fp)INT_Excep_ELC_ELSR8I, +//;0x0144 Reserved + (fp)0, +//;0x0148 Reserved + (fp)0, +//;0x014C Reserved + (fp)0, +//;0x0150 Reserved + (fp)0, +//;0x0154 Reserved + (fp)0, +//;0x0158 Reserved + (fp)0, +//;0x015C Reserved + (fp)0, +//;0x0160 LVD/CMPA_LVD1/CMPA1 + (fp)INT_Excep_LVD_LVD1, +//;0x0164 LVD/CMPA_LVD2/CMPA2 + (fp)INT_Excep_LVD_LVD2, +//;0x0168 USB0_USBR0 + (fp)INT_Excep_USB0_USBR0, +//;0x016C VBATT_VBTLVDI + (fp)INT_Excep_VBATT_VBTLVDI, +//;0x0170 RTC_ALM + (fp)INT_Excep_RTC_ALM, +//;0x0174 RTC_PRD + (fp)INT_Excep_RTC_PRD, +//;0x0178 Reserved + (fp)0, +//;0x017C Reserved + (fp)0, +//;0x0180 Reserved + (fp)0, +//;0x0184 Reserved + (fp)0, +//;0x0188 Reserved + (fp)0, +//;0x018C Reserved + (fp)0, +//;0x0190 Reserved + (fp)0, +//;0x0194 Reserved + (fp)0, +//;0x0198 S12AD_S12ADI0 + (fp)INT_Excep_S12AD_S12ADI0, +//;0x019C S12AD_GBADI + (fp)INT_Excep_S12AD_GBADI, +//;0x01A0 CMPB1_CMPB2 + (fp)INT_Excep_CMPB1_CMPB2, +//;0x01A4 CMPB1_CMPB3 + (fp)INT_Excep_CMPB1_CMPB3, +//;0x01A8 ELC_ELSR18I + (fp)INT_Excep_ELC_ELSR18I, +//;0x01AC ELC_ELSR19I + (fp)INT_Excep_ELC_ELSR19I, +//;0x01B0 SSI0_SSIF0 + (fp)INT_Excep_SSI0_SSIF0, +//;0x01B4 SSI0_SSIRXI0 + (fp)INT_Excep_SSI0_SSIRXI0, +//;0x01B8 SSI0_SSITXI0 + (fp)INT_Excep_SSI0_SSITXI0, +//;0x01BC Secure_RD + (fp)INT_Excep_SECURITY_RD, +//;0x01C0 Secure_WR + (fp)INT_Excep_SECURITY_WR, +//;0x01C4 Secure_Error + (fp)INT_Excep_SECURITY_ERR, +//;0x01C8 MTU0_TGIA0 + (fp)INT_Excep_MTU0_TGIA0, +//;0x01CC MTU0_TGIB0 + (fp)INT_Excep_MTU0_TGIB0, +//;0x01D0 MTU0_TGIC0 + (fp)INT_Excep_MTU0_TGIC0, +//;0x01D4 MTU0_TGID0 + (fp)INT_Excep_MTU0_TGID0, +//;0x01D8 MTU0_TCIV0 + (fp)INT_Excep_MTU0_TCIV0, +//;0x01DC MTU0_TGIE0 + (fp)INT_Excep_MTU0_TGIE0, +//;0x01E0 MTU0_TGIF0 + (fp)INT_Excep_MTU0_TGIF0, +//;0x01E4 MTU1_TGIA1 + (fp)INT_Excep_MTU1_TGIA1, +//;0x01E8 MTU1_TGIB1 + (fp)INT_Excep_MTU1_TGIB1, +//;0x01EC MTU1_TCIV1 + (fp)INT_Excep_MTU1_TCIV1, +//;0x01F0 MTU1_TCIU1 + (fp)INT_Excep_MTU1_TCIU1, +//;0x01F4 MTU2_TGIA2 + (fp)INT_Excep_MTU2_TGIA2, +//;0x01F8 MTU2_TGIB2 + (fp)INT_Excep_MTU2_TGIB2, +//;0x01FC MTU2_TCIV2 + (fp)INT_Excep_MTU2_TCIV2, +//;0x0200 MTU2_TCIU2 + (fp)INT_Excep_MTU2_TCIU2, +//;0x0204 MTU3_TGIA3 + (fp)INT_Excep_MTU3_TGIA3, +//;0x0208 MTU3_TGIB3 + (fp)INT_Excep_MTU3_TGIB3, +//;0x020C MTU3_TGIC3 + (fp)INT_Excep_MTU3_TGIC3, +//;0x0210 MTU3_TGID3 + (fp)INT_Excep_MTU3_TGID3, +//;0x0214 MTU3_TCIV3 + (fp)INT_Excep_MTU3_TCIV3, +//;0x0218 MTU4_TGIA4 + (fp)INT_Excep_MTU4_TGIA4, +//;0x021C MTU4_TGIB4 + (fp)INT_Excep_MTU4_TGIB4, +//;0x0220 MTU4_TGIC4 + (fp)INT_Excep_MTU4_TGIC4, +//;0x0224 MTU4_TGID4 + (fp)INT_Excep_MTU4_TGID4, +//;0x0228 MTU4_TCIV4 + (fp)INT_Excep_MTU4_TCIV4, +//;0x022C MTU5_TGIU5 + (fp)INT_Excep_MTU5_TGIU5, +//;0x0230 MTU5_TGIV5 + (fp)INT_Excep_MTU5_TGIV5, +//;0x0234 MTU5_TGIW5 + (fp)INT_Excep_MTU5_TGIW5, +//;0x0238 TPU0_TGI0A + (fp)INT_Excep_TPU0_TGI0A, +//;0x023C TPU0_TGI0B + (fp)INT_Excep_TPU0_TGI0B, +//;0x0240 TPU0_TGI0C + (fp)INT_Excep_TPU0_TGI0C, +//;0x0244 TPU0_TGI0D + (fp)INT_Excep_TPU0_TGI0D, +//;0x0248 TPU0_TCI0V + (fp)INT_Excep_TPU0_TCI0V, +//;0x024C TPU1_TGI1A + (fp)INT_Excep_TPU1_TGI1A, +//;0x0250 TPU1_TGI1B + (fp)INT_Excep_TPU1_TGI1B, +//;0x0254 TPU1_TCI1V + (fp)INT_Excep_TPU1_TCI1V, +//;0x0258 TPU1_TCI1U + (fp)INT_Excep_TPU1_TCI1U, +//;0x025C TPU2_TGI2A + (fp)INT_Excep_TPU2_TGI2A, +//;0x0260 TPU2_TGI2B + (fp)INT_Excep_TPU2_TGI2B, +//;0x0264 TPU2_TCI2V + (fp)INT_Excep_TPU2_TCI2V, +//;0x0268 TPU2_TCI2U + (fp)INT_Excep_TPU2_TCI2U, +//;0x026C TPU3_TGI3A + (fp)INT_Excep_TPU3_TGI3A, +//;0x0270 TPU3_TGI3B + (fp)INT_Excep_TPU3_TGI3B, +//;0x0274 TPU3_TGI3C + (fp)INT_Excep_TPU3_TGI3C, +//;0x0278 TPU3_TGI3D + (fp)INT_Excep_TPU3_TGI3D, +//;0x027C TPU3_TCI3V + (fp)INT_Excep_TPU3_TCI3V, +//;0x0280 TPU4_TGI4A + (fp)INT_Excep_TPU4_TGI4A, +//;0x0284 TPU4_TGI4B + (fp)INT_Excep_TPU4_TGI4B, +//;0x0288 TPU4_TCI4V + (fp)INT_Excep_TPU4_TCI4V, +//;0x028C TPU4_TCI4U + (fp)INT_Excep_TPU4_TCI4U, +//;0x0290 TPU5_TGI5A + (fp)INT_Excep_TPU5_TGI5A, +//;0x0294 TPU5_TGI5B + (fp)INT_Excep_TPU5_TGI5B, +//;0x0298 TPU5_TCI5V + (fp)INT_Excep_TPU5_TCI5V, +//;0x029C TPU5_TCI5U + (fp)INT_Excep_TPU5_TCI5U, +//;0x02A0 Reserved + (fp)0, +//;0x02A4 Reserved + (fp)0, +//;0x02A8 POE_OEI1 + (fp)INT_Excep_POE_OEI1, +//;0x02AC POE_OEI2 + (fp)INT_Excep_POE_OEI2, +//;0x02B0 Reserved + (fp)0, +//;0x02B4 Reserved + (fp)0, +//;0x02B8 TMR0_CMIA0 + (fp)vIntQTimerISR0, +//;0x02BC TMR0_CMIB0 + (fp)INT_Excep_TMR0_CMIB0, +//;0x02C0 TMR0_OVI0 + (fp)INT_Excep_TMR0_OVI0, +//;0x02C4 TMR1_CMIA1 + (fp)INT_Excep_TMR1_CMIA1, +//;0x02C8 TMR1_CMIB1 + (fp)INT_Excep_TMR1_CMIB1, +//;0x02CC TMR1_OVI1 + (fp)INT_Excep_TMR1_OVI1, +//;0x02D0 TMR2_CMIA2 + (fp)vIntQTimerISR1, +//;0x02D4 TMR2_CMIB2 + (fp)INT_Excep_TMR2_CMIB2, +//;0x02D8 TMR2_OVI2 + (fp)INT_Excep_TMR2_OVI2, +//;0x02DC TMR3_CMIA3 + (fp)INT_Excep_TMR3_CMIA3, +//;0x02E0 TMR3_CMIB3 + (fp)INT_Excep_TMR3_CMIB3, +//;0x02E4 TMR3_OVI3 + (fp)INT_Excep_TMR3_OVI3, +//;0x02E8 Reserved + (fp)0, +//;0x02EC Reserved + (fp)0, +//;0x02F0 Reserved + (fp)0, +//;0x02F4 Reserved + (fp)0, +//;0x02F8 Reserved + (fp)0, +//;0x02FC Reserved + (fp)0, +//;0x0300 Reserved + (fp)0, +//;0x0304 Reserved + (fp)0, +//;0x0308 Reserved + (fp)0, +//;0x030C Reserved + (fp)0, +//;0x0310 Reserved + (fp)0, +//;0x0314 Reserved + (fp)0, +//;0x0318 DMAC_DMAC0I + (fp)INT_Excep_DMAC_DMAC0I, +//;0x031C DMAC_DMAC1I + (fp)INT_Excep_DMAC_DMAC1I, +//;0x0320 DMAC_DMAC2I + (fp)INT_Excep_DMAC_DMAC2I, +//;0x0324 DMAC_DMAC3I + (fp)INT_Excep_DMAC_DMAC3I, +//;0x0328 Reserved + (fp)0, +//;0x032C Reserved + (fp)0, +//;0x0330 Reserved + (fp)0, +//;0x0334 Reserved + (fp)0, +//;0x0338 Reserved + (fp)0, +//;0x033C Reserved + (fp)0, +//;0x0340 Reserved + (fp)0, +//;0x0344 Reserved + (fp)0, +//;0x0348 Reserved + (fp)0, +//;0x034C Reserved + (fp)0, +//;0x0350 Reserved + (fp)0, +//;0x0354 Reserved + (fp)0, +//;0x0358 SCI0_ERI0 + (fp)INT_Excep_SCI0_ERI0, +//;0x035C SCI0_RXI0 + (fp)INT_Excep_SCI0_RXI0, +//;0x0360 SCI0_TXI0 + (fp)INT_Excep_SCI0_TXI0, +//;0x0364 SCI0_TEI0 + (fp)INT_Excep_SCI0_TEI0, +//;0x0368 SCI1_ERI1 + (fp)INT_Excep_SCI1_ERI1, +//;0x036C SCI1_RXI1 + (fp)INT_Excep_SCI1_RXI1, +//;0x0370 SCI1_TXI1 + (fp)INT_Excep_SCI1_TXI1, +//;0x0374 SCI1_TEI1 + (fp)INT_Excep_SCI1_TEI1, +//;0x0378 SCI5_ERI5 + (fp)INT_Excep_SCI5_ERI5, +//;0x037C SCI5_RXI5 + (fp)INT_Excep_SCI5_RXI5, +//;0x0380 SCI5_TXI5 + (fp)INT_Excep_SCI5_TXI5, +//;0x0384 SCI5_TEI5 + (fp)INT_Excep_SCI5_TEI5, +//;0x0388 SCI6_ERI6 + (fp)INT_Excep_SCI6_ERI6, +//;0x038C SCI6_RXI6 + (fp)INT_Excep_SCI6_RXI6, +//;0x0390 SCI6_TXI6 + (fp)INT_Excep_SCI6_TXI6, +//;0x0394 SCI6_TEI6 + (fp)INT_Excep_SCI6_TEI6, +//;0x0398 SCI8_ERI8 + (fp)INT_Excep_SCI8_ERI8, +//;0x039C SCI8_RXI8 + (fp)INT_Excep_SCI8_RXI8, +//;0x03A0 SCI8_TXI8 + (fp)INT_Excep_SCI8_TXI8, +//;0x03A4 SCI8_TEI8 + (fp)INT_Excep_SCI8_TEI8, +//;0x03A8 SCI9_ERI9 + (fp)INT_Excep_SCI9_ERI9, +//;0x03AC SCI9_RXI9 + (fp)INT_Excep_SCI9_RXI9, +//;0x03B0 SCI9_TXI9 + (fp)INT_Excep_SCI9_TXI9, +//;0x03B4 SCI9_TEI9 + (fp)INT_Excep_SCI9_TEI9, +//;0x03B8 SCI12_ERI12 + (fp)INT_Excep_SCI12_ERI12, +//;0x03BC SCI12_RXI12 + (fp)INT_Excep_SCI12_RXI12, +//;0x03C0 SCI12_TXI12 + (fp)INT_Excep_SCI12_TXI12, +//;0x03C4 SCI12_TEI12 + (fp)INT_Excep_SCI12_TEI12, +//;0x03C8 SCI12_SCIX0 + (fp)INT_Excep_SCI12_SCIX0, +//;0x03CC SCI12_SCIX1 + (fp)INT_Excep_SCI12_SCIX1, +//;0x03D0 SCI12_SCIX2 + (fp)INT_Excep_SCI12_SCIX2, +//;0x03D4 SCI12_SCIX3 + (fp)INT_Excep_SCI12_SCIX3, +//;0x03D8 RIIC0_EEI0 + (fp)INT_Excep_RIIC0_EEI0, +//;0x03DC RIIC0_RXI0 + (fp)INT_Excep_RIIC0_RXI0, +//;0x03E0 RIIC0_TXI0 + (fp)INT_Excep_RIIC0_TXI0, +//;0x03E4 RIIC0_TEI0 + (fp)INT_Excep_RIIC0_TEI0, +//;0x03E8 Reserved + (fp)0, +//;0x03EC Reserved + (fp)0, +//;0x03F0 Reserved + (fp)0, +//;0x03F4 Reserved + (fp)0, +//;0x03F8 Reserved + (fp)0, +//;0x03FC Reserved + (fp)0, +}; diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc.c b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc.c new file mode 100644 index 000000000..1e082fac8 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc.c @@ -0,0 +1,115 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cgc.c +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : GCCRX +* Description : This file implements device driver for CGC module. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_CGC_Create +* Description : This function initializes the clock generator. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_CGC_Create(void) +{ + uint32_t sckcr_dummy; + volatile uint32_t memorywaitcycle; + + /* Set main clock control registers */ + SYSTEM.MOFCR.BYTE = _00_CGC_MAINOSC_RESONATOR | _00_CGC_MAINOSC_UNDER10M; + SYSTEM.MOSCWTCR.BYTE = _06_CGC_OSC_WAIT_CYCLE_32768; + + /* Set main clock operation */ + SYSTEM.MOSCCR.BIT.MOSTP = 0U; + + /* Wait for main clock oscillator wait counter overflow */ + while (1U != SYSTEM.OSCOVFSR.BIT.MOOVF); + + /* Set system clock */ + sckcr_dummy = _00000000_CGC_PCLKD_DIV_1 | _00000100_CGC_PCLKB_DIV_2 | _00001000_CGC_PCLKA_DIV_2 | + _00010000_CGC_BCLK_DIV_2 | _00000000_CGC_ICLK_DIV_1 | _10000000_CGC_FCLK_DIV_2; + SYSTEM.SCKCR.LONG = sckcr_dummy; + + while (SYSTEM.SCKCR.LONG != sckcr_dummy); + + /* Set PLL circuit */ + SYSTEM.PLLCR.WORD = _0000_CGC_PLL_FREQ_DIV_1 | _0C00_CGC_PLL_FREQ_MUL_6_5; + SYSTEM.PLLCR2.BIT.PLLEN = 0U; + + /* Wait for PLL wait counter overflow */ + while (1U != SYSTEM.OSCOVFSR.BIT.PLOVF); + + /* Disable sub-clock */ + SYSTEM.SOSCCR.BIT.SOSTP = 1U; + + /* Wait for the register modification to complete */ + while (1U != SYSTEM.SOSCCR.BIT.SOSTP); + + /* Disable sub-clock */ + RTC.RCR3.BIT.RTCEN = 0U; + + /* Wait for the register modification to complete */ + while (0U != RTC.RCR3.BIT.RTCEN); + + /* Set BCLK */ + SYSTEM.SCKCR.BIT.PSTOP1 = 1U; + + /* Set memory wait cycle setting register */ + SYSTEM.MEMWAIT.BIT.MEMWAIT = 1U; + memorywaitcycle = SYSTEM.MEMWAIT.BYTE; + memorywaitcycle++; + + /* Set clock source */ + SYSTEM.SCKCR3.WORD = _0400_CGC_CLOCKSOURCE_PLL; + + while (SYSTEM.SCKCR3.WORD != _0400_CGC_CLOCKSOURCE_PLL); + + /* Set LOCO */ + SYSTEM.LOCOCR.BIT.LCSTP = 1U; +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc.h b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc.h new file mode 100644 index 000000000..7732241d2 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc.h @@ -0,0 +1,227 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cgc.h +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : GCCRX +* Description : This file implements device driver for CGC module. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ +#ifndef CGC_H +#define CGC_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ +/* + System Clock Control Register (SCKCR) +*/ +/* Peripheral Module Clock D (PCLKD) */ +#define _00000000_CGC_PCLKD_DIV_1 (0x00000000UL) /* x1 */ +#define _00000001_CGC_PCLKD_DIV_2 (0x00000001UL) /* x1/2 */ +#define _00000002_CGC_PCLKD_DIV_4 (0x00000002UL) /* x1/4 */ +#define _00000003_CGC_PCLKD_DIV_8 (0x00000003UL) /* x1/8 */ +#define _00000004_CGC_PCLKD_DIV_16 (0x00000004UL) /* x1/16 */ +#define _00000005_CGC_PCLKD_DIV_32 (0x00000005UL) /* x1/32 */ +#define _00000006_CGC_PCLKD_DIV_64 (0x00000006UL) /* x1/64 */ +/* Peripheral Module Clock B (PCLKB) */ +#define _00000000_CGC_PCLKB_DIV_1 (0x00000000UL) /* x1 */ +#define _00000100_CGC_PCLKB_DIV_2 (0x00000100UL) /* x1/2 */ +#define _00000200_CGC_PCLKB_DIV_4 (0x00000200UL) /* x1/4 */ +#define _00000300_CGC_PCLKB_DIV_8 (0x00000300UL) /* x1/8 */ +#define _00000400_CGC_PCLKB_DIV_16 (0x00000400UL) /* x1/16 */ +#define _00000500_CGC_PCLKB_DIV_32 (0x00000500UL) /* x1/32 */ +#define _00000600_CGC_PCLKB_DIV_64 (0x00000600UL) /* x1/64 */ +/* Peripheral Module Clock A (PCLKA) */ +#define _00000000_CGC_PCLKA_DIV_1 (0x00000000UL) /* x1 */ +#define _00001000_CGC_PCLKA_DIV_2 (0x00001000UL) /* x1/2 */ +#define _00002000_CGC_PCLKA_DIV_4 (0x00002000UL) /* x1/4 */ +#define _00003000_CGC_PCLKA_DIV_8 (0x00003000UL) /* x1/8 */ +#define _00004000_CGC_PCLKA_DIV_16 (0x00004000UL) /* x1/16 */ +#define _00005000_CGC_PCLKA_DIV_32 (0x00005000UL) /* x1/32 */ +#define _00006000_CGC_PCLKA_DIV_64 (0x00006000UL) /* x1/64 */ +/* External Bus Clock (BCLK) */ +#define _00000000_CGC_BCLK_DIV_1 (0x00000000UL) /* x1 */ +#define _00010000_CGC_BCLK_DIV_2 (0x00010000UL) /* x1/2 */ +#define _00020000_CGC_BCLK_DIV_4 (0x00020000UL) /* x1/4 */ +#define _00030000_CGC_BCLK_DIV_8 (0x00030000UL) /* x1/8 */ +#define _00040000_CGC_BCLK_DIV_16 (0x00040000UL) /* x1/16 */ +#define _00050000_CGC_BCLK_DIV_32 (0x00050000UL) /* x1/32 */ +#define _00060000_CGC_BCLK_DIV_64 (0x00060000UL) /* x1/64 */ +/* System Clock (ICLK) */ +#define _00000000_CGC_ICLK_DIV_1 (0x00000000UL) /* x1 */ +#define _01000000_CGC_ICLK_DIV_2 (0x01000000UL) /* x1/2 */ +#define _02000000_CGC_ICLK_DIV_4 (0x02000000UL) /* x1/4 */ +#define _03000000_CGC_ICLK_DIV_8 (0x03000000UL) /* x1/8 */ +#define _04000000_CGC_ICLK_DIV_16 (0x04000000UL) /* x1/16 */ +#define _05000000_CGC_ICLK_DIV_32 (0x05000000UL) /* x1/32 */ +#define _06000000_CGC_ICLK_DIV_64 (0x06000000UL) /* x1/64 */ +/* System Clock (FCLK) */ +#define _00000000_CGC_FCLK_DIV_1 (0x00000000UL) /* x1 */ +#define _10000000_CGC_FCLK_DIV_2 (0x10000000UL) /* x1/2 */ +#define _20000000_CGC_FCLK_DIV_4 (0x20000000UL) /* x1/4 */ +#define _30000000_CGC_FCLK_DIV_8 (0x30000000UL) /* x1/8 */ +#define _40000000_CGC_FCLK_DIV_16 (0x40000000UL) /* x1/16 */ +#define _50000000_CGC_FCLK_DIV_32 (0x50000000UL) /* x1/32 */ +#define _60000000_CGC_FCLK_DIV_64 (0x60000000UL) /* x1/64 */ + +/* + System Clock Control Register 3 (SCKCR3) +*/ +#define _0000_CGC_CLOCKSOURCE_LOCO (0x0000U) /* LOCO */ +#define _0100_CGC_CLOCKSOURCE_HOCO (0x0100U) /* HOCO */ +#define _0200_CGC_CLOCKSOURCE_MAINCLK (0x0200U) /* Main clock oscillator */ +#define _0300_CGC_CLOCKSOURCE_SUBCLK (0x0300U) /* Sub-clock oscillator */ +#define _0400_CGC_CLOCKSOURCE_PLL (0x0400U) /* PLL circuit */ + +/* + PLL Control Register (PLLCR) +*/ +/* PLL Input Frequency Division Ratio Select (PLIDIV[1:0]) */ +#define _0000_CGC_PLL_FREQ_DIV_1 (0x0000U) /* x1 */ +#define _0001_CGC_PLL_FREQ_DIV_2 (0x0001U) /* x1/2 */ +#define _0002_CGC_PLL_FREQ_DIV_4 (0x0002U) /* x1/4 */ +/* Frequency Multiplication Factor Select (STC[5:0]) */ +#define _0700_CGC_PLL_FREQ_MUL_4_0 (0x0700U) /* x4 */ +#define _0800_CGC_PLL_FREQ_MUL_4_5 (0x0800U) /* x4.5 */ +#define _0900_CGC_PLL_FREQ_MUL_5_0 (0x0900U) /* x5 */ +#define _0A00_CGC_PLL_FREQ_MUL_5_5 (0x0A00U) /* x5.5 */ +#define _0B00_CGC_PLL_FREQ_MUL_6_0 (0x0B00U) /* x6 */ +#define _0C00_CGC_PLL_FREQ_MUL_6_5 (0x0C00U) /* x6.5 */ +#define _0D00_CGC_PLL_FREQ_MUL_7_0 (0x0D00U) /* x7 */ +#define _0E00_CGC_PLL_FREQ_MUL_7_5 (0x0E00U) /* x7.5 */ +#define _0F00_CGC_PLL_FREQ_MUL_8_0 (0x0F00U) /* x8 */ +#define _1000_CGC_PLL_FREQ_MUL_8_5 (0x1000U) /* x8.5 */ +#define _1100_CGC_PLL_FREQ_MUL_9_0 (0x1100U) /* x9 */ +#define _1200_CGC_PLL_FREQ_MUL_9_5 (0x1200U) /* x9.5 */ +#define _1300_CGC_PLL_FREQ_MUL_10_0 (0x1300U) /* x10 */ +#define _1400_CGC_PLL_FREQ_MUL_10_5 (0x1400U) /* x10.5 */ +#define _1500_CGC_PLL_FREQ_MUL_11_0 (0x1500U) /* x11 */ +#define _1600_CGC_PLL_FREQ_MUL_11_5 (0x1600U) /* 11.5 */ +#define _1700_CGC_PLL_FREQ_MUL_12_0 (0x1700U) /* x12 */ +#define _1800_CGC_PLL_FREQ_MUL_12_5 (0x1800U) /* x12.5 */ +#define _1900_CGC_PLL_FREQ_MUL_13_0 (0x1900U) /* x13 */ +#define _1A00_CGC_PLL_FREQ_MUL_13_5 (0x1A00U) /* x13.5 */ +/* + USB-dedicated PLL Control Register (UPLLCR) +*/ +/* USB-dedicated PLL Input Frequency Division Ratio Select (UPLIDIV[1:0]) */ +#define _0000_CGC_UPLL_DIV_1 (0x0000U) /* x1 */ +#define _0001_CGC_UPLL_DIV_2 (0x0001U) /* x1/2 */ +#define _0002_CGC_UPLL_DIV_4 (0x0002U) /* x1/4 */ +/* UCLK Source USB-Dedicated PLL Select (UCKUPLLSEL) */ +#define _0000_CGC_UCLK_SYSCLK (0x0000U) /* System clock is selected as UCLK */ +#define _0010_CGC_UCLK_USBPLL (0x0010U) /* USB-dedicated PLL is selected as UCLK */ +/* Frequency Multiplication Factor Select (USTC[5:0]) */ +#define _0700_CGC_UPLL_MUL_4 (0x0700U) /* x4 */ +#define _0B00_CGC_UPLL_MUL_6 (0x0B00U) /* x6 */ +#define _0F00_CGC_UPLL_MUL_8 (0x0F00U) /* x8 */ +#define _1700_CGC_UPLL_MUL_12 (0x1700U) /* x12 */ + +/* + High-Speed On-Chip Oscillator Control Register 2 (HOCOCR2) +*/ +/* HOCO Frequency Setting (HCFRQ[1:0]) */ +#define _00_CGC_HOCO_CLK_32 (0x00U) /* 32 MHz */ +#define _03_CGC_HOCO_CLK_54 (0x03U) /* 54 MHz */ + +/* + Oscillation Stop Detection Control Register (OSTDCR) +*/ +/* Oscillation Stop Detection Interrupt Enable (OSTDIE) */ +#define _00_CGC_OSC_STOP_INT_DISABLE (0x00U) /* The oscillation stop detection interrupt is disabled */ +#define _01_CGC_OSC_STOP_INT_ENABLE (0x01U) /* The oscillation stop detection interrupt is enabled */ +/* Oscillation Stop Detection Function Enable (OSTDE) */ +#define _00_CGC_OSC_STOP_DISABLE (0x00U) /* Oscillation stop detection function is disabled */ +#define _80_CGC_OSC_STOP_ENABLE (0x80U) /* Oscillation stop detection function is enabled */ + +/* + Main Clock Oscillator Wait Control Register (MOSCWTCR) +*/ +/* Main Clock Oscillator Wait Time (MSTS[4:0]) */ +#define _00_CGC_OSC_WAIT_CYCLE_2 (0x00U) /* Wait time = 2 cycles */ +#define _01_CGC_OSC_WAIT_CYCLE_1024 (0x01U) /* Wait time = 1024 cycles */ +#define _02_CGC_OSC_WAIT_CYCLE_2048 (0x02U) /* Wait time = 2048 cycles */ +#define _03_CGC_OSC_WAIT_CYCLE_4096 (0x03U) /* Wait time = 4096 cycles */ +#define _04_CGC_OSC_WAIT_CYCLE_8192 (0x04U) /* Wait time = 8192 cycles */ +#define _05_CGC_OSC_WAIT_CYCLE_16384 (0x05U) /* Wait time = 16384 cycles */ +#define _06_CGC_OSC_WAIT_CYCLE_32768 (0x06U) /* Wait time = 32768 cycles */ +#define _07_CGC_OSC_WAIT_CYCLE_65536 (0x07U) /* Wait time = 65536 cycles */ + +/* + Clock Output Control Register (CKOCR) +*/ +/* Clock Output Source Select (CKOSEL[2:0]) */ +#define _0000_CGC_CLKOUT_LOCO (0x0000U) /* LOCO */ +#define _0100_CGC_CLKOUT_HOCO (0x0100U) /* HOCO */ +#define _0200_CGC_CLKOUT_MAINCLK (0x0200U) /* Main clock oscillator */ +#define _0300_CGC_CLKOUT_SUBCLK (0x0300U) /* Sub-clock oscillator */ +#define _0400_CGC_CLKOUT_PLLCLK (0x0400U) /* PLL clock oscillator */ +/* Clock Output Division Ratio Select (CKODIV[2:0]) */ +#define _0000_CGC_CLKOUT_DIV_1 (0x0000U) /* x1 */ +#define _1000_CGC_CLKOUT_DIV_2 (0x1000U) /* x1/2 */ +#define _2000_CGC_CLKOUT_DIV_4 (0x2000U) /* x1/4 */ +#define _3000_CGC_CLKOUT_DIV_8 (0x3000U) /* x1/8 */ +#define _4000_CGC_CLKOUT_DIV_16 (0x4000U) /* x1/16 */ +/* Clock Output Control (CKOSTP) */ +#define _0000_CGC_CLKOUT_ENABLE (0x0000U) /* CLKOUT pin output is operating */ +#define _8000_CGC_CLKOUT_DISABLE (0x8000U) /* CLKOUT pin output is stopped (fixed at low level) */ + +/* + Main Clock Oscillator Forced Oscillation Control Register (MOFCR) +*/ +/* Main Oscillator Drive Capability Switch (MODRV21) */ +#define _00_CGC_MAINOSC_UNDER10M (0x00U) /* 1 MHz to 10 MHz */ +#define _20_CGC_MAINOSC_OVER10M (0x20U) /* 10 MHz to 20 MHz */ +/* Main Clock Oscillator Switch (MOSEL) */ +#define _00_CGC_MAINOSC_RESONATOR (0x00U) /* Resonator */ +#define _40_CGC_MAINOSC_EXTERNAL (0x40U) /* External oscillator input */ + +/* + Low-power timer control register 1 (LPTCR1) +*/ +/* Low-Power Timer Clock Division Ratio Select (LPCNTPSSEL[2:0]) */ +#define _01_CGC_LPT_CLK_DIV_2 (0x01U) /* x1/2 */ +#define _02_CGC_LPT_CLK_DIV_4 (0x02U) /* x1/4 */ +#define _03_CGC_LPT_CLK_DIV_8 (0x03U) /* x1/8 */ +#define _04_CGC_LPT_CLK_DIV_16 (0x04U) /* x1/16 */ +#define _05_CGC_LPT_CLK_DIV_32 (0x05U) /* x1/32 */ +/* Low-Power Timer Clock Source Select (LPCNTCKSEL) */ +#define _00_CGC_LPT_SOURCE_SUB (0x00U) /* Sub-clock */ +#define _10_CGC_LPT_SOURCE_IWDT (0x10U) /* IWDT-dedicated on-chip */ + + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_CGC_Create(void); + +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc_user.c b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc_user.c new file mode 100644 index 000000000..611001e2a --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc_user.c @@ -0,0 +1,52 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cgc_user.c +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : GCCRX +* Description : This file implements device driver for CGC module. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_hardware_setup.c b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_hardware_setup.c new file mode 100644 index 000000000..f1bd64fd1 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_hardware_setup.c @@ -0,0 +1,92 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_hardware_setup.c +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : GCCRX +* Description : This file implements system initializing function. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +int HardwareSetup(void); +void R_Systeminit(void); + +/*********************************************************************************************************************** +* Function Name: R_Systeminit +* Description : This function initializes every macro. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_Systeminit(void) +{ + /* Enable writing to registers related to operating modes, LPC, LPT, LVD, CGC and software reset */ + SYSTEM.PRCR.WORD = 0xA50FU; + + /* Enable writing to MPC pin function control registers */ + MPC.PWPR.BIT.B0WI = 0U; + MPC.PWPR.BIT.PFSWE = 1U; + + /* Set peripheral settings */ + R_CGC_Create(); + + /* Disable writing to MPC pin function control registers */ + MPC.PWPR.BIT.PFSWE = 0U; + MPC.PWPR.BIT.B0WI = 1U; + + /* Enable protection */ + SYSTEM.PRCR.WORD = 0xA500U; +} +/*********************************************************************************************************************** +* Function Name: HardwareSetup +* Description : This function initializes hardware setting. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +int HardwareSetup(void) +{ + R_Systeminit(); + + return (1U); +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_interrupt_handlers.h b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_interrupt_handlers.h new file mode 100644 index 000000000..c306c8b2e --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_interrupt_handlers.h @@ -0,0 +1,72 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_interrupt_handlers.h +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : GCCRX +* Description : This file declares interrupt handlers. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ +#ifndef INTERRUPT_HANDLERS_H +#define INTERRUPT_HANDLERS_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ + +/* Undefined */ +void r_undefined_exception(void) __attribute__ ((interrupt)); + +/* Access Exception */ +void r_access_exception(void) __attribute__ ((interrupt)); + +/* Privileged Instruction Exception */ +void r_privileged_exception(void) __attribute__ ((interrupt)); + +/* Floating Point Exception */ +void r_floatingpoint_exception(void) __attribute__ ((interrupt)); + +/* NMI */ +void r_nmi_exception(void) __attribute__ ((interrupt)); + +/* BRK */ +void r_brk_exception(void) __attribute__ ((interrupt)); + +/* Hardware Vectors */ +void PowerON_Reset(void) __attribute__ ((interrupt)); + +/* Idle Vectors */ +void r_undefined_exception(void) __attribute__ ((interrupt)); +void r_reserved_exception(void) __attribute__ ((interrupt)); + +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_macrodriver.h b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_macrodriver.h new file mode 100644 index 000000000..e8e55270d --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_macrodriver.h @@ -0,0 +1,98 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_macrodriver.h +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : GCCRX +* Description : This file implements general head file. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ +#ifndef STATUS_H +#define STATUS_H +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "../iodefine.h" +#include "r_cg_interrupt_handlers.h" + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#ifndef __TYPEDEF__ + +/* Status list definition */ +#define MD_STATUSBASE (0x00U) +#define MD_OK (MD_STATUSBASE + 0x00U) /* register setting OK */ +#define MD_SPT (MD_STATUSBASE + 0x01U) /* IIC stop */ +#define MD_NACK (MD_STATUSBASE + 0x02U) /* IIC no ACK */ +#define MD_BUSY1 (MD_STATUSBASE + 0x03U) /* busy 1 */ +#define MD_BUSY2 (MD_STATUSBASE + 0x04U) /* busy 2 */ + +/* Error list definition */ +#define MD_ERRORBASE (0x80U) +#define MD_ERROR (MD_ERRORBASE + 0x00U) /* error */ +#define MD_ARGERROR (MD_ERRORBASE + 0x01U) /* error argument input error */ +#define MD_ERROR1 (MD_ERRORBASE + 0x02U) /* error 1 */ +#define MD_ERROR2 (MD_ERRORBASE + 0x03U) /* error 2 */ +#define MD_ERROR3 (MD_ERRORBASE + 0x04U) /* error 3 */ +#define MD_ERROR4 (MD_ERRORBASE + 0x05U) /* error 4 */ +#define MD_ERROR5 (MD_ERRORBASE + 0x06U) /* error 5 */ + + +#define nop() asm("nop;") +#define brk() asm("brk;") +#define wait() asm("wait;") + +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +#ifndef __TYPEDEF__ + #ifndef _STDINT_H + typedef signed char int8_t; + typedef unsigned char uint8_t; + typedef signed short int16_t; + typedef unsigned short uint16_t; + typedef signed long int32_t; + typedef unsigned long uint32_t; + + typedef signed char int_least8_t; + typedef signed short int_least16_t; + typedef signed long int_least32_t; + typedef unsigned char uint_least8_t; + typedef unsigned short uint_least16_t; + typedef unsigned long uint_least32_t; + #endif + + typedef unsigned short MD_STATUS; + #define __TYPEDEF__ +#endif + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ + +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_main.c b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_main.c new file mode 100644 index 000000000..4807a41f7 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_main.c @@ -0,0 +1,90 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_main.c +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : GCCRX +* Description : This file implements main function. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + + +void R_MAIN_UserInit(void); +/*********************************************************************************************************************** +* Function Name: main +* Description : This function implements main function. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void main(void) +{ + R_MAIN_UserInit(); + /* Start user code. Do not edit comment generated here */ + while (1U) + { + ; + } + /* End user code. Do not edit comment generated here */ +} +/*********************************************************************************************************************** +* Function Name: R_MAIN_UserInit +* Description : This function adds user code before implementing main function. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_MAIN_UserInit(void) +{ + /* Start user code. Do not edit comment generated here */ + uint16_t protect_dummy = (uint16_t)(SYSTEM.PRCR.WORD & 0x000FU); + + /* Disable protect bit */ + SYSTEM.PRCR.WORD = 0xA50FU; + + SYSTEM.VBATTCR.BYTE = 0x81U; + + /* Restore the previous state of the protect register */ + SYSTEM.PRCR.WORD = (uint16_t)(0xA500U | protect_dummy); + /* End user code. Do not edit comment generated here */ +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_reset_program.asm b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_reset_program.asm new file mode 100644 index 000000000..197bc41ce --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_reset_program.asm @@ -0,0 +1,195 @@ +;;/********************************************************************************************************************* +;;* DISCLAIMER +;;* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +;;* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +;;* applicable laws, including copyright laws. +;;* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +;;* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +;;* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +;;* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +;;* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +;;* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +;;* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +;;* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +;;* following link: +;;* http://www.renesas.com/disclaimer +;;* +;;* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +;;*********************************************************************************************************************/ +;;/* +;;********************************************************************************************************************** +;;* File Name : r_cg_reset_program.asm +;;* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +;;* Device(s) : R5F52318AxFP +;;* Tool-Chain : GCCRX +;;* Description : This is start up file for RX. +;;* Creation Date: 23/09/2015 +;;********************************************************************************************************************** +;;*/ + +;;reset_program.asm + + .list + .section .text + .global _PowerON_Reset ;;global Start routine + + .extern _HardwareSetup ;;external Sub-routine to initialise Hardware + .extern _data + .extern _mdata + .extern _ebss + .extern _bss + .extern _edata + .extern _main + .extern _ustack + .extern _istack + .extern _rvectors + .extern _exit + + +_PowerON_Reset : +;;initialise user stack pointer + mvtc #_ustack,USP + +;;initialise interrupt stack pointer + mvtc #_istack,ISP + +#ifdef __RXv2__ +;; setup exception vector + mvtc #_ExceptVectors, extb ;;EXCEPTION VECTOR ADDRESS +#endif +;;setup intb + mvtc #_rvectors_start, intb ;;INTERRUPT VECTOR ADDRESS definition + +;;setup FPSW + mvtc #100h, fpsw + +;;load data section from ROM to RAM + + mov #_mdata,r2 ;;src ROM address of data section in R2 + mov #_data,r1 ;;dest start RAM address of data section in R1 + mov #_edata,r3 ;;end RAM address of data section in R3 + sub r1,r3 ;;size of data section in R3 (R3=R3-R1) + smovf ;;block copy R3 bytes from R2 to R1 + +;;bss initialisation : zero out bss + + mov #00h,r2 ;;load R2 reg with zero + mov #_ebss, r3 ;;store the end address of bss in R3 + mov #_bss, r1 ;;store the start address of bss in R1 + sub r1,r3 ;;ize of bss section in R3 (R3=R3-R1) + sstr.b +;;call the hardware initialiser + bsr.a _HardwareSetup + nop + +;;setup PSW + mvtc #10000h, psw ;;Set Ubit & Ibit for PSW + +;;change PSW PM to user-mode + MVFC PSW,R1 +;;DO NOT CHANGE TO USER MODE OR #00100000h,R1 + PUSH.L R1 + MVFC PC,R1 + ADD #10,R1 + PUSH.L R1 + RTE + NOP + NOP +#ifdef CPPAPP + bsr.a __rx_init +#endif +;;start user program + bsr.a _main + bsr.a _exit + +#ifdef CPPAPP + .global _rx_run_preinit_array + .type _rx_run_preinit_array,@function +_rx_run_preinit_array: + mov #__preinit_array_start,r1 + mov #__preinit_array_end,r2 + bra.a _rx_run_inilist + + .global _rx_run_init_array + .type _rx_run_init_array,@function +_rx_run_init_array: + mov #__init_array_start,r1 + mov #__init_array_end,r2 + mov #4, r3 + bra.a _rx_run_inilist + + .global _rx_run_fini_array + .type _rx_run_fini_array,@function +_rx_run_fini_array: + mov #__fini_array_start,r2 + mov #__fini_array_end,r1 + mov #-4, r3 + ;;fall through + +_rx_run_inilist: +next_inilist: + cmp r1,r2 + beq.b done_inilist + mov.l [r1],r4 + cmp #-1, r4 + beq.b skip_inilist + cmp #0, r4 + beq.b skip_inilist + pushm r1-r3 + jsr r4 + popm r1-r3 +skip_inilist: + add r3,r1 + bra.b next_inilist +done_inilist: + rts + + .section .init,"ax" + .balign 4 + + .global __rx_init +__rx_init: + + .section .fini,"ax" + .balign 4 + + .global __rx_fini +__rx_fini: + bsr.a _rx_run_fini_array + + .section .sdata + .balign 4 + .global __gp + .weak __gp +__gp: + + .section .data + .global ___dso_handle + .weak ___dso_handle +___dso_handle: + .long 0 + + .section .init,"ax" + bsr.a _rx_run_preinit_array + bsr.a _rx_run_init_array + rts + + .global __rx_init_end +__rx_init_end: + + .section .fini,"ax" + + rts + .global __rx_fini_end +__rx_fini_end: + +#endif + +;;call to exit +_exit: + bra _loop_here +_loop_here: + bra _loop_here + + .text + .end diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_userdefine.h b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_userdefine.h new file mode 100644 index 000000000..02e722de2 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_userdefine.h @@ -0,0 +1,37 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_userdefine.h +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : GCCRX +* Description : This file includes user definition. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ +#ifndef _USER_DEF_H +#define _USER_DEF_H + +/*********************************************************************************************************************** +User definitions +***********************************************************************************************************************/ + +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_vector_table.c b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_vector_table.c new file mode 100644 index 000000000..0218fd306 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_vector_table.c @@ -0,0 +1,467 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_vector_table.c +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : GCCRX +* Description : This file implements interrupt vector. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +typedef void (*fp) (void); +extern void PowerON_Reset (void); +extern void stack (void); + +#define OFS0_VAL 0xFFFFFFFFUL +#define OFS1_VAL 0xFFFFFFFFUL +#define EXVECT_SECT __attribute__ ((section (".exvectors"))) + +const void *ExceptVectors[] EXVECT_SECT = { +/* Start user code for adding. Do not edit comment generated here */ + /* 0xffffff80 MDE register */ +#ifdef __RX_BIG_ENDIAN__ + /* Big endian */ + (fp)0xfffffff8, +#else + /* Little endian */ + (fp)0xffffffff, +#endif + /* 0xffffff84 Reserved */ + r_reserved_exception, + /* 0xffffff88 OFS1 register */ + (fp) OFS1_VAL, + /* 0xffffff8c OFS0 register */ + (fp) OFS0_VAL, + /* 0xffffff90 Reserved */ + r_reserved_exception, + /* 0xffffff94 Reserved */ + r_reserved_exception, + /* 0xffffff98 Reserved */ + r_reserved_exception, + /* 0xffffff9c Reserved */ + r_reserved_exception, + /* 0xffffffa0 ID */ + (fp)0xffffffff, + /* 0xffffffa4 ID */ + (fp)0xffffffff, + /* 0xffffffa8 ID */ + (fp)0xffffffff, + /* 0xffffffac ID */ + (fp)0xffffffff, + /* 0xffffffb0 Reserved */ + r_reserved_exception, + /* 0xffffffb4 Reserved */ + r_reserved_exception, + /* 0xffffffb8 Reserved */ + r_reserved_exception, + /* 0xffffffbc Reserved */ + r_reserved_exception, + /* 0xffffffc0 Reserved */ + r_reserved_exception, + /* 0xffffffc4 Reserved */ + r_reserved_exception, + /* 0xffffffc8 Reserved */ + r_reserved_exception, + /* 0xffffffcc Reserved */ + r_reserved_exception, + /* 0xffffffd0 Exception(Supervisor Instruction) */ + r_privileged_exception, + /* 0xffffffd4 Exception(Access Instruction) */ + r_access_exception, + /* 0xffffffd8 Reserved */ + r_undefined_exception, + /* 0xffffffdc Exception(Undefined Instruction) */ + r_undefined_exception, + /* 0xffffffe0 Reserved */ + r_undefined_exception, + /* 0xffffffe4 Exception(Floating Point) */ + r_floatingpoint_exception, + /* 0xffffffe8 Reserved */ + r_undefined_exception, + /* 0xffffffec Reserved */ + r_undefined_exception, + /* 0xfffffff0 Reserved */ + r_undefined_exception, + /* 0xfffffff4 Reserved */ + r_undefined_exception, + /* 0xfffffff8 NMI */ + r_nmi_exception +/* End user code. Do not edit comment generated here */ +}; + +#define FVECT_SECT __attribute__ ((section (".fvectors"))) +const void *HardwareVectors[] FVECT_SECT = { + /* 0xfffffffc RESET */ + /* <> */ + /* Power On Reset PC */ + PowerON_Reset + /* <> */ +}; + +#define RVECT_SECT __attribute__ ((section (".rvectors"))) + +const fp RelocatableVectors[] RVECT_SECT = { + /* 0x0000 Reserved */ + (fp)r_reserved_exception, + /* 0x0004 Reserved */ + (fp)r_reserved_exception, + /* 0x0008 Reserved */ + (fp)r_reserved_exception, + /* 0x000C Reserved */ + (fp)r_reserved_exception, + /* 0x0010 Reserved */ + (fp)r_reserved_exception, + /* 0x0014 Reserved */ + (fp)r_reserved_exception, + /* 0x0018 Reserved */ + (fp)r_reserved_exception, + /* 0x001C Reserved */ + (fp)r_reserved_exception, + /* 0x0020 Reserved */ + (fp)r_reserved_exception, + /* 0x0024 Reserved */ + (fp)r_reserved_exception, + /* 0x0028 Reserved */ + (fp)r_reserved_exception, + /* 0x002C Reserved */ + (fp)r_reserved_exception, + /* 0x0030 Reserved */ + (fp)r_reserved_exception, + /* 0x0034 Reserved */ + (fp)r_reserved_exception, + /* 0x0038 Reserved */ + (fp)r_reserved_exception, + /* 0x003C Reserved */ + (fp)r_reserved_exception, + /* 0x0040 BSC BUSERR */ + (fp)r_undefined_exception, + /* 0x0044 Reserved */ + (fp)r_reserved_exception, + /* 0x0048 Reserved */ + (fp)r_undefined_exception, + /* 0x004C Reserved */ + (fp)r_reserved_exception, + /* 0x0050 Reserved */ + (fp)r_reserved_exception, + /* 0x0054 Reserved */ + (fp)r_undefined_exception, + /* 0x0058 Reserved */ + (fp)r_reserved_exception, + /* 0x005C Reserved */ + (fp)r_undefined_exception, + /* 0x0060 Reserved */ + (fp)r_reserved_exception, + /* 0x0064 Reserved */ + (fp)r_reserved_exception, + /* 0x0068 ICU SWINT2 */ + (fp)r_undefined_exception, + /* 0x006C ICU SWINT */ + (fp)r_undefined_exception, + /* 0x0070 CMT0 */ + (fp)r_undefined_exception, + /* 0x0074 CMT1 */ + (fp)r_undefined_exception, + /* 0x0078 CMTW0 */ + (fp)r_undefined_exception, + /* 0x007C CMTW1 */ + (fp)r_undefined_exception, + /* 0x0080 USBA D0FIFO2 */ + (fp)r_undefined_exception, + /* 0x0084 USBA D1FIFO2 */ + (fp)r_undefined_exception, + /* 0x0088 USB0 D0FIFO0 */ + (fp)r_undefined_exception, + /* 0x008C USB0 D0FIFO0 */ + (fp)r_undefined_exception, + /* 0x0090 Reserved */ + (fp)r_reserved_exception, + /* 0x0094 Reserved */ + (fp)r_reserved_exception, + /* 0x0098 RSPI0 SPRI0 */ + (fp)r_undefined_exception, + /* 0x009C RSPI0 SPTI0 */ + (fp)r_undefined_exception, + /* 0x00A0 RSPI1 SPRI1 */ + (fp)r_undefined_exception, + /* 0x00A4 RSPI1 SPTI1 */ + (fp)r_undefined_exception, + /* 0x00A8 QSPI SPRI */ + (fp)r_undefined_exception, + /* 0x00AC QSPI SPTI */ + (fp)r_undefined_exception, + /* 0x00B0 SDHI SBFAI */ + (fp)r_undefined_exception, + /* 0x00B4 MMC MBFAI */ + (fp)r_undefined_exception, + /* 0x00B8 SSI0 SSITX0 */ + (fp)r_undefined_exception, + /* 0x00BC SSI0 SSIRX0 */ + (fp)r_undefined_exception, + /* 0x00C0 SSI1 SSIRTI1 */ + (fp)r_undefined_exception, + /* 0x00C4 Reserved */ + (fp)r_reserved_exception, + /* 0x00C8 SRC IDEI */ + (fp)r_undefined_exception, + /* 0x00CC SRC ODFI */ + (fp)r_undefined_exception, + /* 0x00E0 Reserved */ + (fp)r_reserved_exception, + /* 0x00E4 Reserved */ + (fp)r_reserved_exception, + /* 0x00E8 SCI0 RXI0 */ + (fp)r_undefined_exception, + /* 0x00EC SCI0 TXI0 */ + (fp)r_undefined_exception, + /* 0x00F0 SCI1 RXI1 */ + (fp)r_undefined_exception, + /* 0x00F4 SCI1 TXI1 */ + (fp)r_undefined_exception, + /* 0x00F8 SCI2 RXI2 */ + (fp)r_undefined_exception, + /* 0x00FC SCI2 TXI2 */ + (fp)r_undefined_exception, + /* 0x0100 ICU IRQ0 */ + (fp)r_undefined_exception, + /* 0x0104 ICU IRQ1 */ + (fp)r_undefined_exception, + /* 0x0108 ICU IRQ2 */ + (fp)r_undefined_exception, + /* 0x010C ICU IRQ3 */ + (fp)r_undefined_exception, + /* 0x0110 ICU IRQ4 */ + (fp)r_undefined_exception, + /* 0x0114 ICU IRQ5 */ + (fp)r_undefined_exception, + /* 0x0118 ICU IRQ6 */ + (fp)r_undefined_exception, + /* 0x011C ICU IRQ7 */ + (fp)r_undefined_exception, + /* 0x0120 ICU IRQ8 */ + (fp)r_undefined_exception, + /* 0x0124 ICU IRQ9 */ + (fp)r_undefined_exception, + /* 0x0128 ICU IRQ10 */ + (fp)r_undefined_exception, + /* 0x012C ICU IRQ11 */ + (fp)r_undefined_exception, + /* 0x0130 ICU IRQ12 */ + (fp)r_undefined_exception, + /* 0x0134 ICU IRQ13 */ + (fp)r_undefined_exception, + /* 0x0138 ICU IRQ14 */ + (fp)r_undefined_exception, + /* 0x013C ICU IRQ15 */ + (fp)r_undefined_exception, + /* 0x0140 SCI3 RXI3 */ + (fp)r_undefined_exception, + /* 0x0144 SCI3 TXI3 */ + (fp)r_undefined_exception, + /* 0x0148 SCI4 RXI4 */ + (fp)r_undefined_exception, + /* 0x014C SCI4 TXI4 */ + (fp)r_undefined_exception, + /* 0x0150 SCI5 RXI5 */ + (fp)r_undefined_exception, + /* 0x0154 SCI5 TXI5 */ + (fp)r_undefined_exception, + /* 0x0158 SCI6 RXI6 */ + (fp)r_undefined_exception, + /* 0x015C SCI6 TXI6 */ + (fp)r_undefined_exception, + /* 0x0160 LVD LVD1 */ + (fp)r_undefined_exception, + /* 0x0164 LVD LVD2 */ + (fp)r_undefined_exception, + /* 0x0168 USB0 USBR0 */ + (fp)r_undefined_exception, + /* 0x016C Reserved */ + (fp)r_reserved_exception, + /* 0x0170 RTC ALM */ + (fp)r_undefined_exception, + /* 0x0174 RTC PRD */ + (fp)r_undefined_exception, + /* 0x0178 USBA USBHSR */ + (fp)r_undefined_exception, + /* 0x0184 PDC PCDFI */ + (fp)r_undefined_exception, + /* 0x0188 SCI7 RXI7 */ + (fp)r_undefined_exception, + /* 0x018C SCI7 TXI7 */ + (fp)r_undefined_exception, + /* 0x0190 SCIFA8 RXIF8 */ + (fp)r_undefined_exception, + /* 0x0194 SCIF8 TXIF8 */ + (fp)r_undefined_exception, + /* 0x0198 SCIF9 RXIF9 */ + (fp)r_undefined_exception, + /* 0x019C SCIF9 TXIF9 */ + (fp)r_undefined_exception, + /* 0x01A0 SCIF10 RXIF10 */ + (fp)r_undefined_exception, + /* 0x01A4 SCIF10 TXIF10 */ + (fp)r_undefined_exception, + /* 0x01A8 ICU GROUP_BE0 */ + (fp)r_undefined_exception, + /* 0x01AC Reserved */ + (fp)r_reserved_exception, + /* 0x01B0 Reserved */ + (fp)r_reserved_exception, + /* 0x01B4 Reserved */ + (fp)r_reserved_exception, + /* 0x01B8 ICU GROUP_BL0 */ + (fp)r_undefined_exception, + /* 0x01BC ICU GROUP_BL1 */ + (fp)r_undefined_exception, + /* 0x01C0 ICU GROUP_AL0 */ + (fp)r_undefined_exception, + /* 0x01C4 ICU GROUP_AL1 */ + (fp)r_undefined_exception, + /* 0x01C8 SCIF11 RXIF11 */ + (fp)r_undefined_exception, + /* 0x01CC SCIF11 TXIF11 */ + (fp)r_undefined_exception, + /* 0x01D0 SCI12 RXI12 */ + (fp)r_undefined_exception, + /* 0x01D4 SCI12 TXI12 */ + (fp)r_undefined_exception, + /* 0x01D8 Reserved */ + (fp)r_reserved_exception, + /* 0x01DC Reserved */ + (fp)r_reserved_exception, + /* 0x01F4 OST OST */ + (fp)r_undefined_exception, + /* 0x01F8 EXDMAC EXDMAC0I */ + (fp)r_undefined_exception, + /* 0x01FC EXDMAC EXDMAC1I */ + (fp)r_undefined_exception, + /* 0x0318 DMAC DMAC0I */ + (fp)r_undefined_exception, + /* 0x031C DMAC DMAC1I */ + (fp)r_undefined_exception, + /* 0x0320 DMAC DMAC2I */ + (fp)r_undefined_exception, + /* 0x0324 DMAC DMAC3I */ + (fp)r_undefined_exception, + /* 0x03D8 RIIC0 EEI0 */ + (fp)r_undefined_exception, + /* 0x03DC RIIC0 RXI0 */ + (fp)r_undefined_exception, + /* 0x03E0 RIIC0 TXI0 */ + (fp)r_undefined_exception, + /* 0x03E4 RIIC0 TEI0 */ + (fp)r_undefined_exception, + +}; + +/*********************************************************************************************************************** +* Function Name: r_undefined_exception +* Description : None +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void r_undefined_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} +/*********************************************************************************************************************** +* Function Name: r_reserved_exception +* Description : None +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void r_reserved_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} +/*********************************************************************************************************************** +* Function Name: r_nmi_exception +* Description : None +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void r_nmi_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} +/*********************************************************************************************************************** +* Function Name: r_brk_exception +* Description : None +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void r_brk_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} +/*********************************************************************************************************************** +* Function Name: r_privileged_exception +* Description : None +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void r_privileged_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} +/*********************************************************************************************************************** +* Function Name: r_access_exception +* Description : None +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void r_access_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} +/*********************************************************************************************************************** +* Function Name: r_floatingpoint_exception +* Description : None +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void r_floatingpoint_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/iodefine.h b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/iodefine.h new file mode 100644 index 000000000..ded747368 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/iodefine.h @@ -0,0 +1,22195 @@ +/***************************************************************/ +/* */ +/* PROJECT NAME : RTOSDemo */ +/* FILE : iodefine.h */ +/* DESCRIPTION : Definition of I/O Registers */ +/* CPU SERIES : RX200 */ +/* CPU TYPE : RX231 */ +/* */ +/* This file is generated by e2 studio. */ +/* */ +/***************************************************************/ + + + + +/********************************************************************************* +* +* Device : RX/RX200/RX231 +* +* File Name : iodefine.h +* +* Abstract : Definition of I/O Register. +* +* History : 0.5A (2014-09-18) [Hardware Manual Revision : 0.50] +* : 1.0A (2015-05-18) [Hardware Manual Revision : 1.00] +* : 1.0C (2015-07-21) [Hardware Manual Revision : 1.00] +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright (C) 2015 (2014) Renesas Electronics Corporation. +* +*********************************************************************************/ +/********************************************************************************/ +/* */ +/* DESCRIPTION : Definition of ICU Register */ +/* CPU TYPE : RX231 */ +/* */ +/* Usage : IR,DTCER,IER,IPR of ICU Register */ +/* The following IR, DTCE, IEN, IPR macro functions simplify usage. */ +/* The bit access operation is "Bit_Name(interrupt source,name)". */ +/* A part of the name can be omitted. */ +/* for example : */ +/* IR(MTU0,TGIA0) = 0; expands to : */ +/* ICU.IR[114].BIT.IR = 0; */ +/* */ +/* DTCE(ICU,IRQ0) = 1; expands to : */ +/* ICU.DTCER[64].BIT.DTCE = 1; */ +/* */ +/* IEN(CMT0,CMI0) = 1; expands to : */ +/* ICU.IER[0x03].BIT.IEN4 = 1; */ +/* */ +/* IPR(MTU1,TGIA1) = 2; expands to : */ +/* IPR(MTU1,TGI ) = 2; // TGIA1,TGIB1 share IPR level. */ +/* ICU.IPR[121].BIT.IPR = 2; */ +/* */ +/* IPR(SCI0,ERI0) = 3; expands to : */ +/* IPR(SCI0, ) = 3; // SCI0 uses single IPR for all sources. */ +/* ICU.IPR[214].BIT.IPR = 3; */ +/* */ +/* Usage : #pragma interrupt Function_Identifier(vect=**) */ +/* The number of vector is "(interrupt source, name)". */ +/* for example : */ +/* #pragma interrupt INT_IRQ0(vect=VECT(ICU,IRQ0)) expands to : */ +/* #pragma interrupt INT_IRQ0(vect=64) */ +/* #pragma interrupt INT_CMT0_CMI0(vect=VECT(CMT0,CMI0)) expands to : */ +/* #pragma interrupt INT_CMT0_CMI0(vect=28) */ +/* #pragma interrupt INT_MTU0_TGIA0(vect=VECT(MTU0,TGIA0)) expands to : */ +/* #pragma interrupt INT_MTU0_TGIA0(vect=114) */ +/* #pragma interrupt INT_TPU0_TGI0A(vect=VECT(TPU0,TGI0A)) expands to : */ +/* #pragma interrupt INT_TPU0_TGI0A(vect=142) */ +/* */ +/* Usage : MSTPCRA,MSTPCRB,MSTPCRC of SYSTEM Register */ +/* The bit access operation is "MSTP(name)". */ +/* The name that can be used is a macro name defined with "iodefine.h". */ +/* for example : */ +/* MSTP(TMR2) = 0; // TMR2,TMR3,TMR23 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; */ +/* MSTP(SCI0) = 0; // SCI0,SMCI0 expands to : */ +/* SYSTEM.MSTPCRB.BIT.MSTPB31 = 0; */ +/* MSTP(MTU4) = 0; // MTU,MTU0,MTU1,MTU2,MTU3,MTU4,MTU5 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA9 = 0; */ +/* MSTP(TPU4) = 0; // TPU,TPU0,TPU1,TPU2,TPU3,TPU4,TPU5 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA13 = 0; */ +/* MSTP(CMT3) = 0; // CMT2,CMT3 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA14 = 0; */ +/* */ +/* */ +/********************************************************************************/ +#ifndef __RX231IODEFINE_HEADER__ +#define __RX231IODEFINE_HEADER__ + +#pragma pack(4) + +struct st_bsc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char STSCLR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char STSCLR : 1; +#endif + } BIT; + } BERCLR; + char wk0[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IGAEN : 1; + unsigned char TOEN : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TOEN : 1; + unsigned char IGAEN : 1; +#endif + } BIT; + } BEREN; + char wk1[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IA : 1; + unsigned char TO : 1; + unsigned char : 2; + unsigned char MST : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MST : 3; + unsigned char : 2; + unsigned char TO : 1; + unsigned char IA : 1; +#endif + } BIT; + } BERSR1; + char wk2[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 3; + unsigned short ADDR : 13; +#else + unsigned short ADDR : 13; + unsigned short : 3; +#endif + } BIT; + } BERSR2; + char wk3[4]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short BPRA : 2; + unsigned short BPRO : 2; + unsigned short BPIB : 2; + unsigned short BPGB : 2; + unsigned short BPHB : 2; + unsigned short BPFB : 2; + unsigned short BPEB : 2; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short BPEB : 2; + unsigned short BPFB : 2; + unsigned short BPHB : 2; + unsigned short BPGB : 2; + unsigned short BPIB : 2; + unsigned short BPRO : 2; + unsigned short BPRA : 2; +#endif + } BIT; + } BUSPRI; + char wk4[7408]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif + } BIT; + } CS0MOD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif + } BIT; + } CS0WCR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif + } BIT; + } CS0WCR2; + char wk5[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif + } BIT; + } CS1MOD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif + } BIT; + } CS1WCR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif + } BIT; + } CS1WCR2; + char wk6[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif + } BIT; + } CS2MOD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif + } BIT; + } CS2WCR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif + } BIT; + } CS2WCR2; + char wk7[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif + } BIT; + } CS3MOD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif + } BIT; + } CS3WCR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif + } BIT; + } CS3WCR2; + char wk8[1990]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif + } BIT; + } CS0CR; + char wk9[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif + } BIT; + } CS0REC; + char wk10[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif + } BIT; + } CS1CR; + char wk11[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif + } BIT; + } CS1REC; + char wk12[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif + } BIT; + } CS2CR; + char wk13[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif + } BIT; + } CS2REC; + char wk14[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif + } BIT; + } CS3CR; + char wk15[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif + } BIT; + } CS3REC; + char wk16[68]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RCVEN0 : 1; + unsigned short RCVEN1 : 1; + unsigned short RCVEN2 : 1; + unsigned short RCVEN3 : 1; + unsigned short RCVEN4 : 1; + unsigned short RCVEN5 : 1; + unsigned short RCVEN6 : 1; + unsigned short RCVEN7 : 1; + unsigned short RCVENM0 : 1; + unsigned short RCVENM1 : 1; + unsigned short RCVENM2 : 1; + unsigned short RCVENM3 : 1; + unsigned short RCVENM4 : 1; + unsigned short RCVENM5 : 1; + unsigned short RCVENM6 : 1; + unsigned short RCVENM7 : 1; +#else + unsigned short RCVENM7 : 1; + unsigned short RCVENM6 : 1; + unsigned short RCVENM5 : 1; + unsigned short RCVENM4 : 1; + unsigned short RCVENM3 : 1; + unsigned short RCVENM2 : 1; + unsigned short RCVENM1 : 1; + unsigned short RCVENM0 : 1; + unsigned short RCVEN7 : 1; + unsigned short RCVEN6 : 1; + unsigned short RCVEN5 : 1; + unsigned short RCVEN4 : 1; + unsigned short RCVEN3 : 1; + unsigned short RCVEN2 : 1; + unsigned short RCVEN1 : 1; + unsigned short RCVEN0 : 1; +#endif + } BIT; + } CSRECEN; +}; + +struct st_cac { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CFME : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CFME : 1; +#endif + } BIT; + } CACR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CACREFE : 1; + unsigned char FMCS : 3; + unsigned char TCSS : 2; + unsigned char EDGES : 2; +#else + unsigned char EDGES : 2; + unsigned char TCSS : 2; + unsigned char FMCS : 3; + unsigned char CACREFE : 1; +#endif + } BIT; + } CACR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RPS : 1; + unsigned char RSCS : 3; + unsigned char RCDS : 2; + unsigned char DFS : 2; +#else + unsigned char DFS : 2; + unsigned char RCDS : 2; + unsigned char RSCS : 3; + unsigned char RPS : 1; +#endif + } BIT; + } CACR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FERRIE : 1; + unsigned char MENDIE : 1; + unsigned char OVFIE : 1; + unsigned char : 1; + unsigned char FERRFCL : 1; + unsigned char MENDFCL : 1; + unsigned char OVFFCL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char OVFFCL : 1; + unsigned char MENDFCL : 1; + unsigned char FERRFCL : 1; + unsigned char : 1; + unsigned char OVFIE : 1; + unsigned char MENDIE : 1; + unsigned char FERRIE : 1; +#endif + } BIT; + } CAICR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FERRF : 1; + unsigned char MENDF : 1; + unsigned char OVFF : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char OVFF : 1; + unsigned char MENDF : 1; + unsigned char FERRF : 1; +#endif + } BIT; + } CASTR; + char wk0[1]; + unsigned short CAULVR; + unsigned short CALLVR; + unsigned short CACNTBR; +}; + +struct st_rscan { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TPRI : 1; + unsigned short DCE : 1; + unsigned short DRE : 1; + unsigned short MME : 1; + unsigned short DCS : 1; + unsigned short : 3; + unsigned short TSP : 4; + unsigned short TSSS : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short TSSS : 1; + unsigned short TSP : 4; + unsigned short : 3; + unsigned short DCS : 1; + unsigned short MME : 1; + unsigned short DRE : 1; + unsigned short DCE : 1; + unsigned short TPRI : 1; +#endif + } BIT; + } GCFGL; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ITRCP : 16; +#else + unsigned short ITRCP : 16; +#endif + } BIT; + } GCFGH; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GMDC : 2; + unsigned short GSLPR : 1; + unsigned short : 5; + unsigned short DEIE : 1; + unsigned short MEIE : 1; + unsigned short THLEIE : 1; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short THLEIE : 1; + unsigned short MEIE : 1; + unsigned short DEIE : 1; + unsigned short : 5; + unsigned short GSLPR : 1; + unsigned short GMDC : 2; +#endif + } BIT; + } GCTRL; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TSRST : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short TSRST : 1; +#endif + } BIT; + } GCTRH; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GRSTSTS : 1; + unsigned short GHLTSTS : 1; + unsigned short GSLPSTS : 1; + unsigned short GRAMINIT : 1; + unsigned short : 12; +#else + unsigned short : 12; + unsigned short GRAMINIT : 1; + unsigned short GSLPSTS : 1; + unsigned short GHLTSTS : 1; + unsigned short GRSTSTS : 1; +#endif + } BIT; + } GSTS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DEF : 1; + unsigned char MES : 1; + unsigned char THLES : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char THLES : 1; + unsigned char MES : 1; + unsigned char DEF : 1; +#endif + } BIT; + } GERFLL; + char wk0[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TS : 16; +#else + unsigned short TS : 16; +#endif + } BIT; + } GTSC; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RNC0 : 5; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short RNC0 : 5; +#endif + } BIT; + } GAFLCFG; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short NRXMB : 5; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short NRXMB : 5; +#endif + } BIT; + } RMNB; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMNS : 16; +#else + unsigned short RMNS : 16; +#endif + } BIT; + } RMND0; + char wk1[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFE : 1; + unsigned short RFIE : 1; + unsigned short : 6; + unsigned short RFDC : 3; + unsigned short : 1; + unsigned short RFIM : 1; + unsigned short RFIGCV : 3; +#else + unsigned short RFIGCV : 3; + unsigned short RFIM : 1; + unsigned short : 1; + unsigned short RFDC : 3; + unsigned short : 6; + unsigned short RFIE : 1; + unsigned short RFE : 1; +#endif + } BIT; + } RFCC0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFE : 1; + unsigned short RFIE : 1; + unsigned short : 6; + unsigned short RFDC : 3; + unsigned short : 1; + unsigned short RFIM : 1; + unsigned short RFIGCV : 3; +#else + unsigned short RFIGCV : 3; + unsigned short RFIM : 1; + unsigned short : 1; + unsigned short RFDC : 3; + unsigned short : 6; + unsigned short RFIE : 1; + unsigned short RFE : 1; +#endif + } BIT; + } RFCC1; + char wk2[4]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFEMP : 1; + unsigned short RFFLL : 1; + unsigned short RFMLT : 1; + unsigned short RFIF : 1; + unsigned short : 4; + unsigned short RFMC : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short RFMC : 6; + unsigned short : 4; + unsigned short RFIF : 1; + unsigned short RFMLT : 1; + unsigned short RFFLL : 1; + unsigned short RFEMP : 1; +#endif + } BIT; + } RFSTS0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFEMP : 1; + unsigned short RFFLL : 1; + unsigned short RFMLT : 1; + unsigned short RFIF : 1; + unsigned short : 4; + unsigned short RFMC : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short RFMC : 6; + unsigned short : 4; + unsigned short RFIF : 1; + unsigned short RFMLT : 1; + unsigned short RFFLL : 1; + unsigned short RFEMP : 1; +#endif + } BIT; + } RFSTS1; + char wk3[4]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFPC : 8; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short RFPC : 8; +#endif + } BIT; + } RFPCTR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFPC : 8; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short RFPC : 8; +#endif + } BIT; + } RFPCTR1; + char wk4[20]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RF0MLT : 1; + unsigned char RF1MLT : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char RF1MLT : 1; + unsigned char RF0MLT : 1; +#endif + } BIT; + } RFMSTS; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RF0IF : 1; + unsigned char RF1IF : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char RF1IF : 1; + unsigned char RF0IF : 1; +#endif + } BIT; + } RFISTS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CF0IF : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CF0IF : 1; +#endif + } BIT; + } CFISTS; + char wk6[36]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TSIF0 : 1; + unsigned short TAIF0 : 1; + unsigned short CFTIF0 : 1; + unsigned short THIF0 : 1; + unsigned short : 12; +#else + unsigned short : 12; + unsigned short THIF0 : 1; + unsigned short CFTIF0 : 1; + unsigned short TAIF0 : 1; + unsigned short TSIF0 : 1; +#endif + } BIT; + } GTINTSTS; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RPAGE : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short RPAGE : 1; +#endif + } BIT; + } GRWCR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short RTMPS : 3; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short RTMPS : 3; + unsigned short : 8; +#endif + } BIT; + } GTSTCFG; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char RTME : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char RTME : 1; + unsigned char : 2; +#endif + } BIT; + } GTSTCTRL; + char wk7[5]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short LOCK : 16; +#else + unsigned short LOCK : 16; +#endif + } BIT; + } GLOCKK; + char wk8[10]; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL0; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH0; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS0; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR0; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF00; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF10; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF20; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF30; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL1; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH1; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS1; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR1; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF01; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF11; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF21; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF31; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL2; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH2; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS2; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR2; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF02; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF12; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF22; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF32; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL3; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH3; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS3; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR3; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF03; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF13; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF23; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF33; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL4; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH4; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS4; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR4; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL6; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF04; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH6; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF14; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML6; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF24; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH6; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF34; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL6; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL5; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH6; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH5; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL7; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS5; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH7; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR5; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML7; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF05; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH7; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF15; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL7; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF25; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH7; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF35; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL8; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL6; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH8; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH6; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML8; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS6; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH8; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR6; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL8; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF06; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH8; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF16; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL9; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF26; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH9; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF36; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML9; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL7; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH9; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH7; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL9; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS7; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH9; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR7; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL10; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF07; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH10; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF17; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML10; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF27; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH10; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF37; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL10; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL8; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH10; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH8; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL11; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS8; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH11; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR8; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML11; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF08; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH11; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF18; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL11; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF28; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH11; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF38; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL9; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH9; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS9; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR9; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF09; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF19; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF29; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF39; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL10; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH10; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS10; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR10; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL14; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF010; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH14; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF110; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML14; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF210; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH14; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF310; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL14; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL11; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH14; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH11; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL15; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS11; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH15; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR11; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML15; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF011; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH15; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF111; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL15; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF211; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH15; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF311; + }; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF012; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF112; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF212; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF312; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF013; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF113; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF213; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF313; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL14; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH14; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS14; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR14; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF014; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF114; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF214; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF314; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL15; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH15; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS15; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR15; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF015; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF115; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF215; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF315; + char wk9[224]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC6; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC7; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC8; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC9; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC10; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC11; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC14; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC15; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFID : 16; +#else + unsigned short RFID : 16; +#endif + } BIT; + } RFIDL0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC16; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFID : 13; + unsigned short : 1; + unsigned short RFRTR : 1; + unsigned short RFIDE : 1; +#else + unsigned short RFIDE : 1; + unsigned short RFRTR : 1; + unsigned short : 1; + unsigned short RFID : 13; +#endif + } BIT; + } RFIDH0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC17; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFTS : 16; +#else + unsigned short RFTS : 16; +#endif + } BIT; + } RFTS0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC18; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFPTR : 12; + unsigned short RFDLC : 4; +#else + unsigned short RFDLC : 4; + unsigned short RFPTR : 12; +#endif + } BIT; + } RFPTR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC19; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFDB0 : 8; + unsigned short RFDB1 : 8; +#else + unsigned short RFDB1 : 8; + unsigned short RFDB0 : 8; +#endif + } BIT; + } RFDF00; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC20; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFDB2 : 8; + unsigned short RFDB3 : 8; +#else + unsigned short RFDB3 : 8; + unsigned short RFDB2 : 8; +#endif + } BIT; + } RFDF10; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC21; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFDB4 : 8; + unsigned short RFDB5 : 8; +#else + unsigned short RFDB5 : 8; + unsigned short RFDB4 : 8; +#endif + } BIT; + } RFDF20; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC22; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFDB6 : 8; + unsigned short RFDB7 : 8; +#else + unsigned short RFDB7 : 8; + unsigned short RFDB6 : 8; +#endif + } BIT; + } RFDF30; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC23; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFID : 16; +#else + unsigned short RFID : 16; +#endif + } BIT; + } RFIDL1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC24; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFID : 13; + unsigned short : 1; + unsigned short RFRTR : 1; + unsigned short RFIDE : 1; +#else + unsigned short RFIDE : 1; + unsigned short RFRTR : 1; + unsigned short : 1; + unsigned short RFID : 13; +#endif + } BIT; + } RFIDH1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC25; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFTS : 16; +#else + unsigned short RFTS : 16; +#endif + } BIT; + } RFTS1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC26; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFPTR : 12; + unsigned short RFDLC : 4; +#else + unsigned short RFDLC : 4; + unsigned short RFPTR : 12; +#endif + } BIT; + } RFPTR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC27; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFDB0 : 8; + unsigned short RFDB1 : 8; +#else + unsigned short RFDB1 : 8; + unsigned short RFDB0 : 8; +#endif + } BIT; + } RFDF01; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC28; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFDB2 : 8; + unsigned short RFDB3 : 8; +#else + unsigned short RFDB3 : 8; + unsigned short RFDB2 : 8; +#endif + } BIT; + } RFDF11; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC29; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFDB4 : 8; + unsigned short RFDB5 : 8; +#else + unsigned short RFDB5 : 8; + unsigned short RFDB4 : 8; +#endif + } BIT; + } RFDF21; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC30; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFDB6 : 8; + unsigned short RFDB7 : 8; +#else + unsigned short RFDB7 : 8; + unsigned short RFDB6 : 8; +#endif + } BIT; + } RFDF31; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC31; + }; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC32; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC33; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC34; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC35; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC36; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC37; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC38; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC39; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC40; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC41; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC42; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC43; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC44; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC45; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC46; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC47; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC48; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC49; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC50; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC51; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC52; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC53; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC54; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC55; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC56; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC57; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC58; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC59; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC60; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC61; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC62; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC63; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC64; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC65; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC66; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC67; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC68; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC69; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC70; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC71; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC72; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC73; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC74; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC75; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC76; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC77; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC78; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC79; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC80; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC81; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC82; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC83; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC84; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC85; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC86; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC87; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC88; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC89; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC90; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC91; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC92; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC93; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC94; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC95; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC96; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC97; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC98; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC99; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC100; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC101; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC102; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC103; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC104; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC105; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC106; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC107; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC108; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC109; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC110; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC111; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC112; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC113; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC114; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC115; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC116; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC117; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC118; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC119; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC120; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC121; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC122; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC123; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC124; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC125; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC126; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC127; +}; + +struct st_rscan0 { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short BRP : 10; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short BRP : 10; +#endif + } BIT; + } CFGL; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TSEG1 : 4; + unsigned short TSEG2 : 3; + unsigned short : 1; + unsigned short SJW : 2; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short SJW : 2; + unsigned short : 1; + unsigned short TSEG2 : 3; + unsigned short TSEG1 : 4; +#endif + } BIT; + } CFGH; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CHMDC : 2; + unsigned short CSLPR : 1; + unsigned short RTBO : 1; + unsigned short : 4; + unsigned short BEIE : 1; + unsigned short EWIE : 1; + unsigned short EPIE : 1; + unsigned short BOEIE : 1; + unsigned short BORIE : 1; + unsigned short OLIE : 1; + unsigned short BLIE : 1; + unsigned short ALIE : 1; +#else + unsigned short ALIE : 1; + unsigned short BLIE : 1; + unsigned short OLIE : 1; + unsigned short BORIE : 1; + unsigned short BOEIE : 1; + unsigned short EPIE : 1; + unsigned short EWIE : 1; + unsigned short BEIE : 1; + unsigned short : 4; + unsigned short RTBO : 1; + unsigned short CSLPR : 1; + unsigned short CHMDC : 2; +#endif + } BIT; + } CTRL; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TAIE : 1; + unsigned short : 4; + unsigned short BOM : 2; + unsigned short ERRD : 1; + unsigned short CTME : 1; + unsigned short CTMS : 2; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short CTMS : 2; + unsigned short CTME : 1; + unsigned short ERRD : 1; + unsigned short BOM : 2; + unsigned short : 4; + unsigned short TAIE : 1; +#endif + } BIT; + } CTRH; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CRSTSTS : 1; + unsigned short CHLTSTS : 1; + unsigned short CSLPSTS : 1; + unsigned short EPSTS : 1; + unsigned short BOSTS : 1; + unsigned short TRMSTS : 1; + unsigned short RECSTS : 1; + unsigned short COMSTS : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short COMSTS : 1; + unsigned short RECSTS : 1; + unsigned short TRMSTS : 1; + unsigned short BOSTS : 1; + unsigned short EPSTS : 1; + unsigned short CSLPSTS : 1; + unsigned short CHLTSTS : 1; + unsigned short CRSTSTS : 1; +#endif + } BIT; + } STSL; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short REC : 8; + unsigned short TEC : 8; +#else + unsigned short TEC : 8; + unsigned short REC : 8; +#endif + } BIT; + } STSH; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short BEF : 1; + unsigned short EWF : 1; + unsigned short EPF : 1; + unsigned short BOEF : 1; + unsigned short BORF : 1; + unsigned short OVLF : 1; + unsigned short BLF : 1; + unsigned short ALF : 1; + unsigned short SERR : 1; + unsigned short FERR : 1; + unsigned short AERR : 1; + unsigned short CERR : 1; + unsigned short B1ERR : 1; + unsigned short B0ERR : 1; + unsigned short ADERR : 1; + unsigned short : 1; +#else + unsigned short : 1; + unsigned short ADERR : 1; + unsigned short B0ERR : 1; + unsigned short B1ERR : 1; + unsigned short CERR : 1; + unsigned short AERR : 1; + unsigned short FERR : 1; + unsigned short SERR : 1; + unsigned short ALF : 1; + unsigned short BLF : 1; + unsigned short OVLF : 1; + unsigned short BORF : 1; + unsigned short BOEF : 1; + unsigned short EPF : 1; + unsigned short EWF : 1; + unsigned short BEF : 1; +#endif + } BIT; + } ERFLL; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CRCREG : 15; + unsigned short : 1; +#else + unsigned short : 1; + unsigned short CRCREG : 15; +#endif + } BIT; + } ERFLH; + char wk0[64]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFE : 1; + unsigned short CFRXIE : 1; + unsigned short CFTXIE : 1; + unsigned short : 5; + unsigned short CFDC : 3; + unsigned short : 1; + unsigned short CFIM : 1; + unsigned short CFIGCV : 3; +#else + unsigned short CFIGCV : 3; + unsigned short CFIM : 1; + unsigned short : 1; + unsigned short CFDC : 3; + unsigned short : 5; + unsigned short CFTXIE : 1; + unsigned short CFRXIE : 1; + unsigned short CFE : 1; +#endif + } BIT; + } CFCCL0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFM : 2; + unsigned short CFITSS : 1; + unsigned short CFITR : 1; + unsigned short CFTML : 2; + unsigned short : 2; + unsigned short CFITT : 8; +#else + unsigned short CFITT : 8; + unsigned short : 2; + unsigned short CFTML : 2; + unsigned short CFITR : 1; + unsigned short CFITSS : 1; + unsigned short CFM : 2; +#endif + } BIT; + } CFCCH0; + char wk1[4]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFEMP : 1; + unsigned short CFFLL : 1; + unsigned short CFMLT : 1; + unsigned short CFRXIF : 1; + unsigned short CFTXIF : 1; + unsigned short : 3; + unsigned short CFMC : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short CFMC : 6; + unsigned short : 3; + unsigned short CFTXIF : 1; + unsigned short CFRXIF : 1; + unsigned short CFMLT : 1; + unsigned short CFFLL : 1; + unsigned short CFEMP : 1; +#endif + } BIT; + } CFSTS0; + char wk2[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFPC : 8; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short CFPC : 8; +#endif + } BIT; + } CFPCTR0; + char wk3[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CF0MLT : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CF0MLT : 1; +#endif + } BIT; + } CFMSTS; + char wk4[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMTR : 1; + unsigned char TMTAR : 1; + unsigned char TMOM : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TMOM : 1; + unsigned char TMTAR : 1; + unsigned char TMTR : 1; +#endif + } BIT; + } TMC0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMTR : 1; + unsigned char TMTAR : 1; + unsigned char TMOM : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TMOM : 1; + unsigned char TMTAR : 1; + unsigned char TMTR : 1; +#endif + } BIT; + } TMC1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMTR : 1; + unsigned char TMTAR : 1; + unsigned char TMOM : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TMOM : 1; + unsigned char TMTAR : 1; + unsigned char TMTR : 1; +#endif + } BIT; + } TMC2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMTR : 1; + unsigned char TMTAR : 1; + unsigned char TMOM : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TMOM : 1; + unsigned char TMTAR : 1; + unsigned char TMTR : 1; +#endif + } BIT; + } TMC3; + char wk5[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMTSTS : 1; + unsigned char TMTRF : 2; + unsigned char TMTRM : 1; + unsigned char TMTARM : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char TMTARM : 1; + unsigned char TMTRM : 1; + unsigned char TMTRF : 2; + unsigned char TMTSTS : 1; +#endif + } BIT; + } TMSTS0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMTSTS : 1; + unsigned char TMTRF : 2; + unsigned char TMTRM : 1; + unsigned char TMTARM : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char TMTARM : 1; + unsigned char TMTRM : 1; + unsigned char TMTRF : 2; + unsigned char TMTSTS : 1; +#endif + } BIT; + } TMSTS1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMTSTS : 1; + unsigned char TMTRF : 2; + unsigned char TMTRM : 1; + unsigned char TMTARM : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char TMTARM : 1; + unsigned char TMTRM : 1; + unsigned char TMTRF : 2; + unsigned char TMTSTS : 1; +#endif + } BIT; + } TMSTS2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMTSTS : 1; + unsigned char TMTRF : 2; + unsigned char TMTRM : 1; + unsigned char TMTARM : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char TMTARM : 1; + unsigned char TMTRM : 1; + unsigned char TMTRF : 2; + unsigned char TMTSTS : 1; +#endif + } BIT; + } TMSTS3; + char wk6[4]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMTRSTS0 : 1; + unsigned short TMTRSTS1 : 1; + unsigned short TMTRSTS2 : 1; + unsigned short TMTRSTS3 : 1; + unsigned short : 12; +#else + unsigned short : 12; + unsigned short TMTRSTS3 : 1; + unsigned short TMTRSTS2 : 1; + unsigned short TMTRSTS1 : 1; + unsigned short TMTRSTS0 : 1; +#endif + } BIT; + } TMTRSTS; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMTCSTS0 : 1; + unsigned short TMTCSTS1 : 1; + unsigned short TMTCSTS2 : 1; + unsigned short TMTCSTS3 : 1; + unsigned short : 12; +#else + unsigned short : 12; + unsigned short TMTCSTS3 : 1; + unsigned short TMTCSTS2 : 1; + unsigned short TMTCSTS1 : 1; + unsigned short TMTCSTS0 : 1; +#endif + } BIT; + } TMTCSTS; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMTASTS0 : 1; + unsigned short TMTASTS1 : 1; + unsigned short TMTASTS2 : 1; + unsigned short TMTASTS3 : 1; + unsigned short : 12; +#else + unsigned short : 12; + unsigned short TMTASTS3 : 1; + unsigned short TMTASTS2 : 1; + unsigned short TMTASTS1 : 1; + unsigned short TMTASTS0 : 1; +#endif + } BIT; + } TMTASTS; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMIE0 : 1; + unsigned short TMIE1 : 1; + unsigned short TMIE2 : 1; + unsigned short TMIE3 : 1; + unsigned short : 12; +#else + unsigned short : 12; + unsigned short TMIE3 : 1; + unsigned short TMIE2 : 1; + unsigned short TMIE1 : 1; + unsigned short TMIE0 : 1; +#endif + } BIT; + } TMIEC; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short THLE : 1; + unsigned short : 7; + unsigned short THLIE : 1; + unsigned short THLIM : 1; + unsigned short THLDTE : 1; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short THLDTE : 1; + unsigned short THLIM : 1; + unsigned short THLIE : 1; + unsigned short : 7; + unsigned short THLE : 1; +#endif + } BIT; + } THLCC0; + char wk7[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short THLEMP : 1; + unsigned short THLFLL : 1; + unsigned short THLELT : 1; + unsigned short THLIF : 1; + unsigned short : 4; + unsigned short THLMC : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short THLMC : 4; + unsigned short : 4; + unsigned short THLIF : 1; + unsigned short THLELT : 1; + unsigned short THLFLL : 1; + unsigned short THLEMP : 1; +#endif + } BIT; + } THLSTS0; + char wk8[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short THLPC : 8; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short THLPC : 8; +#endif + } BIT; + } THLPCTR0; + char wk9[602]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFID : 16; +#else + unsigned short CFID : 16; +#endif + } BIT; + } CFIDL0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFID : 13; + unsigned short THLEN : 1; + unsigned short CFRTR : 1; + unsigned short CFIDE : 1; +#else + unsigned short CFIDE : 1; + unsigned short CFRTR : 1; + unsigned short THLEN : 1; + unsigned short CFID : 13; +#endif + } BIT; + } CFIDH0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFTS : 16; +#else + unsigned short CFTS : 16; +#endif + } BIT; + } CFTS0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFPTR : 12; + unsigned short CFDLC : 4; +#else + unsigned short CFDLC : 4; + unsigned short CFPTR : 12; +#endif + } BIT; + } CFPTR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFDB0 : 8; + unsigned short CFDB1 : 8; +#else + unsigned short CFDB1 : 8; + unsigned short CFDB0 : 8; +#endif + } BIT; + } CFDF00; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFDB2 : 8; + unsigned short CFDB3 : 8; +#else + unsigned short CFDB3 : 8; + unsigned short CFDB2 : 8; +#endif + } BIT; + } CFDF10; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFDB4 : 8; + unsigned short CFDB5 : 8; +#else + unsigned short CFDB5 : 8; + unsigned short CFDB4 : 8; +#endif + } BIT; + } CFDF20; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFDB6 : 8; + unsigned short CFDB7 : 8; +#else + unsigned short CFDB7 : 8; + unsigned short CFDB6 : 8; +#endif + } BIT; + } CFDF30; + char wk10[16]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMID : 16; +#else + unsigned short TMID : 16; +#endif + } BIT; + } TMIDL0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMID : 13; + unsigned short THLEN : 1; + unsigned short TMRTR : 1; + unsigned short TMIDE : 1; +#else + unsigned short TMIDE : 1; + unsigned short TMRTR : 1; + unsigned short THLEN : 1; + unsigned short TMID : 13; +#endif + } BIT; + } TMIDH0; + char wk11[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMPTR : 8; + unsigned short : 4; + unsigned short TMDLC : 4; +#else + unsigned short TMDLC : 4; + unsigned short : 4; + unsigned short TMPTR : 8; +#endif + } BIT; + } TMPTR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB0 : 8; + unsigned short TMDB1 : 8; +#else + unsigned short TMDB1 : 8; + unsigned short TMDB0 : 8; +#endif + } BIT; + } TMDF00; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB2 : 8; + unsigned short TMDB3 : 8; +#else + unsigned short TMDB3 : 8; + unsigned short TMDB2 : 8; +#endif + } BIT; + } TMDF10; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB4 : 8; + unsigned short TMDB5 : 8; +#else + unsigned short TMDB5 : 8; + unsigned short TMDB4 : 8; +#endif + } BIT; + } TMDF20; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB6 : 8; + unsigned short TMDB7 : 8; +#else + unsigned short TMDB7 : 8; + unsigned short TMDB6 : 8; +#endif + } BIT; + } TMDF30; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMID : 16; +#else + unsigned short TMID : 16; +#endif + } BIT; + } TMIDL1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMID : 13; + unsigned short THLEN : 1; + unsigned short TMRTR : 1; + unsigned short TMIDE : 1; +#else + unsigned short TMIDE : 1; + unsigned short TMRTR : 1; + unsigned short THLEN : 1; + unsigned short TMID : 13; +#endif + } BIT; + } TMIDH1; + char wk12[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMPTR : 8; + unsigned short : 4; + unsigned short TMDLC : 4; +#else + unsigned short TMDLC : 4; + unsigned short : 4; + unsigned short TMPTR : 8; +#endif + } BIT; + } TMPTR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB0 : 8; + unsigned short TMDB1 : 8; +#else + unsigned short TMDB1 : 8; + unsigned short TMDB0 : 8; +#endif + } BIT; + } TMDF01; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB2 : 8; + unsigned short TMDB3 : 8; +#else + unsigned short TMDB3 : 8; + unsigned short TMDB2 : 8; +#endif + } BIT; + } TMDF11; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB4 : 8; + unsigned short TMDB5 : 8; +#else + unsigned short TMDB5 : 8; + unsigned short TMDB4 : 8; +#endif + } BIT; + } TMDF21; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB6 : 8; + unsigned short TMDB7 : 8; +#else + unsigned short TMDB7 : 8; + unsigned short TMDB6 : 8; +#endif + } BIT; + } TMDF31; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMID : 16; +#else + unsigned short TMID : 16; +#endif + } BIT; + } TMIDL2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMID : 13; + unsigned short THLEN : 1; + unsigned short TMRTR : 1; + unsigned short TMIDE : 1; +#else + unsigned short TMIDE : 1; + unsigned short TMRTR : 1; + unsigned short THLEN : 1; + unsigned short TMID : 13; +#endif + } BIT; + } TMIDH2; + char wk13[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMPTR : 8; + unsigned short : 4; + unsigned short TMDLC : 4; +#else + unsigned short TMDLC : 4; + unsigned short : 4; + unsigned short TMPTR : 8; +#endif + } BIT; + } TMPTR2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB0 : 8; + unsigned short TMDB1 : 8; +#else + unsigned short TMDB1 : 8; + unsigned short TMDB0 : 8; +#endif + } BIT; + } TMDF02; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB2 : 8; + unsigned short TMDB3 : 8; +#else + unsigned short TMDB3 : 8; + unsigned short TMDB2 : 8; +#endif + } BIT; + } TMDF12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB4 : 8; + unsigned short TMDB5 : 8; +#else + unsigned short TMDB5 : 8; + unsigned short TMDB4 : 8; +#endif + } BIT; + } TMDF22; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB6 : 8; + unsigned short TMDB7 : 8; +#else + unsigned short TMDB7 : 8; + unsigned short TMDB6 : 8; +#endif + } BIT; + } TMDF32; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMID : 16; +#else + unsigned short TMID : 16; +#endif + } BIT; + } TMIDL3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMID : 13; + unsigned short THLEN : 1; + unsigned short TMRTR : 1; + unsigned short TMIDE : 1; +#else + unsigned short TMIDE : 1; + unsigned short TMRTR : 1; + unsigned short THLEN : 1; + unsigned short TMID : 13; +#endif + } BIT; + } TMIDH3; + char wk14[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMPTR : 8; + unsigned short : 4; + unsigned short TMDLC : 4; +#else + unsigned short TMDLC : 4; + unsigned short : 4; + unsigned short TMPTR : 8; +#endif + } BIT; + } TMPTR3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB0 : 8; + unsigned short TMDB1 : 8; +#else + unsigned short TMDB1 : 8; + unsigned short TMDB0 : 8; +#endif + } BIT; + } TMDF03; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB2 : 8; + unsigned short TMDB3 : 8; +#else + unsigned short TMDB3 : 8; + unsigned short TMDB2 : 8; +#endif + } BIT; + } TMDF13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB4 : 8; + unsigned short TMDB5 : 8; +#else + unsigned short TMDB5 : 8; + unsigned short TMDB4 : 8; +#endif + } BIT; + } TMDF23; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB6 : 8; + unsigned short TMDB7 : 8; +#else + unsigned short TMDB7 : 8; + unsigned short TMDB6 : 8; +#endif + } BIT; + } TMDF33; + char wk15[64]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short BT : 2; + unsigned short : 1; + unsigned short BN : 2; + unsigned short : 3; + unsigned short TID : 8; +#else + unsigned short TID : 8; + unsigned short : 3; + unsigned short BN : 2; + unsigned short : 1; + unsigned short BT : 2; +#endif + } BIT; + } THLACC0; +}; + +struct st_cmpb { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB0INI : 1; + unsigned char : 3; + unsigned char CPB1INI : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CPB1INI : 1; + unsigned char : 3; + unsigned char CPB0INI : 1; +#endif + } BIT; + } CPBCNT1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB0WCP : 1; + unsigned char : 3; + unsigned char CPB1WCP : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CPB1WCP : 1; + unsigned char : 3; + unsigned char CPB0WCP : 1; +#endif + } BIT; + } CPBCNT2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char CPB0OUT : 1; + unsigned char : 3; + unsigned char CPB1OUT : 1; +#else + unsigned char CPB1OUT : 1; + unsigned char : 3; + unsigned char CPB0OUT : 1; + unsigned char : 3; +#endif + } BIT; + } CPBFLG; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB0INTEN : 1; + unsigned char CPB0INTEG : 1; + unsigned char CPB0INTPL : 1; + unsigned char : 1; + unsigned char CPB1INTEN : 1; + unsigned char CPB1INTEG : 1; + unsigned char CPB1INTPL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CPB1INTPL : 1; + unsigned char CPB1INTEG : 1; + unsigned char CPB1INTEN : 1; + unsigned char : 1; + unsigned char CPB0INTPL : 1; + unsigned char CPB0INTEG : 1; + unsigned char CPB0INTEN : 1; +#endif + } BIT; + } CPBINT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB0FEN : 1; + unsigned char : 1; + unsigned char CPB0F : 2; + unsigned char CPB1FEN : 1; + unsigned char : 1; + unsigned char CPB1F : 2; +#else + unsigned char CPB1F : 2; + unsigned char : 1; + unsigned char CPB1FEN : 1; + unsigned char CPB0F : 2; + unsigned char : 1; + unsigned char CPB0FEN : 1; +#endif + } BIT; + } CPBF; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPBSPDMD : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CPBSPDMD : 1; +#endif + } BIT; + } CPBMD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB0VRF : 1; + unsigned char : 3; + unsigned char CPB1VRF : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CPB1VRF : 1; + unsigned char : 3; + unsigned char CPB0VRF : 1; +#endif + } BIT; + } CPBREF; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB0OE : 1; + unsigned char CPB0OP : 1; + unsigned char : 2; + unsigned char CPB1OE : 1; + unsigned char CPB1OP : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char CPB1OP : 1; + unsigned char CPB1OE : 1; + unsigned char : 2; + unsigned char CPB0OP : 1; + unsigned char CPB0OE : 1; +#endif + } BIT; + } CPBOCR; + char wk0[24]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB2INI : 1; + unsigned char : 3; + unsigned char CPB3INI : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CPB3INI : 1; + unsigned char : 3; + unsigned char CPB2INI : 1; +#endif + } BIT; + } CPB1CNT1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB2WCP : 1; + unsigned char : 3; + unsigned char CPB3WCP : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CPB3WCP : 1; + unsigned char : 3; + unsigned char CPB2WCP : 1; +#endif + } BIT; + } CPB1CNT2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char CPB2OUT : 1; + unsigned char : 3; + unsigned char CPB3OUT : 1; +#else + unsigned char CPB3OUT : 1; + unsigned char : 3; + unsigned char CPB2OUT : 1; + unsigned char : 3; +#endif + } BIT; + } CPB1FLG; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB2INTEN : 1; + unsigned char CPB2INTEG : 1; + unsigned char CPB2INTPL : 1; + unsigned char : 1; + unsigned char CPB3INTEN : 1; + unsigned char CPB3INTEG : 1; + unsigned char CPB3INTPL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CPB3INTPL : 1; + unsigned char CPB3INTEG : 1; + unsigned char CPB3INTEN : 1; + unsigned char : 1; + unsigned char CPB2INTPL : 1; + unsigned char CPB2INTEG : 1; + unsigned char CPB2INTEN : 1; +#endif + } BIT; + } CPB1INT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB2FEN : 1; + unsigned char : 1; + unsigned char CPB2F : 2; + unsigned char CPB3FEN : 1; + unsigned char : 1; + unsigned char CPB3F : 2; +#else + unsigned char CPB3F : 2; + unsigned char : 1; + unsigned char CPB3FEN : 1; + unsigned char CPB2F : 2; + unsigned char : 1; + unsigned char CPB2FEN : 1; +#endif + } BIT; + } CPB1F; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB1SPDMD : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CPB1SPDMD : 1; +#endif + } BIT; + } CPB1MD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB2VRF : 1; + unsigned char : 3; + unsigned char CPB3VRF : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CPB3VRF : 1; + unsigned char : 3; + unsigned char CPB2VRF : 1; +#endif + } BIT; + } CPB1REF; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB2OE : 1; + unsigned char CPB2OP : 1; + unsigned char : 2; + unsigned char CPB3OE : 1; + unsigned char CPB3OP : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char CPB3OP : 1; + unsigned char CPB3OE : 1; + unsigned char : 2; + unsigned char CPB2OP : 1; + unsigned char CPB2OE : 1; +#endif + } BIT; + } CPB1OCR; +}; + +struct st_cmt { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short STR0 : 1; + unsigned short STR1 : 1; + unsigned short : 14; +#else + unsigned short : 14; + unsigned short STR1 : 1; + unsigned short STR0 : 1; +#endif + } BIT; + } CMSTR0; + char wk0[14]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short STR2 : 1; + unsigned short STR3 : 1; + unsigned short : 14; +#else + unsigned short : 14; + unsigned short STR3 : 1; + unsigned short STR2 : 1; +#endif + } BIT; + } CMSTR1; +}; + +struct st_cmt0 { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CKS : 2; + unsigned short : 4; + unsigned short CMIE : 1; + unsigned short : 9; +#else + unsigned short : 9; + unsigned short CMIE : 1; + unsigned short : 4; + unsigned short CKS : 2; +#endif + } BIT; + } CMCR; + unsigned short CMCNT; + unsigned short CMCOR; +}; + +struct st_crc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char GPS : 2; + unsigned char LMS : 1; + unsigned char : 4; + unsigned char DORCLR : 1; +#else + unsigned char DORCLR : 1; + unsigned char : 4; + unsigned char LMS : 1; + unsigned char GPS : 2; +#endif + } BIT; + } CRCCR; + unsigned char CRCDIR; + unsigned short CRCDOR; +}; + +struct st_ctsu { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUSTRT : 1; + unsigned char CTSUCAP : 1; + unsigned char CTSUSNZ : 1; + unsigned char : 1; + unsigned char CTSUINIT : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CTSUINIT : 1; + unsigned char : 1; + unsigned char CTSUSNZ : 1; + unsigned char CTSUCAP : 1; + unsigned char CTSUSTRT : 1; +#endif + } BIT; + } CTSUCR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUPON : 1; + unsigned char CTSUCSW : 1; + unsigned char CTSUATUNE0 : 1; + unsigned char CTSUATUNE1 : 1; + unsigned char CTSUCLK : 2; + unsigned char CTSUMD : 2; +#else + unsigned char CTSUMD : 2; + unsigned char CTSUCLK : 2; + unsigned char CTSUATUNE1 : 1; + unsigned char CTSUATUNE0 : 1; + unsigned char CTSUCSW : 1; + unsigned char CTSUPON : 1; +#endif + } BIT; + } CTSUCR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUPRRATIO : 4; + unsigned char CTSUPRMODE : 2; + unsigned char CTSUSOFF : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CTSUSOFF : 1; + unsigned char CTSUPRMODE : 2; + unsigned char CTSUPRRATIO : 4; +#endif + } BIT; + } CTSUSDPRS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUSST : 8; +#else + unsigned char CTSUSST : 8; +#endif + } BIT; + } CTSUSST; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUMCH0 : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char CTSUMCH0 : 6; +#endif + } BIT; + } CTSUMCH0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUMCH1 : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char CTSUMCH1 : 6; +#endif + } BIT; + } CTSUMCH1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUCHAC00 : 1; + unsigned char CTSUCHAC01 : 1; + unsigned char CTSUCHAC02 : 1; + unsigned char CTSUCHAC03 : 1; + unsigned char CTSUCHAC04 : 1; + unsigned char CTSUCHAC05 : 1; + unsigned char CTSUCHAC06 : 1; + unsigned char CTSUCHAC07 : 1; +#else + unsigned char CTSUCHAC07 : 1; + unsigned char CTSUCHAC06 : 1; + unsigned char CTSUCHAC05 : 1; + unsigned char CTSUCHAC04 : 1; + unsigned char CTSUCHAC03 : 1; + unsigned char CTSUCHAC02 : 1; + unsigned char CTSUCHAC01 : 1; + unsigned char CTSUCHAC00 : 1; +#endif + } BIT; + } CTSUCHAC0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUCHAC10 : 1; + unsigned char CTSUCHAC11 : 1; + unsigned char CTSUCHAC12 : 1; + unsigned char CTSUCHAC13 : 1; + unsigned char CTSUCHAC14 : 1; + unsigned char CTSUCHAC15 : 1; + unsigned char CTSUCHAC16 : 1; + unsigned char CTSUCHAC17 : 1; +#else + unsigned char CTSUCHAC17 : 1; + unsigned char CTSUCHAC16 : 1; + unsigned char CTSUCHAC15 : 1; + unsigned char CTSUCHAC14 : 1; + unsigned char CTSUCHAC13 : 1; + unsigned char CTSUCHAC12 : 1; + unsigned char CTSUCHAC11 : 1; + unsigned char CTSUCHAC10 : 1; +#endif + } BIT; + } CTSUCHAC1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUCHAC20 : 1; + unsigned char CTSUCHAC21 : 1; + unsigned char CTSUCHAC22 : 1; + unsigned char CTSUCHAC23 : 1; + unsigned char CTSUCHAC24 : 1; + unsigned char CTSUCHAC25 : 1; + unsigned char CTSUCHAC26 : 1; + unsigned char CTSUCHAC27 : 1; +#else + unsigned char CTSUCHAC27 : 1; + unsigned char CTSUCHAC26 : 1; + unsigned char CTSUCHAC25 : 1; + unsigned char CTSUCHAC24 : 1; + unsigned char CTSUCHAC23 : 1; + unsigned char CTSUCHAC22 : 1; + unsigned char CTSUCHAC21 : 1; + unsigned char CTSUCHAC20 : 1; +#endif + } BIT; + } CTSUCHAC2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUCHAC30 : 1; + unsigned char CTSUCHAC31 : 1; + unsigned char CTSUCHAC32 : 1; + unsigned char CTSUCHAC33 : 1; + unsigned char CTSUCHAC34 : 1; + unsigned char CTSUCHAC35 : 1; + unsigned char CTSUCHAC36 : 1; + unsigned char CTSUCHAC37 : 1; +#else + unsigned char CTSUCHAC37 : 1; + unsigned char CTSUCHAC36 : 1; + unsigned char CTSUCHAC35 : 1; + unsigned char CTSUCHAC34 : 1; + unsigned char CTSUCHAC33 : 1; + unsigned char CTSUCHAC32 : 1; + unsigned char CTSUCHAC31 : 1; + unsigned char CTSUCHAC30 : 1; +#endif + } BIT; + } CTSUCHAC3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUCHAC40 : 1; + unsigned char CTSUCHAC41 : 1; + unsigned char CTSUCHAC42 : 1; + unsigned char CTSUCHAC43 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char CTSUCHAC43 : 1; + unsigned char CTSUCHAC42 : 1; + unsigned char CTSUCHAC41 : 1; + unsigned char CTSUCHAC40 : 1; +#endif + } BIT; + } CTSUCHAC4; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUCHTRC00 : 1; + unsigned char CTSUCHTRC01 : 1; + unsigned char CTSUCHTRC02 : 1; + unsigned char CTSUCHTRC03 : 1; + unsigned char CTSUCHTRC04 : 1; + unsigned char CTSUCHTRC05 : 1; + unsigned char CTSUCHTRC06 : 1; + unsigned char CTSUCHTRC07 : 1; +#else + unsigned char CTSUCHTRC07 : 1; + unsigned char CTSUCHTRC06 : 1; + unsigned char CTSUCHTRC05 : 1; + unsigned char CTSUCHTRC04 : 1; + unsigned char CTSUCHTRC03 : 1; + unsigned char CTSUCHTRC02 : 1; + unsigned char CTSUCHTRC01 : 1; + unsigned char CTSUCHTRC00 : 1; +#endif + } BIT; + } CTSUCHTRC0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUCHTRC10 : 1; + unsigned char CTSUCHTRC11 : 1; + unsigned char CTSUCHTRC12 : 1; + unsigned char CTSUCHTRC13 : 1; + unsigned char CTSUCHTRC14 : 1; + unsigned char CTSUCHTRC15 : 1; + unsigned char CTSUCHTRC16 : 1; + unsigned char CTSUCHTRC17 : 1; +#else + unsigned char CTSUCHTRC17 : 1; + unsigned char CTSUCHTRC16 : 1; + unsigned char CTSUCHTRC15 : 1; + unsigned char CTSUCHTRC14 : 1; + unsigned char CTSUCHTRC13 : 1; + unsigned char CTSUCHTRC12 : 1; + unsigned char CTSUCHTRC11 : 1; + unsigned char CTSUCHTRC10 : 1; +#endif + } BIT; + } CTSUCHTRC1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUCHTRC20 : 1; + unsigned char CTSUCHTRC21 : 1; + unsigned char CTSUCHTRC22 : 1; + unsigned char CTSUCHTRC23 : 1; + unsigned char CTSUCHTRC24 : 1; + unsigned char CTSUCHTRC25 : 1; + unsigned char CTSUCHTRC26 : 1; + unsigned char CTSUCHTRC27 : 1; +#else + unsigned char CTSUCHTRC27 : 1; + unsigned char CTSUCHTRC26 : 1; + unsigned char CTSUCHTRC25 : 1; + unsigned char CTSUCHTRC24 : 1; + unsigned char CTSUCHTRC23 : 1; + unsigned char CTSUCHTRC22 : 1; + unsigned char CTSUCHTRC21 : 1; + unsigned char CTSUCHTRC20 : 1; +#endif + } BIT; + } CTSUCHTRC2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUCHTRC30 : 1; + unsigned char CTSUCHTRC31 : 1; + unsigned char CTSUCHTRC32 : 1; + unsigned char CTSUCHTRC33 : 1; + unsigned char CTSUCHTRC34 : 1; + unsigned char CTSUCHTRC35 : 1; + unsigned char CTSUCHTRC36 : 1; + unsigned char CTSUCHTRC37 : 1; +#else + unsigned char CTSUCHTRC37 : 1; + unsigned char CTSUCHTRC36 : 1; + unsigned char CTSUCHTRC35 : 1; + unsigned char CTSUCHTRC34 : 1; + unsigned char CTSUCHTRC33 : 1; + unsigned char CTSUCHTRC32 : 1; + unsigned char CTSUCHTRC31 : 1; + unsigned char CTSUCHTRC30 : 1; +#endif + } BIT; + } CTSUCHTRC3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUCHTRC40 : 1; + unsigned char CTSUCHTRC41 : 1; + unsigned char CTSUCHTRC42 : 1; + unsigned char CTSUCHTRC43 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char CTSUCHTRC43 : 1; + unsigned char CTSUCHTRC42 : 1; + unsigned char CTSUCHTRC41 : 1; + unsigned char CTSUCHTRC40 : 1; +#endif + } BIT; + } CTSUCHTRC4; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUSSMOD : 2; + unsigned char : 2; + unsigned char CTSUSSCNT : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char CTSUSSCNT : 2; + unsigned char : 2; + unsigned char CTSUSSMOD : 2; +#endif + } BIT; + } CTSUDCLKC; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUSTC : 3; + unsigned char : 1; + unsigned char CTSUDTSR : 1; + unsigned char CTSUSOVF : 1; + unsigned char CTSUROVF : 1; + unsigned char CTSUPS : 1; +#else + unsigned char CTSUPS : 1; + unsigned char CTSUROVF : 1; + unsigned char CTSUSOVF : 1; + unsigned char CTSUDTSR : 1; + unsigned char : 1; + unsigned char CTSUSTC : 3; +#endif + } BIT; + } CTSUST; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short CTSUSSDIV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short CTSUSSDIV : 4; + unsigned short : 8; +#endif + } BIT; + } CTSUSSC; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CTSUSO : 10; + unsigned short CTSUSNUM : 6; +#else + unsigned short CTSUSNUM : 6; + unsigned short CTSUSO : 10; +#endif + } BIT; + } CTSUSO0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CTSURICOA : 8; + unsigned short CTSUSDPA : 5; + unsigned short CTSUICOG : 2; + unsigned short : 1; +#else + unsigned short : 1; + unsigned short CTSUICOG : 2; + unsigned short CTSUSDPA : 5; + unsigned short CTSURICOA : 8; +#endif + } BIT; + } CTSUSO1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CTSUSC : 16; +#else + unsigned short CTSUSC : 16; +#endif + } BIT; + } CTSUSC; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CTSURC : 16; +#else + unsigned short CTSURC : 16; +#endif + } BIT; + } CTSURC; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 15; + unsigned short CTSUICOMP : 1; +#else + unsigned short CTSUICOMP : 1; + unsigned short : 15; +#endif + } BIT; + } CTSUERRS; +}; + +struct st_da { + unsigned short DADR0; + unsigned short DADR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char DAOE0 : 1; + unsigned char DAOE1 : 1; +#else + unsigned char DAOE1 : 1; + unsigned char DAOE0 : 1; + unsigned char : 6; +#endif + } BIT; + } DACR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char DPSEL : 1; +#else + unsigned char DPSEL : 1; + unsigned char : 7; +#endif + } BIT; + } DADPR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char DAADST : 1; +#else + unsigned char DAADST : 1; + unsigned char : 7; +#endif + } BIT; + } DAADSCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char REF : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char REF : 3; +#endif + } BIT; + } DAVREFCR; +}; + +struct st_dmac { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DMST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DMST : 1; +#endif + } BIT; + } DMAST; +}; + +struct st_dmac0 { + void *DMSAR; + void *DMDAR; + unsigned long DMCRA; + unsigned short DMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DCTG : 2; + unsigned short : 6; + unsigned short SZ : 2; + unsigned short : 2; + unsigned short DTS : 2; + unsigned short MD : 2; +#else + unsigned short MD : 2; + unsigned short DTS : 2; + unsigned short : 2; + unsigned short SZ : 2; + unsigned short : 6; + unsigned short DCTG : 2; +#endif + } BIT; + } DMTMD; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DARIE : 1; + unsigned char SARIE : 1; + unsigned char RPTIE : 1; + unsigned char ESIE : 1; + unsigned char DTIE : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char DTIE : 1; + unsigned char ESIE : 1; + unsigned char RPTIE : 1; + unsigned char SARIE : 1; + unsigned char DARIE : 1; +#endif + } BIT; + } DMINT; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DARA : 5; + unsigned short : 1; + unsigned short DM : 2; + unsigned short SARA : 5; + unsigned short : 1; + unsigned short SM : 2; +#else + unsigned short SM : 2; + unsigned short : 1; + unsigned short SARA : 5; + unsigned short DM : 2; + unsigned short : 1; + unsigned short DARA : 5; +#endif + } BIT; + } DMAMD; + char wk2[2]; + unsigned long DMOFR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTE : 1; +#endif + } BIT; + } DMCNT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SWREQ : 1; + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; + unsigned char SWREQ : 1; +#endif + } BIT; + } DMREQ; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ESIF : 1; + unsigned char : 3; + unsigned char DTIF : 1; + unsigned char : 2; + unsigned char ACT : 1; +#else + unsigned char ACT : 1; + unsigned char : 2; + unsigned char DTIF : 1; + unsigned char : 3; + unsigned char ESIF : 1; +#endif + } BIT; + } DMSTS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DISEL : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DISEL : 1; +#endif + } BIT; + } DMCSL; +}; + +struct st_dmac1 { + void *DMSAR; + void *DMDAR; + unsigned long DMCRA; + unsigned short DMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DCTG : 2; + unsigned short : 6; + unsigned short SZ : 2; + unsigned short : 2; + unsigned short DTS : 2; + unsigned short MD : 2; +#else + unsigned short MD : 2; + unsigned short DTS : 2; + unsigned short : 2; + unsigned short SZ : 2; + unsigned short : 6; + unsigned short DCTG : 2; +#endif + } BIT; + } DMTMD; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DARIE : 1; + unsigned char SARIE : 1; + unsigned char RPTIE : 1; + unsigned char ESIE : 1; + unsigned char DTIE : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char DTIE : 1; + unsigned char ESIE : 1; + unsigned char RPTIE : 1; + unsigned char SARIE : 1; + unsigned char DARIE : 1; +#endif + } BIT; + } DMINT; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DARA : 5; + unsigned short : 1; + unsigned short DM : 2; + unsigned short SARA : 5; + unsigned short : 1; + unsigned short SM : 2; +#else + unsigned short SM : 2; + unsigned short : 1; + unsigned short SARA : 5; + unsigned short DM : 2; + unsigned short : 1; + unsigned short DARA : 5; +#endif + } BIT; + } DMAMD; + char wk2[6]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTE : 1; +#endif + } BIT; + } DMCNT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SWREQ : 1; + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; + unsigned char SWREQ : 1; +#endif + } BIT; + } DMREQ; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ESIF : 1; + unsigned char : 3; + unsigned char DTIF : 1; + unsigned char : 2; + unsigned char ACT : 1; +#else + unsigned char ACT : 1; + unsigned char : 2; + unsigned char DTIF : 1; + unsigned char : 3; + unsigned char ESIF : 1; +#endif + } BIT; + } DMSTS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DISEL : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DISEL : 1; +#endif + } BIT; + } DMCSL; +}; + +struct st_doc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OMS : 2; + unsigned char DCSEL : 1; + unsigned char : 1; + unsigned char DOPCIE : 1; + unsigned char DOPCF : 1; + unsigned char DOPCFCL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char DOPCFCL : 1; + unsigned char DOPCF : 1; + unsigned char DOPCIE : 1; + unsigned char : 1; + unsigned char DCSEL : 1; + unsigned char OMS : 2; +#endif + } BIT; + } DOCR; + char wk0[1]; + unsigned short DODIR; + unsigned short DODSR; +}; + +struct st_dtc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char RRS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char RRS : 1; + unsigned char : 4; +#endif + } BIT; + } DTCCR; + char wk0[3]; + void *DTCVBR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SHORT : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SHORT : 1; +#endif + } BIT; + } DTCADMOD; + char wk1[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTCST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTCST : 1; +#endif + } BIT; + } DTCST; + char wk2[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short VECN : 8; + unsigned short : 7; + unsigned short ACT : 1; +#else + unsigned short ACT : 1; + unsigned short : 7; + unsigned short VECN : 8; +#endif + } BIT; + } DTCSTS; +}; + +struct st_elc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ELCON : 1; +#else + unsigned char ELCON : 1; + unsigned char : 7; +#endif + } BIT; + } ELCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR[30]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char MTU1MD : 2; + unsigned char MTU2MD : 2; + unsigned char MTU3MD : 2; +#else + unsigned char MTU3MD : 2; + unsigned char MTU2MD : 2; + unsigned char MTU1MD : 2; + unsigned char : 2; +#endif + } BIT; + } ELOPA; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MTU4MD : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char MTU4MD : 2; +#endif + } BIT; + } ELOPB; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char CMT1MD : 2; + unsigned char LPTMD : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char LPTMD : 2; + unsigned char CMT1MD : 2; + unsigned char : 2; +#endif + } BIT; + } ELOPC; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMR0MD : 2; + unsigned char : 2; + unsigned char TMR2MD : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char TMR2MD : 2; + unsigned char : 2; + unsigned char TMR0MD : 2; +#endif + } BIT; + } ELOPD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PGR0 : 1; + unsigned char PGR1 : 1; + unsigned char PGR2 : 1; + unsigned char PGR3 : 1; + unsigned char PGR4 : 1; + unsigned char PGR5 : 1; + unsigned char PGR6 : 1; + unsigned char PGR7 : 1; +#else + unsigned char PGR7 : 1; + unsigned char PGR6 : 1; + unsigned char PGR5 : 1; + unsigned char PGR4 : 1; + unsigned char PGR3 : 1; + unsigned char PGR2 : 1; + unsigned char PGR1 : 1; + unsigned char PGR0 : 1; +#endif + } BIT; + } PGR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PGR0 : 1; + unsigned char PGR1 : 1; + unsigned char PGR2 : 1; + unsigned char PGR3 : 1; + unsigned char PGR4 : 1; + unsigned char PGR5 : 1; + unsigned char PGR6 : 1; + unsigned char PGR7 : 1; +#else + unsigned char PGR7 : 1; + unsigned char PGR6 : 1; + unsigned char PGR5 : 1; + unsigned char PGR4 : 1; + unsigned char PGR3 : 1; + unsigned char PGR2 : 1; + unsigned char PGR1 : 1; + unsigned char PGR0 : 1; +#endif + } BIT; + } PGR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PGCI : 2; + unsigned char PGCOVE : 1; + unsigned char : 1; + unsigned char PGCO : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PGCO : 3; + unsigned char : 1; + unsigned char PGCOVE : 1; + unsigned char PGCI : 2; +#endif + } BIT; + } PGC1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PGCI : 2; + unsigned char PGCOVE : 1; + unsigned char : 1; + unsigned char PGCO : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PGCO : 3; + unsigned char : 1; + unsigned char PGCOVE : 1; + unsigned char PGCI : 2; +#endif + } BIT; + } PGC2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PDBF0 : 1; + unsigned char PDBF1 : 1; + unsigned char PDBF2 : 1; + unsigned char PDBF3 : 1; + unsigned char PDBF4 : 1; + unsigned char PDBF5 : 1; + unsigned char PDBF6 : 1; + unsigned char PDBF7 : 1; +#else + unsigned char PDBF7 : 1; + unsigned char PDBF6 : 1; + unsigned char PDBF5 : 1; + unsigned char PDBF4 : 1; + unsigned char PDBF3 : 1; + unsigned char PDBF2 : 1; + unsigned char PDBF1 : 1; + unsigned char PDBF0 : 1; +#endif + } BIT; + } PDBF1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PDBF0 : 1; + unsigned char PDBF1 : 1; + unsigned char PDBF2 : 1; + unsigned char PDBF3 : 1; + unsigned char PDBF4 : 1; + unsigned char PDBF5 : 1; + unsigned char PDBF6 : 1; + unsigned char PDBF7 : 1; +#else + unsigned char PDBF7 : 1; + unsigned char PDBF6 : 1; + unsigned char PDBF5 : 1; + unsigned char PDBF4 : 1; + unsigned char PDBF3 : 1; + unsigned char PDBF2 : 1; + unsigned char PDBF1 : 1; + unsigned char PDBF0 : 1; +#endif + } BIT; + } PDBF2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSB : 3; + unsigned char PSP : 2; + unsigned char PSM : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSM : 2; + unsigned char PSP : 2; + unsigned char PSB : 3; +#endif + } BIT; + } PEL0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSB : 3; + unsigned char PSP : 2; + unsigned char PSM : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSM : 2; + unsigned char PSP : 2; + unsigned char PSB : 3; +#endif + } BIT; + } PEL1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSB : 3; + unsigned char PSP : 2; + unsigned char PSM : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSM : 2; + unsigned char PSP : 2; + unsigned char PSB : 3; +#endif + } BIT; + } PEL2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSB : 3; + unsigned char PSP : 2; + unsigned char PSM : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSM : 2; + unsigned char PSP : 2; + unsigned char PSB : 3; +#endif + } BIT; + } PEL3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEG : 1; + unsigned char : 5; + unsigned char WE : 1; + unsigned char WI : 1; +#else + unsigned char WI : 1; + unsigned char WE : 1; + unsigned char : 5; + unsigned char SEG : 1; +#endif + } BIT; + } ELSEGR; +}; + +struct st_flash { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DFLEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DFLEN : 1; +#endif + } BIT; + } DFLCTL; + char wk0[111]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char FMS0 : 1; + unsigned char : 1; + unsigned char RPDIS : 1; + unsigned char FMS1 : 1; + unsigned char : 1; + unsigned char LVPE : 1; + unsigned char FMS2 : 1; +#else + unsigned char FMS2 : 1; + unsigned char LVPE : 1; + unsigned char : 1; + unsigned char FMS1 : 1; + unsigned char RPDIS : 1; + unsigned char : 1; + unsigned char FMS0 : 1; + unsigned char : 1; +#endif + } BIT; + } FPMCR; + char wk1[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char EXS : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char EXS : 1; +#endif + } BIT; + } FASR; + char wk2[3]; + unsigned short FSARL; + char wk3[6]; + unsigned short FSARH; + char wk4[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMD : 4; + unsigned char : 2; + unsigned char STOP : 1; + unsigned char OPST : 1; +#else + unsigned char OPST : 1; + unsigned char STOP : 1; + unsigned char : 2; + unsigned char CMD : 4; +#endif + } BIT; + } FCR; + char wk5[3]; + unsigned short FEARL; + char wk6[6]; + unsigned short FEARH; + char wk7[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FRESET : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char FRESET : 1; +#endif + } BIT; + } FRESETR; + char wk8[7]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char FRDY : 1; + unsigned char EXRDY : 1; +#else + unsigned char EXRDY : 1; + unsigned char FRDY : 1; + unsigned char : 6; +#endif + } BIT; + } FSTATR1; + char wk9[3]; + unsigned short FWB0; + char wk10[6]; + unsigned short FWB1; + char wk11[6]; + unsigned short FWB2; + char wk12[2]; + unsigned short FWB3; + char wk13[58]; + unsigned char FPR; + char wk14[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PERR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char PERR : 1; +#endif + } BIT; + } FPSR; + char wk15[59]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short SASMF : 1; + unsigned short : 7; +#else + unsigned short : 7; + unsigned short SASMF : 1; + unsigned short : 8; +#endif + } BIT; + } FSCMR; + char wk16[6]; + unsigned short FAWSMR; + char wk17[6]; + unsigned short FAWEMR; + char wk18[6]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PCKA : 5; + unsigned char : 1; + unsigned char SAS : 2; +#else + unsigned char SAS : 2; + unsigned char : 1; + unsigned char PCKA : 5; +#endif + } BIT; + } FISR; + char wk19[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMD : 3; + unsigned char : 4; + unsigned char OPST : 1; +#else + unsigned char OPST : 1; + unsigned char : 4; + unsigned char CMD : 3; +#endif + } BIT; + } FEXCR; + char wk20[3]; + unsigned short FEAML; + char wk21[6]; + unsigned short FEAMH; + char wk22[6]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ERERR : 1; + unsigned char PRGERR : 1; + unsigned char : 1; + unsigned char BCERR : 1; + unsigned char ILGLERR : 1; + unsigned char EILGLERR : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char EILGLERR : 1; + unsigned char ILGLERR : 1; + unsigned char BCERR : 1; + unsigned char : 1; + unsigned char PRGERR : 1; + unsigned char ERERR : 1; +#endif + } BIT; + } FSTATR0; + char wk23[15809]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FENTRY0 : 1; + unsigned short : 6; + unsigned short FENTRYD : 1; + unsigned short FEKEY : 8; +#else + unsigned short FEKEY : 8; + unsigned short FENTRYD : 1; + unsigned short : 6; + unsigned short FENTRY0 : 1; +#endif + } BIT; + } FENTRYR; +}; + +struct st_flashconst { + unsigned long UIDR0; + unsigned long UIDR1; + unsigned long UIDR2; + unsigned long UIDR3; +}; + +struct st_icu { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char IR : 1; +#endif + } BIT; + } IR[254]; + char wk0[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTCE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTCE : 1; +#endif + } BIT; + } DTCER[253]; + char wk1[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IEN0 : 1; + unsigned char IEN1 : 1; + unsigned char IEN2 : 1; + unsigned char IEN3 : 1; + unsigned char IEN4 : 1; + unsigned char IEN5 : 1; + unsigned char IEN6 : 1; + unsigned char IEN7 : 1; +#else + unsigned char IEN7 : 1; + unsigned char IEN6 : 1; + unsigned char IEN5 : 1; + unsigned char IEN4 : 1; + unsigned char IEN3 : 1; + unsigned char IEN2 : 1; + unsigned char IEN1 : 1; + unsigned char IEN0 : 1; +#endif + } BIT; + } IER[32]; + char wk2[192]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SWINT : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SWINT : 1; +#endif + } BIT; + } SWINTR; + char wk3[15]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FVCT : 8; + unsigned short : 7; + unsigned short FIEN : 1; +#else + unsigned short FIEN : 1; + unsigned short : 7; + unsigned short FVCT : 8; +#endif + } BIT; + } FIR; + char wk4[14]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IPR : 4; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char IPR : 4; +#endif + } BIT; + } IPR[251]; + char wk5[5]; + unsigned char DMRSR0; + char wk6[3]; + unsigned char DMRSR1; + char wk7[3]; + unsigned char DMRSR2; + char wk8[3]; + unsigned char DMRSR3; + char wk9[243]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char IRQMD : 2; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char IRQMD : 2; + unsigned char : 2; +#endif + } BIT; + } IRQCR[8]; + char wk10[8]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FLTEN0 : 1; + unsigned char FLTEN1 : 1; + unsigned char FLTEN2 : 1; + unsigned char FLTEN3 : 1; + unsigned char FLTEN4 : 1; + unsigned char FLTEN5 : 1; + unsigned char FLTEN6 : 1; + unsigned char FLTEN7 : 1; +#else + unsigned char FLTEN7 : 1; + unsigned char FLTEN6 : 1; + unsigned char FLTEN5 : 1; + unsigned char FLTEN4 : 1; + unsigned char FLTEN3 : 1; + unsigned char FLTEN2 : 1; + unsigned char FLTEN1 : 1; + unsigned char FLTEN0 : 1; +#endif + } BIT; + } IRQFLTE0; + char wk11[3]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FCLKSEL0 : 2; + unsigned short FCLKSEL1 : 2; + unsigned short FCLKSEL2 : 2; + unsigned short FCLKSEL3 : 2; + unsigned short FCLKSEL4 : 2; + unsigned short FCLKSEL5 : 2; + unsigned short FCLKSEL6 : 2; + unsigned short FCLKSEL7 : 2; +#else + unsigned short FCLKSEL7 : 2; + unsigned short FCLKSEL6 : 2; + unsigned short FCLKSEL5 : 2; + unsigned short FCLKSEL4 : 2; + unsigned short FCLKSEL3 : 2; + unsigned short FCLKSEL2 : 2; + unsigned short FCLKSEL1 : 2; + unsigned short FCLKSEL0 : 2; +#endif + } BIT; + } IRQFLTC0; + char wk12[106]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NMIST : 1; + unsigned char OSTST : 1; + unsigned char WDTST : 1; + unsigned char IWDTST : 1; + unsigned char LVD1ST : 1; + unsigned char LVD2ST : 1; + unsigned char VBATST : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char VBATST : 1; + unsigned char LVD2ST : 1; + unsigned char LVD1ST : 1; + unsigned char IWDTST : 1; + unsigned char WDTST : 1; + unsigned char OSTST : 1; + unsigned char NMIST : 1; +#endif + } BIT; + } NMISR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NMIEN : 1; + unsigned char OSTEN : 1; + unsigned char WDTEN : 1; + unsigned char IWDTEN : 1; + unsigned char LVD1EN : 1; + unsigned char LVD2EN : 1; + unsigned char VBATEN : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char VBATEN : 1; + unsigned char LVD2EN : 1; + unsigned char LVD1EN : 1; + unsigned char IWDTEN : 1; + unsigned char WDTEN : 1; + unsigned char OSTEN : 1; + unsigned char NMIEN : 1; +#endif + } BIT; + } NMIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NMICLR : 1; + unsigned char OSTCLR : 1; + unsigned char WDTCLR : 1; + unsigned char IWDTCLR : 1; + unsigned char LVD1CLR : 1; + unsigned char LVD2CLR : 1; + unsigned char VBATCLR : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char VBATCLR : 1; + unsigned char LVD2CLR : 1; + unsigned char LVD1CLR : 1; + unsigned char IWDTCLR : 1; + unsigned char WDTCLR : 1; + unsigned char OSTCLR : 1; + unsigned char NMICLR : 1; +#endif + } BIT; + } NMICLR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char NMIMD : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char NMIMD : 1; + unsigned char : 3; +#endif + } BIT; + } NMICR; + char wk13[12]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFLTEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char NFLTEN : 1; +#endif + } BIT; + } NMIFLTE; + char wk14[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFCLKSEL : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char NFCLKSEL : 2; +#endif + } BIT; + } NMIFLTC; +}; + +struct st_irda { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char IRRXINV : 1; + unsigned char IRTXINV : 1; + unsigned char IRCKS : 3; + unsigned char IRE : 1; +#else + unsigned char IRE : 1; + unsigned char IRCKS : 3; + unsigned char IRTXINV : 1; + unsigned char IRRXINV : 1; + unsigned char : 2; +#endif + } BIT; + } IRCR; +}; + +struct st_iwdt { + unsigned char IWDTRR; + char wk0[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TOPS : 2; + unsigned short : 2; + unsigned short CKS : 4; + unsigned short RPES : 2; + unsigned short : 2; + unsigned short RPSS : 2; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short RPSS : 2; + unsigned short : 2; + unsigned short RPES : 2; + unsigned short CKS : 4; + unsigned short : 2; + unsigned short TOPS : 2; +#endif + } BIT; + } IWDTCR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CNTVAL : 14; + unsigned short UNDFF : 1; + unsigned short REFEF : 1; +#else + unsigned short REFEF : 1; + unsigned short UNDFF : 1; + unsigned short CNTVAL : 14; +#endif + } BIT; + } IWDTSR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char RSTIRQS : 1; +#else + unsigned char RSTIRQS : 1; + unsigned char : 7; +#endif + } BIT; + } IWDTRCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char SLCSTP : 1; +#else + unsigned char SLCSTP : 1; + unsigned char : 7; +#endif + } BIT; + } IWDTCSTPR; +}; + +struct st_lpt { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LPCNTPSSEL : 3; + unsigned char : 1; + unsigned char LPCNTCKSEL : 1; + unsigned char : 1; + unsigned char LPCMRE0 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char LPCMRE0 : 1; + unsigned char : 1; + unsigned char LPCNTCKSEL : 1; + unsigned char : 1; + unsigned char LPCNTPSSEL : 3; +#endif + } BIT; + } LPTCR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LPCNTSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char LPCNTSTP : 1; +#endif + } BIT; + } LPTCR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LPCNTEN : 1; + unsigned char LPCNTRST : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char LPCNTRST : 1; + unsigned char LPCNTEN : 1; +#endif + } BIT; + } LPTCR3; + char wk0[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short LPCNTPRD : 16; +#else + unsigned short LPCNTPRD : 16; +#endif + } BIT; + } LPTPRD; + char wk1[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short LPCMR0 : 16; +#else + unsigned short LPCMR0 : 16; +#endif + } BIT; + } LPCMR0; + char wk2[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 15; + unsigned short LPWKUPEN : 1; +#else + unsigned short LPWKUPEN : 1; + unsigned short : 15; +#endif + } BIT; + } LPWUCR; +}; + +struct st_mpc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CS0E : 1; + unsigned char CS1E : 1; + unsigned char CS2E : 1; + unsigned char CS3E : 1; + unsigned char CS4E : 1; + unsigned char CS5E : 1; + unsigned char CS6E : 1; + unsigned char CS7E : 1; +#else + unsigned char CS7E : 1; + unsigned char CS6E : 1; + unsigned char CS5E : 1; + unsigned char CS4E : 1; + unsigned char CS3E : 1; + unsigned char CS2E : 1; + unsigned char CS1E : 1; + unsigned char CS0E : 1; +#endif + } BIT; + } PFCSE; + char wk0[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char A8E : 1; + unsigned char A9E : 1; + unsigned char A10E : 1; + unsigned char A11E : 1; + unsigned char A12E : 1; + unsigned char A13E : 1; + unsigned char A14E : 1; + unsigned char A15E : 1; +#else + unsigned char A15E : 1; + unsigned char A14E : 1; + unsigned char A13E : 1; + unsigned char A12E : 1; + unsigned char A11E : 1; + unsigned char A10E : 1; + unsigned char A9E : 1; + unsigned char A8E : 1; +#endif + } BIT; + } PFAOE0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char A16E : 1; + unsigned char A17E : 1; + unsigned char A18E : 1; + unsigned char A19E : 1; + unsigned char A20E : 1; + unsigned char A21E : 1; + unsigned char A22E : 1; + unsigned char A23E : 1; +#else + unsigned char A23E : 1; + unsigned char A22E : 1; + unsigned char A21E : 1; + unsigned char A20E : 1; + unsigned char A19E : 1; + unsigned char A18E : 1; + unsigned char A17E : 1; + unsigned char A16E : 1; +#endif + } BIT; + } PFAOE1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADRLE : 1; + unsigned char : 3; + unsigned char DHE : 1; + unsigned char : 1; + unsigned char WR1BC1E : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char WR1BC1E : 1; + unsigned char : 1; + unsigned char DHE : 1; + unsigned char : 3; + unsigned char ADRLE : 1; +#endif + } BIT; + } PFBCR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char WAITS : 2; + unsigned char ALEOE : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char ALEOE : 1; + unsigned char WAITS : 2; +#endif + } BIT; + } PFBCR1; + char wk1[23]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char PFSWE : 1; + unsigned char B0WI : 1; +#else + unsigned char B0WI : 1; + unsigned char PFSWE : 1; + unsigned char : 6; +#endif + } BIT; + } PWPR; + char wk2[35]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 2; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 2; + unsigned char PSEL : 5; +#endif + } BIT; + } P03PFS; + char wk3[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 2; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 2; + unsigned char PSEL : 5; +#endif + } BIT; + } P05PFS; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P07PFS; + char wk5[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P12PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P13PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P14PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P15PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P16PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P17PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P20PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P21PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P22PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P23PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P24PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P25PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 2; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 2; + unsigned char PSEL : 5; +#endif + } BIT; + } P26PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 2; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 2; + unsigned char PSEL : 5; +#endif + } BIT; + } P27PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P30PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P31PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P32PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P33PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P34PFS; + char wk6[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P40PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P41PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P42PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P43PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P44PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P45PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P46PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P47PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P50PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P51PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P52PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P53PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P54PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P55PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P56PFS; + char wk7[33]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PA0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PA1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PA2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PA3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PA4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PA5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PA6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PA7PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PB0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PB1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PB2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PB3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PB4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PB5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PB6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PB7PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC7PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PD0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PD1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PD2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PD3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PD4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PD5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PD6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PD7PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 2; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 2; + unsigned char PSEL : 5; +#endif + } BIT; + } PE0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 2; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 2; + unsigned char PSEL : 5; +#endif + } BIT; + } PE1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PE2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 2; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 2; + unsigned char PSEL : 5; +#endif + } BIT; + } PE3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 2; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 2; + unsigned char PSEL : 5; +#endif + } BIT; + } PE4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PE5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PE6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PE7PFS; + char wk8[16]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PH0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PH1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PH2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PH3PFS; + char wk9[7]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PJ3PFS; +}; + +struct st_mpu { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE3; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE3; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE4; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE4; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE5; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE5; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE6; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE6; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE7; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE7; + char wk0[192]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MPEN : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long MPEN : 1; +#endif + } BIT; + } MPEN; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 1; + unsigned long UBAC : 3; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long UBAC : 3; + unsigned long : 1; +#endif + } BIT; + } MPBAC; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CLR : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long CLR : 1; +#endif + } BIT; + } MPECLR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IMPER : 1; + unsigned long DMPER : 1; + unsigned long DRW : 1; + unsigned long : 29; +#else + unsigned long : 29; + unsigned long DRW : 1; + unsigned long DMPER : 1; + unsigned long IMPER : 1; +#endif + } BIT; + } MPESTS; + char wk1[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DEA : 32; +#else + unsigned long DEA : 32; +#endif + } BIT; + } MPDEA; + char wk2[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SA : 32; +#else + unsigned long SA : 32; +#endif + } BIT; + } MPSA; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short S : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short S : 1; +#endif + } BIT; + } MPOPS; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short INV : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short INV : 1; +#endif + } BIT; + } MPOPI; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 1; + unsigned long UHACI : 3; + unsigned long : 12; + unsigned long HITI : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long HITI : 8; + unsigned long : 12; + unsigned long UHACI : 3; + unsigned long : 1; +#endif + } BIT; + } MHITI; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 1; + unsigned long UHACD : 3; + unsigned long : 12; + unsigned long HITD : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long HITD : 8; + unsigned long : 12; + unsigned long UHACD : 3; + unsigned long : 1; +#endif + } BIT; + } MHITD; +}; + +struct st_mtu { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OE3B : 1; + unsigned char OE4A : 1; + unsigned char OE4B : 1; + unsigned char OE3D : 1; + unsigned char OE4C : 1; + unsigned char OE4D : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char OE4D : 1; + unsigned char OE4C : 1; + unsigned char OE3D : 1; + unsigned char OE4B : 1; + unsigned char OE4A : 1; + unsigned char OE3B : 1; +#endif + } BIT; + } TOER; + char wk0[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char UF : 1; + unsigned char VF : 1; + unsigned char WF : 1; + unsigned char FB : 1; + unsigned char P : 1; + unsigned char N : 1; + unsigned char BDC : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char BDC : 1; + unsigned char N : 1; + unsigned char P : 1; + unsigned char FB : 1; + unsigned char WF : 1; + unsigned char VF : 1; + unsigned char UF : 1; +#endif + } BIT; + } TGCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLSP : 1; + unsigned char OLSN : 1; + unsigned char TOCS : 1; + unsigned char TOCL : 1; + unsigned char : 2; + unsigned char PSYE : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSYE : 1; + unsigned char : 2; + unsigned char TOCL : 1; + unsigned char TOCS : 1; + unsigned char OLSN : 1; + unsigned char OLSP : 1; +#endif + } BIT; + } TOCR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLS1P : 1; + unsigned char OLS1N : 1; + unsigned char OLS2P : 1; + unsigned char OLS2N : 1; + unsigned char OLS3P : 1; + unsigned char OLS3N : 1; + unsigned char BF : 2; +#else + unsigned char BF : 2; + unsigned char OLS3N : 1; + unsigned char OLS3P : 1; + unsigned char OLS2N : 1; + unsigned char OLS2P : 1; + unsigned char OLS1N : 1; + unsigned char OLS1P : 1; +#endif + } BIT; + } TOCR2; + char wk1[4]; + unsigned short TCDR; + unsigned short TDDR; + char wk2[8]; + unsigned short TCNTS; + unsigned short TCBR; + char wk3[12]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char T4VCOR : 3; + unsigned char T4VEN : 1; + unsigned char T3ACOR : 3; + unsigned char T3AEN : 1; +#else + unsigned char T3AEN : 1; + unsigned char T3ACOR : 3; + unsigned char T4VEN : 1; + unsigned char T4VCOR : 3; +#endif + } BIT; + } TITCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char T4VCNT : 3; + unsigned char : 1; + unsigned char T3ACNT : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char T3ACNT : 3; + unsigned char : 1; + unsigned char T4VCNT : 3; +#endif + } BIT; + } TITCNT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BTE : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char BTE : 2; +#endif + } BIT; + } TBTER; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TDER : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TDER : 1; +#endif + } BIT; + } TDER; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLS1P : 1; + unsigned char OLS1N : 1; + unsigned char OLS2P : 1; + unsigned char OLS2N : 1; + unsigned char OLS3P : 1; + unsigned char OLS3N : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char OLS3N : 1; + unsigned char OLS3P : 1; + unsigned char OLS2N : 1; + unsigned char OLS2P : 1; + unsigned char OLS1N : 1; + unsigned char OLS1P : 1; +#endif + } BIT; + } TOLBR; + char wk6[41]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char WRE : 1; + unsigned char : 6; + unsigned char CCE : 1; +#else + unsigned char CCE : 1; + unsigned char : 6; + unsigned char WRE : 1; +#endif + } BIT; + } TWCR; + char wk7[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CST0 : 1; + unsigned char CST1 : 1; + unsigned char CST2 : 1; + unsigned char : 3; + unsigned char CST3 : 1; + unsigned char CST4 : 1; +#else + unsigned char CST4 : 1; + unsigned char CST3 : 1; + unsigned char : 3; + unsigned char CST2 : 1; + unsigned char CST1 : 1; + unsigned char CST0 : 1; +#endif + } BIT; + } TSTR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SYNC0 : 1; + unsigned char SYNC1 : 1; + unsigned char SYNC2 : 1; + unsigned char : 3; + unsigned char SYNC3 : 1; + unsigned char SYNC4 : 1; +#else + unsigned char SYNC4 : 1; + unsigned char SYNC3 : 1; + unsigned char : 3; + unsigned char SYNC2 : 1; + unsigned char SYNC1 : 1; + unsigned char SYNC0 : 1; +#endif + } BIT; + } TSYR; + char wk8[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RWE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char RWE : 1; +#endif + } BIT; + } TRWER; +}; + +struct st_mtu0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk0[111]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char BFE : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char BFE : 1; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; + char wk1[16]; + unsigned short TGRE; + unsigned short TGRF; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEE : 1; + unsigned char TGIEF : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TGIEF : 1; + unsigned char TGIEE : 1; +#endif + } BIT; + } TIER2; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char TTSE : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TTSE : 1; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif + } BIT; + } TBTM; +}; + +struct st_mtu1 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk1[238]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CCLR : 2; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + char wk3[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char I1AE : 1; + unsigned char I1BE : 1; + unsigned char I2AE : 1; + unsigned char I2BE : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char I2BE : 1; + unsigned char I2AE : 1; + unsigned char I1BE : 1; + unsigned char I1AE : 1; +#endif + } BIT; + } TICCR; +}; + +struct st_mtu2 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk0[365]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CCLR : 2; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_mtu3 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + char wk2[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + char wk3[7]; + unsigned short TCNT; + char wk4[6]; + unsigned short TGRA; + unsigned short TGRB; + char wk5[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk6[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + char wk7[11]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char TTSE : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TTSE : 1; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif + } BIT; + } TBTM; + char wk8[90]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; +}; + +struct st_mtu4 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + char wk2[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + char wk3[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 1; + unsigned char TTGE2 : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char TTGE2 : 1; + unsigned char : 1; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + char wk4[8]; + unsigned short TCNT; + char wk5[8]; + unsigned short TGRA; + unsigned short TGRB; + char wk6[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk7[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + char wk8[11]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char TTSE : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TTSE : 1; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif + } BIT; + } TBTM; + char wk9[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ITB4VE : 1; + unsigned short ITB3AE : 1; + unsigned short ITA4VE : 1; + unsigned short ITA3AE : 1; + unsigned short DT4BE : 1; + unsigned short UT4BE : 1; + unsigned short DT4AE : 1; + unsigned short UT4AE : 1; + unsigned short : 6; + unsigned short BF : 2; +#else + unsigned short BF : 2; + unsigned short : 6; + unsigned short UT4AE : 1; + unsigned short DT4AE : 1; + unsigned short UT4BE : 1; + unsigned short DT4BE : 1; + unsigned short ITA3AE : 1; + unsigned short ITA4VE : 1; + unsigned short ITB3AE : 1; + unsigned short ITB4VE : 1; +#endif + } BIT; + } TADCR; + char wk10[2]; + unsigned short TADCORA; + unsigned short TADCORB; + unsigned short TADCOBRA; + unsigned short TADCOBRB; + char wk11[72]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; +}; + +struct st_mtu5 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFUEN : 1; + unsigned char NFVEN : 1; + unsigned char NFWEN : 1; + unsigned char : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 1; + unsigned char NFWEN : 1; + unsigned char NFVEN : 1; + unsigned char NFUEN : 1; +#endif + } BIT; + } NFCR; + char wk1[490]; + unsigned short TCNTU; + unsigned short TGRU; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TPSC : 2; +#endif + } BIT; + } TCRU; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char IOC : 5; +#endif + } BIT; + } TIORU; + char wk3[9]; + unsigned short TCNTV; + unsigned short TGRV; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TPSC : 2; +#endif + } BIT; + } TCRV; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char IOC : 5; +#endif + } BIT; + } TIORV; + char wk5[9]; + unsigned short TCNTW; + unsigned short TGRW; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TPSC : 2; +#endif + } BIT; + } TCRW; + char wk6[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char IOC : 5; +#endif + } BIT; + } TIORW; + char wk7[11]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIE5W : 1; + unsigned char TGIE5V : 1; + unsigned char TGIE5U : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TGIE5U : 1; + unsigned char TGIE5V : 1; + unsigned char TGIE5W : 1; +#endif + } BIT; + } TIER; + char wk8[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CSTW5 : 1; + unsigned char CSTV5 : 1; + unsigned char CSTU5 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char CSTU5 : 1; + unsigned char CSTV5 : 1; + unsigned char CSTW5 : 1; +#endif + } BIT; + } TSTR; + char wk9[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPCLR5W : 1; + unsigned char CMPCLR5V : 1; + unsigned char CMPCLR5U : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char CMPCLR5U : 1; + unsigned char CMPCLR5V : 1; + unsigned char CMPCLR5W : 1; +#endif + } BIT; + } TCNTCMPCLR; +}; + +struct st_poe { + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short POE0M : 2; + unsigned short POE1M : 2; + unsigned short POE2M : 2; + unsigned short POE3M : 2; + unsigned short PIE1 : 1; + unsigned short : 3; + unsigned short POE0F : 1; + unsigned short POE1F : 1; + unsigned short POE2F : 1; + unsigned short POE3F : 1; +#else + unsigned short POE3F : 1; + unsigned short POE2F : 1; + unsigned short POE1F : 1; + unsigned short POE0F : 1; + unsigned short : 3; + unsigned short PIE1 : 1; + unsigned short POE3M : 2; + unsigned short POE2M : 2; + unsigned short POE1M : 2; + unsigned short POE0M : 2; +#endif + } BIT; + } ICSR1; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short OIE1 : 1; + unsigned short OCE1 : 1; + unsigned short : 5; + unsigned short OSF1 : 1; +#else + unsigned short OSF1 : 1; + unsigned short : 5; + unsigned short OCE1 : 1; + unsigned short OIE1 : 1; + unsigned short : 8; +#endif + } BIT; + } OCSR1; + char wk0[4]; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short POE8M : 2; + unsigned short : 6; + unsigned short PIE2 : 1; + unsigned short POE8E : 1; + unsigned short : 2; + unsigned short POE8F : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short POE8F : 1; + unsigned short : 2; + unsigned short POE8E : 1; + unsigned short PIE2 : 1; + unsigned short : 6; + unsigned short POE8M : 2; +#endif + } BIT; + } ICSR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CH34HIZ : 1; + unsigned char CH0HIZ : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char CH0HIZ : 1; + unsigned char CH34HIZ : 1; +#endif + } BIT; + } SPOER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PE0ZE : 1; + unsigned char PE1ZE : 1; + unsigned char PE2ZE : 1; + unsigned char PE3ZE : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char PE3ZE : 1; + unsigned char PE2ZE : 1; + unsigned char PE1ZE : 1; + unsigned char PE0ZE : 1; +#endif + } BIT; + } POECR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char P3CZEA : 1; + unsigned char P2CZEA : 1; + unsigned char P1CZEA : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char P1CZEA : 1; + unsigned char P2CZEA : 1; + unsigned char P3CZEA : 1; + unsigned char : 4; +#endif + } BIT; + } POECR2; + char wk1[1]; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 1; + unsigned short : 8; + unsigned short OSTSTE : 1; + unsigned short : 2; + unsigned short OSTSTF : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short OSTSTF : 1; + unsigned short : 2; + unsigned short OSTSTE : 1; + unsigned short : 8; + unsigned short : 1; +#endif + } BIT; + } ICSR3; +}; + +struct st_port { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL0 : 1; + unsigned char PSEL1 : 1; + unsigned char : 1; + unsigned char PSEL3 : 1; + unsigned char : 1; + unsigned char PSEL5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL5 : 1; + unsigned char : 1; + unsigned char PSEL3 : 1; + unsigned char : 1; + unsigned char PSEL1 : 1; + unsigned char PSEL0 : 1; +#endif + } BIT; + } PSRB; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char PSEL6 : 1; + unsigned char PSEL7 : 1; +#else + unsigned char PSEL7 : 1; + unsigned char PSEL6 : 1; + unsigned char : 6; +#endif + } BIT; + } PSRA; +}; + +struct st_port0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PMR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PCR; +}; + +struct st_port1 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } PMR; + char wk3[32]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 4; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[61]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } DSCR; +}; + +struct st_port2 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[33]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[60]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_port3 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[34]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 3; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 3; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[59]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_port4 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; +}; + +struct st_port5 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[36]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[57]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_porta { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[41]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[52]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_portb { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[42]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[51]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_portc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[43]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[50]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_portd { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk4[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_porte { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[45]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[48]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_porth { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk4[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_portj { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PMR; + char wk3[49]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } ODR0; + char wk4[45]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } DSCR; +}; + +struct st_riic { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SDAI : 1; + unsigned char SCLI : 1; + unsigned char SDAO : 1; + unsigned char SCLO : 1; + unsigned char SOWP : 1; + unsigned char CLO : 1; + unsigned char IICRST : 1; + unsigned char ICE : 1; +#else + unsigned char ICE : 1; + unsigned char IICRST : 1; + unsigned char CLO : 1; + unsigned char SOWP : 1; + unsigned char SCLO : 1; + unsigned char SDAO : 1; + unsigned char SCLI : 1; + unsigned char SDAI : 1; +#endif + } BIT; + } ICCR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char ST : 1; + unsigned char RS : 1; + unsigned char SP : 1; + unsigned char : 1; + unsigned char TRS : 1; + unsigned char MST : 1; + unsigned char BBSY : 1; +#else + unsigned char BBSY : 1; + unsigned char MST : 1; + unsigned char TRS : 1; + unsigned char : 1; + unsigned char SP : 1; + unsigned char RS : 1; + unsigned char ST : 1; + unsigned char : 1; +#endif + } BIT; + } ICCR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BC : 3; + unsigned char BCWP : 1; + unsigned char CKS : 3; + unsigned char MTWP : 1; +#else + unsigned char MTWP : 1; + unsigned char CKS : 3; + unsigned char BCWP : 1; + unsigned char BC : 3; +#endif + } BIT; + } ICMR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOS : 1; + unsigned char TMOL : 1; + unsigned char TMOH : 1; + unsigned char : 1; + unsigned char SDDL : 3; + unsigned char DLCS : 1; +#else + unsigned char DLCS : 1; + unsigned char SDDL : 3; + unsigned char : 1; + unsigned char TMOH : 1; + unsigned char TMOL : 1; + unsigned char TMOS : 1; +#endif + } BIT; + } ICMR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NF : 2; + unsigned char ACKBR : 1; + unsigned char ACKBT : 1; + unsigned char ACKWP : 1; + unsigned char RDRFS : 1; + unsigned char WAIT : 1; + unsigned char SMBS : 1; +#else + unsigned char SMBS : 1; + unsigned char WAIT : 1; + unsigned char RDRFS : 1; + unsigned char ACKWP : 1; + unsigned char ACKBT : 1; + unsigned char ACKBR : 1; + unsigned char NF : 2; +#endif + } BIT; + } ICMR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOE : 1; + unsigned char MALE : 1; + unsigned char NALE : 1; + unsigned char SALE : 1; + unsigned char NACKE : 1; + unsigned char NFE : 1; + unsigned char SCLE : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SCLE : 1; + unsigned char NFE : 1; + unsigned char NACKE : 1; + unsigned char SALE : 1; + unsigned char NALE : 1; + unsigned char MALE : 1; + unsigned char TMOE : 1; +#endif + } BIT; + } ICFER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SAR0E : 1; + unsigned char SAR1E : 1; + unsigned char SAR2E : 1; + unsigned char GCAE : 1; + unsigned char : 1; + unsigned char DIDE : 1; + unsigned char : 1; + unsigned char HOAE : 1; +#else + unsigned char HOAE : 1; + unsigned char : 1; + unsigned char DIDE : 1; + unsigned char : 1; + unsigned char GCAE : 1; + unsigned char SAR2E : 1; + unsigned char SAR1E : 1; + unsigned char SAR0E : 1; +#endif + } BIT; + } ICSER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOIE : 1; + unsigned char ALIE : 1; + unsigned char STIE : 1; + unsigned char SPIE : 1; + unsigned char NAKIE : 1; + unsigned char RIE : 1; + unsigned char TEIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char TEIE : 1; + unsigned char RIE : 1; + unsigned char NAKIE : 1; + unsigned char SPIE : 1; + unsigned char STIE : 1; + unsigned char ALIE : 1; + unsigned char TMOIE : 1; +#endif + } BIT; + } ICIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char AAS0 : 1; + unsigned char AAS1 : 1; + unsigned char AAS2 : 1; + unsigned char GCA : 1; + unsigned char : 1; + unsigned char DID : 1; + unsigned char : 1; + unsigned char HOA : 1; +#else + unsigned char HOA : 1; + unsigned char : 1; + unsigned char DID : 1; + unsigned char : 1; + unsigned char GCA : 1; + unsigned char AAS2 : 1; + unsigned char AAS1 : 1; + unsigned char AAS0 : 1; +#endif + } BIT; + } ICSR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOF : 1; + unsigned char AL : 1; + unsigned char START : 1; + unsigned char STOP : 1; + unsigned char NACKF : 1; + unsigned char RDRF : 1; + unsigned char TEND : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char TEND : 1; + unsigned char RDRF : 1; + unsigned char NACKF : 1; + unsigned char STOP : 1; + unsigned char START : 1; + unsigned char AL : 1; + unsigned char TMOF : 1; +#endif + } BIT; + } ICSR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SVA0 : 1; + unsigned char SVA : 7; +#else + unsigned char SVA : 7; + unsigned char SVA0 : 1; +#endif + } BIT; + } SARL0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FS : 1; + unsigned char SVA : 2; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SVA : 2; + unsigned char FS : 1; +#endif + } BIT; + } SARU0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SVA0 : 1; + unsigned char SVA : 7; +#else + unsigned char SVA : 7; + unsigned char SVA0 : 1; +#endif + } BIT; + } SARL1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FS : 1; + unsigned char SVA : 2; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SVA : 2; + unsigned char FS : 1; +#endif + } BIT; + } SARU1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SVA0 : 1; + unsigned char SVA : 7; +#else + unsigned char SVA : 7; + unsigned char SVA0 : 1; +#endif + } BIT; + } SARL2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FS : 1; + unsigned char SVA : 2; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SVA : 2; + unsigned char FS : 1; +#endif + } BIT; + } SARU2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BRL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char BRL : 5; +#endif + } BIT; + } ICBRL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BRH : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char BRH : 5; +#endif + } BIT; + } ICBRH; + unsigned char ICDRT; + unsigned char ICDRR; +}; + +struct st_rspi { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPMS : 1; + unsigned char TXMD : 1; + unsigned char MODFEN : 1; + unsigned char MSTR : 1; + unsigned char SPEIE : 1; + unsigned char SPTIE : 1; + unsigned char SPE : 1; + unsigned char SPRIE : 1; +#else + unsigned char SPRIE : 1; + unsigned char SPE : 1; + unsigned char SPTIE : 1; + unsigned char SPEIE : 1; + unsigned char MSTR : 1; + unsigned char MODFEN : 1; + unsigned char TXMD : 1; + unsigned char SPMS : 1; +#endif + } BIT; + } SPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSL0P : 1; + unsigned char SSL1P : 1; + unsigned char SSL2P : 1; + unsigned char SSL3P : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char SSL3P : 1; + unsigned char SSL2P : 1; + unsigned char SSL1P : 1; + unsigned char SSL0P : 1; +#endif + } BIT; + } SSLP; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPLP : 1; + unsigned char SPLP2 : 1; + unsigned char : 2; + unsigned char MOIFV : 1; + unsigned char MOIFE : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char MOIFE : 1; + unsigned char MOIFV : 1; + unsigned char : 2; + unsigned char SPLP2 : 1; + unsigned char SPLP : 1; +#endif + } BIT; + } SPPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OVRF : 1; + unsigned char IDLNF : 1; + unsigned char MODF : 1; + unsigned char PERF : 1; + unsigned char : 1; + unsigned char SPTEF : 1; + unsigned char : 1; + unsigned char SPRF : 1; +#else + unsigned char SPRF : 1; + unsigned char : 1; + unsigned char SPTEF : 1; + unsigned char : 1; + unsigned char PERF : 1; + unsigned char MODF : 1; + unsigned char IDLNF : 1; + unsigned char OVRF : 1; +#endif + } BIT; + } SPSR; + union { + unsigned long LONG; + struct { + unsigned short H; + } WORD; + } SPDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPSLN : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SPSLN : 3; +#endif + } BIT; + } SPSCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPCP : 3; + unsigned char : 1; + unsigned char SPECM : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SPECM : 3; + unsigned char : 1; + unsigned char SPCP : 3; +#endif + } BIT; + } SPSSR; + unsigned char SPBR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPFC : 2; + unsigned char : 2; + unsigned char SPRDTD : 1; + unsigned char SPLW : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char SPLW : 1; + unsigned char SPRDTD : 1; + unsigned char : 2; + unsigned char SPFC : 2; +#endif + } BIT; + } SPDCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SCKDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SCKDL : 3; +#endif + } BIT; + } SPCKD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLNDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SLNDL : 3; +#endif + } BIT; + } SSLND; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPNDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SPNDL : 3; +#endif + } BIT; + } SPND; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPPE : 1; + unsigned char SPOE : 1; + unsigned char SPIIE : 1; + unsigned char PTE : 1; + unsigned char SCKASE : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char SCKASE : 1; + unsigned char PTE : 1; + unsigned char SPIIE : 1; + unsigned char SPOE : 1; + unsigned char SPPE : 1; +#endif + } BIT; + } SPCR2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD6; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD7; +}; + +struct st_rtc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char F64HZ : 1; + unsigned char F32HZ : 1; + unsigned char F16HZ : 1; + unsigned char F8HZ : 1; + unsigned char F4HZ : 1; + unsigned char F2HZ : 1; + unsigned char F1HZ : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char F1HZ : 1; + unsigned char F2HZ : 1; + unsigned char F4HZ : 1; + unsigned char F8HZ : 1; + unsigned char F16HZ : 1; + unsigned char F32HZ : 1; + unsigned char F64HZ : 1; +#endif + } BIT; + } R64CNT; + char wk0[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif + } BIT; + } RSECCNT; + unsigned char BCNT0; + }; + char wk1[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif + } BIT; + } RMINCNT; + unsigned char BCNT1; + }; + char wk2[1]; + union { + unsigned char BCNT2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif + } BIT; + } RHRCNT; + }; + char wk3[1]; + union { + unsigned char BCNT3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DAYW : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char DAYW : 3; +#endif + } BIT; + } RWKCNT; + }; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif + } BIT; + } RDAYCNT; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif + } BIT; + } RMONCNT; + char wk6[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short YR1 : 4; + unsigned short YR10 : 4; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short YR10 : 4; + unsigned short YR1 : 4; +#endif + } BIT; + } RYRCNT; + union { + unsigned char BCNT0AR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif + } BIT; + } RSECAR; + }; + char wk7[1]; + union { + unsigned char BCNT1AR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif + } BIT; + } RMINAR; + }; + char wk8[1]; + union { + unsigned char BCNT2AR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif + } BIT; + } RHRAR; + }; + char wk9[1]; + union { + unsigned char BCNT3AR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DAYW : 3; + unsigned char : 4; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 4; + unsigned char DAYW : 3; +#endif + } BIT; + } RWKAR; + }; + char wk10[1]; + union { + unsigned char BCNT0AER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 1; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 1; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif + } BIT; + } RDAYAR; + }; + char wk11[1]; + union { + unsigned char BCNT1AER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 2; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 2; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif + } BIT; + } RMONAR; + }; + char wk12[1]; + union { + unsigned short BCNT2AER; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short YR1 : 4; + unsigned short YR10 : 4; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short YR10 : 4; + unsigned short YR1 : 4; +#endif + } BIT; + } RYRAR; + }; + union { + unsigned char BCNT3AER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 7; +#endif + } BIT; + } RYRAREN; + }; + char wk13[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char AIE : 1; + unsigned char CIE : 1; + unsigned char PIE : 1; + unsigned char RTCOS : 1; + unsigned char PES : 4; +#else + unsigned char PES : 4; + unsigned char RTCOS : 1; + unsigned char PIE : 1; + unsigned char CIE : 1; + unsigned char AIE : 1; +#endif + } BIT; + } RCR1; + char wk14[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char START : 1; + unsigned char RESET : 1; + unsigned char ADJ30 : 1; + unsigned char RTCOE : 1; + unsigned char AADJE : 1; + unsigned char AADJP : 1; + unsigned char HR24 : 1; + unsigned char CNTMD : 1; +#else + unsigned char CNTMD : 1; + unsigned char HR24 : 1; + unsigned char AADJP : 1; + unsigned char AADJE : 1; + unsigned char RTCOE : 1; + unsigned char ADJ30 : 1; + unsigned char RESET : 1; + unsigned char START : 1; +#endif + } BIT; + } RCR2; + char wk15[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RTCEN : 1; + unsigned char RTCDV : 3; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char RTCDV : 3; + unsigned char RTCEN : 1; +#endif + } BIT; + } RCR3; + char wk16[7]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADJ : 6; + unsigned char PMADJ : 2; +#else + unsigned char PMADJ : 2; + unsigned char ADJ : 6; +#endif + } BIT; + } RADJ; + char wk17[17]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCCT : 2; + unsigned char TCST : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCEN : 1; +#else + unsigned char TCEN : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCST : 1; + unsigned char TCCT : 2; +#endif + } BIT; + } RTCCR0; + char wk18[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCCT : 2; + unsigned char TCST : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCEN : 1; +#else + unsigned char TCEN : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCST : 1; + unsigned char TCCT : 2; +#endif + } BIT; + } RTCCR1; + char wk19[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCCT : 2; + unsigned char TCST : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCEN : 1; +#else + unsigned char TCEN : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCST : 1; + unsigned char TCCT : 2; +#endif + } BIT; + } RTCCR2; + char wk20[13]; + union { + unsigned char BCNT0CP0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif + } BIT; + } RSECCP0; + }; + char wk21[1]; + union { + unsigned char BCNT1CP0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif + } BIT; + } RMINCP0; + }; + char wk22[1]; + union { + unsigned char BCNT2CP0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif + } BIT; + } RHRCP0; + }; + char wk23[3]; + union { + unsigned char BCNT3CP0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif + } BIT; + } RDAYCP0; + }; + char wk24[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif + } BIT; + } RMONCP0; + char wk25[5]; + union { + unsigned char BCNT0CP1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif + } BIT; + } RSECCP1; + }; + char wk26[1]; + union { + unsigned char BCNT1CP1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif + } BIT; + } RMINCP1; + }; + char wk27[1]; + union { + unsigned char BCNT2CP1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif + } BIT; + } RHRCP1; + }; + char wk28[3]; + union { + unsigned char BCNT3CP1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif + } BIT; + } RDAYCP1; + }; + char wk29[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif + } BIT; + } RMONCP1; + char wk30[5]; + union { + unsigned char BCNT0CP2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif + } BIT; + } RSECCP2; + }; + char wk31[1]; + union { + unsigned char BCNT1CP2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif + } BIT; + } RMINCP2; + }; + char wk32[1]; + union { + unsigned char BCNT2CP2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif + } BIT; + } RHRCP2; + }; + char wk33[3]; + union { + unsigned char BCNT3CP2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif + } BIT; + } RDAYCP2; + }; + char wk34[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif + } BIT; + } RMONCP2; +}; + +struct st_s12ad { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DBLANS : 5; + unsigned short : 1; + unsigned short GBADIE : 1; + unsigned short DBLE : 1; + unsigned short EXTRG : 1; + unsigned short TRGE : 1; + unsigned short ADHSC : 1; + unsigned short : 1; + unsigned short ADIE : 1; + unsigned short ADCS : 2; + unsigned short ADST : 1; +#else + unsigned short ADST : 1; + unsigned short ADCS : 2; + unsigned short ADIE : 1; + unsigned short : 1; + unsigned short ADHSC : 1; + unsigned short TRGE : 1; + unsigned short EXTRG : 1; + unsigned short DBLE : 1; + unsigned short GBADIE : 1; + unsigned short : 1; + unsigned short DBLANS : 5; +#endif + } BIT; + } ADCSR; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSA000 : 1; + unsigned short ANSA001 : 1; + unsigned short ANSA002 : 1; + unsigned short ANSA003 : 1; + unsigned short ANSA004 : 1; + unsigned short ANSA005 : 1; + unsigned short ANSA006 : 1; + unsigned short ANSA007 : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short ANSA007 : 1; + unsigned short ANSA006 : 1; + unsigned short ANSA005 : 1; + unsigned short ANSA004 : 1; + unsigned short ANSA003 : 1; + unsigned short ANSA002 : 1; + unsigned short ANSA001 : 1; + unsigned short ANSA000 : 1; +#endif + } BIT; + } ADANSA0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSA100 : 1; + unsigned short ANSA101 : 1; + unsigned short ANSA102 : 1; + unsigned short ANSA103 : 1; + unsigned short ANSA104 : 1; + unsigned short ANSA105 : 1; + unsigned short ANSA106 : 1; + unsigned short ANSA107 : 1; + unsigned short ANSA108 : 1; + unsigned short ANSA109 : 1; + unsigned short ANSA110 : 1; + unsigned short ANSA111 : 1; + unsigned short ANSA112 : 1; + unsigned short ANSA113 : 1; + unsigned short ANSA114 : 1; + unsigned short ANSA115 : 1; +#else + unsigned short ANSA115 : 1; + unsigned short ANSA114 : 1; + unsigned short ANSA113 : 1; + unsigned short ANSA112 : 1; + unsigned short ANSA111 : 1; + unsigned short ANSA110 : 1; + unsigned short ANSA109 : 1; + unsigned short ANSA108 : 1; + unsigned short ANSA107 : 1; + unsigned short ANSA106 : 1; + unsigned short ANSA105 : 1; + unsigned short ANSA104 : 1; + unsigned short ANSA103 : 1; + unsigned short ANSA102 : 1; + unsigned short ANSA101 : 1; + unsigned short ANSA100 : 1; +#endif + } BIT; + } ADANSA1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ADS000 : 1; + unsigned short ADS001 : 1; + unsigned short ADS002 : 1; + unsigned short ADS003 : 1; + unsigned short ADS004 : 1; + unsigned short ADS005 : 1; + unsigned short ADS006 : 1; + unsigned short ADS007 : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short ADS007 : 1; + unsigned short ADS006 : 1; + unsigned short ADS005 : 1; + unsigned short ADS004 : 1; + unsigned short ADS003 : 1; + unsigned short ADS002 : 1; + unsigned short ADS001 : 1; + unsigned short ADS000 : 1; +#endif + } BIT; + } ADADS0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ADS100 : 1; + unsigned short ADS101 : 1; + unsigned short ADS102 : 1; + unsigned short ADS103 : 1; + unsigned short ADS104 : 1; + unsigned short ADS105 : 1; + unsigned short ADS106 : 1; + unsigned short ADS107 : 1; + unsigned short ADS108 : 1; + unsigned short ADS109 : 1; + unsigned short ADS110 : 1; + unsigned short ADS111 : 1; + unsigned short ADS112 : 1; + unsigned short ADS113 : 1; + unsigned short ADS114 : 1; + unsigned short ADS115 : 1; +#else + unsigned short ADS115 : 1; + unsigned short ADS114 : 1; + unsigned short ADS113 : 1; + unsigned short ADS112 : 1; + unsigned short ADS111 : 1; + unsigned short ADS110 : 1; + unsigned short ADS109 : 1; + unsigned short ADS108 : 1; + unsigned short ADS107 : 1; + unsigned short ADS106 : 1; + unsigned short ADS105 : 1; + unsigned short ADS104 : 1; + unsigned short ADS103 : 1; + unsigned short ADS102 : 1; + unsigned short ADS101 : 1; + unsigned short ADS100 : 1; +#endif + } BIT; + } ADADS1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADC : 3; + unsigned char : 4; + unsigned char AVEE : 1; +#else + unsigned char AVEE : 1; + unsigned char : 4; + unsigned char ADC : 3; +#endif + } BIT; + } ADADC; + char wk1[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 5; + unsigned short ACE : 1; + unsigned short : 2; + unsigned short DIAGVAL : 2; + unsigned short DIAGLD : 1; + unsigned short DIAGM : 1; + unsigned short : 3; + unsigned short ADRFMT : 1; +#else + unsigned short ADRFMT : 1; + unsigned short : 3; + unsigned short DIAGM : 1; + unsigned short DIAGLD : 1; + unsigned short DIAGVAL : 2; + unsigned short : 2; + unsigned short ACE : 1; + unsigned short : 5; +#endif + } BIT; + } ADCER; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TRSB : 6; + unsigned short : 2; + unsigned short TRSA : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short TRSA : 6; + unsigned short : 2; + unsigned short TRSB : 6; +#endif + } BIT; + } ADSTRGR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TSSAD : 1; + unsigned short OCSAD : 1; + unsigned short : 6; + unsigned short TSSA : 1; + unsigned short OCSA : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short OCSA : 1; + unsigned short TSSA : 1; + unsigned short : 6; + unsigned short OCSAD : 1; + unsigned short TSSAD : 1; +#endif + } BIT; + } ADEXICR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSB000 : 1; + unsigned short ANSB001 : 1; + unsigned short ANSB002 : 1; + unsigned short ANSB003 : 1; + unsigned short ANSB004 : 1; + unsigned short ANSB005 : 1; + unsigned short ANSB006 : 1; + unsigned short ANSB007 : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short ANSB007 : 1; + unsigned short ANSB006 : 1; + unsigned short ANSB005 : 1; + unsigned short ANSB004 : 1; + unsigned short ANSB003 : 1; + unsigned short ANSB002 : 1; + unsigned short ANSB001 : 1; + unsigned short ANSB000 : 1; +#endif + } BIT; + } ADANSB0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSB100 : 1; + unsigned short ANSB101 : 1; + unsigned short ANSB102 : 1; + unsigned short ANSB103 : 1; + unsigned short ANSB104 : 1; + unsigned short ANSB105 : 1; + unsigned short ANSB106 : 1; + unsigned short ANSB107 : 1; + unsigned short ANSB108 : 1; + unsigned short ANSB109 : 1; + unsigned short ANSB110 : 1; + unsigned short ANSB111 : 1; + unsigned short ANSB112 : 1; + unsigned short ANSB113 : 1; + unsigned short ANSB114 : 1; + unsigned short ANSB115 : 1; +#else + unsigned short ANSB115 : 1; + unsigned short ANSB114 : 1; + unsigned short ANSB113 : 1; + unsigned short ANSB112 : 1; + unsigned short ANSB111 : 1; + unsigned short ANSB110 : 1; + unsigned short ANSB109 : 1; + unsigned short ANSB108 : 1; + unsigned short ANSB107 : 1; + unsigned short ANSB106 : 1; + unsigned short ANSB105 : 1; + unsigned short ANSB104 : 1; + unsigned short ANSB103 : 1; + unsigned short ANSB102 : 1; + unsigned short ANSB101 : 1; + unsigned short ANSB100 : 1; +#endif + } BIT; + } ADANSB1; + unsigned short ADDBLDR; + unsigned short ADTSDR; + unsigned short ADOCDR; + union { + unsigned short WORD; + union { + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short AD : 12; + unsigned short : 2; + unsigned short DIAGST : 2; +#else + unsigned short DIAGST : 2; + unsigned short : 2; + unsigned short AD : 12; +#endif + } RIGHT; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DIAGST : 2; + unsigned short : 2; + unsigned short AD : 12; +#else + unsigned short AD : 12; + unsigned short : 2; + unsigned short DIAGST : 2; +#endif + } LEFT; + } BIT; + } ADRD; + unsigned short ADDR0; + unsigned short ADDR1; + unsigned short ADDR2; + unsigned short ADDR3; + unsigned short ADDR4; + unsigned short ADDR5; + unsigned short ADDR6; + unsigned short ADDR7; + char wk2[16]; + unsigned short ADDR16; + unsigned short ADDR17; + unsigned short ADDR18; + unsigned short ADDR19; + unsigned short ADDR20; + unsigned short ADDR21; + unsigned short ADDR22; + unsigned short ADDR23; + unsigned short ADDR24; + unsigned short ADDR25; + unsigned short ADDR26; + unsigned short ADDR27; + unsigned short ADDR28; + unsigned short ADDR29; + unsigned short ADDR30; + unsigned short ADDR31; + char wk4[26]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADNDIS : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char ADNDIS : 5; +#endif + } BIT; + } ADDISCR; + char wk5[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELCC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char ELCC : 2; +#endif + } BIT; + } ADELCCR; + char wk6[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PGS : 1; + unsigned short GBRSCN : 1; + unsigned short : 13; + unsigned short GBRP : 1; +#else + unsigned short GBRP : 1; + unsigned short : 13; + unsigned short GBRSCN : 1; + unsigned short PGS : 1; +#endif + } BIT; + } ADGSPCR; + char wk7[8]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HVSEL : 2; + unsigned char : 2; + unsigned char LVSEL : 1; + unsigned char : 2; + unsigned char ADSLP : 1; +#else + unsigned char ADSLP : 1; + unsigned char : 2; + unsigned char LVSEL : 1; + unsigned char : 2; + unsigned char HVSEL : 2; +#endif + } BIT; + } ADHVREFCNT; + char wk8[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MONCOMB : 1; + unsigned char : 3; + unsigned char MONCMPA : 1; + unsigned char MONCMPB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char MONCMPB : 1; + unsigned char MONCMPA : 1; + unsigned char : 3; + unsigned char MONCOMB : 1; +#endif + } BIT; + } ADWINMON; + char wk9[3]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPAB : 2; + unsigned short : 7; + unsigned short CMPBE : 1; + unsigned short : 1; + unsigned short CMPAE : 1; + unsigned short : 2; + unsigned short WCMPE : 1; + unsigned short : 1; +#else + unsigned short : 1; + unsigned short WCMPE : 1; + unsigned short : 2; + unsigned short CMPAE : 1; + unsigned short : 1; + unsigned short CMPBE : 1; + unsigned short : 7; + unsigned short CMPAB : 2; +#endif + } BIT; + } ADCMPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPTSA : 1; + unsigned char CMPOCA : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char CMPOCA : 1; + unsigned char CMPTSA : 1; +#endif + } BIT; + } ADCMPANSER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPLTSA : 1; + unsigned char CMPLOCA : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char CMPLOCA : 1; + unsigned char CMPLTSA : 1; +#endif + } BIT; + } ADCMPLER; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPCHA000 : 1; + unsigned short CMPCHA001 : 1; + unsigned short CMPCHA002 : 1; + unsigned short CMPCHA003 : 1; + unsigned short CMPCHA004 : 1; + unsigned short CMPCHA005 : 1; + unsigned short CMPCHA006 : 1; + unsigned short CMPCHA007 : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short CMPCHA007 : 1; + unsigned short CMPCHA006 : 1; + unsigned short CMPCHA005 : 1; + unsigned short CMPCHA004 : 1; + unsigned short CMPCHA003 : 1; + unsigned short CMPCHA002 : 1; + unsigned short CMPCHA001 : 1; + unsigned short CMPCHA000 : 1; +#endif + } BIT; + } ADCMPANSR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPCHA100 : 1; + unsigned short CMPCHA101 : 1; + unsigned short CMPCHA102 : 1; + unsigned short CMPCHA103 : 1; + unsigned short CMPCHA104 : 1; + unsigned short CMPCHA105 : 1; + unsigned short CMPCHA106 : 1; + unsigned short CMPCHA107 : 1; + unsigned short CMPCHA108 : 1; + unsigned short CMPCHA109 : 1; + unsigned short CMPCHA110 : 1; + unsigned short CMPCHA111 : 1; + unsigned short CMPCHA112 : 1; + unsigned short CMPCHA113 : 1; + unsigned short CMPCHA114 : 1; + unsigned short CMPCHA115 : 1; +#else + unsigned short CMPCHA115 : 1; + unsigned short CMPCHA114 : 1; + unsigned short CMPCHA113 : 1; + unsigned short CMPCHA112 : 1; + unsigned short CMPCHA111 : 1; + unsigned short CMPCHA110 : 1; + unsigned short CMPCHA109 : 1; + unsigned short CMPCHA108 : 1; + unsigned short CMPCHA107 : 1; + unsigned short CMPCHA106 : 1; + unsigned short CMPCHA105 : 1; + unsigned short CMPCHA104 : 1; + unsigned short CMPCHA103 : 1; + unsigned short CMPCHA102 : 1; + unsigned short CMPCHA101 : 1; + unsigned short CMPCHA100 : 1; +#endif + } BIT; + } ADCMPANSR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPLCHA000 : 1; + unsigned short CMPLCHA001 : 1; + unsigned short CMPLCHA002 : 1; + unsigned short CMPLCHA003 : 1; + unsigned short CMPLCHA004 : 1; + unsigned short CMPLCHA005 : 1; + unsigned short CMPLCHA006 : 1; + unsigned short CMPLCHA007 : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short CMPLCHA007 : 1; + unsigned short CMPLCHA006 : 1; + unsigned short CMPLCHA005 : 1; + unsigned short CMPLCHA004 : 1; + unsigned short CMPLCHA003 : 1; + unsigned short CMPLCHA002 : 1; + unsigned short CMPLCHA001 : 1; + unsigned short CMPLCHA000 : 1; +#endif + } BIT; + } ADCMPLR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPLCHA100 : 1; + unsigned short CMPLCHA101 : 1; + unsigned short CMPLCHA102 : 1; + unsigned short CMPLCHA103 : 1; + unsigned short CMPLCHA104 : 1; + unsigned short CMPLCHA105 : 1; + unsigned short CMPLCHA106 : 1; + unsigned short CMPLCHA107 : 1; + unsigned short CMPLCHA108 : 1; + unsigned short CMPLCHA109 : 1; + unsigned short CMPLCHA110 : 1; + unsigned short CMPLCHA111 : 1; + unsigned short CMPLCHA112 : 1; + unsigned short CMPLCHA113 : 1; + unsigned short CMPLCHA114 : 1; + unsigned short CMPLCHA115 : 1; +#else + unsigned short CMPLCHA115 : 1; + unsigned short CMPLCHA114 : 1; + unsigned short CMPLCHA113 : 1; + unsigned short CMPLCHA112 : 1; + unsigned short CMPLCHA111 : 1; + unsigned short CMPLCHA110 : 1; + unsigned short CMPLCHA109 : 1; + unsigned short CMPLCHA108 : 1; + unsigned short CMPLCHA107 : 1; + unsigned short CMPLCHA106 : 1; + unsigned short CMPLCHA105 : 1; + unsigned short CMPLCHA104 : 1; + unsigned short CMPLCHA103 : 1; + unsigned short CMPLCHA102 : 1; + unsigned short CMPLCHA101 : 1; + unsigned short CMPLCHA100 : 1; +#endif + } BIT; + } ADCMPLR1; + unsigned short ADCMPDR0; + unsigned short ADCMPDR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPSTCHA000 : 1; + unsigned short CMPSTCHA001 : 1; + unsigned short CMPSTCHA002 : 1; + unsigned short CMPSTCHA003 : 1; + unsigned short CMPSTCHA004 : 1; + unsigned short CMPSTCHA005 : 1; + unsigned short CMPSTCHA006 : 1; + unsigned short CMPSTCHA007 : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short CMPSTCHA007 : 1; + unsigned short CMPSTCHA006 : 1; + unsigned short CMPSTCHA005 : 1; + unsigned short CMPSTCHA004 : 1; + unsigned short CMPSTCHA003 : 1; + unsigned short CMPSTCHA002 : 1; + unsigned short CMPSTCHA001 : 1; + unsigned short CMPSTCHA000 : 1; +#endif + } BIT; + } ADCMPSR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPSTCHA100 : 1; + unsigned short CMPSTCHA101 : 1; + unsigned short CMPSTCHA102 : 1; + unsigned short CMPSTCHA103 : 1; + unsigned short CMPSTCHA104 : 1; + unsigned short CMPSTCHA105 : 1; + unsigned short CMPSTCHA106 : 1; + unsigned short CMPSTCHA107 : 1; + unsigned short CMPSTCHA108 : 1; + unsigned short CMPSTCHA109 : 1; + unsigned short CMPSTCHA110 : 1; + unsigned short CMPSTCHA111 : 1; + unsigned short CMPSTCHA112 : 1; + unsigned short CMPSTCHA113 : 1; + unsigned short CMPSTCHA114 : 1; + unsigned short CMPSTCHA115 : 1; +#else + unsigned short CMPSTCHA115 : 1; + unsigned short CMPSTCHA114 : 1; + unsigned short CMPSTCHA113 : 1; + unsigned short CMPSTCHA112 : 1; + unsigned short CMPSTCHA111 : 1; + unsigned short CMPSTCHA110 : 1; + unsigned short CMPSTCHA109 : 1; + unsigned short CMPSTCHA108 : 1; + unsigned short CMPSTCHA107 : 1; + unsigned short CMPSTCHA106 : 1; + unsigned short CMPSTCHA105 : 1; + unsigned short CMPSTCHA104 : 1; + unsigned short CMPSTCHA103 : 1; + unsigned short CMPSTCHA102 : 1; + unsigned short CMPSTCHA101 : 1; + unsigned short CMPSTCHA100 : 1; +#endif + } BIT; + } ADCMPSR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPSTTSA : 1; + unsigned char CMPSTOCA : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char CMPSTOCA : 1; + unsigned char CMPSTTSA : 1; +#endif + } BIT; + } ADCMPSER; + char wk10[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPCHB : 6; + unsigned char : 1; + unsigned char CMPLB : 1; +#else + unsigned char CMPLB : 1; + unsigned char : 1; + unsigned char CMPCHB : 6; +#endif + } BIT; + } ADCMPBNSR; + char wk11[1]; + unsigned short ADWINLLB; + unsigned short ADWINULB; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPSTB : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CMPSTB : 1; +#endif + } BIT; + } ADCMPBSR; + char wk12[3]; + unsigned short ADBUF0; + unsigned short ADBUF1; + unsigned short ADBUF2; + unsigned short ADBUF3; + unsigned short ADBUF4; + unsigned short ADBUF5; + unsigned short ADBUF6; + unsigned short ADBUF7; + unsigned short ADBUF8; + unsigned short ADBUF9; + unsigned short ADBUF10; + unsigned short ADBUF11; + unsigned short ADBUF12; + unsigned short ADBUF13; + unsigned short ADBUF14; + unsigned short ADBUF15; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BUFEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char BUFEN : 1; +#endif + } BIT; + } ADBUFEN; + char wk13[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BUFPTR : 4; + unsigned char PTROVF : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PTROVF : 1; + unsigned char BUFPTR : 4; +#endif + } BIT; + } ADBUFPTR; + char wk14[10]; + unsigned char ADSSTRL; + unsigned char ADSSTRT; + unsigned char ADSSTRO; + unsigned char ADSSTR0; + unsigned char ADSSTR1; + unsigned char ADSSTR2; + unsigned char ADSSTR3; + unsigned char ADSSTR4; + unsigned char ADSSTR5; + unsigned char ADSSTR6; + unsigned char ADSSTR7; +}; + +struct st_sci0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char MP : 1; + unsigned char STOP : 1; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char CHR : 1; + unsigned char CM : 1; +#else + unsigned char CM : 1; + unsigned char CHR : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char STOP : 1; + unsigned char MP : 1; + unsigned char CKS : 2; +#endif + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char FER : 1; + unsigned char ORER : 1; + unsigned char RDRF : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char RDRF : 1; + unsigned char ORER : 1; + unsigned char FER : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char CHR1 : 1; + unsigned char : 2; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 2; + unsigned char CHR1 : 1; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ACS0 : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ABCS : 1; + unsigned char NFEN : 1; + unsigned char BGDM : 1; + unsigned char RXDESEL : 1; +#else + unsigned char RXDESEL : 1; + unsigned char BGDM : 1; + unsigned char NFEN : 1; + unsigned char ABCS : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ACS0 : 1; +#endif + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFCS : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char NFCS : 3; +#endif + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICM : 1; + unsigned char : 2; + unsigned char IICDL : 5; +#else + unsigned char IICDL : 5; + unsigned char : 2; + unsigned char IICM : 1; +#endif + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICINTM : 1; + unsigned char IICCSC : 1; + unsigned char : 3; + unsigned char IICACKT : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char IICACKT : 1; + unsigned char : 3; + unsigned char IICCSC : 1; + unsigned char IICINTM : 1; +#endif + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICSTAREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICSTIF : 1; + unsigned char IICSDAS : 2; + unsigned char IICSCLS : 2; +#else + unsigned char IICSCLS : 2; + unsigned char IICSDAS : 2; + unsigned char IICSTIF : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTAREQ : 1; +#endif + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICACKR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char IICACKR : 1; +#endif + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSE : 1; + unsigned char CTSE : 1; + unsigned char MSS : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char CKPOL : 1; + unsigned char CKPH : 1; +#else + unsigned char CKPH : 1; + unsigned char CKPOL : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char MSS : 1; + unsigned char CTSE : 1; + unsigned char SSE : 1; +#endif + } BIT; + } SPMR; + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + unsigned char MDDR; +}; + +struct st_sci12 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char MP : 1; + unsigned char STOP : 1; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char CHR : 1; + unsigned char CM : 1; +#else + unsigned char CM : 1; + unsigned char CHR : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char STOP : 1; + unsigned char MP : 1; + unsigned char CKS : 2; +#endif + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char FER : 1; + unsigned char ORER : 1; + unsigned char RDRF : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char RDRF : 1; + unsigned char ORER : 1; + unsigned char FER : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char CHR1 : 1; + unsigned char : 2; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 2; + unsigned char CHR1 : 1; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ACS0 : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ABCS : 1; + unsigned char NFEN : 1; + unsigned char BGDM : 1; + unsigned char RXDESEL : 1; +#else + unsigned char RXDESEL : 1; + unsigned char BGDM : 1; + unsigned char NFEN : 1; + unsigned char ABCS : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ACS0 : 1; +#endif + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFCS : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char NFCS : 3; +#endif + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICM : 1; + unsigned char : 2; + unsigned char IICDL : 5; +#else + unsigned char IICDL : 5; + unsigned char : 2; + unsigned char IICM : 1; +#endif + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICINTM : 1; + unsigned char IICCSC : 1; + unsigned char : 3; + unsigned char IICACKT : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char IICACKT : 1; + unsigned char : 3; + unsigned char IICCSC : 1; + unsigned char IICINTM : 1; +#endif + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICSTAREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICSTIF : 1; + unsigned char IICSDAS : 2; + unsigned char IICSCLS : 2; +#else + unsigned char IICSCLS : 2; + unsigned char IICSDAS : 2; + unsigned char IICSTIF : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTAREQ : 1; +#endif + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICACKR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char IICACKR : 1; +#endif + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSE : 1; + unsigned char CTSE : 1; + unsigned char MSS : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char CKPOL : 1; + unsigned char CKPH : 1; +#else + unsigned char CKPH : 1; + unsigned char CKPOL : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char MSS : 1; + unsigned char CTSE : 1; + unsigned char SSE : 1; +#endif + } BIT; + } SPMR; + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + unsigned char MDDR; + char wk0[13]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ESME : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char ESME : 1; +#endif + } BIT; + } ESMER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char SFSF : 1; + unsigned char RXDSF : 1; + unsigned char BRME : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char BRME : 1; + unsigned char RXDSF : 1; + unsigned char SFSF : 1; + unsigned char : 1; +#endif + } BIT; + } CR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFE : 1; + unsigned char CF0RE : 1; + unsigned char CF1DS : 2; + unsigned char PIBE : 1; + unsigned char PIBS : 3; +#else + unsigned char PIBS : 3; + unsigned char PIBE : 1; + unsigned char CF1DS : 2; + unsigned char CF0RE : 1; + unsigned char BFE : 1; +#endif + } BIT; + } CR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DFCS : 3; + unsigned char : 1; + unsigned char BCCS : 2; + unsigned char RTS : 2; +#else + unsigned char RTS : 2; + unsigned char BCCS : 2; + unsigned char : 1; + unsigned char DFCS : 3; +#endif + } BIT; + } CR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SDST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SDST : 1; +#endif + } BIT; + } CR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TXDXPS : 1; + unsigned char RXDXPS : 1; + unsigned char : 2; + unsigned char SHARPS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char SHARPS : 1; + unsigned char : 2; + unsigned char RXDXPS : 1; + unsigned char TXDXPS : 1; +#endif + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFDIE : 1; + unsigned char CF0MIE : 1; + unsigned char CF1MIE : 1; + unsigned char PIBDIE : 1; + unsigned char BCDIE : 1; + unsigned char AEDIE : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char AEDIE : 1; + unsigned char BCDIE : 1; + unsigned char PIBDIE : 1; + unsigned char CF1MIE : 1; + unsigned char CF0MIE : 1; + unsigned char BFDIE : 1; +#endif + } BIT; + } ICR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFDF : 1; + unsigned char CF0MF : 1; + unsigned char CF1MF : 1; + unsigned char PIBDF : 1; + unsigned char BCDF : 1; + unsigned char AEDF : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char AEDF : 1; + unsigned char BCDF : 1; + unsigned char PIBDF : 1; + unsigned char CF1MF : 1; + unsigned char CF0MF : 1; + unsigned char BFDF : 1; +#endif + } BIT; + } STR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFDCL : 1; + unsigned char CF0MCL : 1; + unsigned char CF1MCL : 1; + unsigned char PIBDCL : 1; + unsigned char BCDCL : 1; + unsigned char AEDCL : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char AEDCL : 1; + unsigned char BCDCL : 1; + unsigned char PIBDCL : 1; + unsigned char CF1MCL : 1; + unsigned char CF0MCL : 1; + unsigned char BFDCL : 1; +#endif + } BIT; + } STCR; + unsigned char CF0DR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CF0CE0 : 1; + unsigned char CF0CE1 : 1; + unsigned char CF0CE2 : 1; + unsigned char CF0CE3 : 1; + unsigned char CF0CE4 : 1; + unsigned char CF0CE5 : 1; + unsigned char CF0CE6 : 1; + unsigned char CF0CE7 : 1; +#else + unsigned char CF0CE7 : 1; + unsigned char CF0CE6 : 1; + unsigned char CF0CE5 : 1; + unsigned char CF0CE4 : 1; + unsigned char CF0CE3 : 1; + unsigned char CF0CE2 : 1; + unsigned char CF0CE1 : 1; + unsigned char CF0CE0 : 1; +#endif + } BIT; + } CF0CR; + unsigned char CF0RR; + unsigned char PCF1DR; + unsigned char SCF1DR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CF1CE0 : 1; + unsigned char CF1CE1 : 1; + unsigned char CF1CE2 : 1; + unsigned char CF1CE3 : 1; + unsigned char CF1CE4 : 1; + unsigned char CF1CE5 : 1; + unsigned char CF1CE6 : 1; + unsigned char CF1CE7 : 1; +#else + unsigned char CF1CE7 : 1; + unsigned char CF1CE6 : 1; + unsigned char CF1CE5 : 1; + unsigned char CF1CE4 : 1; + unsigned char CF1CE3 : 1; + unsigned char CF1CE2 : 1; + unsigned char CF1CE1 : 1; + unsigned char CF1CE0 : 1; +#endif + } BIT; + } CF1CR; + unsigned char CF1RR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TCST : 1; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TOMS : 2; + unsigned char : 1; + unsigned char TWRC : 1; + unsigned char TCSS : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char TCSS : 3; + unsigned char TWRC : 1; + unsigned char : 1; + unsigned char TOMS : 2; +#endif + } BIT; + } TMR; + unsigned char TPRE; + unsigned char TCNT; +}; + +struct st_sdhi { + union { + unsigned long LONG; +// struct { +// unsigned long :16; +// unsigned long CMD12AT:2; +// unsigned long TRSTP:1; +// unsigned long CMDRW:1; +// unsigned long CMDTP:1; +// unsigned long RSPTP:3; +// unsigned long ACMD:2; +// unsigned long CMDIDX:6; +// } BIT; + } SDCMD; + char wk0[4]; + unsigned long SDARG; + char wk1[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long STP : 1; + unsigned long : 7; + unsigned long SDBLKCNTEN : 1; + unsigned long : 23; +#else + unsigned long : 23; + unsigned long SDBLKCNTEN : 1; + unsigned long : 7; + unsigned long STP : 1; +#endif + } BIT; + } SDSTOP; + unsigned long SDBLKCNT; + unsigned long SDRSP10; + char wk2[4]; + unsigned long SDRSP32; + char wk3[4]; + unsigned long SDRSP54; + char wk4[4]; + unsigned long SDRSP76; + char wk5[4]; + union { + unsigned long LONG; +// struct { +// unsigned long :21; +// unsigned long SDD3MON:1; +// unsigned long SDD3IN:1; +// unsigned long SDD3RM:1; +// unsigned long SDWPMON:1; +// unsigned long :1; +// unsigned long SDCDMON:1; +// unsigned long SDCDIN:1; +// unsigned long SDCDRM:1; +// unsigned long ACEND:1; +// unsigned long :1; +// unsigned long RSPEND:1; +// } BIT; + } SDSTS1; + union { + unsigned long LONG; +// struct { +// unsigned long :16; +// unsigned long ILA:1; +// unsigned long CBSY:1; +// unsigned long SDCLKCREN:1; +// unsigned long :3; +// unsigned long BWE:1; +// unsigned long BRE:1; +// unsigned long SDD0MON:1; +// unsigned long RSPTO:1; +// unsigned long ILR:1; +// unsigned long ILW:1; +// unsigned long DTO:1; +// unsigned long ENDE:1; +// unsigned long CRCE:1; +// unsigned long CMDE:1; +// } BIT; + } SDSTS2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RSPENDM : 1; + unsigned long : 1; + unsigned long ACENDM : 1; + unsigned long SDCDRMM : 1; + unsigned long SDCDINM : 1; + unsigned long : 3; + unsigned long SDD3RMM : 1; + unsigned long SDD3INM : 1; + unsigned long : 22; +#else + unsigned long : 22; + unsigned long SDD3INM : 1; + unsigned long SDD3RMM : 1; + unsigned long : 3; + unsigned long SDCDINM : 1; + unsigned long SDCDRMM : 1; + unsigned long ACENDM : 1; + unsigned long : 1; + unsigned long RSPENDM : 1; +#endif + } BIT; + } SDIMSK1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CMDEM : 1; + unsigned long CRCEM : 1; + unsigned long ENDEM : 1; + unsigned long DTTOM : 1; + unsigned long ILWM : 1; + unsigned long ILRM : 1; + unsigned long RSPTOM : 1; + unsigned long : 1; + unsigned long BREM : 1; + unsigned long BWEM : 1; + unsigned long : 5; + unsigned long ILAM : 1; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long ILAM : 1; + unsigned long : 5; + unsigned long BWEM : 1; + unsigned long BREM : 1; + unsigned long : 1; + unsigned long RSPTOM : 1; + unsigned long ILRM : 1; + unsigned long ILWM : 1; + unsigned long DTTOM : 1; + unsigned long ENDEM : 1; + unsigned long CRCEM : 1; + unsigned long CMDEM : 1; +#endif + } BIT; + } SDIMSK2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CLKSEL : 8; + unsigned long CLKEN : 1; + unsigned long CLKCTRLEN : 1; + unsigned long : 22; +#else + unsigned long : 22; + unsigned long CLKCTRLEN : 1; + unsigned long CLKEN : 1; + unsigned long CLKSEL : 8; +#endif + } BIT; + } SDCLKCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long LEN : 10; + unsigned long : 22; +#else + unsigned long : 22; + unsigned long LEN : 10; +#endif + } BIT; + } SDSIZE; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CTOP : 4; + unsigned long TOP : 4; + unsigned long : 7; + unsigned long WIDTH : 1; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long WIDTH : 1; + unsigned long : 7; + unsigned long TOP : 4; + unsigned long CTOP : 4; +#endif + } BIT; + } SDOPT; + char wk6[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CMDE0 : 1; + unsigned long CMDE1 : 1; + unsigned long RSPLENE0 : 1; + unsigned long RSPLENE1 : 1; + unsigned long RDLENE : 1; + unsigned long CRCLENE : 1; + unsigned long : 2; + unsigned long RSPCRCE0 : 1; + unsigned long RSPCRCE1 : 1; + unsigned long RDCRCE : 1; + unsigned long CRCTKE : 1; + unsigned long CRCTK : 3; + unsigned long : 17; +#else + unsigned long : 17; + unsigned long CRCTK : 3; + unsigned long CRCTKE : 1; + unsigned long RDCRCE : 1; + unsigned long RSPCRCE1 : 1; + unsigned long RSPCRCE0 : 1; + unsigned long : 2; + unsigned long CRCLENE : 1; + unsigned long RDLENE : 1; + unsigned long RSPLENE1 : 1; + unsigned long RSPLENE0 : 1; + unsigned long CMDE1 : 1; + unsigned long CMDE0 : 1; +#endif + } BIT; + } SDERSTS1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RSPTO0 : 1; + unsigned long RSPTO1 : 1; + unsigned long BSYTO0 : 1; + unsigned long BSYTO1 : 1; + unsigned long RDTO : 1; + unsigned long CRCTO : 1; + unsigned long CRCBSYTO : 1; + unsigned long : 25; +#else + unsigned long : 25; + unsigned long CRCBSYTO : 1; + unsigned long CRCTO : 1; + unsigned long RDTO : 1; + unsigned long BSYTO1 : 1; + unsigned long BSYTO0 : 1; + unsigned long RSPTO1 : 1; + unsigned long RSPTO0 : 1; +#endif + } BIT; + } SDERSTS2; + unsigned long SDBUFR; + char wk7[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long INTEN : 1; + unsigned long : 1; + unsigned long RWREQ : 1; + unsigned long : 5; + unsigned long IOABT : 1; + unsigned long C52PUB : 1; + unsigned long : 22; +#else + unsigned long : 22; + unsigned long C52PUB : 1; + unsigned long IOABT : 1; + unsigned long : 5; + unsigned long RWREQ : 1; + unsigned long : 1; + unsigned long INTEN : 1; +#endif + } BIT; + } SDIOMD; + union { + unsigned long LONG; +// struct { +// unsigned long :16; +// unsigned long EXWT:1; +// unsigned long EXPUB52:1; +// unsigned long :13; +// unsigned long IOIRQ:1; +// } BIT; + } SDIOSTS; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IOIRQM : 1; + unsigned long : 13; + unsigned long EXPUB52M : 1; + unsigned long EXWTM : 1; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long EXWTM : 1; + unsigned long EXPUB52M : 1; + unsigned long : 13; + unsigned long IOIRQM : 1; +#endif + } BIT; + } SDIOIMSK; + char wk8[316]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 1; + unsigned long DMAEN : 1; + unsigned long : 30; +#else + unsigned long : 30; + unsigned long DMAEN : 1; + unsigned long : 1; +#endif + } BIT; + } SDDMAEN; + char wk9[12]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SDRST : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long SDRST : 1; +#endif + } BIT; + } SDRST; + char wk10[28]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 6; + unsigned long BWSWP : 1; + unsigned long BRSWP : 1; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long BRSWP : 1; + unsigned long BWSWP : 1; + unsigned long : 6; +#endif + } BIT; + } SDSWAP; +}; + +struct st_smci { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char BCP : 2; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char BLK : 1; + unsigned char GM : 1; +#else + unsigned char GM : 1; + unsigned char BLK : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char BCP : 2; + unsigned char CKS : 2; +#endif + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char ERS : 1; + unsigned char ORER : 1; + unsigned char RDRF : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char RDRF : 1; + unsigned char ORER : 1; + unsigned char ERS : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char CHR1 : 1; + unsigned char : 2; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 2; + unsigned char CHR1 : 1; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif + } BIT; + } SCMR; + char wk0[7]; + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + unsigned char MDDR; +}; + +struct st_ssi { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long REN : 1; + unsigned long TEN : 1; + unsigned long : 1; + unsigned long MUEN : 1; + unsigned long CKDV : 4; + unsigned long DEL : 1; + unsigned long PDTA : 1; + unsigned long SDTA : 1; + unsigned long SPDP : 1; + unsigned long SWSP : 1; + unsigned long SCKP : 1; + unsigned long SWSD : 1; + unsigned long SCKD : 1; + unsigned long SWL : 3; + unsigned long DWL : 3; + unsigned long CHNL : 2; + unsigned long : 1; + unsigned long IIEN : 1; + unsigned long ROIEN : 1; + unsigned long RUIEN : 1; + unsigned long TOIEN : 1; + unsigned long TUIEN : 1; + unsigned long CKS : 1; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CKS : 1; + unsigned long TUIEN : 1; + unsigned long TOIEN : 1; + unsigned long RUIEN : 1; + unsigned long ROIEN : 1; + unsigned long IIEN : 1; + unsigned long : 1; + unsigned long CHNL : 2; + unsigned long DWL : 3; + unsigned long SWL : 3; + unsigned long SCKD : 1; + unsigned long SWSD : 1; + unsigned long SCKP : 1; + unsigned long SWSP : 1; + unsigned long SPDP : 1; + unsigned long SDTA : 1; + unsigned long PDTA : 1; + unsigned long DEL : 1; + unsigned long CKDV : 4; + unsigned long MUEN : 1; + unsigned long : 1; + unsigned long TEN : 1; + unsigned long REN : 1; +#endif + } BIT; + } SSICR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IDST : 1; + unsigned long RSWNO : 1; + unsigned long RCHNO : 2; + unsigned long TSWNO : 1; + unsigned long TCHNO : 2; + unsigned long : 18; + unsigned long IIRQ : 1; + unsigned long ROIRQ : 1; + unsigned long RUIRQ : 1; + unsigned long TOIRQ : 1; + unsigned long TUIRQ : 1; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TUIRQ : 1; + unsigned long TOIRQ : 1; + unsigned long RUIRQ : 1; + unsigned long ROIRQ : 1; + unsigned long IIRQ : 1; + unsigned long : 18; + unsigned long TCHNO : 2; + unsigned long TSWNO : 1; + unsigned long RCHNO : 2; + unsigned long RSWNO : 1; + unsigned long IDST : 1; +#endif + } BIT; + } SSISR; + char wk0[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RFRST : 1; + unsigned long TFRST : 1; + unsigned long RIE : 1; + unsigned long TIE : 1; + unsigned long RTRG : 2; + unsigned long TTRG : 2; + unsigned long : 8; + unsigned long SSIRST : 1; + unsigned long : 14; + unsigned long AUCKE : 1; +#else + unsigned long AUCKE : 1; + unsigned long : 14; + unsigned long SSIRST : 1; + unsigned long : 8; + unsigned long TTRG : 2; + unsigned long RTRG : 2; + unsigned long TIE : 1; + unsigned long RIE : 1; + unsigned long TFRST : 1; + unsigned long RFRST : 1; +#endif + } BIT; + } SSIFCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RDF : 1; + unsigned long : 7; + unsigned long RDC : 4; + unsigned long : 4; + unsigned long TDE : 1; + unsigned long : 7; + unsigned long TDC : 4; + unsigned long : 4; +#else + unsigned long : 4; + unsigned long TDC : 4; + unsigned long : 7; + unsigned long TDE : 1; + unsigned long : 4; + unsigned long RDC : 4; + unsigned long : 7; + unsigned long RDF : 1; +#endif + } BIT; + } SSIFSR; + unsigned long SSIFTDR; + unsigned long SSIFRDR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 8; + unsigned long CONT : 1; + unsigned long : 23; +#else + unsigned long : 23; + unsigned long CONT : 1; + unsigned long : 8; +#endif + } BIT; + } SSITDMR; +}; + +struct st_system { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short MD : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short MD : 1; +#endif + } BIT; + } MDMONR; + char wk0[4]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ROME : 1; + unsigned short EXBE : 1; + unsigned short : 6; + unsigned short KEY : 8; +#else + unsigned short KEY : 8; + unsigned short : 6; + unsigned short EXBE : 1; + unsigned short ROME : 1; +#endif + } BIT; + } SYSCR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RAME : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short RAME : 1; +#endif + } BIT; + } SYSCR1; + char wk1[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 14; + unsigned short OPE : 1; + unsigned short SSBY : 1; +#else + unsigned short SSBY : 1; + unsigned short OPE : 1; + unsigned short : 14; +#endif + } BIT; + } SBYCR; + char wk2[2]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long MSTPA4 : 1; + unsigned long MSTPA5 : 1; + unsigned long : 3; + unsigned long MSTPA9 : 1; + unsigned long : 3; + unsigned long MSTPA13 : 1; + unsigned long MSTPA14 : 1; + unsigned long MSTPA15 : 1; + unsigned long : 1; + unsigned long MSTPA17 : 1; + unsigned long : 1; + unsigned long MSTPA19 : 1; + unsigned long : 8; + unsigned long MSTPA28 : 1; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long MSTPA28 : 1; + unsigned long : 8; + unsigned long MSTPA19 : 1; + unsigned long : 1; + unsigned long MSTPA17 : 1; + unsigned long : 1; + unsigned long MSTPA15 : 1; + unsigned long MSTPA14 : 1; + unsigned long MSTPA13 : 1; + unsigned long : 3; + unsigned long MSTPA9 : 1; + unsigned long : 3; + unsigned long MSTPA5 : 1; + unsigned long MSTPA4 : 1; + unsigned long : 4; +#endif + } BIT; + } MSTPCRA; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MSTPB0 : 1; + unsigned long : 3; + unsigned long MSTPB4 : 1; + unsigned long : 1; + unsigned long MSTPB6 : 1; + unsigned long : 2; + unsigned long MSTPB9 : 1; + unsigned long MSTPB10 : 1; + unsigned long : 6; + unsigned long MSTPB17 : 1; + unsigned long : 1; + unsigned long MSTPB19 : 1; + unsigned long : 1; + unsigned long MSTPB21 : 1; + unsigned long : 1; + unsigned long MSTPB23 : 1; + unsigned long : 1; + unsigned long MSTPB25 : 1; + unsigned long MSTPB26 : 1; + unsigned long : 3; + unsigned long MSTPB30 : 1; + unsigned long MSTPB31 : 1; +#else + unsigned long MSTPB31 : 1; + unsigned long MSTPB30 : 1; + unsigned long : 3; + unsigned long MSTPB26 : 1; + unsigned long MSTPB25 : 1; + unsigned long : 1; + unsigned long MSTPB23 : 1; + unsigned long : 1; + unsigned long MSTPB21 : 1; + unsigned long : 1; + unsigned long MSTPB19 : 1; + unsigned long : 1; + unsigned long MSTPB17 : 1; + unsigned long : 6; + unsigned long MSTPB10 : 1; + unsigned long MSTPB9 : 1; + unsigned long : 2; + unsigned long MSTPB6 : 1; + unsigned long : 1; + unsigned long MSTPB4 : 1; + unsigned long : 3; + unsigned long MSTPB0 : 1; +#endif + } BIT; + } MSTPCRB; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MSTPC0 : 1; + unsigned long MSTPC1 : 1; + unsigned long : 17; + unsigned long MSTPC19 : 1; + unsigned long MSTPC20 : 1; + unsigned long : 5; + unsigned long MSTPC26 : 1; + unsigned long MSTPC27 : 1; + unsigned long MSTPC28 : 1; + unsigned long MSTPC29 : 1; + unsigned long MSTPC30 : 1; + unsigned long DSLPE : 1; +#else + unsigned long DSLPE : 1; + unsigned long MSTPC30 : 1; + unsigned long MSTPC29 : 1; + unsigned long MSTPC28 : 1; + unsigned long MSTPC27 : 1; + unsigned long MSTPC26 : 1; + unsigned long : 5; + unsigned long MSTPC20 : 1; + unsigned long MSTPC19 : 1; + unsigned long : 17; + unsigned long MSTPC1 : 1; + unsigned long MSTPC0 : 1; +#endif + } BIT; + } MSTPCRC; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 10; + unsigned long MSTPD10 : 1; + unsigned long : 4; + unsigned long MSTPD15 : 1; + unsigned long : 3; + unsigned long MSTPD19 : 1; + unsigned long : 11; + unsigned long MSTPD31 : 1; +#else + unsigned long MSTPD31 : 1; + unsigned long : 11; + unsigned long MSTPD19 : 1; + unsigned long : 3; + unsigned long MSTPD15 : 1; + unsigned long : 4; + unsigned long MSTPD10 : 1; + unsigned long : 10; +#endif + } BIT; + } MSTPCRD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PCKD : 4; + unsigned long : 4; + unsigned long PCKB : 4; + unsigned long PCKA : 4; + unsigned long BCK : 4; + unsigned long : 3; + unsigned long PSTOP1 : 1; + unsigned long ICK : 4; + unsigned long FCK : 4; +#else + unsigned long FCK : 4; + unsigned long ICK : 4; + unsigned long PSTOP1 : 1; + unsigned long : 3; + unsigned long BCK : 4; + unsigned long PCKA : 4; + unsigned long PCKB : 4; + unsigned long : 4; + unsigned long PCKD : 4; +#endif + } BIT; + } SCKCR; + char wk3[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short CKSEL : 3; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short CKSEL : 3; + unsigned short : 8; +#endif + } BIT; + } SCKCR3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PLIDIV : 2; + unsigned short : 6; + unsigned short STC : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short STC : 6; + unsigned short : 6; + unsigned short PLIDIV : 2; +#endif + } BIT; + } PLLCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PLLEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char PLLEN : 1; +#endif + } BIT; + } PLLCR2; + char wk4[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short UPLIDIV : 2; + unsigned short : 2; + unsigned short UCKUPLLSEL : 1; + unsigned short : 3; + unsigned short USTC : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short USTC : 6; + unsigned short : 3; + unsigned short UCKUPLLSEL : 1; + unsigned short : 2; + unsigned short UPLIDIV : 2; +#endif + } BIT; + } UPLLCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char UPLLEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char UPLLEN : 1; +#endif + } BIT; + } UPLLCR2; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCLKDIV : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char BCLKDIV : 1; +#endif + } BIT; + } BCKCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MEMWAIT : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char MEMWAIT : 1; +#endif + } BIT; + } MEMWAIT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MOSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char MOSTP : 1; +#endif + } BIT; + } MOSCCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SOSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SOSTP : 1; +#endif + } BIT; + } SOSCCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LCSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char LCSTP : 1; +#endif + } BIT; + } LOCOCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ILCSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char ILCSTP : 1; +#endif + } BIT; + } ILOCOCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HCSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char HCSTP : 1; +#endif + } BIT; + } HOCOCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HCFRQ : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char HCFRQ : 2; +#endif + } BIT; + } HOCOCR2; + char wk6[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MOOVF : 1; + unsigned char : 1; + unsigned char PLOVF : 1; + unsigned char HCOVF : 1; + unsigned char : 1; + unsigned char UPLOVF : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char UPLOVF : 1; + unsigned char : 1; + unsigned char HCOVF : 1; + unsigned char PLOVF : 1; + unsigned char : 1; + unsigned char MOOVF : 1; +#endif + } BIT; + } OSCOVFSR; + char wk7[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short CKOSEL : 4; + unsigned short CKODIV : 3; + unsigned short CKOSTP : 1; +#else + unsigned short CKOSTP : 1; + unsigned short CKODIV : 3; + unsigned short CKOSEL : 4; + unsigned short : 8; +#endif + } BIT; + } CKOCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSTDIE : 1; + unsigned char : 6; + unsigned char OSTDE : 1; +#else + unsigned char OSTDE : 1; + unsigned char : 6; + unsigned char OSTDIE : 1; +#endif + } BIT; + } OSTDCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSTDF : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char OSTDF : 1; +#endif + } BIT; + } OSTDSR; + char wk8[30]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LOCOTRD : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char LOCOTRD : 5; +#endif + } BIT; + } LOCOTRR; + char wk9[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ILOCOTRD : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char ILOCOTRD : 5; +#endif + } BIT; + } ILOCOTRR; + char wk10[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HOCOTRD : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char HOCOTRD : 6; +#endif + } BIT; + } HOCOTRR0; + char wk11[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HOCOTRD : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char HOCOTRD : 6; +#endif + } BIT; + } HOCOTRR3; + char wk12[52]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OPCM : 3; + unsigned char : 1; + unsigned char OPCMTSF : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char OPCMTSF : 1; + unsigned char : 1; + unsigned char OPCM : 3; +#endif + } BIT; + } OPCCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RSTCKSEL : 3; + unsigned char : 4; + unsigned char RSTCKEN : 1; +#else + unsigned char RSTCKEN : 1; + unsigned char : 4; + unsigned char RSTCKSEL : 3; +#endif + } BIT; + } RSTCKCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MSTS : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char MSTS : 5; +#endif + } BIT; + } MOSCWTCR; + char wk13[7]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SOPCM : 1; + unsigned char : 3; + unsigned char SOPCMTSF : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char SOPCMTSF : 1; + unsigned char : 3; + unsigned char SOPCM : 1; +#endif + } BIT; + } SOPCCR; + char wk14[21]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IWDTRF : 1; + unsigned char WDTRF : 1; + unsigned char SWRF : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SWRF : 1; + unsigned char WDTRF : 1; + unsigned char IWDTRF : 1; +#endif + } BIT; + } RSTSR2; + char wk15[1]; + unsigned short SWRR; + char wk16[28]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1IDTSEL : 2; + unsigned char LVD1IRQSEL : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char LVD1IRQSEL : 1; + unsigned char LVD1IDTSEL : 2; +#endif + } BIT; + } LVD1CR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1DET : 1; + unsigned char LVD1MON : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char LVD1MON : 1; + unsigned char LVD1DET : 1; +#endif + } BIT; + } LVD1SR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD2IDTSEL : 2; + unsigned char LVD2IRQSEL : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char LVD2IRQSEL : 1; + unsigned char LVD2IDTSEL : 2; +#endif + } BIT; + } LVD2CR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD2DET : 1; + unsigned char LVD2MON : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char LVD2MON : 1; + unsigned char LVD2DET : 1; +#endif + } BIT; + } LVD2SR; + char wk17[794]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PRC0 : 1; + unsigned short PRC1 : 1; + unsigned short PRC2 : 1; + unsigned short PRC3 : 1; + unsigned short : 4; + unsigned short PRKEY : 8; +#else + unsigned short PRKEY : 8; + unsigned short : 4; + unsigned short PRC3 : 1; + unsigned short PRC2 : 1; + unsigned short PRC1 : 1; + unsigned short PRC0 : 1; +#endif + } BIT; + } PRCR; + char wk18[48784]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PORF : 1; + unsigned char LVD0RF : 1; + unsigned char LVD1RF : 1; + unsigned char LVD2RF : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char LVD2RF : 1; + unsigned char LVD1RF : 1; + unsigned char LVD0RF : 1; + unsigned char PORF : 1; +#endif + } BIT; + } RSTSR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CWSF : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CWSF : 1; +#endif + } BIT; + } RSTSR1; + char wk19[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 5; + unsigned char MODRV21 : 1; + unsigned char MOSEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MOSEL : 1; + unsigned char MODRV21 : 1; + unsigned char : 5; +#endif + } BIT; + } MOFCR; + char wk20[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char EXVCCINP2 : 1; + unsigned char : 1; + unsigned char LVD1E : 1; + unsigned char LVD2E : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char LVD2E : 1; + unsigned char LVD1E : 1; + unsigned char : 1; + unsigned char EXVCCINP2 : 1; + unsigned char : 3; +#endif + } BIT; + } LVCMPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1LVL : 4; + unsigned char LVD2LVL : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char LVD2LVL : 2; + unsigned char LVD1LVL : 4; +#endif + } BIT; + } LVDLVLR; + char wk21[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1RIE : 1; + unsigned char : 1; + unsigned char LVD1CMPE : 1; + unsigned char : 3; + unsigned char LVD1RI : 1; + unsigned char LVD1RN : 1; +#else + unsigned char LVD1RN : 1; + unsigned char LVD1RI : 1; + unsigned char : 3; + unsigned char LVD1CMPE : 1; + unsigned char : 1; + unsigned char LVD1RIE : 1; +#endif + } BIT; + } LVD1CR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD2RIE : 1; + unsigned char : 1; + unsigned char LVD2CMPE : 1; + unsigned char : 3; + unsigned char LVD2RI : 1; + unsigned char LVD2RN : 1; +#else + unsigned char LVD2RN : 1; + unsigned char LVD2RI : 1; + unsigned char : 3; + unsigned char LVD2CMPE : 1; + unsigned char : 1; + unsigned char LVD2RIE : 1; +#endif + } BIT; + } LVD2CR0; + char wk22[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char VBATTDIS : 1; + unsigned char : 3; + unsigned char VBTLVDEN : 1; + unsigned char : 1; + unsigned char VBTLVDLVL : 2; +#else + unsigned char VBTLVDLVL : 2; + unsigned char : 1; + unsigned char VBTLVDEN : 1; + unsigned char : 3; + unsigned char VBATTDIS : 1; +#endif + } BIT; + } VBATTCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char VBATRLVDETF : 1; + unsigned char VBTLVDMON : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char VBTLVDMON : 1; + unsigned char VBATRLVDETF : 1; +#endif + } BIT; + } VBATTSR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char VBTLVDIE : 1; + unsigned char VBTLVDISEL : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char VBTLVDISEL : 1; + unsigned char VBTLVDIE : 1; +#endif + } BIT; + } VBTLVDICR; +}; + +struct st_tempsconst { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 16; + unsigned long TSCD : 12; + unsigned long : 4; +#else + unsigned long : 4; + unsigned long TSCD : 12; + unsigned long : 16; +#endif + } BIT; + } TSCDR; +}; + +struct st_tmr0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char CCLR : 2; + unsigned char OVIE : 1; + unsigned char CMIEA : 1; + unsigned char CMIEB : 1; +#else + unsigned char CMIEB : 1; + unsigned char CMIEA : 1; + unsigned char OVIE : 1; + unsigned char CCLR : 2; + unsigned char : 3; +#endif + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSA : 2; + unsigned char OSB : 2; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char OSB : 2; + unsigned char OSA : 2; +#endif + } BIT; + } TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 3; + unsigned char CSS : 2; + unsigned char : 2; + unsigned char TMRIS : 1; +#else + unsigned char TMRIS : 1; + unsigned char : 2; + unsigned char CSS : 2; + unsigned char CKS : 3; +#endif + } BIT; + } TCCR; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCS : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TCS : 1; +#endif + } BIT; + } TCSTR; +}; + +struct st_tmr1 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char CCLR : 2; + unsigned char OVIE : 1; + unsigned char CMIEA : 1; + unsigned char CMIEB : 1; +#else + unsigned char CMIEB : 1; + unsigned char CMIEA : 1; + unsigned char OVIE : 1; + unsigned char CCLR : 2; + unsigned char : 3; +#endif + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSA : 2; + unsigned char OSB : 2; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char OSB : 2; + unsigned char OSA : 2; +#endif + } BIT; + } TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 3; + unsigned char CSS : 2; + unsigned char : 2; + unsigned char TMRIS : 1; +#else + unsigned char TMRIS : 1; + unsigned char : 2; + unsigned char CSS : 2; + unsigned char CKS : 3; +#endif + } BIT; + } TCCR; +}; + +struct st_tmr01 { + unsigned short TCORA; + unsigned short TCORB; + unsigned short TCNT; + unsigned short TCCR; +}; + +struct st_tpu { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CST0 : 1; + unsigned char CST1 : 1; + unsigned char CST2 : 1; + unsigned char CST3 : 1; + unsigned char CST4 : 1; + unsigned char CST5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char CST5 : 1; + unsigned char CST4 : 1; + unsigned char CST3 : 1; + unsigned char CST2 : 1; + unsigned char CST1 : 1; + unsigned char CST0 : 1; +#endif + } BIT; + } TSTR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SYNC0 : 1; + unsigned char SYNC1 : 1; + unsigned char SYNC2 : 1; + unsigned char SYNC3 : 1; + unsigned char SYNC4 : 1; + unsigned char SYNC5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char SYNC5 : 1; + unsigned char SYNC4 : 1; + unsigned char SYNC3 : 1; + unsigned char SYNC2 : 1; + unsigned char SYNC1 : 1; + unsigned char SYNC0 : 1; +#endif + } BIT; + } TSYR; +}; + +struct st_tpu0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk0[7]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char ICSELB : 1; + unsigned char ICSELD : 1; +#else + unsigned char ICSELD : 1; + unsigned char ICSELB : 1; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGFA : 1; + unsigned char TGFB : 1; + unsigned char TGFC : 1; + unsigned char TGFD : 1; + unsigned char TCFV : 1; + unsigned char TCFU : 1; + unsigned char : 1; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 1; + unsigned char TCFU : 1; + unsigned char TCFV : 1; + unsigned char TGFD : 1; + unsigned char TGFC : 1; + unsigned char TGFB : 1; + unsigned char TGFA : 1; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; +}; + +struct st_tpu1 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk1[22]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char ICSELB : 1; + unsigned char ICSELD : 1; +#else + unsigned char ICSELD : 1; + unsigned char ICSELB : 1; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGFA : 1; + unsigned char TGFB : 1; + unsigned char TGFC : 1; + unsigned char TGFD : 1; + unsigned char TCFV : 1; + unsigned char TCFU : 1; + unsigned char : 1; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 1; + unsigned char TCFU : 1; + unsigned char TCFV : 1; + unsigned char TGFD : 1; + unsigned char TGFC : 1; + unsigned char TGFB : 1; + unsigned char TGFA : 1; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_tpu2 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk0[37]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char ICSELB : 1; + unsigned char ICSELD : 1; +#else + unsigned char ICSELD : 1; + unsigned char ICSELB : 1; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGFA : 1; + unsigned char TGFB : 1; + unsigned char TGFC : 1; + unsigned char TGFD : 1; + unsigned char TCFV : 1; + unsigned char TCFU : 1; + unsigned char : 1; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 1; + unsigned char TCFU : 1; + unsigned char TCFV : 1; + unsigned char TGFD : 1; + unsigned char TGFC : 1; + unsigned char TGFB : 1; + unsigned char TGFA : 1; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_tpu3 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk1[52]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char ICSELB : 1; + unsigned char ICSELD : 1; +#else + unsigned char ICSELD : 1; + unsigned char ICSELB : 1; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGFA : 1; + unsigned char TGFB : 1; + unsigned char TGFC : 1; + unsigned char TGFD : 1; + unsigned char TCFV : 1; + unsigned char TCFU : 1; + unsigned char : 1; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 1; + unsigned char TCFU : 1; + unsigned char TCFV : 1; + unsigned char TGFD : 1; + unsigned char TGFC : 1; + unsigned char TGFB : 1; + unsigned char TGFA : 1; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; +}; + +struct st_tpu4 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk0[67]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char ICSELB : 1; + unsigned char ICSELD : 1; +#else + unsigned char ICSELD : 1; + unsigned char ICSELB : 1; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGFA : 1; + unsigned char TGFB : 1; + unsigned char TGFC : 1; + unsigned char TGFD : 1; + unsigned char TCFV : 1; + unsigned char TCFU : 1; + unsigned char : 1; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 1; + unsigned char TCFU : 1; + unsigned char TCFV : 1; + unsigned char TGFD : 1; + unsigned char TGFC : 1; + unsigned char TGFB : 1; + unsigned char TGFA : 1; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_tpu5 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk1[82]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char ICSELB : 1; + unsigned char ICSELD : 1; +#else + unsigned char ICSELD : 1; + unsigned char ICSELB : 1; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGFA : 1; + unsigned char TGFB : 1; + unsigned char TGFC : 1; + unsigned char TGFD : 1; + unsigned char TCFV : 1; + unsigned char TCFU : 1; + unsigned char : 1; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 1; + unsigned char TCFU : 1; + unsigned char TCFV : 1; + unsigned char TGFD : 1; + unsigned char TGFC : 1; + unsigned char TGFB : 1; + unsigned char TGFA : 1; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_usb0 { + union { + unsigned short WORD; +// struct { +// unsigned short :5; +// unsigned short SCKE:1; +// unsigned short :1; +// unsigned short CNEN:1; +// unsigned short :1; +// unsigned short DCFM:1; +// unsigned short DRPD:1; +// unsigned short DPRPU:1; +// unsigned short DMRPU:1; +// unsigned short :2; +// unsigned short USBE:1; +// } BIT; + } SYSCFG; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short LNST : 2; + unsigned short IDMON : 1; + unsigned short : 3; + unsigned short HTACT : 1; + unsigned short : 7; + unsigned short OVCMON : 2; +#else + unsigned short OVCMON : 2; + unsigned short : 7; + unsigned short HTACT : 1; + unsigned short : 3; + unsigned short IDMON : 1; + unsigned short LNST : 2; +#endif + } BIT; + } SYSSTS0; + char wk1[2]; + union { + unsigned short WORD; +// struct { +// unsigned short :4; +// unsigned short HNPBTOA:1; +// unsigned short EXICEN:1; +// unsigned short VBUSEN:1; +// unsigned short WKUP:1; +// unsigned short RWUPE:1; +// unsigned short USBRST:1; +// unsigned short RESUME:1; +// unsigned short UACT:1; +// unsigned short :1; +// unsigned short RHST:3; +// } BIT; + } DVSTCTR0; + char wk2[10]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } CFIFO; + char wk3[2]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } D0FIFO; + char wk4[2]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } D1FIFO; + char wk5[2]; + union { + unsigned short WORD; +// struct { +// unsigned short RCNT:1; +// unsigned short REW:1; +// unsigned short :3; +// unsigned short MBW:1; +// unsigned short :1; +// unsigned short BIGEND:1; +// unsigned short :2; +// unsigned short ISEL:1; +// unsigned short :1; +// unsigned short CURPIPE:4; +// } BIT; + } CFIFOSEL; + union { + unsigned short WORD; +// struct { +// unsigned short BVAL:1; +// unsigned short BCLR:1; +// unsigned short FRDY:1; +// unsigned short :4; +// unsigned short DTLN:9; +// } BIT; + } CFIFOCTR; + char wk6[4]; + union { + unsigned short WORD; +// struct { +// unsigned short RCNT:1; +// unsigned short REW:1; +// unsigned short DCLRM:1; +// unsigned short DREQE:1; +// unsigned short :1; +// unsigned short MBW:1; +// unsigned short :1; +// unsigned short BIGEND:1; +// unsigned short :4; +// unsigned short CURPIPE:4; +// } BIT; + } D0FIFOSEL; + union { + unsigned short WORD; +// struct { +// unsigned short BVAL:1; +// unsigned short BCLR:1; +// unsigned short FRDY:1; +// unsigned short :4; +// unsigned short DTLN:9; +// } BIT; + } D0FIFOCTR; + union { + unsigned short WORD; +// struct { +// unsigned short RCNT:1; +// unsigned short REW:1; +// unsigned short DCLRM:1; +// unsigned short DREQE:1; +// unsigned short :1; +// unsigned short MBW:1; +// unsigned short :1; +// unsigned short BIGEND:1; +// unsigned short :4; +// unsigned short CURPIPE:4; +// } BIT; + } D1FIFOSEL; + union { + unsigned short WORD; +// struct { +// unsigned short BVAL:1; +// unsigned short BCLR:1; +// unsigned short FRDY:1; +// unsigned short :4; +// unsigned short DTLN:9; +// } BIT; + } D1FIFOCTR; + union { + unsigned short WORD; +// struct { +// unsigned short VBSE:1; +// unsigned short RSME:1; +// unsigned short SOFE:1; +// unsigned short DVSE:1; +// unsigned short CTRE:1; +// unsigned short BEMPE:1; +// unsigned short NRDYE:1; +// unsigned short BRDYE:1; +// unsigned short :8; +// } BIT; + } INTENB0; + union { + unsigned short WORD; +// struct { +// unsigned short OVRCRE:1; +// unsigned short BCHGE:1; +// unsigned short :1; +// unsigned short DTCHE:1; +// unsigned short ATTCHE:1; +// unsigned short :4; +// unsigned short EOFERRE:1; +// unsigned short SIGNE:1; +// unsigned short SACKE:1; +// unsigned short :3; +// unsigned short PDDETINTE0:1; +// } BIT; + } INTENB1; + char wk7[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PIPE0BRDYE : 1; + unsigned short PIPE1BRDYE : 1; + unsigned short PIPE2BRDYE : 1; + unsigned short PIPE3BRDYE : 1; + unsigned short PIPE4BRDYE : 1; + unsigned short PIPE5BRDYE : 1; + unsigned short PIPE6BRDYE : 1; + unsigned short PIPE7BRDYE : 1; + unsigned short PIPE8BRDYE : 1; + unsigned short PIPE9BRDYE : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short PIPE9BRDYE : 1; + unsigned short PIPE8BRDYE : 1; + unsigned short PIPE7BRDYE : 1; + unsigned short PIPE6BRDYE : 1; + unsigned short PIPE5BRDYE : 1; + unsigned short PIPE4BRDYE : 1; + unsigned short PIPE3BRDYE : 1; + unsigned short PIPE2BRDYE : 1; + unsigned short PIPE1BRDYE : 1; + unsigned short PIPE0BRDYE : 1; +#endif + } BIT; + } BRDYENB; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PIPE0NRDYE : 1; + unsigned short PIPE1NRDYE : 1; + unsigned short PIPE2NRDYE : 1; + unsigned short PIPE3NRDYE : 1; + unsigned short PIPE4NRDYE : 1; + unsigned short PIPE5NRDYE : 1; + unsigned short PIPE6NRDYE : 1; + unsigned short PIPE7NRDYE : 1; + unsigned short PIPE8NRDYE : 1; + unsigned short PIPE9NRDYE : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short PIPE9NRDYE : 1; + unsigned short PIPE8NRDYE : 1; + unsigned short PIPE7NRDYE : 1; + unsigned short PIPE6NRDYE : 1; + unsigned short PIPE5NRDYE : 1; + unsigned short PIPE4NRDYE : 1; + unsigned short PIPE3NRDYE : 1; + unsigned short PIPE2NRDYE : 1; + unsigned short PIPE1NRDYE : 1; + unsigned short PIPE0NRDYE : 1; +#endif + } BIT; + } NRDYENB; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PIPE0BEMPE : 1; + unsigned short PIPE1BEMPE : 1; + unsigned short PIPE2BEMPE : 1; + unsigned short PIPE3BEMPE : 1; + unsigned short PIPE4BEMPE : 1; + unsigned short PIPE5BEMPE : 1; + unsigned short PIPE6BEMPE : 1; + unsigned short PIPE7BEMPE : 1; + unsigned short PIPE8BEMPE : 1; + unsigned short PIPE9BEMPE : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short PIPE9BEMPE : 1; + unsigned short PIPE8BEMPE : 1; + unsigned short PIPE7BEMPE : 1; + unsigned short PIPE6BEMPE : 1; + unsigned short PIPE5BEMPE : 1; + unsigned short PIPE4BEMPE : 1; + unsigned short PIPE3BEMPE : 1; + unsigned short PIPE2BEMPE : 1; + unsigned short PIPE1BEMPE : 1; + unsigned short PIPE0BEMPE : 1; +#endif + } BIT; + } BEMPENB; + union { + unsigned short WORD; +// struct { +// unsigned short :7; +// unsigned short TRNENSEL:1; +// unsigned short :1; +// unsigned short BRDYM:1; +// unsigned short :1; +// unsigned short EDGESTS:1; +// unsigned short :4; +// } BIT; + } SOFCFG; + char wk8[2]; + union { + unsigned short WORD; +// struct { +// unsigned short VBINT:1; +// unsigned short RESM:1; +// unsigned short SOFR:1; +// unsigned short DVST:1; +// unsigned short CTRT:1; +// unsigned short BEMP:1; +// unsigned short NRDY:1; +// unsigned short BRDY:1; +// unsigned short VBSTS:1; +// unsigned short DVSQ:3; +// unsigned short VALID:1; +// unsigned short CTSQ:3; +// } BIT; + } INTSTS0; + union { + unsigned short WORD; +// struct { +// unsigned short OVRCR:1; +// unsigned short BCHG:1; +// unsigned short :1; +// unsigned short DTCH:1; +// unsigned short ATTCH:1; +// unsigned short :4; +// unsigned short EOFERR:1; +// unsigned short SIGN:1; +// unsigned short SACK:1; +// unsigned short :3; +// unsigned short PDDETINT0:1; +// } BIT; + } INTSTS1; + char wk9[2]; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short PIPE9BRDY:1; +// unsigned short PIPE8BRDY:1; +// unsigned short PIPE7BRDY:1; +// unsigned short PIPE6BRDY:1; +// unsigned short PIPE5BRDY:1; +// unsigned short PIPE4BRDY:1; +// unsigned short PIPE3BRDY:1; +// unsigned short PIPE2BRDY:1; +// unsigned short PIPE1BRDY:1; +// unsigned short PIPE0BRDY:1; +// } BIT; + } BRDYSTS; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short PIPE9NRDY:1; +// unsigned short PIPE8NRDY:1; +// unsigned short PIPE7NRDY:1; +// unsigned short PIPE6NRDY:1; +// unsigned short PIPE5NRDY:1; +// unsigned short PIPE4NRDY:1; +// unsigned short PIPE3NRDY:1; +// unsigned short PIPE2NRDY:1; +// unsigned short PIPE1NRDY:1; +// unsigned short PIPE0NRDY:1; +// } BIT; + } NRDYSTS; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short PIPE9BEMP:1; +// unsigned short PIPE8BEMP:1; +// unsigned short PIPE7BEMP:1; +// unsigned short PIPE6BEMP:1; +// unsigned short PIPE5BEMP:1; +// unsigned short PIPE4BEMP:1; +// unsigned short PIPE3BEMP:1; +// unsigned short PIPE2BEMP:1; +// unsigned short PIPE1BEMP:1; +// unsigned short PIPE0BEMP:1; +// } BIT; + } BEMPSTS; + union { + unsigned short WORD; +// struct { +// unsigned short OVRN:1; +// unsigned short CRCE:1; +// unsigned short :3; +// unsigned short FRNM:11; +// } BIT; + } FRMNUM; + char wk10[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short BMREQUESTTYPE : 8; + unsigned short BREQUEST : 8; +#else + unsigned short BREQUEST : 8; + unsigned short BMREQUESTTYPE : 8; +#endif + } BIT; + } USBREQ; + unsigned short USBVAL; + unsigned short USBINDX; + unsigned short USBLENG; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short SHTNAK:1; +// unsigned short :2; +// unsigned short DIR:1; +// unsigned short :4; +// } BIT; + } DCPCFG; + union { + unsigned short WORD; +// struct { +// unsigned short DEVSEL:4; +// unsigned short :5; +// unsigned short MXPS:7; +// } BIT; + } DCPMAXP; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short SUREQ:1; +// unsigned short :2; +// unsigned short SUREQCLR:1; +// unsigned short :2; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :2; +// unsigned short CCPL:1; +// unsigned short PID:2; +// } BIT; + } DCPCTR; + char wk11[2]; + union { + unsigned short WORD; +// struct { +// unsigned short :12; +// unsigned short PIPESEL:4; +// } BIT; + } PIPESEL; + char wk12[2]; + union { + unsigned short WORD; +// struct { +// unsigned short TYPE:2; +// unsigned short :3; +// unsigned short BFRE:1; +// unsigned short DBLB:1; +// unsigned short :1; +// unsigned short SHTNAK:1; +// unsigned short :2; +// unsigned short DIR:1; +// unsigned short EPNUM:4; +// } BIT; + } PIPECFG; + char wk13[2]; + union { + unsigned short WORD; +// struct { +// unsigned short DEVSEL:4; +// unsigned short :3; +// unsigned short MXPS:9; +// } BIT; + } PIPEMAXP; + union { + unsigned short WORD; +// struct { +// unsigned short :3; +// unsigned short IFIS:1; +// unsigned short :9; +// unsigned short IITV:3; +// } BIT; + } PIPEPERI; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE1CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE2CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE3CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE4CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE5CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short :5; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE6CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short :5; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE7CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short :5; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE8CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short :5; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE9CTR; + char wk14[14]; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// unsigned short :8; +// } BIT; + } PIPE1TRE; + unsigned short PIPE1TRN; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// unsigned short :8; +// } BIT; + } PIPE2TRE; + unsigned short PIPE2TRN; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// unsigned short :8; +// } BIT; + } PIPE3TRE; + unsigned short PIPE3TRN; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// unsigned short :8; +// } BIT; + } PIPE4TRE; + unsigned short PIPE4TRN; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// unsigned short :8; +// } BIT; + } PIPE5TRE; + unsigned short PIPE5TRN; + char wk15[12]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RPDME0 : 1; + unsigned short IDPSRCE0 : 1; + unsigned short IDMSINKE0 : 1; + unsigned short VDPSRCE0 : 1; + unsigned short IDPSINKE0 : 1; + unsigned short VDMSRCE0 : 1; + unsigned short : 1; + unsigned short BATCHGE0 : 1; + unsigned short CHGDETSTS0 : 1; + unsigned short PDDETSTS0 : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short PDDETSTS0 : 1; + unsigned short CHGDETSTS0 : 1; + unsigned short BATCHGE0 : 1; + unsigned short : 1; + unsigned short VDMSRCE0 : 1; + unsigned short IDPSINKE0 : 1; + unsigned short VDPSRCE0 : 1; + unsigned short IDMSINKE0 : 1; + unsigned short IDPSRCE0 : 1; + unsigned short RPDME0 : 1; +#endif + } BIT; + } USBBCCTRL0; + char wk16[26]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short VDDUSBE : 1; + unsigned short : 6; + unsigned short VDCEN : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short VDCEN : 1; + unsigned short : 6; + unsigned short VDDUSBE : 1; +#endif + } BIT; + } USBMC; + char wk17[2]; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// unsigned short :6; +// } BIT; + } DEVADD0; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// unsigned short :6; +// } BIT; + } DEVADD1; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// unsigned short :6; +// } BIT; + } DEVADD2; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// unsigned short :6; +// } BIT; + } DEVADD3; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// unsigned short :6; +// } BIT; + } DEVADD4; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// unsigned short :6; +// } BIT; + } DEVADD5; +}; + +struct st_wdt { + unsigned char WDTRR; + char wk0[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TOPS : 2; + unsigned short : 2; + unsigned short CKS : 4; + unsigned short RPES : 2; + unsigned short : 2; + unsigned short RPSS : 2; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short RPSS : 2; + unsigned short : 2; + unsigned short RPES : 2; + unsigned short CKS : 4; + unsigned short : 2; + unsigned short TOPS : 2; +#endif + } BIT; + } WDTCR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CNTVAL : 14; + unsigned short UNDFF : 1; + unsigned short REFEF : 1; +#else + unsigned short REFEF : 1; + unsigned short UNDFF : 1; + unsigned short CNTVAL : 14; +#endif + } BIT; + } WDTSR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char RSTIRQS : 1; +#else + unsigned char RSTIRQS : 1; + unsigned char : 7; +#endif + } BIT; + } WDTRCR; +}; + +enum enum_ir { +IR_BSC_BUSERR=16,IR_FCU_FRDYI=23, +IR_ICU_SWINT=27, +IR_CMT0_CMI0,IR_CMT1_CMI1, +IR_CMT2_CMI2,IR_CMT3_CMI3, +IR_CAC_FERRF,IR_CAC_MENDF,IR_CAC_OVFF, +IR_USB0_D0FIFO0=36,IR_USB0_D1FIFO0,IR_USB0_USBI0, +IR_SDHI_SBFAI=40,IR_SDHI_CDETI,IR_SDHI_CACI,IR_SDHI_SDACI, +IR_RSPI0_SPEI0,IR_RSPI0_SPRI0,IR_RSPI0_SPTI0,IR_RSPI0_SPII0, +IR_RSCAN_COMFRXINT=52,IR_RSCAN_RXFINT,IR_RSCAN_TXINT,IR_RSCAN_CHERRINT,IR_RSCAN_GLERRINT, +IR_DOC_DOPCF, +IR_CMPB_CMPB0,IR_CMPB_CMPB1, +IR_CTSU_CTSUWR,IR_CTSU_CTSURD,IR_CTSU_CTSUFN, +IR_RTC_CUP, +IR_ICU_IRQ0,IR_ICU_IRQ1,IR_ICU_IRQ2,IR_ICU_IRQ3,IR_ICU_IRQ4,IR_ICU_IRQ5,IR_ICU_IRQ6,IR_ICU_IRQ7, +IR_ELC_ELSR8I=80, +IR_LVD_LVD1=88,IR_LVD_LVD2, +IR_CMPA_CMPA1=88,IR_CMPA_CMPA2, +IR_USB0_USBR0, +IR_VBATT_VBTLVDI, +IR_RTC_ALM,IR_RTC_PRD, +IR_S12AD_S12ADI0=102,IR_S12AD_GBADI, +IR_CMPB1_CMPB2,IR_CMPB1_CMPB3, +IR_ELC_ELSR18I,IR_ELC_ELSR19I, +IR_SSI0_SSIF0,IR_SSI0_SSIRXI0,IR_SSI0_SSITXI0, +IR_SECURITY_RD,IR_SECURITY_WR,IR_SECURITY_ERR, +IR_MTU0_TGIA0,IR_MTU0_TGIB0,IR_MTU0_TGIC0,IR_MTU0_TGID0,IR_MTU0_TCIV0,IR_MTU0_TGIE0,IR_MTU0_TGIF0, +IR_MTU1_TGIA1,IR_MTU1_TGIB1,IR_MTU1_TCIV1,IR_MTU1_TCIU1, +IR_MTU2_TGIA2,IR_MTU2_TGIB2,IR_MTU2_TCIV2,IR_MTU2_TCIU2, +IR_MTU3_TGIA3,IR_MTU3_TGIB3,IR_MTU3_TGIC3,IR_MTU3_TGID3,IR_MTU3_TCIV3, +IR_MTU4_TGIA4,IR_MTU4_TGIB4,IR_MTU4_TGIC4,IR_MTU4_TGID4,IR_MTU4_TCIV4, +IR_MTU5_TGIU5,IR_MTU5_TGIV5,IR_MTU5_TGIW5, +IR_TPU0_TGI0A,IR_TPU0_TGI0B,IR_TPU0_TGI0C,IR_TPU0_TGI0D,IR_TPU0_TCI0V, +IR_TPU1_TGI1A,IR_TPU1_TGI1B,IR_TPU1_TCI1V,IR_TPU1_TCI1U, +IR_TPU2_TGI2A,IR_TPU2_TGI2B,IR_TPU2_TCI2V,IR_TPU2_TCI2U, +IR_TPU3_TGI3A,IR_TPU3_TGI3B,IR_TPU3_TGI3C,IR_TPU3_TGI3D,IR_TPU3_TCI3V, +IR_TPU4_TGI4A,IR_TPU4_TGI4B,IR_TPU4_TCI4V,IR_TPU4_TCI4U, +IR_TPU5_TGI5A,IR_TPU5_TGI5B,IR_TPU5_TCI5V,IR_TPU5_TCI5U, +IR_POE_OEI1=170,IR_POE_OEI2, +IR_TMR0_CMIA0=174,IR_TMR0_CMIB0,IR_TMR0_OVI0, +IR_TMR1_CMIA1,IR_TMR1_CMIB1,IR_TMR1_OVI1, +IR_TMR2_CMIA2,IR_TMR2_CMIB2,IR_TMR2_OVI2, +IR_TMR3_CMIA3,IR_TMR3_CMIB3,IR_TMR3_OVI3, +IR_DMAC_DMAC0I=198,IR_DMAC_DMAC1I,IR_DMAC_DMAC2I,IR_DMAC_DMAC3I, +IR_SCI0_ERI0=214,IR_SCI0_RXI0,IR_SCI0_TXI0,IR_SCI0_TEI0, +IR_SCI1_ERI1,IR_SCI1_RXI1,IR_SCI1_TXI1,IR_SCI1_TEI1, +IR_SCI5_ERI5,IR_SCI5_RXI5,IR_SCI5_TXI5,IR_SCI5_TEI5, +IR_SCI6_ERI6,IR_SCI6_RXI6,IR_SCI6_TXI6,IR_SCI6_TEI6, +IR_SCI8_ERI8,IR_SCI8_RXI8,IR_SCI8_TXI8,IR_SCI8_TEI8, +IR_SCI9_ERI9,IR_SCI9_RXI9,IR_SCI9_TXI9,IR_SCI9_TEI9, +IR_SCI12_ERI12,IR_SCI12_RXI12,IR_SCI12_TXI12,IR_SCI12_TEI12,IR_SCI12_SCIX0,IR_SCI12_SCIX1,IR_SCI12_SCIX2,IR_SCI12_SCIX3, +IR_RIIC0_EEI0,IR_RIIC0_RXI0,IR_RIIC0_TXI0,IR_RIIC0_TEI0 +}; + +enum enum_dtce { +DTCE_ICU_SWINT=27, +DTCE_CMT0_CMI0,DTCE_CMT1_CMI1, +DTCE_CMT2_CMI2,DTCE_CMT3_CMI3, +DTCE_USB0_D0FIFO0=36,DTCE_USB0_D1FIFO0, +DTCE_SDHI_SBFAI=40, +DTCE_RSPI0_SPRI0=45,DTCE_RSPI0_SPTI0, +DTCE_RSCAN_COMFRXINT=52, +DTCE_CMPB_CMPB0=58,DTCE_CMPB_CMPB1, +DTCE_CTSU_CTSUWR,DTCE_CTSU_CTSURD, +DTCE_ICU_IRQ0=64,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7, +DTCE_S12AD_S12ADI0=102,DTCE_S12AD_GBADI, +DTCE_CMPB1_CMPB2,DTCE_CMPB1_CMPB3, +DTCE_ELC_ELSR18I,DTCE_ELC_ELSR19I, +DTCE_SSI0_SSIRXI0=109,DTCE_SSI0_SSITXI0, +DTCE_SECURITY_RD,DTCE_SECURITY_WR, +DTCE_MTU0_TGIA0=114,DTCE_MTU0_TGIB0,DTCE_MTU0_TGIC0,DTCE_MTU0_TGID0, +DTCE_MTU1_TGIA1=121,DTCE_MTU1_TGIB1, +DTCE_MTU2_TGIA2=125,DTCE_MTU2_TGIB2, +DTCE_MTU3_TGIA3=129,DTCE_MTU3_TGIB3,DTCE_MTU3_TGIC3,DTCE_MTU3_TGID3, +DTCE_MTU4_TGIA4=134,DTCE_MTU4_TGIB4,DTCE_MTU4_TGIC4,DTCE_MTU4_TGID4,DTCE_MTU4_TCIV4, +DTCE_MTU5_TGIU5,DTCE_MTU5_TGIV5,DTCE_MTU5_TGIW5, +DTCE_TPU0_TGI0A,DTCE_TPU0_TGI0B,DTCE_TPU0_TGI0C,DTCE_TPU0_TGI0D, +DTCE_TPU1_TGI1A=147,DTCE_TPU1_TGI1B, +DTCE_TPU2_TGI2A=151,DTCE_TPU2_TGI2B, +DTCE_TPU3_TGI3A=155,DTCE_TPU3_TGI3B,DTCE_TPU3_TGI3C,DTCE_TPU3_TGI3D, +DTCE_TPU4_TGI4A=160,DTCE_TPU4_TGI4B, +DTCE_TPU5_TGI5A=164,DTCE_TPU5_TGI5B, +DTCE_TMR0_CMIA0=174,DTCE_TMR0_CMIB0, +DTCE_TMR1_CMIA1=177,DTCE_TMR1_CMIB1, +DTCE_TMR2_CMIA2=180,DTCE_TMR2_CMIB2, +DTCE_TMR3_CMIA3=183,DTCE_TMR3_CMIB3, +DTCE_DMAC_DMAC0I=198,DTCE_DMAC_DMAC1I,DTCE_DMAC_DMAC2I,DTCE_DMAC_DMAC3I, +DTCE_SCI0_RXI0=215,DTCE_SCI0_TXI0, +DTCE_SCI1_RXI1=219,DTCE_SCI1_TXI1, +DTCE_SCI5_RXI5=223,DTCE_SCI5_TXI5, +DTCE_SCI6_RXI6=227,DTCE_SCI6_TXI6, +DTCE_SCI8_RXI8=231,DTCE_SCI8_TXI8, +DTCE_SCI9_RXI9=235,DTCE_SCI9_TXI9, +DTCE_SCI12_RXI12=239,DTCE_SCI12_TXI12, +DTCE_RIIC0_RXI0=247,DTCE_RIIC0_TXI0 +}; + +enum enum_ier { +IER_BSC_BUSERR=0x02, +IER_FCU_FRDYI=0x02, +IER_ICU_SWINT=0x03, +IER_CMT0_CMI0=0x03,IER_CMT1_CMI1=0x03, +IER_CMT2_CMI2=0x03,IER_CMT3_CMI3=0x03, +IER_CAC_FERRF=0x04,IER_CAC_MENDF=0x04,IER_CAC_OVFF=0x04, +IER_USB0_D0FIFO0=0x04,IER_USB0_D1FIFO0=0x04,IER_USB0_USBI0=0x04, +IER_SDHI_SBFAI=0x05,IER_SDHI_CDETI=0x05,IER_SDHI_CACI=0x05,IER_SDHI_SDACI=0x05, +IER_RSPI0_SPEI0=0x05,IER_RSPI0_SPRI0=0x05,IER_RSPI0_SPTI0=0x05,IER_RSPI0_SPII0=0x05, +IER_RSCAN_COMFRXINT=0x06,IER_RSCAN_RXFINT=0x06,IER_RSCAN_TXINT=0x06,IER_RSCAN_CHERRINT=0x06,IER_RSCAN_GLERRINT=0x07, +IER_DOC_DOPCF=0x07, +IER_CMPB_CMPB0=0x07,IER_CMPB_CMPB1=0x07, +IER_CTSU_CTSUWR=0x07,IER_CTSU_CTSURD=0x07,IER_CTSU_CTSUFN=0x07, +IER_RTC_CUP=0x07, +IER_ICU_IRQ0=0x08,IER_ICU_IRQ1=0x08,IER_ICU_IRQ2=0x08,IER_ICU_IRQ3=0x08,IER_ICU_IRQ4=0x08,IER_ICU_IRQ5=0x08,IER_ICU_IRQ6=0x08,IER_ICU_IRQ7=0x08, +IER_ELC_ELSR8I=0x0A, +IER_LVD_LVD1=0x0B,IER_LVD_LVD2=0x0B, +IER_CMPA_CMPA1=0x0B,IER_CMPA_CMPA2=0x0B, +IER_USB0_USBR0=0x0B, +IER_VBATT_VBTLVDI=0x0B, +IER_RTC_ALM=0x0B,IER_RTC_PRD=0x0B, +IER_S12AD_S12ADI0=0x0C,IER_S12AD_GBADI=0x0C, +IER_CMPB1_CMPB2=0x0D,IER_CMPB1_CMPB3=0x0D, +IER_ELC_ELSR18I=0x0D,IER_ELC_ELSR19I=0x0D, +IER_SSI0_SSIF0=0x0D,IER_SSI0_SSIRXI0=0x0D,IER_SSI0_SSITXI0=0x0D, +IER_SECURITY_RD=0x0D,IER_SECURITY_WR=0x0E,IER_SECURITY_ERR=0x0E, +IER_MTU0_TGIA0=0x0E,IER_MTU0_TGIB0=0x0E,IER_MTU0_TGIC0=0x0E,IER_MTU0_TGID0=0x0E,IER_MTU0_TCIV0=0x0E,IER_MTU0_TGIE0=0x0E,IER_MTU0_TGIF0=0x0F, +IER_MTU1_TGIA1=0x0F,IER_MTU1_TGIB1=0x0F,IER_MTU1_TCIV1=0x0F,IER_MTU1_TCIU1=0x0F, +IER_MTU2_TGIA2=0x0F,IER_MTU2_TGIB2=0x0F,IER_MTU2_TCIV2=0x0F,IER_MTU2_TCIU2=0x10, +IER_MTU3_TGIA3=0x10,IER_MTU3_TGIB3=0x10,IER_MTU3_TGIC3=0x10,IER_MTU3_TGID3=0x10,IER_MTU3_TCIV3=0x10, +IER_MTU4_TGIA4=0x10,IER_MTU4_TGIB4=0x10,IER_MTU4_TGIC4=0x11,IER_MTU4_TGID4=0x11,IER_MTU4_TCIV4=0x11, +IER_MTU5_TGIU5=0x11,IER_MTU5_TGIV5=0x11,IER_MTU5_TGIW5=0x11, +IER_TPU0_TGI0A=0x11,IER_TPU0_TGI0B=0x11,IER_TPU0_TGI0C=0x12,IER_TPU0_TGI0D=0x12,IER_TPU0_TCI0V=0x12, +IER_TPU1_TGI1A=0x12,IER_TPU1_TGI1B=0x12,IER_TPU1_TCI1V=0x12,IER_TPU1_TCI1U=0x12, +IER_TPU2_TGI2A=0x12,IER_TPU2_TGI2B=0x13,IER_TPU2_TCI2V=0x13,IER_TPU2_TCI2U=0x13, +IER_TPU3_TGI3A=0x13,IER_TPU3_TGI3B=0x13,IER_TPU3_TGI3C=0x13,IER_TPU3_TGI3D=0x13,IER_TPU3_TCI3V=0x13, +IER_TPU4_TGI4A=0x14,IER_TPU4_TGI4B=0x14,IER_TPU4_TCI4V=0x14,IER_TPU4_TCI4U=0x14, +IER_TPU5_TGI5A=0x14,IER_TPU5_TGI5B=0x14,IER_TPU5_TCI5V=0x14,IER_TPU5_TCI5U=0x14, +IER_POE_OEI1=0x15,IER_POE_OEI2=0x15, +IER_TMR0_CMIA0=0x15,IER_TMR0_CMIB0=0x15,IER_TMR0_OVI0=0x16, +IER_TMR1_CMIA1=0x16,IER_TMR1_CMIB1=0x16,IER_TMR1_OVI1=0x16, +IER_TMR2_CMIA2=0x16,IER_TMR2_CMIB2=0x16,IER_TMR2_OVI2=0x16, +IER_TMR3_CMIA3=0x16,IER_TMR3_CMIB3=0x17,IER_TMR3_OVI3=0x17, +IER_DMAC_DMAC0I=0x18,IER_DMAC_DMAC1I=0x18,IER_DMAC_DMAC2I=0x19,IER_DMAC_DMAC3I=0x19, +IER_SCI0_ERI0=0x1A,IER_SCI0_RXI0=0x1A,IER_SCI0_TXI0=0x1B,IER_SCI0_TEI0=0x1B, +IER_SCI1_ERI1=0x1B,IER_SCI1_RXI1=0x1B,IER_SCI1_TXI1=0x1B,IER_SCI1_TEI1=0x1B, +IER_SCI5_ERI5=0x1B,IER_SCI5_RXI5=0x1B,IER_SCI5_TXI5=0x1C,IER_SCI5_TEI5=0x1C, +IER_SCI6_ERI6=0x1C,IER_SCI6_RXI6=0x1C,IER_SCI6_TXI6=0x1C,IER_SCI6_TEI6=0x1C, +IER_SCI8_ERI8=0x1C,IER_SCI8_RXI8=0x1C,IER_SCI8_TXI8=0x1D,IER_SCI8_TEI8=0x1D, +IER_SCI9_ERI9=0x1D,IER_SCI9_RXI9=0x1D,IER_SCI9_TXI9=0x1D,IER_SCI9_TEI9=0x1D, +IER_SCI12_ERI12=0x1D,IER_SCI12_RXI12=0x1D,IER_SCI12_TXI12=0x1E,IER_SCI12_TEI12=0x1E,IER_SCI12_SCIX0=0x1E,IER_SCI12_SCIX1=0x1E,IER_SCI12_SCIX2=0x1E,IER_SCI12_SCIX3=0x1E, +IER_RIIC0_EEI0=0x1E,IER_RIIC0_RXI0=0x1E,IER_RIIC0_TXI0=0x1F,IER_RIIC0_TEI0=0x1F +}; + +enum enum_ipr { +IPR_BSC_BUSERR=0, +IPR_FCU_FRDYI=2, +IPR_ICU_SWINT=3, +IPR_CMT0_CMI0=4,IPR_CMT1_CMI1=5, +IPR_CMT2_CMI2=6,IPR_CMT3_CMI3=7, +IPR_CAC_FERRF=32,IPR_CAC_MENDF=33,IPR_CAC_OVFF=34, +IPR_USB0_D0FIFO0=36,IPR_USB0_D1FIFO0=37,IPR_USB0_USBI0=38, +IPR_SDHI_SBFAI=40,IPR_SDHI_CDETI=41,IPR_SDHI_CACI=42,IPR_SDHI_SDACI=43, +IPR_RSPI0_SPEI0=44,IPR_RSPI0_SPRI0=44,IPR_RSPI0_SPTI0=44,IPR_RSPI0_SPII0=44, +IPR_RSCAN_COMFRXINT=52,IPR_RSCAN_RXFINT=53,IPR_RSCAN_TXINT=54,IPR_RSCAN_CHERRINT=55,IPR_RSCAN_GLERRINT=56, +IPR_DOC_DOPCF=57, +IPR_CMPB_CMPB0=58,IPR_CMPB_CMPB1=59, +IPR_CTSU_CTSUWR=60,IPR_CTSU_CTSURD=60,IPR_CTSU_CTSUFN=60, +IPR_RTC_CUP=63, +IPR_ICU_IRQ0=64,IPR_ICU_IRQ1=65,IPR_ICU_IRQ2=66,IPR_ICU_IRQ3=67,IPR_ICU_IRQ4=68,IPR_ICU_IRQ5=69,IPR_ICU_IRQ6=70,IPR_ICU_IRQ7=71, +IPR_ELC_ELSR8I=80, +IPR_LVD_LVD1=88,IPR_LVD_LVD2=89, +IPR_CMPA_CMPA1=88,IPR_CMPA_CMPA2=89, +IPR_USB0_USBR0=90, +IPR_VBATT_VBTLVDI=91, +IPR_RTC_ALM=92,IPR_RTC_PRD=93, +IPR_S12AD_S12ADI0=102,IPR_S12AD_GBADI=103, +IPR_CMPB1_CMPB2=104,IPR_CMPB1_CMPB3=105, +IPR_ELC_ELSR18I=106,IPR_ELC_ELSR19I=107, +IPR_SSI0_SSIF0=108,IPR_SSI0_SSIRXI0=108,IPR_SSI0_SSITXI0=108, +IPR_SECURITY_RD=111,IPR_SECURITY_WR=111,IPR_SECURITY_ERR=113, +IPR_MTU0_TGIA0=114,IPR_MTU0_TGIB0=114,IPR_MTU0_TGIC0=114,IPR_MTU0_TGID0=114,IPR_MTU0_TCIV0=118,IPR_MTU0_TGIE0=118,IPR_MTU0_TGIF0=118, +IPR_MTU1_TGIA1=121,IPR_MTU1_TGIB1=121,IPR_MTU1_TCIV1=123,IPR_MTU1_TCIU1=123, +IPR_MTU2_TGIA2=125,IPR_MTU2_TGIB2=125,IPR_MTU2_TCIV2=127,IPR_MTU2_TCIU2=127, +IPR_MTU3_TGIA3=129,IPR_MTU3_TGIB3=129,IPR_MTU3_TGIC3=129,IPR_MTU3_TGID3=129,IPR_MTU3_TCIV3=133, +IPR_MTU4_TGIA4=134,IPR_MTU4_TGIB4=134,IPR_MTU4_TGIC4=134,IPR_MTU4_TGID4=134,IPR_MTU4_TCIV4=138, +IPR_MTU5_TGIU5=139,IPR_MTU5_TGIV5=139,IPR_MTU5_TGIW5=139, +IPR_TPU0_TGI0A=142,IPR_TPU0_TGI0B=142,IPR_TPU0_TGI0C=142,IPR_TPU0_TGI0D=142,IPR_TPU0_TCI0V=146, +IPR_TPU1_TGI1A=147,IPR_TPU1_TGI1B=147,IPR_TPU1_TCI1V=149,IPR_TPU1_TCI1U=149, +IPR_TPU2_TGI2A=151,IPR_TPU2_TGI2B=151,IPR_TPU2_TCI2V=153,IPR_TPU2_TCI2U=153, +IPR_TPU3_TGI3A=155,IPR_TPU3_TGI3B=155,IPR_TPU3_TGI3C=155,IPR_TPU3_TGI3D=155,IPR_TPU3_TCI3V=159, +IPR_TPU4_TGI4A=160,IPR_TPU4_TGI4B=160,IPR_TPU4_TCI4V=162,IPR_TPU4_TCI4U=162, +IPR_TPU5_TGI5A=164,IPR_TPU5_TGI5B=164,IPR_TPU5_TCI5V=166,IPR_TPU5_TCI5U=166, +IPR_POE_OEI1=170,IPR_POE_OEI2=171, +IPR_TMR0_CMIA0=174,IPR_TMR0_CMIB0=174,IPR_TMR0_OVI0=174, +IPR_TMR1_CMIA1=177,IPR_TMR1_CMIB1=177,IPR_TMR1_OVI1=177, +IPR_TMR2_CMIA2=180,IPR_TMR2_CMIB2=180,IPR_TMR2_OVI2=180, +IPR_TMR3_CMIA3=183,IPR_TMR3_CMIB3=183,IPR_TMR3_OVI3=183, +IPR_DMAC_DMAC0I=198,IPR_DMAC_DMAC1I=199,IPR_DMAC_DMAC2I=200,IPR_DMAC_DMAC3I=201, +IPR_SCI0_ERI0=214,IPR_SCI0_RXI0=214,IPR_SCI0_TXI0=214,IPR_SCI0_TEI0=214, +IPR_SCI1_ERI1=218,IPR_SCI1_RXI1=218,IPR_SCI1_TXI1=218,IPR_SCI1_TEI1=218, +IPR_SCI5_ERI5=222,IPR_SCI5_RXI5=222,IPR_SCI5_TXI5=222,IPR_SCI5_TEI5=222, +IPR_SCI6_ERI6=226,IPR_SCI6_RXI6=226,IPR_SCI6_TXI6=226,IPR_SCI6_TEI6=226, +IPR_SCI8_ERI8=230,IPR_SCI8_RXI8=230,IPR_SCI8_TXI8=230,IPR_SCI8_TEI8=230, +IPR_SCI9_ERI9=234,IPR_SCI9_RXI9=234,IPR_SCI9_TXI9=234,IPR_SCI9_TEI9=234, +IPR_SCI12_ERI12=238,IPR_SCI12_RXI12=238,IPR_SCI12_TXI12=238,IPR_SCI12_TEI12=238,IPR_SCI12_SCIX0=242,IPR_SCI12_SCIX1=243,IPR_SCI12_SCIX2=244,IPR_SCI12_SCIX3=245, +IPR_RIIC0_EEI0=246,IPR_RIIC0_RXI0=247,IPR_RIIC0_TXI0=248,IPR_RIIC0_TEI0=249, +IPR_BSC_=0, +IPR_FCU_=2, +IPR_RSPI0_=44, +IPR_DOC_=57, +IPR_VBATT_=91, +IPR_MTU1_TGI=121, +IPR_MTU1_TCI=123, +IPR_MTU2_TGI=125, +IPR_MTU2_TCI=127, +IPR_MTU3_TGI=129, +IPR_MTU4_TGI=134, +IPR_MTU5_=139, +IPR_MTU5_TGI=139, +IPR_TPU0_TGI=142, +IPR_TPU1_TGI=147, +IPR_TPU1_TCI=149, +IPR_TPU2_TGI=151, +IPR_TPU2_TCI=153, +IPR_TPU3_TGI=155, +IPR_TPU4_TGI=160, +IPR_TPU4_TCI=162, +IPR_TPU5_TGI=164, +IPR_TPU5_TCI=166, +IPR_TMR0_=174, +IPR_TMR1_=177, +IPR_TMR2_=180, +IPR_TMR3_=183, +IPR_SCI0_=214, +IPR_SCI1_=218, +IPR_SCI5_=222, +IPR_SCI6_=226, +IPR_SCI8_=230, +IPR_SCI9_=234 +}; + +#define IEN_BSC_BUSERR IEN0 +#define IEN_FCU_FRDYI IEN7 +#define IEN_ICU_SWINT IEN3 +#define IEN_CMT0_CMI0 IEN4 +#define IEN_CMT1_CMI1 IEN5 +#define IEN_CMT2_CMI2 IEN6 +#define IEN_CMT3_CMI3 IEN7 +#define IEN_CAC_FERRF IEN0 +#define IEN_CAC_MENDF IEN1 +#define IEN_CAC_OVFF IEN2 +#define IEN_USB0_D0FIFO0 IEN4 +#define IEN_USB0_D1FIFO0 IEN5 +#define IEN_USB0_USBI0 IEN6 +#define IEN_SDHI_SBFAI IEN0 +#define IEN_SDHI_CDETI IEN1 +#define IEN_SDHI_CACI IEN2 +#define IEN_SDHI_SDACI IEN3 +#define IEN_RSPI0_SPEI0 IEN4 +#define IEN_RSPI0_SPRI0 IEN5 +#define IEN_RSPI0_SPTI0 IEN6 +#define IEN_RSPI0_SPII0 IEN7 +#define IEN_RSCAN_COMFRXINT IEN4 +#define IEN_RSCAN_RXFINT IEN5 +#define IEN_RSCAN_TXINT IEN6 +#define IEN_RSCAN_CHERRINT IEN7 +#define IEN_RSCAN_GLERRINT IEN0 +#define IEN_DOC_DOPCF IEN1 +#define IEN_CMPB_CMPB0 IEN2 +#define IEN_CMPB_CMPB1 IEN3 +#define IEN_CTSU_CTSUWR IEN4 +#define IEN_CTSU_CTSURD IEN5 +#define IEN_CTSU_CTSUFN IEN6 +#define IEN_RTC_CUP IEN7 +#define IEN_ICU_IRQ0 IEN0 +#define IEN_ICU_IRQ1 IEN1 +#define IEN_ICU_IRQ2 IEN2 +#define IEN_ICU_IRQ3 IEN3 +#define IEN_ICU_IRQ4 IEN4 +#define IEN_ICU_IRQ5 IEN5 +#define IEN_ICU_IRQ6 IEN6 +#define IEN_ICU_IRQ7 IEN7 +#define IEN_ELC_ELSR8I IEN0 +#define IEN_LVD_LVD1 IEN0 +#define IEN_LVD_LVD2 IEN1 +#define IEN_CMPA_CMPA1 IEN0 +#define IEN_CMPA_CMPA2 IEN1 +#define IEN_USB0_USBR0 IEN2 +#define IEN_VBATT_VBTLVDI IEN3 +#define IEN_RTC_ALM IEN4 +#define IEN_RTC_PRD IEN5 +#define IEN_S12AD_S12ADI0 IEN6 +#define IEN_S12AD_GBADI IEN7 +#define IEN_CMPB1_CMPB2 IEN0 +#define IEN_CMPB1_CMPB3 IEN1 +#define IEN_ELC_ELSR18I IEN2 +#define IEN_ELC_ELSR19I IEN3 +#define IEN_SSI0_SSIF0 IEN4 +#define IEN_SSI0_SSIRXI0 IEN5 +#define IEN_SSI0_SSITXI0 IEN6 +#define IEN_SECURITY_RD IEN7 +#define IEN_SECURITY_WR IEN0 +#define IEN_SECURITY_ERR IEN1 +#define IEN_MTU0_TGIA0 IEN2 +#define IEN_MTU0_TGIB0 IEN3 +#define IEN_MTU0_TGIC0 IEN4 +#define IEN_MTU0_TGID0 IEN5 +#define IEN_MTU0_TCIV0 IEN6 +#define IEN_MTU0_TGIE0 IEN7 +#define IEN_MTU0_TGIF0 IEN0 +#define IEN_MTU1_TGIA1 IEN1 +#define IEN_MTU1_TGIB1 IEN2 +#define IEN_MTU1_TCIV1 IEN3 +#define IEN_MTU1_TCIU1 IEN4 +#define IEN_MTU2_TGIA2 IEN5 +#define IEN_MTU2_TGIB2 IEN6 +#define IEN_MTU2_TCIV2 IEN7 +#define IEN_MTU2_TCIU2 IEN0 +#define IEN_MTU3_TGIA3 IEN1 +#define IEN_MTU3_TGIB3 IEN2 +#define IEN_MTU3_TGIC3 IEN3 +#define IEN_MTU3_TGID3 IEN4 +#define IEN_MTU3_TCIV3 IEN5 +#define IEN_MTU4_TGIA4 IEN6 +#define IEN_MTU4_TGIB4 IEN7 +#define IEN_MTU4_TGIC4 IEN0 +#define IEN_MTU4_TGID4 IEN1 +#define IEN_MTU4_TCIV4 IEN2 +#define IEN_MTU5_TGIU5 IEN3 +#define IEN_MTU5_TGIV5 IEN4 +#define IEN_MTU5_TGIW5 IEN5 +#define IEN_TPU0_TGI0A IEN6 +#define IEN_TPU0_TGI0B IEN7 +#define IEN_TPU0_TGI0C IEN0 +#define IEN_TPU0_TGI0D IEN1 +#define IEN_TPU0_TCI0V IEN2 +#define IEN_TPU1_TGI1A IEN3 +#define IEN_TPU1_TGI1B IEN4 +#define IEN_TPU1_TCI1V IEN5 +#define IEN_TPU1_TCI1U IEN6 +#define IEN_TPU2_TGI2A IEN7 +#define IEN_TPU2_TGI2B IEN0 +#define IEN_TPU2_TCI2V IEN1 +#define IEN_TPU2_TCI2U IEN2 +#define IEN_TPU3_TGI3A IEN3 +#define IEN_TPU3_TGI3B IEN4 +#define IEN_TPU3_TGI3C IEN5 +#define IEN_TPU3_TGI3D IEN6 +#define IEN_TPU3_TCI3V IEN7 +#define IEN_TPU4_TGI4A IEN0 +#define IEN_TPU4_TGI4B IEN1 +#define IEN_TPU4_TCI4V IEN2 +#define IEN_TPU4_TCI4U IEN3 +#define IEN_TPU5_TGI5A IEN4 +#define IEN_TPU5_TGI5B IEN5 +#define IEN_TPU5_TCI5V IEN6 +#define IEN_TPU5_TCI5U IEN7 +#define IEN_POE_OEI1 IEN2 +#define IEN_POE_OEI2 IEN3 +#define IEN_TMR0_CMIA0 IEN6 +#define IEN_TMR0_CMIB0 IEN7 +#define IEN_TMR0_OVI0 IEN0 +#define IEN_TMR1_CMIA1 IEN1 +#define IEN_TMR1_CMIB1 IEN2 +#define IEN_TMR1_OVI1 IEN3 +#define IEN_TMR2_CMIA2 IEN4 +#define IEN_TMR2_CMIB2 IEN5 +#define IEN_TMR2_OVI2 IEN6 +#define IEN_TMR3_CMIA3 IEN7 +#define IEN_TMR3_CMIB3 IEN0 +#define IEN_TMR3_OVI3 IEN1 +#define IEN_DMAC_DMAC0I IEN6 +#define IEN_DMAC_DMAC1I IEN7 +#define IEN_DMAC_DMAC2I IEN0 +#define IEN_DMAC_DMAC3I IEN1 +#define IEN_SCI0_ERI0 IEN6 +#define IEN_SCI0_RXI0 IEN7 +#define IEN_SCI0_TXI0 IEN0 +#define IEN_SCI0_TEI0 IEN1 +#define IEN_SCI1_ERI1 IEN2 +#define IEN_SCI1_RXI1 IEN3 +#define IEN_SCI1_TXI1 IEN4 +#define IEN_SCI1_TEI1 IEN5 +#define IEN_SCI5_ERI5 IEN6 +#define IEN_SCI5_RXI5 IEN7 +#define IEN_SCI5_TXI5 IEN0 +#define IEN_SCI5_TEI5 IEN1 +#define IEN_SCI6_ERI6 IEN2 +#define IEN_SCI6_RXI6 IEN3 +#define IEN_SCI6_TXI6 IEN4 +#define IEN_SCI6_TEI6 IEN5 +#define IEN_SCI8_ERI8 IEN6 +#define IEN_SCI8_RXI8 IEN7 +#define IEN_SCI8_TXI8 IEN0 +#define IEN_SCI8_TEI8 IEN1 +#define IEN_SCI9_ERI9 IEN2 +#define IEN_SCI9_RXI9 IEN3 +#define IEN_SCI9_TXI9 IEN4 +#define IEN_SCI9_TEI9 IEN5 +#define IEN_SCI12_ERI12 IEN6 +#define IEN_SCI12_RXI12 IEN7 +#define IEN_SCI12_TXI12 IEN0 +#define IEN_SCI12_TEI12 IEN1 +#define IEN_SCI12_SCIX0 IEN2 +#define IEN_SCI12_SCIX1 IEN3 +#define IEN_SCI12_SCIX2 IEN4 +#define IEN_SCI12_SCIX3 IEN5 +#define IEN_RIIC0_EEI0 IEN6 +#define IEN_RIIC0_RXI0 IEN7 +#define IEN_RIIC0_TXI0 IEN0 +#define IEN_RIIC0_TEI0 IEN1 + +#define VECT_BSC_BUSERR 16 +#define VECT_FCU_FRDYI 23 +#define VECT_ICU_SWINT 27 +#define VECT_CMT0_CMI0 28 +#define VECT_CMT1_CMI1 29 +#define VECT_CMT2_CMI2 30 +#define VECT_CMT3_CMI3 31 +#define VECT_CAC_FERRF 32 +#define VECT_CAC_MENDF 33 +#define VECT_CAC_OVFF 34 +#define VECT_USB0_D0FIFO0 36 +#define VECT_USB0_D1FIFO0 37 +#define VECT_USB0_USBI0 38 +#define VECT_SDHI_SBFAI 40 +#define VECT_SDHI_CDETI 41 +#define VECT_SDHI_CACI 42 +#define VECT_SDHI_SDACI 43 +#define VECT_RSPI0_SPEI0 44 +#define VECT_RSPI0_SPRI0 45 +#define VECT_RSPI0_SPTI0 46 +#define VECT_RSPI0_SPII0 47 +#define VECT_RSCAN_COMFRXINT 52 +#define VECT_RSCAN_RXFINT 53 +#define VECT_RSCAN_TXINT 54 +#define VECT_RSCAN_CHERRINT 55 +#define VECT_RSCAN_GLERRINT 56 +#define VECT_DOC_DOPCF 57 +#define VECT_CMPB_CMPB0 58 +#define VECT_CMPB_CMPB1 59 +#define VECT_CTSU_CTSUWR 60 +#define VECT_CTSU_CTSURD 61 +#define VECT_CTSU_CTSUFN 62 +#define VECT_RTC_CUP 63 +#define VECT_ICU_IRQ0 64 +#define VECT_ICU_IRQ1 65 +#define VECT_ICU_IRQ2 66 +#define VECT_ICU_IRQ3 67 +#define VECT_ICU_IRQ4 68 +#define VECT_ICU_IRQ5 69 +#define VECT_ICU_IRQ6 70 +#define VECT_ICU_IRQ7 71 +#define VECT_ELC_ELSR8I 80 +#define VECT_LVD_LVD1 88 +#define VECT_LVD_LVD2 89 +#define VECT_CMPA_CMPA1 88 +#define VECT_CMPA_CMPA2 89 +#define VECT_USB0_USBR0 90 +#define VECT_VBATT_VBTLVDI 91 +#define VECT_RTC_ALM 92 +#define VECT_RTC_PRD 93 +#define VECT_S12AD_S12ADI0 102 +#define VECT_S12AD_GBADI 103 +#define VECT_CMPB1_CMPB2 104 +#define VECT_CMPB1_CMPB3 105 +#define VECT_ELC_ELSR18I 106 +#define VECT_ELC_ELSR19I 107 +#define VECT_SSI0_SSIF0 108 +#define VECT_SSI0_SSIRXI0 109 +#define VECT_SSI0_SSITXI0 110 +#define VECT_SECURITY_RD 111 +#define VECT_SECURITY_WR 112 +#define VECT_SECURITY_ERR 113 +#define VECT_MTU0_TGIA0 114 +#define VECT_MTU0_TGIB0 115 +#define VECT_MTU0_TGIC0 116 +#define VECT_MTU0_TGID0 117 +#define VECT_MTU0_TCIV0 118 +#define VECT_MTU0_TGIE0 119 +#define VECT_MTU0_TGIF0 120 +#define VECT_MTU1_TGIA1 121 +#define VECT_MTU1_TGIB1 122 +#define VECT_MTU1_TCIV1 123 +#define VECT_MTU1_TCIU1 124 +#define VECT_MTU2_TGIA2 125 +#define VECT_MTU2_TGIB2 126 +#define VECT_MTU2_TCIV2 127 +#define VECT_MTU2_TCIU2 128 +#define VECT_MTU3_TGIA3 129 +#define VECT_MTU3_TGIB3 130 +#define VECT_MTU3_TGIC3 131 +#define VECT_MTU3_TGID3 132 +#define VECT_MTU3_TCIV3 133 +#define VECT_MTU4_TGIA4 134 +#define VECT_MTU4_TGIB4 135 +#define VECT_MTU4_TGIC4 136 +#define VECT_MTU4_TGID4 137 +#define VECT_MTU4_TCIV4 138 +#define VECT_MTU5_TGIU5 139 +#define VECT_MTU5_TGIV5 140 +#define VECT_MTU5_TGIW5 141 +#define VECT_TPU0_TGI0A 142 +#define VECT_TPU0_TGI0B 143 +#define VECT_TPU0_TGI0C 144 +#define VECT_TPU0_TGI0D 145 +#define VECT_TPU0_TCI0V 146 +#define VECT_TPU1_TGI1A 147 +#define VECT_TPU1_TGI1B 148 +#define VECT_TPU1_TCI1V 149 +#define VECT_TPU1_TCI1U 150 +#define VECT_TPU2_TGI2A 151 +#define VECT_TPU2_TGI2B 152 +#define VECT_TPU2_TCI2V 153 +#define VECT_TPU2_TCI2U 154 +#define VECT_TPU3_TGI3A 155 +#define VECT_TPU3_TGI3B 156 +#define VECT_TPU3_TGI3C 157 +#define VECT_TPU3_TGI3D 158 +#define VECT_TPU3_TCI3V 159 +#define VECT_TPU4_TGI4A 160 +#define VECT_TPU4_TGI4B 161 +#define VECT_TPU4_TCI4V 162 +#define VECT_TPU4_TCI4U 163 +#define VECT_TPU5_TGI5A 164 +#define VECT_TPU5_TGI5B 165 +#define VECT_TPU5_TCI5V 166 +#define VECT_TPU5_TCI5U 167 +#define VECT_POE_OEI1 170 +#define VECT_POE_OEI2 171 +#define VECT_TMR0_CMIA0 174 +#define VECT_TMR0_CMIB0 175 +#define VECT_TMR0_OVI0 176 +#define VECT_TMR1_CMIA1 177 +#define VECT_TMR1_CMIB1 178 +#define VECT_TMR1_OVI1 179 +#define VECT_TMR2_CMIA2 180 +#define VECT_TMR2_CMIB2 181 +#define VECT_TMR2_OVI2 182 +#define VECT_TMR3_CMIA3 183 +#define VECT_TMR3_CMIB3 184 +#define VECT_TMR3_OVI3 185 +#define VECT_DMAC_DMAC0I 198 +#define VECT_DMAC_DMAC1I 199 +#define VECT_DMAC_DMAC2I 200 +#define VECT_DMAC_DMAC3I 201 +#define VECT_SCI0_ERI0 214 +#define VECT_SCI0_RXI0 215 +#define VECT_SCI0_TXI0 216 +#define VECT_SCI0_TEI0 217 +#define VECT_SCI1_ERI1 218 +#define VECT_SCI1_RXI1 219 +#define VECT_SCI1_TXI1 220 +#define VECT_SCI1_TEI1 221 +#define VECT_SCI5_ERI5 222 +#define VECT_SCI5_RXI5 223 +#define VECT_SCI5_TXI5 224 +#define VECT_SCI5_TEI5 225 +#define VECT_SCI6_ERI6 226 +#define VECT_SCI6_RXI6 227 +#define VECT_SCI6_TXI6 228 +#define VECT_SCI6_TEI6 229 +#define VECT_SCI8_ERI8 230 +#define VECT_SCI8_RXI8 231 +#define VECT_SCI8_TXI8 232 +#define VECT_SCI8_TEI8 233 +#define VECT_SCI9_ERI9 234 +#define VECT_SCI9_RXI9 235 +#define VECT_SCI9_TXI9 236 +#define VECT_SCI9_TEI9 237 +#define VECT_SCI12_ERI12 238 +#define VECT_SCI12_RXI12 239 +#define VECT_SCI12_TXI12 240 +#define VECT_SCI12_TEI12 241 +#define VECT_SCI12_SCIX0 242 +#define VECT_SCI12_SCIX1 243 +#define VECT_SCI12_SCIX2 244 +#define VECT_SCI12_SCIX3 245 +#define VECT_RIIC0_EEI0 246 +#define VECT_RIIC0_RXI0 247 +#define VECT_RIIC0_TXI0 248 +#define VECT_RIIC0_TEI0 249 + +#define MSTP_DMAC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC0 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC1 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC2 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC3 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DTC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DA SYSTEM.MSTPCRA.BIT.MSTPA19 +#define MSTP_S12AD SYSTEM.MSTPCRA.BIT.MSTPA17 +#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_CMT3 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_TPU SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU0 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU1 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU2 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU3 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU4 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU5 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_MTU SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU0 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU1 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU2 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU4 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU5 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_TMR0 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR1 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR01 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR2 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR3 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR23 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_SCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SMCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SMCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SMCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_SMCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_CRC SYSTEM.MSTPCRB.BIT.MSTPB23 +#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPB21 +#define MSTP_USB0 SYSTEM.MSTPCRB.BIT.MSTPB19 +#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPB17 +#define MSTP_CMPB SYSTEM.MSTPCRB.BIT.MSTPB10 +#define MSTP_ELC SYSTEM.MSTPCRB.BIT.MSTPB9 +#define MSTP_DOC SYSTEM.MSTPCRB.BIT.MSTPB6 +#define MSTP_SCI12 SYSTEM.MSTPCRB.BIT.MSTPB4 +#define MSTP_SMCI12 SYSTEM.MSTPCRB.BIT.MSTPB4 +#define MSTP_RSCAN SYSTEM.MSTPCRB.BIT.MSTPB0 +#define MSTP_RSCAN0 SYSTEM.MSTPCRB.BIT.MSTPB0 +#define MSTP_SCI8 SYSTEM.MSTPCRC.BIT.MSTPC27 +#define MSTP_SMCI8 SYSTEM.MSTPCRC.BIT.MSTPC27 +#define MSTP_SCI9 SYSTEM.MSTPCRC.BIT.MSTPC26 +#define MSTP_SMCI9 SYSTEM.MSTPCRC.BIT.MSTPC26 +#define MSTP_IRDA SYSTEM.MSTPCRC.BIT.MSTPC20 +#define MSTP_CAC SYSTEM.MSTPCRC.BIT.MSTPC19 +#define MSTP_RAM0 SYSTEM.MSTPCRC.BIT.MSTPC0 +#define MSTP_SDHI SYSTEM.MSTPCRD.BIT.MSTPD19 +#define MSTP_SSI0 SYSTEM.MSTPCRD.BIT.MSTPD15 +#define MSTP_CTSU SYSTEM.MSTPCRD.BIT.MSTPD10 + +#define __IR( x ) ICU.IR[ IR ## x ].BIT.IR +#define _IR( x ) __IR( x ) +#define IR( x , y ) _IR( _ ## x ## _ ## y ) +#define __DTCE( x ) ICU.DTCER[ DTCE ## x ].BIT.DTCE +#define _DTCE( x ) __DTCE( x ) +#define DTCE( x , y ) _DTCE( _ ## x ## _ ## y ) +#define __IEN( x ) ICU.IER[ IER ## x ].BIT.IEN ## x +#define _IEN( x ) __IEN( x ) +#define IEN( x , y ) _IEN( _ ## x ## _ ## y ) +#define __IPR( x ) ICU.IPR[ IPR ## x ].BIT.IPR +#define _IPR( x ) __IPR( x ) +#define IPR( x , y ) _IPR( _ ## x ## _ ## y ) +#define __VECT( x ) VECT ## x +#define _VECT( x ) __VECT( x ) +#define VECT( x , y ) _VECT( _ ## x ## _ ## y ) +#define __MSTP( x ) MSTP ## x +#define _MSTP( x ) __MSTP( x ) +#define MSTP( x ) _MSTP( _ ## x ) + +#define BSC (*(volatile struct st_bsc *)0x81300) +#define CAC (*(volatile struct st_cac *)0x8B000) +#define CMPB (*(volatile struct st_cmpb *)0x8C580) +#define CMT (*(volatile struct st_cmt *)0x88000) +#define CMT0 (*(volatile struct st_cmt0 *)0x88002) +#define CMT1 (*(volatile struct st_cmt0 *)0x88008) +#define CMT2 (*(volatile struct st_cmt0 *)0x88012) +#define CMT3 (*(volatile struct st_cmt0 *)0x88018) +#define CRC (*(volatile struct st_crc *)0x88280) +#define CTSU (*(volatile struct st_ctsu *)0xA0900) +#define DA (*(volatile struct st_da *)0x88040) +#define DMAC (*(volatile struct st_dmac *)0x82200) +#define DMAC0 (*(volatile struct st_dmac0 *)0x82000) +#define DMAC1 (*(volatile struct st_dmac1 *)0x82040) +#define DMAC2 (*(volatile struct st_dmac1 *)0x82080) +#define DMAC3 (*(volatile struct st_dmac1 *)0x820C0) +#define DOC (*(volatile struct st_doc *)0x8B080) +#define DTC (*(volatile struct st_dtc *)0x82400) +#define ELC (*(volatile struct st_elc *)0x8B100) +#define FLASH (*(volatile struct st_flash *)0x7FC090) +#define FLASHCONST (*(volatile struct st_flashconst *)0x7FC350) +#define ICU (*(volatile struct st_icu *)0x87000) +#define IRDA (*(volatile struct st_irda *)0x88410) +#define IWDT (*(volatile struct st_iwdt *)0x88030) +#define LPT (*(volatile struct st_lpt *)0x800B0) +#define MPC (*(volatile struct st_mpc *)0x8C100) +#define MPU (*(volatile struct st_mpu *)0x86400) +#define MTU (*(volatile struct st_mtu *)0xD0A0A) +#define MTU0 (*(volatile struct st_mtu0 *)0xD0A90) +#define MTU1 (*(volatile struct st_mtu1 *)0xD0A90) +#define MTU2 (*(volatile struct st_mtu2 *)0xD0A92) +#define MTU3 (*(volatile struct st_mtu3 *)0xD0A00) +#define MTU4 (*(volatile struct st_mtu4 *)0xD0A00) +#define MTU5 (*(volatile struct st_mtu5 *)0xD0A94) +#define POE (*(volatile struct st_poe *)0x88900) +#define PORT (*(volatile struct st_port *)0x8C120) +#define PORT0 (*(volatile struct st_port0 *)0x8C000) +#define PORT1 (*(volatile struct st_port1 *)0x8C001) +#define PORT2 (*(volatile struct st_port2 *)0x8C002) +#define PORT3 (*(volatile struct st_port3 *)0x8C003) +#define PORT4 (*(volatile struct st_port4 *)0x8C004) +#define PORT5 (*(volatile struct st_port5 *)0x8C005) +#define PORTA (*(volatile struct st_porta *)0x8C00A) +#define PORTB (*(volatile struct st_portb *)0x8C00B) +#define PORTC (*(volatile struct st_portc *)0x8C00C) +#define PORTD (*(volatile struct st_portd *)0x8C00D) +#define PORTE (*(volatile struct st_porte *)0x8C00E) +#define PORTH (*(volatile struct st_porth *)0x8C011) +#define PORTJ (*(volatile struct st_portj *)0x8C012) +#define RIIC0 (*(volatile struct st_riic *)0x88300) +#define RSCAN (*(volatile struct st_rscan *)0xA8322) +#define RSCAN0 (*(volatile struct st_rscan0 *)0xA8300) +#define RSPI0 (*(volatile struct st_rspi *)0x88380) +#define RTC (*(volatile struct st_rtc *)0x8C400) +#define S12AD (*(volatile struct st_s12ad *)0x89000) +#define SCI0 (*(volatile struct st_sci0 *)0x8A000) +#define SCI1 (*(volatile struct st_sci0 *)0x8A020) +#define SCI5 (*(volatile struct st_sci0 *)0x8A0A0) +#define SCI6 (*(volatile struct st_sci0 *)0x8A0C0) +#define SCI8 (*(volatile struct st_sci0 *)0x8A100) +#define SCI9 (*(volatile struct st_sci0 *)0x8A120) +#define SCI12 (*(volatile struct st_sci12 *)0x8B300) +#define SDHI (*(volatile struct st_sdhi *)0x8AC00) +#define SMCI0 (*(volatile struct st_smci *)0x8A000) +#define SMCI1 (*(volatile struct st_smci *)0x8A020) +#define SMCI2 (*(volatile struct st_smci *)0x8A040) +#define SMCI3 (*(volatile struct st_smci *)0x8A060) +#define SMCI4 (*(volatile struct st_smci *)0x8A080) +#define SMCI5 (*(volatile struct st_smci *)0x8A0A0) +#define SMCI6 (*(volatile struct st_smci *)0x8A0C0) +#define SMCI7 (*(volatile struct st_smci *)0x8A0E0) +#define SMCI8 (*(volatile struct st_smci *)0x8A100) +#define SMCI9 (*(volatile struct st_smci *)0x8A120) +#define SMCI10 (*(volatile struct st_smci *)0x8A140) +#define SMCI11 (*(volatile struct st_smci *)0x8A150) +#define SMCI12 (*(volatile struct st_smci *)0x8B300) +#define SSI0 (*(volatile struct st_ssi *)0x8A500) +#define SYSTEM (*(volatile struct st_system *)0x80000) +#define TEMPSCONST (*(volatile struct st_tempsconst *)0x7FC0A0) +#define TMR0 (*(volatile struct st_tmr0 *)0x88200) +#define TMR1 (*(volatile struct st_tmr1 *)0x88201) +#define TMR2 (*(volatile struct st_tmr0 *)0x88210) +#define TMR3 (*(volatile struct st_tmr1 *)0x88211) +#define TMR01 (*(volatile struct st_tmr01 *)0x88204) +#define TMR23 (*(volatile struct st_tmr01 *)0x88214) +#define TPU (*(volatile struct st_tpu *)0x88100) +#define TPU0 (*(volatile struct st_tpu0 *)0x88108) +#define TPU1 (*(volatile struct st_tpu1 *)0x88108) +#define TPU2 (*(volatile struct st_tpu2 *)0x8810A) +#define TPU3 (*(volatile struct st_tpu3 *)0x8810A) +#define TPU4 (*(volatile struct st_tpu4 *)0x8810C) +#define TPU5 (*(volatile struct st_tpu5 *)0x8810C) +#define USB0 (*(volatile struct st_usb0 *)0xA0000) +#define WDT (*(volatile struct st_wdt *)0x88020) + +#pragma pack() +#endif + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/main.c b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/main.c new file mode 100644 index 000000000..409c03775 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/main.c @@ -0,0 +1,251 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * This project provides two demo applications. A simple blinky style project, + * and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to + * select between the two. The simply blinky demo is implemented and described + * in main_blinky.c. The more comprehensive test and demo application is + * implemented and described in main_full.c. + * + * This file implements the code that is not demo specific, including the + * hardware setup, standard FreeRTOS hook functions, and the ISR hander called + * by the RTOS after interrupt entry (including nesting) has been taken care of. + * + * ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON + * THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO + * APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT! + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, +or 0 to run the more comprehensive test and demo application. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 + +/*-----------------------------------------------------------*/ + +/* + * Configure the hardware as necessary to run this demo. + */ +static void prvSetupHardware( void ); + +/* + * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. + * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. + */ +#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + extern void main_blinky( void ); +#else + extern void main_full( void ); +#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */ + +/* Prototypes for the standard FreeRTOS callback/hook functions implemented +within this file. */ +void vApplicationMallocFailedHook( void ); +void vApplicationIdleHook( void ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationTickHook( void ); + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Configure the hardware ready to run the demo. */ + prvSetupHardware(); + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + of this file. */ + #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + { + main_blinky(); + } + #else + { + main_full(); + } + #endif + + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ +/* Start user code. Do not edit comment generated here */ +uint16_t usProtectDummy = ( uint16_t ) ( SYSTEM.PRCR.WORD & 0x000FU ); + + /* Disable protect bit */ + SYSTEM.PRCR.WORD = 0xA50FU; + + SYSTEM.VBATTCR.BYTE = 0x81U; + + /* Restore the previous state of the protect register */ + SYSTEM.PRCR.WORD = ( uint16_t )( 0xA500U | usProtectDummy ); +} +/*-----------------------------------------------------------*/ + +void vApplicationMallocFailedHook( void ) +{ + /* Called if a call to pvPortMalloc() fails because there is insufficient + free memory available in the FreeRTOS heap. pvPortMalloc() is called + internally by FreeRTOS API functions that create tasks, queues, software + timers, and semaphores. The size of the FreeRTOS heap is set by the + configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); +} +/*-----------------------------------------------------------*/ + +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +{ + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + function is called if a stack overflow is detected. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ +volatile size_t xFreeHeapSpace; + + /* This is just a trivial example of an idle hook. It is called on each + cycle of the idle task. It must *NOT* attempt to block. In this case the + idle task just queries the amount of FreeRTOS heap that remains. See the + memory management section on the http://www.FreeRTOS.org web site for memory + management options. If there is a lot of heap memory free then the + configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up + RAM. */ + xFreeHeapSpace = xPortGetFreeHeapSize(); + + /* Remove compiler warning about xFreeHeapSpace being set but never used. */ + ( void ) xFreeHeapSpace; +} +/*-----------------------------------------------------------*/ + +void vApplicationTickHook( void ) +{ + #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 + { + extern void vFullDemoTickHook( void ); + + vFullDemoTickHook(); + } + #endif +} +/*-----------------------------------------------------------*/ + +/* The RX port uses this callback function to configure its tick interrupt. +This allows the application to choose the tick interrupt source. */ +void vApplicationSetupTimerInterrupt( void ) +{ +const uint32_t ulEnableRegisterWrite = 0xA50BUL, ulDisableRegisterWrite = 0xA500UL; + + /* Disable register write protection. */ + SYSTEM.PRCR.WORD = ulEnableRegisterWrite; + + /* Enable compare match timer 0. */ + MSTP( CMT0 ) = 0; + + /* Interrupt on compare match. */ + CMT0.CMCR.BIT.CMIE = 1; + + /* Set the compare match value. */ + CMT0.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) -1 ) / 8 ); + + /* Divide the PCLK by 8. */ + CMT0.CMCR.BIT.CKS = 0; + + /* Enable the interrupt... */ + _IEN( _CMT0_CMI0 ) = 1; + + /* ...and set its priority to the application defined kernel priority. */ + _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the timer. */ + CMT.CMSTR0.BIT.STR0 = 1; + + /* Reneable register protection. */ + SYSTEM.PRCR.WORD = ulDisableRegisterWrite; +} + + + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.HardwareDebuglinker b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.HardwareDebuglinker new file mode 100644 index 000000000..9eb2fea9d --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.HardwareDebuglinker @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.cproject b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.cproject new file mode 100644 index 000000000..5b2301311 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.cproject @@ -0,0 +1,157 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.info b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.info new file mode 100644 index 000000000..7a5b86fda --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.info @@ -0,0 +1,6 @@ +TOOL_CHAIN=Renesas RXC Toolchain +VERSION=v2.03.00 +TC_INSTALL=C:\devtools\Renesas\RX\2_3_0\ +VERSION_IDE= +E2STUDIO_VERSION=4.0.2.008 +ACTIVE_CONFIGURATION=HardwareDebug \ No newline at end of file diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.project b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.project new file mode 100644 index 000000000..2d5073011 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.project @@ -0,0 +1,232 @@ + + + RTOSDemo + + + + + + com.renesas.cdt.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + com.renesas.cdt.core.kpitcnature + com.renesas.cdt.core.kpitccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + src/FreeRTOS_Source + 2 + FREERTOS_ROOT/FreeRTOS/Source + + + src/Full_Demo/Standard_Demo_Tasks + 2 + FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal + + + src/Full_Demo/Standard_Demo_Tasks/include + 2 + FREERTOS_ROOT/FreeRTOS/Demo/Common/include + + + + + 1442942249601 + src/FreeRTOS_Source + 6 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-croutine.c + + + + 1442942274534 + src/FreeRTOS_Source/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-MemMang + + + + 1442942274544 + src/FreeRTOS_Source/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-Renesas + + + + 1442947187801 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-BlockQ.c + + + + 1442947187811 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-blocktim.c + + + + 1442947187821 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-countsem.c + + + + 1442947187821 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-death.c + + + + 1442947187831 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-dynamic.c + + + + 1442947187831 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-EventGroupsDemo.c + + + + 1442947187841 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-flop.c + + + + 1442947187841 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-GenQTest.c + + + + 1442947187851 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-IntQueue.c + + + + 1442947187851 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-IntSemTest.c + + + + 1442947187861 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-QueueOverwrite.c + + + + 1442947187871 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-recmutex.c + + + + 1442947187871 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-semtest.c + + + + 1442947187881 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-TaskNotify.c + + + + 1442947187881 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-TimerDemo.c + + + + 1442946309422 + src/FreeRTOS_Source/portable/MemMang + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-heap_4.c + + + + 1442942460340 + src/FreeRTOS_Source/portable/Renesas + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-RX600v2 + + + + + + FREERTOS_ROOT + $%7BPARENT-3-PROJECT_LOC%7D + + + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.settings/CodeGenerator/cgproject.cgp b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.settings/CodeGenerator/cgproject.cgp new file mode 100644 index 000000000..b32777510 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.settings/CodeGenerator/cgproject.cgp @@ -0,0 +1,182288 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.settings/CodeGenerator/cgprojectDatas.datas @@ -0,0 +1,3 @@ +# +#Tue Sep 22 17:05:11 BST 2015 +CGExist=true diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.settings/Dependency_Scan_Preferences.prefs b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.settings/Dependency_Scan_Preferences.prefs new file mode 100644 index 000000000..c52c797ff --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.settings/Dependency_Scan_Preferences.prefs @@ -0,0 +1,4 @@ +Build\ project\ excluding\ the\ dependencies=false +Re-generate\ and\ use\ dependencies\ during\ project\ build=true +Use\ existing\ dependencies\ during\ project\ build=false +eclipse.preferences.version=1 diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.settings/Project_Generation_Prefrences.prefs b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.settings/Project_Generation_Prefrences.prefs new file mode 100644 index 000000000..fa4334b2e --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.settings/Project_Generation_Prefrences.prefs @@ -0,0 +1,54 @@ +com.renesas.cdt.renesas.Assembler.option.userDefine=-nologo;;; +com.renesas.cdt.renesas.Compiler.option.C=com.renesas.cdt.renesas.Compiler.option.C89 +com.renesas.cdt.renesas.Compiler.option.UserDef=-nologo; +com.renesas.cdt.renesas.Compiler.option.defines=__RX; +com.renesas.cdt.renesas.Compiler.option.incFileDirectories="${TCINSTALL}/include"; +com.renesas.cdt.renesas.Configurator.option.cfgPath="" +com.renesas.cdt.renesas.Configurator.option.rtosName=None +com.renesas.cdt.renesas.Configurator.option.rtosPath="" +com.renesas.cdt.renesas.Configurator.option.rtosVersion=None +com.renesas.cdt.renesas.Linker.option.rom=D\=R;D_1\=R_1;D_2\=R_2; +com.renesas.cdt.renesas.Linker.option.typeOfOutputFileOption=Stype via absolute +com.renesas.cdt.renesas.StandardLibrary.option.complexC99=false +com.renesas.cdt.renesas.StandardLibrary.option.ctypec89=false +com.renesas.cdt.renesas.StandardLibrary.option.fenvC99=false +com.renesas.cdt.renesas.StandardLibrary.option.inttypesC99=false +com.renesas.cdt.renesas.StandardLibrary.option.libConfiguration=C(C89) +com.renesas.cdt.renesas.StandardLibrary.option.mathc89=false +com.renesas.cdt.renesas.StandardLibrary.option.mathfc89=false +com.renesas.cdt.renesas.StandardLibrary.option.mode=com.renesas.cdt.renesas.StandardLibrary.option.buildOnlyWhenOptionsChanged +com.renesas.cdt.renesas.StandardLibrary.option.runtime=true +com.renesas.cdt.renesas.StandardLibrary.option.rxccomplexCPP=false +com.renesas.cdt.renesas.StandardLibrary.option.rxciosCPP=false +com.renesas.cdt.renesas.StandardLibrary.option.rxcnewCPP=false +com.renesas.cdt.renesas.StandardLibrary.option.rxcstringCPP=false +com.renesas.cdt.renesas.StandardLibrary.option.stdargc89=false +com.renesas.cdt.renesas.StandardLibrary.option.stdioc89=false +com.renesas.cdt.renesas.StandardLibrary.option.stdlibc89=true +com.renesas.cdt.renesas.StandardLibrary.option.stringc89=true +com.renesas.cdt.renesas.StandardLibrary.option.wcharC99=false +com.renesas.cdt.renesas.StandardLibrary.option.wctypeC99=false +com.renesas.cdt.rxc.HardwareDebug.Assembler.option.endian=Little-endian data +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.RAM=None +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.ROM=None +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.address=00000000 +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.addressRegister=None +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.allocLowerBit=Lower bit +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.cpuType=RX200 +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.denormalized=false +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.endian=Little-endian data +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.enumSize=false +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.packStructures=false +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.patchCode=None +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.precisionDouble=Single precision +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.registerFastInterrupt=None +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.replaceFromIntWithShort=false +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.roundTo=Nearest +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.saveacc=false +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.signBitField=unsigned +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.signChar=unsigned +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.useDynamic=false +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.useTry=false +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.widthDivergence=24 bit +com.renesas.cdt.rxc.HardwareDebug.StandardLibrary.option.endian=Little-endian data +eclipse.preferences.version=1 diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/RTOSDemo HardwareDebug.launch b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/RTOSDemo HardwareDebug.launch new file mode 100644 index 000000000..62208bac8 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/RTOSDemo HardwareDebug.launch @@ -0,0 +1,101 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/custom.bat b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/custom.bat new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/makefile.init b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/makefile.init new file mode 100644 index 000000000..6e9134b91 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/makefile.init @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +export INC_RX=C:\devtools\Renesas\RX\2_3_0\include +export RXC_LIB=C:\devtools\Renesas\RX\2_3_0\bin +export BIN_RX=C:\devtools\Renesas\RX\2_3_0\bin +PATH := $(PATH):C:\devtools\Renesas\RX\2_3_0\bin \ No newline at end of file diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Blinky_Demo/main_blinky.c new file mode 100644 index 000000000..0a919d156 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Blinky_Demo/main_blinky.c @@ -0,0 +1,230 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky style + * project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select + * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY + * in main.c. This file implements the simply blinky style version. + * + * NOTE 2: This file only contains the source code that is specific to the + * basic demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware are defined in main.c. + ****************************************************************************** + * + * main_blinky() creates one queue, and two tasks. It then starts the + * scheduler. + * + * The Queue Send Task: + * The queue send task is implemented by the prvQueueSendTask() function in + * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly + * block for 200 milliseconds, before sending the value 100 to the queue that + * was created within main_blinky(). Once the value is sent, the task loops + * back around to block for another 200 milliseconds...and so on. + * + * The Queue Receive Task: + * The queue receive task is implemented by the prvQueueReceiveTask() function + * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly + * blocks on attempts to read data from the queue that was created within + * main_blinky(). When data is received, the task checks the value of the + * data, and if the value equals the expected 100, toggles an LED. The 'block + * time' parameter passed to the queue receive function specifies that the + * task should be held in the Blocked state indefinitely to wait for data to + * be available on the queue. The queue receive task will only leave the + * Blocked state when the queue send task writes to the queue. As the queue + * send task writes to the queue every 200 milliseconds, the queue receive + * task leaves the Blocked state every 200 milliseconds, and therefore toggles + * the LED every 200 milliseconds. + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Priorities at which the tasks are created. */ +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The rate at which data is sent to the queue. The 200ms value is converted +to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) + +/* The number of items the queue can hold. This is 1 as the receive task +will remove items as they are added, meaning the send task should always find +the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) + +/*-----------------------------------------------------------*/ + +/* + * Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in + * main.c. + */ +void main_blinky( void ); + +/* + * The tasks as described in the comments at the top of this file. + */ +static void prvQueueReceiveTask( void *pvParameters ); +static void prvQueueSendTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The queue used by both tasks. */ +static QueueHandle_t xQueue = NULL; + +/*-----------------------------------------------------------*/ + +void main_blinky( void ) +{ + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + NULL, /* The parameter passed to the task - not used in this case. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ + + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was either insufficient FreeRTOS heap memory available for the idle + and/or timer tasks to be created, or vTaskStartScheduler() was called from + User mode. See the memory management section on the FreeRTOS web site for + more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + mode from which main() is called is set in the C start up code and must be + a privileged mode (not user mode). */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvQueueSendTask( void *pvParameters ) +{ +TickType_t xNextWakeTime; +const unsigned long ulValueToSend = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Place this task in the blocked state until it is time to run again. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + toggle the LED. 0 is used as the block time so the sending operation + will not block - it shouldn't need to block as the queue should always + be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } +} +/*-----------------------------------------------------------*/ + +static void prvQueueReceiveTask( void *pvParameters ) +{ +unsigned long ulReceivedValue; +const unsigned long ulExpectedValue = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + for( ;; ) + { + /* Wait until something arrives in the queue - this task will block + indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + is it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == ulExpectedValue ) + { +//_RB_ LED0 = !LED0; + ulReceivedValue = 0U; + } + } +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/FreeRTOSConfig.h b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/FreeRTOSConfig.h new file mode 100644 index 000000000..ff23b62c2 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/FreeRTOSConfig.h @@ -0,0 +1,182 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/* Renesas hardware definition header. */ +#include "iodefine.h" + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 1 +#define configCPU_CLOCK_HZ ( 52000000UL ) /*_RB_ guess*/ +#define configPERIPHERAL_CLOCK_HZ ( 26000000UL ) /*_RB_ guess*/ +#define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 140 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 40 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 12 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_CO_ROUTINES 0 +#define configUSE_MUTEXES 1 +#define configGENERATE_RUN_TIME_STATS 0 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 0 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_QUEUE_SETS 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configMAX_PRIORITIES ( 7 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE ) + +/* The interrupt priority used by the kernel itself for the tick interrupt and +the pended interrupt. This would normally be the lowest priority. */ +#define configKERNEL_INTERRUPT_PRIORITY 1 + +/* The maximum interrupt priority from which FreeRTOS API calls can be made. +Interrupts that use a priority above this will not be effected by anything the +kernel is doing. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +/* The peripheral used to generate the tick interrupt is configured as part of +the application code. This constant should be set to the vector number of the +peripheral chosen. As supplied this is CMT0. */ +#define configTICK_VECTOR _CMT0_CMI0 + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTimerPendFunctionCall 1 + +void vAssertCalled( void ); +#define configASSERT( x ) if( ( x ) == 0 ) { brk(); taskDISABLE_INTERRUPTS(); for( ;; ); } + +/* Override some of the priorities set in the common demo tasks. This is +required to ensure false positive timing errors are not reported. */ +#define bktPRIMARY_PRIORITY ( configMAX_PRIORITIES - 3 ) +#define bktSECONDARY_PRIORITY ( configMAX_PRIORITIES - 4 ) +#define intqHIGHER_PRIORITY ( configMAX_PRIORITIES - 3 ) + + +/*----------------------------------------------------------- + * Ethernet configuration. + *-----------------------------------------------------------*/ + +/* MAC address configuration. */ +#define configMAC_ADDR0 0x00 +#define configMAC_ADDR1 0x12 +#define configMAC_ADDR2 0x13 +#define configMAC_ADDR3 0x10 +#define configMAC_ADDR4 0x15 +#define configMAC_ADDR5 0x11 + +/* IP address configuration. */ +#define configIP_ADDR0 192 +#define configIP_ADDR1 168 +#define configIP_ADDR2 0 +#define configIP_ADDR3 200 + +/* Netmask configuration. */ +#define configNET_MASK0 255 +#define configNET_MASK1 255 +#define configNET_MASK2 255 +#define configNET_MASK3 0 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.c new file mode 100644 index 000000000..e7dffe6e3 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.c @@ -0,0 +1,162 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * This file contains the non-portable and therefore RX62N specific parts of + * the IntQueue standard demo task - namely the configuration of the timers + * that generate the interrupts and the interrupt entry points. + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo includes. */ +#include "IntQueueTimer.h" +#include "IntQueue.h" + +/* Hardware specifics. */ +#include "iodefine.h" + +#define tmrTIMER_0_1_FREQUENCY ( 2000UL ) +#define tmrTIMER_2_3_FREQUENCY ( 2407UL ) + +void vInitialiseTimerForIntQueueTest( void ) +{ + /* Ensure interrupts do not start until full configuration is complete. */ + portENTER_CRITICAL(); + { + SYSTEM.PRCR.WORD = 0xa502; + + /* Cascade two 8bit timer channels to generate the interrupts. + 8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are + utilised for this test. */ + + /* Enable the timers. */ + SYSTEM.MSTPCRA.BIT.MSTPA5 = 0; + SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; + + /* Enable compare match A interrupt request. */ + TMR0.TCR.BIT.CMIEA = 1; + TMR2.TCR.BIT.CMIEA = 1; + + /* Clear the timer on compare match A. */ + TMR0.TCR.BIT.CCLR = 1; + TMR2.TCR.BIT.CCLR = 1; + + /* Set the compare match value. */ + TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 ); + TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 ); + + /* 16 bit operation ( count from timer 1,2 ). */ + TMR0.TCCR.BIT.CSS = 3; + TMR2.TCCR.BIT.CSS = 3; + + /* Use PCLK as the input. */ + TMR1.TCCR.BIT.CSS = 1; + TMR3.TCCR.BIT.CSS = 1; + + /* Divide PCLK by 8. */ + TMR1.TCCR.BIT.CKS = 2; + TMR3.TCCR.BIT.CKS = 2; + + /* Enable TMR 0, 2 interrupts. */ + TMR0.TCR.BIT.CMIEA = 1; + TMR2.TCR.BIT.CMIEA = 1; + + /* Set interrupt priority and enable. */ + IPR( TMR0, CMIA0 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1; + IR( TMR0, CMIA0 ) = 0U; + IEN( TMR0, CMIA0 ) = 1U; + + /* Do the same for TMR2, but to vector 129. */ + IPR( TMR2, CMIA2 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 2; + IR( TMR2, CMIA2 ) = 0U; + IEN( TMR2, CMIA2 ) = 1U; + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +#pragma interrupt r_tmr_cmia0_interrupt(vect=VECT(TMR0,CMIA0)) +void r_tmr_cmia0_interrupt( void ) +{ + portYIELD_FROM_ISR( xFirstTimerHandler() ); +} +/*-----------------------------------------------------------*/ + +#pragma interrupt r_tmr_cmia2_interrupt(vect=VECT(TMR2,CMIA2)) +void r_tmr_cmia2_interrupt( void ) +{ + portYIELD_FROM_ISR( xSecondTimerHandler() ); +} + + + + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.h new file mode 100644 index 000000000..fcf9f8c1f --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.h @@ -0,0 +1,78 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef INT_QUEUE_TIMER_H +#define INT_QUEUE_TIMER_H + +void vInitialiseTimerForIntQueueTest( void ); +portBASE_TYPE xTimer0Handler( void ); +portBASE_TYPE xTimer1Handler( void ); + +#endif + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Full_Demo/main_full.c b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Full_Demo/main_full.c new file mode 100644 index 000000000..4df406c7f --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Full_Demo/main_full.c @@ -0,0 +1,668 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky + * style project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to + * select between the two. See the notes on using + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY in main.c. This file implements the + * comprehensive version. + * + * NOTE 2: This file only contains the source code that is specific to the + * full demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware, are defined in main.c. + * + ****************************************************************************** + * + * main_full() creates all the demo application tasks and software timers, then + * starts the scheduler. The web documentation provides more details of the + * standard demo application tasks, which provide no particular functionality, + * but do provide a good example of how to use the FreeRTOS API. + * + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "Reg test" tasks - These fill both the core and floating point registers with + * known values, then check that each register maintains its expected value for + * the lifetime of the task. Each task uses a different set of values. The reg + * test tasks execute with a very low priority, so get preempted very + * frequently. A register containing an unexpected value is indicative of an + * error in the context switching mechanism. + * + * "Check" task - The check task period is initially set to three seconds. The + * task checks that all the standard demo tasks, and the register check tasks, + * are not only still executing, but are executing without reporting any errors. + * If the check task discovers that a task has either stalled, or reported an + * error, then it changes its own execution period from the initial three + * seconds, to just 200ms. The check task also toggles an LED each time it is + * called. This provides a visual indication of the system status: If the LED + * toggles every three seconds, then no issues have been discovered. If the LED + * toggles every 200ms, then an issue has been discovered with at least one + * task. + */ + +/* Standard includes. */ +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "semphr.h" + +/* Standard demo application includes. */ +#include "flop.h" +#include "semtest.h" +#include "dynamic.h" +#include "BlockQ.h" +#include "blocktim.h" +#include "countsem.h" +#include "GenQTest.h" +#include "recmutex.h" +#include "death.h" +#include "partest.h" +#include "comtest2.h" +#include "serial.h" +#include "TimerDemo.h" +#include "QueueOverwrite.h" +#include "IntQueue.h" +#include "EventGroupsDemo.h" +#include "TaskNotify.h" +#include "IntSemTest.h" + +/* Priorities for the demo application tasks. */ +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) +#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3UL ) +#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY ) + +/* The priority used by the UART command console task. */ +#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) + +/* A block time of zero simply means "don't block". */ +#define mainDONT_BLOCK ( 0UL ) + +/* The period after which the check timer will expire, in ms, provided no errors +have been reported by any of the standard demo tasks. ms are converted to the +equivalent in ticks using the portTICK_PERIOD_MS constant. */ +#define mainNO_ERROR_CHECK_TASK_PERIOD ( 3000UL / portTICK_PERIOD_MS ) + +/* The period at which the check timer will expire, in ms, if an error has been +reported in one of the standard demo tasks. ms are converted to the equivalent +in ticks using the portTICK_PERIOD_MS constant. */ +#define mainERROR_CHECK_TASK_PERIOD ( 200UL / portTICK_PERIOD_MS ) + +/* Parameters that are passed into the register check tasks solely for the +purpose of ensuring parameters are passed into tasks correctly. */ +#define mainREG_TEST_1_PARAMETER ( ( void * ) 0x12121212UL ) +#define mainREG_TEST_2_PARAMETER ( ( void * ) 0x12345678UL ) + +/* The base period used by the timer test tasks. */ +#define mainTIMER_TEST_PERIOD ( 50 ) + +/*-----------------------------------------------------------*/ + +/* + * Entry point for the comprehensive demo (as opposed to the simple blinky + * demo). + */ +void main_full( void ); + +/* + * The full demo includes some functionality called from the tick hook. + */ +void vFullDemoTickHook( void ); + + /* + * The check task, as described at the top of this file. + */ +static void prvCheckTask( void *pvParameters ); + +/* + * Register check tasks, and the tasks used to write over and check the contents + * of the registers, as described at the top of this file. The nature of these + * files necessitates that they are written in assembly, but the entry points + * are kept in the C file for the convenience of checking the task parameter. + */ +static void prvRegTest1Task( void *pvParameters ); +static void prvRegTest2Task( void *pvParameters ); +static void prvRegTest1Implementation( void ); +static void prvRegTest2Implementation( void ); + +/* + * A high priority task that does nothing other than execute at a pseudo random + * time to ensure the other test tasks don't just execute in a repeating + * pattern. + */ +static void prvPseudoRandomiser( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The following two variables are used to communicate the status of the +register check tasks to the check task. If the variables keep incrementing, +then the register check tasks have not discovered any errors. If a variable +stops incrementing, then an error has been found. */ +volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; + +/* String for display in the web server. It is set to an error message if the +check task detects an error. */ +const char *pcStatusMessage = "All tasks running without error"; +/*-----------------------------------------------------------*/ + +void main_full( void ) +{ + /* Start all the other standard demo/test tasks. They have no particular + functionality, but do demonstrate how to use the FreeRTOS API and test the + kernel port. */ + vStartInterruptQueueTasks(); + vStartDynamicPriorityTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vCreateBlockTimeTasks(); + vStartCountingSemaphoreTasks(); + vStartGenericQueueTasks( tskIDLE_PRIORITY ); + vStartRecursiveMutexTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartMathTasks( mainFLOP_TASK_PRIORITY ); + vStartTimerDemoTask( mainTIMER_TEST_PERIOD ); + vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY ); + vStartEventGroupTasks(); + vStartTaskNotifyTask(); + vStartInterruptSemaphoreTasks(); + + /* Create the register check tasks, as described at the top of this file */ + xTaskCreate( prvRegTest1Task, "RegTst1", configMINIMAL_STACK_SIZE, mainREG_TEST_1_PARAMETER, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvRegTest2Task, "RegTst2", configMINIMAL_STACK_SIZE, mainREG_TEST_2_PARAMETER, tskIDLE_PRIORITY, NULL ); + + /* Create the task that just adds a little random behaviour. */ + xTaskCreate( prvPseudoRandomiser, "Rnd", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL ); + + /* Create the task that performs the 'check' functionality, as described at + the top of this file. */ + xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* The set of tasks created by the following function call have to be + created last as they keep account of the number of tasks they expect to see + running. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was either insufficient FreeRTOS heap memory available for the idle + and/or timer tasks to be created, or vTaskStartScheduler() was called from + User mode. See the memory management section on the FreeRTOS web site for + more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + mode from which main() is called is set in the C start up code and must be + a privileged mode (not user mode). */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvCheckTask( void *pvParameters ) +{ +TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD; +TickType_t xLastExecutionTime; +static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; +unsigned long ulErrorFound = pdFALSE; + + /* Just to stop compiler warnings. */ + ( void ) pvParameters; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. The onboard LED is toggled on each iteration. + If an error is detected then the delay period is decreased from + mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the + effect of increasing the rate at which the onboard LED toggles, and in so + doing gives visual feedback of the system status. */ + for( ;; ) + { + /* Delay until it is time to execute again. */ + vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod ); + + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none have detected an error. */ + if( xAreIntQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 0UL; + } + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 1UL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 2UL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 3UL; + } + + if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 4UL; + } + + if ( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 5UL; + } + + if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 6UL; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 7UL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 8UL; + } + + if( xAreTimerDemoTasksStillRunning( ( TickType_t ) mainNO_ERROR_CHECK_TASK_PERIOD ) != pdPASS ) + { + ulErrorFound |= 1UL << 9UL; + } + + if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 10UL; + } + + if( xIsQueueOverwriteTaskStillRunning() != pdPASS ) + { + ulErrorFound |= 1UL << 11UL; + } + + if( xAreEventGroupTasksStillRunning() != pdPASS ) + { + ulErrorFound |= 1UL << 12UL; + } + + if( xAreTaskNotificationTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 13UL; + } + + if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 14UL; + } + + /* Check that the register test 1 task is still running. */ + if( ulLastRegTest1Value == ulRegTest1LoopCounter ) + { + ulErrorFound |= 1UL << 15UL; + } + ulLastRegTest1Value = ulRegTest1LoopCounter; + + /* Check that the register test 2 task is still running. */ + if( ulLastRegTest2Value == ulRegTest2LoopCounter ) + { + ulErrorFound |= 1UL << 16UL; + } + ulLastRegTest2Value = ulRegTest2LoopCounter; + + /* Toggle the check LED to give an indication of the system status. If + the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then + everything is ok. A faster toggle indicates an error. */ +//_RB_ LED0 = !LED0; + + if( ulErrorFound != pdFALSE ) + { + /* An error has been detected in one of the tasks - flash the LED + at a higher frequency to give visible feedback that something has + gone wrong (it might just be that the loop back connector required + by the comtest tasks has not been fitted). */ + xDelayPeriod = mainERROR_CHECK_TASK_PERIOD; + pcStatusMessage = "Error found in at least one task."; + } + } +} +/*-----------------------------------------------------------*/ + +static void prvPseudoRandomiser( void *pvParameters ) +{ +const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL, ulMinDelay = ( 35 / portTICK_PERIOD_MS ); +volatile uint32_t ulNextRand = ( uint32_t ) &pvParameters, ulValue; + + /* This task does nothing other than ensure there is a little bit of + disruption in the scheduling pattern of the other tasks. Normally this is + done by generating interrupts at pseudo random times. */ + for( ;; ) + { + ulNextRand = ( ulMultiplier * ulNextRand ) + ulIncrement; + ulValue = ( ulNextRand >> 16UL ) & 0xffUL; + + if( ulValue < ulMinDelay ) + { + ulValue = ulMinDelay; + } + + vTaskDelay( ulValue ); + + while( ulValue > 0 ) + { + nop(); + nop(); + nop(); + nop(); + nop(); + nop(); + nop(); + nop(); + + ulValue--; + } + } +} +/*-----------------------------------------------------------*/ + +void vFullDemoTickHook( void ) +{ + /* The full demo includes a software timer demo/test that requires + prodding periodically from the tick interrupt. */ + vTimerPeriodicISRTests(); + + /* Call the periodic queue overwrite from ISR demo. */ + vQueueOverwritePeriodicISRDemo(); + + /* Call the periodic event group from ISR demo. */ + vPeriodicEventGroupsProcessing(); + + /* Use task notifications from an interrupt. */ + xNotifyTaskFromISR(); + + /* Use mutexes from interrupts. */ + vInterruptSemaphorePeriodicTest(); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +static void prvRegTest1Task( void *pvParameters ) +{ + if( pvParameters != mainREG_TEST_1_PARAMETER ) + { + /* The parameter did not contain the expected value. */ + for( ;; ) + { + /* Stop the tick interrupt so its obvious something has gone wrong. */ + taskDISABLE_INTERRUPTS(); + } + } + + /* This is an inline asm function that never returns. */ + prvRegTest1Implementation(); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +static void prvRegTest2Task( void *pvParameters ) +{ + if( pvParameters != mainREG_TEST_2_PARAMETER ) + { + /* The parameter did not contain the expected value. */ + for( ;; ) + { + /* Stop the tick interrupt so its obvious something has gone wrong. */ + taskDISABLE_INTERRUPTS(); + } + } + + /* This is an inline asm function that never returns. */ + prvRegTest2Implementation(); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +#pragma inline_asm prvRegTest1Implementation +static void prvRegTest1Implementation( void ) +{ + ; Put a known value in each register. + MOV.L #1, R1 + MOV.L #2, R2 + MOV.L #3, R3 + MOV.L #4, R4 + MOV.L #5, R5 + MOV.L #6, R6 + MOV.L #7, R7 + MOV.L #8, R8 + MOV.L #9, R9 + MOV.L #10, R10 + MOV.L #11, R11 + MOV.L #12, R12 + MOV.L #13, R13 + MOV.L #14, R14 + MOV.L #15, R15 + + ; Loop, checking each itteration that each register still contains the + ; expected value. +TestLoop1: + + ; Push the registers that are going to get clobbered. + PUSHM R14-R15 + + ; Increment the loop counter to show this task is still getting CPU time. + MOV.L #_ulRegTest1LoopCounter, R14 + MOV.L [ R14 ], R15 + ADD #1, R15 + MOV.L R15, [ R14 ] + + ; Yield to extend the text coverage. Set the bit in the ITU SWINTR register. + MOV.L #1, R14 + MOV.L #0872E0H, R15 + MOV.B R14, [R15] + NOP + NOP + + ; Restore the clobbered registers. + POPM R14-R15 + + ; Now compare each register to ensure it still contains the value that was + ; set before this loop was entered. + CMP #1, R1 + BNE RegTest1Error + CMP #2, R2 + BNE RegTest1Error + CMP #3, R3 + BNE RegTest1Error + CMP #4, R4 + BNE RegTest1Error + CMP #5, R5 + BNE RegTest1Error + CMP #6, R6 + BNE RegTest1Error + CMP #7, R7 + BNE RegTest1Error + CMP #8, R8 + BNE RegTest1Error + CMP #9, R9 + BNE RegTest1Error + CMP #10, R10 + BNE RegTest1Error + CMP #11, R11 + BNE RegTest1Error + CMP #12, R12 + BNE RegTest1Error + CMP #13, R13 + BNE RegTest1Error + CMP #14, R14 + BNE RegTest1Error + CMP #15, R15 + BNE RegTest1Error + + ; All comparisons passed, start a new itteratio of this loop. + BRA TestLoop1 + +RegTest1Error: + ; A compare failed, just loop here so the loop counter stops incrementing + ; causing the check task to indicate the error. + BRA RegTest1Error +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +#pragma inline_asm prvRegTest2Implementation +static void prvRegTest2Implementation( void ) +{ + ; Put a known value in each register. + MOV.L #10, R1 + MOV.L #20, R2 + MOV.L #30, R3 + MOV.L #40, R4 + MOV.L #50, R5 + MOV.L #60, R6 + MOV.L #70, R7 + MOV.L #80, R8 + MOV.L #90, R9 + MOV.L #100, R10 + MOV.L #110, R11 + MOV.L #120, R12 + MOV.L #130, R13 + MOV.L #140, R14 + MOV.L #150, R15 + + ; Loop, checking on each itteration that each register still contains the + ; expected value. +TestLoop2: + + ; Push the registers that are going to get clobbered. + PUSHM R14-R15 + + ; Increment the loop counter to show this task is still getting CPU time. + MOV.L #_ulRegTest2LoopCounter, R14 + MOV.L [ R14 ], R15 + ADD #1, R15 + MOV.L R15, [ R14 ] + + ; Restore the clobbered registers. + POPM R14-R15 + + CMP #10, R1 + BNE RegTest2Error + CMP #20, R2 + BNE RegTest2Error + CMP #30, R3 + BNE RegTest2Error + CMP #40, R4 + BNE RegTest2Error + CMP #50, R5 + BNE RegTest2Error + CMP #60, R6 + BNE RegTest2Error + CMP #70, R7 + BNE RegTest2Error + CMP #80, R8 + BNE RegTest2Error + CMP #90, R9 + BNE RegTest2Error + CMP #100, R10 + BNE RegTest2Error + CMP #110, R11 + BNE RegTest2Error + CMP #120, R12 + BNE RegTest2Error + CMP #130, R13 + BNE RegTest2Error + CMP #140, R14 + BNE RegTest2Error + CMP #150, R15 + BNE RegTest2Error + + ; All comparisons passed, start a new itteratio of this loop. + BRA TestLoop2 + +RegTest2Error: + ; A compare failed, just loop here so the loop counter stops incrementing + ; - causing the check task to indicate the error. + BRA RegTest2Error +} +/*-----------------------------------------------------------*/ + + + + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Renesas_Code/stacksct.h b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Renesas_Code/stacksct.h new file mode 100644 index 000000000..3c08dcb1d --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Renesas_Code/stacksct.h @@ -0,0 +1,13 @@ +/***************************************************************/ +/* */ +/* PROJECT NAME : RTOSDemo */ +/* FILE : stacksct.h */ +/* DESCRIPTION : Setting of Stack area */ +/* CPU SERIES : RX200 */ +/* CPU TYPE : RX231 */ +/* */ +/* This file is generated by e2 studio. */ +/* */ +/***************************************************************/ +#pragma stacksize su=0x300 +#pragma stacksize si=0x300 \ No newline at end of file diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Renesas_Code/typedefine.h b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Renesas_Code/typedefine.h new file mode 100644 index 000000000..c50b4f754 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Renesas_Code/typedefine.h @@ -0,0 +1,42 @@ +/***************************************************************/ +/* */ +/* PROJECT NAME : RTOSDemo */ +/* FILE : typedefine.h */ +/* DESCRIPTION : Aliases of Integer Type */ +/* CPU SERIES : RX200 */ +/* CPU TYPE : RX231 */ +/* */ +/* This file is generated by e2 studio. */ +/* */ +/***************************************************************/ + + + + +/********************************************************************* +* +* Device : RX +* +* File Name : typedefine.h +* +* Abstract : Aliases of Integer Type. +* +* History : 1.00 (2009-08-07) +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright (C) 2009 Renesas Electronics Corporation. +* and Renesas Solutions Corporation. All rights reserved. +* +*********************************************************************/ + +typedef signed char _SBYTE; +typedef unsigned char _UBYTE; +typedef signed short _SWORD; +typedef unsigned short _UWORD; +typedef signed int _SINT; +typedef unsigned int _UINT; +typedef signed long _SDWORD; +typedef unsigned long _UDWORD; +typedef signed long long _SQWORD; +typedef unsigned long long _UQWORD; diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Renesas_Code/vect.h b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Renesas_Code/vect.h new file mode 100644 index 000000000..c761e6d0d --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Renesas_Code/vect.h @@ -0,0 +1,849 @@ +/***************************************************************/ +/* */ +/* PROJECT NAME : RTOSDemo */ +/* FILE : vect.h */ +/* DESCRIPTION : Definition of vector */ +/* CPU SERIES : RX200 */ +/* CPU TYPE : RX231 */ +/* */ +/* This file is generated by e2 studio. */ +/* */ +/***************************************************************/ + + + + +/************************************************************************ +* +* Device : RX/RX200/RX231 +* +* File Name : vect.h +* +* Abstract : Definition of Vector. +* +* History : 0.50 (2014-09-18) [Hardware Manual Revision : 0.50] +* : 1.00 (2015-05-18) [Hardware Manual Revision : 1.00] +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright (C) 2015 (2014) Renesas Electronics Corporation. +* +************************************************************************/ + +// Exception(Supervisor Instruction) +#pragma interrupt (Excep_SuperVisorInst) +void Excep_SuperVisorInst(void); + +// Exception(Access Instruction) +#pragma interrupt (Excep_AccessInst) +void Excep_AccessInst(void); + +// Exception(Undefined Instruction) +#pragma interrupt (Excep_UndefinedInst) +void Excep_UndefinedInst(void); + +// Exception(Floating Point) +#pragma interrupt (Excep_FloatingPoint) +void Excep_FloatingPoint(void); + +// NMI +#pragma interrupt (NonMaskableInterrupt) +void NonMaskableInterrupt(void); + +// Dummy +#pragma interrupt (Dummy) +void Dummy(void); + +// BRK +#pragma interrupt (Excep_BRK(vect=0)) +void Excep_BRK(void); + +// vector 1 reserved +// vector 2 reserved +// vector 3 reserved +// vector 4 reserved +// vector 5 reserved +// vector 6 reserved +// vector 7 reserved +// vector 8 reserved +// vector 9 reserved +// vector 10 reserved +// vector 11 reserved +// vector 12 reserved +// vector 13 reserved +// vector 14 reserved +// vector 15 reserved + +// BSC BUSERR +#pragma interrupt (Excep_BSC_BUSERR(vect=16)) +void Excep_BSC_BUSERR(void); + +// vector 17 reserved +// vector 18 reserved +// vector 19 reserved +// vector 20 reserved +// vector 21 reserved +// vector 22 reserved + +// FCU FRDYI +#pragma interrupt (Excep_FCU_FRDYI(vect=23)) +void Excep_FCU_FRDYI(void); + +// vector 24 reserved +// vector 25 reserved +// vector 26 reserved + +// ICU SWINT +// FreeRTOS installs its own software interrupt. +//#pragma interrupt (Excep_ICU_SWINT(vect=27)) +//void Excep_ICU_SWINT(void); + +// CMT0 CMI0 +// By default FreeRTOS uses CMT0 to generate the tick interrupt. +//#pragma interrupt (Excep_CMT0_CMI0(vect=28)) +//void Excep_CMT0_CMI0(void); + +// CMT1 CMI1 +#pragma interrupt (Excep_CMT1_CMI1(vect=29)) +void Excep_CMT1_CMI1(void); + +// CMT2 CMI2 +#pragma interrupt (Excep_CMT2_CMI2(vect=30)) +void Excep_CMT2_CMI2(void); + +// CMT3 CMI3 +#pragma interrupt (Excep_CMT3_CMI3(vect=31)) +void Excep_CMT3_CMI3(void); + +// CAC FERRF +#pragma interrupt (Excep_CAC_FERRF(vect=32)) +void Excep_CAC_FERRF(void); + +// CAC MENDF +#pragma interrupt (Excep_CAC_MENDF(vect=33)) +void Excep_CAC_MENDF(void); + +// CAC OVFF +#pragma interrupt (Excep_CAC_OVFF(vect=34)) +void Excep_CAC_OVFF(void); + +// vector 35 reserved + +// USB0 D0FIFO0 +#pragma interrupt (Excep_USB0_D0FIFO0(vect=36)) +void Excep_USB0_D0FIFO0(void); + +// USB0 D1FIFO0 +#pragma interrupt (Excep_USB0_D1FIFO0(vect=37)) +void Excep_USB0_D1FIFO0(void); + +// USB0 USBI0 +#pragma interrupt (Excep_USB0_USBI0(vect=38)) +void Excep_USB0_USBI0(void); + +// vector 39 reserved + +// SDHI SBFAI +#pragma interrupt (Excep_SDHI_SBFAI(vect=40)) +void Excep_SDHI_SBFAI(void); + +// SDHI CDETI +#pragma interrupt (Excep_SDHI_CDETI(vect=41)) +void Excep_SDHI_CDETI(void); + +// SDHI CACI +#pragma interrupt (Excep_SDHI_CACI(vect=42)) +void Excep_SDHI_CACI(void); + +// SDHI SDACI +#pragma interrupt (Excep_SDHI_SDACI(vect=43)) +void Excep_SDHI_SDACI(void); + +// RSPI0 SPEI0 +#pragma interrupt (Excep_RSPI0_SPEI0(vect=44)) +void Excep_RSPI0_SPEI0(void); + +// RSPI0 SPRI0 +#pragma interrupt (Excep_RSPI0_SPRI0(vect=45)) +void Excep_RSPI0_SPRI0(void); + +// RSPI0 SPTI0 +#pragma interrupt (Excep_RSPI0_SPTI0(vect=46)) +void Excep_RSPI0_SPTI0(void); + +// RSPI0 SPII0 +#pragma interrupt (Excep_RSPI0_SPII0(vect=47)) +void Excep_RSPI0_SPII0(void); + +// vector 48 reserved +// vector 49 reserved +// vector 50 reserved +// vector 51 reserved + +// RSCAN COMFRXINT +#pragma interrupt (Excep_RSCAN_COMFRXINT(vect=52)) +void Excep_RSCAN_COMFRXINT(void); + +// RSCAN RXFINT +#pragma interrupt (Excep_RSCAN_RXFINT(vect=53)) +void Excep_RSCAN_RXFINT(void); + +// RSCAN TXINT +#pragma interrupt (Excep_RSCAN_TXINT(vect=54)) +void Excep_RSCAN_TXINT(void); + +// RSCAN CHERRINT +#pragma interrupt (Excep_RSCAN_CHERRINT(vect=55)) +void Excep_RSCAN_CHERRINT(void); + +// RSCAN GLERRINT +#pragma interrupt (Excep_RSCAN_GLERRINT(vect=56)) +void Excep_RSCAN_GLERRINT(void); + +// DOC DOPCF +#pragma interrupt (Excep_DOC_DOPCF(vect=57)) +void Excep_DOC_DOPCF(void); + +// CMPB CMPB0 +#pragma interrupt (Excep_CMPB_CMPB0(vect=58)) +void Excep_CMPB_CMPB0(void); + +// CMPB CMPB1 +#pragma interrupt (Excep_CMPB_CMPB1(vect=59)) +void Excep_CMPB_CMPB1(void); + +// CTSU CTSUWR +#pragma interrupt (Excep_CTSU_CTSUWR(vect=60)) +void Excep_CTSU_CTSUWR(void); + +// CTSU CTSURD +#pragma interrupt (Excep_CTSU_CTSURD(vect=61)) +void Excep_CTSU_CTSURD(void); + +// CTSU CTSUFN +#pragma interrupt (Excep_CTSU_CTSUFN(vect=62)) +void Excep_CTSU_CTSUFN(void); + +// RTC CUP +#pragma interrupt (Excep_RTC_CUP(vect=63)) +void Excep_RTC_CUP(void); + +// ICU IRQ0 +#pragma interrupt (Excep_ICU_IRQ0(vect=64)) +void Excep_ICU_IRQ0(void); + +// ICU IRQ1 +#pragma interrupt (Excep_ICU_IRQ1(vect=65)) +void Excep_ICU_IRQ1(void); + +// ICU IRQ2 +#pragma interrupt (Excep_ICU_IRQ2(vect=66)) +void Excep_ICU_IRQ2(void); + +// ICU IRQ3 +#pragma interrupt (Excep_ICU_IRQ3(vect=67)) +void Excep_ICU_IRQ3(void); + +// ICU IRQ4 +#pragma interrupt (Excep_ICU_IRQ4(vect=68)) +void Excep_ICU_IRQ4(void); + +// ICU IRQ5 +#pragma interrupt (Excep_ICU_IRQ5(vect=69)) +void Excep_ICU_IRQ5(void); + +// ICU IRQ6 +#pragma interrupt (Excep_ICU_IRQ6(vect=70)) +void Excep_ICU_IRQ6(void); + +// ICU IRQ7 +#pragma interrupt (Excep_ICU_IRQ7(vect=71)) +void Excep_ICU_IRQ7(void); + +// vector 72 reserved +// vector 73 reserved +// vector 74 reserved +// vector 75 reserved +// vector 76 reserved +// vector 77 reserved +// vector 78 reserved +// vector 79 reserved + +// ELC ELSR8I +#pragma interrupt (Excep_ELC_ELSR8I(vect=80)) +void Excep_ELC_ELSR8I(void); + +// vector 81 reserved +// vector 82 reserved +// vector 83 reserved +// vector 84 reserved +// vector 85 reserved +// vector 86 reserved +// vector 87 reserved + +// LVD LVD1 +#pragma interrupt (Excep_LVD_LVD1(vect=88)) +void Excep_LVD_LVD1(void); + +// LVD LVD2 +#pragma interrupt (Excep_LVD_LVD2(vect=89)) +void Excep_LVD_LVD2(void); + +// CMPA CMPA1 +//#pragma interrupt (Excep_CMPA_CMPA1(vect=88)) +//void Excep_CMPA_CMPA1(void); + +// CMPA CMPA2 +//#pragma interrupt (Excep_CMPA_CMPA2(vect=89)) +//void Excep_CMPA_CMPA2(void); + +// USB0 USBR0 +#pragma interrupt (Excep_USB0_USBR0(vect=90)) +void Excep_USB0_USBR0(void); + +// VBATT VBTLVDI +#pragma interrupt (Excep_VBATT_VBTLVDI(vect=91)) +void Excep_VBATT_VBTLVDI(void); + +// RTC ALM +#pragma interrupt (Excep_RTC_ALM(vect=92)) +void Excep_RTC_ALM(void); + +// RTC PRD +#pragma interrupt (Excep_RTC_PRD(vect=93)) +void Excep_RTC_PRD(void); + +// vector 94 reserved +// vector 95 reserved +// vector 96 reserved +// vector 97 reserved +// vector 98 reserved +// vector 99 reserved +// vector 100 reserved +// vector 101 reserved + +// S12AD S12ADI0 +#pragma interrupt (Excep_S12AD_S12ADI0(vect=102)) +void Excep_S12AD_S12ADI0(void); + +// S12AD GBADI +#pragma interrupt (Excep_S12AD_GBADI(vect=103)) +void Excep_S12AD_GBADI(void); + +// CMPB1 CMPB2 +#pragma interrupt (Excep_CMPB1_CMPB2(vect=104)) +void Excep_CMPB1_CMPB2(void); + +// CMPB1 CMPB3 +#pragma interrupt (Excep_CMPB1_CMPB3(vect=105)) +void Excep_CMPB1_CMPB3(void); + +// ELC ELSR18I +#pragma interrupt (Excep_ELC_ELSR18I(vect=106)) +void Excep_ELC_ELSR18I(void); + +// ELC ELSR19I +#pragma interrupt (Excep_ELC_ELSR19I(vect=107)) +void Excep_ELC_ELSR19I(void); + +// SSI0 SSIF0 +#pragma interrupt (Excep_SSI0_SSIF0(vect=108)) +void Excep_SSI0_SSIF0(void); + +// SSI0 SSIRXI0 +#pragma interrupt (Excep_SSI0_SSIRXI0(vect=109)) +void Excep_SSI0_SSIRXI0(void); + +// SSI0 SSITXI0 +#pragma interrupt (Excep_SSI0_SSITXI0(vect=110)) +void Excep_SSI0_SSITXI0(void); + +// SECURITY RD +#pragma interrupt (Excep_SECURITY_RD(vect=111)) +void Excep_SECURITY_RD(void); + +// SECURITY WR +#pragma interrupt (Excep_SECURITY_WR(vect=112)) +void Excep_SECURITY_WR(void); + +// SECURITY ERR +#pragma interrupt (Excep_SECURITY_ERR(vect=113)) +void Excep_SECURITY_ERR(void); + +// MTU0 TGIA0 +#pragma interrupt (Excep_MTU0_TGIA0(vect=114)) +void Excep_MTU0_TGIA0(void); + +// MTU0 TGIB0 +#pragma interrupt (Excep_MTU0_TGIB0(vect=115)) +void Excep_MTU0_TGIB0(void); + +// MTU0 TGIC0 +#pragma interrupt (Excep_MTU0_TGIC0(vect=116)) +void Excep_MTU0_TGIC0(void); + +// MTU0 TGID0 +#pragma interrupt (Excep_MTU0_TGID0(vect=117)) +void Excep_MTU0_TGID0(void); + +// MTU0 TCIV0 +#pragma interrupt (Excep_MTU0_TCIV0(vect=118)) +void Excep_MTU0_TCIV0(void); + +// MTU0 TGIE0 +#pragma interrupt (Excep_MTU0_TGIE0(vect=119)) +void Excep_MTU0_TGIE0(void); + +// MTU0 TGIF0 +#pragma interrupt (Excep_MTU0_TGIF0(vect=120)) +void Excep_MTU0_TGIF0(void); + +// MTU1 TGIA1 +#pragma interrupt (Excep_MTU1_TGIA1(vect=121)) +void Excep_MTU1_TGIA1(void); + +// MTU1 TGIB1 +#pragma interrupt (Excep_MTU1_TGIB1(vect=122)) +void Excep_MTU1_TGIB1(void); + +// MTU1 TCIV1 +#pragma interrupt (Excep_MTU1_TCIV1(vect=123)) +void Excep_MTU1_TCIV1(void); + +// MTU1 TCIU1 +#pragma interrupt (Excep_MTU1_TCIU1(vect=124)) +void Excep_MTU1_TCIU1(void); + +// MTU2 TGIA2 +#pragma interrupt (Excep_MTU2_TGIA2(vect=125)) +void Excep_MTU2_TGIA2(void); + +// MTU2 TGIB2 +#pragma interrupt (Excep_MTU2_TGIB2(vect=126)) +void Excep_MTU2_TGIB2(void); + +// MTU2 TCIV2 +#pragma interrupt (Excep_MTU2_TCIV2(vect=127)) +void Excep_MTU2_TCIV2(void); + +// MTU2 TCIU2 +#pragma interrupt (Excep_MTU2_TCIU2(vect=128)) +void Excep_MTU2_TCIU2(void); + +// MTU3 TGIA3 +#pragma interrupt (Excep_MTU3_TGIA3(vect=129)) +void Excep_MTU3_TGIA3(void); + +// MTU3 TGIB3 +#pragma interrupt (Excep_MTU3_TGIB3(vect=130)) +void Excep_MTU3_TGIB3(void); + +// MTU3 TGIC3 +#pragma interrupt (Excep_MTU3_TGIC3(vect=131)) +void Excep_MTU3_TGIC3(void); + +// MTU3 TGID3 +#pragma interrupt (Excep_MTU3_TGID3(vect=132)) +void Excep_MTU3_TGID3(void); + +// MTU3 TCIV3 +#pragma interrupt (Excep_MTU3_TCIV3(vect=133)) +void Excep_MTU3_TCIV3(void); + +// MTU4 TGIA4 +#pragma interrupt (Excep_MTU4_TGIA4(vect=134)) +void Excep_MTU4_TGIA4(void); + +// MTU4 TGIB4 +#pragma interrupt (Excep_MTU4_TGIB4(vect=135)) +void Excep_MTU4_TGIB4(void); + +// MTU4 TGIC4 +#pragma interrupt (Excep_MTU4_TGIC4(vect=136)) +void Excep_MTU4_TGIC4(void); + +// MTU4 TGID4 +#pragma interrupt (Excep_MTU4_TGID4(vect=137)) +void Excep_MTU4_TGID4(void); + +// MTU4 TCIV4 +#pragma interrupt (Excep_MTU4_TCIV4(vect=138)) +void Excep_MTU4_TCIV4(void); + +// MTU5 TGIU5 +#pragma interrupt (Excep_MTU5_TGIU5(vect=139)) +void Excep_MTU5_TGIU5(void); + +// MTU5 TGIV5 +#pragma interrupt (Excep_MTU5_TGIV5(vect=140)) +void Excep_MTU5_TGIV5(void); + +// MTU5 TGIW5 +#pragma interrupt (Excep_MTU5_TGIW5(vect=141)) +void Excep_MTU5_TGIW5(void); + +// TPU0 TGI0A +#pragma interrupt (Excep_TPU0_TGI0A(vect=142)) +void Excep_TPU0_TGI0A(void); + +// TPU0 TGI0B +#pragma interrupt (Excep_TPU0_TGI0B(vect=143)) +void Excep_TPU0_TGI0B(void); + +// TPU0 TGI0C +#pragma interrupt (Excep_TPU0_TGI0C(vect=144)) +void Excep_TPU0_TGI0C(void); + +// TPU0 TGI0D +#pragma interrupt (Excep_TPU0_TGI0D(vect=145)) +void Excep_TPU0_TGI0D(void); + +// TPU0 TCI0V +#pragma interrupt (Excep_TPU0_TCI0V(vect=146)) +void Excep_TPU0_TCI0V(void); + +// TPU1 TGI1A +#pragma interrupt (Excep_TPU1_TGI1A(vect=147)) +void Excep_TPU1_TGI1A(void); + +// TPU1 TGI1B +#pragma interrupt (Excep_TPU1_TGI1B(vect=148)) +void Excep_TPU1_TGI1B(void); + +// TPU1 TCI1V +#pragma interrupt (Excep_TPU1_TCI1V(vect=149)) +void Excep_TPU1_TCI1V(void); + +// TPU1 TCI1U +#pragma interrupt (Excep_TPU1_TCI1U(vect=150)) +void Excep_TPU1_TCI1U(void); + +// TPU2 TGI2A +#pragma interrupt (Excep_TPU2_TGI2A(vect=151)) +void Excep_TPU2_TGI2A(void); + +// TPU2 TGI2B +#pragma interrupt (Excep_TPU2_TGI2B(vect=152)) +void Excep_TPU2_TGI2B(void); + +// TPU2 TCI2V +#pragma interrupt (Excep_TPU2_TCI2V(vect=153)) +void Excep_TPU2_TCI2V(void); + +// TPU2 TCI2U +#pragma interrupt (Excep_TPU2_TCI2U(vect=154)) +void Excep_TPU2_TCI2U(void); + +// TPU3 TGI3A +#pragma interrupt (Excep_TPU3_TGI3A(vect=155)) +void Excep_TPU3_TGI3A(void); + +// TPU3 TGI3B +#pragma interrupt (Excep_TPU3_TGI3B(vect=156)) +void Excep_TPU3_TGI3B(void); + +// TPU3 TGI3C +#pragma interrupt (Excep_TPU3_TGI3C(vect=157)) +void Excep_TPU3_TGI3C(void); + +// TPU3 TGI3D +#pragma interrupt (Excep_TPU3_TGI3D(vect=158)) +void Excep_TPU3_TGI3D(void); + +// TPU3 TCI3V +#pragma interrupt (Excep_TPU3_TCI3V(vect=159)) +void Excep_TPU3_TCI3V(void); + +// TPU4 TGI4A +#pragma interrupt (Excep_TPU4_TGI4A(vect=160)) +void Excep_TPU4_TGI4A(void); + +// TPU4 TGI4B +#pragma interrupt (Excep_TPU4_TGI4B(vect=161)) +void Excep_TPU4_TGI4B(void); + +// TPU4 TCI4V +#pragma interrupt (Excep_TPU4_TCI4V(vect=162)) +void Excep_TPU4_TCI4V(void); + +// TPU4 TCI4U +#pragma interrupt (Excep_TPU4_TCI4U(vect=163)) +void Excep_TPU4_TCI4U(void); + +// TPU5 TGI5A +#pragma interrupt (Excep_TPU5_TGI5A(vect=164)) +void Excep_TPU5_TGI5A(void); + +// TPU5 TGI5B +#pragma interrupt (Excep_TPU5_TGI5B(vect=165)) +void Excep_TPU5_TGI5B(void); + +// TPU5 TCI5V +#pragma interrupt (Excep_TPU5_TCI5V(vect=166)) +void Excep_TPU5_TCI5V(void); + +// TPU5 TCI5U +#pragma interrupt (Excep_TPU5_TCI5U(vect=167)) +void Excep_TPU5_TCI5U(void); + +// vector 168 reserved +// vector 169 reserved + +// POE OEI1 +#pragma interrupt (Excep_POE_OEI1(vect=170)) +void Excep_POE_OEI1(void); + +// POE OEI2 +#pragma interrupt (Excep_POE_OEI2(vect=171)) +void Excep_POE_OEI2(void); + +// vector 172 reserved +// vector 173 reserved + +// TMR0 CMIA0 +// Used by the FreeRTOS demo. +//#pragma interrupt (Excep_TMR0_CMIA0(vect=174)) +//void Excep_TMR0_CMIA0(void); + +// TMR0 CMIB0 +#pragma interrupt (Excep_TMR0_CMIB0(vect=175)) +void Excep_TMR0_CMIB0(void); + +// TMR0 OVI0 +#pragma interrupt (Excep_TMR0_OVI0(vect=176)) +void Excep_TMR0_OVI0(void); + +// TMR1 CMIA1 +#pragma interrupt (Excep_TMR1_CMIA1(vect=177)) +void Excep_TMR1_CMIA1(void); + +// TMR1 CMIB1 +#pragma interrupt (Excep_TMR1_CMIB1(vect=178)) +void Excep_TMR1_CMIB1(void); + +// TMR1 OVI1 +#pragma interrupt (Excep_TMR1_OVI1(vect=179)) +void Excep_TMR1_OVI1(void); + +// TMR2 CMIA2 +// Used by teh FreeRTOS demo. +//#pragma interrupt (Excep_TMR2_CMIA2(vect=180)) +//void Excep_TMR2_CMIA2(void); + +// TMR2 CMIB2 +#pragma interrupt (Excep_TMR2_CMIB2(vect=181)) +void Excep_TMR2_CMIB2(void); + +// TMR2 OVI2 +#pragma interrupt (Excep_TMR2_OVI2(vect=182)) +void Excep_TMR2_OVI2(void); + +// TMR3 CMIA3 +#pragma interrupt (Excep_TMR3_CMIA3(vect=183)) +void Excep_TMR3_CMIA3(void); + +// TMR3 CMIB3 +#pragma interrupt (Excep_TMR3_CMIB3(vect=184)) +void Excep_TMR3_CMIB3(void); + +// TMR3 OVI3 +#pragma interrupt (Excep_TMR3_OVI3(vect=185)) +void Excep_TMR3_OVI3(void); + +// vector 186 reserved +// vector 187 reserved +// vector 188 reserved +// vector 189 reserved +// vector 190 reserved +// vector 191 reserved +// vector 192 reserved +// vector 193 reserved +// vector 194 reserved +// vector 195 reserved +// vector 196 reserved +// vector 197 reserved + +// DMAC DMAC0I +#pragma interrupt (Excep_DMAC_DMAC0I(vect=198)) +void Excep_DMAC_DMAC0I(void); + +// DMAC DMAC1I +#pragma interrupt (Excep_DMAC_DMAC1I(vect=199)) +void Excep_DMAC_DMAC1I(void); + +// DMAC DMAC2I +#pragma interrupt (Excep_DMAC_DMAC2I(vect=200)) +void Excep_DMAC_DMAC2I(void); + +// DMAC DMAC3I +#pragma interrupt (Excep_DMAC_DMAC3I(vect=201)) +void Excep_DMAC_DMAC3I(void); + +// vector 202 reserved +// vector 203 reserved +// vector 204 reserved +// vector 205 reserved +// vector 206 reserved +// vector 207 reserved +// vector 208 reserved +// vector 209 reserved +// vector 210 reserved +// vector 211 reserved +// vector 212 reserved +// vector 213 reserved + +// SCI0 ERI0 +#pragma interrupt (Excep_SCI0_ERI0(vect=214)) +void Excep_SCI0_ERI0(void); + +// SCI0 RXI0 +#pragma interrupt (Excep_SCI0_RXI0(vect=215)) +void Excep_SCI0_RXI0(void); + +// SCI0 TXI0 +#pragma interrupt (Excep_SCI0_TXI0(vect=216)) +void Excep_SCI0_TXI0(void); + +// SCI0 TEI0 +#pragma interrupt (Excep_SCI0_TEI0(vect=217)) +void Excep_SCI0_TEI0(void); + +// SCI1 ERI1 +#pragma interrupt (Excep_SCI1_ERI1(vect=218)) +void Excep_SCI1_ERI1(void); + +// SCI1 RXI1 +#pragma interrupt (Excep_SCI1_RXI1(vect=219)) +void Excep_SCI1_RXI1(void); + +// SCI1 TXI1 +#pragma interrupt (Excep_SCI1_TXI1(vect=220)) +void Excep_SCI1_TXI1(void); + +// SCI1 TEI1 +#pragma interrupt (Excep_SCI1_TEI1(vect=221)) +void Excep_SCI1_TEI1(void); + +// SCI5 ERI5 +#pragma interrupt (Excep_SCI5_ERI5(vect=222)) +void Excep_SCI5_ERI5(void); + +// SCI5 RXI5 +#pragma interrupt (Excep_SCI5_RXI5(vect=223)) +void Excep_SCI5_RXI5(void); + +// SCI5 TXI5 +#pragma interrupt (Excep_SCI5_TXI5(vect=224)) +void Excep_SCI5_TXI5(void); + +// SCI5 TEI5 +#pragma interrupt (Excep_SCI5_TEI5(vect=225)) +void Excep_SCI5_TEI5(void); + +// SCI6 ERI6 +#pragma interrupt (Excep_SCI6_ERI6(vect=226)) +void Excep_SCI6_ERI6(void); + +// SCI6 RXI6 +#pragma interrupt (Excep_SCI6_RXI6(vect=227)) +void Excep_SCI6_RXI6(void); + +// SCI6 TXI6 +#pragma interrupt (Excep_SCI6_TXI6(vect=228)) +void Excep_SCI6_TXI6(void); + +// SCI6 TEI6 +#pragma interrupt (Excep_SCI6_TEI6(vect=229)) +void Excep_SCI6_TEI6(void); + +// SCI8 ERI8 +#pragma interrupt (Excep_SCI8_ERI8(vect=230)) +void Excep_SCI8_ERI8(void); + +// SCI8 RXI8 +#pragma interrupt (Excep_SCI8_RXI8(vect=231)) +void Excep_SCI8_RXI8(void); + +// SCI8 TXI8 +#pragma interrupt (Excep_SCI8_TXI8(vect=232)) +void Excep_SCI8_TXI8(void); + +// SCI8 TEI8 +#pragma interrupt (Excep_SCI8_TEI8(vect=233)) +void Excep_SCI8_TEI8(void); + +// SCI9 ERI9 +#pragma interrupt (Excep_SCI9_ERI9(vect=234)) +void Excep_SCI9_ERI9(void); + +// SCI9 RXI9 +#pragma interrupt (Excep_SCI9_RXI9(vect=235)) +void Excep_SCI9_RXI9(void); + +// SCI9 TXI9 +#pragma interrupt (Excep_SCI9_TXI9(vect=236)) +void Excep_SCI9_TXI9(void); + +// SCI9 TEI9 +#pragma interrupt (Excep_SCI9_TEI9(vect=237)) +void Excep_SCI9_TEI9(void); + +// SCI12 ERI12 +#pragma interrupt (Excep_SCI12_ERI12(vect=238)) +void Excep_SCI12_ERI12(void); + +// SCI12 RXI12 +#pragma interrupt (Excep_SCI12_RXI12(vect=239)) +void Excep_SCI12_RXI12(void); + +// SCI12 TXI12 +#pragma interrupt (Excep_SCI12_TXI12(vect=240)) +void Excep_SCI12_TXI12(void); + +// SCI12 TEI12 +#pragma interrupt (Excep_SCI12_TEI12(vect=241)) +void Excep_SCI12_TEI12(void); + +// SCI12 SCIX0 +#pragma interrupt (Excep_SCI12_SCIX0(vect=242)) +void Excep_SCI12_SCIX0(void); + +// SCI12 SCIX1 +#pragma interrupt (Excep_SCI12_SCIX1(vect=243)) +void Excep_SCI12_SCIX1(void); + +// SCI12 SCIX2 +#pragma interrupt (Excep_SCI12_SCIX2(vect=244)) +void Excep_SCI12_SCIX2(void); + +// SCI12 SCIX3 +#pragma interrupt (Excep_SCI12_SCIX3(vect=245)) +void Excep_SCI12_SCIX3(void); + +// RIIC0 EEI0 +#pragma interrupt (Excep_RIIC0_EEI0(vect=246)) +void Excep_RIIC0_EEI0(void); + +// RIIC0 RXI0 +#pragma interrupt (Excep_RIIC0_RXI0(vect=247)) +void Excep_RIIC0_RXI0(void); + +// RIIC0 TXI0 +#pragma interrupt (Excep_RIIC0_TXI0(vect=248)) +void Excep_RIIC0_TXI0(void); + +// RIIC0 TEI0 +#pragma interrupt (Excep_RIIC0_TEI0(vect=249)) +void Excep_RIIC0_TEI0(void); + +// vector 250 reserved +// vector 251 reserved +// vector 252 reserved +// vector 253 reserved +// vector 254 reserved +// vector 255 reserved + +//;<> +//;Power On Reset PC +extern void PowerON_Reset_PC(void); +//;<> diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_cgc.c b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_cgc.c new file mode 100644 index 000000000..7a23f21fe --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_cgc.c @@ -0,0 +1,115 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cgc.c +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : CCRX +* Description : This file implements device driver for CGC module. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_CGC_Create +* Description : This function initializes the clock generator. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_CGC_Create(void) +{ + uint32_t sckcr_dummy; + volatile uint32_t memorywaitcycle; + + /* Set main clock control registers */ + SYSTEM.MOFCR.BYTE = _00_CGC_MAINOSC_RESONATOR | _00_CGC_MAINOSC_UNDER10M; + SYSTEM.MOSCWTCR.BYTE = _06_CGC_OSC_WAIT_CYCLE_32768; + + /* Set main clock operation */ + SYSTEM.MOSCCR.BIT.MOSTP = 0U; + + /* Wait for main clock oscillator wait counter overflow */ + while (1U != SYSTEM.OSCOVFSR.BIT.MOOVF); + + /* Set system clock */ + sckcr_dummy = _00000000_CGC_PCLKD_DIV_1 | _00000100_CGC_PCLKB_DIV_2 | _00001000_CGC_PCLKA_DIV_2 | + _00010000_CGC_BCLK_DIV_2 | _00000000_CGC_ICLK_DIV_1 | _10000000_CGC_FCLK_DIV_2; + SYSTEM.SCKCR.LONG = sckcr_dummy; + + while (SYSTEM.SCKCR.LONG != sckcr_dummy); + + /* Set PLL circuit */ + SYSTEM.PLLCR.WORD = _0000_CGC_PLL_FREQ_DIV_1 | _0C00_CGC_PLL_FREQ_MUL_6_5; + SYSTEM.PLLCR2.BIT.PLLEN = 0U; + + /* Wait for PLL wait counter overflow */ + while (1U != SYSTEM.OSCOVFSR.BIT.PLOVF); + + /* Disable sub-clock */ + SYSTEM.SOSCCR.BIT.SOSTP = 1U; + + /* Wait for the register modification to complete */ + while (1U != SYSTEM.SOSCCR.BIT.SOSTP); + + /* Disable sub-clock */ + RTC.RCR3.BIT.RTCEN = 0U; + + /* Wait for the register modification to complete */ + while (0U != RTC.RCR3.BIT.RTCEN); + + /* Set BCLK */ + SYSTEM.SCKCR.BIT.PSTOP1 = 1U; + + /* Set memory wait cycle setting register */ + SYSTEM.MEMWAIT.BIT.MEMWAIT = 1U; + memorywaitcycle = SYSTEM.MEMWAIT.BYTE; + memorywaitcycle++; + + /* Set clock source */ + SYSTEM.SCKCR3.WORD = _0400_CGC_CLOCKSOURCE_PLL; + + while (SYSTEM.SCKCR3.WORD != _0400_CGC_CLOCKSOURCE_PLL); + + /* Set LOCO */ + SYSTEM.LOCOCR.BIT.LCSTP = 1U; +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_cgc.h b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_cgc.h new file mode 100644 index 000000000..59e2c6850 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_cgc.h @@ -0,0 +1,227 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cgc.h +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : CCRX +* Description : This file implements device driver for CGC module. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ +#ifndef CGC_H +#define CGC_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ +/* + System Clock Control Register (SCKCR) +*/ +/* Peripheral Module Clock D (PCLKD) */ +#define _00000000_CGC_PCLKD_DIV_1 (0x00000000UL) /* x1 */ +#define _00000001_CGC_PCLKD_DIV_2 (0x00000001UL) /* x1/2 */ +#define _00000002_CGC_PCLKD_DIV_4 (0x00000002UL) /* x1/4 */ +#define _00000003_CGC_PCLKD_DIV_8 (0x00000003UL) /* x1/8 */ +#define _00000004_CGC_PCLKD_DIV_16 (0x00000004UL) /* x1/16 */ +#define _00000005_CGC_PCLKD_DIV_32 (0x00000005UL) /* x1/32 */ +#define _00000006_CGC_PCLKD_DIV_64 (0x00000006UL) /* x1/64 */ +/* Peripheral Module Clock B (PCLKB) */ +#define _00000000_CGC_PCLKB_DIV_1 (0x00000000UL) /* x1 */ +#define _00000100_CGC_PCLKB_DIV_2 (0x00000100UL) /* x1/2 */ +#define _00000200_CGC_PCLKB_DIV_4 (0x00000200UL) /* x1/4 */ +#define _00000300_CGC_PCLKB_DIV_8 (0x00000300UL) /* x1/8 */ +#define _00000400_CGC_PCLKB_DIV_16 (0x00000400UL) /* x1/16 */ +#define _00000500_CGC_PCLKB_DIV_32 (0x00000500UL) /* x1/32 */ +#define _00000600_CGC_PCLKB_DIV_64 (0x00000600UL) /* x1/64 */ +/* Peripheral Module Clock A (PCLKA) */ +#define _00000000_CGC_PCLKA_DIV_1 (0x00000000UL) /* x1 */ +#define _00001000_CGC_PCLKA_DIV_2 (0x00001000UL) /* x1/2 */ +#define _00002000_CGC_PCLKA_DIV_4 (0x00002000UL) /* x1/4 */ +#define _00003000_CGC_PCLKA_DIV_8 (0x00003000UL) /* x1/8 */ +#define _00004000_CGC_PCLKA_DIV_16 (0x00004000UL) /* x1/16 */ +#define _00005000_CGC_PCLKA_DIV_32 (0x00005000UL) /* x1/32 */ +#define _00006000_CGC_PCLKA_DIV_64 (0x00006000UL) /* x1/64 */ +/* External Bus Clock (BCLK) */ +#define _00000000_CGC_BCLK_DIV_1 (0x00000000UL) /* x1 */ +#define _00010000_CGC_BCLK_DIV_2 (0x00010000UL) /* x1/2 */ +#define _00020000_CGC_BCLK_DIV_4 (0x00020000UL) /* x1/4 */ +#define _00030000_CGC_BCLK_DIV_8 (0x00030000UL) /* x1/8 */ +#define _00040000_CGC_BCLK_DIV_16 (0x00040000UL) /* x1/16 */ +#define _00050000_CGC_BCLK_DIV_32 (0x00050000UL) /* x1/32 */ +#define _00060000_CGC_BCLK_DIV_64 (0x00060000UL) /* x1/64 */ +/* System Clock (ICLK) */ +#define _00000000_CGC_ICLK_DIV_1 (0x00000000UL) /* x1 */ +#define _01000000_CGC_ICLK_DIV_2 (0x01000000UL) /* x1/2 */ +#define _02000000_CGC_ICLK_DIV_4 (0x02000000UL) /* x1/4 */ +#define _03000000_CGC_ICLK_DIV_8 (0x03000000UL) /* x1/8 */ +#define _04000000_CGC_ICLK_DIV_16 (0x04000000UL) /* x1/16 */ +#define _05000000_CGC_ICLK_DIV_32 (0x05000000UL) /* x1/32 */ +#define _06000000_CGC_ICLK_DIV_64 (0x06000000UL) /* x1/64 */ +/* System Clock (FCLK) */ +#define _00000000_CGC_FCLK_DIV_1 (0x00000000UL) /* x1 */ +#define _10000000_CGC_FCLK_DIV_2 (0x10000000UL) /* x1/2 */ +#define _20000000_CGC_FCLK_DIV_4 (0x20000000UL) /* x1/4 */ +#define _30000000_CGC_FCLK_DIV_8 (0x30000000UL) /* x1/8 */ +#define _40000000_CGC_FCLK_DIV_16 (0x40000000UL) /* x1/16 */ +#define _50000000_CGC_FCLK_DIV_32 (0x50000000UL) /* x1/32 */ +#define _60000000_CGC_FCLK_DIV_64 (0x60000000UL) /* x1/64 */ + +/* + System Clock Control Register 3 (SCKCR3) +*/ +#define _0000_CGC_CLOCKSOURCE_LOCO (0x0000U) /* LOCO */ +#define _0100_CGC_CLOCKSOURCE_HOCO (0x0100U) /* HOCO */ +#define _0200_CGC_CLOCKSOURCE_MAINCLK (0x0200U) /* Main clock oscillator */ +#define _0300_CGC_CLOCKSOURCE_SUBCLK (0x0300U) /* Sub-clock oscillator */ +#define _0400_CGC_CLOCKSOURCE_PLL (0x0400U) /* PLL circuit */ + +/* + PLL Control Register (PLLCR) +*/ +/* PLL Input Frequency Division Ratio Select (PLIDIV[1:0]) */ +#define _0000_CGC_PLL_FREQ_DIV_1 (0x0000U) /* x1 */ +#define _0001_CGC_PLL_FREQ_DIV_2 (0x0001U) /* x1/2 */ +#define _0002_CGC_PLL_FREQ_DIV_4 (0x0002U) /* x1/4 */ +/* Frequency Multiplication Factor Select (STC[5:0]) */ +#define _0700_CGC_PLL_FREQ_MUL_4_0 (0x0700U) /* x4 */ +#define _0800_CGC_PLL_FREQ_MUL_4_5 (0x0800U) /* x4.5 */ +#define _0900_CGC_PLL_FREQ_MUL_5_0 (0x0900U) /* x5 */ +#define _0A00_CGC_PLL_FREQ_MUL_5_5 (0x0A00U) /* x5.5 */ +#define _0B00_CGC_PLL_FREQ_MUL_6_0 (0x0B00U) /* x6 */ +#define _0C00_CGC_PLL_FREQ_MUL_6_5 (0x0C00U) /* x6.5 */ +#define _0D00_CGC_PLL_FREQ_MUL_7_0 (0x0D00U) /* x7 */ +#define _0E00_CGC_PLL_FREQ_MUL_7_5 (0x0E00U) /* x7.5 */ +#define _0F00_CGC_PLL_FREQ_MUL_8_0 (0x0F00U) /* x8 */ +#define _1000_CGC_PLL_FREQ_MUL_8_5 (0x1000U) /* x8.5 */ +#define _1100_CGC_PLL_FREQ_MUL_9_0 (0x1100U) /* x9 */ +#define _1200_CGC_PLL_FREQ_MUL_9_5 (0x1200U) /* x9.5 */ +#define _1300_CGC_PLL_FREQ_MUL_10_0 (0x1300U) /* x10 */ +#define _1400_CGC_PLL_FREQ_MUL_10_5 (0x1400U) /* x10.5 */ +#define _1500_CGC_PLL_FREQ_MUL_11_0 (0x1500U) /* x11 */ +#define _1600_CGC_PLL_FREQ_MUL_11_5 (0x1600U) /* 11.5 */ +#define _1700_CGC_PLL_FREQ_MUL_12_0 (0x1700U) /* x12 */ +#define _1800_CGC_PLL_FREQ_MUL_12_5 (0x1800U) /* x12.5 */ +#define _1900_CGC_PLL_FREQ_MUL_13_0 (0x1900U) /* x13 */ +#define _1A00_CGC_PLL_FREQ_MUL_13_5 (0x1A00U) /* x13.5 */ +/* + USB-dedicated PLL Control Register (UPLLCR) +*/ +/* USB-dedicated PLL Input Frequency Division Ratio Select (UPLIDIV[1:0]) */ +#define _0000_CGC_UPLL_DIV_1 (0x0000U) /* x1 */ +#define _0001_CGC_UPLL_DIV_2 (0x0001U) /* x1/2 */ +#define _0002_CGC_UPLL_DIV_4 (0x0002U) /* x1/4 */ +/* UCLK Source USB-Dedicated PLL Select (UCKUPLLSEL) */ +#define _0000_CGC_UCLK_SYSCLK (0x0000U) /* System clock is selected as UCLK */ +#define _0010_CGC_UCLK_USBPLL (0x0010U) /* USB-dedicated PLL is selected as UCLK */ +/* Frequency Multiplication Factor Select (USTC[5:0]) */ +#define _0700_CGC_UPLL_MUL_4 (0x0700U) /* x4 */ +#define _0B00_CGC_UPLL_MUL_6 (0x0B00U) /* x6 */ +#define _0F00_CGC_UPLL_MUL_8 (0x0F00U) /* x8 */ +#define _1700_CGC_UPLL_MUL_12 (0x1700U) /* x12 */ + +/* + High-Speed On-Chip Oscillator Control Register 2 (HOCOCR2) +*/ +/* HOCO Frequency Setting (HCFRQ[1:0]) */ +#define _00_CGC_HOCO_CLK_32 (0x00U) /* 32 MHz */ +#define _03_CGC_HOCO_CLK_54 (0x03U) /* 54 MHz */ + +/* + Oscillation Stop Detection Control Register (OSTDCR) +*/ +/* Oscillation Stop Detection Interrupt Enable (OSTDIE) */ +#define _00_CGC_OSC_STOP_INT_DISABLE (0x00U) /* The oscillation stop detection interrupt is disabled */ +#define _01_CGC_OSC_STOP_INT_ENABLE (0x01U) /* The oscillation stop detection interrupt is enabled */ +/* Oscillation Stop Detection Function Enable (OSTDE) */ +#define _00_CGC_OSC_STOP_DISABLE (0x00U) /* Oscillation stop detection function is disabled */ +#define _80_CGC_OSC_STOP_ENABLE (0x80U) /* Oscillation stop detection function is enabled */ + +/* + Main Clock Oscillator Wait Control Register (MOSCWTCR) +*/ +/* Main Clock Oscillator Wait Time (MSTS[4:0]) */ +#define _00_CGC_OSC_WAIT_CYCLE_2 (0x00U) /* Wait time = 2 cycles */ +#define _01_CGC_OSC_WAIT_CYCLE_1024 (0x01U) /* Wait time = 1024 cycles */ +#define _02_CGC_OSC_WAIT_CYCLE_2048 (0x02U) /* Wait time = 2048 cycles */ +#define _03_CGC_OSC_WAIT_CYCLE_4096 (0x03U) /* Wait time = 4096 cycles */ +#define _04_CGC_OSC_WAIT_CYCLE_8192 (0x04U) /* Wait time = 8192 cycles */ +#define _05_CGC_OSC_WAIT_CYCLE_16384 (0x05U) /* Wait time = 16384 cycles */ +#define _06_CGC_OSC_WAIT_CYCLE_32768 (0x06U) /* Wait time = 32768 cycles */ +#define _07_CGC_OSC_WAIT_CYCLE_65536 (0x07U) /* Wait time = 65536 cycles */ + +/* + Clock Output Control Register (CKOCR) +*/ +/* Clock Output Source Select (CKOSEL[2:0]) */ +#define _0000_CGC_CLKOUT_LOCO (0x0000U) /* LOCO */ +#define _0100_CGC_CLKOUT_HOCO (0x0100U) /* HOCO */ +#define _0200_CGC_CLKOUT_MAINCLK (0x0200U) /* Main clock oscillator */ +#define _0300_CGC_CLKOUT_SUBCLK (0x0300U) /* Sub-clock oscillator */ +#define _0400_CGC_CLKOUT_PLLCLK (0x0400U) /* PLL clock oscillator */ +/* Clock Output Division Ratio Select (CKODIV[2:0]) */ +#define _0000_CGC_CLKOUT_DIV_1 (0x0000U) /* x1 */ +#define _1000_CGC_CLKOUT_DIV_2 (0x1000U) /* x1/2 */ +#define _2000_CGC_CLKOUT_DIV_4 (0x2000U) /* x1/4 */ +#define _3000_CGC_CLKOUT_DIV_8 (0x3000U) /* x1/8 */ +#define _4000_CGC_CLKOUT_DIV_16 (0x4000U) /* x1/16 */ +/* Clock Output Control (CKOSTP) */ +#define _0000_CGC_CLKOUT_ENABLE (0x0000U) /* CLKOUT pin output is operating */ +#define _8000_CGC_CLKOUT_DISABLE (0x8000U) /* CLKOUT pin output is stopped (fixed at low level) */ + +/* + Main Clock Oscillator Forced Oscillation Control Register (MOFCR) +*/ +/* Main Oscillator Drive Capability Switch (MODRV21) */ +#define _00_CGC_MAINOSC_UNDER10M (0x00U) /* 1 MHz to 10 MHz */ +#define _20_CGC_MAINOSC_OVER10M (0x20U) /* 10 MHz to 20 MHz */ +/* Main Clock Oscillator Switch (MOSEL) */ +#define _00_CGC_MAINOSC_RESONATOR (0x00U) /* Resonator */ +#define _40_CGC_MAINOSC_EXTERNAL (0x40U) /* External oscillator input */ + +/* + Low-power timer control register 1 (LPTCR1) +*/ +/* Low-Power Timer Clock Division Ratio Select (LPCNTPSSEL[2:0]) */ +#define _01_CGC_LPT_CLK_DIV_2 (0x01U) /* x1/2 */ +#define _02_CGC_LPT_CLK_DIV_4 (0x02U) /* x1/4 */ +#define _03_CGC_LPT_CLK_DIV_8 (0x03U) /* x1/8 */ +#define _04_CGC_LPT_CLK_DIV_16 (0x04U) /* x1/16 */ +#define _05_CGC_LPT_CLK_DIV_32 (0x05U) /* x1/32 */ +/* Low-Power Timer Clock Source Select (LPCNTCKSEL) */ +#define _00_CGC_LPT_SOURCE_SUB (0x00U) /* Sub-clock */ +#define _10_CGC_LPT_SOURCE_IWDT (0x10U) /* IWDT-dedicated on-chip */ + + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_CGC_Create(void); + +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_cgc_user.c b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_cgc_user.c new file mode 100644 index 000000000..4b653fff0 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_cgc_user.c @@ -0,0 +1,52 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cgc_user.c +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : CCRX +* Description : This file implements device driver for CGC module. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_dbsct.c b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_dbsct.c new file mode 100644 index 000000000..430cda236 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_dbsct.c @@ -0,0 +1,84 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_dbsct.c +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : CCRX +* Description : Setting of B. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ + +#pragma unpack + +#pragma section C C$DSEC +extern const struct { + uint8_t *rom_s; /* Start address of the initialized data section in ROM */ + uint8_t *rom_e; /* End address of the initialized data section in ROM */ + uint8_t *ram_s; /* Start address of the initialized data section in RAM */ +} _DTBL[] = { + { __sectop("D"), __secend("D"), __sectop("R") }, + { __sectop("D_2"), __secend("D_2"), __sectop("R_2") }, + { __sectop("D_1"), __secend("D_1"), __sectop("R_1") } +}; +#pragma section C C$BSEC +extern const struct { + uint8_t *b_s; /* Start address of non-initialized data section */ + uint8_t *b_e; /* End address of non-initialized data section */ +} _BTBL[] = { + { __sectop("B"), __secend("B") }, + { __sectop("B_2"), __secend("B_2") }, + { __sectop("B_1"), __secend("B_1") } +}; + +#pragma section + +/* +** CTBL prevents excessive output of L1100 messages when linking. +** Even if CTBL is deleted, the operation of the program does not change. +*/ +uint8_t * const _CTBL[] = { + __sectop("C_1"), __sectop("C_2"), __sectop("C"), + __sectop("W_1"), __sectop("W_2"), __sectop("W"), + __sectop("L"), __sectop("SU"), + __sectop("C$DSEC"), __sectop("C$BSEC"), + __sectop("C$INIT"), __sectop("C$VTBL"), __sectop("C$VECT") +}; + +#pragma packoption + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_hardware_setup.c b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_hardware_setup.c new file mode 100644 index 000000000..30fdc9df3 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_hardware_setup.c @@ -0,0 +1,87 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_hardware_setup.c +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : CCRX +* Description : This file implements system initializing function. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_Systeminit +* Description : This function initializes every macro. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_Systeminit(void) +{ + /* Enable writing to registers related to operating modes, LPC, LPT, LVD, CGC and software reset */ + SYSTEM.PRCR.WORD = 0xA50FU; + + /* Enable writing to MPC pin function control registers */ + MPC.PWPR.BIT.B0WI = 0U; + MPC.PWPR.BIT.PFSWE = 1U; + + /* Set peripheral settings */ + R_CGC_Create(); + + /* Disable writing to MPC pin function control registers */ + MPC.PWPR.BIT.PFSWE = 0U; + MPC.PWPR.BIT.B0WI = 1U; + + /* Enable protection */ + SYSTEM.PRCR.WORD = 0xA500U; +} +/*********************************************************************************************************************** +* Function Name: HardwareSetup +* Description : This function initializes hardware setting. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void HardwareSetup(void) +{ + R_Systeminit(); +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_intprg.c b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_intprg.c new file mode 100644 index 000000000..2343d7c46 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_intprg.c @@ -0,0 +1,99 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_intprg.c +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : CCRX +* Description : Setting of B. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include +#include "r_cg_vect.h" +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ + +#pragma section IntPRG + +/* Undefined Instruction Exception */ +void r_undefined_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* Privileged Instruction Exception */ +void r_privileged_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* Floating Point Exception */ +void r_floatingpoint_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* Access Exception */ +void r_access_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* Reserved */ +void r_reserved_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* NMI */ +void r_nmi_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* BRK */ +void r_brk_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_macrodriver.h b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_macrodriver.h new file mode 100644 index 000000000..fde1c5181 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_macrodriver.h @@ -0,0 +1,100 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_macrodriver.h +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : CCRX +* Description : This file implements general head file. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ +#ifndef MODULEID_H +#define MODULEID_H +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "../iodefine.h" +#include + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#ifndef __TYPEDEF__ + +/* Status list definition */ +#define MD_STATUSBASE (0x00U) +#define MD_OK (MD_STATUSBASE + 0x00U) /* register setting OK */ +#define MD_SPT (MD_STATUSBASE + 0x01U) /* IIC stop */ +#define MD_NACK (MD_STATUSBASE + 0x02U) /* IIC no ACK */ +#define MD_BUSY1 (MD_STATUSBASE + 0x03U) /* busy 1 */ +#define MD_BUSY2 (MD_STATUSBASE + 0x04U) /* busy 2 */ + +/* Error list definition */ +#define MD_ERRORBASE (0x80U) +#define MD_ERROR (MD_ERRORBASE + 0x00U) /* error */ +#define MD_ARGERROR (MD_ERRORBASE + 0x01U) /* error argument input error */ +#define MD_ERROR1 (MD_ERRORBASE + 0x02U) /* error 1 */ +#define MD_ERROR2 (MD_ERRORBASE + 0x03U) /* error 2 */ +#define MD_ERROR3 (MD_ERRORBASE + 0x04U) /* error 3 */ +#define MD_ERROR4 (MD_ERRORBASE + 0x05U) /* error 4 */ +#define MD_ERROR5 (MD_ERRORBASE + 0x06U) /* error 5 */ + +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +#ifndef __TYPEDEF__ + #ifndef _STD_USING_INT_TYPES + #define _SYS_INT_TYPES_H + #ifndef _STD_USING_BIT_TYPES + #define __int8_t_defined + typedef signed char int8_t; + typedef signed short int16_t; + #endif + + typedef unsigned char uint8_t; + typedef unsigned short uint16_t; + typedef signed long int32_t; + typedef unsigned long uint32_t; + + typedef signed char int_least8_t; + typedef signed short int_least16_t; + typedef signed long int_least32_t; + typedef unsigned char uint_least8_t; + typedef unsigned short uint_least16_t; + typedef unsigned long uint_least32_t; + #endif + + typedef unsigned short MD_STATUS; + #define __TYPEDEF__ +#endif + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void HardwareSetup(void); +void R_Systeminit(void); + +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_main.c b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_main.c new file mode 100644 index 000000000..d8ae57956 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_main.c @@ -0,0 +1,90 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_main.c +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : CCRX +* Description : This file implements main function. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + + +void R_MAIN_UserInit(void); +/*********************************************************************************************************************** +* Function Name: main +* Description : This function implements main function. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void main(void) +{ + R_MAIN_UserInit(); + /* Start user code. Do not edit comment generated here */ + while (1U) + { + ; + } + /* End user code. Do not edit comment generated here */ +} +/*********************************************************************************************************************** +* Function Name: R_MAIN_UserInit +* Description : This function adds user code before implementing main function. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_MAIN_UserInit(void) +{ + /* Start user code. Do not edit comment generated here */ + uint16_t protect_dummy = (uint16_t)(SYSTEM.PRCR.WORD & 0x000FU); + + /* Disable protect bit */ + SYSTEM.PRCR.WORD = 0xA50FU; + + SYSTEM.VBATTCR.BYTE = 0x81U; + + /* Restore the previous state of the protect register */ + SYSTEM.PRCR.WORD = (uint16_t)(0xA500U | protect_dummy); + /* End user code. Do not edit comment generated here */ +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_resetprg.c b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_resetprg.c new file mode 100644 index 000000000..d8b14c896 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_resetprg.c @@ -0,0 +1,94 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_resetprg.c +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : CCRX +* Description : Reset program. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include +#include <_h_c_lib.h> +//#include // Remove the comment when you use errno +//#include // Remove the comment when you use rand() +#include "r_cg_stacksct.h" +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif +void PowerON_Reset_PC(void); +void main(void); +#ifdef __cplusplus +} +#endif + +#define PSW_init 0x00010000 /* PSW bit pattern */ +#define FPSW_init 0x00000000 /* FPSW bit base pattern */ + +#pragma section ResetPRG /* output PowerON_Reset_PC to PResetPRG section */ + +#pragma entry PowerON_Reset_PC + +void PowerON_Reset_PC(void) +{ +#ifdef __RXV2 + set_extb(__sectop("EXCEPTVECT")); +#endif + set_intb(__sectop("C$VECT")); + +#ifdef __ROZ /* Initialize FPSW */ +#define _ROUND 0x00000001 /* Let FPSW RMbits=01 (round to zero) */ +#else +#define _ROUND 0x00000000 /* Let FPSW RMbits=00 (round to nearest) */ +#endif +#ifdef __DOFF +#define _DENOM 0x00000100 /* Let FPSW DNbit=1 (denormal as zero) */ +#else +#define _DENOM 0x00000000 /* Let FPSW DNbit=0 (denormal as is) */ +#endif + + set_fpsw(FPSW_init | _ROUND | _DENOM); + + _INITSCT(); /* Initialize Sections */ + HardwareSetup(); /* Use Hardware Setup */ + nop(); + set_psw(PSW_init); /* Set Ubit & Ibit for PSW */ + main(); + brk(); +} +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_sbrk.c b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_sbrk.c new file mode 100644 index 000000000..2d118c276 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_sbrk.c @@ -0,0 +1,86 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_sbrk.c +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : CCRX +* Description : Program of sbrk. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include +#include +#include "r_cg_sbrk.h" +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ + +int8_t *sbrk(size_t size); + +extern int8_t *_s1ptr; + +union HEAP_TYPE +{ + int16_t dummy ; /* Dummy for 4-byte boundary */ + int8_t heap[HEAPSIZE]; /* Declaration of the area managed by sbrk */ +}; + +static union HEAP_TYPE heap_area ; + +/* End address allocated by sbrk */ +static int8_t *brk = (int8_t *) &heap_area; + +/**************************************************************************/ +/* sbrk:Memory area allocation */ +/* Return value:Start address of allocated area (Pass) */ +/* -1 (Failure) */ +/**************************************************************************/ +int8_t *sbrk(size_t size) /* Assigned area size */ +{ + int8_t *p; + + if (brk+size > heap_area.heap + HEAPSIZE) /* Empty area size */ + { + p = (int8_t *)-1; + } + else + { + p = brk; /* Area assignment */ + brk += size; /* End address update */ + } + + return p; +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_sbrk.h b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_sbrk.h new file mode 100644 index 000000000..dc14a2132 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_sbrk.h @@ -0,0 +1,48 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_sbrk.h +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : CCRX +* Description : Header file of sbrk file. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ +#ifndef _SBRK_H +#define _SBRK_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +#define HEAPSIZE (0x400U) /* Size of area managed by sbrk */ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ + +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_stacksct.h b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_stacksct.h new file mode 100644 index 000000000..40a247509 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_stacksct.h @@ -0,0 +1,50 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_stacksct.h +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : CCRX +* Description : Setting of Stack area. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ +#ifndef _STACKSCT_H +#define _STACKSCT_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +#pragma stacksize su = 0x100 +#pragma stacksize si = 0x300 + + +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_userdefine.h b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_userdefine.h new file mode 100644 index 000000000..767d34492 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_userdefine.h @@ -0,0 +1,38 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_userdefine.h +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : CCRX +* Description : This file includes user definition. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ +#ifndef _USER_DEF_H +#define _USER_DEF_H + +/*********************************************************************************************************************** +User definitions +***********************************************************************************************************************/ +#define FAST_INTERRUPT_VECTOR 0 + +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_vect.h b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_vect.h new file mode 100644 index 000000000..49c995016 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_vect.h @@ -0,0 +1,79 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_vect.h +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : CCRX +* Description : This file contains definition of vector. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ +#ifndef _VECT_H +#define _VECT_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +/* Undefined */ +#pragma interrupt (r_undefined_exception) +void r_undefined_exception(void); + +/* Access Exception */ +#pragma interrupt (r_access_exception) +void r_access_exception(void); + +/* Privileged Instruction Exception */ +#pragma interrupt (r_privileged_exception) +void r_privileged_exception(void); + +/* Floating Point Exception */ +#pragma interrupt (r_floatingpoint_exception) +void r_floatingpoint_exception(void); + +/* Reserved */ +#pragma interrupt (r_reserved_exception) +void r_reserved_exception(void); + +/* NMI */ +#pragma interrupt (r_nmi_exception) +void r_nmi_exception(void); + +/* BRK */ +#pragma interrupt (r_brk_exception(vect=0)) +void r_brk_exception(void); + +/*;<> */ +/*;Power On Reset PC */ +extern void PowerON_Reset_PC(void); +/*;<> */ + +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_vecttbl.c b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_vecttbl.c new file mode 100644 index 000000000..ddfb8b3de --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_vecttbl.c @@ -0,0 +1,130 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_vecttbl.c +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : CCRX +* Description : This file initializes the vector table. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_vect.h" +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ + + +#define OFS0_VAL 0xFFFFFFFFUL +#define OFS1_VAL 0xFFFFFFFFUL + +#pragma section C EXCEPTVECT +/* Start user code for adding. Do not edit comment generated here */ +void (*const Excpt_Vectors[])(void) = { +/*;0xffffff80 MDE register */ +#ifdef __BIG + /* Big endian */ + (void (*)(void))0xfffffff8, +#else + /* Little endian */ + (void (*)(void))0xffffffff, +#endif +/*;0xffffff84 Reserved */ + r_reserved_exception, +/*;0xffffff88 OFS1 register */ + (void (*) (void)) OFS1_VAL, +/*;0xffffff8c OFS0 register */ + (void (*) (void)) OFS0_VAL, +/*;0xffffff90 Reserved */ + r_reserved_exception, +/*;0xffffff94 Reserved */ + r_reserved_exception, +/*;0xffffff98 Reserved */ + r_reserved_exception, +/*;0xffffff9c Reserved */ + r_reserved_exception, +/*;0xffffffa0 ID */ + (void (*)(void))0xffffffff, +/*;0xffffffa4 ID */ + (void (*)(void))0xffffffff, +/*;0xffffffa8 ID */ + (void (*)(void))0xffffffff, +/*;0xffffffac ID */ + (void (*)(void))0xffffffff, +/*;0xffffffb0 Reserved */ + r_reserved_exception, +/*;0xffffffb4 Reserved */ + r_reserved_exception, +/*;0xffffffb8 Reserved */ + r_reserved_exception, +/*;0xffffffbc Reserved */ + r_reserved_exception, +/*;0xffffffc0 Reserved */ + r_reserved_exception, +/*;0xffffffc4 Reserved */ + r_reserved_exception, +/*;0xffffffc8 Reserved */ + r_reserved_exception, +/*;0xffffffcc Reserved */ + r_reserved_exception, +/*;0xffffffd0 Exception(Privileged Instruction) */ + r_privileged_exception, +/*;0xffffffd4 Exception(Access) */ + r_access_exception, +/*;0xffffffd8 Reserved */ + r_reserved_exception, +/*;0xffffffdc Exception(Undefined Instruction) */ + r_undefined_exception, +/*;0xffffffe0 Reserved */ + r_reserved_exception, +/*;0xffffffe4 Exception(Floating Point) */ + r_floatingpoint_exception, +/*;0xffffffe8 Reserved */ + r_reserved_exception, +/*;0xffffffec Reserved */ + r_reserved_exception, +/*;0xfffffff0 Reserved */ + r_reserved_exception, +/*;0xfffffff4 Reserved */ + r_reserved_exception, +/*;0xfffffff8 NMI */ + r_nmi_exception, +}; +/* End user code. Do not edit comment generated here */ + +#pragma section C RESETVECT +void (*const Reset_Vectors[])(void) = { +/*;<> */ +/*;Power On Reset PC */ + /*(void*)*/ PowerON_Reset_PC +/*;<> */ +}; diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/iodefine.h b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/iodefine.h new file mode 100644 index 000000000..0e1684ea2 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/iodefine.h @@ -0,0 +1,12985 @@ +/***************************************************************/ +/* */ +/* PROJECT NAME : RTOSDemo */ +/* FILE : iodefine.h */ +/* DESCRIPTION : I/O register definitions */ +/* CPU SERIES : RX200 */ +/* CPU TYPE : RX231 */ +/* */ +/* This file is generated by e2 studio. */ +/* */ +/***************************************************************/ + + + + +/********************************************************************************* +* +* Device : RX/RX200/RX231 +* +* File Name : iodefine.h +* +* Abstract : Definition of I/O Register. +* +* History : 0.5A (2014-09-18) [Hardware Manual Revision : 0.50] +* : 1.0A (2015-05-18) [Hardware Manual Revision : 1.00] +* : 1.0C (2015-07-21) [Hardware Manual Revision : 1.00] +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright (C) 2015 (2014) Renesas Electronics Corporation. +* +*********************************************************************************/ +/********************************************************************************/ +/* */ +/* DESCRIPTION : Definition of ICU Register */ +/* CPU TYPE : RX231 */ +/* */ +/* Usage : IR,DTCER,IER,IPR of ICU Register */ +/* The following IR, DTCE, IEN, IPR macro functions simplify usage. */ +/* The bit access operation is "Bit_Name(interrupt source,name)". */ +/* A part of the name can be omitted. */ +/* for example : */ +/* IR(MTU0,TGIA0) = 0; expands to : */ +/* ICU.IR[114].BIT.IR = 0; */ +/* */ +/* DTCE(ICU,IRQ0) = 1; expands to : */ +/* ICU.DTCER[64].BIT.DTCE = 1; */ +/* */ +/* IEN(CMT0,CMI0) = 1; expands to : */ +/* ICU.IER[0x03].BIT.IEN4 = 1; */ +/* */ +/* IPR(MTU1,TGIA1) = 2; expands to : */ +/* IPR(MTU1,TGI ) = 2; // TGIA1,TGIB1 share IPR level. */ +/* ICU.IPR[121].BIT.IPR = 2; */ +/* */ +/* IPR(SCI0,ERI0) = 3; expands to : */ +/* IPR(SCI0, ) = 3; // SCI0 uses single IPR for all sources. */ +/* ICU.IPR[214].BIT.IPR = 3; */ +/* */ +/* Usage : #pragma interrupt Function_Identifier(vect=**) */ +/* The number of vector is "(interrupt source, name)". */ +/* for example : */ +/* #pragma interrupt INT_IRQ0(vect=VECT(ICU,IRQ0)) expands to : */ +/* #pragma interrupt INT_IRQ0(vect=64) */ +/* #pragma interrupt INT_CMT0_CMI0(vect=VECT(CMT0,CMI0)) expands to : */ +/* #pragma interrupt INT_CMT0_CMI0(vect=28) */ +/* #pragma interrupt INT_MTU0_TGIA0(vect=VECT(MTU0,TGIA0)) expands to : */ +/* #pragma interrupt INT_MTU0_TGIA0(vect=114) */ +/* #pragma interrupt INT_TPU0_TGI0A(vect=VECT(TPU0,TGI0A)) expands to : */ +/* #pragma interrupt INT_TPU0_TGI0A(vect=142) */ +/* */ +/* Usage : MSTPCRA,MSTPCRB,MSTPCRC of SYSTEM Register */ +/* The bit access operation is "MSTP(name)". */ +/* The name that can be used is a macro name defined with "iodefine.h". */ +/* for example : */ +/* MSTP(TMR2) = 0; // TMR2,TMR3,TMR23 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; */ +/* MSTP(SCI0) = 0; // SCI0,SMCI0 expands to : */ +/* SYSTEM.MSTPCRB.BIT.MSTPB31 = 0; */ +/* MSTP(MTU4) = 0; // MTU,MTU0,MTU1,MTU2,MTU3,MTU4,MTU5 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA9 = 0; */ +/* MSTP(TPU4) = 0; // TPU,TPU0,TPU1,TPU2,TPU3,TPU4,TPU5 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA13 = 0; */ +/* MSTP(CMT3) = 0; // CMT2,CMT3 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA14 = 0; */ +/* */ +/* */ +/********************************************************************************/ +#ifndef __RX231IODEFINE_HEADER__ +#define __RX231IODEFINE_HEADER__ +#pragma bit_order left +#pragma unpack +struct st_bsc { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char STSCLR:1; + } BIT; + } BERCLR; + char wk0[3]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TOEN:1; + unsigned char IGAEN:1; + } BIT; + } BEREN; + char wk1[3]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MST:3; + unsigned char :2; + unsigned char TO:1; + unsigned char IA:1; + } BIT; + } BERSR1; + char wk2[1]; + union { + unsigned short WORD; + struct { + unsigned short ADDR:13; + unsigned short :3; + } BIT; + } BERSR2; + char wk3[4]; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short BPEB:2; + unsigned short BPFB:2; + unsigned short BPHB:2; + unsigned short BPGB:2; + unsigned short BPIB:2; + unsigned short BPRO:2; + unsigned short BPRA:2; + } BIT; + } BUSPRI; + char wk4[7408]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS0MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS0WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS0WCR2; + char wk5[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS1MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS1WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS1WCR2; + char wk6[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS2MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS2WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS2WCR2; + char wk7[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS3MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS3WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS3WCR2; + char wk8[1990]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS0CR; + char wk9[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS0REC; + char wk10[6]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS1CR; + char wk11[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS1REC; + char wk12[6]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS2CR; + char wk13[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS2REC; + char wk14[6]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS3CR; + char wk15[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS3REC; + char wk16[68]; + union { + unsigned short WORD; + struct { + unsigned short RCVENM7:1; + unsigned short RCVENM6:1; + unsigned short RCVENM5:1; + unsigned short RCVENM4:1; + unsigned short RCVENM3:1; + unsigned short RCVENM2:1; + unsigned short RCVENM1:1; + unsigned short RCVENM0:1; + unsigned short RCVEN7:1; + unsigned short RCVEN6:1; + unsigned short RCVEN5:1; + unsigned short RCVEN4:1; + unsigned short RCVEN3:1; + unsigned short RCVEN2:1; + unsigned short RCVEN1:1; + unsigned short RCVEN0:1; + } BIT; + } CSRECEN; +}; + +struct st_cac { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char CFME:1; + } BIT; + } CACR0; + union { + unsigned char BYTE; + struct { + unsigned char EDGES:2; + unsigned char TCSS:2; + unsigned char FMCS:3; + unsigned char CACREFE:1; + } BIT; + } CACR1; + union { + unsigned char BYTE; + struct { + unsigned char DFS:2; + unsigned char RCDS:2; + unsigned char RSCS:3; + unsigned char RPS:1; + } BIT; + } CACR2; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char OVFFCL:1; + unsigned char MENDFCL:1; + unsigned char FERRFCL:1; + unsigned char :1; + unsigned char OVFIE:1; + unsigned char MENDIE:1; + unsigned char FERRIE:1; + } BIT; + } CAICR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char OVFF:1; + unsigned char MENDF:1; + unsigned char FERRF:1; + } BIT; + } CASTR; + char wk0[1]; + unsigned short CAULVR; + unsigned short CALLVR; + unsigned short CACNTBR; +}; + +struct st_rscan { + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short TSSS:1; + unsigned short TSP:4; + unsigned short :3; + unsigned short DCS:1; + unsigned short MME:1; + unsigned short DRE:1; + unsigned short DCE:1; + unsigned short TPRI:1; + } BIT; + } GCFGL; + union { + unsigned short WORD; + struct { + unsigned short ITRCP:16; + } BIT; + } GCFGH; + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short THLEIE:1; + unsigned short MEIE:1; + unsigned short DEIE:1; + unsigned short :5; + unsigned short GSLPR:1; + unsigned short GMDC:2; + } BIT; + } GCTRL; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short TSRST:1; + } BIT; + } GCTRH; + union { + unsigned short WORD; + struct { + unsigned short :12; + unsigned short GRAMINIT:1; + unsigned short GSLPSTS:1; + unsigned short GHLTSTS:1; + unsigned short GRSTSTS:1; + } BIT; + } GSTS; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char THLES:1; + unsigned char MES:1; + unsigned char DEF:1; + } BIT; + } GERFLL; + char wk0[1]; + union { + unsigned short WORD; + struct { + unsigned short TS:16; + } BIT; + } GTSC; + union { + unsigned short WORD; + struct { + unsigned short :11; + unsigned short RNC0:5; + } BIT; + } GAFLCFG; + union { + unsigned short WORD; + struct { + unsigned short :11; + unsigned short NRXMB:5; + } BIT; + } RMNB; + union { + unsigned short WORD; + struct { + unsigned short RMNS:16; + } BIT; + } RMND0; + char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short RFIGCV:3; + unsigned short RFIM:1; + unsigned short :1; + unsigned short RFDC:3; + unsigned short :6; + unsigned short RFIE:1; + unsigned short RFE:1; + } BIT; + } RFCC0; + union { + unsigned short WORD; + struct { + unsigned short RFIGCV:3; + unsigned short RFIM:1; + unsigned short :1; + unsigned short RFDC:3; + unsigned short :6; + unsigned short RFIE:1; + unsigned short RFE:1; + } BIT; + } RFCC1; + char wk2[4]; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short RFMC:6; + unsigned short :4; + unsigned short RFIF:1; + unsigned short RFMLT:1; + unsigned short RFFLL:1; + unsigned short RFEMP:1; + } BIT; + } RFSTS0; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short RFMC:6; + unsigned short :4; + unsigned short RFIF:1; + unsigned short RFMLT:1; + unsigned short RFFLL:1; + unsigned short RFEMP:1; + } BIT; + } RFSTS1; + char wk3[4]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short RFPC:8; + } BIT; + } RFPCTR0; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short RFPC:8; + } BIT; + } RFPCTR1; + char wk4[20]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char RF1MLT:1; + unsigned char RF0MLT:1; + } BIT; + } RFMSTS; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char RF1IF:1; + unsigned char RF0IF:1; + } BIT; + } RFISTS; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char CF0IF:1; + } BIT; + } CFISTS; + char wk6[36]; + union { + unsigned short WORD; + struct { + unsigned short :12; + unsigned short THIF0:1; + unsigned short CFTIF0:1; + unsigned short TAIF0:1; + unsigned short TSIF0:1; + } BIT; + } GTINTSTS; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short RPAGE:1; + } BIT; + } GRWCR; + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short RTMPS:3; + unsigned short :8; + } BIT; + } GTSTCFG; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char RTME:1; + unsigned char :2; + } BIT; + } GTSTCTRL; + char wk7[5]; + union { + unsigned short WORD; + struct { + unsigned short LOCK:16; + } BIT; + } GLOCKK; + char wk8[10]; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLID:16; + } BIT; + } GAFLIDL0; + union { + unsigned short WORD; + struct { + unsigned short RMID:16; + } BIT; + } RMIDL0; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDE:1; + unsigned short GAFLRTR:1; + unsigned short GAFLLB:1; + unsigned short GAFLID:13; + } BIT; + } GAFLIDH0; + union { + unsigned short WORD; + struct { + unsigned short RMIDE:1; + unsigned short RMRTR:1; + unsigned short :1; + unsigned short RMID:13; + } BIT; + } RMIDH0; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDM:16; + } BIT; + } GAFLML0; + union { + unsigned short WORD; + struct { + unsigned short RMTS:16; + } BIT; + } RMTS0; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDEM:1; + unsigned short GAFLRTRM:1; + unsigned short :1; + unsigned short GAFLIDM:13; + } BIT; + } GAFLMH0; + union { + unsigned short WORD; + struct { + unsigned short RMDLC:4; + unsigned short RMPTR:12; + } BIT; + } RMPTR0; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLRMV:1; + unsigned short GAFLRMDP:7; + unsigned short :3; + unsigned short GAFLFDP4:1; + unsigned short :2; + unsigned short GAFLFDP1:1; + unsigned short GAFLFDP0:1; + } BIT; + } GAFLPL0; + union { + unsigned short WORD; + struct { + unsigned short RMDB1:8; + unsigned short RMDB0:8; + } BIT; + } RMDF00; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLDLC:4; + unsigned short GAFLPTR:12; + } BIT; + } GAFLPH0; + union { + unsigned short WORD; + struct { + unsigned short RMDB3:8; + unsigned short RMDB2:8; + } BIT; + } RMDF10; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLID:16; + } BIT; + } GAFLIDL1; + union { + unsigned short WORD; + struct { + unsigned short RMDB5:8; + unsigned short RMDB4:8; + } BIT; + } RMDF20; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDE:1; + unsigned short GAFLRTR:1; + unsigned short GAFLLB:1; + unsigned short GAFLID:13; + } BIT; + } GAFLIDH1; + union { + unsigned short WORD; + struct { + unsigned short RMDB7:8; + unsigned short RMDB6:8; + } BIT; + } RMDF30; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDM:16; + } BIT; + } GAFLML1; + union { + unsigned short WORD; + struct { + unsigned short RMID:16; + } BIT; + } RMIDL1; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDEM:1; + unsigned short GAFLRTRM:1; + unsigned short :1; + unsigned short GAFLIDM:13; + } BIT; + } GAFLMH1; + union { + unsigned short WORD; + struct { + unsigned short RMIDE:1; + unsigned short RMRTR:1; + unsigned short :1; + unsigned short RMID:13; + } BIT; + } RMIDH1; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLRMV:1; + unsigned short GAFLRMDP:7; + unsigned short :3; + unsigned short GAFLFDP4:1; + unsigned short :2; + unsigned short GAFLFDP1:1; + unsigned short GAFLFDP0:1; + } BIT; + } GAFLPL1; + union { + unsigned short WORD; + struct { + unsigned short RMTS:16; + } BIT; + } RMTS1; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLDLC:4; + unsigned short GAFLPTR:12; + } BIT; + } GAFLPH1; + union { + unsigned short WORD; + struct { + unsigned short RMDLC:4; + unsigned short RMPTR:12; + } BIT; + } RMPTR1; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLID:16; + } BIT; + } GAFLIDL2; + union { + unsigned short WORD; + struct { + unsigned short RMDB1:8; + unsigned short RMDB0:8; + } BIT; + } RMDF01; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDE:1; + unsigned short GAFLRTR:1; + unsigned short GAFLLB:1; + unsigned short GAFLID:13; + } BIT; + } GAFLIDH2; + union { + unsigned short WORD; + struct { + unsigned short RMDB3:8; + unsigned short RMDB2:8; + } BIT; + } RMDF11; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDM:16; + } BIT; + } GAFLML2; + union { + unsigned short WORD; + struct { + unsigned short RMDB5:8; + unsigned short RMDB4:8; + } BIT; + } RMDF21; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDEM:1; + unsigned short GAFLRTRM:1; + unsigned short :1; + unsigned short GAFLIDM:13; + } BIT; + } GAFLMH2; + union { + unsigned short WORD; + struct { + unsigned short RMDB7:8; + unsigned short RMDB6:8; + } BIT; + } RMDF31; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLRMV:1; + unsigned short GAFLRMDP:7; + unsigned short :3; + unsigned short GAFLFDP4:1; + unsigned short :2; + unsigned short GAFLFDP1:1; + unsigned short GAFLFDP0:1; + } BIT; + } GAFLPL2; + union { + unsigned short WORD; + struct { + unsigned short RMID:16; + } BIT; + } RMIDL2; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLDLC:4; + unsigned short GAFLPTR:12; + } BIT; + } GAFLPH2; + union { + unsigned short WORD; + struct { + unsigned short RMIDE:1; + unsigned short RMRTR:1; + unsigned short :1; + unsigned short RMID:13; + } BIT; + } RMIDH2; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLID:16; + } BIT; + } GAFLIDL3; + union { + unsigned short WORD; + struct { + unsigned short RMTS:16; + } BIT; + } RMTS2; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDE:1; + unsigned short GAFLRTR:1; + unsigned short GAFLLB:1; + unsigned short GAFLID:13; + } BIT; + } GAFLIDH3; + union { + unsigned short WORD; + struct { + unsigned short RMDLC:4; + unsigned short RMPTR:12; + } BIT; + } RMPTR2; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDM:16; + } BIT; + } GAFLML3; + union { + unsigned short WORD; + struct { + unsigned short RMDB1:8; + unsigned short RMDB0:8; + } BIT; + } RMDF02; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDEM:1; + unsigned short GAFLRTRM:1; + unsigned short :1; + unsigned short GAFLIDM:13; + } BIT; + } GAFLMH3; + union { + unsigned short WORD; + struct { + unsigned short RMDB3:8; + unsigned short RMDB2:8; + } BIT; + } RMDF12; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLRMV:1; + unsigned short GAFLRMDP:7; + unsigned short :3; + unsigned short GAFLFDP4:1; + unsigned short :2; + unsigned short GAFLFDP1:1; + unsigned short GAFLFDP0:1; + } BIT; + } GAFLPL3; + union { + unsigned short WORD; + struct { + unsigned short RMDB5:8; + unsigned short RMDB4:8; + } BIT; + } RMDF22; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLDLC:4; + unsigned short GAFLPTR:12; + } BIT; + } GAFLPH3; + union { + unsigned short WORD; + struct { + unsigned short RMDB7:8; + unsigned short RMDB6:8; + } BIT; + } RMDF32; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLID:16; + } BIT; + } GAFLIDL4; + union { + unsigned short WORD; + struct { + unsigned short RMID:16; + } BIT; + } RMIDL3; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDE:1; + unsigned short GAFLRTR:1; + unsigned short GAFLLB:1; + unsigned short GAFLID:13; + } BIT; + } GAFLIDH4; + union { + unsigned short WORD; + struct { + unsigned short RMIDE:1; + unsigned short RMRTR:1; + unsigned short :1; + unsigned short RMID:13; + } BIT; + } RMIDH3; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDM:16; + } BIT; + } GAFLML4; + union { + unsigned short WORD; + struct { + unsigned short RMTS:16; + } BIT; + } RMTS3; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDEM:1; + unsigned short GAFLRTRM:1; + unsigned short :1; + unsigned short GAFLIDM:13; + } BIT; + } GAFLMH4; + union { + unsigned short WORD; + struct { + unsigned short RMDLC:4; + unsigned short RMPTR:12; + } BIT; + } RMPTR3; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLRMV:1; + unsigned short GAFLRMDP:7; + unsigned short :3; + unsigned short GAFLFDP4:1; + unsigned short :2; + unsigned short GAFLFDP1:1; + unsigned short GAFLFDP0:1; + } BIT; + } GAFLPL4; + union { + unsigned short WORD; + struct { + unsigned short RMDB1:8; + unsigned short RMDB0:8; + } BIT; + } RMDF03; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLDLC:4; + unsigned short GAFLPTR:12; + } BIT; + } GAFLPH4; + union { + unsigned short WORD; + struct { + unsigned short RMDB3:8; + unsigned short RMDB2:8; + } BIT; + } RMDF13; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLID:16; + } BIT; + } GAFLIDL5; + union { + unsigned short WORD; + struct { + unsigned short RMDB5:8; + unsigned short RMDB4:8; + } BIT; + } RMDF23; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDE:1; + unsigned short GAFLRTR:1; + unsigned short GAFLLB:1; + unsigned short GAFLID:13; + } BIT; + } GAFLIDH5; + union { + unsigned short WORD; + struct { + unsigned short RMDB7:8; + unsigned short RMDB6:8; + } BIT; + } RMDF33; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDM:16; + } BIT; + } GAFLML5; + union { + unsigned short WORD; + struct { + unsigned short RMID:16; + } BIT; + } RMIDL4; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDEM:1; + unsigned short GAFLRTRM:1; + unsigned short :1; + unsigned short GAFLIDM:13; + } BIT; + } GAFLMH5; + union { + unsigned short WORD; + struct { + unsigned short RMIDE:1; + unsigned short RMRTR:1; + unsigned short :1; + unsigned short RMID:13; + } BIT; + } RMIDH4; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLRMV:1; + unsigned short GAFLRMDP:7; + unsigned short :3; + unsigned short GAFLFDP4:1; + unsigned short :2; + unsigned short GAFLFDP1:1; + unsigned short GAFLFDP0:1; + } BIT; + } GAFLPL5; + union { + unsigned short WORD; + struct { + unsigned short RMTS:16; + } BIT; + } RMTS4; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLDLC:4; + unsigned short GAFLPTR:12; + } BIT; + } GAFLPH5; + union { + unsigned short WORD; + struct { + unsigned short RMDLC:4; + unsigned short RMPTR:12; + } BIT; + } RMPTR4; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLID:16; + } BIT; + } GAFLIDL6; + union { + unsigned short WORD; + struct { + unsigned short RMDB1:8; + unsigned short RMDB0:8; + } BIT; + } RMDF04; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDE:1; + unsigned short GAFLRTR:1; + unsigned short GAFLLB:1; + unsigned short GAFLID:13; + } BIT; + } GAFLIDH6; + union { + unsigned short WORD; + struct { + unsigned short RMDB3:8; + unsigned short RMDB2:8; + } BIT; + } RMDF14; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDM:16; + } BIT; + } GAFLML6; + union { + unsigned short WORD; + struct { + unsigned short RMDB5:8; + unsigned short RMDB4:8; + } BIT; + } RMDF24; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDEM:1; + unsigned short GAFLRTRM:1; + unsigned short :1; + unsigned short GAFLIDM:13; + } BIT; + } GAFLMH6; + union { + unsigned short WORD; + struct { + unsigned short RMDB7:8; + unsigned short RMDB6:8; + } BIT; + } RMDF34; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLRMV:1; + unsigned short GAFLRMDP:7; + unsigned short :3; + unsigned short GAFLFDP4:1; + unsigned short :2; + unsigned short GAFLFDP1:1; + unsigned short GAFLFDP0:1; + } BIT; + } GAFLPL6; + union { + unsigned short WORD; + struct { + unsigned short RMID:16; + } BIT; + } RMIDL5; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLDLC:4; + unsigned short GAFLPTR:12; + } BIT; + } GAFLPH6; + union { + unsigned short WORD; + struct { + unsigned short RMIDE:1; + unsigned short RMRTR:1; + unsigned short :1; + unsigned short RMID:13; + } BIT; + } RMIDH5; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLID:16; + } BIT; + } GAFLIDL7; + union { + unsigned short WORD; + struct { + unsigned short RMTS:16; + } BIT; + } RMTS5; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDE:1; + unsigned short GAFLRTR:1; + unsigned short GAFLLB:1; + unsigned short GAFLID:13; + } BIT; + } GAFLIDH7; + union { + unsigned short WORD; + struct { + unsigned short RMDLC:4; + unsigned short RMPTR:12; + } BIT; + } RMPTR5; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDM:16; + } BIT; + } GAFLML7; + union { + unsigned short WORD; + struct { + unsigned short RMDB1:8; + unsigned short RMDB0:8; + } BIT; + } RMDF05; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDEM:1; + unsigned short GAFLRTRM:1; + unsigned short :1; + unsigned short GAFLIDM:13; + } BIT; + } GAFLMH7; + union { + unsigned short WORD; + struct { + unsigned short RMDB3:8; + unsigned short RMDB2:8; + } BIT; + } RMDF15; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLRMV:1; + unsigned short GAFLRMDP:7; + unsigned short :3; + unsigned short GAFLFDP4:1; + unsigned short :2; + unsigned short GAFLFDP1:1; + unsigned short GAFLFDP0:1; + } BIT; + } GAFLPL7; + union { + unsigned short WORD; + struct { + unsigned short RMDB5:8; + unsigned short RMDB4:8; + } BIT; + } RMDF25; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLDLC:4; + unsigned short GAFLPTR:12; + } BIT; + } GAFLPH7; + union { + unsigned short WORD; + struct { + unsigned short RMDB7:8; + unsigned short RMDB6:8; + } BIT; + } RMDF35; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLID:16; + } BIT; + } GAFLIDL8; + union { + unsigned short WORD; + struct { + unsigned short RMID:16; + } BIT; + } RMIDL6; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDE:1; + unsigned short GAFLRTR:1; + unsigned short GAFLLB:1; + unsigned short GAFLID:13; + } BIT; + } GAFLIDH8; + union { + unsigned short WORD; + struct { + unsigned short RMIDE:1; + unsigned short RMRTR:1; + unsigned short :1; + unsigned short RMID:13; + } BIT; + } RMIDH6; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDM:16; + } BIT; + } GAFLML8; + union { + unsigned short WORD; + struct { + unsigned short RMTS:16; + } BIT; + } RMTS6; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDEM:1; + unsigned short GAFLRTRM:1; + unsigned short :1; + unsigned short GAFLIDM:13; + } BIT; + } GAFLMH8; + union { + unsigned short WORD; + struct { + unsigned short RMDLC:4; + unsigned short RMPTR:12; + } BIT; + } RMPTR6; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLRMV:1; + unsigned short GAFLRMDP:7; + unsigned short :3; + unsigned short GAFLFDP4:1; + unsigned short :2; + unsigned short GAFLFDP1:1; + unsigned short GAFLFDP0:1; + } BIT; + } GAFLPL8; + union { + unsigned short WORD; + struct { + unsigned short RMDB1:8; + unsigned short RMDB0:8; + } BIT; + } RMDF06; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLDLC:4; + unsigned short GAFLPTR:12; + } BIT; + } GAFLPH8; + union { + unsigned short WORD; + struct { + unsigned short RMDB3:8; + unsigned short RMDB2:8; + } BIT; + } RMDF16; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLID:16; + } BIT; + } GAFLIDL9; + union { + unsigned short WORD; + struct { + unsigned short RMDB5:8; + unsigned short RMDB4:8; + } BIT; + } RMDF26; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDE:1; + unsigned short GAFLRTR:1; + unsigned short GAFLLB:1; + unsigned short GAFLID:13; + } BIT; + } GAFLIDH9; + union { + unsigned short WORD; + struct { + unsigned short RMDB7:8; + unsigned short RMDB6:8; + } BIT; + } RMDF36; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDM:16; + } BIT; + } GAFLML9; + union { + unsigned short WORD; + struct { + unsigned short RMID:16; + } BIT; + } RMIDL7; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDEM:1; + unsigned short GAFLRTRM:1; + unsigned short :1; + unsigned short GAFLIDM:13; + } BIT; + } GAFLMH9; + union { + unsigned short WORD; + struct { + unsigned short RMIDE:1; + unsigned short RMRTR:1; + unsigned short :1; + unsigned short RMID:13; + } BIT; + } RMIDH7; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLRMV:1; + unsigned short GAFLRMDP:7; + unsigned short :3; + unsigned short GAFLFDP4:1; + unsigned short :2; + unsigned short GAFLFDP1:1; + unsigned short GAFLFDP0:1; + } BIT; + } GAFLPL9; + union { + unsigned short WORD; + struct { + unsigned short RMTS:16; + } BIT; + } RMTS7; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLDLC:4; + unsigned short GAFLPTR:12; + } BIT; + } GAFLPH9; + union { + unsigned short WORD; + struct { + unsigned short RMDLC:4; + unsigned short RMPTR:12; + } BIT; + } RMPTR7; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLID:16; + } BIT; + } GAFLIDL10; + union { + unsigned short WORD; + struct { + unsigned short RMDB1:8; + unsigned short RMDB0:8; + } BIT; + } RMDF07; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDE:1; + unsigned short GAFLRTR:1; + unsigned short GAFLLB:1; + unsigned short GAFLID:13; + } BIT; + } GAFLIDH10; + union { + unsigned short WORD; + struct { + unsigned short RMDB3:8; + unsigned short RMDB2:8; + } BIT; + } RMDF17; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDM:16; + } BIT; + } GAFLML10; + union { + unsigned short WORD; + struct { + unsigned short RMDB5:8; + unsigned short RMDB4:8; + } BIT; + } RMDF27; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDEM:1; + unsigned short GAFLRTRM:1; + unsigned short :1; + unsigned short GAFLIDM:13; + } BIT; + } GAFLMH10; + union { + unsigned short WORD; + struct { + unsigned short RMDB7:8; + unsigned short RMDB6:8; + } BIT; + } RMDF37; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLRMV:1; + unsigned short GAFLRMDP:7; + unsigned short :3; + unsigned short GAFLFDP4:1; + unsigned short :2; + unsigned short GAFLFDP1:1; + unsigned short GAFLFDP0:1; + } BIT; + } GAFLPL10; + union { + unsigned short WORD; + struct { + unsigned short RMID:16; + } BIT; + } RMIDL8; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLDLC:4; + unsigned short GAFLPTR:12; + } BIT; + } GAFLPH10; + union { + unsigned short WORD; + struct { + unsigned short RMIDE:1; + unsigned short RMRTR:1; + unsigned short :1; + unsigned short RMID:13; + } BIT; + } RMIDH8; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLID:16; + } BIT; + } GAFLIDL11; + union { + unsigned short WORD; + struct { + unsigned short RMTS:16; + } BIT; + } RMTS8; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDE:1; + unsigned short GAFLRTR:1; + unsigned short GAFLLB:1; + unsigned short GAFLID:13; + } BIT; + } GAFLIDH11; + union { + unsigned short WORD; + struct { + unsigned short RMDLC:4; + unsigned short RMPTR:12; + } BIT; + } RMPTR8; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDM:16; + } BIT; + } GAFLML11; + union { + unsigned short WORD; + struct { + unsigned short RMDB1:8; + unsigned short RMDB0:8; + } BIT; + } RMDF08; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDEM:1; + unsigned short GAFLRTRM:1; + unsigned short :1; + unsigned short GAFLIDM:13; + } BIT; + } GAFLMH11; + union { + unsigned short WORD; + struct { + unsigned short RMDB3:8; + unsigned short RMDB2:8; + } BIT; + } RMDF18; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLRMV:1; + unsigned short GAFLRMDP:7; + unsigned short :3; + unsigned short GAFLFDP4:1; + unsigned short :2; + unsigned short GAFLFDP1:1; + unsigned short GAFLFDP0:1; + } BIT; + } GAFLPL11; + union { + unsigned short WORD; + struct { + unsigned short RMDB5:8; + unsigned short RMDB4:8; + } BIT; + } RMDF28; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLDLC:4; + unsigned short GAFLPTR:12; + } BIT; + } GAFLPH11; + union { + unsigned short WORD; + struct { + unsigned short RMDB7:8; + unsigned short RMDB6:8; + } BIT; + } RMDF38; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLID:16; + } BIT; + } GAFLIDL12; + union { + unsigned short WORD; + struct { + unsigned short RMID:16; + } BIT; + } RMIDL9; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDE:1; + unsigned short GAFLRTR:1; + unsigned short GAFLLB:1; + unsigned short GAFLID:13; + } BIT; + } GAFLIDH12; + union { + unsigned short WORD; + struct { + unsigned short RMIDE:1; + unsigned short RMRTR:1; + unsigned short :1; + unsigned short RMID:13; + } BIT; + } RMIDH9; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDM:16; + } BIT; + } GAFLML12; + union { + unsigned short WORD; + struct { + unsigned short RMTS:16; + } BIT; + } RMTS9; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDEM:1; + unsigned short GAFLRTRM:1; + unsigned short :1; + unsigned short GAFLIDM:13; + } BIT; + } GAFLMH12; + union { + unsigned short WORD; + struct { + unsigned short RMDLC:4; + unsigned short RMPTR:12; + } BIT; + } RMPTR9; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLRMV:1; + unsigned short GAFLRMDP:7; + unsigned short :3; + unsigned short GAFLFDP4:1; + unsigned short :2; + unsigned short GAFLFDP1:1; + unsigned short GAFLFDP0:1; + } BIT; + } GAFLPL12; + union { + unsigned short WORD; + struct { + unsigned short RMDB1:8; + unsigned short RMDB0:8; + } BIT; + } RMDF09; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLDLC:4; + unsigned short GAFLPTR:12; + } BIT; + } GAFLPH12; + union { + unsigned short WORD; + struct { + unsigned short RMDB3:8; + unsigned short RMDB2:8; + } BIT; + } RMDF19; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLID:16; + } BIT; + } GAFLIDL13; + union { + unsigned short WORD; + struct { + unsigned short RMDB5:8; + unsigned short RMDB4:8; + } BIT; + } RMDF29; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDE:1; + unsigned short GAFLRTR:1; + unsigned short GAFLLB:1; + unsigned short GAFLID:13; + } BIT; + } GAFLIDH13; + union { + unsigned short WORD; + struct { + unsigned short RMDB7:8; + unsigned short RMDB6:8; + } BIT; + } RMDF39; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDM:16; + } BIT; + } GAFLML13; + union { + unsigned short WORD; + struct { + unsigned short RMID:16; + } BIT; + } RMIDL10; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDEM:1; + unsigned short GAFLRTRM:1; + unsigned short :1; + unsigned short GAFLIDM:13; + } BIT; + } GAFLMH13; + union { + unsigned short WORD; + struct { + unsigned short RMIDE:1; + unsigned short RMRTR:1; + unsigned short :1; + unsigned short RMID:13; + } BIT; + } RMIDH10; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLRMV:1; + unsigned short GAFLRMDP:7; + unsigned short :3; + unsigned short GAFLFDP4:1; + unsigned short :2; + unsigned short GAFLFDP1:1; + unsigned short GAFLFDP0:1; + } BIT; + } GAFLPL13; + union { + unsigned short WORD; + struct { + unsigned short RMTS:16; + } BIT; + } RMTS10; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLDLC:4; + unsigned short GAFLPTR:12; + } BIT; + } GAFLPH13; + union { + unsigned short WORD; + struct { + unsigned short RMDLC:4; + unsigned short RMPTR:12; + } BIT; + } RMPTR10; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLID:16; + } BIT; + } GAFLIDL14; + union { + unsigned short WORD; + struct { + unsigned short RMDB1:8; + unsigned short RMDB0:8; + } BIT; + } RMDF010; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDE:1; + unsigned short GAFLRTR:1; + unsigned short GAFLLB:1; + unsigned short GAFLID:13; + } BIT; + } GAFLIDH14; + union { + unsigned short WORD; + struct { + unsigned short RMDB3:8; + unsigned short RMDB2:8; + } BIT; + } RMDF110; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDM:16; + } BIT; + } GAFLML14; + union { + unsigned short WORD; + struct { + unsigned short RMDB5:8; + unsigned short RMDB4:8; + } BIT; + } RMDF210; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDEM:1; + unsigned short GAFLRTRM:1; + unsigned short :1; + unsigned short GAFLIDM:13; + } BIT; + } GAFLMH14; + union { + unsigned short WORD; + struct { + unsigned short RMDB7:8; + unsigned short RMDB6:8; + } BIT; + } RMDF310; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLRMV:1; + unsigned short GAFLRMDP:7; + unsigned short :3; + unsigned short GAFLFDP4:1; + unsigned short :2; + unsigned short GAFLFDP1:1; + unsigned short GAFLFDP0:1; + } BIT; + } GAFLPL14; + union { + unsigned short WORD; + struct { + unsigned short RMID:16; + } BIT; + } RMIDL11; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLDLC:4; + unsigned short GAFLPTR:12; + } BIT; + } GAFLPH14; + union { + unsigned short WORD; + struct { + unsigned short RMIDE:1; + unsigned short RMRTR:1; + unsigned short :1; + unsigned short RMID:13; + } BIT; + } RMIDH11; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLID:16; + } BIT; + } GAFLIDL15; + union { + unsigned short WORD; + struct { + unsigned short RMTS:16; + } BIT; + } RMTS11; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDE:1; + unsigned short GAFLRTR:1; + unsigned short GAFLLB:1; + unsigned short GAFLID:13; + } BIT; + } GAFLIDH15; + union { + unsigned short WORD; + struct { + unsigned short RMDLC:4; + unsigned short RMPTR:12; + } BIT; + } RMPTR11; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDM:16; + } BIT; + } GAFLML15; + union { + unsigned short WORD; + struct { + unsigned short RMDB1:8; + unsigned short RMDB0:8; + } BIT; + } RMDF011; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDEM:1; + unsigned short GAFLRTRM:1; + unsigned short :1; + unsigned short GAFLIDM:13; + } BIT; + } GAFLMH15; + union { + unsigned short WORD; + struct { + unsigned short RMDB3:8; + unsigned short RMDB2:8; + } BIT; + } RMDF111; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLRMV:1; + unsigned short GAFLRMDP:7; + unsigned short :3; + unsigned short GAFLFDP4:1; + unsigned short :2; + unsigned short GAFLFDP1:1; + unsigned short GAFLFDP0:1; + } BIT; + } GAFLPL15; + union { + unsigned short WORD; + struct { + unsigned short RMDB5:8; + unsigned short RMDB4:8; + } BIT; + } RMDF211; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLDLC:4; + unsigned short GAFLPTR:12; + } BIT; + } GAFLPH15; + union { + unsigned short WORD; + struct { + unsigned short RMDB7:8; + unsigned short RMDB6:8; + } BIT; + } RMDF311; + }; + union { + unsigned short WORD; + struct { + unsigned short RMID:16; + } BIT; + } RMIDL12; + union { + unsigned short WORD; + struct { + unsigned short RMIDE:1; + unsigned short RMRTR:1; + unsigned short :1; + unsigned short RMID:13; + } BIT; + } RMIDH12; + union { + unsigned short WORD; + struct { + unsigned short RMTS:16; + } BIT; + } RMTS12; + union { + unsigned short WORD; + struct { + unsigned short RMDLC:4; + unsigned short RMPTR:12; + } BIT; + } RMPTR12; + union { + unsigned short WORD; + struct { + unsigned short RMDB1:8; + unsigned short RMDB0:8; + } BIT; + } RMDF012; + union { + unsigned short WORD; + struct { + unsigned short RMDB3:8; + unsigned short RMDB2:8; + } BIT; + } RMDF112; + union { + unsigned short WORD; + struct { + unsigned short RMDB5:8; + unsigned short RMDB4:8; + } BIT; + } RMDF212; + union { + unsigned short WORD; + struct { + unsigned short RMDB7:8; + unsigned short RMDB6:8; + } BIT; + } RMDF312; + union { + unsigned short WORD; + struct { + unsigned short RMID:16; + } BIT; + } RMIDL13; + union { + unsigned short WORD; + struct { + unsigned short RMIDE:1; + unsigned short RMRTR:1; + unsigned short :1; + unsigned short RMID:13; + } BIT; + } RMIDH13; + union { + unsigned short WORD; + struct { + unsigned short RMTS:16; + } BIT; + } RMTS13; + union { + unsigned short WORD; + struct { + unsigned short RMDLC:4; + unsigned short RMPTR:12; + } BIT; + } RMPTR13; + union { + unsigned short WORD; + struct { + unsigned short RMDB1:8; + unsigned short RMDB0:8; + } BIT; + } RMDF013; + union { + unsigned short WORD; + struct { + unsigned short RMDB3:8; + unsigned short RMDB2:8; + } BIT; + } RMDF113; + union { + unsigned short WORD; + struct { + unsigned short RMDB5:8; + unsigned short RMDB4:8; + } BIT; + } RMDF213; + union { + unsigned short WORD; + struct { + unsigned short RMDB7:8; + unsigned short RMDB6:8; + } BIT; + } RMDF313; + union { + unsigned short WORD; + struct { + unsigned short RMID:16; + } BIT; + } RMIDL14; + union { + unsigned short WORD; + struct { + unsigned short RMIDE:1; + unsigned short RMRTR:1; + unsigned short :1; + unsigned short RMID:13; + } BIT; + } RMIDH14; + union { + unsigned short WORD; + struct { + unsigned short RMTS:16; + } BIT; + } RMTS14; + union { + unsigned short WORD; + struct { + unsigned short RMDLC:4; + unsigned short RMPTR:12; + } BIT; + } RMPTR14; + union { + unsigned short WORD; + struct { + unsigned short RMDB1:8; + unsigned short RMDB0:8; + } BIT; + } RMDF014; + union { + unsigned short WORD; + struct { + unsigned short RMDB3:8; + unsigned short RMDB2:8; + } BIT; + } RMDF114; + union { + unsigned short WORD; + struct { + unsigned short RMDB5:8; + unsigned short RMDB4:8; + } BIT; + } RMDF214; + union { + unsigned short WORD; + struct { + unsigned short RMDB7:8; + unsigned short RMDB6:8; + } BIT; + } RMDF314; + union { + unsigned short WORD; + struct { + unsigned short RMID:16; + } BIT; + } RMIDL15; + union { + unsigned short WORD; + struct { + unsigned short RMIDE:1; + unsigned short RMRTR:1; + unsigned short :1; + unsigned short RMID:13; + } BIT; + } RMIDH15; + union { + unsigned short WORD; + struct { + unsigned short RMTS:16; + } BIT; + } RMTS15; + union { + unsigned short WORD; + struct { + unsigned short RMDLC:4; + unsigned short RMPTR:12; + } BIT; + } RMPTR15; + union { + unsigned short WORD; + struct { + unsigned short RMDB1:8; + unsigned short RMDB0:8; + } BIT; + } RMDF015; + union { + unsigned short WORD; + struct { + unsigned short RMDB3:8; + unsigned short RMDB2:8; + } BIT; + } RMDF115; + union { + unsigned short WORD; + struct { + unsigned short RMDB5:8; + unsigned short RMDB4:8; + } BIT; + } RMDF215; + union { + unsigned short WORD; + struct { + unsigned short RMDB7:8; + unsigned short RMDB6:8; + } BIT; + } RMDF315; + char wk9[224]; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC0; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC1; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC2; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC3; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC4; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC5; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC6; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC7; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC8; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC9; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC10; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC11; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC12; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC13; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC14; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC15; + union { + union { + unsigned short WORD; + struct { + unsigned short RFID:16; + } BIT; + } RFIDL0; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC16; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short RFIDE:1; + unsigned short RFRTR:1; + unsigned short :1; + unsigned short RFID:13; + } BIT; + } RFIDH0; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC17; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short RFTS:16; + } BIT; + } RFTS0; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC18; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short RFDLC:4; + unsigned short RFPTR:12; + } BIT; + } RFPTR0; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC19; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short RFDB1:8; + unsigned short RFDB0:8; + } BIT; + } RFDF00; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC20; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short RFDB3:8; + unsigned short RFDB2:8; + } BIT; + } RFDF10; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC21; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short RFDB5:8; + unsigned short RFDB4:8; + } BIT; + } RFDF20; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC22; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short RFDB7:8; + unsigned short RFDB6:8; + } BIT; + } RFDF30; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC23; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short RFID:16; + } BIT; + } RFIDL1; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC24; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short RFIDE:1; + unsigned short RFRTR:1; + unsigned short :1; + unsigned short RFID:13; + } BIT; + } RFIDH1; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC25; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short RFTS:16; + } BIT; + } RFTS1; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC26; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short RFDLC:4; + unsigned short RFPTR:12; + } BIT; + } RFPTR1; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC27; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short RFDB1:8; + unsigned short RFDB0:8; + } BIT; + } RFDF01; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC28; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short RFDB3:8; + unsigned short RFDB2:8; + } BIT; + } RFDF11; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC29; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short RFDB5:8; + unsigned short RFDB4:8; + } BIT; + } RFDF21; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC30; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short RFDB7:8; + unsigned short RFDB6:8; + } BIT; + } RFDF31; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC31; + }; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC32; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC33; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC34; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC35; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC36; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC37; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC38; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC39; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC40; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC41; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC42; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC43; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC44; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC45; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC46; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC47; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC48; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC49; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC50; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC51; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC52; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC53; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC54; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC55; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC56; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC57; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC58; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC59; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC60; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC61; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC62; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC63; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC64; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC65; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC66; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC67; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC68; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC69; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC70; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC71; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC72; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC73; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC74; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC75; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC76; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC77; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC78; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC79; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC80; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC81; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC82; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC83; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC84; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC85; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC86; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC87; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC88; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC89; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC90; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC91; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC92; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC93; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC94; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC95; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC96; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC97; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC98; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC99; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC100; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC101; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC102; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC103; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC104; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC105; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC106; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC107; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC108; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC109; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC110; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC111; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC112; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC113; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC114; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC115; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC116; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC117; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC118; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC119; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC120; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC121; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC122; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC123; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC124; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC125; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC126; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC127; +}; + +struct st_rscan0 { + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short BRP:10; + } BIT; + } CFGL; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short SJW:2; + unsigned short :1; + unsigned short TSEG2:3; + unsigned short TSEG1:4; + } BIT; + } CFGH; + union { + unsigned short WORD; + struct { + unsigned short ALIE:1; + unsigned short BLIE:1; + unsigned short OLIE:1; + unsigned short BORIE:1; + unsigned short BOEIE:1; + unsigned short EPIE:1; + unsigned short EWIE:1; + unsigned short BEIE:1; + unsigned short :4; + unsigned short RTBO:1; + unsigned short CSLPR:1; + unsigned short CHMDC:2; + } BIT; + } CTRL; + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short CTMS:2; + unsigned short CTME:1; + unsigned short ERRD:1; + unsigned short BOM:2; + unsigned short :4; + unsigned short TAIE:1; + } BIT; + } CTRH; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short COMSTS:1; + unsigned short RECSTS:1; + unsigned short TRMSTS:1; + unsigned short BOSTS:1; + unsigned short EPSTS:1; + unsigned short CSLPSTS:1; + unsigned short CHLTSTS:1; + unsigned short CRSTSTS:1; + } BIT; + } STSL; + union { + unsigned short WORD; + struct { + unsigned short TEC:8; + unsigned short REC:8; + } BIT; + } STSH; + union { + unsigned short WORD; + struct { + unsigned short :1; + unsigned short ADERR:1; + unsigned short B0ERR:1; + unsigned short B1ERR:1; + unsigned short CERR:1; + unsigned short AERR:1; + unsigned short FERR:1; + unsigned short SERR:1; + unsigned short ALF:1; + unsigned short BLF:1; + unsigned short OVLF:1; + unsigned short BORF:1; + unsigned short BOEF:1; + unsigned short EPF:1; + unsigned short EWF:1; + unsigned short BEF:1; + } BIT; + } ERFLL; + union { + unsigned short WORD; + struct { + unsigned short :1; + unsigned short CRCREG:15; + } BIT; + } ERFLH; + char wk0[64]; + union { + unsigned short WORD; + struct { + unsigned short CFIGCV:3; + unsigned short CFIM:1; + unsigned short :1; + unsigned short CFDC:3; + unsigned short :5; + unsigned short CFTXIE:1; + unsigned short CFRXIE:1; + unsigned short CFE:1; + } BIT; + } CFCCL0; + union { + unsigned short WORD; + struct { + unsigned short CFITT:8; + unsigned short :2; + unsigned short CFTML:2; + unsigned short CFITR:1; + unsigned short CFITSS:1; + unsigned short CFM:2; + } BIT; + } CFCCH0; + char wk1[4]; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short CFMC:6; + unsigned short :3; + unsigned short CFTXIF:1; + unsigned short CFRXIF:1; + unsigned short CFMLT:1; + unsigned short CFFLL:1; + unsigned short CFEMP:1; + } BIT; + } CFSTS0; + char wk2[2]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short CFPC:8; + } BIT; + } CFPCTR0; + char wk3[3]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char CF0MLT:1; + } BIT; + } CFMSTS; + char wk4[2]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TMOM:1; + unsigned char TMTAR:1; + unsigned char TMTR:1; + } BIT; + } TMC0; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TMOM:1; + unsigned char TMTAR:1; + unsigned char TMTR:1; + } BIT; + } TMC1; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TMOM:1; + unsigned char TMTAR:1; + unsigned char TMTR:1; + } BIT; + } TMC2; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TMOM:1; + unsigned char TMTAR:1; + unsigned char TMTR:1; + } BIT; + } TMC3; + char wk5[4]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char TMTARM:1; + unsigned char TMTRM:1; + unsigned char TMTRF:2; + unsigned char TMTSTS:1; + } BIT; + } TMSTS0; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char TMTARM:1; + unsigned char TMTRM:1; + unsigned char TMTRF:2; + unsigned char TMTSTS:1; + } BIT; + } TMSTS1; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char TMTARM:1; + unsigned char TMTRM:1; + unsigned char TMTRF:2; + unsigned char TMTSTS:1; + } BIT; + } TMSTS2; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char TMTARM:1; + unsigned char TMTRM:1; + unsigned char TMTRF:2; + unsigned char TMTSTS:1; + } BIT; + } TMSTS3; + char wk6[4]; + union { + unsigned short WORD; + struct { + unsigned short :12; + unsigned short TMTRSTS3:1; + unsigned short TMTRSTS2:1; + unsigned short TMTRSTS1:1; + unsigned short TMTRSTS0:1; + } BIT; + } TMTRSTS; + union { + unsigned short WORD; + struct { + unsigned short :12; + unsigned short TMTCSTS3:1; + unsigned short TMTCSTS2:1; + unsigned short TMTCSTS1:1; + unsigned short TMTCSTS0:1; + } BIT; + } TMTCSTS; + union { + unsigned short WORD; + struct { + unsigned short :12; + unsigned short TMTASTS3:1; + unsigned short TMTASTS2:1; + unsigned short TMTASTS1:1; + unsigned short TMTASTS0:1; + } BIT; + } TMTASTS; + union { + unsigned short WORD; + struct { + unsigned short :12; + unsigned short TMIE3:1; + unsigned short TMIE2:1; + unsigned short TMIE1:1; + unsigned short TMIE0:1; + } BIT; + } TMIEC; + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short THLDTE:1; + unsigned short THLIM:1; + unsigned short THLIE:1; + unsigned short :7; + unsigned short THLE:1; + } BIT; + } THLCC0; + char wk7[2]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short THLMC:4; + unsigned short :4; + unsigned short THLIF:1; + unsigned short THLELT:1; + unsigned short THLFLL:1; + unsigned short THLEMP:1; + } BIT; + } THLSTS0; + char wk8[2]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short THLPC:8; + } BIT; + } THLPCTR0; + char wk9[602]; + union { + unsigned short WORD; + struct { + unsigned short CFID:16; + } BIT; + } CFIDL0; + union { + unsigned short WORD; + struct { + unsigned short CFIDE:1; + unsigned short CFRTR:1; + unsigned short THLEN:1; + unsigned short CFID:13; + } BIT; + } CFIDH0; + union { + unsigned short WORD; + struct { + unsigned short CFTS:16; + } BIT; + } CFTS0; + union { + unsigned short WORD; + struct { + unsigned short CFDLC:4; + unsigned short CFPTR:12; + } BIT; + } CFPTR0; + union { + unsigned short WORD; + struct { + unsigned short CFDB1:8; + unsigned short CFDB0:8; + } BIT; + } CFDF00; + union { + unsigned short WORD; + struct { + unsigned short CFDB3:8; + unsigned short CFDB2:8; + } BIT; + } CFDF10; + union { + unsigned short WORD; + struct { + unsigned short CFDB5:8; + unsigned short CFDB4:8; + } BIT; + } CFDF20; + union { + unsigned short WORD; + struct { + unsigned short CFDB7:8; + unsigned short CFDB6:8; + } BIT; + } CFDF30; + char wk10[16]; + union { + unsigned short WORD; + struct { + unsigned short TMID:16; + } BIT; + } TMIDL0; + union { + unsigned short WORD; + struct { + unsigned short TMIDE:1; + unsigned short TMRTR:1; + unsigned short THLEN:1; + unsigned short TMID:13; + } BIT; + } TMIDH0; + char wk11[2]; + union { + unsigned short WORD; + struct { + unsigned short TMDLC:4; + unsigned short :4; + unsigned short TMPTR:8; + } BIT; + } TMPTR0; + union { + unsigned short WORD; + struct { + unsigned short TMDB1:8; + unsigned short TMDB0:8; + } BIT; + } TMDF00; + union { + unsigned short WORD; + struct { + unsigned short TMDB3:8; + unsigned short TMDB2:8; + } BIT; + } TMDF10; + union { + unsigned short WORD; + struct { + unsigned short TMDB5:8; + unsigned short TMDB4:8; + } BIT; + } TMDF20; + union { + unsigned short WORD; + struct { + unsigned short TMDB7:8; + unsigned short TMDB6:8; + } BIT; + } TMDF30; + union { + unsigned short WORD; + struct { + unsigned short TMID:16; + } BIT; + } TMIDL1; + union { + unsigned short WORD; + struct { + unsigned short TMIDE:1; + unsigned short TMRTR:1; + unsigned short THLEN:1; + unsigned short TMID:13; + } BIT; + } TMIDH1; + char wk12[2]; + union { + unsigned short WORD; + struct { + unsigned short TMDLC:4; + unsigned short :4; + unsigned short TMPTR:8; + } BIT; + } TMPTR1; + union { + unsigned short WORD; + struct { + unsigned short TMDB1:8; + unsigned short TMDB0:8; + } BIT; + } TMDF01; + union { + unsigned short WORD; + struct { + unsigned short TMDB3:8; + unsigned short TMDB2:8; + } BIT; + } TMDF11; + union { + unsigned short WORD; + struct { + unsigned short TMDB5:8; + unsigned short TMDB4:8; + } BIT; + } TMDF21; + union { + unsigned short WORD; + struct { + unsigned short TMDB7:8; + unsigned short TMDB6:8; + } BIT; + } TMDF31; + union { + unsigned short WORD; + struct { + unsigned short TMID:16; + } BIT; + } TMIDL2; + union { + unsigned short WORD; + struct { + unsigned short TMIDE:1; + unsigned short TMRTR:1; + unsigned short THLEN:1; + unsigned short TMID:13; + } BIT; + } TMIDH2; + char wk13[2]; + union { + unsigned short WORD; + struct { + unsigned short TMDLC:4; + unsigned short :4; + unsigned short TMPTR:8; + } BIT; + } TMPTR2; + union { + unsigned short WORD; + struct { + unsigned short TMDB1:8; + unsigned short TMDB0:8; + } BIT; + } TMDF02; + union { + unsigned short WORD; + struct { + unsigned short TMDB3:8; + unsigned short TMDB2:8; + } BIT; + } TMDF12; + union { + unsigned short WORD; + struct { + unsigned short TMDB5:8; + unsigned short TMDB4:8; + } BIT; + } TMDF22; + union { + unsigned short WORD; + struct { + unsigned short TMDB7:8; + unsigned short TMDB6:8; + } BIT; + } TMDF32; + union { + unsigned short WORD; + struct { + unsigned short TMID:16; + } BIT; + } TMIDL3; + union { + unsigned short WORD; + struct { + unsigned short TMIDE:1; + unsigned short TMRTR:1; + unsigned short THLEN:1; + unsigned short TMID:13; + } BIT; + } TMIDH3; + char wk14[2]; + union { + unsigned short WORD; + struct { + unsigned short TMDLC:4; + unsigned short :4; + unsigned short TMPTR:8; + } BIT; + } TMPTR3; + union { + unsigned short WORD; + struct { + unsigned short TMDB1:8; + unsigned short TMDB0:8; + } BIT; + } TMDF03; + union { + unsigned short WORD; + struct { + unsigned short TMDB3:8; + unsigned short TMDB2:8; + } BIT; + } TMDF13; + union { + unsigned short WORD; + struct { + unsigned short TMDB5:8; + unsigned short TMDB4:8; + } BIT; + } TMDF23; + union { + unsigned short WORD; + struct { + unsigned short TMDB7:8; + unsigned short TMDB6:8; + } BIT; + } TMDF33; + char wk15[64]; + union { + unsigned short WORD; + struct { + unsigned short TID:8; + unsigned short :3; + unsigned short BN:2; + unsigned short :1; + unsigned short BT:2; + } BIT; + } THLACC0; +}; + +struct st_cmpb { + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CPB1INI:1; + unsigned char :3; + unsigned char CPB0INI:1; + } BIT; + } CPBCNT1; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CPB1WCP:1; + unsigned char :3; + unsigned char CPB0WCP:1; + } BIT; + } CPBCNT2; + union { + unsigned char BYTE; + struct { + unsigned char CPB1OUT:1; + unsigned char :3; + unsigned char CPB0OUT:1; + unsigned char :3; + } BIT; + } CPBFLG; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char CPB1INTPL:1; + unsigned char CPB1INTEG:1; + unsigned char CPB1INTEN:1; + unsigned char :1; + unsigned char CPB0INTPL:1; + unsigned char CPB0INTEG:1; + unsigned char CPB0INTEN:1; + } BIT; + } CPBINT; + union { + unsigned char BYTE; + struct { + unsigned char CPB1F:2; + unsigned char :1; + unsigned char CPB1FEN:1; + unsigned char CPB0F:2; + unsigned char :1; + unsigned char CPB0FEN:1; + } BIT; + } CPBF; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char CPBSPDMD:1; + } BIT; + } CPBMD; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CPB1VRF:1; + unsigned char :3; + unsigned char CPB0VRF:1; + } BIT; + } CPBREF; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char CPB1OP:1; + unsigned char CPB1OE:1; + unsigned char :2; + unsigned char CPB0OP:1; + unsigned char CPB0OE:1; + } BIT; + } CPBOCR; + char wk0[24]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CPB3INI:1; + unsigned char :3; + unsigned char CPB2INI:1; + } BIT; + } CPB1CNT1; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CPB3WCP:1; + unsigned char :3; + unsigned char CPB2WCP:1; + } BIT; + } CPB1CNT2; + union { + unsigned char BYTE; + struct { + unsigned char CPB3OUT:1; + unsigned char :3; + unsigned char CPB2OUT:1; + unsigned char :3; + } BIT; + } CPB1FLG; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char CPB3INTPL:1; + unsigned char CPB3INTEG:1; + unsigned char CPB3INTEN:1; + unsigned char :1; + unsigned char CPB2INTPL:1; + unsigned char CPB2INTEG:1; + unsigned char CPB2INTEN:1; + } BIT; + } CPB1INT; + union { + unsigned char BYTE; + struct { + unsigned char CPB3F:2; + unsigned char :1; + unsigned char CPB3FEN:1; + unsigned char CPB2F:2; + unsigned char :1; + unsigned char CPB2FEN:1; + } BIT; + } CPB1F; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char CPB1SPDMD:1; + } BIT; + } CPB1MD; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CPB3VRF:1; + unsigned char :3; + unsigned char CPB2VRF:1; + } BIT; + } CPB1REF; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char CPB3OP:1; + unsigned char CPB3OE:1; + unsigned char :2; + unsigned char CPB2OP:1; + unsigned char CPB2OE:1; + } BIT; + } CPB1OCR; +}; + +struct st_cmt { + union { + unsigned short WORD; + struct { + unsigned short :14; + unsigned short STR1:1; + unsigned short STR0:1; + } BIT; + } CMSTR0; + char wk0[14]; + union { + unsigned short WORD; + struct { + unsigned short :14; + unsigned short STR3:1; + unsigned short STR2:1; + } BIT; + } CMSTR1; +}; + +struct st_cmt0 { + union { + unsigned short WORD; + struct { + unsigned short :9; + unsigned short CMIE:1; + unsigned short :4; + unsigned short CKS:2; + } BIT; + } CMCR; + unsigned short CMCNT; + unsigned short CMCOR; +}; + +struct st_crc { + union { + unsigned char BYTE; + struct { + unsigned char DORCLR:1; + unsigned char :4; + unsigned char LMS:1; + unsigned char GPS:2; + } BIT; + } CRCCR; + unsigned char CRCDIR; + unsigned short CRCDOR; +}; + +struct st_ctsu { + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CTSUINIT:1; + unsigned char :1; + unsigned char CTSUSNZ:1; + unsigned char CTSUCAP:1; + unsigned char CTSUSTRT:1; + } BIT; + } CTSUCR0; + union { + unsigned char BYTE; + struct { + unsigned char CTSUMD:2; + unsigned char CTSUCLK:2; + unsigned char CTSUATUNE1:1; + unsigned char CTSUATUNE0:1; + unsigned char CTSUCSW:1; + unsigned char CTSUPON:1; + } BIT; + } CTSUCR1; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char CTSUSOFF:1; + unsigned char CTSUPRMODE:2; + unsigned char CTSUPRRATIO:4; + } BIT; + } CTSUSDPRS; + union { + unsigned char BYTE; + struct { + unsigned char CTSUSST:8; + } BIT; + } CTSUSST; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char CTSUMCH0:6; + } BIT; + } CTSUMCH0; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char CTSUMCH1:6; + } BIT; + } CTSUMCH1; + union { + unsigned char BYTE; + struct { + unsigned char CTSUCHAC07:1; + unsigned char CTSUCHAC06:1; + unsigned char CTSUCHAC05:1; + unsigned char CTSUCHAC04:1; + unsigned char CTSUCHAC03:1; + unsigned char CTSUCHAC02:1; + unsigned char CTSUCHAC01:1; + unsigned char CTSUCHAC00:1; + } BIT; + } CTSUCHAC0; + union { + unsigned char BYTE; + struct { + unsigned char CTSUCHAC17:1; + unsigned char CTSUCHAC16:1; + unsigned char CTSUCHAC15:1; + unsigned char CTSUCHAC14:1; + unsigned char CTSUCHAC13:1; + unsigned char CTSUCHAC12:1; + unsigned char CTSUCHAC11:1; + unsigned char CTSUCHAC10:1; + } BIT; + } CTSUCHAC1; + union { + unsigned char BYTE; + struct { + unsigned char CTSUCHAC27:1; + unsigned char CTSUCHAC26:1; + unsigned char CTSUCHAC25:1; + unsigned char CTSUCHAC24:1; + unsigned char CTSUCHAC23:1; + unsigned char CTSUCHAC22:1; + unsigned char CTSUCHAC21:1; + unsigned char CTSUCHAC20:1; + } BIT; + } CTSUCHAC2; + union { + unsigned char BYTE; + struct { + unsigned char CTSUCHAC37:1; + unsigned char CTSUCHAC36:1; + unsigned char CTSUCHAC35:1; + unsigned char CTSUCHAC34:1; + unsigned char CTSUCHAC33:1; + unsigned char CTSUCHAC32:1; + unsigned char CTSUCHAC31:1; + unsigned char CTSUCHAC30:1; + } BIT; + } CTSUCHAC3; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char CTSUCHAC43:1; + unsigned char CTSUCHAC42:1; + unsigned char CTSUCHAC41:1; + unsigned char CTSUCHAC40:1; + } BIT; + } CTSUCHAC4; + union { + unsigned char BYTE; + struct { + unsigned char CTSUCHTRC07:1; + unsigned char CTSUCHTRC06:1; + unsigned char CTSUCHTRC05:1; + unsigned char CTSUCHTRC04:1; + unsigned char CTSUCHTRC03:1; + unsigned char CTSUCHTRC02:1; + unsigned char CTSUCHTRC01:1; + unsigned char CTSUCHTRC00:1; + } BIT; + } CTSUCHTRC0; + union { + unsigned char BYTE; + struct { + unsigned char CTSUCHTRC17:1; + unsigned char CTSUCHTRC16:1; + unsigned char CTSUCHTRC15:1; + unsigned char CTSUCHTRC14:1; + unsigned char CTSUCHTRC13:1; + unsigned char CTSUCHTRC12:1; + unsigned char CTSUCHTRC11:1; + unsigned char CTSUCHTRC10:1; + } BIT; + } CTSUCHTRC1; + union { + unsigned char BYTE; + struct { + unsigned char CTSUCHTRC27:1; + unsigned char CTSUCHTRC26:1; + unsigned char CTSUCHTRC25:1; + unsigned char CTSUCHTRC24:1; + unsigned char CTSUCHTRC23:1; + unsigned char CTSUCHTRC22:1; + unsigned char CTSUCHTRC21:1; + unsigned char CTSUCHTRC20:1; + } BIT; + } CTSUCHTRC2; + union { + unsigned char BYTE; + struct { + unsigned char CTSUCHTRC37:1; + unsigned char CTSUCHTRC36:1; + unsigned char CTSUCHTRC35:1; + unsigned char CTSUCHTRC34:1; + unsigned char CTSUCHTRC33:1; + unsigned char CTSUCHTRC32:1; + unsigned char CTSUCHTRC31:1; + unsigned char CTSUCHTRC30:1; + } BIT; + } CTSUCHTRC3; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char CTSUCHTRC43:1; + unsigned char CTSUCHTRC42:1; + unsigned char CTSUCHTRC41:1; + unsigned char CTSUCHTRC40:1; + } BIT; + } CTSUCHTRC4; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char CTSUSSCNT:2; + unsigned char :2; + unsigned char CTSUSSMOD:2; + } BIT; + } CTSUDCLKC; + union { + unsigned char BYTE; + struct { + unsigned char CTSUPS:1; + unsigned char CTSUROVF:1; + unsigned char CTSUSOVF:1; + unsigned char CTSUDTSR:1; + unsigned char :1; + unsigned char CTSUSTC:3; + } BIT; + } CTSUST; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short CTSUSSDIV:4; + unsigned short :8; + } BIT; + } CTSUSSC; + union { + unsigned short WORD; + struct { + unsigned short CTSUSNUM:6; + unsigned short CTSUSO:10; + } BIT; + } CTSUSO0; + union { + unsigned short WORD; + struct { + unsigned short :1; + unsigned short CTSUICOG:2; + unsigned short CTSUSDPA:5; + unsigned short CTSURICOA:8; + } BIT; + } CTSUSO1; + union { + unsigned short WORD; + struct { + unsigned short CTSUSC:16; + } BIT; + } CTSUSC; + union { + unsigned short WORD; + struct { + unsigned short CTSURC:16; + } BIT; + } CTSURC; + union { + unsigned short WORD; + struct { + unsigned short CTSUICOMP:1; + unsigned short :15; + } BIT; + } CTSUERRS; +}; + +struct st_da { + unsigned short DADR0; + unsigned short DADR1; + union { + unsigned char BYTE; + struct { + unsigned char DAOE1:1; + unsigned char DAOE0:1; + unsigned char :6; + } BIT; + } DACR; + union { + unsigned char BYTE; + struct { + unsigned char DPSEL:1; + unsigned char :7; + } BIT; + } DADPR; + union { + unsigned char BYTE; + struct { + unsigned char DAADST:1; + unsigned char :7; + } BIT; + } DAADSCR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char REF:3; + } BIT; + } DAVREFCR; +}; + +struct st_dmac { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DMST:1; + } BIT; + } DMAST; +}; + +struct st_dmac0 { + void *DMSAR; + void *DMDAR; + unsigned long DMCRA; + unsigned short DMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short MD:2; + unsigned short DTS:2; + unsigned short :2; + unsigned short SZ:2; + unsigned short :6; + unsigned short DCTG:2; + } BIT; + } DMTMD; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char DTIE:1; + unsigned char ESIE:1; + unsigned char RPTIE:1; + unsigned char SARIE:1; + unsigned char DARIE:1; + } BIT; + } DMINT; + union { + unsigned short WORD; + struct { + unsigned short SM:2; + unsigned short :1; + unsigned short SARA:5; + unsigned short DM:2; + unsigned short :1; + unsigned short DARA:5; + } BIT; + } DMAMD; + char wk2[2]; + unsigned long DMOFR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTE:1; + } BIT; + } DMCNT; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CLRS:1; + unsigned char :3; + unsigned char SWREQ:1; + } BIT; + } DMREQ; + union { + unsigned char BYTE; + struct { + unsigned char ACT:1; + unsigned char :2; + unsigned char DTIF:1; + unsigned char :3; + unsigned char ESIF:1; + } BIT; + } DMSTS; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DISEL:1; + } BIT; + } DMCSL; +}; + +struct st_dmac1 { + void *DMSAR; + void *DMDAR; + unsigned long DMCRA; + unsigned short DMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short MD:2; + unsigned short DTS:2; + unsigned short :2; + unsigned short SZ:2; + unsigned short :6; + unsigned short DCTG:2; + } BIT; + } DMTMD; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char DTIE:1; + unsigned char ESIE:1; + unsigned char RPTIE:1; + unsigned char SARIE:1; + unsigned char DARIE:1; + } BIT; + } DMINT; + union { + unsigned short WORD; + struct { + unsigned short SM:2; + unsigned short :1; + unsigned short SARA:5; + unsigned short DM:2; + unsigned short :1; + unsigned short DARA:5; + } BIT; + } DMAMD; + char wk2[6]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTE:1; + } BIT; + } DMCNT; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CLRS:1; + unsigned char :3; + unsigned char SWREQ:1; + } BIT; + } DMREQ; + union { + unsigned char BYTE; + struct { + unsigned char ACT:1; + unsigned char :2; + unsigned char DTIF:1; + unsigned char :3; + unsigned char ESIF:1; + } BIT; + } DMSTS; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DISEL:1; + } BIT; + } DMCSL; +}; + +struct st_doc { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char DOPCFCL:1; + unsigned char DOPCF:1; + unsigned char DOPCIE:1; + unsigned char :1; + unsigned char DCSEL:1; + unsigned char OMS:2; + } BIT; + } DOCR; + char wk0[1]; + unsigned short DODIR; + unsigned short DODSR; +}; + +struct st_dtc { + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char RRS:1; + unsigned char :4; + } BIT; + } DTCCR; + char wk0[3]; + void *DTCVBR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SHORT:1; + } BIT; + } DTCADMOD; + char wk1[3]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTCST:1; + } BIT; + } DTCST; + char wk2[1]; + union { + unsigned short WORD; + struct { + unsigned short ACT:1; + unsigned short :7; + unsigned short VECN:8; + } BIT; + } DTCSTS; +}; + +struct st_elc { + union { + unsigned char BYTE; + struct { + unsigned char ELCON:1; + unsigned char :7; + } BIT; + } ELCR; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR[30]; + union { + unsigned char BYTE; + struct { + unsigned char MTU3MD:2; + unsigned char MTU2MD:2; + unsigned char MTU1MD:2; + unsigned char :2; + } BIT; + } ELOPA; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char MTU4MD:2; + } BIT; + } ELOPB; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char LPTMD:2; + unsigned char CMT1MD:2; + unsigned char :2; + } BIT; + } ELOPC; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char TMR2MD:2; + unsigned char :2; + unsigned char TMR0MD:2; + } BIT; + } ELOPD; + union { + unsigned char BYTE; + struct { + unsigned char PGR7:1; + unsigned char PGR6:1; + unsigned char PGR5:1; + unsigned char PGR4:1; + unsigned char PGR3:1; + unsigned char PGR2:1; + unsigned char PGR1:1; + unsigned char PGR0:1; + } BIT; + } PGR1; + union { + unsigned char BYTE; + struct { + unsigned char PGR7:1; + unsigned char PGR6:1; + unsigned char PGR5:1; + unsigned char PGR4:1; + unsigned char PGR3:1; + unsigned char PGR2:1; + unsigned char PGR1:1; + unsigned char PGR0:1; + } BIT; + } PGR2; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PGCO:3; + unsigned char :1; + unsigned char PGCOVE:1; + unsigned char PGCI:2; + } BIT; + } PGC1; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PGCO:3; + unsigned char :1; + unsigned char PGCOVE:1; + unsigned char PGCI:2; + } BIT; + } PGC2; + union { + unsigned char BYTE; + struct { + unsigned char PDBF7:1; + unsigned char PDBF6:1; + unsigned char PDBF5:1; + unsigned char PDBF4:1; + unsigned char PDBF3:1; + unsigned char PDBF2:1; + unsigned char PDBF1:1; + unsigned char PDBF0:1; + } BIT; + } PDBF1; + union { + unsigned char BYTE; + struct { + unsigned char PDBF7:1; + unsigned char PDBF6:1; + unsigned char PDBF5:1; + unsigned char PDBF4:1; + unsigned char PDBF3:1; + unsigned char PDBF2:1; + unsigned char PDBF1:1; + unsigned char PDBF0:1; + } BIT; + } PDBF2; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PSM:2; + unsigned char PSP:2; + unsigned char PSB:3; + } BIT; + } PEL0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PSM:2; + unsigned char PSP:2; + unsigned char PSB:3; + } BIT; + } PEL1; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PSM:2; + unsigned char PSP:2; + unsigned char PSB:3; + } BIT; + } PEL2; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PSM:2; + unsigned char PSP:2; + unsigned char PSB:3; + } BIT; + } PEL3; + union { + unsigned char BYTE; + struct { + unsigned char WI:1; + unsigned char WE:1; + unsigned char :5; + unsigned char SEG:1; + } BIT; + } ELSEGR; +}; + +struct st_flash { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DFLEN:1; + } BIT; + } DFLCTL; + char wk0[111]; + union { + unsigned char BYTE; + struct { + unsigned char FMS2:1; + unsigned char LVPE:1; + unsigned char :1; + unsigned char FMS1:1; + unsigned char RPDIS:1; + unsigned char :1; + unsigned char FMS0:1; + unsigned char :1; + } BIT; + } FPMCR; + char wk1[3]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char EXS:1; + } BIT; + } FASR; + char wk2[3]; + unsigned short FSARL; + char wk3[6]; + unsigned short FSARH; + char wk4[2]; + union { + unsigned char BYTE; + struct { + unsigned char OPST:1; + unsigned char STOP:1; + unsigned char :2; + unsigned char CMD:4; + } BIT; + } FCR; + char wk5[3]; + unsigned short FEARL; + char wk6[6]; + unsigned short FEARH; + char wk7[2]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char FRESET:1; + } BIT; + } FRESETR; + char wk8[7]; + union { + unsigned char BYTE; + struct { + unsigned char EXRDY:1; + unsigned char FRDY:1; + unsigned char :6; + } BIT; + } FSTATR1; + char wk9[3]; + unsigned short FWB0; + char wk10[6]; + unsigned short FWB1; + char wk11[6]; + unsigned short FWB2; + char wk12[2]; + unsigned short FWB3; + char wk13[58]; + unsigned char FPR; + char wk14[3]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char PERR:1; + } BIT; + } FPSR; + char wk15[59]; + union { + unsigned short WORD; + struct { + unsigned short :7; + unsigned short SASMF:1; + unsigned short :8; + } BIT; + } FSCMR; + char wk16[6]; + unsigned short FAWSMR; + char wk17[6]; + unsigned short FAWEMR; + char wk18[6]; + union { + unsigned char BYTE; + struct { + unsigned char SAS:2; + unsigned char :1; + unsigned char PCKA:5; + } BIT; + } FISR; + char wk19[3]; + union { + unsigned char BYTE; + struct { + unsigned char OPST:1; + unsigned char :4; + unsigned char CMD:3; + } BIT; + } FEXCR; + char wk20[3]; + unsigned short FEAML; + char wk21[6]; + unsigned short FEAMH; + char wk22[6]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char EILGLERR:1; + unsigned char ILGLERR:1; + unsigned char BCERR:1; + unsigned char :1; + unsigned char PRGERR:1; + unsigned char ERERR:1; + } BIT; + } FSTATR0; + char wk23[15809]; + union { + unsigned short WORD; + struct { + unsigned short FEKEY:8; + unsigned short FENTRYD:1; + unsigned short :6; + unsigned short FENTRY0:1; + } BIT; + } FENTRYR; +}; + +struct st_flashconst { + unsigned long UIDR0; + unsigned long UIDR1; + unsigned long UIDR2; + unsigned long UIDR3; +}; + +struct st_icu { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char IR:1; + } BIT; + } IR[254]; + char wk0[2]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTCE:1; + } BIT; + } DTCER[253]; + char wk1[3]; + union { + unsigned char BYTE; + struct { + unsigned char IEN7:1; + unsigned char IEN6:1; + unsigned char IEN5:1; + unsigned char IEN4:1; + unsigned char IEN3:1; + unsigned char IEN2:1; + unsigned char IEN1:1; + unsigned char IEN0:1; + } BIT; + } IER[32]; + char wk2[192]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SWINT:1; + } BIT; + } SWINTR; + char wk3[15]; + union { + unsigned short WORD; + struct { + unsigned short FIEN:1; + unsigned short :7; + unsigned short FVCT:8; + } BIT; + } FIR; + char wk4[14]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char IPR:4; + } BIT; + } IPR[251]; + char wk5[5]; + unsigned char DMRSR0; + char wk6[3]; + unsigned char DMRSR1; + char wk7[3]; + unsigned char DMRSR2; + char wk8[3]; + unsigned char DMRSR3; + char wk9[243]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char IRQMD:2; + unsigned char :2; + } BIT; + } IRQCR[8]; + char wk10[8]; + union { + unsigned char BYTE; + struct { + unsigned char FLTEN7:1; + unsigned char FLTEN6:1; + unsigned char FLTEN5:1; + unsigned char FLTEN4:1; + unsigned char FLTEN3:1; + unsigned char FLTEN2:1; + unsigned char FLTEN1:1; + unsigned char FLTEN0:1; + } BIT; + } IRQFLTE0; + char wk11[3]; + union { + unsigned short WORD; + struct { + unsigned short FCLKSEL7:2; + unsigned short FCLKSEL6:2; + unsigned short FCLKSEL5:2; + unsigned short FCLKSEL4:2; + unsigned short FCLKSEL3:2; + unsigned short FCLKSEL2:2; + unsigned short FCLKSEL1:2; + unsigned short FCLKSEL0:2; + } BIT; + } IRQFLTC0; + char wk12[106]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char VBATST:1; + unsigned char LVD2ST:1; + unsigned char LVD1ST:1; + unsigned char IWDTST:1; + unsigned char WDTST:1; + unsigned char OSTST:1; + unsigned char NMIST:1; + } BIT; + } NMISR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char VBATEN:1; + unsigned char LVD2EN:1; + unsigned char LVD1EN:1; + unsigned char IWDTEN:1; + unsigned char WDTEN:1; + unsigned char OSTEN:1; + unsigned char NMIEN:1; + } BIT; + } NMIER; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char VBATCLR:1; + unsigned char LVD2CLR:1; + unsigned char LVD1CLR:1; + unsigned char IWDTCLR:1; + unsigned char WDTCLR:1; + unsigned char OSTCLR:1; + unsigned char NMICLR:1; + } BIT; + } NMICLR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char NMIMD:1; + unsigned char :3; + } BIT; + } NMICR; + char wk13[12]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char NFLTEN:1; + } BIT; + } NMIFLTE; + char wk14[3]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char NFCLKSEL:2; + } BIT; + } NMIFLTC; +}; + +struct st_irda { + union { + unsigned char BYTE; + struct { + unsigned char IRE:1; + unsigned char IRCKS:3; + unsigned char IRTXINV:1; + unsigned char IRRXINV:1; + unsigned char :2; + } BIT; + } IRCR; +}; + +struct st_iwdt { + unsigned char IWDTRR; + char wk0[1]; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short RPSS:2; + unsigned short :2; + unsigned short RPES:2; + unsigned short CKS:4; + unsigned short :2; + unsigned short TOPS:2; + } BIT; + } IWDTCR; + union { + unsigned short WORD; + struct { + unsigned short REFEF:1; + unsigned short UNDFF:1; + unsigned short CNTVAL:14; + } BIT; + } IWDTSR; + union { + unsigned char BYTE; + struct { + unsigned char RSTIRQS:1; + unsigned char :7; + } BIT; + } IWDTRCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char SLCSTP:1; + unsigned char :7; + } BIT; + } IWDTCSTPR; +}; + +struct st_lpt { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char LPCMRE0:1; + unsigned char :1; + unsigned char LPCNTCKSEL:1; + unsigned char :1; + unsigned char LPCNTPSSEL:3; + } BIT; + } LPTCR1; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char LPCNTSTP:1; + } BIT; + } LPTCR2; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char LPCNTRST:1; + unsigned char LPCNTEN:1; + } BIT; + } LPTCR3; + char wk0[1]; + union { + unsigned short WORD; + struct { + unsigned short LPCNTPRD:16; + } BIT; + } LPTPRD; + char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short LPCMR0:16; + } BIT; + } LPCMR0; + char wk2[2]; + union { + unsigned short WORD; + struct { + unsigned short LPWKUPEN:1; + unsigned short :15; + } BIT; + } LPWUCR; +}; + +struct st_mpc { + union { + unsigned char BYTE; + struct { + unsigned char CS7E:1; + unsigned char CS6E:1; + unsigned char CS5E:1; + unsigned char CS4E:1; + unsigned char CS3E:1; + unsigned char CS2E:1; + unsigned char CS1E:1; + unsigned char CS0E:1; + } BIT; + } PFCSE; + char wk0[3]; + union { + unsigned char BYTE; + struct { + unsigned char A15E:1; + unsigned char A14E:1; + unsigned char A13E:1; + unsigned char A12E:1; + unsigned char A11E:1; + unsigned char A10E:1; + unsigned char A9E:1; + unsigned char A8E:1; + } BIT; + } PFAOE0; + union { + unsigned char BYTE; + struct { + unsigned char A23E:1; + unsigned char A22E:1; + unsigned char A21E:1; + unsigned char A20E:1; + unsigned char A19E:1; + unsigned char A18E:1; + unsigned char A17E:1; + unsigned char A16E:1; + } BIT; + } PFAOE1; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char WR1BC1E:1; + unsigned char :1; + unsigned char DHE:1; + unsigned char :3; + unsigned char ADRLE:1; + } BIT; + } PFBCR0; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char ALEOE:1; + unsigned char WAITS:2; + } BIT; + } PFBCR1; + char wk1[23]; + union { + unsigned char BYTE; + struct { + unsigned char B0WI:1; + unsigned char PFSWE:1; + unsigned char :6; + } BIT; + } PWPR; + char wk2[35]; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :2; + unsigned char PSEL:5; + } BIT; + } P03PFS; + char wk3[1]; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :2; + unsigned char PSEL:5; + } BIT; + } P05PFS; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P07PFS; + char wk5[2]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P12PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P13PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P14PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P15PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P16PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P17PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P20PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P21PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P22PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P23PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P24PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P25PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :2; + unsigned char PSEL:5; + } BIT; + } P26PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :2; + unsigned char PSEL:5; + } BIT; + } P27PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P30PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P31PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P32PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P33PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P34PFS; + char wk6[3]; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :7; + } BIT; + } P40PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :7; + } BIT; + } P41PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :7; + } BIT; + } P42PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :7; + } BIT; + } P43PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :7; + } BIT; + } P44PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :7; + } BIT; + } P45PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :7; + } BIT; + } P46PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :7; + } BIT; + } P47PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P50PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P51PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P52PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P53PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P54PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P55PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P56PFS; + char wk7[33]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PA0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PA1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PA2PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PA3PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PA4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PA5PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PA6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PA7PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PB0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PB1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PB2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PB3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PB4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PB5PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PB6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PB7PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PC0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PC1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PC2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PC3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PC4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PC5PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PC6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PC7PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PD0PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PD1PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PD2PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PD3PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PD4PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PD5PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PD6PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PD7PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :2; + unsigned char PSEL:5; + } BIT; + } PE0PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :2; + unsigned char PSEL:5; + } BIT; + } PE1PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PE2PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :2; + unsigned char PSEL:5; + } BIT; + } PE3PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :2; + unsigned char PSEL:5; + } BIT; + } PE4PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PE5PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PE6PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PE7PFS; + char wk8[16]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PH0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PH1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PH2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PH3PFS; + char wk9[7]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PJ3PFS; +}; + +struct st_mpu { + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + unsigned long :4; + } BIT; + } RSPAGE0; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE0; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + unsigned long :4; + } BIT; + } RSPAGE1; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE1; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + unsigned long :4; + } BIT; + } RSPAGE2; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE2; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + unsigned long :4; + } BIT; + } RSPAGE3; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE3; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + unsigned long :4; + } BIT; + } RSPAGE4; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE4; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + unsigned long :4; + } BIT; + } RSPAGE5; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE5; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + unsigned long :4; + } BIT; + } RSPAGE6; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE6; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + unsigned long :4; + } BIT; + } RSPAGE7; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE7; + char wk0[192]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long MPEN:1; + } BIT; + } MPEN; + union { + unsigned long LONG; + struct { + unsigned long :28; + unsigned long UBAC:3; + unsigned long :1; + } BIT; + } MPBAC; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long CLR:1; + } BIT; + } MPECLR; + union { + unsigned long LONG; + struct { + unsigned long :29; + unsigned long DRW:1; + unsigned long DMPER:1; + unsigned long IMPER:1; + } BIT; + } MPESTS; + char wk1[4]; + union { + unsigned long LONG; + struct { + unsigned long DEA:32; + } BIT; + } MPDEA; + char wk2[8]; + union { + unsigned long LONG; + struct { + unsigned long SA:32; + } BIT; + } MPSA; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short S:1; + } BIT; + } MPOPS; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short INV:1; + } BIT; + } MPOPI; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long HITI:8; + unsigned long :12; + unsigned long UHACI:3; + unsigned long :1; + } BIT; + } MHITI; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long HITD:8; + unsigned long :12; + unsigned long UHACD:3; + unsigned long :1; + } BIT; + } MHITD; +}; + +struct st_mtu { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char OE4D:1; + unsigned char OE4C:1; + unsigned char OE3D:1; + unsigned char OE4B:1; + unsigned char OE4A:1; + unsigned char OE3B:1; + } BIT; + } TOER; + char wk0[2]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char BDC:1; + unsigned char N:1; + unsigned char P:1; + unsigned char FB:1; + unsigned char WF:1; + unsigned char VF:1; + unsigned char UF:1; + } BIT; + } TGCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PSYE:1; + unsigned char :2; + unsigned char TOCL:1; + unsigned char TOCS:1; + unsigned char OLSN:1; + unsigned char OLSP:1; + } BIT; + } TOCR1; + union { + unsigned char BYTE; + struct { + unsigned char BF:2; + unsigned char OLS3N:1; + unsigned char OLS3P:1; + unsigned char OLS2N:1; + unsigned char OLS2P:1; + unsigned char OLS1N:1; + unsigned char OLS1P:1; + } BIT; + } TOCR2; + char wk1[4]; + unsigned short TCDR; + unsigned short TDDR; + char wk2[8]; + unsigned short TCNTS; + unsigned short TCBR; + char wk3[12]; + union { + unsigned char BYTE; + struct { + unsigned char T3AEN:1; + unsigned char T3ACOR:3; + unsigned char T4VEN:1; + unsigned char T4VCOR:3; + } BIT; + } TITCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char T3ACNT:3; + unsigned char :1; + unsigned char T4VCNT:3; + } BIT; + } TITCNT; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char BTE:2; + } BIT; + } TBTER; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TDER:1; + } BIT; + } TDER; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char OLS3N:1; + unsigned char OLS3P:1; + unsigned char OLS2N:1; + unsigned char OLS2P:1; + unsigned char OLS1N:1; + unsigned char OLS1P:1; + } BIT; + } TOLBR; + char wk6[41]; + union { + unsigned char BYTE; + struct { + unsigned char CCE:1; + unsigned char :6; + unsigned char WRE:1; + } BIT; + } TWCR; + char wk7[31]; + union { + unsigned char BYTE; + struct { + unsigned char CST4:1; + unsigned char CST3:1; + unsigned char :3; + unsigned char CST2:1; + unsigned char CST1:1; + unsigned char CST0:1; + } BIT; + } TSTR; + union { + unsigned char BYTE; + struct { + unsigned char SYNC4:1; + unsigned char SYNC3:1; + unsigned char :3; + unsigned char SYNC2:1; + unsigned char SYNC1:1; + unsigned char SYNC0:1; + } BIT; + } TSYR; + char wk8[2]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char RWE:1; + } BIT; + } TRWER; +}; + +struct st_mtu0 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk0[111]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char BFE:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :2; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :7; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; + char wk1[16]; + unsigned short TGRE; + unsigned short TGRF; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TGIEF:1; + unsigned char TGIEE:1; + } BIT; + } TIER2; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TTSE:1; + unsigned char TTSB:1; + unsigned char TTSA:1; + } BIT; + } TBTM; +}; + +struct st_mtu1 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk1[238]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char CCLR:2; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :7; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + char wk3[4]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char I2BE:1; + unsigned char I2AE:1; + unsigned char I1BE:1; + unsigned char I1AE:1; + } BIT; + } TICCR; +}; + +struct st_mtu2 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk0[365]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char CCLR:2; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :7; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_mtu3 { + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :2; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + char wk3[7]; + unsigned short TCNT; + char wk4[6]; + unsigned short TGRA; + unsigned short TGRB; + char wk5[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk6[4]; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :7; + } BIT; + } TSR; + char wk7[11]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TTSE:1; + unsigned char TTSB:1; + unsigned char TTSA:1; + } BIT; + } TBTM; + char wk8[90]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; +}; + +struct st_mtu4 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + char wk3[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char TTGE2:1; + unsigned char :1; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + char wk4[8]; + unsigned short TCNT; + char wk5[8]; + unsigned short TGRA; + unsigned short TGRB; + char wk6[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk7[1]; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :7; + } BIT; + } TSR; + char wk8[11]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TTSE:1; + unsigned char TTSB:1; + unsigned char TTSA:1; + } BIT; + } TBTM; + char wk9[6]; + union { + unsigned short WORD; + struct { + unsigned short BF:2; + unsigned short :6; + unsigned short UT4AE:1; + unsigned short DT4AE:1; + unsigned short UT4BE:1; + unsigned short DT4BE:1; + unsigned short ITA3AE:1; + unsigned short ITA4VE:1; + unsigned short ITB3AE:1; + unsigned short ITB4VE:1; + } BIT; + } TADCR; + char wk10[2]; + unsigned short TADCORA; + unsigned short TADCORB; + unsigned short TADCOBRA; + unsigned short TADCOBRB; + char wk11[72]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; +}; + +struct st_mtu5 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char :1; + unsigned char NFWEN:1; + unsigned char NFVEN:1; + unsigned char NFUEN:1; + } BIT; + } NFCR; + char wk1[490]; + unsigned short TCNTU; + unsigned short TGRU; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TPSC:2; + } BIT; + } TCRU; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char IOC:5; + } BIT; + } TIORU; + char wk3[9]; + unsigned short TCNTV; + unsigned short TGRV; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TPSC:2; + } BIT; + } TCRV; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char IOC:5; + } BIT; + } TIORV; + char wk5[9]; + unsigned short TCNTW; + unsigned short TGRW; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TPSC:2; + } BIT; + } TCRW; + char wk6[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char IOC:5; + } BIT; + } TIORW; + char wk7[11]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TGIE5U:1; + unsigned char TGIE5V:1; + unsigned char TGIE5W:1; + } BIT; + } TIER; + char wk8[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char CSTU5:1; + unsigned char CSTV5:1; + unsigned char CSTW5:1; + } BIT; + } TSTR; + char wk9[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char CMPCLR5U:1; + unsigned char CMPCLR5V:1; + unsigned char CMPCLR5W:1; + } BIT; + } TCNTCMPCLR; +}; + +struct st_poe { + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned char POE3F:1; + unsigned char POE2F:1; + unsigned char POE1F:1; + unsigned char POE0F:1; + unsigned char :3; + unsigned char PIE1:1; + unsigned char POE3M:2; + unsigned char POE2M:2; + unsigned char POE1M:2; + unsigned char POE0M:2; + } BIT; + } ICSR1; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned char OSF1:1; + unsigned char :5; + unsigned char OCE1:1; + unsigned char OIE1:1; + unsigned char :8; + } BIT; + } OCSR1; + char wk0[4]; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned char :3; + unsigned char POE8F:1; + unsigned char :2; + unsigned char POE8E:1; + unsigned char PIE2:1; + unsigned char :6; + unsigned char POE8M:2; + } BIT; + } ICSR2; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char CH0HIZ:1; + unsigned char CH34HIZ:1; + } BIT; + } SPOER; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char PE3ZE:1; + unsigned char PE2ZE:1; + unsigned char PE1ZE:1; + unsigned char PE0ZE:1; + } BIT; + } POECR1; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char P1CZEA:1; + unsigned char P2CZEA:1; + unsigned char P3CZEA:1; + unsigned char :4; + } BIT; + } POECR2; + char wk1[1]; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned char :3; + unsigned char OSTSTF:1; + unsigned char :2; + unsigned char OSTSTE:1; + unsigned char :8; + unsigned char :1; + } BIT; + } ICSR3; +}; + +struct st_port { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL5:1; + unsigned char :1; + unsigned char PSEL3:1; + unsigned char :1; + unsigned char PSEL1:1; + unsigned char PSEL0:1; + } BIT; + } PSRB; + union { + unsigned char BYTE; + struct { + unsigned char PSEL7:1; + unsigned char PSEL6:1; + unsigned char :6; + } BIT; + } PSRA; +}; + +struct st_port0 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char :3; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char :3; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char :3; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char :3; + } BIT; + } PMR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char :3; + } BIT; + } PCR; +}; + +struct st_port1 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char :2; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char :2; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char :2; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char :2; + } BIT; + } PMR; + char wk3[32]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :4; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[61]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char :2; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char :2; + } BIT; + } DSCR; +}; + +struct st_port2 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[33]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[60]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_port3 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[34]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :3; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[59]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_port4 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_port5 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[36]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[57]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_porta { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[41]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[52]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_portb { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[42]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[51]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_portc { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[43]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[50]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_portd { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk4[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_porte { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[45]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[48]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_porth { + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk4[31]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_portj { + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char B3:1; + unsigned char :3; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char B3:1; + unsigned char :3; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char B3:1; + unsigned char :3; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char B3:1; + unsigned char :3; + } BIT; + } PMR; + char wk3[49]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char B3:1; + unsigned char :3; + } BIT; + } ODR0; + char wk4[45]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char B3:1; + unsigned char :3; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char B3:1; + unsigned char :3; + } BIT; + } DSCR; +}; + +struct st_riic { + union { + unsigned char BYTE; + struct { + unsigned char ICE:1; + unsigned char IICRST:1; + unsigned char CLO:1; + unsigned char SOWP:1; + unsigned char SCLO:1; + unsigned char SDAO:1; + unsigned char SCLI:1; + unsigned char SDAI:1; + } BIT; + } ICCR1; + union { + unsigned char BYTE; + struct { + unsigned char BBSY:1; + unsigned char MST:1; + unsigned char TRS:1; + unsigned char :1; + unsigned char SP:1; + unsigned char RS:1; + unsigned char ST:1; + unsigned char :1; + } BIT; + } ICCR2; + union { + unsigned char BYTE; + struct { + unsigned char MTWP:1; + unsigned char CKS:3; + unsigned char BCWP:1; + unsigned char BC:3; + } BIT; + } ICMR1; + union { + unsigned char BYTE; + struct { + unsigned char DLCS:1; + unsigned char SDDL:3; + unsigned char :1; + unsigned char TMOH:1; + unsigned char TMOL:1; + unsigned char TMOS:1; + } BIT; + } ICMR2; + union { + unsigned char BYTE; + struct { + unsigned char SMBS:1; + unsigned char WAIT:1; + unsigned char RDRFS:1; + unsigned char ACKWP:1; + unsigned char ACKBT:1; + unsigned char ACKBR:1; + unsigned char NF:2; + } BIT; + } ICMR3; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SCLE:1; + unsigned char NFE:1; + unsigned char NACKE:1; + unsigned char SALE:1; + unsigned char NALE:1; + unsigned char MALE:1; + unsigned char TMOE:1; + } BIT; + } ICFER; + union { + unsigned char BYTE; + struct { + unsigned char HOAE:1; + unsigned char :1; + unsigned char DIDE:1; + unsigned char :1; + unsigned char GCAE:1; + unsigned char SAR2E:1; + unsigned char SAR1E:1; + unsigned char SAR0E:1; + } BIT; + } ICSER; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char TEIE:1; + unsigned char RIE:1; + unsigned char NAKIE:1; + unsigned char SPIE:1; + unsigned char STIE:1; + unsigned char ALIE:1; + unsigned char TMOIE:1; + } BIT; + } ICIER; + union { + unsigned char BYTE; + struct { + unsigned char HOA:1; + unsigned char :1; + unsigned char DID:1; + unsigned char :1; + unsigned char GCA:1; + unsigned char AAS2:1; + unsigned char AAS1:1; + unsigned char AAS0:1; + } BIT; + } ICSR1; + union { + unsigned char BYTE; + struct { + unsigned char TDRE:1; + unsigned char TEND:1; + unsigned char RDRF:1; + unsigned char NACKF:1; + unsigned char STOP:1; + unsigned char START:1; + unsigned char AL:1; + unsigned char TMOF:1; + } BIT; + } ICSR2; + union { + unsigned char BYTE; + struct { + unsigned char SVA:7; + unsigned char SVA0:1; + } BIT; + } SARL0; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SVA:2; + unsigned char FS:1; + } BIT; + } SARU0; + union { + unsigned char BYTE; + struct { + unsigned char SVA:7; + unsigned char SVA0:1; + } BIT; + } SARL1; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SVA:2; + unsigned char FS:1; + } BIT; + } SARU1; + union { + unsigned char BYTE; + struct { + unsigned char SVA:7; + unsigned char SVA0:1; + } BIT; + } SARL2; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SVA:2; + unsigned char FS:1; + } BIT; + } SARU2; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char BRL:5; + } BIT; + } ICBRL; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char BRH:5; + } BIT; + } ICBRH; + unsigned char ICDRT; + unsigned char ICDRR; +}; + +struct st_rspi { + union { + unsigned char BYTE; + struct { + unsigned char SPRIE:1; + unsigned char SPE:1; + unsigned char SPTIE:1; + unsigned char SPEIE:1; + unsigned char MSTR:1; + unsigned char MODFEN:1; + unsigned char TXMD:1; + unsigned char SPMS:1; + } BIT; + } SPCR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char SSL3P:1; + unsigned char SSL2P:1; + unsigned char SSL1P:1; + unsigned char SSL0P:1; + } BIT; + } SSLP; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char MOIFE:1; + unsigned char MOIFV:1; + unsigned char :2; + unsigned char SPLP2:1; + unsigned char SPLP:1; + } BIT; + } SPPCR; + union { + unsigned char BYTE; + struct { + unsigned char SPRF:1; + unsigned char :1; + unsigned char SPTEF:1; + unsigned char :1; + unsigned char PERF:1; + unsigned char MODF:1; + unsigned char IDLNF:1; + unsigned char OVRF:1; + } BIT; + } SPSR; + union { + unsigned long LONG; + struct { + unsigned short H; + } WORD; + } SPDR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SPSLN:3; + } BIT; + } SPSCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SPECM:3; + unsigned char :1; + unsigned char SPCP:3; + } BIT; + } SPSSR; + unsigned char SPBR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char SPLW:1; + unsigned char SPRDTD:1; + unsigned char :2; + unsigned char SPFC:2; + } BIT; + } SPDCR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SCKDL:3; + } BIT; + } SPCKD; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SLNDL:3; + } BIT; + } SSLND; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SPNDL:3; + } BIT; + } SPND; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char SCKASE:1; + unsigned char PTE:1; + unsigned char SPIIE:1; + unsigned char SPOE:1; + unsigned char SPPE:1; + } BIT; + } SPCR2; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD0; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD1; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD2; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD3; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD4; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD5; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD6; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD7; +}; + +struct st_rtc { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char F1HZ:1; + unsigned char F2HZ:1; + unsigned char F4HZ:1; + unsigned char F8HZ:1; + unsigned char F16HZ:1; + unsigned char F32HZ:1; + unsigned char F64HZ:1; + } BIT; + } R64CNT; + char wk0[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECCNT; + unsigned char BCNT0; + }; + char wk1[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINCNT; + unsigned char BCNT1; + }; + char wk2[1]; + union { + unsigned char BCNT2; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PM:1; + unsigned char HR10:2; + unsigned char HR1:4; + } BIT; + } RHRCNT; + }; + char wk3[1]; + union { + unsigned char BCNT3; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char DAYW:3; + } BIT; + } RWKCNT; + }; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char DATE10:2; + unsigned char DATE1:4; + } BIT; + } RDAYCNT; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONCNT; + char wk6[1]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short YR10:4; + unsigned short YR1:4; + } BIT; + } RYRCNT; + union { + unsigned char BCNT0AR; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECAR; + }; + char wk7[1]; + union { + unsigned char BCNT1AR; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINAR; + }; + char wk8[1]; + union { + unsigned char BCNT2AR; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char PM:1; + unsigned char HR10:2; + unsigned char HR1:4; + } BIT; + } RHRAR; + }; + char wk9[1]; + union { + unsigned char BCNT3AR; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :4; + unsigned char DAYW:3; + } BIT; + } RWKAR; + }; + char wk10[1]; + union { + unsigned char BCNT0AER; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :1; + unsigned char DATE10:2; + unsigned char DATE1:4; + } BIT; + } RDAYAR; + }; + char wk11[1]; + union { + unsigned char BCNT1AER; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :2; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONAR; + }; + char wk12[1]; + union { + unsigned short BCNT2AER; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short YR10:4; + unsigned short YR1:4; + } BIT; + } RYRAR; + }; + union { + unsigned char BCNT3AER; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :7; + } BIT; + } RYRAREN; + }; + char wk13[3]; + union { + unsigned char BYTE; + struct { + unsigned char PES:4; + unsigned char RTCOS:1; + unsigned char PIE:1; + unsigned char CIE:1; + unsigned char AIE:1; + } BIT; + } RCR1; + char wk14[1]; + union { + unsigned char BYTE; + struct { + unsigned char CNTMD:1; + unsigned char HR24:1; + unsigned char AADJP:1; + unsigned char AADJE:1; + unsigned char RTCOE:1; + unsigned char ADJ30:1; + unsigned char RESET:1; + unsigned char START:1; + } BIT; + } RCR2; + char wk15[1]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char RTCDV:3; + unsigned char RTCEN:1; + } BIT; + } RCR3; + char wk16[7]; + union { + unsigned char BYTE; + struct { + unsigned char PMADJ:2; + unsigned char ADJ:6; + } BIT; + } RADJ; + char wk17[17]; + union { + unsigned char BYTE; + struct { + unsigned char TCEN:1; + unsigned char :1; + unsigned char TCNF:2; + unsigned char :1; + unsigned char TCST:1; + unsigned char TCCT:2; + } BIT; + } RTCCR0; + char wk18[1]; + union { + unsigned char BYTE; + struct { + unsigned char TCEN:1; + unsigned char :1; + unsigned char TCNF:2; + unsigned char :1; + unsigned char TCST:1; + unsigned char TCCT:2; + } BIT; + } RTCCR1; + char wk19[1]; + union { + unsigned char BYTE; + struct { + unsigned char TCEN:1; + unsigned char :1; + unsigned char TCNF:2; + unsigned char :1; + unsigned char TCST:1; + unsigned char TCCT:2; + } BIT; + } RTCCR2; + char wk20[13]; + union { + unsigned char BCNT0CP0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECCP0; + }; + char wk21[1]; + union { + unsigned char BCNT1CP0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINCP0; + }; + char wk22[1]; + union { + unsigned char BCNT2CP0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PM:1; + unsigned char HR10:2; + unsigned char HR1:4; + } BIT; + } RHRCP0; + }; + char wk23[3]; + union { + unsigned char BCNT3CP0; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char DATE10:2; + unsigned char DATE1:4; + } BIT; + } RDAYCP0; + }; + char wk24[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONCP0; + char wk25[5]; + union { + unsigned char BCNT0CP1; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECCP1; + }; + char wk26[1]; + union { + unsigned char BCNT1CP1; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINCP1; + }; + char wk27[1]; + union { + unsigned char BCNT2CP1; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PM:1; + unsigned char HR10:2; + unsigned char HR1:4; + } BIT; + } RHRCP1; + }; + char wk28[3]; + union { + unsigned char BCNT3CP1; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char DATE10:2; + unsigned char DATE1:4; + } BIT; + } RDAYCP1; + }; + char wk29[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONCP1; + char wk30[5]; + union { + unsigned char BCNT0CP2; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECCP2; + }; + char wk31[1]; + union { + unsigned char BCNT1CP2; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINCP2; + }; + char wk32[1]; + union { + unsigned char BCNT2CP2; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PM:1; + unsigned char HR10:2; + unsigned char HR1:4; + } BIT; + } RHRCP2; + }; + char wk33[3]; + union { + unsigned char BCNT3CP2; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char DATE10:2; + unsigned char DATE1:4; + } BIT; + } RDAYCP2; + }; + char wk34[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONCP2; +}; + +struct st_s12ad { + union { + unsigned short WORD; + struct { + unsigned short ADST:1; + unsigned short ADCS:2; + unsigned short ADIE:1; + unsigned short :1; + unsigned short ADHSC:1; + unsigned short TRGE:1; + unsigned short EXTRG:1; + unsigned short DBLE:1; + unsigned short GBADIE:1; + unsigned short :1; + unsigned short DBLANS:5; + } BIT; + } ADCSR; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short ANSA007:1; + unsigned short ANSA006:1; + unsigned short ANSA005:1; + unsigned short ANSA004:1; + unsigned short ANSA003:1; + unsigned short ANSA002:1; + unsigned short ANSA001:1; + unsigned short ANSA000:1; + } BIT; + } ADANSA0; + union { + unsigned short WORD; + struct { + unsigned short ANSA115:1; + unsigned short ANSA114:1; + unsigned short ANSA113:1; + unsigned short ANSA112:1; + unsigned short ANSA111:1; + unsigned short ANSA110:1; + unsigned short ANSA109:1; + unsigned short ANSA108:1; + unsigned short ANSA107:1; + unsigned short ANSA106:1; + unsigned short ANSA105:1; + unsigned short ANSA104:1; + unsigned short ANSA103:1; + unsigned short ANSA102:1; + unsigned short ANSA101:1; + unsigned short ANSA100:1; + } BIT; + } ADANSA1; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short ADS007:1; + unsigned short ADS006:1; + unsigned short ADS005:1; + unsigned short ADS004:1; + unsigned short ADS003:1; + unsigned short ADS002:1; + unsigned short ADS001:1; + unsigned short ADS000:1; + } BIT; + } ADADS0; + union { + unsigned short WORD; + struct { + unsigned short ADS115:1; + unsigned short ADS114:1; + unsigned short ADS113:1; + unsigned short ADS112:1; + unsigned short ADS111:1; + unsigned short ADS110:1; + unsigned short ADS109:1; + unsigned short ADS108:1; + unsigned short ADS107:1; + unsigned short ADS106:1; + unsigned short ADS105:1; + unsigned short ADS104:1; + unsigned short ADS103:1; + unsigned short ADS102:1; + unsigned short ADS101:1; + unsigned short ADS100:1; + } BIT; + } ADADS1; + union { + unsigned char BYTE; + struct { + unsigned char AVEE:1; + unsigned char :4; + unsigned char ADC:3; + } BIT; + } ADADC; + char wk1[1]; + union { + unsigned short WORD; + struct { + unsigned short ADRFMT:1; + unsigned short :3; + unsigned short DIAGM:1; + unsigned short DIAGLD:1; + unsigned short DIAGVAL:2; + unsigned short :2; + unsigned short ACE:1; + unsigned short :5; + } BIT; + } ADCER; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short TRSA:6; + unsigned short :2; + unsigned short TRSB:6; + } BIT; + } ADSTRGR; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short OCSA:1; + unsigned short TSSA:1; + unsigned short :6; + unsigned short OCSAD:1; + unsigned short TSSAD:1; + } BIT; + } ADEXICR; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short ANSB007:1; + unsigned short ANSB006:1; + unsigned short ANSB005:1; + unsigned short ANSB004:1; + unsigned short ANSB003:1; + unsigned short ANSB002:1; + unsigned short ANSB001:1; + unsigned short ANSB000:1; + } BIT; + } ADANSB0; + union { + unsigned short WORD; + struct { + unsigned short ANSB115:1; + unsigned short ANSB114:1; + unsigned short ANSB113:1; + unsigned short ANSB112:1; + unsigned short ANSB111:1; + unsigned short ANSB110:1; + unsigned short ANSB109:1; + unsigned short ANSB108:1; + unsigned short ANSB107:1; + unsigned short ANSB106:1; + unsigned short ANSB105:1; + unsigned short ANSB104:1; + unsigned short ANSB103:1; + unsigned short ANSB102:1; + unsigned short ANSB101:1; + unsigned short ANSB100:1; + } BIT; + } ADANSB1; + unsigned short ADDBLDR; + unsigned short ADTSDR; + unsigned short ADOCDR; + union { + unsigned short WORD; + union { + struct { + unsigned short DIAGST:2; + unsigned short :2; + unsigned short AD:12; + } RIGHT; + struct { + unsigned short AD:12; + unsigned short :2; + unsigned short DIAGST:2; + } LEFT; + } BIT; + } ADRD; + unsigned short ADDR0; + unsigned short ADDR1; + unsigned short ADDR2; + unsigned short ADDR3; + unsigned short ADDR4; + unsigned short ADDR5; + unsigned short ADDR6; + unsigned short ADDR7; + char wk2[16]; + unsigned short ADDR16; + unsigned short ADDR17; + unsigned short ADDR18; + unsigned short ADDR19; + unsigned short ADDR20; + unsigned short ADDR21; + unsigned short ADDR22; + unsigned short ADDR23; + unsigned short ADDR24; + unsigned short ADDR25; + unsigned short ADDR26; + unsigned short ADDR27; + unsigned short ADDR28; + unsigned short ADDR29; + unsigned short ADDR30; + unsigned short ADDR31; + char wk4[26]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char ADNDIS:5; + } BIT; + } ADDISCR; + char wk5[2]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char ELCC:2; + } BIT; + } ADELCCR; + char wk6[2]; + union { + unsigned short WORD; + struct { + unsigned short GBRP:1; + unsigned short :13; + unsigned short GBRSCN:1; + unsigned short PGS:1; + } BIT; + } ADGSPCR; + char wk7[8]; + union { + unsigned char BYTE; + struct { + unsigned char ADSLP:1; + unsigned char :2; + unsigned char LVSEL:1; + unsigned char :2; + unsigned char HVSEL:2; + } BIT; + } ADHVREFCNT; + char wk8[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char MONCMPB:1; + unsigned char MONCMPA:1; + unsigned char :3; + unsigned char MONCOMB:1; + } BIT; + } ADWINMON; + char wk9[3]; + union { + unsigned short WORD; + struct { + unsigned short :1; + unsigned short WCMPE:1; + unsigned short :2; + unsigned short CMPAE:1; + unsigned short :1; + unsigned short CMPBE:1; + unsigned short :7; + unsigned short CMPAB:2; + } BIT; + } ADCMPCR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char CMPOCA:1; + unsigned char CMPTSA:1; + } BIT; + } ADCMPANSER; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char CMPLOCA:1; + unsigned char CMPLTSA:1; + } BIT; + } ADCMPLER; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short CMPCHA007:1; + unsigned short CMPCHA006:1; + unsigned short CMPCHA005:1; + unsigned short CMPCHA004:1; + unsigned short CMPCHA003:1; + unsigned short CMPCHA002:1; + unsigned short CMPCHA001:1; + unsigned short CMPCHA000:1; + } BIT; + } ADCMPANSR0; + union { + unsigned short WORD; + struct { + unsigned short CMPCHA115:1; + unsigned short CMPCHA114:1; + unsigned short CMPCHA113:1; + unsigned short CMPCHA112:1; + unsigned short CMPCHA111:1; + unsigned short CMPCHA110:1; + unsigned short CMPCHA109:1; + unsigned short CMPCHA108:1; + unsigned short CMPCHA107:1; + unsigned short CMPCHA106:1; + unsigned short CMPCHA105:1; + unsigned short CMPCHA104:1; + unsigned short CMPCHA103:1; + unsigned short CMPCHA102:1; + unsigned short CMPCHA101:1; + unsigned short CMPCHA100:1; + } BIT; + } ADCMPANSR1; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short CMPLCHA007:1; + unsigned short CMPLCHA006:1; + unsigned short CMPLCHA005:1; + unsigned short CMPLCHA004:1; + unsigned short CMPLCHA003:1; + unsigned short CMPLCHA002:1; + unsigned short CMPLCHA001:1; + unsigned short CMPLCHA000:1; + } BIT; + } ADCMPLR0; + union { + unsigned short WORD; + struct { + unsigned short CMPLCHA115:1; + unsigned short CMPLCHA114:1; + unsigned short CMPLCHA113:1; + unsigned short CMPLCHA112:1; + unsigned short CMPLCHA111:1; + unsigned short CMPLCHA110:1; + unsigned short CMPLCHA109:1; + unsigned short CMPLCHA108:1; + unsigned short CMPLCHA107:1; + unsigned short CMPLCHA106:1; + unsigned short CMPLCHA105:1; + unsigned short CMPLCHA104:1; + unsigned short CMPLCHA103:1; + unsigned short CMPLCHA102:1; + unsigned short CMPLCHA101:1; + unsigned short CMPLCHA100:1; + } BIT; + } ADCMPLR1; + unsigned short ADCMPDR0; + unsigned short ADCMPDR1; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short CMPSTCHA007:1; + unsigned short CMPSTCHA006:1; + unsigned short CMPSTCHA005:1; + unsigned short CMPSTCHA004:1; + unsigned short CMPSTCHA003:1; + unsigned short CMPSTCHA002:1; + unsigned short CMPSTCHA001:1; + unsigned short CMPSTCHA000:1; + } BIT; + } ADCMPSR0; + union { + unsigned short WORD; + struct { + unsigned short CMPSTCHA115:1; + unsigned short CMPSTCHA114:1; + unsigned short CMPSTCHA113:1; + unsigned short CMPSTCHA112:1; + unsigned short CMPSTCHA111:1; + unsigned short CMPSTCHA110:1; + unsigned short CMPSTCHA109:1; + unsigned short CMPSTCHA108:1; + unsigned short CMPSTCHA107:1; + unsigned short CMPSTCHA106:1; + unsigned short CMPSTCHA105:1; + unsigned short CMPSTCHA104:1; + unsigned short CMPSTCHA103:1; + unsigned short CMPSTCHA102:1; + unsigned short CMPSTCHA101:1; + unsigned short CMPSTCHA100:1; + } BIT; + } ADCMPSR1; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char CMPSTOCA:1; + unsigned char CMPSTTSA:1; + } BIT; + } ADCMPSER; + char wk10[1]; + union { + unsigned char BYTE; + struct { + unsigned char CMPLB:1; + unsigned char :1; + unsigned char CMPCHB:6; + } BIT; + } ADCMPBNSR; + char wk11[1]; + unsigned short ADWINLLB; + unsigned short ADWINULB; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char CMPSTB:1; + } BIT; + } ADCMPBSR; + char wk12[3]; + unsigned short ADBUF0; + unsigned short ADBUF1; + unsigned short ADBUF2; + unsigned short ADBUF3; + unsigned short ADBUF4; + unsigned short ADBUF5; + unsigned short ADBUF6; + unsigned short ADBUF7; + unsigned short ADBUF8; + unsigned short ADBUF9; + unsigned short ADBUF10; + unsigned short ADBUF11; + unsigned short ADBUF12; + unsigned short ADBUF13; + unsigned short ADBUF14; + unsigned short ADBUF15; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char BUFEN:1; + } BIT; + } ADBUFEN; + char wk13[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PTROVF:1; + unsigned char BUFPTR:4; + } BIT; + } ADBUFPTR; + char wk14[10]; + unsigned char ADSSTRL; + unsigned char ADSSTRT; + unsigned char ADSSTRO; + unsigned char ADSSTR0; + unsigned char ADSSTR1; + unsigned char ADSSTR2; + unsigned char ADSSTR3; + unsigned char ADSSTR4; + unsigned char ADSSTR5; + unsigned char ADSSTR6; + unsigned char ADSSTR7; +}; + +struct st_sci0 { + union { + unsigned char BYTE; + struct { + unsigned char CM:1; + unsigned char CHR:1; + unsigned char PE:1; + unsigned char PM:1; + unsigned char STOP:1; + unsigned char MP:1; + unsigned char CKS:2; + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char RIE:1; + unsigned char TE:1; + unsigned char RE:1; + unsigned char MPIE:1; + unsigned char TEIE:1; + unsigned char CKE:2; + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + unsigned char TDRE:1; + unsigned char RDRF:1; + unsigned char ORER:1; + unsigned char FER:1; + unsigned char PER:1; + unsigned char TEND:1; + unsigned char MPB:1; + unsigned char MPBT:1; + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + unsigned char BCP2:1; + unsigned char :2; + unsigned char CHR1:1; + unsigned char SDIR:1; + unsigned char SINV:1; + unsigned char :1; + unsigned char SMIF:1; + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + unsigned char RXDESEL:1; + unsigned char BGDM:1; + unsigned char NFEN:1; + unsigned char ABCS:1; + unsigned char :1; + unsigned char BRME:1; + unsigned char :1; + unsigned char ACS0:1; + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char NFCS:3; + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + unsigned char IICDL:5; + unsigned char :2; + unsigned char IICM:1; + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char IICACKT:1; + unsigned char :3; + unsigned char IICCSC:1; + unsigned char IICINTM:1; + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + unsigned char IICSCLS:2; + unsigned char IICSDAS:2; + unsigned char IICSTIF:1; + unsigned char IICSTPREQ:1; + unsigned char IICRSTAREQ:1; + unsigned char IICSTAREQ:1; + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char IICACKR:1; + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + unsigned char CKPH:1; + unsigned char CKPOL:1; + unsigned char :1; + unsigned char MFF:1; + unsigned char :1; + unsigned char MSS:1; + unsigned char CTSE:1; + unsigned char SSE:1; + } BIT; + } SPMR; + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + unsigned char MDDR; +}; + +struct st_sci12 { + union { + unsigned char BYTE; + struct { + unsigned char CM:1; + unsigned char CHR:1; + unsigned char PE:1; + unsigned char PM:1; + unsigned char STOP:1; + unsigned char MP:1; + unsigned char CKS:2; + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char RIE:1; + unsigned char TE:1; + unsigned char RE:1; + unsigned char MPIE:1; + unsigned char TEIE:1; + unsigned char CKE:2; + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + unsigned char TDRE:1; + unsigned char RDRF:1; + unsigned char ORER:1; + unsigned char FER:1; + unsigned char PER:1; + unsigned char TEND:1; + unsigned char MPB:1; + unsigned char MPBT:1; + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + unsigned char BCP2:1; + unsigned char :2; + unsigned char CHR1:1; + unsigned char SDIR:1; + unsigned char SINV:1; + unsigned char :1; + unsigned char SMIF:1; + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + unsigned char RXDESEL:1; + unsigned char BGDM:1; + unsigned char NFEN:1; + unsigned char ABCS:1; + unsigned char :1; + unsigned char BRME:1; + unsigned char :1; + unsigned char ACS0:1; + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char NFCS:3; + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + unsigned char IICDL:5; + unsigned char :2; + unsigned char IICM:1; + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char IICACKT:1; + unsigned char :3; + unsigned char IICCSC:1; + unsigned char IICINTM:1; + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + unsigned char IICSCLS:2; + unsigned char IICSDAS:2; + unsigned char IICSTIF:1; + unsigned char IICSTPREQ:1; + unsigned char IICRSTAREQ:1; + unsigned char IICSTAREQ:1; + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char IICACKR:1; + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + unsigned char CKPH:1; + unsigned char CKPOL:1; + unsigned char :1; + unsigned char MFF:1; + unsigned char :1; + unsigned char MSS:1; + unsigned char CTSE:1; + unsigned char SSE:1; + } BIT; + } SPMR; + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + unsigned char MDDR; + char wk0[13]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char ESME:1; + } BIT; + } ESMER; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char BRME:1; + unsigned char RXDSF:1; + unsigned char SFSF:1; + unsigned char :1; + } BIT; + } CR0; + union { + unsigned char BYTE; + struct { + unsigned char PIBS:3; + unsigned char PIBE:1; + unsigned char CF1DS:2; + unsigned char CF0RE:1; + unsigned char BFE:1; + } BIT; + } CR1; + union { + unsigned char BYTE; + struct { + unsigned char RTS:2; + unsigned char BCCS:2; + unsigned char :1; + unsigned char DFCS:3; + } BIT; + } CR2; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SDST:1; + } BIT; + } CR3; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char SHARPS:1; + unsigned char :2; + unsigned char RXDXPS:1; + unsigned char TXDXPS:1; + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char AEDIE:1; + unsigned char BCDIE:1; + unsigned char PIBDIE:1; + unsigned char CF1MIE:1; + unsigned char CF0MIE:1; + unsigned char BFDIE:1; + } BIT; + } ICR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char AEDF:1; + unsigned char BCDF:1; + unsigned char PIBDF:1; + unsigned char CF1MF:1; + unsigned char CF0MF:1; + unsigned char BFDF:1; + } BIT; + } STR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char AEDCL:1; + unsigned char BCDCL:1; + unsigned char PIBDCL:1; + unsigned char CF1MCL:1; + unsigned char CF0MCL:1; + unsigned char BFDCL:1; + } BIT; + } STCR; + unsigned char CF0DR; + union { + unsigned char BYTE; + struct { + unsigned char CF0CE7:1; + unsigned char CF0CE6:1; + unsigned char CF0CE5:1; + unsigned char CF0CE4:1; + unsigned char CF0CE3:1; + unsigned char CF0CE2:1; + unsigned char CF0CE1:1; + unsigned char CF0CE0:1; + } BIT; + } CF0CR; + unsigned char CF0RR; + unsigned char PCF1DR; + unsigned char SCF1DR; + union { + unsigned char BYTE; + struct { + unsigned char CF1CE7:1; + unsigned char CF1CE6:1; + unsigned char CF1CE5:1; + unsigned char CF1CE4:1; + unsigned char CF1CE3:1; + unsigned char CF1CE2:1; + unsigned char CF1CE1:1; + unsigned char CF1CE0:1; + } BIT; + } CF1CR; + unsigned char CF1RR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TCST:1; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char TCSS:3; + unsigned char TWRC:1; + unsigned char :1; + unsigned char TOMS:2; + } BIT; + } TMR; + unsigned char TPRE; + unsigned char TCNT; +}; + +struct st_sdhi { + union { + unsigned long LONG; +// struct { +// unsigned long :16; +// unsigned long CMD12AT:2; +// unsigned long TRSTP:1; +// unsigned long CMDRW:1; +// unsigned long CMDTP:1; +// unsigned long RSPTP:3; +// unsigned long ACMD:2; +// unsigned long CMDIDX:6; +// } BIT; + } SDCMD; + char wk0[4]; + unsigned long SDARG; + char wk1[4]; + union { + unsigned long LONG; + struct { + unsigned long :23; + unsigned long SDBLKCNTEN:1; + unsigned long :7; + unsigned long STP:1; + } BIT; + } SDSTOP; + unsigned long SDBLKCNT; + unsigned long SDRSP10; + char wk2[4]; + unsigned long SDRSP32; + char wk3[4]; + unsigned long SDRSP54; + char wk4[4]; + unsigned long SDRSP76; + char wk5[4]; + union { + unsigned long LONG; +// struct { +// unsigned long :21; +// unsigned long SDD3MON:1; +// unsigned long SDD3IN:1; +// unsigned long SDD3RM:1; +// unsigned long SDWPMON:1; +// unsigned long :1; +// unsigned long SDCDMON:1; +// unsigned long SDCDIN:1; +// unsigned long SDCDRM:1; +// unsigned long ACEND:1; +// unsigned long :1; +// unsigned long RSPEND:1; +// } BIT; + } SDSTS1; + union { + unsigned long LONG; +// struct { +// unsigned long :16; +// unsigned long ILA:1; +// unsigned long CBSY:1; +// unsigned long SDCLKCREN:1; +// unsigned long :3; +// unsigned long BWE:1; +// unsigned long BRE:1; +// unsigned long SDD0MON:1; +// unsigned long RSPTO:1; +// unsigned long ILR:1; +// unsigned long ILW:1; +// unsigned long DTO:1; +// unsigned long ENDE:1; +// unsigned long CRCE:1; +// unsigned long CMDE:1; +// } BIT; + } SDSTS2; + union { + unsigned long LONG; + struct { + unsigned long :22; + unsigned long SDD3INM:1; + unsigned long SDD3RMM:1; + unsigned long :3; + unsigned long SDCDINM:1; + unsigned long SDCDRMM:1; + unsigned long ACENDM:1; + unsigned long :1; + unsigned long RSPENDM:1; + } BIT; + } SDIMSK1; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long ILAM:1; + unsigned long :5; + unsigned long BWEM:1; + unsigned long BREM:1; + unsigned long :1; + unsigned long RSPTOM:1; + unsigned long ILRM:1; + unsigned long ILWM:1; + unsigned long DTTOM:1; + unsigned long ENDEM:1; + unsigned long CRCEM:1; + unsigned long CMDEM:1; + } BIT; + } SDIMSK2; + union { + unsigned long LONG; + struct { + unsigned long :22; + unsigned long CLKCTRLEN:1; + unsigned long CLKEN:1; + unsigned long CLKSEL:8; + } BIT; + } SDCLKCR; + union { + unsigned long LONG; + struct { + unsigned long :22; + unsigned long LEN:10; + } BIT; + } SDSIZE; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long WIDTH:1; + unsigned long :7; + unsigned long TOP:4; + unsigned long CTOP:4; + } BIT; + } SDOPT; + char wk6[4]; + union { + unsigned long LONG; + struct { + unsigned long :17; + unsigned long CRCTK:3; + unsigned long CRCTKE:1; + unsigned long RDCRCE:1; + unsigned long RSPCRCE1:1; + unsigned long RSPCRCE0:1; + unsigned long :2; + unsigned long CRCLENE:1; + unsigned long RDLENE:1; + unsigned long RSPLENE1:1; + unsigned long RSPLENE0:1; + unsigned long CMDE1:1; + unsigned long CMDE0:1; + } BIT; + } SDERSTS1; + union { + unsigned long LONG; + struct { + unsigned long :25; + unsigned long CRCBSYTO:1; + unsigned long CRCTO:1; + unsigned long RDTO:1; + unsigned long BSYTO1:1; + unsigned long BSYTO0:1; + unsigned long RSPTO1:1; + unsigned long RSPTO0:1; + } BIT; + } SDERSTS2; + unsigned long SDBUFR; + char wk7[4]; + union { + unsigned long LONG; + struct { + unsigned long :22; + unsigned long C52PUB:1; + unsigned long IOABT:1; + unsigned long :5; + unsigned long RWREQ:1; + unsigned long :1; + unsigned long INTEN:1; + } BIT; + } SDIOMD; + union { + unsigned long LONG; +// struct { +// unsigned long :16; +// unsigned long EXWT:1; +// unsigned long EXPUB52:1; +// unsigned long :13; +// unsigned long IOIRQ:1; +// } BIT; + } SDIOSTS; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long EXWTM:1; + unsigned long EXPUB52M:1; + unsigned long :13; + unsigned long IOIRQM:1; + } BIT; + } SDIOIMSK; + char wk8[316]; + union { + unsigned long LONG; + struct { + unsigned long :30; + unsigned long DMAEN:1; + unsigned long :1; + } BIT; + } SDDMAEN; + char wk9[12]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long SDRST:1; + } BIT; + } SDRST; + char wk10[28]; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long BRSWP:1; + unsigned long BWSWP:1; + unsigned long :6; + } BIT; + } SDSWAP; +}; + +struct st_smci { + union { + unsigned char BYTE; + struct { + unsigned char GM:1; + unsigned char BLK:1; + unsigned char PE:1; + unsigned char PM:1; + unsigned char BCP:2; + unsigned char CKS:2; + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char RIE:1; + unsigned char TE:1; + unsigned char RE:1; + unsigned char MPIE:1; + unsigned char TEIE:1; + unsigned char CKE:2; + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + unsigned char TDRE:1; + unsigned char RDRF:1; + unsigned char ORER:1; + unsigned char ERS:1; + unsigned char PER:1; + unsigned char TEND:1; + unsigned char MPB:1; + unsigned char MPBT:1; + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + unsigned char BCP2:1; + unsigned char :2; + unsigned char CHR1:1; + unsigned char SDIR:1; + unsigned char SINV:1; + unsigned char :1; + unsigned char SMIF:1; + } BIT; + } SCMR; + char wk0[7]; + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + unsigned char MDDR; +}; + +struct st_ssi { + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CKS:1; + unsigned long TUIEN:1; + unsigned long TOIEN:1; + unsigned long RUIEN:1; + unsigned long ROIEN:1; + unsigned long IIEN:1; + unsigned long :1; + unsigned long CHNL:2; + unsigned long DWL:3; + unsigned long SWL:3; + unsigned long SCKD:1; + unsigned long SWSD:1; + unsigned long SCKP:1; + unsigned long SWSP:1; + unsigned long SPDP:1; + unsigned long SDTA:1; + unsigned long PDTA:1; + unsigned long DEL:1; + unsigned long CKDV:4; + unsigned long MUEN:1; + unsigned long :1; + unsigned long TEN:1; + unsigned long REN:1; + } BIT; + } SSICR; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TUIRQ:1; + unsigned long TOIRQ:1; + unsigned long RUIRQ:1; + unsigned long ROIRQ:1; + unsigned long IIRQ:1; + unsigned long :18; + unsigned long TCHNO:2; + unsigned long TSWNO:1; + unsigned long RCHNO:2; + unsigned long RSWNO:1; + unsigned long IDST:1; + } BIT; + } SSISR; + char wk0[8]; + union { + unsigned long LONG; + struct { + unsigned long AUCKE:1; + unsigned long :14; + unsigned long SSIRST:1; + unsigned long :8; + unsigned long TTRG:2; + unsigned long RTRG:2; + unsigned long TIE:1; + unsigned long RIE:1; + unsigned long TFRST:1; + unsigned long RFRST:1; + } BIT; + } SSIFCR; + union { + unsigned long LONG; + struct { + unsigned long :4; + unsigned long TDC:4; + unsigned long :7; + unsigned long TDE:1; + unsigned long :4; + unsigned long RDC:4; + unsigned long :7; + unsigned long RDF:1; + } BIT; + } SSIFSR; + unsigned long SSIFTDR; + unsigned long SSIFRDR; + union { + unsigned long LONG; + struct { + unsigned long :23; + unsigned long CONT:1; + unsigned long :8; + } BIT; + } SSITDMR; +}; + +struct st_system { + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short MD:1; + } BIT; + } MDMONR; + char wk0[4]; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short :6; + unsigned short EXBE:1; + unsigned short ROME:1; + } BIT; + } SYSCR0; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short RAME:1; + } BIT; + } SYSCR1; + char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short SSBY:1; + unsigned short OPE:1; + unsigned short :14; + } BIT; + } SBYCR; + char wk2[2]; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long MSTPA28:1; + unsigned long :8; + unsigned long MSTPA19:1; + unsigned long :1; + unsigned long MSTPA17:1; + unsigned long :1; + unsigned long MSTPA15:1; + unsigned long MSTPA14:1; + unsigned long MSTPA13:1; + unsigned long :3; + unsigned long MSTPA9:1; + unsigned long :3; + unsigned long MSTPA5:1; + unsigned long MSTPA4:1; + unsigned long :4; + } BIT; + } MSTPCRA; + union { + unsigned long LONG; + struct { + unsigned long MSTPB31:1; + unsigned long MSTPB30:1; + unsigned long :3; + unsigned long MSTPB26:1; + unsigned long MSTPB25:1; + unsigned long :1; + unsigned long MSTPB23:1; + unsigned long :1; + unsigned long MSTPB21:1; + unsigned long :1; + unsigned long MSTPB19:1; + unsigned long :1; + unsigned long MSTPB17:1; + unsigned long :6; + unsigned long MSTPB10:1; + unsigned long MSTPB9:1; + unsigned long :2; + unsigned long MSTPB6:1; + unsigned long :1; + unsigned long MSTPB4:1; + unsigned long :3; + unsigned long MSTPB0:1; + } BIT; + } MSTPCRB; + union { + unsigned long LONG; + struct { + unsigned long DSLPE:1; + unsigned long MSTPC30:1; + unsigned long MSTPC29:1; + unsigned long MSTPC28:1; + unsigned long MSTPC27:1; + unsigned long MSTPC26:1; + unsigned long :5; + unsigned long MSTPC20:1; + unsigned long MSTPC19:1; + unsigned long :17; + unsigned long MSTPC1:1; + unsigned long MSTPC0:1; + } BIT; + } MSTPCRC; + union { + unsigned long LONG; + struct { + unsigned long MSTPD31:1; + unsigned long :11; + unsigned long MSTPD19:1; + unsigned long :3; + unsigned long MSTPD15:1; + unsigned long :4; + unsigned long MSTPD10:1; + unsigned long :10; + } BIT; + } MSTPCRD; + union { + unsigned long LONG; + struct { + unsigned long FCK:4; + unsigned long ICK:4; + unsigned long PSTOP1:1; + unsigned long :3; + unsigned long BCK:4; + unsigned long PCKA:4; + unsigned long PCKB:4; + unsigned long :4; + unsigned long PCKD:4; + } BIT; + } SCKCR; + char wk3[2]; + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short CKSEL:3; + unsigned short :8; + } BIT; + } SCKCR3; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short STC:6; + unsigned short :6; + unsigned short PLIDIV:2; + } BIT; + } PLLCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char PLLEN:1; + } BIT; + } PLLCR2; + char wk4[1]; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short USTC:6; + unsigned short :3; + unsigned short UCKUPLLSEL:1; + unsigned short :2; + unsigned short UPLIDIV:2; + } BIT; + } UPLLCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char UPLLEN:1; + } BIT; + } UPLLCR2; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char BCLKDIV:1; + } BIT; + } BCKCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char MEMWAIT:1; + } BIT; + } MEMWAIT; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char MOSTP:1; + } BIT; + } MOSCCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SOSTP:1; + } BIT; + } SOSCCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char LCSTP:1; + } BIT; + } LOCOCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char ILCSTP:1; + } BIT; + } ILOCOCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char HCSTP:1; + } BIT; + } HOCOCR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char HCFRQ:2; + } BIT; + } HOCOCR2; + char wk6[4]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char UPLOVF:1; + unsigned char :1; + unsigned char HCOVF:1; + unsigned char PLOVF:1; + unsigned char :1; + unsigned char MOOVF:1; + } BIT; + } OSCOVFSR; + char wk7[1]; + union { + unsigned short WORD; + struct { + unsigned short CKOSTP:1; + unsigned short CKODIV:3; + unsigned short CKOSEL:4; + unsigned short :8; + } BIT; + } CKOCR; + union { + unsigned char BYTE; + struct { + unsigned char OSTDE:1; + unsigned char :6; + unsigned char OSTDIE:1; + } BIT; + } OSTDCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char OSTDF:1; + } BIT; + } OSTDSR; + char wk8[30]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char LOCOTRD:5; + } BIT; + } LOCOTRR; + char wk9[3]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char ILOCOTRD:5; + } BIT; + } ILOCOTRR; + char wk10[3]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char HOCOTRD:6; + } BIT; + } HOCOTRR0; + char wk11[2]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char HOCOTRD:6; + } BIT; + } HOCOTRR3; + char wk12[52]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char OPCMTSF:1; + unsigned char :1; + unsigned char OPCM:3; + } BIT; + } OPCCR; + union { + unsigned char BYTE; + struct { + unsigned char RSTCKEN:1; + unsigned char :4; + unsigned char RSTCKSEL:3; + } BIT; + } RSTCKCR; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char MSTS:5; + } BIT; + } MOSCWTCR; + char wk13[7]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char SOPCMTSF:1; + unsigned char :3; + unsigned char SOPCM:1; + } BIT; + } SOPCCR; + char wk14[21]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SWRF:1; + unsigned char WDTRF:1; + unsigned char IWDTRF:1; + } BIT; + } RSTSR2; + char wk15[1]; + unsigned short SWRR; + char wk16[28]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char LVD1IRQSEL:1; + unsigned char LVD1IDTSEL:2; + } BIT; + } LVD1CR1; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char LVD1MON:1; + unsigned char LVD1DET:1; + } BIT; + } LVD1SR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char LVD2IRQSEL:1; + unsigned char LVD2IDTSEL:2; + } BIT; + } LVD2CR1; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char LVD2MON:1; + unsigned char LVD2DET:1; + } BIT; + } LVD2SR; + char wk17[794]; + union { + unsigned short WORD; + struct { + unsigned short PRKEY:8; + unsigned short :4; + unsigned short PRC3:1; + unsigned short PRC2:1; + unsigned short PRC1:1; + unsigned short PRC0:1; + } BIT; + } PRCR; + char wk18[48784]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char LVD2RF:1; + unsigned char LVD1RF:1; + unsigned char LVD0RF:1; + unsigned char PORF:1; + } BIT; + } RSTSR0; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char CWSF:1; + } BIT; + } RSTSR1; + char wk19[1]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MOSEL:1; + unsigned char MODRV21:1; + unsigned char :5; + } BIT; + } MOFCR; + char wk20[3]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char LVD2E:1; + unsigned char LVD1E:1; + unsigned char :1; + unsigned char EXVCCINP2:1; + unsigned char :3; + } BIT; + } LVCMPCR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char LVD2LVL:2; + unsigned char LVD1LVL:4; + } BIT; + } LVDLVLR; + char wk21[1]; + union { + unsigned char BYTE; + struct { + unsigned char LVD1RN:1; + unsigned char LVD1RI:1; + unsigned char :3; + unsigned char LVD1CMPE:1; + unsigned char :1; + unsigned char LVD1RIE:1; + } BIT; + } LVD1CR0; + union { + unsigned char BYTE; + struct { + unsigned char LVD2RN:1; + unsigned char LVD2RI:1; + unsigned char :3; + unsigned char LVD2CMPE:1; + unsigned char :1; + unsigned char LVD2RIE:1; + } BIT; + } LVD2CR0; + char wk22[1]; + union { + unsigned char BYTE; + struct { + unsigned char VBTLVDLVL:2; + unsigned char :1; + unsigned char VBTLVDEN:1; + unsigned char :3; + unsigned char VBATTDIS:1; + } BIT; + } VBATTCR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char VBTLVDMON:1; + unsigned char VBATRLVDETF:1; + } BIT; + } VBATTSR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char VBTLVDISEL:1; + unsigned char VBTLVDIE:1; + } BIT; + } VBTLVDICR; +}; + +struct st_tempsconst { + union { + unsigned long LONG; + struct { + unsigned long :4; + unsigned long TSCD:12; + unsigned long :16; + } BIT; + } TSCDR; +}; + +struct st_tmr0 { + union { + unsigned char BYTE; + struct { + unsigned char CMIEB:1; + unsigned char CMIEA:1; + unsigned char OVIE:1; + unsigned char CCLR:2; + unsigned char :3; + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char OSB:2; + unsigned char OSA:2; + } BIT; + } TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char TMRIS:1; + unsigned char :2; + unsigned char CSS:2; + unsigned char CKS:3; + } BIT; + } TCCR; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TCS:1; + } BIT; + } TCSTR; +}; + +struct st_tmr1 { + union { + unsigned char BYTE; + struct { + unsigned char CMIEB:1; + unsigned char CMIEA:1; + unsigned char OVIE:1; + unsigned char CCLR:2; + unsigned char :3; + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char OSB:2; + unsigned char OSA:2; + } BIT; + } TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char TMRIS:1; + unsigned char :2; + unsigned char CSS:2; + unsigned char CKS:3; + } BIT; + } TCCR; +}; + +struct st_tmr01 { + unsigned short TCORA; + unsigned short TCORB; + unsigned short TCNT; + unsigned short TCCR; +}; + +struct st_tpu { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char CST5:1; + unsigned char CST4:1; + unsigned char CST3:1; + unsigned char CST2:1; + unsigned char CST1:1; + unsigned char CST0:1; + } BIT; + } TSTR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char SYNC5:1; + unsigned char SYNC4:1; + unsigned char SYNC3:1; + unsigned char SYNC2:1; + unsigned char SYNC1:1; + unsigned char SYNC0:1; + } BIT; + } TSYR; +}; + +struct st_tpu0 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk0[7]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char ICSELD:1; + unsigned char ICSELB:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :1; + unsigned char TCFU:1; + unsigned char TCFV:1; + unsigned char TGFD:1; + unsigned char TGFC:1; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; +}; + +struct st_tpu1 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk1[22]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char ICSELD:1; + unsigned char ICSELB:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :1; + unsigned char TCFU:1; + unsigned char TCFV:1; + unsigned char TGFD:1; + unsigned char TGFC:1; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_tpu2 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk0[37]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char ICSELD:1; + unsigned char ICSELB:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :1; + unsigned char TCFU:1; + unsigned char TCFV:1; + unsigned char TGFD:1; + unsigned char TGFC:1; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_tpu3 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk1[52]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char ICSELD:1; + unsigned char ICSELB:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :1; + unsigned char TCFU:1; + unsigned char TCFV:1; + unsigned char TGFD:1; + unsigned char TGFC:1; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; +}; + +struct st_tpu4 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk0[67]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char ICSELD:1; + unsigned char ICSELB:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :1; + unsigned char TCFU:1; + unsigned char TCFV:1; + unsigned char TGFD:1; + unsigned char TGFC:1; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_tpu5 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk1[82]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char ICSELD:1; + unsigned char ICSELB:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :1; + unsigned char TCFU:1; + unsigned char TCFV:1; + unsigned char TGFD:1; + unsigned char TGFC:1; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_usb0 { + union { + unsigned short WORD; +// struct { +// unsigned short :5; +// unsigned short SCKE:1; +// unsigned short :1; +// unsigned short CNEN:1; +// unsigned short :1; +// unsigned short DCFM:1; +// unsigned short DRPD:1; +// unsigned short DPRPU:1; +// unsigned short DMRPU:1; +// unsigned short :2; +// unsigned short USBE:1; +// } BIT; + } SYSCFG; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short OVCMON:2; + unsigned short :7; + unsigned short HTACT:1; + unsigned short :3; + unsigned short IDMON:1; + unsigned short LNST:2; + } BIT; + } SYSSTS0; + char wk1[2]; + union { + unsigned short WORD; +// struct { +// unsigned short :4; +// unsigned short HNPBTOA:1; +// unsigned short EXICEN:1; +// unsigned short VBUSEN:1; +// unsigned short WKUP:1; +// unsigned short RWUPE:1; +// unsigned short USBRST:1; +// unsigned short RESUME:1; +// unsigned short UACT:1; +// unsigned short :1; +// unsigned short RHST:3; +// } BIT; + } DVSTCTR0; + char wk2[10]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } CFIFO; + char wk3[2]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } D0FIFO; + char wk4[2]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } D1FIFO; + char wk5[2]; + union { + unsigned short WORD; +// struct { +// unsigned short RCNT:1; +// unsigned short REW:1; +// unsigned short :3; +// unsigned short MBW:1; +// unsigned short :1; +// unsigned short BIGEND:1; +// unsigned short :2; +// unsigned short ISEL:1; +// unsigned short :1; +// unsigned short CURPIPE:4; +// } BIT; + } CFIFOSEL; + union { + unsigned short WORD; +// struct { +// unsigned short BVAL:1; +// unsigned short BCLR:1; +// unsigned short FRDY:1; +// unsigned short :4; +// unsigned short DTLN:9; +// } BIT; + } CFIFOCTR; + char wk6[4]; + union { + unsigned short WORD; +// struct { +// unsigned short RCNT:1; +// unsigned short REW:1; +// unsigned short DCLRM:1; +// unsigned short DREQE:1; +// unsigned short :1; +// unsigned short MBW:1; +// unsigned short :1; +// unsigned short BIGEND:1; +// unsigned short :4; +// unsigned short CURPIPE:4; +// } BIT; + } D0FIFOSEL; + union { + unsigned short WORD; +// struct { +// unsigned short BVAL:1; +// unsigned short BCLR:1; +// unsigned short FRDY:1; +// unsigned short :4; +// unsigned short DTLN:9; +// } BIT; + } D0FIFOCTR; + union { + unsigned short WORD; +// struct { +// unsigned short RCNT:1; +// unsigned short REW:1; +// unsigned short DCLRM:1; +// unsigned short DREQE:1; +// unsigned short :1; +// unsigned short MBW:1; +// unsigned short :1; +// unsigned short BIGEND:1; +// unsigned short :4; +// unsigned short CURPIPE:4; +// } BIT; + } D1FIFOSEL; + union { + unsigned short WORD; +// struct { +// unsigned short BVAL:1; +// unsigned short BCLR:1; +// unsigned short FRDY:1; +// unsigned short :4; +// unsigned short DTLN:9; +// } BIT; + } D1FIFOCTR; + union { + unsigned short WORD; +// struct { +// unsigned short VBSE:1; +// unsigned short RSME:1; +// unsigned short SOFE:1; +// unsigned short DVSE:1; +// unsigned short CTRE:1; +// unsigned short BEMPE:1; +// unsigned short NRDYE:1; +// unsigned short BRDYE:1; +// unsigned short :8; +// } BIT; + } INTENB0; + union { + unsigned short WORD; +// struct { +// unsigned short OVRCRE:1; +// unsigned short BCHGE:1; +// unsigned short :1; +// unsigned short DTCHE:1; +// unsigned short ATTCHE:1; +// unsigned short :4; +// unsigned short EOFERRE:1; +// unsigned short SIGNE:1; +// unsigned short SACKE:1; +// unsigned short :3; +// unsigned short PDDETINTE0:1; +// } BIT; + } INTENB1; + char wk7[2]; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BRDYE:1; + unsigned short PIPE8BRDYE:1; + unsigned short PIPE7BRDYE:1; + unsigned short PIPE6BRDYE:1; + unsigned short PIPE5BRDYE:1; + unsigned short PIPE4BRDYE:1; + unsigned short PIPE3BRDYE:1; + unsigned short PIPE2BRDYE:1; + unsigned short PIPE1BRDYE:1; + unsigned short PIPE0BRDYE:1; + } BIT; + } BRDYENB; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9NRDYE:1; + unsigned short PIPE8NRDYE:1; + unsigned short PIPE7NRDYE:1; + unsigned short PIPE6NRDYE:1; + unsigned short PIPE5NRDYE:1; + unsigned short PIPE4NRDYE:1; + unsigned short PIPE3NRDYE:1; + unsigned short PIPE2NRDYE:1; + unsigned short PIPE1NRDYE:1; + unsigned short PIPE0NRDYE:1; + } BIT; + } NRDYENB; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BEMPE:1; + unsigned short PIPE8BEMPE:1; + unsigned short PIPE7BEMPE:1; + unsigned short PIPE6BEMPE:1; + unsigned short PIPE5BEMPE:1; + unsigned short PIPE4BEMPE:1; + unsigned short PIPE3BEMPE:1; + unsigned short PIPE2BEMPE:1; + unsigned short PIPE1BEMPE:1; + unsigned short PIPE0BEMPE:1; + } BIT; + } BEMPENB; + union { + unsigned short WORD; +// struct { +// unsigned short :7; +// unsigned short TRNENSEL:1; +// unsigned short :1; +// unsigned short BRDYM:1; +// unsigned short :1; +// unsigned short EDGESTS:1; +// unsigned short :4; +// } BIT; + } SOFCFG; + char wk8[2]; + union { + unsigned short WORD; +// struct { +// unsigned short VBINT:1; +// unsigned short RESM:1; +// unsigned short SOFR:1; +// unsigned short DVST:1; +// unsigned short CTRT:1; +// unsigned short BEMP:1; +// unsigned short NRDY:1; +// unsigned short BRDY:1; +// unsigned short VBSTS:1; +// unsigned short DVSQ:3; +// unsigned short VALID:1; +// unsigned short CTSQ:3; +// } BIT; + } INTSTS0; + union { + unsigned short WORD; +// struct { +// unsigned short OVRCR:1; +// unsigned short BCHG:1; +// unsigned short :1; +// unsigned short DTCH:1; +// unsigned short ATTCH:1; +// unsigned short :4; +// unsigned short EOFERR:1; +// unsigned short SIGN:1; +// unsigned short SACK:1; +// unsigned short :3; +// unsigned short PDDETINT0:1; +// } BIT; + } INTSTS1; + char wk9[2]; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short PIPE9BRDY:1; +// unsigned short PIPE8BRDY:1; +// unsigned short PIPE7BRDY:1; +// unsigned short PIPE6BRDY:1; +// unsigned short PIPE5BRDY:1; +// unsigned short PIPE4BRDY:1; +// unsigned short PIPE3BRDY:1; +// unsigned short PIPE2BRDY:1; +// unsigned short PIPE1BRDY:1; +// unsigned short PIPE0BRDY:1; +// } BIT; + } BRDYSTS; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short PIPE9NRDY:1; +// unsigned short PIPE8NRDY:1; +// unsigned short PIPE7NRDY:1; +// unsigned short PIPE6NRDY:1; +// unsigned short PIPE5NRDY:1; +// unsigned short PIPE4NRDY:1; +// unsigned short PIPE3NRDY:1; +// unsigned short PIPE2NRDY:1; +// unsigned short PIPE1NRDY:1; +// unsigned short PIPE0NRDY:1; +// } BIT; + } NRDYSTS; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short PIPE9BEMP:1; +// unsigned short PIPE8BEMP:1; +// unsigned short PIPE7BEMP:1; +// unsigned short PIPE6BEMP:1; +// unsigned short PIPE5BEMP:1; +// unsigned short PIPE4BEMP:1; +// unsigned short PIPE3BEMP:1; +// unsigned short PIPE2BEMP:1; +// unsigned short PIPE1BEMP:1; +// unsigned short PIPE0BEMP:1; +// } BIT; + } BEMPSTS; + union { + unsigned short WORD; +// struct { +// unsigned short OVRN:1; +// unsigned short CRCE:1; +// unsigned short :3; +// unsigned short FRNM:11; +// } BIT; + } FRMNUM; + char wk10[6]; + union { + unsigned short WORD; + struct { + unsigned short BREQUEST:8; + unsigned short BMREQUESTTYPE:8; + } BIT; + } USBREQ; + unsigned short USBVAL; + unsigned short USBINDX; + unsigned short USBLENG; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short SHTNAK:1; +// unsigned short :2; +// unsigned short DIR:1; +// unsigned short :4; +// } BIT; + } DCPCFG; + union { + unsigned short WORD; +// struct { +// unsigned short DEVSEL:4; +// unsigned short :5; +// unsigned short MXPS:7; +// } BIT; + } DCPMAXP; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short SUREQ:1; +// unsigned short :2; +// unsigned short SUREQCLR:1; +// unsigned short :2; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :2; +// unsigned short CCPL:1; +// unsigned short PID:2; +// } BIT; + } DCPCTR; + char wk11[2]; + union { + unsigned short WORD; +// struct { +// unsigned short :12; +// unsigned short PIPESEL:4; +// } BIT; + } PIPESEL; + char wk12[2]; + union { + unsigned short WORD; +// struct { +// unsigned short TYPE:2; +// unsigned short :3; +// unsigned short BFRE:1; +// unsigned short DBLB:1; +// unsigned short :1; +// unsigned short SHTNAK:1; +// unsigned short :2; +// unsigned short DIR:1; +// unsigned short EPNUM:4; +// } BIT; + } PIPECFG; + char wk13[2]; + union { + unsigned short WORD; +// struct { +// unsigned short DEVSEL:4; +// unsigned short :3; +// unsigned short MXPS:9; +// } BIT; + } PIPEMAXP; + union { + unsigned short WORD; +// struct { +// unsigned short :3; +// unsigned short IFIS:1; +// unsigned short :9; +// unsigned short IITV:3; +// } BIT; + } PIPEPERI; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE1CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE2CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE3CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE4CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE5CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short :5; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE6CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short :5; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE7CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short :5; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE8CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short :5; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE9CTR; + char wk14[14]; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// unsigned short :8; +// } BIT; + } PIPE1TRE; + unsigned short PIPE1TRN; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// unsigned short :8; +// } BIT; + } PIPE2TRE; + unsigned short PIPE2TRN; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// unsigned short :8; +// } BIT; + } PIPE3TRE; + unsigned short PIPE3TRN; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// unsigned short :8; +// } BIT; + } PIPE4TRE; + unsigned short PIPE4TRN; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// unsigned short :8; +// } BIT; + } PIPE5TRE; + unsigned short PIPE5TRN; + char wk15[12]; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PDDETSTS0:1; + unsigned short CHGDETSTS0:1; + unsigned short BATCHGE0:1; + unsigned short :1; + unsigned short VDMSRCE0:1; + unsigned short IDPSINKE0:1; + unsigned short VDPSRCE0:1; + unsigned short IDMSINKE0:1; + unsigned short IDPSRCE0:1; + unsigned short RPDME0:1; + } BIT; + } USBBCCTRL0; + char wk16[26]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short VDCEN:1; + unsigned short :6; + unsigned short VDDUSBE:1; + } BIT; + } USBMC; + char wk17[2]; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// unsigned short :6; +// } BIT; + } DEVADD0; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// unsigned short :6; +// } BIT; + } DEVADD1; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// unsigned short :6; +// } BIT; + } DEVADD2; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// unsigned short :6; +// } BIT; + } DEVADD3; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// unsigned short :6; +// } BIT; + } DEVADD4; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// unsigned short :6; +// } BIT; + } DEVADD5; +}; + +struct st_wdt { + unsigned char WDTRR; + char wk0[1]; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short RPSS:2; + unsigned short :2; + unsigned short RPES:2; + unsigned short CKS:4; + unsigned short :2; + unsigned short TOPS:2; + } BIT; + } WDTCR; + union { + unsigned short WORD; + struct { + unsigned short REFEF:1; + unsigned short UNDFF:1; + unsigned short CNTVAL:14; + } BIT; + } WDTSR; + union { + unsigned char BYTE; + struct { + unsigned char RSTIRQS:1; + unsigned char :7; + } BIT; + } WDTRCR; +}; + +enum enum_ir { +IR_BSC_BUSERR=16,IR_FCU_FRDYI=23, +IR_ICU_SWINT=27, +IR_CMT0_CMI0,IR_CMT1_CMI1, +IR_CMT2_CMI2,IR_CMT3_CMI3, +IR_CAC_FERRF,IR_CAC_MENDF,IR_CAC_OVFF, +IR_USB0_D0FIFO0=36,IR_USB0_D1FIFO0,IR_USB0_USBI0, +IR_SDHI_SBFAI=40,IR_SDHI_CDETI,IR_SDHI_CACI,IR_SDHI_SDACI, +IR_RSPI0_SPEI0,IR_RSPI0_SPRI0,IR_RSPI0_SPTI0,IR_RSPI0_SPII0, +IR_RSCAN_COMFRXINT=52,IR_RSCAN_RXFINT,IR_RSCAN_TXINT,IR_RSCAN_CHERRINT,IR_RSCAN_GLERRINT, +IR_DOC_DOPCF, +IR_CMPB_CMPB0,IR_CMPB_CMPB1, +IR_CTSU_CTSUWR,IR_CTSU_CTSURD,IR_CTSU_CTSUFN, +IR_RTC_CUP, +IR_ICU_IRQ0,IR_ICU_IRQ1,IR_ICU_IRQ2,IR_ICU_IRQ3,IR_ICU_IRQ4,IR_ICU_IRQ5,IR_ICU_IRQ6,IR_ICU_IRQ7, +IR_ELC_ELSR8I=80, +IR_LVD_LVD1=88,IR_LVD_LVD2, +IR_CMPA_CMPA1=88,IR_CMPA_CMPA2, +IR_USB0_USBR0, +IR_VBATT_VBTLVDI, +IR_RTC_ALM,IR_RTC_PRD, +IR_S12AD_S12ADI0=102,IR_S12AD_GBADI, +IR_CMPB1_CMPB2,IR_CMPB1_CMPB3, +IR_ELC_ELSR18I,IR_ELC_ELSR19I, +IR_SSI0_SSIF0,IR_SSI0_SSIRXI0,IR_SSI0_SSITXI0, +IR_SECURITY_RD,IR_SECURITY_WR,IR_SECURITY_ERR, +IR_MTU0_TGIA0,IR_MTU0_TGIB0,IR_MTU0_TGIC0,IR_MTU0_TGID0,IR_MTU0_TCIV0,IR_MTU0_TGIE0,IR_MTU0_TGIF0, +IR_MTU1_TGIA1,IR_MTU1_TGIB1,IR_MTU1_TCIV1,IR_MTU1_TCIU1, +IR_MTU2_TGIA2,IR_MTU2_TGIB2,IR_MTU2_TCIV2,IR_MTU2_TCIU2, +IR_MTU3_TGIA3,IR_MTU3_TGIB3,IR_MTU3_TGIC3,IR_MTU3_TGID3,IR_MTU3_TCIV3, +IR_MTU4_TGIA4,IR_MTU4_TGIB4,IR_MTU4_TGIC4,IR_MTU4_TGID4,IR_MTU4_TCIV4, +IR_MTU5_TGIU5,IR_MTU5_TGIV5,IR_MTU5_TGIW5, +IR_TPU0_TGI0A,IR_TPU0_TGI0B,IR_TPU0_TGI0C,IR_TPU0_TGI0D,IR_TPU0_TCI0V, +IR_TPU1_TGI1A,IR_TPU1_TGI1B,IR_TPU1_TCI1V,IR_TPU1_TCI1U, +IR_TPU2_TGI2A,IR_TPU2_TGI2B,IR_TPU2_TCI2V,IR_TPU2_TCI2U, +IR_TPU3_TGI3A,IR_TPU3_TGI3B,IR_TPU3_TGI3C,IR_TPU3_TGI3D,IR_TPU3_TCI3V, +IR_TPU4_TGI4A,IR_TPU4_TGI4B,IR_TPU4_TCI4V,IR_TPU4_TCI4U, +IR_TPU5_TGI5A,IR_TPU5_TGI5B,IR_TPU5_TCI5V,IR_TPU5_TCI5U, +IR_POE_OEI1=170,IR_POE_OEI2, +IR_TMR0_CMIA0=174,IR_TMR0_CMIB0,IR_TMR0_OVI0, +IR_TMR1_CMIA1,IR_TMR1_CMIB1,IR_TMR1_OVI1, +IR_TMR2_CMIA2,IR_TMR2_CMIB2,IR_TMR2_OVI2, +IR_TMR3_CMIA3,IR_TMR3_CMIB3,IR_TMR3_OVI3, +IR_DMAC_DMAC0I=198,IR_DMAC_DMAC1I,IR_DMAC_DMAC2I,IR_DMAC_DMAC3I, +IR_SCI0_ERI0=214,IR_SCI0_RXI0,IR_SCI0_TXI0,IR_SCI0_TEI0, +IR_SCI1_ERI1,IR_SCI1_RXI1,IR_SCI1_TXI1,IR_SCI1_TEI1, +IR_SCI5_ERI5,IR_SCI5_RXI5,IR_SCI5_TXI5,IR_SCI5_TEI5, +IR_SCI6_ERI6,IR_SCI6_RXI6,IR_SCI6_TXI6,IR_SCI6_TEI6, +IR_SCI8_ERI8,IR_SCI8_RXI8,IR_SCI8_TXI8,IR_SCI8_TEI8, +IR_SCI9_ERI9,IR_SCI9_RXI9,IR_SCI9_TXI9,IR_SCI9_TEI9, +IR_SCI12_ERI12,IR_SCI12_RXI12,IR_SCI12_TXI12,IR_SCI12_TEI12,IR_SCI12_SCIX0,IR_SCI12_SCIX1,IR_SCI12_SCIX2,IR_SCI12_SCIX3, +IR_RIIC0_EEI0,IR_RIIC0_RXI0,IR_RIIC0_TXI0,IR_RIIC0_TEI0 +}; + +enum enum_dtce { +DTCE_ICU_SWINT=27, +DTCE_CMT0_CMI0,DTCE_CMT1_CMI1, +DTCE_CMT2_CMI2,DTCE_CMT3_CMI3, +DTCE_USB0_D0FIFO0=36,DTCE_USB0_D1FIFO0, +DTCE_SDHI_SBFAI=40, +DTCE_RSPI0_SPRI0=45,DTCE_RSPI0_SPTI0, +DTCE_RSCAN_COMFRXINT=52, +DTCE_CMPB_CMPB0=58,DTCE_CMPB_CMPB1, +DTCE_CTSU_CTSUWR,DTCE_CTSU_CTSURD, +DTCE_ICU_IRQ0=64,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7, +DTCE_S12AD_S12ADI0=102,DTCE_S12AD_GBADI, +DTCE_CMPB1_CMPB2,DTCE_CMPB1_CMPB3, +DTCE_ELC_ELSR18I,DTCE_ELC_ELSR19I, +DTCE_SSI0_SSIRXI0=109,DTCE_SSI0_SSITXI0, +DTCE_SECURITY_RD,DTCE_SECURITY_WR, +DTCE_MTU0_TGIA0=114,DTCE_MTU0_TGIB0,DTCE_MTU0_TGIC0,DTCE_MTU0_TGID0, +DTCE_MTU1_TGIA1=121,DTCE_MTU1_TGIB1, +DTCE_MTU2_TGIA2=125,DTCE_MTU2_TGIB2, +DTCE_MTU3_TGIA3=129,DTCE_MTU3_TGIB3,DTCE_MTU3_TGIC3,DTCE_MTU3_TGID3, +DTCE_MTU4_TGIA4=134,DTCE_MTU4_TGIB4,DTCE_MTU4_TGIC4,DTCE_MTU4_TGID4,DTCE_MTU4_TCIV4, +DTCE_MTU5_TGIU5,DTCE_MTU5_TGIV5,DTCE_MTU5_TGIW5, +DTCE_TPU0_TGI0A,DTCE_TPU0_TGI0B,DTCE_TPU0_TGI0C,DTCE_TPU0_TGI0D, +DTCE_TPU1_TGI1A=147,DTCE_TPU1_TGI1B, +DTCE_TPU2_TGI2A=151,DTCE_TPU2_TGI2B, +DTCE_TPU3_TGI3A=155,DTCE_TPU3_TGI3B,DTCE_TPU3_TGI3C,DTCE_TPU3_TGI3D, +DTCE_TPU4_TGI4A=160,DTCE_TPU4_TGI4B, +DTCE_TPU5_TGI5A=164,DTCE_TPU5_TGI5B, +DTCE_TMR0_CMIA0=174,DTCE_TMR0_CMIB0, +DTCE_TMR1_CMIA1=177,DTCE_TMR1_CMIB1, +DTCE_TMR2_CMIA2=180,DTCE_TMR2_CMIB2, +DTCE_TMR3_CMIA3=183,DTCE_TMR3_CMIB3, +DTCE_DMAC_DMAC0I=198,DTCE_DMAC_DMAC1I,DTCE_DMAC_DMAC2I,DTCE_DMAC_DMAC3I, +DTCE_SCI0_RXI0=215,DTCE_SCI0_TXI0, +DTCE_SCI1_RXI1=219,DTCE_SCI1_TXI1, +DTCE_SCI5_RXI5=223,DTCE_SCI5_TXI5, +DTCE_SCI6_RXI6=227,DTCE_SCI6_TXI6, +DTCE_SCI8_RXI8=231,DTCE_SCI8_TXI8, +DTCE_SCI9_RXI9=235,DTCE_SCI9_TXI9, +DTCE_SCI12_RXI12=239,DTCE_SCI12_TXI12, +DTCE_RIIC0_RXI0=247,DTCE_RIIC0_TXI0 +}; + +enum enum_ier { +IER_BSC_BUSERR=0x02, +IER_FCU_FRDYI=0x02, +IER_ICU_SWINT=0x03, +IER_CMT0_CMI0=0x03,IER_CMT1_CMI1=0x03, +IER_CMT2_CMI2=0x03,IER_CMT3_CMI3=0x03, +IER_CAC_FERRF=0x04,IER_CAC_MENDF=0x04,IER_CAC_OVFF=0x04, +IER_USB0_D0FIFO0=0x04,IER_USB0_D1FIFO0=0x04,IER_USB0_USBI0=0x04, +IER_SDHI_SBFAI=0x05,IER_SDHI_CDETI=0x05,IER_SDHI_CACI=0x05,IER_SDHI_SDACI=0x05, +IER_RSPI0_SPEI0=0x05,IER_RSPI0_SPRI0=0x05,IER_RSPI0_SPTI0=0x05,IER_RSPI0_SPII0=0x05, +IER_RSCAN_COMFRXINT=0x06,IER_RSCAN_RXFINT=0x06,IER_RSCAN_TXINT=0x06,IER_RSCAN_CHERRINT=0x06,IER_RSCAN_GLERRINT=0x07, +IER_DOC_DOPCF=0x07, +IER_CMPB_CMPB0=0x07,IER_CMPB_CMPB1=0x07, +IER_CTSU_CTSUWR=0x07,IER_CTSU_CTSURD=0x07,IER_CTSU_CTSUFN=0x07, +IER_RTC_CUP=0x07, +IER_ICU_IRQ0=0x08,IER_ICU_IRQ1=0x08,IER_ICU_IRQ2=0x08,IER_ICU_IRQ3=0x08,IER_ICU_IRQ4=0x08,IER_ICU_IRQ5=0x08,IER_ICU_IRQ6=0x08,IER_ICU_IRQ7=0x08, +IER_ELC_ELSR8I=0x0A, +IER_LVD_LVD1=0x0B,IER_LVD_LVD2=0x0B, +IER_CMPA_CMPA1=0x0B,IER_CMPA_CMPA2=0x0B, +IER_USB0_USBR0=0x0B, +IER_VBATT_VBTLVDI=0x0B, +IER_RTC_ALM=0x0B,IER_RTC_PRD=0x0B, +IER_S12AD_S12ADI0=0x0C,IER_S12AD_GBADI=0x0C, +IER_CMPB1_CMPB2=0x0D,IER_CMPB1_CMPB3=0x0D, +IER_ELC_ELSR18I=0x0D,IER_ELC_ELSR19I=0x0D, +IER_SSI0_SSIF0=0x0D,IER_SSI0_SSIRXI0=0x0D,IER_SSI0_SSITXI0=0x0D, +IER_SECURITY_RD=0x0D,IER_SECURITY_WR=0x0E,IER_SECURITY_ERR=0x0E, +IER_MTU0_TGIA0=0x0E,IER_MTU0_TGIB0=0x0E,IER_MTU0_TGIC0=0x0E,IER_MTU0_TGID0=0x0E,IER_MTU0_TCIV0=0x0E,IER_MTU0_TGIE0=0x0E,IER_MTU0_TGIF0=0x0F, +IER_MTU1_TGIA1=0x0F,IER_MTU1_TGIB1=0x0F,IER_MTU1_TCIV1=0x0F,IER_MTU1_TCIU1=0x0F, +IER_MTU2_TGIA2=0x0F,IER_MTU2_TGIB2=0x0F,IER_MTU2_TCIV2=0x0F,IER_MTU2_TCIU2=0x10, +IER_MTU3_TGIA3=0x10,IER_MTU3_TGIB3=0x10,IER_MTU3_TGIC3=0x10,IER_MTU3_TGID3=0x10,IER_MTU3_TCIV3=0x10, +IER_MTU4_TGIA4=0x10,IER_MTU4_TGIB4=0x10,IER_MTU4_TGIC4=0x11,IER_MTU4_TGID4=0x11,IER_MTU4_TCIV4=0x11, +IER_MTU5_TGIU5=0x11,IER_MTU5_TGIV5=0x11,IER_MTU5_TGIW5=0x11, +IER_TPU0_TGI0A=0x11,IER_TPU0_TGI0B=0x11,IER_TPU0_TGI0C=0x12,IER_TPU0_TGI0D=0x12,IER_TPU0_TCI0V=0x12, +IER_TPU1_TGI1A=0x12,IER_TPU1_TGI1B=0x12,IER_TPU1_TCI1V=0x12,IER_TPU1_TCI1U=0x12, +IER_TPU2_TGI2A=0x12,IER_TPU2_TGI2B=0x13,IER_TPU2_TCI2V=0x13,IER_TPU2_TCI2U=0x13, +IER_TPU3_TGI3A=0x13,IER_TPU3_TGI3B=0x13,IER_TPU3_TGI3C=0x13,IER_TPU3_TGI3D=0x13,IER_TPU3_TCI3V=0x13, +IER_TPU4_TGI4A=0x14,IER_TPU4_TGI4B=0x14,IER_TPU4_TCI4V=0x14,IER_TPU4_TCI4U=0x14, +IER_TPU5_TGI5A=0x14,IER_TPU5_TGI5B=0x14,IER_TPU5_TCI5V=0x14,IER_TPU5_TCI5U=0x14, +IER_POE_OEI1=0x15,IER_POE_OEI2=0x15, +IER_TMR0_CMIA0=0x15,IER_TMR0_CMIB0=0x15,IER_TMR0_OVI0=0x16, +IER_TMR1_CMIA1=0x16,IER_TMR1_CMIB1=0x16,IER_TMR1_OVI1=0x16, +IER_TMR2_CMIA2=0x16,IER_TMR2_CMIB2=0x16,IER_TMR2_OVI2=0x16, +IER_TMR3_CMIA3=0x16,IER_TMR3_CMIB3=0x17,IER_TMR3_OVI3=0x17, +IER_DMAC_DMAC0I=0x18,IER_DMAC_DMAC1I=0x18,IER_DMAC_DMAC2I=0x19,IER_DMAC_DMAC3I=0x19, +IER_SCI0_ERI0=0x1A,IER_SCI0_RXI0=0x1A,IER_SCI0_TXI0=0x1B,IER_SCI0_TEI0=0x1B, +IER_SCI1_ERI1=0x1B,IER_SCI1_RXI1=0x1B,IER_SCI1_TXI1=0x1B,IER_SCI1_TEI1=0x1B, +IER_SCI5_ERI5=0x1B,IER_SCI5_RXI5=0x1B,IER_SCI5_TXI5=0x1C,IER_SCI5_TEI5=0x1C, +IER_SCI6_ERI6=0x1C,IER_SCI6_RXI6=0x1C,IER_SCI6_TXI6=0x1C,IER_SCI6_TEI6=0x1C, +IER_SCI8_ERI8=0x1C,IER_SCI8_RXI8=0x1C,IER_SCI8_TXI8=0x1D,IER_SCI8_TEI8=0x1D, +IER_SCI9_ERI9=0x1D,IER_SCI9_RXI9=0x1D,IER_SCI9_TXI9=0x1D,IER_SCI9_TEI9=0x1D, +IER_SCI12_ERI12=0x1D,IER_SCI12_RXI12=0x1D,IER_SCI12_TXI12=0x1E,IER_SCI12_TEI12=0x1E,IER_SCI12_SCIX0=0x1E,IER_SCI12_SCIX1=0x1E,IER_SCI12_SCIX2=0x1E,IER_SCI12_SCIX3=0x1E, +IER_RIIC0_EEI0=0x1E,IER_RIIC0_RXI0=0x1E,IER_RIIC0_TXI0=0x1F,IER_RIIC0_TEI0=0x1F +}; + +enum enum_ipr { +IPR_BSC_BUSERR=0, +IPR_FCU_FRDYI=2, +IPR_ICU_SWINT=3, +IPR_CMT0_CMI0=4,IPR_CMT1_CMI1=5, +IPR_CMT2_CMI2=6,IPR_CMT3_CMI3=7, +IPR_CAC_FERRF=32,IPR_CAC_MENDF=33,IPR_CAC_OVFF=34, +IPR_USB0_D0FIFO0=36,IPR_USB0_D1FIFO0=37,IPR_USB0_USBI0=38, +IPR_SDHI_SBFAI=40,IPR_SDHI_CDETI=41,IPR_SDHI_CACI=42,IPR_SDHI_SDACI=43, +IPR_RSPI0_SPEI0=44,IPR_RSPI0_SPRI0=44,IPR_RSPI0_SPTI0=44,IPR_RSPI0_SPII0=44, +IPR_RSCAN_COMFRXINT=52,IPR_RSCAN_RXFINT=53,IPR_RSCAN_TXINT=54,IPR_RSCAN_CHERRINT=55,IPR_RSCAN_GLERRINT=56, +IPR_DOC_DOPCF=57, +IPR_CMPB_CMPB0=58,IPR_CMPB_CMPB1=59, +IPR_CTSU_CTSUWR=60,IPR_CTSU_CTSURD=60,IPR_CTSU_CTSUFN=60, +IPR_RTC_CUP=63, +IPR_ICU_IRQ0=64,IPR_ICU_IRQ1=65,IPR_ICU_IRQ2=66,IPR_ICU_IRQ3=67,IPR_ICU_IRQ4=68,IPR_ICU_IRQ5=69,IPR_ICU_IRQ6=70,IPR_ICU_IRQ7=71, +IPR_ELC_ELSR8I=80, +IPR_LVD_LVD1=88,IPR_LVD_LVD2=89, +IPR_CMPA_CMPA1=88,IPR_CMPA_CMPA2=89, +IPR_USB0_USBR0=90, +IPR_VBATT_VBTLVDI=91, +IPR_RTC_ALM=92,IPR_RTC_PRD=93, +IPR_S12AD_S12ADI0=102,IPR_S12AD_GBADI=103, +IPR_CMPB1_CMPB2=104,IPR_CMPB1_CMPB3=105, +IPR_ELC_ELSR18I=106,IPR_ELC_ELSR19I=107, +IPR_SSI0_SSIF0=108,IPR_SSI0_SSIRXI0=108,IPR_SSI0_SSITXI0=108, +IPR_SECURITY_RD=111,IPR_SECURITY_WR=111,IPR_SECURITY_ERR=113, +IPR_MTU0_TGIA0=114,IPR_MTU0_TGIB0=114,IPR_MTU0_TGIC0=114,IPR_MTU0_TGID0=114,IPR_MTU0_TCIV0=118,IPR_MTU0_TGIE0=118,IPR_MTU0_TGIF0=118, +IPR_MTU1_TGIA1=121,IPR_MTU1_TGIB1=121,IPR_MTU1_TCIV1=123,IPR_MTU1_TCIU1=123, +IPR_MTU2_TGIA2=125,IPR_MTU2_TGIB2=125,IPR_MTU2_TCIV2=127,IPR_MTU2_TCIU2=127, +IPR_MTU3_TGIA3=129,IPR_MTU3_TGIB3=129,IPR_MTU3_TGIC3=129,IPR_MTU3_TGID3=129,IPR_MTU3_TCIV3=133, +IPR_MTU4_TGIA4=134,IPR_MTU4_TGIB4=134,IPR_MTU4_TGIC4=134,IPR_MTU4_TGID4=134,IPR_MTU4_TCIV4=138, +IPR_MTU5_TGIU5=139,IPR_MTU5_TGIV5=139,IPR_MTU5_TGIW5=139, +IPR_TPU0_TGI0A=142,IPR_TPU0_TGI0B=142,IPR_TPU0_TGI0C=142,IPR_TPU0_TGI0D=142,IPR_TPU0_TCI0V=146, +IPR_TPU1_TGI1A=147,IPR_TPU1_TGI1B=147,IPR_TPU1_TCI1V=149,IPR_TPU1_TCI1U=149, +IPR_TPU2_TGI2A=151,IPR_TPU2_TGI2B=151,IPR_TPU2_TCI2V=153,IPR_TPU2_TCI2U=153, +IPR_TPU3_TGI3A=155,IPR_TPU3_TGI3B=155,IPR_TPU3_TGI3C=155,IPR_TPU3_TGI3D=155,IPR_TPU3_TCI3V=159, +IPR_TPU4_TGI4A=160,IPR_TPU4_TGI4B=160,IPR_TPU4_TCI4V=162,IPR_TPU4_TCI4U=162, +IPR_TPU5_TGI5A=164,IPR_TPU5_TGI5B=164,IPR_TPU5_TCI5V=166,IPR_TPU5_TCI5U=166, +IPR_POE_OEI1=170,IPR_POE_OEI2=171, +IPR_TMR0_CMIA0=174,IPR_TMR0_CMIB0=174,IPR_TMR0_OVI0=174, +IPR_TMR1_CMIA1=177,IPR_TMR1_CMIB1=177,IPR_TMR1_OVI1=177, +IPR_TMR2_CMIA2=180,IPR_TMR2_CMIB2=180,IPR_TMR2_OVI2=180, +IPR_TMR3_CMIA3=183,IPR_TMR3_CMIB3=183,IPR_TMR3_OVI3=183, +IPR_DMAC_DMAC0I=198,IPR_DMAC_DMAC1I=199,IPR_DMAC_DMAC2I=200,IPR_DMAC_DMAC3I=201, +IPR_SCI0_ERI0=214,IPR_SCI0_RXI0=214,IPR_SCI0_TXI0=214,IPR_SCI0_TEI0=214, +IPR_SCI1_ERI1=218,IPR_SCI1_RXI1=218,IPR_SCI1_TXI1=218,IPR_SCI1_TEI1=218, +IPR_SCI5_ERI5=222,IPR_SCI5_RXI5=222,IPR_SCI5_TXI5=222,IPR_SCI5_TEI5=222, +IPR_SCI6_ERI6=226,IPR_SCI6_RXI6=226,IPR_SCI6_TXI6=226,IPR_SCI6_TEI6=226, +IPR_SCI8_ERI8=230,IPR_SCI8_RXI8=230,IPR_SCI8_TXI8=230,IPR_SCI8_TEI8=230, +IPR_SCI9_ERI9=234,IPR_SCI9_RXI9=234,IPR_SCI9_TXI9=234,IPR_SCI9_TEI9=234, +IPR_SCI12_ERI12=238,IPR_SCI12_RXI12=238,IPR_SCI12_TXI12=238,IPR_SCI12_TEI12=238,IPR_SCI12_SCIX0=242,IPR_SCI12_SCIX1=243,IPR_SCI12_SCIX2=244,IPR_SCI12_SCIX3=245, +IPR_RIIC0_EEI0=246,IPR_RIIC0_RXI0=247,IPR_RIIC0_TXI0=248,IPR_RIIC0_TEI0=249, +IPR_BSC_=0, +IPR_FCU_=2, +IPR_RSPI0_=44, +IPR_DOC_=57, +IPR_VBATT_=91, +IPR_MTU1_TGI=121, +IPR_MTU1_TCI=123, +IPR_MTU2_TGI=125, +IPR_MTU2_TCI=127, +IPR_MTU3_TGI=129, +IPR_MTU4_TGI=134, +IPR_MTU5_=139, +IPR_MTU5_TGI=139, +IPR_TPU0_TGI=142, +IPR_TPU1_TGI=147, +IPR_TPU1_TCI=149, +IPR_TPU2_TGI=151, +IPR_TPU2_TCI=153, +IPR_TPU3_TGI=155, +IPR_TPU4_TGI=160, +IPR_TPU4_TCI=162, +IPR_TPU5_TGI=164, +IPR_TPU5_TCI=166, +IPR_TMR0_=174, +IPR_TMR1_=177, +IPR_TMR2_=180, +IPR_TMR3_=183, +IPR_SCI0_=214, +IPR_SCI1_=218, +IPR_SCI5_=222, +IPR_SCI6_=226, +IPR_SCI8_=230, +IPR_SCI9_=234 +}; + +#define IEN_BSC_BUSERR IEN0 +#define IEN_FCU_FRDYI IEN7 +#define IEN_ICU_SWINT IEN3 +#define IEN_CMT0_CMI0 IEN4 +#define IEN_CMT1_CMI1 IEN5 +#define IEN_CMT2_CMI2 IEN6 +#define IEN_CMT3_CMI3 IEN7 +#define IEN_CAC_FERRF IEN0 +#define IEN_CAC_MENDF IEN1 +#define IEN_CAC_OVFF IEN2 +#define IEN_USB0_D0FIFO0 IEN4 +#define IEN_USB0_D1FIFO0 IEN5 +#define IEN_USB0_USBI0 IEN6 +#define IEN_SDHI_SBFAI IEN0 +#define IEN_SDHI_CDETI IEN1 +#define IEN_SDHI_CACI IEN2 +#define IEN_SDHI_SDACI IEN3 +#define IEN_RSPI0_SPEI0 IEN4 +#define IEN_RSPI0_SPRI0 IEN5 +#define IEN_RSPI0_SPTI0 IEN6 +#define IEN_RSPI0_SPII0 IEN7 +#define IEN_RSCAN_COMFRXINT IEN4 +#define IEN_RSCAN_RXFINT IEN5 +#define IEN_RSCAN_TXINT IEN6 +#define IEN_RSCAN_CHERRINT IEN7 +#define IEN_RSCAN_GLERRINT IEN0 +#define IEN_DOC_DOPCF IEN1 +#define IEN_CMPB_CMPB0 IEN2 +#define IEN_CMPB_CMPB1 IEN3 +#define IEN_CTSU_CTSUWR IEN4 +#define IEN_CTSU_CTSURD IEN5 +#define IEN_CTSU_CTSUFN IEN6 +#define IEN_RTC_CUP IEN7 +#define IEN_ICU_IRQ0 IEN0 +#define IEN_ICU_IRQ1 IEN1 +#define IEN_ICU_IRQ2 IEN2 +#define IEN_ICU_IRQ3 IEN3 +#define IEN_ICU_IRQ4 IEN4 +#define IEN_ICU_IRQ5 IEN5 +#define IEN_ICU_IRQ6 IEN6 +#define IEN_ICU_IRQ7 IEN7 +#define IEN_ELC_ELSR8I IEN0 +#define IEN_LVD_LVD1 IEN0 +#define IEN_LVD_LVD2 IEN1 +#define IEN_CMPA_CMPA1 IEN0 +#define IEN_CMPA_CMPA2 IEN1 +#define IEN_USB0_USBR0 IEN2 +#define IEN_VBATT_VBTLVDI IEN3 +#define IEN_RTC_ALM IEN4 +#define IEN_RTC_PRD IEN5 +#define IEN_S12AD_S12ADI0 IEN6 +#define IEN_S12AD_GBADI IEN7 +#define IEN_CMPB1_CMPB2 IEN0 +#define IEN_CMPB1_CMPB3 IEN1 +#define IEN_ELC_ELSR18I IEN2 +#define IEN_ELC_ELSR19I IEN3 +#define IEN_SSI0_SSIF0 IEN4 +#define IEN_SSI0_SSIRXI0 IEN5 +#define IEN_SSI0_SSITXI0 IEN6 +#define IEN_SECURITY_RD IEN7 +#define IEN_SECURITY_WR IEN0 +#define IEN_SECURITY_ERR IEN1 +#define IEN_MTU0_TGIA0 IEN2 +#define IEN_MTU0_TGIB0 IEN3 +#define IEN_MTU0_TGIC0 IEN4 +#define IEN_MTU0_TGID0 IEN5 +#define IEN_MTU0_TCIV0 IEN6 +#define IEN_MTU0_TGIE0 IEN7 +#define IEN_MTU0_TGIF0 IEN0 +#define IEN_MTU1_TGIA1 IEN1 +#define IEN_MTU1_TGIB1 IEN2 +#define IEN_MTU1_TCIV1 IEN3 +#define IEN_MTU1_TCIU1 IEN4 +#define IEN_MTU2_TGIA2 IEN5 +#define IEN_MTU2_TGIB2 IEN6 +#define IEN_MTU2_TCIV2 IEN7 +#define IEN_MTU2_TCIU2 IEN0 +#define IEN_MTU3_TGIA3 IEN1 +#define IEN_MTU3_TGIB3 IEN2 +#define IEN_MTU3_TGIC3 IEN3 +#define IEN_MTU3_TGID3 IEN4 +#define IEN_MTU3_TCIV3 IEN5 +#define IEN_MTU4_TGIA4 IEN6 +#define IEN_MTU4_TGIB4 IEN7 +#define IEN_MTU4_TGIC4 IEN0 +#define IEN_MTU4_TGID4 IEN1 +#define IEN_MTU4_TCIV4 IEN2 +#define IEN_MTU5_TGIU5 IEN3 +#define IEN_MTU5_TGIV5 IEN4 +#define IEN_MTU5_TGIW5 IEN5 +#define IEN_TPU0_TGI0A IEN6 +#define IEN_TPU0_TGI0B IEN7 +#define IEN_TPU0_TGI0C IEN0 +#define IEN_TPU0_TGI0D IEN1 +#define IEN_TPU0_TCI0V IEN2 +#define IEN_TPU1_TGI1A IEN3 +#define IEN_TPU1_TGI1B IEN4 +#define IEN_TPU1_TCI1V IEN5 +#define IEN_TPU1_TCI1U IEN6 +#define IEN_TPU2_TGI2A IEN7 +#define IEN_TPU2_TGI2B IEN0 +#define IEN_TPU2_TCI2V IEN1 +#define IEN_TPU2_TCI2U IEN2 +#define IEN_TPU3_TGI3A IEN3 +#define IEN_TPU3_TGI3B IEN4 +#define IEN_TPU3_TGI3C IEN5 +#define IEN_TPU3_TGI3D IEN6 +#define IEN_TPU3_TCI3V IEN7 +#define IEN_TPU4_TGI4A IEN0 +#define IEN_TPU4_TGI4B IEN1 +#define IEN_TPU4_TCI4V IEN2 +#define IEN_TPU4_TCI4U IEN3 +#define IEN_TPU5_TGI5A IEN4 +#define IEN_TPU5_TGI5B IEN5 +#define IEN_TPU5_TCI5V IEN6 +#define IEN_TPU5_TCI5U IEN7 +#define IEN_POE_OEI1 IEN2 +#define IEN_POE_OEI2 IEN3 +#define IEN_TMR0_CMIA0 IEN6 +#define IEN_TMR0_CMIB0 IEN7 +#define IEN_TMR0_OVI0 IEN0 +#define IEN_TMR1_CMIA1 IEN1 +#define IEN_TMR1_CMIB1 IEN2 +#define IEN_TMR1_OVI1 IEN3 +#define IEN_TMR2_CMIA2 IEN4 +#define IEN_TMR2_CMIB2 IEN5 +#define IEN_TMR2_OVI2 IEN6 +#define IEN_TMR3_CMIA3 IEN7 +#define IEN_TMR3_CMIB3 IEN0 +#define IEN_TMR3_OVI3 IEN1 +#define IEN_DMAC_DMAC0I IEN6 +#define IEN_DMAC_DMAC1I IEN7 +#define IEN_DMAC_DMAC2I IEN0 +#define IEN_DMAC_DMAC3I IEN1 +#define IEN_SCI0_ERI0 IEN6 +#define IEN_SCI0_RXI0 IEN7 +#define IEN_SCI0_TXI0 IEN0 +#define IEN_SCI0_TEI0 IEN1 +#define IEN_SCI1_ERI1 IEN2 +#define IEN_SCI1_RXI1 IEN3 +#define IEN_SCI1_TXI1 IEN4 +#define IEN_SCI1_TEI1 IEN5 +#define IEN_SCI5_ERI5 IEN6 +#define IEN_SCI5_RXI5 IEN7 +#define IEN_SCI5_TXI5 IEN0 +#define IEN_SCI5_TEI5 IEN1 +#define IEN_SCI6_ERI6 IEN2 +#define IEN_SCI6_RXI6 IEN3 +#define IEN_SCI6_TXI6 IEN4 +#define IEN_SCI6_TEI6 IEN5 +#define IEN_SCI8_ERI8 IEN6 +#define IEN_SCI8_RXI8 IEN7 +#define IEN_SCI8_TXI8 IEN0 +#define IEN_SCI8_TEI8 IEN1 +#define IEN_SCI9_ERI9 IEN2 +#define IEN_SCI9_RXI9 IEN3 +#define IEN_SCI9_TXI9 IEN4 +#define IEN_SCI9_TEI9 IEN5 +#define IEN_SCI12_ERI12 IEN6 +#define IEN_SCI12_RXI12 IEN7 +#define IEN_SCI12_TXI12 IEN0 +#define IEN_SCI12_TEI12 IEN1 +#define IEN_SCI12_SCIX0 IEN2 +#define IEN_SCI12_SCIX1 IEN3 +#define IEN_SCI12_SCIX2 IEN4 +#define IEN_SCI12_SCIX3 IEN5 +#define IEN_RIIC0_EEI0 IEN6 +#define IEN_RIIC0_RXI0 IEN7 +#define IEN_RIIC0_TXI0 IEN0 +#define IEN_RIIC0_TEI0 IEN1 + +#define VECT_BSC_BUSERR 16 +#define VECT_FCU_FRDYI 23 +#define VECT_ICU_SWINT 27 +#define VECT_CMT0_CMI0 28 +#define VECT_CMT1_CMI1 29 +#define VECT_CMT2_CMI2 30 +#define VECT_CMT3_CMI3 31 +#define VECT_CAC_FERRF 32 +#define VECT_CAC_MENDF 33 +#define VECT_CAC_OVFF 34 +#define VECT_USB0_D0FIFO0 36 +#define VECT_USB0_D1FIFO0 37 +#define VECT_USB0_USBI0 38 +#define VECT_SDHI_SBFAI 40 +#define VECT_SDHI_CDETI 41 +#define VECT_SDHI_CACI 42 +#define VECT_SDHI_SDACI 43 +#define VECT_RSPI0_SPEI0 44 +#define VECT_RSPI0_SPRI0 45 +#define VECT_RSPI0_SPTI0 46 +#define VECT_RSPI0_SPII0 47 +#define VECT_RSCAN_COMFRXINT 52 +#define VECT_RSCAN_RXFINT 53 +#define VECT_RSCAN_TXINT 54 +#define VECT_RSCAN_CHERRINT 55 +#define VECT_RSCAN_GLERRINT 56 +#define VECT_DOC_DOPCF 57 +#define VECT_CMPB_CMPB0 58 +#define VECT_CMPB_CMPB1 59 +#define VECT_CTSU_CTSUWR 60 +#define VECT_CTSU_CTSURD 61 +#define VECT_CTSU_CTSUFN 62 +#define VECT_RTC_CUP 63 +#define VECT_ICU_IRQ0 64 +#define VECT_ICU_IRQ1 65 +#define VECT_ICU_IRQ2 66 +#define VECT_ICU_IRQ3 67 +#define VECT_ICU_IRQ4 68 +#define VECT_ICU_IRQ5 69 +#define VECT_ICU_IRQ6 70 +#define VECT_ICU_IRQ7 71 +#define VECT_ELC_ELSR8I 80 +#define VECT_LVD_LVD1 88 +#define VECT_LVD_LVD2 89 +#define VECT_CMPA_CMPA1 88 +#define VECT_CMPA_CMPA2 89 +#define VECT_USB0_USBR0 90 +#define VECT_VBATT_VBTLVDI 91 +#define VECT_RTC_ALM 92 +#define VECT_RTC_PRD 93 +#define VECT_S12AD_S12ADI0 102 +#define VECT_S12AD_GBADI 103 +#define VECT_CMPB1_CMPB2 104 +#define VECT_CMPB1_CMPB3 105 +#define VECT_ELC_ELSR18I 106 +#define VECT_ELC_ELSR19I 107 +#define VECT_SSI0_SSIF0 108 +#define VECT_SSI0_SSIRXI0 109 +#define VECT_SSI0_SSITXI0 110 +#define VECT_SECURITY_RD 111 +#define VECT_SECURITY_WR 112 +#define VECT_SECURITY_ERR 113 +#define VECT_MTU0_TGIA0 114 +#define VECT_MTU0_TGIB0 115 +#define VECT_MTU0_TGIC0 116 +#define VECT_MTU0_TGID0 117 +#define VECT_MTU0_TCIV0 118 +#define VECT_MTU0_TGIE0 119 +#define VECT_MTU0_TGIF0 120 +#define VECT_MTU1_TGIA1 121 +#define VECT_MTU1_TGIB1 122 +#define VECT_MTU1_TCIV1 123 +#define VECT_MTU1_TCIU1 124 +#define VECT_MTU2_TGIA2 125 +#define VECT_MTU2_TGIB2 126 +#define VECT_MTU2_TCIV2 127 +#define VECT_MTU2_TCIU2 128 +#define VECT_MTU3_TGIA3 129 +#define VECT_MTU3_TGIB3 130 +#define VECT_MTU3_TGIC3 131 +#define VECT_MTU3_TGID3 132 +#define VECT_MTU3_TCIV3 133 +#define VECT_MTU4_TGIA4 134 +#define VECT_MTU4_TGIB4 135 +#define VECT_MTU4_TGIC4 136 +#define VECT_MTU4_TGID4 137 +#define VECT_MTU4_TCIV4 138 +#define VECT_MTU5_TGIU5 139 +#define VECT_MTU5_TGIV5 140 +#define VECT_MTU5_TGIW5 141 +#define VECT_TPU0_TGI0A 142 +#define VECT_TPU0_TGI0B 143 +#define VECT_TPU0_TGI0C 144 +#define VECT_TPU0_TGI0D 145 +#define VECT_TPU0_TCI0V 146 +#define VECT_TPU1_TGI1A 147 +#define VECT_TPU1_TGI1B 148 +#define VECT_TPU1_TCI1V 149 +#define VECT_TPU1_TCI1U 150 +#define VECT_TPU2_TGI2A 151 +#define VECT_TPU2_TGI2B 152 +#define VECT_TPU2_TCI2V 153 +#define VECT_TPU2_TCI2U 154 +#define VECT_TPU3_TGI3A 155 +#define VECT_TPU3_TGI3B 156 +#define VECT_TPU3_TGI3C 157 +#define VECT_TPU3_TGI3D 158 +#define VECT_TPU3_TCI3V 159 +#define VECT_TPU4_TGI4A 160 +#define VECT_TPU4_TGI4B 161 +#define VECT_TPU4_TCI4V 162 +#define VECT_TPU4_TCI4U 163 +#define VECT_TPU5_TGI5A 164 +#define VECT_TPU5_TGI5B 165 +#define VECT_TPU5_TCI5V 166 +#define VECT_TPU5_TCI5U 167 +#define VECT_POE_OEI1 170 +#define VECT_POE_OEI2 171 +#define VECT_TMR0_CMIA0 174 +#define VECT_TMR0_CMIB0 175 +#define VECT_TMR0_OVI0 176 +#define VECT_TMR1_CMIA1 177 +#define VECT_TMR1_CMIB1 178 +#define VECT_TMR1_OVI1 179 +#define VECT_TMR2_CMIA2 180 +#define VECT_TMR2_CMIB2 181 +#define VECT_TMR2_OVI2 182 +#define VECT_TMR3_CMIA3 183 +#define VECT_TMR3_CMIB3 184 +#define VECT_TMR3_OVI3 185 +#define VECT_DMAC_DMAC0I 198 +#define VECT_DMAC_DMAC1I 199 +#define VECT_DMAC_DMAC2I 200 +#define VECT_DMAC_DMAC3I 201 +#define VECT_SCI0_ERI0 214 +#define VECT_SCI0_RXI0 215 +#define VECT_SCI0_TXI0 216 +#define VECT_SCI0_TEI0 217 +#define VECT_SCI1_ERI1 218 +#define VECT_SCI1_RXI1 219 +#define VECT_SCI1_TXI1 220 +#define VECT_SCI1_TEI1 221 +#define VECT_SCI5_ERI5 222 +#define VECT_SCI5_RXI5 223 +#define VECT_SCI5_TXI5 224 +#define VECT_SCI5_TEI5 225 +#define VECT_SCI6_ERI6 226 +#define VECT_SCI6_RXI6 227 +#define VECT_SCI6_TXI6 228 +#define VECT_SCI6_TEI6 229 +#define VECT_SCI8_ERI8 230 +#define VECT_SCI8_RXI8 231 +#define VECT_SCI8_TXI8 232 +#define VECT_SCI8_TEI8 233 +#define VECT_SCI9_ERI9 234 +#define VECT_SCI9_RXI9 235 +#define VECT_SCI9_TXI9 236 +#define VECT_SCI9_TEI9 237 +#define VECT_SCI12_ERI12 238 +#define VECT_SCI12_RXI12 239 +#define VECT_SCI12_TXI12 240 +#define VECT_SCI12_TEI12 241 +#define VECT_SCI12_SCIX0 242 +#define VECT_SCI12_SCIX1 243 +#define VECT_SCI12_SCIX2 244 +#define VECT_SCI12_SCIX3 245 +#define VECT_RIIC0_EEI0 246 +#define VECT_RIIC0_RXI0 247 +#define VECT_RIIC0_TXI0 248 +#define VECT_RIIC0_TEI0 249 + +#define MSTP_DMAC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC0 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC1 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC2 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC3 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DTC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DA SYSTEM.MSTPCRA.BIT.MSTPA19 +#define MSTP_S12AD SYSTEM.MSTPCRA.BIT.MSTPA17 +#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_CMT3 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_TPU SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU0 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU1 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU2 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU3 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU4 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU5 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_MTU SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU0 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU1 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU2 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU4 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU5 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_TMR0 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR1 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR01 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR2 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR3 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR23 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_SCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SMCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SMCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SMCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_SMCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_CRC SYSTEM.MSTPCRB.BIT.MSTPB23 +#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPB21 +#define MSTP_USB0 SYSTEM.MSTPCRB.BIT.MSTPB19 +#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPB17 +#define MSTP_CMPB SYSTEM.MSTPCRB.BIT.MSTPB10 +#define MSTP_ELC SYSTEM.MSTPCRB.BIT.MSTPB9 +#define MSTP_DOC SYSTEM.MSTPCRB.BIT.MSTPB6 +#define MSTP_SCI12 SYSTEM.MSTPCRB.BIT.MSTPB4 +#define MSTP_SMCI12 SYSTEM.MSTPCRB.BIT.MSTPB4 +#define MSTP_RSCAN SYSTEM.MSTPCRB.BIT.MSTPB0 +#define MSTP_RSCAN0 SYSTEM.MSTPCRB.BIT.MSTPB0 +#define MSTP_SCI8 SYSTEM.MSTPCRC.BIT.MSTPC27 +#define MSTP_SMCI8 SYSTEM.MSTPCRC.BIT.MSTPC27 +#define MSTP_SCI9 SYSTEM.MSTPCRC.BIT.MSTPC26 +#define MSTP_SMCI9 SYSTEM.MSTPCRC.BIT.MSTPC26 +#define MSTP_IRDA SYSTEM.MSTPCRC.BIT.MSTPC20 +#define MSTP_CAC SYSTEM.MSTPCRC.BIT.MSTPC19 +#define MSTP_RAM0 SYSTEM.MSTPCRC.BIT.MSTPC0 +#define MSTP_SDHI SYSTEM.MSTPCRD.BIT.MSTPD19 +#define MSTP_SSI0 SYSTEM.MSTPCRD.BIT.MSTPD15 +#define MSTP_CTSU SYSTEM.MSTPCRD.BIT.MSTPD10 + +#define __IR( x ) ICU.IR[ IR ## x ].BIT.IR +#define _IR( x ) __IR( x ) +#define IR( x , y ) _IR( _ ## x ## _ ## y ) +#define __DTCE( x ) ICU.DTCER[ DTCE ## x ].BIT.DTCE +#define _DTCE( x ) __DTCE( x ) +#define DTCE( x , y ) _DTCE( _ ## x ## _ ## y ) +#define __IEN( x ) ICU.IER[ IER ## x ].BIT.IEN ## x +#define _IEN( x ) __IEN( x ) +#define IEN( x , y ) _IEN( _ ## x ## _ ## y ) +#define __IPR( x ) ICU.IPR[ IPR ## x ].BIT.IPR +#define _IPR( x ) __IPR( x ) +#define IPR( x , y ) _IPR( _ ## x ## _ ## y ) +#define __VECT( x ) VECT ## x +#define _VECT( x ) __VECT( x ) +#define VECT( x , y ) _VECT( _ ## x ## _ ## y ) +#define __MSTP( x ) MSTP ## x +#define _MSTP( x ) __MSTP( x ) +#define MSTP( x ) _MSTP( _ ## x ) + +#define BSC (*(volatile struct st_bsc __evenaccess *)0x81300) +#define CAC (*(volatile struct st_cac __evenaccess *)0x8B000) +#define CMPB (*(volatile struct st_cmpb __evenaccess *)0x8C580) +#define CMT (*(volatile struct st_cmt __evenaccess *)0x88000) +#define CMT0 (*(volatile struct st_cmt0 __evenaccess *)0x88002) +#define CMT1 (*(volatile struct st_cmt0 __evenaccess *)0x88008) +#define CMT2 (*(volatile struct st_cmt0 __evenaccess *)0x88012) +#define CMT3 (*(volatile struct st_cmt0 __evenaccess *)0x88018) +#define CRC (*(volatile struct st_crc __evenaccess *)0x88280) +#define CTSU (*(volatile struct st_ctsu __evenaccess *)0xA0900) +#define DA (*(volatile struct st_da __evenaccess *)0x88040) +#define DMAC (*(volatile struct st_dmac __evenaccess *)0x82200) +#define DMAC0 (*(volatile struct st_dmac0 __evenaccess *)0x82000) +#define DMAC1 (*(volatile struct st_dmac1 __evenaccess *)0x82040) +#define DMAC2 (*(volatile struct st_dmac1 __evenaccess *)0x82080) +#define DMAC3 (*(volatile struct st_dmac1 __evenaccess *)0x820C0) +#define DOC (*(volatile struct st_doc __evenaccess *)0x8B080) +#define DTC (*(volatile struct st_dtc __evenaccess *)0x82400) +#define ELC (*(volatile struct st_elc __evenaccess *)0x8B100) +#define FLASH (*(volatile struct st_flash __evenaccess *)0x7FC090) +#define FLASHCONST (*(volatile struct st_flashconst __evenaccess *)0x7FC350) +#define ICU (*(volatile struct st_icu __evenaccess *)0x87000) +#define IRDA (*(volatile struct st_irda __evenaccess *)0x88410) +#define IWDT (*(volatile struct st_iwdt __evenaccess *)0x88030) +#define LPT (*(volatile struct st_lpt __evenaccess *)0x800B0) +#define MPC (*(volatile struct st_mpc __evenaccess *)0x8C100) +#define MPU (*(volatile struct st_mpu __evenaccess *)0x86400) +#define MTU (*(volatile struct st_mtu __evenaccess *)0xD0A0A) +#define MTU0 (*(volatile struct st_mtu0 __evenaccess *)0xD0A90) +#define MTU1 (*(volatile struct st_mtu1 __evenaccess *)0xD0A90) +#define MTU2 (*(volatile struct st_mtu2 __evenaccess *)0xD0A92) +#define MTU3 (*(volatile struct st_mtu3 __evenaccess *)0xD0A00) +#define MTU4 (*(volatile struct st_mtu4 __evenaccess *)0xD0A00) +#define MTU5 (*(volatile struct st_mtu5 __evenaccess *)0xD0A94) +#define POE (*(volatile struct st_poe __evenaccess *)0x88900) +#define PORT (*(volatile struct st_port __evenaccess *)0x8C120) +#define PORT0 (*(volatile struct st_port0 __evenaccess *)0x8C000) +#define PORT1 (*(volatile struct st_port1 __evenaccess *)0x8C001) +#define PORT2 (*(volatile struct st_port2 __evenaccess *)0x8C002) +#define PORT3 (*(volatile struct st_port3 __evenaccess *)0x8C003) +#define PORT4 (*(volatile struct st_port4 __evenaccess *)0x8C004) +#define PORT5 (*(volatile struct st_port5 __evenaccess *)0x8C005) +#define PORTA (*(volatile struct st_porta __evenaccess *)0x8C00A) +#define PORTB (*(volatile struct st_portb __evenaccess *)0x8C00B) +#define PORTC (*(volatile struct st_portc __evenaccess *)0x8C00C) +#define PORTD (*(volatile struct st_portd __evenaccess *)0x8C00D) +#define PORTE (*(volatile struct st_porte __evenaccess *)0x8C00E) +#define PORTH (*(volatile struct st_porth __evenaccess *)0x8C011) +#define PORTJ (*(volatile struct st_portj __evenaccess *)0x8C012) +#define RIIC0 (*(volatile struct st_riic __evenaccess *)0x88300) +#define RSCAN (*(volatile struct st_rscan __evenaccess *)0xA8322) +#define RSCAN0 (*(volatile struct st_rscan0 __evenaccess *)0xA8300) +#define RSPI0 (*(volatile struct st_rspi __evenaccess *)0x88380) +#define RTC (*(volatile struct st_rtc __evenaccess *)0x8C400) +#define S12AD (*(volatile struct st_s12ad __evenaccess *)0x89000) +#define SCI0 (*(volatile struct st_sci0 __evenaccess *)0x8A000) +#define SCI1 (*(volatile struct st_sci0 __evenaccess *)0x8A020) +#define SCI5 (*(volatile struct st_sci0 __evenaccess *)0x8A0A0) +#define SCI6 (*(volatile struct st_sci0 __evenaccess *)0x8A0C0) +#define SCI8 (*(volatile struct st_sci0 __evenaccess *)0x8A100) +#define SCI9 (*(volatile struct st_sci0 __evenaccess *)0x8A120) +#define SCI12 (*(volatile struct st_sci12 __evenaccess *)0x8B300) +#define SDHI (*(volatile struct st_sdhi __evenaccess *)0x8AC00) +#define SMCI0 (*(volatile struct st_smci __evenaccess *)0x8A000) +#define SMCI1 (*(volatile struct st_smci __evenaccess *)0x8A020) +#define SMCI2 (*(volatile struct st_smci __evenaccess *)0x8A040) +#define SMCI3 (*(volatile struct st_smci __evenaccess *)0x8A060) +#define SMCI4 (*(volatile struct st_smci __evenaccess *)0x8A080) +#define SMCI5 (*(volatile struct st_smci __evenaccess *)0x8A0A0) +#define SMCI6 (*(volatile struct st_smci __evenaccess *)0x8A0C0) +#define SMCI7 (*(volatile struct st_smci __evenaccess *)0x8A0E0) +#define SMCI8 (*(volatile struct st_smci __evenaccess *)0x8A100) +#define SMCI9 (*(volatile struct st_smci __evenaccess *)0x8A120) +#define SMCI10 (*(volatile struct st_smci __evenaccess *)0x8A140) +#define SMCI11 (*(volatile struct st_smci __evenaccess *)0x8A150) +#define SMCI12 (*(volatile struct st_smci __evenaccess *)0x8B300) +#define SSI0 (*(volatile struct st_ssi __evenaccess *)0x8A500) +#define SYSTEM (*(volatile struct st_system __evenaccess *)0x80000) +#define TEMPSCONST (*(volatile struct st_tempsconst __evenaccess *)0x7FC0A0) +#define TMR0 (*(volatile struct st_tmr0 __evenaccess *)0x88200) +#define TMR1 (*(volatile struct st_tmr1 __evenaccess *)0x88201) +#define TMR2 (*(volatile struct st_tmr0 __evenaccess *)0x88210) +#define TMR3 (*(volatile struct st_tmr1 __evenaccess *)0x88211) +#define TMR01 (*(volatile struct st_tmr01 __evenaccess *)0x88204) +#define TMR23 (*(volatile struct st_tmr01 __evenaccess *)0x88214) +#define TPU (*(volatile struct st_tpu __evenaccess *)0x88100) +#define TPU0 (*(volatile struct st_tpu0 __evenaccess *)0x88108) +#define TPU1 (*(volatile struct st_tpu1 __evenaccess *)0x88108) +#define TPU2 (*(volatile struct st_tpu2 __evenaccess *)0x8810A) +#define TPU3 (*(volatile struct st_tpu3 __evenaccess *)0x8810A) +#define TPU4 (*(volatile struct st_tpu4 __evenaccess *)0x8810C) +#define TPU5 (*(volatile struct st_tpu5 __evenaccess *)0x8810C) +#define USB0 (*(volatile struct st_usb0 __evenaccess *)0xA0000) +#define WDT (*(volatile struct st_wdt __evenaccess *)0x88020) +#pragma bit_order +#pragma packoption +#endif diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/main.c b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/main.c new file mode 100644 index 000000000..409c03775 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/main.c @@ -0,0 +1,251 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * This project provides two demo applications. A simple blinky style project, + * and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to + * select between the two. The simply blinky demo is implemented and described + * in main_blinky.c. The more comprehensive test and demo application is + * implemented and described in main_full.c. + * + * This file implements the code that is not demo specific, including the + * hardware setup, standard FreeRTOS hook functions, and the ISR hander called + * by the RTOS after interrupt entry (including nesting) has been taken care of. + * + * ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON + * THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO + * APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT! + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, +or 0 to run the more comprehensive test and demo application. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 + +/*-----------------------------------------------------------*/ + +/* + * Configure the hardware as necessary to run this demo. + */ +static void prvSetupHardware( void ); + +/* + * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. + * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. + */ +#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + extern void main_blinky( void ); +#else + extern void main_full( void ); +#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */ + +/* Prototypes for the standard FreeRTOS callback/hook functions implemented +within this file. */ +void vApplicationMallocFailedHook( void ); +void vApplicationIdleHook( void ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationTickHook( void ); + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Configure the hardware ready to run the demo. */ + prvSetupHardware(); + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + of this file. */ + #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + { + main_blinky(); + } + #else + { + main_full(); + } + #endif + + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ +/* Start user code. Do not edit comment generated here */ +uint16_t usProtectDummy = ( uint16_t ) ( SYSTEM.PRCR.WORD & 0x000FU ); + + /* Disable protect bit */ + SYSTEM.PRCR.WORD = 0xA50FU; + + SYSTEM.VBATTCR.BYTE = 0x81U; + + /* Restore the previous state of the protect register */ + SYSTEM.PRCR.WORD = ( uint16_t )( 0xA500U | usProtectDummy ); +} +/*-----------------------------------------------------------*/ + +void vApplicationMallocFailedHook( void ) +{ + /* Called if a call to pvPortMalloc() fails because there is insufficient + free memory available in the FreeRTOS heap. pvPortMalloc() is called + internally by FreeRTOS API functions that create tasks, queues, software + timers, and semaphores. The size of the FreeRTOS heap is set by the + configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); +} +/*-----------------------------------------------------------*/ + +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +{ + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + function is called if a stack overflow is detected. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ +volatile size_t xFreeHeapSpace; + + /* This is just a trivial example of an idle hook. It is called on each + cycle of the idle task. It must *NOT* attempt to block. In this case the + idle task just queries the amount of FreeRTOS heap that remains. See the + memory management section on the http://www.FreeRTOS.org web site for memory + management options. If there is a lot of heap memory free then the + configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up + RAM. */ + xFreeHeapSpace = xPortGetFreeHeapSize(); + + /* Remove compiler warning about xFreeHeapSpace being set but never used. */ + ( void ) xFreeHeapSpace; +} +/*-----------------------------------------------------------*/ + +void vApplicationTickHook( void ) +{ + #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 + { + extern void vFullDemoTickHook( void ); + + vFullDemoTickHook(); + } + #endif +} +/*-----------------------------------------------------------*/ + +/* The RX port uses this callback function to configure its tick interrupt. +This allows the application to choose the tick interrupt source. */ +void vApplicationSetupTimerInterrupt( void ) +{ +const uint32_t ulEnableRegisterWrite = 0xA50BUL, ulDisableRegisterWrite = 0xA500UL; + + /* Disable register write protection. */ + SYSTEM.PRCR.WORD = ulEnableRegisterWrite; + + /* Enable compare match timer 0. */ + MSTP( CMT0 ) = 0; + + /* Interrupt on compare match. */ + CMT0.CMCR.BIT.CMIE = 1; + + /* Set the compare match value. */ + CMT0.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) -1 ) / 8 ); + + /* Divide the PCLK by 8. */ + CMT0.CMCR.BIT.CKS = 0; + + /* Enable the interrupt... */ + _IEN( _CMT0_CMI0 ) = 1; + + /* ...and set its priority to the application defined kernel priority. */ + _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the timer. */ + CMT.CMSTR0.BIT.STR0 = 1; + + /* Reneable register protection. */ + SYSTEM.PRCR.WORD = ulDisableRegisterWrite; +} + + + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.cproject b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.cproject index bc67806b2..592b8164c 100644 --- a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.cproject +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.cproject @@ -120,7 +120,7 @@ - + @@ -134,5 +134,9 @@ - + + + + + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.project b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.project index e1a619318..d82dcb065 100644 --- a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.project +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.project @@ -42,6 +42,15 @@ + + 1442924121510 + + 10 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-RTOSDemo + + 1442756186478 src/FreeRTOS_Source @@ -51,6 +60,15 @@ 1.0-name-matches-false-false-croutine.c + + 1442924751731 + src/Full_Demo + 6 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-*_IAR.* + + 1442753620317 src/FreeRTOS_Source/portable diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.settings/language.settings.xml b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.settings/language.settings.xml index ec00737f5..809fddcfc 100644 --- a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.settings/language.settings.xml +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.settings/language.settings.xml @@ -3,7 +3,7 @@ - + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/RTOSDemo.ewd b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/RTOSDemo.ewd new file mode 100644 index 000000000..3ef1570c0 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/RTOSDemo.ewd @@ -0,0 +1,771 @@ + + + + 2 + + Debug + + RX + + 1 + + C-SPY + 3 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RXEMUE20 + 4 + + 4 + 1 + 1 + + + + + + + + + + + + + + + RXE2LITE + 1 + + 0 + 1 + 1 + + + + + + + + + + + + + + + RXJLINK + 4 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + SIMRX + 1 + + 1 + 1 + 1 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXRxPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + RX + + 0 + + C-SPY + 3 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RXEMUE20 + 4 + + 4 + 1 + 0 + + + + + + + + + + + + + + + RXE2LITE + 1 + + 0 + 1 + 0 + + + + + + + + + + + + + + + RXJLINK + 4 + + 5 + 1 + 0 + + + + + + + + + + + + + + + + + + SIMRX + 1 + + 1 + 1 + 0 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXRxPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/RTOSDemo.ewp b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/RTOSDemo.ewp new file mode 100644 index 000000000..9ea5290e2 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/RTOSDemo.ewp @@ -0,0 +1,2050 @@ + + + + 2 + + Debug + + RX + + 1 + + General + 6 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCRX + 8 + + 17 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARX + 6 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 1 + + 0 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 4 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 1 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + RX + + 0 + + General + 6 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCRX + 8 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARX + 6 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 1 + + 0 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 4 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 1 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Blinky_Demo + + $PROJ_DIR$\src\Blinky_Demo\main_blinky.c + + + + cg_src + + $PROJ_DIR$\src\cg_src\r_cg_cgc.c + + + $PROJ_DIR$\src\cg_src\r_cg_hardware_setup.c + + + $PROJ_DIR$\src\cg_src\r_cg_icu.c + + + $PROJ_DIR$\src\cg_src\r_cg_port.c + + + $PROJ_DIR$\src\cg_src\r_cg_sci.c + + + $PROJ_DIR$\src\cg_src\r_cg_sci_user_iar.c + + + + FreeRTOS_Source + + portable + + MemMang + + $PROJ_DIR$\..\..\Source\portable\MemMang\heap_4.c + + + + $PROJ_DIR$\..\..\Source\portable\IAR\RXv2\port.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\RXv2\port_asm.s + + + + $PROJ_DIR$\..\..\Source\event_groups.c + + + $PROJ_DIR$\..\..\Source\list.c + + + $PROJ_DIR$\..\..\Source\queue.c + + + $PROJ_DIR$\..\..\Source\tasks.c + + + $PROJ_DIR$\..\..\Source\timers.c + + + + Full_Demo + + Standard_Demo_Tasks + + $PROJ_DIR$\..\Common\Minimal\BlockQ.c + + + $PROJ_DIR$\..\Common\Minimal\blocktim.c + + + $PROJ_DIR$\..\Common\Minimal\countsem.c + + + $PROJ_DIR$\..\Common\Minimal\death.c + + + $PROJ_DIR$\..\Common\Minimal\dynamic.c + + + $PROJ_DIR$\..\Common\Minimal\EventGroupsDemo.c + + + $PROJ_DIR$\..\Common\Minimal\flop.c + + + $PROJ_DIR$\..\Common\Minimal\GenQTest.c + + + $PROJ_DIR$\..\Common\Minimal\IntQueue.c + + + $PROJ_DIR$\..\Common\Minimal\IntSemTest.c + + + $PROJ_DIR$\..\Common\Minimal\QueueOverwrite.c + + + $PROJ_DIR$\..\Common\Minimal\recmutex.c + + + $PROJ_DIR$\..\Common\Minimal\semtest.c + + + $PROJ_DIR$\..\Common\Minimal\TaskNotify.c + + + $PROJ_DIR$\..\Common\Minimal\TimerDemo.c + + + + $PROJ_DIR$\src\Full_Demo\IntQueueTimer.c + + + $PROJ_DIR$\src\Full_Demo\main_full.c + + + $PROJ_DIR$\src\Full_Demo\RegTest_IAR.s + + + + $PROJ_DIR$\src\FreeRTOSConfig.h + + + $PROJ_DIR$\src\main.c + + + $PROJ_DIR$\src\rskrx71mdef.h + + + + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/RTOSDemo.eww b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/RTOSDemo.eww new file mode 100644 index 000000000..239a9381e --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/RTOSDemo.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\RTOSDemo.ewp + + + + + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.cspy.bat b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.cspy.bat new file mode 100644 index 000000000..ac83a6234 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%1" == "" goto debugFile + +@echo on + +"C:\DevTools\IAR Systems\Embedded Workbench 7.2\common\bin\cspybat" -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\RX700_RX71M_RSK_GCC_e2studio_IAR\settings\RTOSDemo.Debug.general.xcl" --backend -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\RX700_RX71M_RSK_GCC_e2studio_IAR\settings\RTOSDemo.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\DevTools\IAR Systems\Embedded Workbench 7.2\common\bin\cspybat" -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\RX700_RX71M_RSK_GCC_e2studio_IAR\settings\RTOSDemo.Debug.general.xcl" "--debug_file=%1" --backend -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\RX700_RX71M_RSK_GCC_e2studio_IAR\settings\RTOSDemo.Debug.driver.xcl" + +@echo off +:end \ No newline at end of file diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.driver.xcl b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.driver.xcl new file mode 100644 index 000000000..1830f5d18 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.driver.xcl @@ -0,0 +1,37 @@ + -B + +"-p" + +"C:\DevTools\IAR Systems\Embedded Workbench 7.2\rx\config\debugger\ior5f571ml.ddf" + +"--endian" + +"l" + +"--double" + +"32" + +"--core" + +"rxv2" + +"--int" + +"32" + +"-d" + +"emue20" + +"--drv_mode" + +"debugging" + +"--drv_communication" + +"USB" + + + + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.general.xcl b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.general.xcl new file mode 100644 index 000000000..0ada92176 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.general.xcl @@ -0,0 +1,11 @@ +"C:\DevTools\IAR Systems\Embedded Workbench 7.2\rx\bin\rxproc.dll" + +"C:\DevTools\IAR Systems\Embedded Workbench 7.2\rx\bin\rxe1e20.dll" + +"C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\RX700_RX71M_RSK_GCC_e2studio_IAR\Debug\Exe\RTOSDemo.out" + +--plugin "C:\DevTools\IAR Systems\Embedded Workbench 7.2\rx\bin\rxbat.dll" + + + + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.dbgdt b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.dbgdt new file mode 100644 index 000000000..4f7e51010 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.dbgdt @@ -0,0 +1,244 @@ + + + + + + + 20 + 1622 + + + 20 + 1216 + 324 + 81 + + + + 255 + 27 + 27 + 27 + + + + + Disassembly + _I0 + + + 500 + 20 + + + + 2 + 0 + 0 + + + 1 + 1 + + + + 2 + 0 + 0 + + + + + + + + + TabID-6594-3339 + Debug Log + Debug-Log + + + + TabID-6072-3348 + Build + Build + + + + 0 + + + + + TabID-17343-3342 + Workspace + Workspace + + + RTOSDemo + + + + + 0 + + + + + + TextEditor + $WS_DIR$\src\main.c + 0 + 0 + 0 + 0 + 0 + 66 + 5312 + 5312 + + + TextEditor + $WS_DIR$\src\Full_Demo\RegTest_IAR.s + 0 + 0 + 0 + 0 + 0 + 144 + 5881 + 5881 + + + TextEditor + $WS_DIR$\..\Common\Minimal\flop.c + 0 + 0 + 0 + 0 + 0 + 126 + 6956 + 6956 + + + TextEditor + $WS_DIR$\..\Common\Minimal\TimerDemo.c + 0 + 0 + 0 + 0 + 0 + 242 + 12612 + 12612 + + + TextEditor + $WS_DIR$\..\Common\Minimal\IntQueue.c + 0 + 0 + 0 + 0 + 0 + 381 + 0 + 0 + + + TextEditor + $WS_DIR$\src\Full_Demo\IntQueueTimer.c + 0 + 0 + 0 + 0 + 0 + 154 + 7349 + 7349 + + 5 + + 0 + + + 1000000 + 1000000 + + + 1 + + + + + + + iaridepm.enu1 + + + + + + + debuggergui.enu1 + + + + + + + + + + -2 + -2 + 718 + 329 + -2 + -2 + 200 + 200 + 119048 + 203252 + 197024 + 731707 + + + + + + + + + + + + + + + + -2 + -2 + 198 + 1682 + -2 + -2 + 1684 + 200 + 1002381 + 203252 + 119048 + 203252 + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.dni b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.dni new file mode 100644 index 000000000..c48d2fd74 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.dni @@ -0,0 +1,250 @@ +[DebugChecksum] +Checksum=-126027898 +[CodeCoverage] +Enabled=_ 0 +[Stack] +FillEnabled=0 +OverflowWarningsEnabled=1 +WarningThreshold=90 +SpWarningsEnabled=1 +WarnLogOnly=1 +UseTrigger=1 +TriggerName=main +LimitSize=0 +ByteLimit=50 +[CallStack] +ShowArgs=0 +[Disassembly] +MixedMode=1 +[E1/E20] +BlockBits=15 +B0=1,0 +B1=1,1024 +B2=1,2048 +B3=1,3072 +StartEnabled=0 +StartSymbol= +StopEnabled=0 +StopSymbol= +RecordingCondition=0 +TraceMode=0 +TraceOutput=0 +TraceType=0 +TraceCapacity=0 +TraceRestart=0 +TraceTimeStamp=0 +TraceTimestampDivision=0 +TraceDataTransfer=1 +TraceStackOperation=1 +TraceStringOperation=1 +TraceArithmeticalOperation=1 +TraceLogicalOperation=1 +TraceBitOperation=1 +TraceFPU=1 +TraceException=1 +OperatingFrequency=0.000000 +PerfEnabled=0 +PerfCondition=0,0 +PerfDisplayTime=0,0 +PerfOnlyOnce=0,0 +PerfUse64Bit=0 +ChipName=R5F571ML +PinMode=0 +RegMode=0 +Endian=0 +ExtMemBlockNum=55 +ExtMemEndian_000=0 +ExtMemCondAccess_000=0 +ExtMemEndian_001=0 +ExtMemCondAccess_001=0 +ExtMemEndian_002=0 +ExtMemCondAccess_002=0 +ExtMemEndian_003=0 +ExtMemCondAccess_003=0 +ExtMemEndian_004=0 +ExtMemCondAccess_004=0 +ExtMemEndian_005=0 +ExtMemCondAccess_005=0 +ExtMemEndian_006=0 +ExtMemCondAccess_006=0 +ExtMemEndian_007=0 +ExtMemCondAccess_007=0 +ExtMemEndian_008=0 +ExtMemCondAccess_008=0 +ExtMemEndian_009=0 +ExtMemCondAccess_009=0 +ExtMemEndian_010=0 +ExtMemCondAccess_010=0 +ExtMemEndian_011=0 +ExtMemCondAccess_011=0 +ExtMemEndian_012=0 +ExtMemCondAccess_012=0 +ExtMemEndian_013=0 +ExtMemCondAccess_013=0 +ExtMemEndian_014=0 +ExtMemCondAccess_014=0 +ExtMemEndian_015=0 +ExtMemCondAccess_015=0 +ExtMemEndian_016=0 +ExtMemCondAccess_016=0 +ExtMemEndian_017=0 +ExtMemCondAccess_017=0 +ExtMemEndian_018=0 +ExtMemCondAccess_018=0 +ExtMemEndian_019=0 +ExtMemCondAccess_019=0 +ExtMemEndian_020=0 +ExtMemCondAccess_020=0 +ExtMemEndian_021=0 +ExtMemCondAccess_021=0 +ExtMemEndian_022=0 +ExtMemCondAccess_022=0 +ExtMemEndian_023=0 +ExtMemCondAccess_023=0 +ExtMemEndian_024=0 +ExtMemCondAccess_024=0 +ExtMemEndian_025=0 +ExtMemCondAccess_025=0 +ExtMemEndian_026=0 +ExtMemCondAccess_026=0 +ExtMemEndian_027=0 +ExtMemCondAccess_027=0 +ExtMemEndian_028=0 +ExtMemCondAccess_028=0 +ExtMemEndian_029=0 +ExtMemCondAccess_029=0 +ExtMemEndian_030=0 +ExtMemCondAccess_030=0 +ExtMemEndian_031=0 +ExtMemCondAccess_031=0 +ExtMemEndian_032=0 +ExtMemCondAccess_032=0 +ExtMemEndian_033=0 +ExtMemCondAccess_033=0 +ExtMemEndian_034=0 +ExtMemCondAccess_034=0 +ExtMemEndian_035=0 +ExtMemCondAccess_035=0 +ExtMemEndian_036=0 +ExtMemCondAccess_036=0 +ExtMemEndian_037=0 +ExtMemCondAccess_037=0 +ExtMemEndian_038=0 +ExtMemCondAccess_038=0 +ExtMemEndian_039=0 +ExtMemCondAccess_039=0 +ExtMemEndian_040=0 +ExtMemCondAccess_040=0 +ExtMemEndian_041=0 +ExtMemCondAccess_041=0 +ExtMemEndian_042=0 +ExtMemCondAccess_042=0 +ExtMemEndian_043=0 +ExtMemCondAccess_043=0 +ExtMemEndian_044=0 +ExtMemCondAccess_044=0 +ExtMemEndian_045=0 +ExtMemCondAccess_045=0 +ExtMemEndian_046=0 +ExtMemCondAccess_046=0 +ExtMemEndian_047=0 +ExtMemCondAccess_047=0 +ExtMemEndian_048=0 +ExtMemCondAccess_048=0 +ExtMemEndian_049=0 +ExtMemCondAccess_049=0 +ExtMemEndian_050=0 +ExtMemCondAccess_050=0 +ExtMemEndian_051=0 +ExtMemCondAccess_051=0 +ExtMemEndian_052=0 +ExtMemCondAccess_052=0 +ExtMemEndian_053=0 +ExtMemCondAccess_053=0 +ExtMemEndian_054=0 +ExtMemCondAccess_054=0 +InputClock=25.000000 +ICLK=240.000000 +AllowClkSrcChange=0 +WorkRamStart=4096 +ComunicationSelect=0 +UseExtal=1 +JtagClock=10 +FINE=2000000 +EraseFlash=1,0 +DebugFlags=0,0 +EmulatorMode=0 +PowerTargetFromEmulator=1 +Voltage=0 +UseExtFlashFile_0=0 +ExtFlashFile_0= +EraseExtFlashBeforeDownload_0=0 +UseExtFlashFile_1=0 +ExtFlashFile_1= +EraseExtFlashBeforeDownload_1=0 +UseExtFlashFile_2=0 +ExtFlashFile_2= +EraseExtFlashBeforeDownload_2=0 +UseExtFlashFile_3=0 +ExtFlashFile_3= +EraseExtFlashBeforeDownload_3=0 +NeedInitExtMem=0 +NeedInit=0 +[CallStackLog] +Enabled=0 +[CallStackStripe] +ShowTiming=1 +[InterruptLog] +LogEnabled=0 +GraphEnabled=0 +ShowTimeLog=1 +SumEnabled=0 +ShowTimeSum=1 +SumSortOrder=0 +[DataLog] +LogEnabled=0 +GraphEnabled=0 +ShowTimeLog=1 +SumEnabled=0 +ShowTimeSum=1 +[Breakpoints2] +Count=0 +[Interrupts] +Enabled=1 +[MemoryMap] +Enabled=0 +Base=0 +UseAuto=0 +TypeViolation=1 +UnspecRange=1 +ActionState=1 +[Simulator] +Freq=98000000 +[DataSample] +LogEnabled=0 +GraphEnabled=0 +ShowTimeLog=1 +[DriverProfiling] +Enabled=0 +Mode=1 +Graph=0 +Symbiont=0 +Exclusions= +[Log file] +LoggingEnabled=_ 0 +LogFile=_ "" +Category=_ 0 +[TermIOLog] +LoggingEnabled=_ 0 +LogFile=_ "" +[Breakpoints] +Count=0 +[Monitor Execution] +Leave target running=0 +Release target=0 +[Trace1] +Enabled=0 +ShowSource=1 +[Aliases] +Count=0 +SuppressDialog=0 diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.wsdt b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.wsdt new file mode 100644 index 000000000..d82098c0f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.wsdt @@ -0,0 +1,77 @@ + + + + + + RTOSDemo/Debug + + + + + + + + + 310272727 + + + + + + + 20121632481 + + + 20 + 1622 + + + + + + + + + TabID-13537-752 + Workspace + Workspace + + + RTOSDemoRTOSDemo/Blinky_DemoRTOSDemo/FreeRTOS_SourceRTOSDemo/FreeRTOS_Source/portableRTOSDemo/Full_DemoRTOSDemo/Full_Demo/Standard_Demo_TasksRTOSDemo/cg_src + + + + 0 + + + TabID-29660-3316 + Build + Build + + + + TabID-19897-23353 + Debug Log + Debug-Log + + + + + 0 + + + + + + TextEditor$WS_DIR$\src\main.c000006653125312TextEditor$WS_DIR$\src\Full_Demo\RegTest_IAR.s0000014458815881TextEditor$WS_DIR$\..\Common\Minimal\flop.c0000012669566956TextEditor$WS_DIR$\..\Common\Minimal\TimerDemo.c000002421261212612TextEditor$WS_DIR$\..\Common\Minimal\IntQueue.c0000038100TextEditor$WS_DIR$\src\Full_Demo\IntQueueTimer.c0000014273497349TextEditor$WS_DIR$\..\..\Source\portable\IAR\RXv2\port.c00000614241424160100000010000001 + + + + + + + iaridepm.enu1-2-2742400-2-2200200119048203252239286756098-2-21981682-2-216842001002381203252119048203252 + + + + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.wspos b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.wspos new file mode 100644 index 000000000..ecdc2c482 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.wspos @@ -0,0 +1,2 @@ +[MainWindow] +WindowPlacement=_ 519 0 1619 872 3 diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h index 75141fdca..5faf0cea9 100644 --- a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h @@ -71,7 +71,14 @@ #define FREERTOS_CONFIG_H /* Renesas hardware definition header. */ -#include "iodefine.h" +#ifdef __ICCRX__ + #include + #include +#endif + +#ifdef __GNUC__ + #include "iodefine.h" +#endif /*----------------------------------------------------------- * Application specific definitions. @@ -128,7 +135,7 @@ kernel is doing. */ /* The peripheral used to generate the tick interrupt is configured as part of the application code. This constant should be set to the vector number of the peripheral chosen. As supplied this is CMT0. */ -#define configTICK_VECTOR _CMT0_CMI0 +#define configTICK_VECTOR 28 /*vect _CMT0_CMI0*/ /* Set the following definitions to 1 to include the API function, or zero to exclude the API function. */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c index 0da468ed3..bd4d82417 100644 --- a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c @@ -68,9 +68,9 @@ */ /* - * This file contains the non-portable and therefore RX62N specific parts of - * the IntQueue standard demo task - namely the configuration of the timers - * that generate the interrupts and the interrupt entry points. + * This file contains the non-portable and therefore RX specific parts of the + * IntQueue standard demo task - namely the configuration of the timers that + * generate the interrupts and the interrupt entry points. */ /* Scheduler includes. */ @@ -81,23 +81,8 @@ #include "IntQueueTimer.h" #include "IntQueue.h" -/* Hardware specifics. */ -#include "iodefine.h" - -#define IPR_PERIB_INTB128 128 -#define IPR_PERIB_INTB129 129 -#define IER_PERIB_INTB128 0x10 -#define IER_PERIB_INTB129 0x10 -#define IEN_PERIB_INTB128 IEN0 -#define IEN_PERIB_INTB129 IEN1 -#define IR_PERIB_INTB128 128 -#define IR_PERIB_INTB129 129 - -void vIntQTimerISR0( void ) __attribute__ ((interrupt)); -void vIntQTimerISR1( void ) __attribute__ ((interrupt)); - #define tmrTIMER_0_1_FREQUENCY ( 2000UL ) -#define tmrTIMER_2_3_FREQUENCY ( 2001UL ) +#define tmrTIMER_2_3_FREQUENCY ( 2301UL ) void vInitialiseTimerForIntQueueTest( void ) { @@ -107,7 +92,7 @@ void vInitialiseTimerForIntQueueTest( void ) /* Give write access. */ SYSTEM.PRCR.WORD = 0xa502; - /* Cascade two 8bit timer channels to generate the interrupts. + /* Cascade two 8bit timer channels to generate the interrupts. 8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are utilised for this test. */ @@ -130,11 +115,11 @@ void vInitialiseTimerForIntQueueTest( void ) /* 16 bit operation ( count from timer 1,2 ). */ TMR0.TCCR.BIT.CSS = 3; TMR2.TCCR.BIT.CSS = 3; - + /* Use PCLK as the input. */ TMR1.TCCR.BIT.CSS = 1; TMR3.TCCR.BIT.CSS = 1; - + /* Divide PCLK by 8. */ TMR1.TCCR.BIT.CKS = 2; TMR3.TCCR.BIT.CKS = 2; @@ -143,11 +128,9 @@ void vInitialiseTimerForIntQueueTest( void ) TMR0.TCR.BIT.CMIEA = 1; TMR2.TCR.BIT.CMIEA = 1; - /* Map TMR0 CMIA0 interrupt to vector slot B number 128 and set - priority above the kernel's priority, but below the max syscall - priority. */ - ICU.SLIBXR128.BYTE = 3; /* Three is TMR0 compare match A. */ - IPR( PERIB, INTB128 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1; + /* Set priority and enable interrupt. */ + ICU.SLIBXR128.BYTE = 3; /* Three is TMR0 compare match A. */ + IPR( PERIB, INTB128 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1; IEN( PERIB, INTB128 ) = 1; /* Ensure that the flag is set to 0, otherwise the interrupt will not be @@ -155,8 +138,8 @@ void vInitialiseTimerForIntQueueTest( void ) IR( PERIB, INTB128 ) = 0; /* Do the same for TMR2, but to vector 129. */ - ICU.SLIBXR129.BYTE = 9; /* Nine is TMR2 compare match A. */ - IPR( PERIB, INTB129 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 2; + ICU.SLIBXR129.BYTE = 9; /* Nine is TMR2 compare match A. */ + IPR( PERIB, INTB129 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 2; IEN( PERIB, INTB129 ) = 1; IR( PERIB, INTB129 ) = 0; } @@ -164,25 +147,49 @@ void vInitialiseTimerForIntQueueTest( void ) } /*-----------------------------------------------------------*/ -/* On vector 128. */ -void vIntQTimerISR0( void ) -{ - /* Enable interrupts to allow interrupt nesting. */ - __asm volatile( "setpsw i" ); +#ifdef __GNUC__ + + void vIntQTimerISR0( void ) __attribute__ ((interrupt)); + void vIntQTimerISR1( void ) __attribute__ ((interrupt)); + + void vIntQTimerISR0( void ) + { + /* Enable interrupts to allow interrupt nesting. */ + __asm volatile( "setpsw i" ); + + portYIELD_FROM_ISR( xFirstTimerHandler() ); + } + /*-----------------------------------------------------------*/ + + void vIntQTimerISR1( void ) + { + /* Enable interrupts to allow interrupt nesting. */ + __asm volatile( "setpsw i" ); + + portYIELD_FROM_ISR( xSecondTimerHandler() ); + } +#endif /* __GNUC__ */ +/*-----------------------------------------------------------*/ + +#ifdef __ICCRX__ + +#pragma vector = VECT_PERIB_INTB128 +__interrupt void vT0_1InterruptHandler( void ) +{ + __enable_interrupt(); portYIELD_FROM_ISR( xFirstTimerHandler() ); } /*-----------------------------------------------------------*/ -/* On vector 129. */ -void vIntQTimerISR1( void ) +#pragma vector = VECT_PERIB_INTB129 +__interrupt void vT2_3InterruptHandler( void ) { - /* Enable interrupts to allow interrupt nesting. */ - __asm volatile( "setpsw i" ); - + __enable_interrupt(); portYIELD_FROM_ISR( xSecondTimerHandler() ); } +#endif /* __ICCRX__ */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest.S b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest_GCC.S similarity index 100% rename from FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest.S rename to FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest_GCC.S diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest_IAR.s b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest_IAR.s new file mode 100644 index 000000000..af07b4bf0 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest_IAR.s @@ -0,0 +1,304 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + PUBLIC _vRegTest1Implementation + PUBLIC _vRegTest2Implementation + + EXTERN _ulRegTest1LoopCounter + EXTERN _ulRegTest2LoopCounter + + RSEG CODE:CODE(4) + +/* This function is explained in the comments at the top of main.c. */ +_vRegTest1Implementation: + + ;/* Put a known value in the guard byte of the accumulators. */ + MOV.L #10, R1 + MVTACGU R1, A0 + MOV.L #20, R1 + MVTACGU R1, A1 + + /* Put a known value in each register. */ + MOV #1, R1 + MOV #2, R2 + MOV #3, R3 + MOV #4, R4 + MOV #5, R5 + MOV #6, R6 + MOV #7, R7 + MOV #8, R8 + MOV #9, R9 + MOV #10, R10 + MOV #11, R11 + MOV #12, R12 + MOV #13, R13 + MOV #14, R14 + MOV #15, R15 + + ;/* Put a known value in the hi and low of the accumulators. */ + MVTACHI R1, A0 + MVTACLO R2, A0 + MVTACHI R3, A1 + MVTACLO R4, A1 + /* Loop, checking each itteration that each register still contains the + expected value. */ +TestLoop1: + + /* Push the registers that are going to get clobbered. */ + PUSHM R14-R15 + + /* Increment the loop counter to show this task is still getting CPU time. */ + MOV #_ulRegTest1LoopCounter, R14 + MOV [ R14 ], R15 + ADD #1, R15 + MOV R15, [ R14 ] + + /* Yield to extend the text coverage. Set the bit in the ITU SWINTR register. */ + MOV #1, R14 + MOV #0872E0H, R15 + MOV.B R14, [R15] + NOP + NOP + + ;/* Check accumulators. */ + MVFACHI #0, A0, R15 + CMP #1, R15 + BNE RegTest1Error + MVFACLO #0, A0, R15 + CMP #2, R15 + BNE RegTest1Error + MVFACGU #0, A0, R15 + CMP #10, R15 + BNE RegTest1Error + MVFACHI #0, A1, R15 + CMP #3, R15 + BNE RegTest1Error + MVFACLO #0, A1, R15 + CMP #4, R15 + BNE RegTest1Error + MVFACGU #0, A1, R15 + CMP #20, R15 + BNE RegTest1Error + + /* Restore the clobbered registers. */ + POPM R14-R15 + + /* Now compare each register to ensure it still contains the value that was + set before this loop was entered. */ + CMP #1, R1 + BNE RegTest1Error + CMP #2, R2 + BNE RegTest1Error + CMP #3, R3 + BNE RegTest1Error + CMP #4, R4 + BNE RegTest1Error + CMP #5, R5 + BNE RegTest1Error + CMP #6, R6 + BNE RegTest1Error + CMP #7, R7 + BNE RegTest1Error + CMP #8, R8 + BNE RegTest1Error + CMP #9, R9 + BNE RegTest1Error + CMP #10, R10 + BNE RegTest1Error + CMP #11, R11 + BNE RegTest1Error + CMP #12, R12 + BNE RegTest1Error + CMP #13, R13 + BNE RegTest1Error + CMP #14, R14 + BNE RegTest1Error + CMP #15, R15 + BNE RegTest1Error + + /* All comparisons passed, start a new itteratio of this loop. */ + BRA TestLoop1 + +RegTest1Error: + /* A compare failed, just loop here so the loop counter stops incrementing + - causing the check task to indicate the error. */ + BRA RegTest1Error +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of main.c. */ +_vRegTest2Implementation: + + ;/* Put a known value in the guard byte of the accumulators. */ + MOV.L #1H, R1 + MVTACGU R1, A0 + MOV.L #2H, R1 + MVTACGU R1, A1 + + /* Put a known value in each register. */ + MOV #10H, R1 + MOV #20H, R2 + MOV #30H, R3 + MOV #40H, R4 + MOV #50H, R5 + MOV #60H, R6 + MOV #70H, R7 + MOV #80H, R8 + MOV #90H, R9 + MOV #100H, R10 + MOV #110H, R11 + MOV #120H, R12 + MOV #130H, R13 + MOV #140H, R14 + MOV #150H, R15 + + ;/* Put a known value in the hi and low of the accumulators. */ + MVTACHI R1, A0 + MVTACLO R2, A0 + MVTACHI R3, A1 + MVTACLO R4, A1 + + /* Loop, checking each itteration that each register still contains the + expected value. */ +TestLoop2: + + /* Push the registers that are going to get clobbered. */ + PUSHM R14-R15 + + /* Increment the loop counter to show this task is still getting CPU time. */ + MOV #_ulRegTest2LoopCounter, R14 + MOV [ R14 ], R15 + ADD #1, R15 + MOV R15, [ R14 ] + + ;/* Check accumulators. */ + MVFACHI #0, A0, R15 + CMP #10H, R15 + BNE RegTest1Error + MVFACLO #0, A0, R15 + CMP #20H, R15 + BNE RegTest1Error + MVFACGU #0, A0, R15 + CMP #1H, R15 + BNE RegTest1Error + MVFACHI #0, A1, R15 + CMP #30H, R15 + BNE RegTest1Error + MVFACLO #0, A1, R15 + CMP #40H, R15 + BNE RegTest1Error + MVFACGU #0, A1, R15 + CMP #2H, R15 + BNE RegTest1Error + + /* Restore the clobbered registers. */ + POPM R14-R15 + + /* Now compare each register to ensure it still contains the value that was + set before this loop was entered. */ + CMP #10H, R1 + BNE RegTest2Error + CMP #20H, R2 + BNE RegTest2Error + CMP #30H, R3 + BNE RegTest2Error + CMP #40H, R4 + BNE RegTest2Error + CMP #50H, R5 + BNE RegTest2Error + CMP #60H, R6 + BNE RegTest2Error + CMP #70H, R7 + BNE RegTest2Error + CMP #80H, R8 + BNE RegTest2Error + CMP #90H, R9 + BNE RegTest2Error + CMP #100H, R10 + BNE RegTest2Error + CMP #110H, R11 + BNE RegTest2Error + CMP #120H, R12 + BNE RegTest2Error + CMP #130H, R13 + BNE RegTest2Error + CMP #140H, R14 + BNE RegTest2Error + CMP #150H, R15 + BNE RegTest2Error + + /* All comparisons passed, start a new itteratio of this loop. */ + BRA TestLoop2 + +RegTest2Error: + /* A compare failed, just loop here so the loop counter stops incrementing + - causing the check task to indicate the error. */ + BRA RegTest2Error + + + END diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/PriorityDefinitions.h b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/PriorityDefinitions.h new file mode 100644 index 000000000..1516a0753 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/PriorityDefinitions.h @@ -0,0 +1,86 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef PRIORITY_DEFINITIONS_H +#define PRIORITY_DEFINITIONS_H + +#ifndef __IASMRX__ + #error This file is only intended to be included from the FreeRTOS IAR port layer assembly file. +#endif + +/* The interrupt priority used by the kernel itself for the tick interrupt and +the pended interrupt. This would normally be the lowest priority. */ +#define configKERNEL_INTERRUPT_PRIORITY 1 + +/* The maximum interrupt priority from which FreeRTOS API calls can be made. +Interrupts that use a priority above this will not be effected by anything the +kernel is doing. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +#endif /* PRIORITY_DEFINITIONS_H */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_macrodriver.h b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_macrodriver.h index bd639b9ac..a099d50ff 100644 --- a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_macrodriver.h +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_macrodriver.h @@ -2,15 +2,15 @@ * DISCLAIMER * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. * No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all -* applicable laws, including copyright laws. +* applicable laws, including copyright laws. * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY * LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, * INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR * ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability -* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer * @@ -30,8 +30,14 @@ /*********************************************************************************************************************** Includes ***********************************************************************************************************************/ -#include "../iodefine.h" -//_RB_#include +#ifdef __ICCRX__ + #include + #include +#endif + +#ifdef __GNUC__ + #include "iodefine.h" +#endif /*********************************************************************************************************************** Macro definitions (Register bit) @@ -66,7 +72,7 @@ Macro definitions Typedef definitions ***********************************************************************************************************************/ #ifndef __TYPEDEF__ - #ifndef _STD_USING_INT_TYPES + #if !defined( _STD_USING_INT_TYPES ) && !defined( _STDINT ) #define _SYS_INT_TYPES_H #ifndef _STD_USING_BIT_TYPES #ifndef __int8_t_defined diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sci.c b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sci.c index 4b2528c33..db13525db 100644 --- a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sci.c +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sci.c @@ -2,15 +2,15 @@ * DISCLAIMER * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. * No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all -* applicable laws, including copyright laws. +* applicable laws, including copyright laws. * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY * LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, * INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR * ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability -* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer * @@ -78,11 +78,11 @@ void R_SCI7_Create(void) SCI7.SPMR.BYTE = _00_SCI_RTS | _00_SCI_CLOCK_NOT_INVERTED | _00_SCI_CLOCK_NOT_DELAYED; /* Set control registers */ - SCI7.SMR.BYTE = _00_SCI_CLOCK_PCLK | _00_SCI_STOP_1 | _00_SCI_PARITY_EVEN | _00_SCI_PARITY_DISABLE | + SCI7.SMR.BYTE = _00_SCI_CLOCK_PCLK | _00_SCI_STOP_1 | _00_SCI_PARITY_EVEN | _00_SCI_PARITY_DISABLE | _00_SCI_DATA_LENGTH_8 | _00_SCI_MULTI_PROCESSOR_DISABLE | _00_SCI_ASYNCHRONOUS_MODE; - SCI7.SCMR.BYTE = _00_SCI_SERIAL_MODE | _00_SCI_DATA_INVERT_NONE | _00_SCI_DATA_LSB_FIRST | + SCI7.SCMR.BYTE = _00_SCI_SERIAL_MODE | _00_SCI_DATA_INVERT_NONE | _00_SCI_DATA_LSB_FIRST | _10_SCI_DATA_LENGTH_8_OR_7 | _62_SCI_SCMR_DEFAULT; - SCI7.SEMR.BYTE = _80_SCI_FALLING_EDGE_START_BIT | _00_SCI_NOISE_FILTER_DISABLE | _10_SCI_8_BASE_CLOCK | + SCI7.SEMR.BYTE = _80_SCI_FALLING_EDGE_START_BIT | _00_SCI_NOISE_FILTER_DISABLE | _10_SCI_8_BASE_CLOCK | _00_SCI_BAUDRATE_SINGLE | _00_SCI_BIT_MODULATION_DISABLE; /* Set bitrate */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sci_user_iar.c b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sci_user_iar.c new file mode 100644 index 000000000..56dbc223a --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sci_user_iar.c @@ -0,0 +1,241 @@ +/*Adapted for IAR Embedded Workbench*/ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013, 2014 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_sci_user.c +* Version : Code Generator for RX64M V1.00.01.01 [09 May 2014] +* Device(s) : R5F571MLCxFC +* Tool-Chain : IAR Embedded Workbench +* Description : This file implements device driver for SCI module. +* Creation Date: 30/06/2014 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_sci.h" +/* Start user code for include. Do not edit comment generated here */ +#include "rskrx71mdef.h" +//_RB_#include "r_cg_cmt.h" +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +extern uint8_t * gp_sci7_tx_address; /* SCI7 send buffer address */ +extern uint16_t g_sci7_tx_count; /* SCI7 send data number */ +extern uint8_t * gp_sci7_rx_address; /* SCI7 receive buffer address */ +extern uint16_t g_sci7_rx_count; /* SCI7 receive data number */ +extern uint16_t g_sci7_rx_length; /* SCI7 receive data length */ +/* Start user code for global. Do not edit comment generated here */ + +/* Global used to receive a character from the PC terminal */ +uint8_t g_rx_char; + +/* Flag used to control transmission to PC terminal */ +volatile uint8_t g_tx_flag = FALSE; + +/* Flag used locally to detect transmission complete */ +static volatile uint8_t sci7_txdone; + +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: r_sci7_transmit_interrupt +* Description : None +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +#pragma vector=VECT(SCI7,TXI7) +__interrupt static void r_sci7_transmit_interrupt(void) +{ + if (g_sci7_tx_count > 0U) + { + SCI7.TDR = *gp_sci7_tx_address; + gp_sci7_tx_address++; + g_sci7_tx_count--; + } + else + { + SCI7.SCR.BIT.TIE = 0U; + SCI7.SCR.BIT.TEIE = 1U; + } +} + +/*********************************************************************************************************************** +* Function Name: r_sci7_transmitend_interrupt +* Description : This function is TEI7 interrupt service routine. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void r_sci7_transmitend_interrupt(void) +{ + MPC.P90PFS.BYTE = 0x00U; + PORT9.PMR.BYTE &= 0xFEU; + SCI7.SCR.BIT.TIE = 0U; + SCI7.SCR.BIT.TE = 0U; + SCI7.SCR.BIT.TEIE = 0U; + + r_sci7_callback_transmitend(); +} +/*********************************************************************************************************************** +* Function Name: r_sci7_receive_interrupt +* Description : None +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +#pragma vector=VECT(SCI7,RXI7) +__interrupt static void r_sci7_receive_interrupt(void) +{ + if (g_sci7_rx_length > g_sci7_rx_count) + { + *gp_sci7_rx_address = SCI7.RDR; + gp_sci7_rx_address++; + g_sci7_rx_count++; + + if (g_sci7_rx_length <= g_sci7_rx_count) + { + r_sci7_callback_receiveend(); + } + } +} +/*********************************************************************************************************************** +* Function Name: r_sci7_receiveerror_interrupt +* Description : This function is ERI7 interrupt service routine. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void r_sci7_receiveerror_interrupt(void) +{ + uint8_t err_type; + + r_sci7_callback_receiveerror(); + + /* Clear overrun, framing and parity error flags */ + err_type = SCI7.SSR.BYTE; + err_type &= 0xC7U; + err_type |= 0xC0U; + SCI7.SSR.BYTE = err_type; +} +/*********************************************************************************************************************** +* Function Name: r_sci7_callback_transmitend +* Description : This function is a callback function when SCI7 finishes transmission. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +static void r_sci7_callback_transmitend(void) +{ + /* Start user code. Do not edit comment generated here */ + sci7_txdone = TRUE; + /* End user code. Do not edit comment generated here */ +} +/*********************************************************************************************************************** +* Function Name: r_sci7_callback_receiveend +* Description : This function is a callback function when SCI7 finishes reception. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +static void r_sci7_callback_receiveend(void) +{ + /* Start user code. Do not edit comment generated here */ + /* Check the contents of g_rx_char */ + if ('z' == g_rx_char) + { + /* Stop the timer used to control transmission to PC terminal*/ +// R_CMT1_Stop(); + + /* Turn off LED0 and turn on LED1 to indicate serial transmission + inactive */ + LED0 = LED_OFF; + LED1 = LED_ON; + } + else + { + /* Start the timer used to control transmission to PC terminal*/ +//_RB_ R_CMT1_Start(); + + /* Turn on LED0 and turn off LED1 to indicate serial transmission + active */ + LED0 = LED_ON; + LED1 = LED_OFF; + } + + /* Set up SCI7 receive buffer again */ + R_SCI7_Serial_Receive((uint8_t *)&g_rx_char, 1); + /* End user code. Do not edit comment generated here */ +} +/*********************************************************************************************************************** +* Function Name: r_sci7_callback_receiveerror +* Description : This function is a callback function when SCI7 reception encounters error. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +static void r_sci7_callback_receiveerror(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/*********************************************************************************************************************** +* Function Name: R_SCI7_AsyncTransmit +* Description : This function sends SCI7 data and waits for the transmit end flag. +* Arguments : tx_buf - +* transfer buffer pointer +* tx_num - +* buffer size +* Return Value : status - +* MD_OK or MD_ARGERROR +***********************************************************************************************************************/ +MD_STATUS R_SCI7_AsyncTransmit (uint8_t * const tx_buf, const uint16_t tx_num) +{ + MD_STATUS status = MD_OK; + + /* clear the flag before initiating a new transmission */ + sci7_txdone = FALSE; + + /* Send the data using the API */ + status = R_SCI7_Serial_Send(tx_buf, tx_num); + + /* Wait for the transmit end flag */ + while (FALSE == sci7_txdone) + { + /* Wait */ + } + return (status); +} +/*********************************************************************************************************************** +* End of function R_SCI7_AsyncTransmit +***********************************************************************************************************************/ + + +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/main.c b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/main.c index 1a79fb545..75cfe547d 100644 --- a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/main.c +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/main.c @@ -248,6 +248,23 @@ const uint32_t ulEnableRegisterWrite = 0xA50BUL, ulDisableRegisterWrite = 0xA500 /* Reneable register protection. */ SYSTEM.PRCR.WORD = ulDisableRegisterWrite; } +/*-----------------------------------------------------------*/ + +#ifdef __ICCRX__ + + #include + /* Called from the C start up code when compiled with IAR. */ + #pragma diag_suppress = Pm011 + int __low_level_init(void) + #pragma diag_default = Pm011 + { + extern void R_Systeminit( void ); + + __disable_interrupt(); + R_Systeminit(); + return (int)(1U); + } +#endif /* __ICCRX__ */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/FreeRTOSConfig.h b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/FreeRTOSConfig.h index caa49c718..e7bad4fc4 100644 --- a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/FreeRTOSConfig.h @@ -88,7 +88,7 @@ #define configUSE_PREEMPTION 1 #define configUSE_IDLE_HOOK 1 #define configUSE_TICK_HOOK 1 -#define configCPU_CLOCK_HZ ( 120000000UL ) /*_RB_ guess*/ +#define configCPU_CLOCK_HZ ( 120000000UL ) /*_RB_ guess cg shows 240 and 120*/ #define configPERIPHERAL_CLOCK_HZ ( 60000000UL ) /*_RB_ guess*/ #define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) #define configMINIMAL_STACK_SIZE ( ( unsigned short ) 140 ) diff --git a/FreeRTOS/Source/portable/IAR/RX100/portmacro.h b/FreeRTOS/Source/portable/IAR/RX100/portmacro.h index 041be341e..50efc54ff 100644 --- a/FreeRTOS/Source/portable/IAR/RX100/portmacro.h +++ b/FreeRTOS/Source/portable/IAR/RX100/portmacro.h @@ -179,6 +179,11 @@ extern void vTaskExitCritical( void ); #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/* Prevent warnings of undefined behaviour: the order of volatile accesses is +undefined - all warnings have been manually checked and are not an issue, and +the warnings cannot be prevent by code changes without undesirable effects. */ +#pragma diag_suppress=Pa082 + #ifdef __cplusplus } #endif diff --git a/FreeRTOS/Source/portable/IAR/RXv2/port.c b/FreeRTOS/Source/portable/IAR/RXv2/port.c new file mode 100644 index 000000000..1ba4c92c5 --- /dev/null +++ b/FreeRTOS/Source/portable/IAR/RXv2/port.c @@ -0,0 +1,244 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the SH2A port. + *----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/* Hardware specifics. */ +#warning RX600v1 port included chip specific header file here. +#include + +/*-----------------------------------------------------------*/ + +/* Tasks should start with interrupts enabled and in Supervisor mode, therefore +PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) +#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) + +/*-----------------------------------------------------------*/ + +/* + * Function to start the first task executing - written in asm code as direct + * access to registers is required. + */ +extern void prvStartFirstTask( void ); + +/* + * The tick ISR handler. The peripheral used is configured by the application + * via a hook/callback function. + */ +__interrupt void vTickISR( void ); + +/*-----------------------------------------------------------*/ + +extern void *pxCurrentTCB; + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* R0 is not included as it is the stack pointer. */ + + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSW; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; + + /* When debugging it can be useful if every register is set to a known + value. Otherwise code space can be saved by just setting the registers + that need to be set. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack--; + *pxTopOfStack = 0xffffffff; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xeeeeeeee; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } + #else + { + pxTopOfStack -= 15; + } + #endif + + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_FPSW; + pxTopOfStack--; + *pxTopOfStack = 0x11111111; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x22222222; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x33333333; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x44444444; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x55555555; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x66666666; /* Accumulator 1. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vApplicationSetupTimerInterrupt( void ); + + /* Use pxCurrentTCB just so it does not get optimised away. */ + if( pxCurrentTCB != NULL ) + { + /* Call an application function to set up the timer that will generate the + tick interrupt. This way the application can decide which peripheral to + use. A demo application is provided to show a suitable example. */ + vApplicationSetupTimerInterrupt(); + + /* Enable the software interrupt. */ + _IEN( _ICU_SWINT ) = 1; + + /* Ensure the software interrupt is clear. */ + _IR( _ICU_SWINT ) = 0; + + /* Ensure the software interrupt is set to the kernel priority. */ + _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the first task. */ + prvStartFirstTask(); + } + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +#pragma vector = configTICK_VECTOR +__interrupt void vTickISR( void ) +{ + /* Re-enable interrupts. */ + __enable_interrupt(); + + /* Increment the tick, and perform any processing the new tick value + necessitates. */ + __set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + __set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY ); +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( pxCurrentTCB == NULL ); +} +/*-----------------------------------------------------------*/ + + + diff --git a/FreeRTOS/Source/portable/IAR/RXv2/port_asm.s b/FreeRTOS/Source/portable/IAR/RXv2/port_asm.s new file mode 100644 index 000000000..023ac1a91 --- /dev/null +++ b/FreeRTOS/Source/portable/IAR/RXv2/port_asm.s @@ -0,0 +1,242 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#include "PriorityDefinitions.h" + + PUBLIC _prvStartFirstTask + PUBLIC ___interrupt_27 + + EXTERN _pxCurrentTCB + EXTERN _vTaskSwitchContext + + RSEG CODE:CODE(4) + +_prvStartFirstTask: + + /* When starting the scheduler there is nothing that needs moving to the + interrupt stack because the function is not called from an interrupt. + Just ensure the current stack is the user stack. */ + SETPSW U + + /* Obtain the location of the stack associated with which ever task + pxCurrentTCB is currently pointing to. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [R15], R15 + MOV.L [R15], R0 + + /* Restore the registers from the stack of the task pointed to by + pxCurrentTCB. */ + POP R15 + + /* Accumulator low 32 bits. */ + MVTACLO R15, A0 + POP R15 + + /* Accumulator high 32 bits. */ + MVTACHI R15, A0 + POP R15 + + /* Accumulator guard. */ + MVTACGU R15, A0 + POP R15 + + /* Accumulator low 32 bits. */ + MVTACLO R15, A1 + POP R15 + + /* Accumulator high 32 bits. */ + MVTACHI R15, A1 + POP R15 + + /* Accumulator guard. */ + MVTACGU R15, A1 + POP R15 + + /* Floating point status word. */ + MVTC R15, FPSW + + /* R1 to R15 - R0 is not included as it is the SP. */ + POPM R1-R15 + + /* This pops the remaining registers. */ + RTE + NOP + NOP + +/*-----------------------------------------------------------*/ + +/* The software interrupt - overwrite the default 'weak' definition. */ +___interrupt_27: + + /* Re-enable interrupts. */ + SETPSW I + + /* Move the data that was automatically pushed onto the interrupt stack when + the interrupt occurred from the interrupt stack to the user stack. + + R15 is saved before it is clobbered. */ + PUSH.L R15 + + /* Read the user stack pointer. */ + MVFC USP, R15 + + /* Move the address down to the data being moved. */ + SUB #12, R15 + MVTC R15, USP + + /* Copy the data across, R15, then PC, then PSW. */ + MOV.L [ R0 ], [ R15 ] + MOV.L 4[ R0 ], 4[ R15 ] + MOV.L 8[ R0 ], 8[ R15 ] + + /* Move the interrupt stack pointer to its new correct position. */ + ADD #12, R0 + + /* All the rest of the registers are saved directly to the user stack. */ + SETPSW U + + /* Save the rest of the general registers (R15 has been saved already). */ + PUSHM R1-R14 + + /* Save the FPSW and accumulator. */ + MVFC FPSW, R15 + PUSH.L R15 + MVFACGU #0, A1, R15 + PUSH.L R15 + MVFACHI #0, A1, R15 + PUSH.L R15 + /* Low order word. */ + MVFACLO #0, A1, R15 + PUSH.L R15 + MVFACGU #0, A0, R15 + PUSH.L R15 + MVFACHI #0, A0, R15 + PUSH.L R15 + /* Low order word. */ + MVFACLO #0, A0, R15 + PUSH.L R15 + + /* Save the stack pointer to the TCB. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [ R15 ], R15 + MOV.L R0, [ R15 ] + + /* Ensure the interrupt mask is set to the syscall priority while the kernel + structures are being accessed. */ + MVTIPL #configMAX_SYSCALL_INTERRUPT_PRIORITY + + /* Select the next task to run. */ + BSR.A _vTaskSwitchContext + + /* Reset the interrupt mask as no more data structure access is required. */ + MVTIPL #configKERNEL_INTERRUPT_PRIORITY + + /* Load the stack pointer of the task that is now selected as the Running + state task from its TCB. */ + MOV.L #_pxCurrentTCB,R15 + MOV.L [ R15 ], R15 + MOV.L [ R15 ], R0 + + /* Restore the context of the new task. The PSW (Program Status Word) and + PC will be popped by the RTE instruction. */ + POP R15 + + /* Accumulator low 32 bits. */ + MVTACLO R15, A0 + POP R15 + + /* Accumulator high 32 bits. */ + MVTACHI R15, A0 + POP R15 + + /* Accumulator guard. */ + MVTACGU R15, A0 + POP R15 + + /* Accumulator low 32 bits. */ + MVTACLO R15, A1 + POP R15 + + /* Accumulator high 32 bits. */ + MVTACHI R15, A1 + POP R15 + + /* Accumulator guard. */ + MVTACGU R15, A1 + POP R15 + MVTC R15, FPSW + POPM R1-R15 + RTE + NOP + NOP + +/*-----------------------------------------------------------*/ + + END + diff --git a/FreeRTOS/Source/portable/IAR/RXv2/portmacro.h b/FreeRTOS/Source/portable/IAR/RXv2/portmacro.h new file mode 100644 index 000000000..bc8b55355 --- /dev/null +++ b/FreeRTOS/Source/portable/IAR/RXv2/portmacro.h @@ -0,0 +1,186 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions - these are a bit legacy and not really used now, other than +portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __no_operation() + +/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;" +where portITU_SWINTR is the location of the software interrupt register +(0x000872E0). Don't rely on the assembler to select a register, so instead +save and restore clobbered registers manually. */ +#define portYIELD() \ + __asm volatile \ + ( \ + "PUSH.L R10 \n" \ + "MOV.L #0x872E0, R10 \n" \ + "MOV.B #0x1, [R10] \n" \ + "MOV.L [R10], R10 \n" \ + "POP R10 \n" \ + ) + +#define portYIELD_FROM_ISR( x ) if( ( x ) != pdFALSE ) portYIELD() + +/* These macros should not be called directly, but through the +taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is +performed if configASSERT() is defined to ensure an assertion handler does not +inadvertently attempt to lower the IPL when the call to assert was triggered +because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY +when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API +functions are those that end in FromISR. FreeRTOS maintains a separate +interrupt API to ensure API function and interrupt entry is as fast and as +simple as possible. */ +#define portENABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) 0 ) +#ifdef configASSERT + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#else + #define portDISABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#endif + +/* Critical nesting counts are stored in the TCB. */ +#define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +/* As this port allows interrupt nesting... */ +#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +/* Prevent warnings of undefined behaviour: the order of volatile accesses is +undefined - all warnings have been manually checked and are not an issue, and +the warnings cannot be prevent by code changes without undesirable effects. */ +#pragma diag_suppress=Pa082 + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/FreeRTOS/Source/portable/MemMang/heap_4.c b/FreeRTOS/Source/portable/MemMang/heap_4.c index ce482d005..b89cadbc4 100644 --- a/FreeRTOS/Source/portable/MemMang/heap_4.c +++ b/FreeRTOS/Source/portable/MemMang/heap_4.c @@ -237,7 +237,7 @@ void *pvReturn = NULL; pxBlock->xBlockSize = xWantedSize; /* Insert the new block into the list of free blocks. */ - prvInsertBlockIntoFreeList( ( pxNewBlockLink ) ); + prvInsertBlockIntoFreeList( pxNewBlockLink ); } else { diff --git a/FreeRTOS/Source/tasks.c b/FreeRTOS/Source/tasks.c index 858337971..bd767423c 100644 --- a/FreeRTOS/Source/tasks.c +++ b/FreeRTOS/Source/tasks.c @@ -3581,7 +3581,6 @@ TCB_t *pxTCB; { portASSERT_IF_IN_ISR(); } - } else { -- 2.39.2