From c52c595f6e56f331ab750d0a11ab2552970108b7 Mon Sep 17 00:00:00 2001 From: gaurav-aws Date: Sat, 21 Dec 2019 00:04:04 +0000 Subject: [PATCH] Add IAR MPU project for STM32L475 Discovery Kit IoT Node git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2771 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- .../Demo/app_main.c | 43 - .../Demo/mpu_demo.c | 8 +- .../Projects/IAR/MPUDemo.ewd | 1419 +++++++++++++++++ .../Projects/IAR/MPUDemo.ewp | 1212 ++++++++++++++ .../Projects/IAR/MPUDemo.eww | 7 + .../Projects/IAR/memfault_handler.s | 43 + .../Projects/IAR/startup_stm32l475xx.s | 630 ++++++++ .../Projects/IAR/stm32l475xx_flash.icf | 96 ++ .../Projects/Keil/MPUDemo.uvoptx | 125 +- .../Projects/Keil/MPUDemo.uvprojx | 5 + .../Projects/Keil/memfault_handler.c | 69 + .../STM32Cube/Startup/memfault_handler.c | 48 + 12 files changed, 3593 insertions(+), 112 deletions(-) create mode 100644 FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/MPUDemo.ewd create mode 100644 FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/MPUDemo.ewp create mode 100644 FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/MPUDemo.eww create mode 100644 FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/memfault_handler.s create mode 100644 FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/startup_stm32l475xx.s create mode 100644 FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/stm32l475xx_flash.icf create mode 100644 FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/Keil/memfault_handler.c create mode 100644 FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/STM32Cube/Startup/memfault_handler.c diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Demo/app_main.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Demo/app_main.c index 84f5c97ad..81d6f5f69 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Demo/app_main.c +++ b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Demo/app_main.c @@ -34,33 +34,6 @@ /* Demo includes. */ #include "mpu_demo.h" -#if defined( __ARMCC_VERSION ) - extern uint32_t Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Base; - extern uint32_t Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Limit; - - /* Memory map needed for MPU setup. Must must match the one defined in - * the scatter-loading file (MPUDemo.sct). */ - const uint32_t * __FLASH_segment_start__ = ( uint32_t * ) 0x08000000; - const uint32_t * __FLASH_segment_end__ = ( uint32_t * ) 0x08100000; - const uint32_t * __SRAM_segment_start__ = ( uint32_t * ) 0x20000000; - const uint32_t * __SRAM_segment_end__ = ( uint32_t * ) 0x20018000; - - const uint32_t * __privileged_functions_start__ = ( uint32_t * ) 0x08000000; - const uint32_t * __privileged_functions_end__ = ( uint32_t * ) 0x08008000; - const uint32_t * __privileged_data_start__ = ( uint32_t * ) 0x20000000; - const uint32_t * __privileged_data_end__ = ( uint32_t * ) 0x20000400; - - const uint32_t * __syscalls_flash_start__ = ( uint32_t * ) &( Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Base ); - const uint32_t * __syscalls_flash_end__ = ( uint32_t * ) &( Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Limit ); -#endif /* #if defined( __ARMCC_VERSION ) */ -/*-----------------------------------------------------------*/ - -/** - * @brief Mem fault handler. - */ -void MemManage_Handler( void ) __attribute__ (( naked )); -/*-----------------------------------------------------------*/ - void app_main( void ) { /* Start the MPU demo. */ @@ -142,19 +115,3 @@ static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; } /*-----------------------------------------------------------*/ - -void MemManage_Handler( void ) -{ - __asm volatile - ( - " tst lr, #4 \n" - " ite eq \n" - " mrseq r0, msp \n" - " mrsne r0, psp \n" - " ldr r1, handler_address_const \n" - " bx r1 \n" - " \n" - " handler_address_const: .word vHandleMemoryFault \n" - ); -} -/*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Demo/mpu_demo.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Demo/mpu_demo.c index 9f4c12a35..039439a91 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Demo/mpu_demo.c +++ b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Demo/mpu_demo.c @@ -60,7 +60,7 @@ static uint8_t ucSharedMemory[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( SH * @note We are declaring a region of 32 bytes even though we need only one. * The reason is that the smallest supported MPU region size is 32 bytes. */ -static uint8_t ucROTaskFaultTracker[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) ) = { 0 }; +static volatile uint8_t ucROTaskFaultTracker[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) ) = { 0 }; /*-----------------------------------------------------------*/ /** @@ -209,9 +209,9 @@ TaskParameters_t xROAccessTaskParameters = .uxPriority = tskIDLE_PRIORITY, .puxStackBuffer = xROAccessTaskStack, .xRegions = { - { ucSharedMemory, SHARED_MEMORY_SIZE, portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY | portMPU_REGION_EXECUTE_NEVER }, - { ucROTaskFaultTracker, SHARED_MEMORY_SIZE, portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER}, - { 0, 0, 0 }, + { ucSharedMemory, SHARED_MEMORY_SIZE, portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY | portMPU_REGION_EXECUTE_NEVER }, + { ( void * ) ucROTaskFaultTracker, SHARED_MEMORY_SIZE, portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER }, + { 0, 0, 0 }, } }; TaskParameters_t xRWAccessTaskParameters = diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/MPUDemo.ewd b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/MPUDemo.ewd new file mode 100644 index 000000000..f9ec12dc6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/MPUDemo.ewd @@ -0,0 +1,1419 @@ + + + 3 + + MPUDemo + + ARM + + 1 + + C-SPY + 2 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 1 + + + + + + + + STLINK_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/MPUDemo.ewp b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/MPUDemo.ewp new file mode 100644 index 000000000..73440282a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/MPUDemo.ewp @@ -0,0 +1,1212 @@ + + + 3 + + MPUDemo + + ARM + + 1 + + General + 3 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 34 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 21 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Config + + $PROJ_DIR$\..\..\Config\FreeRTOSConfig.h + + + + Demo + + $PROJ_DIR$\..\..\Demo\app_main.c + + + $PROJ_DIR$\..\..\Demo\app_main.h + + + $PROJ_DIR$\..\..\Demo\mpu_demo.c + + + $PROJ_DIR$\..\..\Demo\mpu_demo.h + + + + FreeRTOS + + $PROJ_DIR$\..\..\..\..\Source\croutine.c + + + $PROJ_DIR$\..\..\..\..\Source\event_groups.c + + + $PROJ_DIR$\..\..\..\..\Source\portable\MemMang\heap_4.c + + + $PROJ_DIR$\..\..\..\..\Source\list.c + + + $PROJ_DIR$\..\..\..\..\Source\portable\Common\mpu_wrappers.c + + + $PROJ_DIR$\..\..\..\..\Source\portable\IAR\ARM_CM4F_MPU\port.c + + + $PROJ_DIR$\..\..\..\..\Source\portable\IAR\ARM_CM4F_MPU\portasm.s + + + $PROJ_DIR$\..\..\..\..\Source\portable\IAR\ARM_CM4F_MPU\portmacro.h + + + $PROJ_DIR$\..\..\..\..\Source\queue.c + + + $PROJ_DIR$\..\..\..\..\Source\stream_buffer.c + + + $PROJ_DIR$\..\..\..\..\Source\tasks.c + + + $PROJ_DIR$\..\..\..\..\Source\timers.c + + + + ST_Code + + Core + + $PROJ_DIR$\..\..\ST_Code\Core\Src\main.c + + + $PROJ_DIR$\..\..\ST_Code\Core\Src\stm32l4xx_hal_msp.c + + + $PROJ_DIR$\..\..\ST_Code\Core\Src\stm32l4xx_hal_timebase_tim.c + + + $PROJ_DIR$\..\..\ST_Code\Core\Src\stm32l4xx_it.c + + + $PROJ_DIR$\..\..\ST_Code\Core\Src\system_stm32l4xx.c + + + + STM32L4xx_HAL_Driver + + $PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c + + + $PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c + + + $PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dfsdm.c + + + $PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c + + + $PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c + + + $PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_exti.c + + + $PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash.c + + + $PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ex.c + + + $PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ramfunc.c + + + $PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c + + + $PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c.c + + + $PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c_ex.c + + + $PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pcd.c + + + $PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pcd_ex.c + + + $PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c + + + $PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c + + + $PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_qspi.c + + + $PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c + + + $PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c + + + $PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi.c + + + $PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi_ex.c + + + $PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim.c + + + $PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim_ex.c + + + $PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart.c + + + $PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart_ex.c + + + $PROJ_DIR$\..\..\ST_Code\Drivers\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_usb.c + + + + + Startup + + $PROJ_DIR$\memfault_handler.s + + + $PROJ_DIR$\startup_stm32l475xx.s + + + diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/MPUDemo.eww b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/MPUDemo.eww new file mode 100644 index 000000000..5fcd4a02f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/MPUDemo.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\MPUDemo.ewp + + + diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/memfault_handler.s b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/memfault_handler.s new file mode 100644 index 000000000..4e7b3afd9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/memfault_handler.s @@ -0,0 +1,43 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + EXTERN vHandleMemoryFault + PUBLIC MemManage_Handler + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +MemManage_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + b vHandleMemoryFault +/*-----------------------------------------------------------*/ + + END diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/startup_stm32l475xx.s b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/startup_stm32l475xx.s new file mode 100644 index 000000000..ca1cd67de --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/startup_stm32l475xx.s @@ -0,0 +1,630 @@ +;/********************* COPYRIGHT(c) 2017 STMicroelectronics ******************** +;* File Name : startup_stm32l475xx.s +;* Author : MCD Application Team +;* Description : STM32L475xx Ultra Low Power Devices vector +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1, ADC2 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt + DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt + DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt + DCD COMP_IRQHandler ; COMP Interrupt + DCD LPTIM1_IRQHandler ; LP TIM1 interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 interrupt + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD LPUART1_IRQHandler ; LP UART 1 interrupt + DCD QUADSPI_IRQHandler ; Quad SPI global interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt + DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface global interrupt + DCD TSC_IRQHandler ; Touch Sense Controller global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG global interrupt + DCD FPU_IRQHandler ; FPU + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_PVM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_PVM_IRQHandler + B PVD_PVM_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_TIM15_IRQHandler + B TIM1_BRK_TIM15_IRQHandler + + PUBWEAK TIM1_UP_TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_TIM16_IRQHandler + B TIM1_UP_TIM16_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_TIM17_IRQHandler + B TIM1_TRG_COM_TIM17_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK DFSDM1_FLT3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT3_IRQHandler + B DFSDM1_FLT3_IRQHandler + + PUBWEAK TIM8_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_IRQHandler + B TIM8_BRK_IRQHandler + + PUBWEAK TIM8_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_IRQHandler + B TIM8_UP_IRQHandler + + PUBWEAK TIM8_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_IRQHandler + B TIM8_TRG_COM_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK ADC3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC3_IRQHandler + B ADC3_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SDMMC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC1_IRQHandler + B SDMMC1_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + PUBWEAK DFSDM1_FLT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT0_IRQHandler + B DFSDM1_FLT0_IRQHandler + + PUBWEAK DFSDM1_FLT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT1_IRQHandler + B DFSDM1_FLT1_IRQHandler + + PUBWEAK DFSDM1_FLT2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT2_IRQHandler + B DFSDM1_FLT2_IRQHandler + + PUBWEAK COMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP_IRQHandler + B COMP_IRQHandler + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + PUBWEAK LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler + B LPTIM2_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel6_IRQHandler + B DMA2_Channel6_IRQHandler + + PUBWEAK DMA2_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel7_IRQHandler + B DMA2_Channel7_IRQHandler + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + PUBWEAK QUADSPI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK SAI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI2_IRQHandler + B SAI2_IRQHandler + + PUBWEAK SWPMI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SWPMI1_IRQHandler + B SWPMI1_IRQHandler + + PUBWEAK TSC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TSC_IRQHandler + B TSC_IRQHandler + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler + B RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/stm32l475xx_flash.icf b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/stm32l475xx_flash.icf new file mode 100644 index 000000000..90a1e1e78 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/IAR/stm32l475xx_flash.icf @@ -0,0 +1,96 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20017FFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + +/* Flash Organization + * 1. Privileged Code: + * Start : 0x08000000 + * End : 0x08007FFF + * Size : 32 Kbytes + * 2. System calls: + * Start : 0x08008000 + * End : 0x08008FFF + * Size : 4 Kbytes + * 3. Unprivileged Code: + * Start : 0x08009000 + * End : 0x080FFFFF + * Size : 988 Kbytes + */ +define symbol __reigon_ROM_privileged_start__ = __ICFEDIT_region_ROM_start__; +define symbol __reigon_ROM_privileged_end__ = 0x08007FFF; +define symbol __reigon_ROM_system_calls_start__ = 0x08008000; +define symbol __reigon_ROM_system_calls_end__ = 0x08008FFF; +define symbol __reigon_ROM_unprivileged_start__ = 0x08009000; +define symbol __reigon_ROM_unprivileged_end__ = __ICFEDIT_region_ROM_end__; + +/* RAM Organization + * 1. Privileged Data: + * Start : 0x20000000 + * End : 0x200003FF + * Size : 1 Kbytes + * 2. Unprivileged Data: + * Start : 0x20000400 + * End : 0x20017FFF + * Size : 95 Kbytes + */ +define symbol __region_RAM_privileged_start__ = __ICFEDIT_region_RAM_start__; +define symbol __region_RAM_privileged_end__ = 0x200003FF; +define symbol __region_RAM_unprivileged_start__ = 0x20000400; +define symbol __region_RAM_unprivileged_end__ = __ICFEDIT_region_RAM_end__; +define symbol __region_SRAM2_start__ = 0x10000000; +define symbol __region_SRAM2_end__ = 0x10007FFF; + +/* Memory regions. */ +define memory mem with size = 4G; +define region ROM_region_privileged = mem:[from __reigon_ROM_privileged_start__ to __reigon_ROM_privileged_end__]; +define region ROM_region_system_calls = mem:[from __reigon_ROM_system_calls_start__ to __reigon_ROM_system_calls_end__]; +define region ROM_region_unprivileged = mem:[from __reigon_ROM_unprivileged_start__ to __reigon_ROM_unprivileged_end__]; +define region RAM_region_privileged = mem:[from __region_RAM_privileged_start__ to __region_RAM_privileged_end__]; +define region RAM_region_unprivileged = mem:[from __region_RAM_unprivileged_start__ to __region_RAM_unprivileged_end__]; +define region SRAM2_region = mem:[from __region_SRAM2_start__ to __region_SRAM2_end__]; + +/* Stack and Heap. */ +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +/* Initialization. */ +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +/* Exported symbols. */ +define exported symbol __FLASH_segment_start__ = __ICFEDIT_region_ROM_start__; +define exported symbol __FLASH_segment_end__ = __ICFEDIT_region_ROM_end__; +define exported symbol __SRAM_segment_start__ = __ICFEDIT_region_RAM_start__; +define exported symbol __SRAM_segment_end__ = __ICFEDIT_region_RAM_end__; + +define exported symbol __privileged_functions_start__ = __reigon_ROM_privileged_start__; +define exported symbol __privileged_functions_end__ = __reigon_ROM_privileged_end__; +define exported symbol __privileged_data_start__ = __region_RAM_privileged_start__; +define exported symbol __privileged_data_end__ = __region_RAM_privileged_end__; + +define exported symbol __syscalls_flash_start__ = __reigon_ROM_system_calls_start__; +define exported symbol __syscalls_flash_end__ = __reigon_ROM_system_calls_end__; + +/* Placements. */ +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region_privileged { readonly section privileged_functions }; +place in ROM_region_system_calls { readonly section freertos_system_calls }; +place in ROM_region_unprivileged { readonly }; + +place in RAM_region_privileged { readwrite section privileged_data }; +place in RAM_region_unprivileged { readwrite, + block CSTACK, block HEAP }; +place in SRAM2_region { }; diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/Keil/MPUDemo.uvoptx b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/Keil/MPUDemo.uvoptx index 7ee260522..6cdaf39cd 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/Keil/MPUDemo.uvoptx +++ b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/Keil/MPUDemo.uvoptx @@ -148,24 +148,7 @@ -U-O142 -O2254 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(2BA01477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32L475VGTx$CMSIS\Flash\STM32L4xx_1024.FLM) - - - 0 - 0 - 112 - 1 -
134274678
- 0 - 0 - 0 - 0 - 0 - 1 - ../../Demo/mpu_demo.c - - \\MPUDemo\../../Demo/mpu_demo.c\112 - - + 0 @@ -236,6 +219,18 @@ 0 0 + + 1 + 2 + 1 + 0 + 0 + 0 + .\memfault_handler.c + memfault_handler.c + 0 + 0 + @@ -246,7 +241,7 @@ 0 2 - 2 + 3 1 0 0 @@ -258,7 +253,7 @@ 2 - 3 + 4 1 0 0 @@ -270,7 +265,7 @@ 2 - 4 + 5 1 0 0 @@ -282,7 +277,7 @@ 2 - 5 + 6 1 0 0 @@ -294,7 +289,7 @@ 2 - 6 + 7 1 0 0 @@ -306,7 +301,7 @@ 2 - 7 + 8 1 0 0 @@ -318,7 +313,7 @@ 2 - 8 + 9 1 0 0 @@ -330,7 +325,7 @@ 2 - 9 + 10 1 0 0 @@ -342,7 +337,7 @@ 2 - 10 + 11 1 0 0 @@ -354,7 +349,7 @@ 2 - 11 + 12 5 0 0 @@ -366,7 +361,7 @@ 2 - 12 + 13 1 0 0 @@ -386,7 +381,7 @@ 0 3 - 13 + 14 5 0 0 @@ -406,7 +401,7 @@ 0 4 - 14 + 15 1 0 0 @@ -418,7 +413,7 @@ 4 - 15 + 16 5 0 0 @@ -430,7 +425,7 @@ 4 - 16 + 17 1 0 0 @@ -442,7 +437,7 @@ 4 - 17 + 18 5 0 0 @@ -462,7 +457,7 @@ 0 5 - 18 + 19 1 0 0 @@ -474,7 +469,7 @@ 5 - 19 + 20 1 0 0 @@ -486,7 +481,7 @@ 5 - 20 + 21 1 0 0 @@ -498,7 +493,7 @@ 5 - 21 + 22 1 0 0 @@ -518,7 +513,7 @@ 0 6 - 22 + 23 1 0 0 @@ -530,7 +525,7 @@ 6 - 23 + 24 1 0 0 @@ -542,7 +537,7 @@ 6 - 24 + 25 1 0 0 @@ -554,7 +549,7 @@ 6 - 25 + 26 1 0 0 @@ -566,7 +561,7 @@ 6 - 26 + 27 1 0 0 @@ -578,7 +573,7 @@ 6 - 27 + 28 1 0 0 @@ -590,7 +585,7 @@ 6 - 28 + 29 1 0 0 @@ -602,7 +597,7 @@ 6 - 29 + 30 1 0 0 @@ -614,7 +609,7 @@ 6 - 30 + 31 1 0 0 @@ -626,7 +621,7 @@ 6 - 31 + 32 1 0 0 @@ -638,7 +633,7 @@ 6 - 32 + 33 1 0 0 @@ -650,7 +645,7 @@ 6 - 33 + 34 1 0 0 @@ -662,7 +657,7 @@ 6 - 34 + 35 1 0 0 @@ -674,7 +669,7 @@ 6 - 35 + 36 1 0 0 @@ -686,7 +681,7 @@ 6 - 36 + 37 1 0 0 @@ -698,7 +693,7 @@ 6 - 37 + 38 1 0 0 @@ -710,7 +705,7 @@ 6 - 38 + 39 1 0 0 @@ -722,7 +717,7 @@ 6 - 39 + 40 1 0 0 @@ -734,7 +729,7 @@ 6 - 40 + 41 1 0 0 @@ -746,7 +741,7 @@ 6 - 41 + 42 1 0 0 @@ -758,7 +753,7 @@ 6 - 42 + 43 1 0 0 @@ -770,7 +765,7 @@ 6 - 43 + 44 1 0 0 @@ -782,7 +777,7 @@ 6 - 44 + 45 1 0 0 @@ -794,7 +789,7 @@ 6 - 45 + 46 1 0 0 @@ -806,7 +801,7 @@ 6 - 46 + 47 1 0 0 @@ -818,7 +813,7 @@ 6 - 47 + 48 1 0 0 @@ -838,7 +833,7 @@ 0 7 - 48 + 49 1 0 0 diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/Keil/MPUDemo.uvprojx b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/Keil/MPUDemo.uvprojx index 3e8a9e390..b69de9de1 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/Keil/MPUDemo.uvprojx +++ b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/Keil/MPUDemo.uvprojx @@ -387,6 +387,11 @@ 2 startup_stm32l475xx.s + + memfault_handler.c + 1 + .\memfault_handler.c + diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/Keil/memfault_handler.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/Keil/memfault_handler.c new file mode 100644 index 000000000..59efcd77f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/Keil/memfault_handler.c @@ -0,0 +1,69 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#include + +extern uint32_t Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Base; +extern uint32_t Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Limit; + +/* Memory map needed for MPU setup. Must must match the one defined in + * the scatter-loading file (MPUDemo.sct). */ +const uint32_t * __FLASH_segment_start__ = ( uint32_t * ) 0x08000000; +const uint32_t * __FLASH_segment_end__ = ( uint32_t * ) 0x08100000; +const uint32_t * __SRAM_segment_start__ = ( uint32_t * ) 0x20000000; +const uint32_t * __SRAM_segment_end__ = ( uint32_t * ) 0x20018000; + +const uint32_t * __privileged_functions_start__ = ( uint32_t * ) 0x08000000; +const uint32_t * __privileged_functions_end__ = ( uint32_t * ) 0x08008000; +const uint32_t * __privileged_data_start__ = ( uint32_t * ) 0x20000000; +const uint32_t * __privileged_data_end__ = ( uint32_t * ) 0x20000400; + +const uint32_t * __syscalls_flash_start__ = ( uint32_t * ) &( Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Base ); +const uint32_t * __syscalls_flash_end__ = ( uint32_t * ) &( Image$$ER_IROM_FREERTOS_SYSTEM_CALLS$$Limit ); +/*-----------------------------------------------------------*/ + +/** + * @brief Mem fault handler. + */ +void MemManage_Handler( void ) __attribute__ (( naked )); +/*-----------------------------------------------------------*/ + +void MemManage_Handler( void ) +{ + __asm volatile + ( + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + " ldr r1, handler_address_const \n" + " bx r1 \n" + " \n" + " handler_address_const: .word vHandleMemoryFault \n" + ); +} +/*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/STM32Cube/Startup/memfault_handler.c b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/STM32Cube/Startup/memfault_handler.c new file mode 100644 index 000000000..f0e1b92e3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube/Projects/STM32Cube/Startup/memfault_handler.c @@ -0,0 +1,48 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/** + * @brief Mem fault handler. + */ +void MemManage_Handler( void ) __attribute__ (( naked )); +/*-----------------------------------------------------------*/ + +void MemManage_Handler( void ) +{ + __asm volatile + ( + " tst lr, #4 \n" + " ite eq \n" + " mrseq r0, msp \n" + " mrsne r0, psp \n" + " ldr r1, handler_address_const \n" + " bx r1 \n" + " \n" + " handler_address_const: .word vHandleMemoryFault \n" + ); +} +/*-----------------------------------------------------------*/ -- 2.39.2