git.sur5r.net Git - groeck-it87/blob - it87.c

   1 /*
   2  *  it87.c - Part of lm_sensors, Linux kernel modules for hardware
   3  *           monitoring.
   4  *
   5  *  The IT8705F is an LPC-based Super I/O part that contains UARTs, a
   6  *  parallel port, an IR port, a MIDI port, a floppy controller, etc., in
   7  *  addition to an Environment Controller (Enhanced Hardware Monitor and
   8  *  Fan Controller)
   9  *
  10  *  This driver supports only the Environment Controller in the IT8705F and
  11  *  similar parts.  The other devices are supported by different drivers.
  12  *
  13  *  Supports: IT8603E  Super I/O chip w/LPC interface
  14  *            IT8606E  Super I/O chip w/LPC interface
  15  *            IT8607E  Super I/O chip w/LPC interface
  16  *            IT8613E  Super I/O chip w/LPC interface
  17  *            IT8620E  Super I/O chip w/LPC interface
  18  *            IT8622E  Super I/O chip w/LPC interface
  19  *            IT8623E  Super I/O chip w/LPC interface
  20  *            IT8625E  Super I/O chip w/LPC interface
  21  *            IT8628E  Super I/O chip w/LPC interface
  22  *            IT8655E  Super I/O chip w/LPC interface
  23  *            IT8665E  Super I/O chip w/LPC interface
  24  *            IT8686E  Super I/O chip w/LPC interface
  25  *            IT8705F  Super I/O chip w/LPC interface
  26  *            IT8712F  Super I/O chip w/LPC interface
  27  *            IT8716F  Super I/O chip w/LPC interface
  28  *            IT8718F  Super I/O chip w/LPC interface
  29  *            IT8720F  Super I/O chip w/LPC interface
  30  *            IT8721F  Super I/O chip w/LPC interface
  31  *            IT8726F  Super I/O chip w/LPC interface
  32  *            IT8728F  Super I/O chip w/LPC interface
  33  *            IT8732F  Super I/O chip w/LPC interface
  34  *            IT8736F  Super I/O chip w/LPC interface
  35  *            IT8738E  Super I/O chip w/LPC interface
  36  *            IT8758E  Super I/O chip w/LPC interface
  37  *            IT8771E  Super I/O chip w/LPC interface
  38  *            IT8772E  Super I/O chip w/LPC interface
  39  *            IT8781F  Super I/O chip w/LPC interface
  40  *            IT8782F  Super I/O chip w/LPC interface
  41  *            IT8783E/F Super I/O chip w/LPC interface
  42  *            IT8786E  Super I/O chip w/LPC interface
  43  *            IT8790E  Super I/O chip w/LPC interface
  44  *            IT8792E  Super I/O chip w/LPC interface
  45  *            Sis950   A clone of the IT8705F
  46  *
  47  *  Copyright (C) 2001 Chris Gauthron
  48  *  Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
  49  *
  50  *  This program is free software; you can redistribute it and/or modify
  51  *  it under the terms of the GNU General Public License as published by
  52  *  the Free Software Foundation; either version 2 of the License, or
  53  *  (at your option) any later version.
  54  *
  55  *  This program is distributed in the hope that it will be useful,
  56  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  57  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  58  *  GNU General Public License for more details.
  59  */
  60
  61 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  62
  63 #include <linux/bitops.h>
  64 #include <linux/module.h>
  65 #include <linux/init.h>
  66 #include <linux/slab.h>
  67 #include <linux/jiffies.h>
  68 #include <linux/platform_device.h>
  69 #include <linux/hwmon.h>
  70 #include <linux/hwmon-sysfs.h>
  71 #include <linux/hwmon-vid.h>
  72 #include <linux/err.h>
  73 #include <linux/mutex.h>
  74 #include <linux/sysfs.h>
  75 #include <linux/string.h>
  76 #include <linux/dmi.h>
  77 #include <linux/acpi.h>
  78 #include <linux/io.h>
  79 #include "compat.h"
  80
  81 #ifndef IT87_DRIVER_VERSION
  82 #define IT87_DRIVER_VERSION     "<not provided>"
  83 #endif
  84
  85 #define DRVNAME "it87"
  86
  87 enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
  88              it8736, it8738,
  89              it8771, it8772, it8781, it8782, it8783, it8786, it8790,
  90              it8792, it8603, it8606, it8607, it8613, it8620, it8622, it8625,
  91              it8628, it8655, it8665, it8686 };
  92
  93 static unsigned short force_id;
  94 module_param(force_id, ushort, 0000);
  95 MODULE_PARM_DESC(force_id, "Override the detected device ID");
  96
  97 static bool ignore_resource_conflict;
  98 module_param(ignore_resource_conflict, bool, 0000);
  99 MODULE_PARM_DESC(ignore_resource_conflict, "Ignore ACPI resource conflict");
 100
 101 static bool mmio;
 102 module_param(mmio, bool, 0000);
 103 MODULE_PARM_DESC(mmio, "Use MMIO if available");
 104
 105 static struct platform_device *it87_pdev[2];
 106
 107 #define REG_2E  0x2e    /* The register to read/write */
 108 #define REG_4E  0x4e    /* Secondary register to read/write */
 109
 110 #define DEV     0x07    /* Register: Logical device select */
 111 #define PME     0x04    /* The device with the fan registers in it */
 112
 113 /* The device with the IT8718F/IT8720F VID value in it */
 114 #define GPIO    0x07
 115
 116 #define DEVID   0x20    /* Register: Device ID */
 117 #define DEVREV  0x22    /* Register: Device Revision */
 118
 119 static inline void __superio_enter(int ioreg)
 120 {
 121         outb(0x87, ioreg);
 122         outb(0x01, ioreg);
 123         outb(0x55, ioreg);
 124         outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
 125 }
 126
 127 static inline int superio_inb(int ioreg, int reg)
 128 {
 129         int val;
 130
 131         outb(reg, ioreg);
 132         val = inb(ioreg + 1);
 133
 134         return val;
 135 }
 136
 137 static inline void superio_outb(int ioreg, int reg, int val)
 138 {
 139         outb(reg, ioreg);
 140         outb(val, ioreg + 1);
 141 }
 142
 143 static int superio_inw(int ioreg, int reg)
 144 {
 145         return (superio_inb(ioreg, reg) << 8) | superio_inb(ioreg, reg + 1);
 146 }
 147
 148 static inline void superio_select(int ioreg, int ldn)
 149 {
 150         outb(DEV, ioreg);
 151         outb(ldn, ioreg + 1);
 152 }
 153
 154 static inline int superio_enter(int ioreg)
 155 {
 156         /*
 157          * Try to reserve ioreg and ioreg + 1 for exclusive access.
 158          */
 159         if (!request_muxed_region(ioreg, 2, DRVNAME))
 160                 return -EBUSY;
 161
 162         __superio_enter(ioreg);
 163         return 0;
 164 }
 165
 166 static inline void superio_exit(int ioreg, bool doexit)
 167 {
 168         if (doexit) {
 169                 outb(0x02, ioreg);
 170                 outb(0x02, ioreg + 1);
 171         }
 172         release_region(ioreg, 2);
 173 }
 174
 175 /* Logical device 4 registers */
 176 #define IT8712F_DEVID 0x8712
 177 #define IT8705F_DEVID 0x8705
 178 #define IT8716F_DEVID 0x8716
 179 #define IT8718F_DEVID 0x8718
 180 #define IT8720F_DEVID 0x8720
 181 #define IT8721F_DEVID 0x8721
 182 #define IT8726F_DEVID 0x8726
 183 #define IT8728F_DEVID 0x8728
 184 #define IT8732F_DEVID 0x8732
 185 #define IT8736F_DEVID 0x8736
 186 #define IT8738E_DEVID 0x8738
 187 #define IT8792E_DEVID 0x8733
 188 #define IT8771E_DEVID 0x8771
 189 #define IT8772E_DEVID 0x8772
 190 #define IT8781F_DEVID 0x8781
 191 #define IT8782F_DEVID 0x8782
 192 #define IT8783E_DEVID 0x8783
 193 #define IT8786E_DEVID 0x8786
 194 #define IT8790E_DEVID 0x8790
 195 #define IT8603E_DEVID 0x8603
 196 #define IT8606E_DEVID 0x8606
 197 #define IT8607E_DEVID 0x8607
 198 #define IT8613E_DEVID 0x8613
 199 #define IT8620E_DEVID 0x8620
 200 #define IT8622E_DEVID 0x8622
 201 #define IT8623E_DEVID 0x8623
 202 #define IT8625E_DEVID 0x8625
 203 #define IT8628E_DEVID 0x8628
 204 #define IT8655E_DEVID 0x8655
 205 #define IT8665E_DEVID 0x8665
 206 #define IT8686E_DEVID 0x8686
 207
 208 /* Logical device 4 (Environmental Monitor) registers */
 209 #define IT87_ACT_REG            0x30
 210 #define IT87_BASE_REG           0x60
 211 #define IT87_SPECIAL_CFG_REG    0xf3    /* special configuration register */
 212
 213 /* Global configuration registers (IT8712F and later) */
 214 #define IT87_EC_HWM_MIO_REG     0x24    /* MMIO configuration register */
 215 #define IT87_SIO_GPIO1_REG      0x25
 216 #define IT87_SIO_GPIO2_REG      0x26
 217 #define IT87_SIO_GPIO3_REG      0x27
 218 #define IT87_SIO_GPIO4_REG      0x28
 219 #define IT87_SIO_GPIO5_REG      0x29
 220 #define IT87_SIO_GPIO9_REG      0xd3
 221 #define IT87_SIO_PINX1_REG      0x2a    /* Pin selection */
 222 #define IT87_SIO_PINX2_REG      0x2c    /* Pin selection */
 223 #define IT87_SIO_PINX4_REG      0x2d    /* Pin selection */
 224
 225 /* Logical device 7 (GPIO) registers (IT8712F and later) */
 226 #define IT87_SIO_SPI_REG        0xef    /* SPI function pin select */
 227 #define IT87_SIO_VID_REG        0xfc    /* VID value */
 228 #define IT87_SIO_BEEP_PIN_REG   0xf6    /* Beep pin mapping */
 229
 230 /* Update battery voltage after every reading if true */
 231 static bool update_vbat;
 232
 233 /* Not all BIOSes properly configure the PWM registers */
 234 static bool fix_pwm_polarity;
 235
 236 /* Many IT87 constants specified below */
 237
 238 /* Length of ISA address segment */
 239 #define IT87_EXTENT 8
 240
 241 /* Length of ISA address segment for Environmental Controller */
 242 #define IT87_EC_EXTENT 2
 243
 244 /* Offset of EC registers from ISA base address */
 245 #define IT87_EC_OFFSET 5
 246
 247 /* Where are the ISA address/data registers relative to the EC base address */
 248 #define IT87_ADDR_REG_OFFSET 0
 249 #define IT87_DATA_REG_OFFSET 1
 250
 251 /*----- The IT87 registers -----*/
 252
 253 #define IT87_REG_CONFIG         0x00
 254
 255 #define IT87_REG_ALARM1         0x01
 256 #define IT87_REG_ALARM2         0x02
 257 #define IT87_REG_ALARM3         0x03
 258
 259 #define IT87_REG_BANK           0x06
 260
 261 /*
 262  * The IT8718F and IT8720F have the VID value in a different register, in
 263  * Super-I/O configuration space.
 264  */
 265 #define IT87_REG_VID            0x0a
 266
 267 /* Interface Selection register on other chips */
 268 #define IT87_REG_IFSEL          0x0a
 269
 270 /*
 271  * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
 272  * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
 273  * mode.
 274  */
 275 #define IT87_REG_FAN_DIV        0x0b
 276 #define IT87_REG_FAN_16BIT      0x0c
 277
 278 /*
 279  * Monitors:
 280  * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12)
 281  * - up to 6 temp (1 to 6)
 282  * - up to 6 fan (1 to 6)
 283  */
 284
 285 static const u8 IT87_REG_FAN[] =        { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
 286 static const u8 IT87_REG_FAN_MIN[] =    { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
 287 static const u8 IT87_REG_FANX[] =       { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
 288 static const u8 IT87_REG_FANX_MIN[] =   { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
 289
 290 static const u8 IT87_REG_FAN_8665[] =   { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x93 };
 291 static const u8 IT87_REG_FAN_MIN_8665[] = {
 292                                         0x10, 0x11, 0x12, 0x84, 0x86, 0xb2 };
 293 static const u8 IT87_REG_FANX_8665[] =  { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x94 };
 294 static const u8 IT87_REG_FANX_MIN_8665[] = {
 295                                         0x1b, 0x1c, 0x1d, 0x85, 0x87, 0xb3 };
 296
 297 static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59, 0x5a, 0x90, 0x91 };
 298
 299 static const u8 IT87_REG_TEMP_OFFSET_8686[] = {
 300                                         0x56, 0x57, 0x59, 0x90, 0x91, 0x92 };
 301
 302 #define IT87_REG_FAN_MAIN_CTRL  0x13
 303 #define IT87_REG_FAN_CTL        0x14
 304
 305 static const u8 IT87_REG_PWM[] =        { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
 306 static const u8 IT87_REG_PWM_8665[] =   { 0x15, 0x16, 0x17, 0x1e, 0x1f, 0x92 };
 307
 308 static const u8 IT87_REG_PWM_DUTY[] =   { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
 309
 310 static const u8 IT87_REG_VIN[]  = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
 311                                     0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
 312
 313 #define IT87_REG_TEMP(nr)       (0x29 + (nr))
 314
 315 #define IT87_REG_VIN_MAX(nr)    (0x30 + (nr) * 2)
 316 #define IT87_REG_VIN_MIN(nr)    (0x31 + (nr) * 2)
 317
 318 static const u8 IT87_REG_TEMP_HIGH[] =  { 0x40, 0x42, 0x44, 0x46, 0xb4, 0xb6 };
 319 static const u8 IT87_REG_TEMP_LOW[] =   { 0x41, 0x43, 0x45, 0x47, 0xb5, 0xb7 };
 320
 321 static const u8 IT87_REG_TEMP_HIGH_8686[] = {
 322                                         0x40, 0x42, 0x44, 0xb4, 0xb6, 0xb8 };
 323 static const u8 IT87_REG_TEMP_LOW_8686[] = {
 324                                         0x41, 0x43, 0x45, 0xb5, 0xb7, 0xb9 };
 325
 326 #define IT87_REG_VIN_ENABLE     0x50
 327 #define IT87_REG_TEMP_ENABLE    0x51
 328 #define IT87_REG_TEMP_EXTRA     0x55
 329 #define IT87_REG_BEEP_ENABLE    0x5c
 330
 331 #define IT87_REG_CHIPID         0x58
 332
 333 static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
 334
 335 #define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i))
 336 #define IT87_REG_AUTO_PWM(nr, i)  (IT87_REG_AUTO_BASE[nr] + 5 + (i))
 337
 338 #define IT87_REG_TEMP456_ENABLE 0x77
 339
 340 static const u16 IT87_REG_TEMP_SRC1[] = { 0x21d, 0x21e, 0x21f };
 341 #define IT87_REG_TEMP_SRC2      0x23d
 342
 343 #define NUM_VIN                 ARRAY_SIZE(IT87_REG_VIN)
 344 #define NUM_VIN_LIMIT           8
 345 #define NUM_TEMP                6
 346 #define NUM_FAN                 ARRAY_SIZE(IT87_REG_FAN)
 347 #define NUM_FAN_DIV             3
 348 #define NUM_PWM                 ARRAY_SIZE(IT87_REG_PWM)
 349 #define NUM_AUTO_PWM            ARRAY_SIZE(IT87_REG_PWM)
 350
 351 struct it87_devices {
 352         const char *name;
 353         const char * const model;
 354         u32 features;
 355         u8 num_temp_limit;
 356         u8 num_temp_offset;
 357         u8 num_temp_map;        /* Number of temperature sources for pwm */
 358         u8 peci_mask;
 359         u8 old_peci_mask;
 360         u8 smbus_bitmap;        /* SMBus enable bits in extra config register */
 361         u8 ec_special_config;
 362 };
 363
 364 #define FEAT_12MV_ADC           BIT(0)
 365 #define FEAT_NEWER_AUTOPWM      BIT(1)
 366 #define FEAT_OLD_AUTOPWM        BIT(2)
 367 #define FEAT_16BIT_FANS         BIT(3)
 368 #define FEAT_TEMP_PECI          BIT(5)
 369 #define FEAT_TEMP_OLD_PECI      BIT(6)
 370 #define FEAT_FAN16_CONFIG       BIT(7)  /* Need to enable 16-bit fans */
 371 #define FEAT_FIVE_FANS          BIT(8)  /* Supports five fans */
 372 #define FEAT_VID                BIT(9)  /* Set if chip supports VID */
 373 #define FEAT_IN7_INTERNAL       BIT(10) /* Set if in7 is internal */
 374 #define FEAT_SIX_FANS           BIT(11) /* Supports six fans */
 375 #define FEAT_10_9MV_ADC         BIT(12)
 376 #define FEAT_AVCC3              BIT(13) /* Chip supports in9/AVCC3 */
 377 #define FEAT_FIVE_PWM           BIT(14) /* Chip supports 5 pwm chn */
 378 #define FEAT_SIX_PWM            BIT(15) /* Chip supports 6 pwm chn */
 379 #define FEAT_PWM_FREQ2          BIT(16) /* Separate pwm freq 2 */
 380 #define FEAT_SIX_TEMP           BIT(17) /* Up to 6 temp sensors */
 381 #define FEAT_VIN3_5V            BIT(18) /* VIN3 connected to +5V */
 382 #define FEAT_FOUR_FANS          BIT(19) /* Supports four fans */
 383 #define FEAT_FOUR_PWM           BIT(20) /* Supports four fan controls */
 384 #define FEAT_BANK_SEL           BIT(21) /* Chip has multi-bank support */
 385 #define FEAT_SCALING            BIT(22) /* Internal voltage scaling */
 386 #define FEAT_FANCTL_ONOFF       BIT(23) /* chip has FAN_CTL ON/OFF */
 387 #define FEAT_11MV_ADC           BIT(24)
 388 #define FEAT_NEW_TEMPMAP        BIT(25) /* new temp input selection */
 389 #define FEAT_MMIO               BIT(26) /* Chip supports MMIO */
 390 #define FEAT_FOUR_TEMP          BIT(27)
 391
 392 static const struct it87_devices it87_devices[] = {
 393         [it87] = {
 394                 .name = "it87",
 395                 .model = "IT87F",
 396                 .features = FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF,
 397                                                 /* may need to overwrite */
 398                 .num_temp_limit = 3,
 399                 .num_temp_offset = 0,
 400                 .num_temp_map = 3,
 401         },
 402         [it8712] = {
 403                 .name = "it8712",
 404                 .model = "IT8712F",
 405                 .features = FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF,
 406                                                 /* may need to overwrite */
 407                 .num_temp_limit = 3,
 408                 .num_temp_offset = 0,
 409                 .num_temp_map = 3,
 410         },
 411         [it8716] = {
 412                 .name = "it8716",
 413                 .model = "IT8716F",
 414                 .features = FEAT_16BIT_FANS | FEAT_VID
 415                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2
 416                   | FEAT_FANCTL_ONOFF,
 417                 .num_temp_limit = 3,
 418                 .num_temp_offset = 3,
 419                 .num_temp_map = 3,
 420         },
 421         [it8718] = {
 422                 .name = "it8718",
 423                 .model = "IT8718F",
 424                 .features = FEAT_16BIT_FANS | FEAT_VID
 425                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 426                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 427                 .num_temp_limit = 3,
 428                 .num_temp_offset = 3,
 429                 .num_temp_map = 3,
 430                 .old_peci_mask = 0x4,
 431         },
 432         [it8720] = {
 433                 .name = "it8720",
 434                 .model = "IT8720F",
 435                 .features = FEAT_16BIT_FANS | FEAT_VID
 436                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
 437                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 438                 .num_temp_limit = 3,
 439                 .num_temp_offset = 3,
 440                 .num_temp_map = 3,
 441                 .old_peci_mask = 0x4,
 442         },
 443         [it8721] = {
 444                 .name = "it8721",
 445                 .model = "IT8721F",
 446                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 447                   | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 448                   | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
 449                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 450                 .num_temp_limit = 3,
 451                 .num_temp_offset = 3,
 452                 .num_temp_map = 3,
 453                 .peci_mask = 0x05,
 454                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 455         },
 456         [it8728] = {
 457                 .name = "it8728",
 458                 .model = "IT8728F",
 459                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 460                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 461                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_SCALING
 462                   | FEAT_FANCTL_ONOFF,
 463                 .num_temp_limit = 6,
 464                 .num_temp_offset = 3,
 465                 .num_temp_map = 3,
 466                 .peci_mask = 0x07,
 467         },
 468         [it8732] = {
 469                 .name = "it8732",
 470                 .model = "IT8732F",
 471                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 472                   | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 473                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS
 474                   | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF | FEAT_SCALING,
 475                 .num_temp_limit = 3,
 476                 .num_temp_offset = 3,
 477                 .num_temp_map = 3,
 478                 .peci_mask = 0x07,
 479                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 480         },
 481         [it8736] = {
 482                 .name = "it8736",
 483                 .model = "IT8736F",
 484                 .features = FEAT_16BIT_FANS
 485                   | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 486                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS
 487                   | FEAT_FANCTL_ONOFF | FEAT_SCALING,
 488                 .num_temp_limit = 3,
 489                 .num_temp_offset = 3,
 490                 .num_temp_map = 3,
 491                 .peci_mask = 0x07,
 492                 .old_peci_mask = 0x02,  /* Actually reports PCH */
 493         },
 494         [it8738] = {
 495                 .name = "it8738",
 496                 .model = "IT8738E",
 497                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 498                   | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
 499                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL
 500                   | FEAT_FANCTL_ONOFF | FEAT_SCALING
 501                   | FEAT_AVCC3,
 502                 .num_temp_limit = 3,
 503                 .num_temp_offset = 3,
 504                 .num_temp_map = 3,
 505                 .peci_mask = 0x07,
 506                 .old_peci_mask = 0x02,
 507         },
 508         [it8771] = {
 509                 .name = "it8771",
 510                 .model = "IT8771E",
 511                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 512                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 513                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 514                                 /* PECI: guesswork */
 515                                 /* 12mV ADC (OHM) */
 516                                 /* 16 bit fans (OHM) */
 517                                 /* three fans, always 16 bit (guesswork) */
 518                 .num_temp_limit = 3,
 519                 .num_temp_offset = 3,
 520                 .num_temp_map = 3,
 521                 .peci_mask = 0x07,
 522         },
 523         [it8772] = {
 524                 .name = "it8772",
 525                 .model = "IT8772E",
 526                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 527                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 528                   | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
 529                                 /* PECI (coreboot) */
 530                                 /* 12mV ADC (HWSensors4, OHM) */
 531                                 /* 16 bit fans (HWSensors4, OHM) */
 532                                 /* three fans, always 16 bit (datasheet) */
 533                 .num_temp_limit = 3,
 534                 .num_temp_offset = 3,
 535                 .num_temp_map = 3,
 536                 .peci_mask = 0x07,
 537         },
 538         [it8781] = {
 539                 .name = "it8781",
 540                 .model = "IT8781F",
 541                 .features = FEAT_16BIT_FANS
 542                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 543                   | FEAT_FANCTL_ONOFF,
 544                 .num_temp_limit = 3,
 545                 .num_temp_offset = 3,
 546                 .num_temp_map = 3,
 547                 .old_peci_mask = 0x4,
 548         },
 549         [it8782] = {
 550                 .name = "it8782",
 551                 .model = "IT8782F",
 552                 .features = FEAT_16BIT_FANS
 553                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 554                   | FEAT_FANCTL_ONOFF,
 555                 .num_temp_limit = 3,
 556                 .num_temp_offset = 3,
 557                 .num_temp_map = 3,
 558                 .old_peci_mask = 0x4,
 559         },
 560         [it8783] = {
 561                 .name = "it8783",
 562                 .model = "IT8783E/F",
 563                 .features = FEAT_16BIT_FANS
 564                   | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
 565                   | FEAT_FANCTL_ONOFF,
 566                 .num_temp_limit = 3,
 567                 .num_temp_offset = 3,
 568                 .num_temp_map = 3,
 569                 .old_peci_mask = 0x4,
 570         },
 571         [it8786] = {
 572                 .name = "it8786",
 573                 .model = "IT8786E",
 574                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 575                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 576                   | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 577                 .num_temp_limit = 3,
 578                 .num_temp_offset = 3,
 579                 .num_temp_map = 3,
 580                 .peci_mask = 0x07,
 581         },
 582         [it8790] = {
 583                 .name = "it8790",
 584                 .model = "IT8790E",
 585                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 586                   | FEAT_16BIT_FANS | FEAT_TEMP_PECI
 587                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 588                 .num_temp_limit = 3,
 589                 .num_temp_offset = 3,
 590                 .num_temp_map = 3,
 591                 .peci_mask = 0x07,
 592         },
 593         [it8792] = {
 594                 .name = "it8792",
 595                 .model = "IT8792E/IT8795E",
 596                 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
 597                   | FEAT_16BIT_FANS | FEAT_TEMP_PECI
 598                   | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
 599                 .num_temp_limit = 3,
 600                 .num_temp_offset = 3,
 601                 .num_temp_map = 3,
 602                 .peci_mask = 0x07,
 603         },
 604         [it8603] = {
 605                 .name = "it8603",
 606                 .model = "IT8603E",
 607                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 608                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 609                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
 610                 .num_temp_limit = 3,
 611                 .num_temp_offset = 3,
 612                 .num_temp_map = 4,
 613                 .peci_mask = 0x07,
 614         },
 615         [it8606] = {
 616                 .name = "it8606",
 617                 .model = "IT8606E",
 618                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 619                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
 620                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
 621                 .num_temp_limit = 3,
 622                 .num_temp_offset = 3,
 623                 .num_temp_map = 3,
 624                 .peci_mask = 0x07,
 625         },
 626         [it8607] = {
 627                 .name = "it8607",
 628                 .model = "IT8607E",
 629                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 630                   | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL | FEAT_NEW_TEMPMAP
 631                   | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING
 632                   | FEAT_FANCTL_ONOFF,
 633                 .num_temp_limit = 3,
 634                 .num_temp_offset = 3,
 635                 .num_temp_map = 6,
 636                 .peci_mask = 0x07,
 637         },
 638         [it8613] = {
 639                 .name = "it8613",
 640                 .model = "IT8613E",
 641                 .features = FEAT_NEWER_AUTOPWM | FEAT_11MV_ADC | FEAT_16BIT_FANS
 642                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS
 643                   | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
 644                   | FEAT_AVCC3 | FEAT_SCALING | FEAT_NEW_TEMPMAP,
 645                 .num_temp_limit = 6,
 646                 .num_temp_offset = 6,
 647                 .num_temp_map = 6,
 648                 .peci_mask = 0x07,
 649         },
 650         [it8620] = {
 651                 .name = "it8620",
 652                 .model = "IT8620E",
 653                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 654                   | FEAT_TEMP_PECI | FEAT_SIX_FANS
 655                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 656                   | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_SCALING
 657                   | FEAT_FANCTL_ONOFF,
 658                 .num_temp_limit = 3,
 659                 .num_temp_offset = 3,
 660                 .num_temp_map = 3,
 661                 .peci_mask = 0x07,
 662         },
 663         [it8622] = {
 664                 .name = "it8622",
 665                 .model = "IT8622E",
 666                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 667                   | FEAT_TEMP_PECI | FEAT_FIVE_FANS | FEAT_FOUR_TEMP
 668                   | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
 669                   | FEAT_AVCC3 | FEAT_VIN3_5V | FEAT_SCALING,
 670                 .num_temp_limit = 3,
 671                 .num_temp_offset = 3,
 672                 .num_temp_map = 4,
 673                 .peci_mask = 0x0f,
 674                 .smbus_bitmap = BIT(1) | BIT(2),
 675         },
 676         [it8625] = {
 677                 .name = "it8625",
 678                 .model = "IT8625E",
 679                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 680                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP
 681                   | FEAT_11MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
 682                   | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_SCALING,
 683                 .num_temp_limit = 6,
 684                 .num_temp_offset = 6,
 685                 .num_temp_map = 6,
 686                 .smbus_bitmap = BIT(1) | BIT(2),
 687         },
 688         [it8628] = {
 689                 .name = "it8628",
 690                 .model = "IT8628E",
 691                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 692                   | FEAT_TEMP_PECI | FEAT_SIX_FANS
 693                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 694                   | FEAT_SIX_TEMP | FEAT_SCALING | FEAT_AVCC3
 695                   | FEAT_FANCTL_ONOFF,
 696                 .num_temp_limit = 6,
 697                 .num_temp_offset = 3,
 698                 .num_temp_map = 3,
 699                 .peci_mask = 0x07,
 700         },
 701         [it8655] = {
 702                 .name = "it8655",
 703                 .model = "IT8655E",
 704                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 705                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
 706                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_BANK_SEL
 707                   | FEAT_SIX_TEMP | FEAT_MMIO,
 708                 .num_temp_limit = 6,
 709                 .num_temp_offset = 6,
 710                 .num_temp_map = 6,
 711                 .smbus_bitmap = BIT(2),
 712         },
 713         [it8665] = {
 714                 .name = "it8665",
 715                 .model = "IT8665E",
 716                 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
 717                   | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
 718                   | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
 719                   | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_MMIO | FEAT_SIX_TEMP,
 720                 .num_temp_limit = 6,
 721                 .num_temp_offset = 6,
 722                 .num_temp_map = 6,
 723                 .smbus_bitmap = BIT(2),
 724         },
 725         [it8686] = {
 726                 .name = "it8686",
 727                 .model = "IT8686E",
 728                 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
 729                   | FEAT_SIX_FANS | FEAT_NEW_TEMPMAP
 730                   | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
 731                   | FEAT_SIX_TEMP | FEAT_BANK_SEL | FEAT_SCALING | FEAT_AVCC3,
 732                 .num_temp_limit = 6,
 733                 .num_temp_offset = 6,
 734                 .num_temp_map = 7,
 735                 .smbus_bitmap = BIT(1) | BIT(2),
 736         },
 737 };
 738
 739 #define has_16bit_fans(data)    ((data)->features & FEAT_16BIT_FANS)
 740 #define has_12mv_adc(data)      ((data)->features & FEAT_12MV_ADC)
 741 #define has_10_9mv_adc(data)    ((data)->features & FEAT_10_9MV_ADC)
 742 #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
 743 #define has_old_autopwm(data)   ((data)->features & FEAT_OLD_AUTOPWM)
 744 #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
 745                                  ((data)->peci_mask & BIT(nr)))
 746 #define has_temp_old_peci(data, nr) \
 747                                 (((data)->features & FEAT_TEMP_OLD_PECI) && \
 748                                  ((data)->old_peci_mask & BIT(nr)))
 749 #define has_fan16_config(data)  ((data)->features & FEAT_FAN16_CONFIG)
 750 #define has_five_fans(data)     ((data)->features & (FEAT_FIVE_FANS | \
 751                                                      FEAT_SIX_FANS))
 752 #define has_vid(data)           ((data)->features & FEAT_VID)
 753 #define has_in7_internal(data)  ((data)->features & FEAT_IN7_INTERNAL)
 754 #define has_six_fans(data)      ((data)->features & FEAT_SIX_FANS)
 755 #define has_avcc3(data)         ((data)->features & FEAT_AVCC3)
 756 #define has_five_pwm(data)      ((data)->features & (FEAT_FIVE_PWM \
 757                                                      | FEAT_SIX_PWM))
 758 #define has_six_pwm(data)       ((data)->features & FEAT_SIX_PWM)
 759 #define has_pwm_freq2(data)     ((data)->features & FEAT_PWM_FREQ2)
 760 #define has_six_temp(data)      ((data)->features & FEAT_SIX_TEMP)
 761 #define has_vin3_5v(data)       ((data)->features & FEAT_VIN3_5V)
 762 #define has_four_fans(data)     ((data)->features & (FEAT_FOUR_FANS | \
 763                                                      FEAT_FIVE_FANS | \
 764                                                      FEAT_SIX_FANS))
 765 #define has_four_pwm(data)      ((data)->features & (FEAT_FOUR_PWM | \
 766                                                      FEAT_FIVE_PWM \
 767                                                      | FEAT_SIX_PWM))
 768 #define has_bank_sel(data)      ((data)->features & FEAT_BANK_SEL)
 769 #define has_scaling(data)       ((data)->features & FEAT_SCALING)
 770 #define has_fanctl_onoff(data)  ((data)->features & FEAT_FANCTL_ONOFF)
 771 #define has_11mv_adc(data)      ((data)->features & FEAT_11MV_ADC)
 772 #define has_new_tempmap(data)   ((data)->features & FEAT_NEW_TEMPMAP)
 773 #define has_mmio(data)          ((data)->features & FEAT_MMIO)
 774 #define has_four_temp(data)     ((data)->features & FEAT_FOUR_TEMP)
 775
 776 struct it87_sio_data {
 777         enum chips type;
 778         u8 sioaddr;
 779         u8 doexit;
 780         /* Values read from Super-I/O config space */
 781         u8 revision;
 782         u8 vid_value;
 783         u8 beep_pin;
 784         u8 internal;    /* Internal sensors can be labeled */
 785         /* Features skipped based on config or DMI */
 786         u16 skip_in;
 787         u8 skip_vid;
 788         u8 skip_fan;
 789         u8 skip_pwm;
 790         u8 skip_temp;
 791         u8 smbus_bitmap;
 792         u8 ec_special_config;
 793 };
 794
 795 /*
 796  * For each registered chip, we need to keep some data in memory.
 797  * The structure is dynamically allocated.
 798  */
 799 struct it87_data {
 800         const struct attribute_group *groups[7];
 801         enum chips type;
 802         u32 features;
 803         u8 peci_mask;
 804         u8 old_peci_mask;
 805
 806         u8 smbus_bitmap;        /* !=0 if SMBus needs to be disabled */
 807         u8 saved_bank;          /* saved bank register value */
 808         u8 ec_special_config;   /* EC special config register restore value */
 809         u8 sioaddr;             /* SIO port address */
 810         bool doexit;            /* true if exit from sio config is ok */
 811
 812         void __iomem *mmio;     /* Remapped MMIO address if available */
 813         int (*read)(struct it87_data *, u16);
 814         void (*write)(struct it87_data *, u16, u8);
 815
 816         const u8 *REG_FAN;
 817         const u8 *REG_FANX;
 818         const u8 *REG_FAN_MIN;
 819         const u8 *REG_FANX_MIN;
 820
 821         const u8 *REG_PWM;
 822
 823         const u8 *REG_TEMP_OFFSET;
 824         const u8 *REG_TEMP_LOW;
 825         const u8 *REG_TEMP_HIGH;
 826
 827         unsigned short addr;
 828         struct mutex update_lock;
 829         char valid;             /* !=0 if following fields are valid */
 830         unsigned long last_updated;     /* In jiffies */
 831
 832         u16 in_scaled;          /* Internal voltage sensors are scaled */
 833         u16 in_internal;        /* Bitfield, internal sensors (for labels) */
 834         u16 has_in;             /* Bitfield, voltage sensors enabled */
 835         u8 in[NUM_VIN][3];              /* [nr][0]=in, [1]=min, [2]=max */
 836         u8 has_fan;             /* Bitfield, fans enabled */
 837         u16 fan[NUM_FAN][2];    /* Register values, [nr][0]=fan, [1]=min */
 838         u8 has_temp;            /* Bitfield, temp sensors enabled */
 839         s8 temp[NUM_TEMP][4];   /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
 840         u8 num_temp_limit;      /* Number of temperature limit registers */
 841         u8 num_temp_offset;     /* Number of temperature offset registers */
 842         u8 temp_src[4];         /* Up to 4 temperature source registers */
 843         u8 sensor;              /* Register value (IT87_REG_TEMP_ENABLE) */
 844         u8 extra;               /* Register value (IT87_REG_TEMP_EXTRA) */
 845         u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
 846         bool has_vid;           /* True if VID supported */
 847         u8 vid;                 /* Register encoding, combined */
 848         u8 vrm;
 849         u32 alarms;             /* Register encoding, combined */
 850         bool has_beep;          /* true if beep supported */
 851         u8 beeps;               /* Register encoding */
 852         u8 fan_main_ctrl;       /* Register value */
 853         u8 fan_ctl;             /* Register value */
 854
 855         /*
 856          * The following 3 arrays correspond to the same registers up to
 857          * the IT8720F. The meaning of bits 6-0 depends on the value of bit
 858          * 7, and we want to preserve settings on mode changes, so we have
 859          * to track all values separately.
 860          * Starting with the IT8721F, the manual PWM duty cycles are stored
 861          * in separate registers (8-bit values), so the separate tracking
 862          * is no longer needed, but it is still done to keep the driver
 863          * simple.
 864          */
 865         u8 has_pwm;             /* Bitfield, pwm control enabled */
 866         u8 pwm_ctrl[NUM_PWM];   /* Register value */
 867         u8 pwm_duty[NUM_PWM];   /* Manual PWM value set by user */
 868         u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
 869         u8 pwm_temp_map_mask;   /* 0x03 for old, 0x07 for new temp map */
 870         u8 pwm_temp_map_shift;  /* 0 for old, 3 for new temp map */
 871         u8 pwm_num_temp_map;    /* from config data, 3..7 depending on chip */
 872
 873         /* Automatic fan speed control registers */
 874         u8 auto_pwm[NUM_AUTO_PWM][4];   /* [nr][3] is hard-coded */
 875         s8 auto_temp[NUM_AUTO_PWM][5];  /* [nr][0] is point1_temp_hyst */
 876 };
 877
 878 static int adc_lsb(const struct it87_data *data, int nr)
 879 {
 880         int lsb;
 881
 882         if (has_12mv_adc(data))
 883                 lsb = 120;
 884         else if (has_10_9mv_adc(data))
 885                 lsb = 109;
 886         else if (has_11mv_adc(data))
 887                 lsb = 110;
 888         else
 889                 lsb = 160;
 890         if (data->in_scaled & BIT(nr))
 891                 lsb <<= 1;
 892         return lsb;
 893 }
 894
 895 static u8 in_to_reg(const struct it87_data *data, int nr, long val)
 896 {
 897         val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr));
 898         return clamp_val(val, 0, 255);
 899 }
 900
 901 static int in_from_reg(const struct it87_data *data, int nr, int val)
 902 {
 903         return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10);
 904 }
 905
 906 static inline u8 FAN_TO_REG(long rpm, int div)
 907 {
 908         if (rpm == 0)
 909                 return 255;
 910         rpm = clamp_val(rpm, 1, 1000000);
 911         return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
 912 }
 913
 914 static inline u16 FAN16_TO_REG(long rpm)
 915 {
 916         if (rpm == 0)
 917                 return 0xffff;
 918         return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
 919 }
 920
 921 #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
 922                                 1350000 / ((val) * (div)))
 923 /* The divider is fixed to 2 in 16-bit mode */
 924 #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
 925                              1350000 / ((val) * 2))
 926
 927 #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
 928                                     ((val) + 500) / 1000), -128, 127))
 929 #define TEMP_FROM_REG(val) ((val) * 1000)
 930
 931 static u8 pwm_to_reg(const struct it87_data *data, long val)
 932 {
 933         if (has_newer_autopwm(data))
 934                 return val;
 935         else
 936                 return val >> 1;
 937 }
 938
 939 static int pwm_from_reg(const struct it87_data *data, u8 reg)
 940 {
 941         if (has_newer_autopwm(data))
 942                 return reg;
 943         else
 944                 return (reg & 0x7f) << 1;
 945 }
 946
 947 static int DIV_TO_REG(int val)
 948 {
 949         int answer = 0;
 950
 951         while (answer < 7 && (val >>= 1))
 952                 answer++;
 953         return answer;
 954 }
 955
 956 #define DIV_FROM_REG(val) BIT(val)
 957
 958 static u8 temp_map_from_reg(const struct it87_data *data, u8 reg)
 959 {
 960         u8 map;
 961
 962         map = (reg >> data->pwm_temp_map_shift) & data->pwm_temp_map_mask;
 963         if (map >= data->pwm_num_temp_map)      /* map is 0-based */
 964                 map = 0;
 965
 966         return map;
 967 }
 968
 969 static u8 temp_map_to_reg(const struct it87_data *data, int nr, u8 map)
 970 {
 971         u8 ctrl = data->pwm_ctrl[nr];
 972
 973         return (ctrl & ~(data->pwm_temp_map_mask << data->pwm_temp_map_shift)) |
 974                (map << data->pwm_temp_map_shift);
 975 }
 976
 977 /*
 978  * PWM base frequencies. The frequency has to be divided by either 128 or 256,
 979  * depending on the chip type, to calculate the actual PWM frequency.
 980  *
 981  * Some of the chip datasheets suggest a base frequency of 51 kHz instead
 982  * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
 983  * of 200 Hz. Sometimes both PWM frequency select registers are affected,
 984  * sometimes just one. It is unknown if this is a datasheet error or real,
 985  * so this is ignored for now.
 986  */
 987 static const unsigned int pwm_freq[8] = {
 988         48000000,
 989         24000000,
 990         12000000,
 991         8000000,
 992         6000000,
 993         3000000,
 994         1500000,
 995         750000,
 996 };
 997
 998 static int _it87_io_read(struct it87_data *data, u16 reg)
 999 {
1000         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
1001         return inb_p(data->addr + IT87_DATA_REG_OFFSET);
1002 }
1003
1004 static void _it87_io_write(struct it87_data *data, u16 reg, u8 value)
1005 {
1006         outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
1007         outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
1008 }
1009
1010 static int smbus_disable(struct it87_data *data)
1011 {
1012         int err;
1013
1014         if (data->smbus_bitmap) {
1015                 err = superio_enter(data->sioaddr);
1016                 if (err)
1017                         return err;
1018                 superio_select(data->sioaddr, PME);
1019                 superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG,
1020                              data->ec_special_config & ~data->smbus_bitmap);
1021                 superio_exit(data->sioaddr, data->doexit);
1022                 if (has_bank_sel(data) && !data->mmio)
1023                         data->saved_bank = _it87_io_read(data, IT87_REG_BANK);
1024         }
1025         return 0;
1026 }
1027
1028 static int smbus_enable(struct it87_data *data)
1029 {
1030         int err;
1031
1032         if (data->smbus_bitmap) {
1033                 if (has_bank_sel(data) && !data->mmio)
1034                         _it87_io_write(data, IT87_REG_BANK, data->saved_bank);
1035                 err = superio_enter(data->sioaddr);
1036                 if (err)
1037                         return err;
1038
1039                 superio_select(data->sioaddr, PME);
1040                 superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG,
1041                              data->ec_special_config);
1042                 superio_exit(data->sioaddr, data->doexit);
1043         }
1044         return 0;
1045 }
1046
1047 static u8 it87_io_set_bank(struct it87_data *data, u8 bank)
1048 {
1049         u8 _bank = bank;
1050
1051         if (has_bank_sel(data)) {
1052                 u8 breg = _it87_io_read(data, IT87_REG_BANK);
1053
1054                 _bank = breg >> 5;
1055                 if (bank != _bank) {
1056                         breg &= 0x1f;
1057                         breg |= (bank << 5);
1058                         _it87_io_write(data, IT87_REG_BANK, breg);
1059                 }
1060         }
1061         return _bank;
1062 }
1063
1064 /*
1065  * Must be called with data->update_lock held, except during initialization.
1066  * Must be called with SMBus accesses disabled.
1067  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
1068  * would slow down the IT87 access and should not be necessary.
1069  */
1070 static int it87_io_read(struct it87_data *data, u16 reg)
1071 {
1072         u8 bank;
1073         int val;
1074
1075         bank = it87_io_set_bank(data, reg >> 8);
1076         val = _it87_io_read(data, reg & 0xff);
1077         it87_io_set_bank(data, bank);
1078
1079         return val;
1080 }
1081
1082 /*
1083  * Must be called with data->update_lock held, except during initialization.
1084  * Must be called with SMBus accesses disabled
1085  * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
1086  * would slow down the IT87 access and should not be necessary.
1087  */
1088 static void it87_io_write(struct it87_data *data, u16 reg, u8 value)
1089 {
1090         u8 bank;
1091
1092         bank = it87_io_set_bank(data, reg >> 8);
1093         _it87_io_write(data, reg & 0xff, value);
1094         it87_io_set_bank(data, bank);
1095 }
1096
1097 static int it87_mmio_read(struct it87_data *data, u16 reg)
1098 {
1099         return readb(data->mmio + reg);
1100 }
1101
1102 static void it87_mmio_write(struct it87_data *data, u16 reg, u8 value)
1103 {
1104         writeb(value, data->mmio + reg);
1105 }
1106
1107 static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
1108 {
1109         u8 ctrl;
1110
1111         ctrl = data->read(data, data->REG_PWM[nr]);
1112         data->pwm_ctrl[nr] = ctrl;
1113         if (has_newer_autopwm(data)) {
1114                 data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
1115                 data->pwm_duty[nr] = data->read(data, IT87_REG_PWM_DUTY[nr]);
1116         } else {
1117                 if (ctrl & 0x80)        /* Automatic mode */
1118                         data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
1119                 else                            /* Manual mode */
1120                         data->pwm_duty[nr] = ctrl & 0x7f;
1121         }
1122
1123         if (has_old_autopwm(data)) {
1124                 int i;
1125
1126                 for (i = 0; i < 5 ; i++)
1127                         data->auto_temp[nr][i] = data->read(data,
1128                                                 IT87_REG_AUTO_TEMP(nr, i));
1129                 for (i = 0; i < 3 ; i++)
1130                         data->auto_pwm[nr][i] = data->read(data,
1131                                                 IT87_REG_AUTO_PWM(nr, i));
1132         } else if (has_newer_autopwm(data)) {
1133                 int i;
1134
1135                 /*
1136                  * 0: temperature hysteresis (base + 5)
1137                  * 1: fan off temperature (base + 0)
1138                  * 2: fan start temperature (base + 1)
1139                  * 3: fan max temperature (base + 2)
1140                  */
1141                 data->auto_temp[nr][0] =
1142                         data->read(data, IT87_REG_AUTO_TEMP(nr, 5));
1143
1144                 for (i = 0; i < 3 ; i++)
1145                         data->auto_temp[nr][i + 1] =
1146                                 data->read(data, IT87_REG_AUTO_TEMP(nr, i));
1147                 /*
1148                  * 0: start pwm value (base + 3)
1149                  * 1: pwm slope (base + 4, 1/8th pwm)
1150                  */
1151                 data->auto_pwm[nr][0] =
1152                         data->read(data, IT87_REG_AUTO_TEMP(nr, 3));
1153                 data->auto_pwm[nr][1] =
1154                         data->read(data, IT87_REG_AUTO_TEMP(nr, 4));
1155         }
1156 }
1157
1158 static int it87_lock(struct it87_data *data)
1159 {
1160         int err;
1161
1162         mutex_lock(&data->update_lock);
1163         err = smbus_disable(data);
1164         if (err)
1165                 mutex_unlock(&data->update_lock);
1166         return err;
1167 }
1168
1169 static void it87_unlock(struct it87_data *data)
1170 {
1171         smbus_enable(data);
1172         mutex_unlock(&data->update_lock);
1173 }
1174
1175 static struct it87_data *it87_update_device(struct device *dev)
1176 {
1177         struct it87_data *data = dev_get_drvdata(dev);
1178         struct it87_data *ret = data;
1179         int err;
1180         int i;
1181
1182         mutex_lock(&data->update_lock);
1183
1184         if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
1185             !data->valid) {
1186                 err = smbus_disable(data);
1187                 if (err) {
1188                         ret = ERR_PTR(err);
1189                         goto unlock;
1190                 }
1191                 if (update_vbat) {
1192                         /*
1193                          * Cleared after each update, so reenable.  Value
1194                          * returned by this read will be previous value
1195                          */
1196                         data->write(data, IT87_REG_CONFIG,
1197                                     data->read(data, IT87_REG_CONFIG) | 0x40);
1198                 }
1199                 for (i = 0; i < NUM_VIN; i++) {
1200                         if (!(data->has_in & BIT(i)))
1201                                 continue;
1202
1203                         data->in[i][0] = data->read(data, IT87_REG_VIN[i]);
1204
1205                         /* VBAT and AVCC don't have limit registers */
1206                         if (i >= NUM_VIN_LIMIT)
1207                                 continue;
1208
1209                         data->in[i][1] = data->read(data, IT87_REG_VIN_MIN(i));
1210                         data->in[i][2] = data->read(data, IT87_REG_VIN_MAX(i));
1211                 }
1212
1213                 for (i = 0; i < NUM_FAN; i++) {
1214                         /* Skip disabled fans */
1215                         if (!(data->has_fan & BIT(i)))
1216                                 continue;
1217
1218                         data->fan[i][1] = data->read(data,
1219                                                      data->REG_FAN_MIN[i]);
1220                         data->fan[i][0] = data->read(data, data->REG_FAN[i]);
1221                         /* Add high byte if in 16-bit mode */
1222                         if (has_16bit_fans(data)) {
1223                                 data->fan[i][0] |= data->read(data,
1224                                                 data->REG_FANX[i]) << 8;
1225                                 data->fan[i][1] |= data->read(data,
1226                                                 data->REG_FANX_MIN[i]) << 8;
1227                         }
1228                 }
1229                 for (i = 0; i < NUM_TEMP; i++) {
1230                         if (!(data->has_temp & BIT(i)))
1231                                 continue;
1232                         data->temp[i][0] =
1233                                 data->read(data, IT87_REG_TEMP(i));
1234
1235                         if (i >= data->num_temp_limit)
1236                                 continue;
1237
1238                         if (i < data->num_temp_offset)
1239                                 data->temp[i][3] =
1240                                   data->read(data, data->REG_TEMP_OFFSET[i]);
1241
1242                         data->temp[i][1] =
1243                                 data->read(data, data->REG_TEMP_LOW[i]);
1244                         data->temp[i][2] =
1245                                 data->read(data, data->REG_TEMP_HIGH[i]);
1246                 }
1247
1248                 /* Newer chips don't have clock dividers */
1249                 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
1250                         i = data->read(data, IT87_REG_FAN_DIV);
1251                         data->fan_div[0] = i & 0x07;
1252                         data->fan_div[1] = (i >> 3) & 0x07;
1253                         data->fan_div[2] = (i & 0x40) ? 3 : 1;
1254                 }
1255
1256                 data->alarms =
1257                         data->read(data, IT87_REG_ALARM1) |
1258                         (data->read(data, IT87_REG_ALARM2) << 8) |
1259                         (data->read(data, IT87_REG_ALARM3) << 16);
1260                 data->beeps = data->read(data, IT87_REG_BEEP_ENABLE);
1261
1262                 data->fan_main_ctrl = data->read(data, IT87_REG_FAN_MAIN_CTRL);
1263                 data->fan_ctl = data->read(data, IT87_REG_FAN_CTL);
1264                 for (i = 0; i < NUM_PWM; i++) {
1265                         if (!(data->has_pwm & BIT(i)))
1266                                 continue;
1267                         it87_update_pwm_ctrl(data, i);
1268                 }
1269
1270                 data->sensor = data->read(data, IT87_REG_TEMP_ENABLE);
1271                 data->extra = data->read(data, IT87_REG_TEMP_EXTRA);
1272                 /*
1273                  * The IT8705F does not have VID capability.
1274                  * The IT8718F and later don't use IT87_REG_VID for the
1275                  * same purpose.
1276                  */
1277                 if (data->type == it8712 || data->type == it8716) {
1278                         data->vid = data->read(data, IT87_REG_VID);
1279                         /*
1280                          * The older IT8712F revisions had only 5 VID pins,
1281                          * but we assume it is always safe to read 6 bits.
1282                          */
1283                         data->vid &= 0x3f;
1284                 }
1285                 data->last_updated = jiffies;
1286                 data->valid = 1;
1287                 smbus_enable(data);
1288         }
1289 unlock:
1290         mutex_unlock(&data->update_lock);
1291         return ret;
1292 }
1293
1294 static ssize_t show_in(struct device *dev, struct device_attribute *attr,
1295                        char *buf)
1296 {
1297         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1298         struct it87_data *data = it87_update_device(dev);
1299         int index = sattr->index;
1300         int nr = sattr->nr;
1301
1302         if (IS_ERR(data))
1303                 return PTR_ERR(data);
1304
1305         return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1306 }
1307
1308 static ssize_t set_in(struct device *dev, struct device_attribute *attr,
1309                       const char *buf, size_t count)
1310 {
1311         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1312         struct it87_data *data = dev_get_drvdata(dev);
1313         int index = sattr->index;
1314         int nr = sattr->nr;
1315         unsigned long val;
1316         int err;
1317
1318         if (kstrtoul(buf, 10, &val) < 0)
1319                 return -EINVAL;
1320
1321         err = it87_lock(data);
1322         if (err)
1323                 return err;
1324
1325         data->in[nr][index] = in_to_reg(data, nr, val);
1326         data->write(data, index == 1 ? IT87_REG_VIN_MIN(nr)
1327                                      : IT87_REG_VIN_MAX(nr),
1328                     data->in[nr][index]);
1329         it87_unlock(data);
1330         return count;
1331 }
1332
1333 static SENSOR_DEVICE_ATTR_2(in0_input, 0444, show_in, NULL, 0, 0);
1334 static SENSOR_DEVICE_ATTR_2(in0_min, 0644, show_in, set_in, 0, 1);
1335 static SENSOR_DEVICE_ATTR_2(in0_max, 0644, show_in, set_in, 0, 2);
1336
1337 static SENSOR_DEVICE_ATTR_2(in1_input, 0444, show_in, NULL, 1, 0);
1338 static SENSOR_DEVICE_ATTR_2(in1_min, 0644, show_in, set_in, 1, 1);
1339 static SENSOR_DEVICE_ATTR_2(in1_max, 0644, show_in, set_in, 1, 2);
1340
1341 static SENSOR_DEVICE_ATTR_2(in2_input, 0444, show_in, NULL, 2, 0);
1342 static SENSOR_DEVICE_ATTR_2(in2_min, 0644, show_in, set_in, 2, 1);
1343 static SENSOR_DEVICE_ATTR_2(in2_max, 0644, show_in, set_in, 2, 2);
1344
1345 static SENSOR_DEVICE_ATTR_2(in3_input, 0444, show_in, NULL, 3, 0);
1346 static SENSOR_DEVICE_ATTR_2(in3_min, 0644, show_in, set_in, 3, 1);
1347 static SENSOR_DEVICE_ATTR_2(in3_max, 0644, show_in, set_in, 3, 2);
1348
1349 static SENSOR_DEVICE_ATTR_2(in4_input, 0444, show_in, NULL, 4, 0);
1350 static SENSOR_DEVICE_ATTR_2(in4_min, 0644, show_in, set_in, 4, 1);
1351 static SENSOR_DEVICE_ATTR_2(in4_max, 0644, show_in, set_in, 4, 2);
1352
1353 static SENSOR_DEVICE_ATTR_2(in5_input, 0444, show_in, NULL, 5, 0);
1354 static SENSOR_DEVICE_ATTR_2(in5_min, 0644, show_in, set_in, 5, 1);
1355 static SENSOR_DEVICE_ATTR_2(in5_max, 0644, show_in, set_in, 5, 2);
1356
1357 static SENSOR_DEVICE_ATTR_2(in6_input, 0444, show_in, NULL, 6, 0);
1358 static SENSOR_DEVICE_ATTR_2(in6_min, 0644, show_in, set_in, 6, 1);
1359 static SENSOR_DEVICE_ATTR_2(in6_max, 0644, show_in, set_in, 6, 2);
1360
1361 static SENSOR_DEVICE_ATTR_2(in7_input, 0444, show_in, NULL, 7, 0);
1362 static SENSOR_DEVICE_ATTR_2(in7_min, 0644, show_in, set_in, 7, 1);
1363 static SENSOR_DEVICE_ATTR_2(in7_max, 0644, show_in, set_in, 7, 2);
1364
1365 static SENSOR_DEVICE_ATTR_2(in8_input, 0444, show_in, NULL, 8, 0);
1366 static SENSOR_DEVICE_ATTR_2(in9_input, 0444, show_in, NULL, 9, 0);
1367 static SENSOR_DEVICE_ATTR_2(in10_input, 0444, show_in, NULL, 10, 0);
1368 static SENSOR_DEVICE_ATTR_2(in11_input, 0444, show_in, NULL, 11, 0);
1369 static SENSOR_DEVICE_ATTR_2(in12_input, 0444, show_in, NULL, 12, 0);
1370
1371 /* Up to 6 temperatures */
1372 static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
1373                          char *buf)
1374 {
1375         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1376         int nr = sattr->nr;
1377         int index = sattr->index;
1378         struct it87_data *data = it87_update_device(dev);
1379
1380         if (IS_ERR(data))
1381                 return PTR_ERR(data);
1382
1383         return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1384 }
1385
1386 static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
1387                         const char *buf, size_t count)
1388 {
1389         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1390         int nr = sattr->nr;
1391         int index = sattr->index;
1392         struct it87_data *data = dev_get_drvdata(dev);
1393         long val;
1394         u8 reg, regval;
1395         int err;
1396
1397         if (kstrtol(buf, 10, &val) < 0)
1398                 return -EINVAL;
1399
1400         err = it87_lock(data);
1401         if (err)
1402                 return err;
1403
1404         switch (index) {
1405         default:
1406         case 1:
1407                 reg = data->REG_TEMP_LOW[nr];
1408                 break;
1409         case 2:
1410                 reg = data->REG_TEMP_HIGH[nr];
1411                 break;
1412         case 3:
1413                 regval = data->read(data, IT87_REG_BEEP_ENABLE);
1414                 if (!(regval & 0x80)) {
1415                         regval |= 0x80;
1416                         data->write(data, IT87_REG_BEEP_ENABLE, regval);
1417                 }
1418                 data->valid = 0;
1419                 reg = data->REG_TEMP_OFFSET[nr];
1420                 break;
1421         }
1422
1423         data->temp[nr][index] = TEMP_TO_REG(val);
1424         data->write(data, reg, data->temp[nr][index]);
1425         it87_unlock(data);
1426         return count;
1427 }
1428
1429 static SENSOR_DEVICE_ATTR_2(temp1_input, 0444, show_temp, NULL, 0, 0);
1430 static SENSOR_DEVICE_ATTR_2(temp1_min, 0644, show_temp, set_temp, 0, 1);
1431 static SENSOR_DEVICE_ATTR_2(temp1_max, 0644, show_temp, set_temp, 0, 2);
1432 static SENSOR_DEVICE_ATTR_2(temp1_offset, 0644, show_temp, set_temp, 0, 3);
1433 static SENSOR_DEVICE_ATTR_2(temp2_input, 0444, show_temp, NULL, 1, 0);
1434 static SENSOR_DEVICE_ATTR_2(temp2_min, 0644, show_temp, set_temp, 1, 1);
1435 static SENSOR_DEVICE_ATTR_2(temp2_max, 0644, show_temp, set_temp, 1, 2);
1436 static SENSOR_DEVICE_ATTR_2(temp2_offset, 0644, show_temp, set_temp, 1, 3);
1437 static SENSOR_DEVICE_ATTR_2(temp3_input, 0444, show_temp, NULL, 2, 0);
1438 static SENSOR_DEVICE_ATTR_2(temp3_min, 0644, show_temp, set_temp, 2, 1);
1439 static SENSOR_DEVICE_ATTR_2(temp3_max, 0644, show_temp, set_temp, 2, 2);
1440 static SENSOR_DEVICE_ATTR_2(temp3_offset, 0644, show_temp, set_temp, 2, 3);
1441 static SENSOR_DEVICE_ATTR_2(temp4_input, 0444, show_temp, NULL, 3, 0);
1442 static SENSOR_DEVICE_ATTR_2(temp4_min, 0644, show_temp, set_temp, 3, 1);
1443 static SENSOR_DEVICE_ATTR_2(temp4_max, 0644, show_temp, set_temp, 3, 2);
1444 static SENSOR_DEVICE_ATTR_2(temp4_offset, 0644, show_temp, set_temp, 3, 3);
1445 static SENSOR_DEVICE_ATTR_2(temp5_input, 0444, show_temp, NULL, 4, 0);
1446 static SENSOR_DEVICE_ATTR_2(temp5_min, 0644, show_temp, set_temp, 4, 1);
1447 static SENSOR_DEVICE_ATTR_2(temp5_max, 0644, show_temp, set_temp, 4, 2);
1448 static SENSOR_DEVICE_ATTR_2(temp5_offset, 0644, show_temp, set_temp, 4, 3);
1449 static SENSOR_DEVICE_ATTR_2(temp6_input, 0444, show_temp, NULL, 5, 0);
1450 static SENSOR_DEVICE_ATTR_2(temp6_min, 0644, show_temp, set_temp, 5, 1);
1451 static SENSOR_DEVICE_ATTR_2(temp6_max, 0644, show_temp, set_temp, 5, 2);
1452 static SENSOR_DEVICE_ATTR_2(temp6_offset, 0644, show_temp, set_temp, 5, 3);
1453
1454 static const u8 temp_types_8686[NUM_TEMP][9] = {
1455         { 0, 8, 8, 8, 8, 8, 8, 8, 7 },
1456         { 0, 6, 8, 8, 6, 0, 0, 0, 7 },
1457         { 0, 6, 5, 8, 6, 0, 0, 0, 7 },
1458         { 4, 8, 8, 8, 8, 8, 8, 8, 7 },
1459         { 4, 6, 8, 8, 6, 0, 0, 0, 7 },
1460         { 4, 6, 5, 8, 6, 0, 0, 0, 7 },
1461 };
1462
1463 static int get_temp_type(struct it87_data *data, int index)
1464 {
1465         u8 reg, extra;
1466         int ttype, type = 0;
1467
1468         if (has_bank_sel(data)) {
1469                 u8 src1, src2;
1470
1471                 src1 = (data->temp_src[index / 2] >> ((index % 2) * 4)) & 0x0f;
1472
1473                 switch (data->type) {
1474                 case it8686:
1475                         if (src1 < 9)
1476                                 type = temp_types_8686[index][src1];
1477                         break;
1478                 case it8625:
1479                         if (index < 3)
1480                                 break;
1481                 case it8655:
1482                 case it8665:
1483                         if (src1 < 3) {
1484                                 index = src1;
1485                                 break;
1486                         }
1487                         src2 = data->temp_src[3];
1488                         switch (src1) {
1489                         case 3:
1490                                 type = (src2 & BIT(index)) ? 6 : 5;
1491                                 break;
1492                         case 4 ... 8:
1493                                 type = (src2 & BIT(index)) ? 4 : 6;
1494                                 break;
1495                         case 9:
1496                                 type = (src2 & BIT(index)) ? 5 : 0;
1497                                 break;
1498                         default:
1499                                 break;
1500                         }
1501                         return type;
1502                 default:
1503                         return 0;
1504                 }
1505         }
1506         if (type)
1507                 return type;
1508
1509         /* Dectect PECI vs. AMDTSI */
1510         ttype = 6;
1511         if ((has_temp_peci(data, index)) || data->type == it8721 ||
1512             data->type == it8720) {
1513                 extra = data->read(data, IT87_REG_IFSEL);
1514                 if ((extra & 0x70) == 0x40)
1515                         ttype = 5;
1516         }
1517
1518         reg = data->read(data, IT87_REG_TEMP_ENABLE);
1519
1520         /* Per chip special detection */
1521         switch (data->type) {
1522         case it8622:
1523                 if (!(reg & 0xc0) && index == 3)
1524                         type = ttype;
1525                 break;
1526         default:
1527                 break;
1528         }
1529
1530         if (type || index >= 3)
1531                 return type;
1532
1533         extra = data->read(data, IT87_REG_TEMP_EXTRA);
1534
1535         if ((has_temp_peci(data, index) && (reg >> 6 == index + 1)) ||
1536             (has_temp_old_peci(data, index) && (extra & 0x80)))
1537                 type = ttype;           /* Intel PECI or AMDTSI */
1538         else if (reg & BIT(index))
1539                 type = 3;               /* thermal diode */
1540         else if (reg & BIT(index + 3))
1541                 type = 4;               /* thermistor */
1542
1543         return type;
1544 }
1545
1546 static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
1547                               char *buf)
1548 {
1549         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1550         struct it87_data *data = it87_update_device(dev);
1551         int type;
1552
1553         if (IS_ERR(data))
1554                 return PTR_ERR(data);
1555
1556         type = get_temp_type(data, sensor_attr->index);
1557         return sprintf(buf, "%d\n", type);
1558 }
1559
1560 static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
1561                              const char *buf, size_t count)
1562 {
1563         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1564         int nr = sensor_attr->index;
1565
1566         struct it87_data *data = dev_get_drvdata(dev);
1567         long val;
1568         u8 reg, extra;
1569         int err;
1570
1571         if (kstrtol(buf, 10, &val) < 0)
1572                 return -EINVAL;
1573
1574         err = it87_lock(data);
1575         if (err)
1576                 return err;
1577
1578         reg = data->read(data, IT87_REG_TEMP_ENABLE);
1579         reg &= ~(1 << nr);
1580         reg &= ~(8 << nr);
1581         if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
1582                 reg &= 0x3f;
1583         extra = data->read(data, IT87_REG_TEMP_EXTRA);
1584         if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
1585                 extra &= 0x7f;
1586         if (val == 2) { /* backwards compatibility */
1587                 dev_warn(dev,
1588                          "Sensor type 2 is deprecated, please use 4 instead\n");
1589                 val = 4;
1590         }
1591         /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1592         if (val == 3)
1593                 reg |= 1 << nr;
1594         else if (val == 4)
1595                 reg |= 8 << nr;
1596         else if (has_temp_peci(data, nr) && val == 6)
1597                 reg |= (nr + 1) << 6;
1598         else if (has_temp_old_peci(data, nr) && val == 6)
1599                 extra |= 0x80;
1600         else if (val != 0) {
1601                 count = -EINVAL;
1602                 goto unlock;
1603         }
1604
1605         data->sensor = reg;
1606         data->extra = extra;
1607         data->write(data, IT87_REG_TEMP_ENABLE, data->sensor);
1608         if (has_temp_old_peci(data, nr))
1609                 data->write(data, IT87_REG_TEMP_EXTRA, data->extra);
1610         data->valid = 0;        /* Force cache refresh */
1611 unlock:
1612         it87_unlock(data);
1613         return count;
1614 }
1615
1616 static SENSOR_DEVICE_ATTR(temp1_type, 0644, show_temp_type, set_temp_type, 0);
1617 static SENSOR_DEVICE_ATTR(temp2_type, 0644, show_temp_type, set_temp_type, 1);
1618 static SENSOR_DEVICE_ATTR(temp3_type, 0644, show_temp_type, set_temp_type, 2);
1619 static SENSOR_DEVICE_ATTR(temp4_type, 0644, show_temp_type, set_temp_type, 3);
1620 static SENSOR_DEVICE_ATTR(temp5_type, 0644, show_temp_type, set_temp_type, 4);
1621 static SENSOR_DEVICE_ATTR(temp6_type, 0644, show_temp_type, set_temp_type, 5);
1622
1623 /* 6 Fans */
1624
1625 static int pwm_mode(const struct it87_data *data, int nr)
1626 {
1627         if (has_fanctl_onoff(data) && nr < 3 &&
1628             !(data->fan_main_ctrl & BIT(nr)))
1629                 return 0;                               /* Full speed */
1630         if (data->pwm_ctrl[nr] & 0x80)
1631                 return 2;                               /* Automatic mode */
1632         if ((!has_fanctl_onoff(data) || nr >= 3) &&
1633             data->pwm_duty[nr] == pwm_to_reg(data, 0xff))
1634                 return 0;                       /* Full speed */
1635
1636         return 1;                               /* Manual mode */
1637 }
1638
1639 static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1640                         char *buf)
1641 {
1642         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1643         int nr = sattr->nr;
1644         int index = sattr->index;
1645         int speed;
1646         struct it87_data *data = it87_update_device(dev);
1647
1648         if (IS_ERR(data))
1649                 return PTR_ERR(data);
1650
1651         speed = has_16bit_fans(data) ?
1652                 FAN16_FROM_REG(data->fan[nr][index]) :
1653                 FAN_FROM_REG(data->fan[nr][index],
1654                              DIV_FROM_REG(data->fan_div[nr]));
1655         return sprintf(buf, "%d\n", speed);
1656 }
1657
1658 static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
1659                             char *buf)
1660 {
1661         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1662         struct it87_data *data = it87_update_device(dev);
1663         int nr = sensor_attr->index;
1664
1665         if (IS_ERR(data))
1666                 return PTR_ERR(data);
1667
1668         return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
1669 }
1670
1671 static ssize_t show_pwm_enable(struct device *dev,
1672                                struct device_attribute *attr, char *buf)
1673 {
1674         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1675         struct it87_data *data = it87_update_device(dev);
1676         int nr = sensor_attr->index;
1677
1678         if (IS_ERR(data))
1679                 return PTR_ERR(data);
1680
1681         return sprintf(buf, "%d\n", pwm_mode(data, nr));
1682 }
1683
1684 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1685                         char *buf)
1686 {
1687         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1688         struct it87_data *data = it87_update_device(dev);
1689         int nr = sensor_attr->index;
1690
1691         if (IS_ERR(data))
1692                 return PTR_ERR(data);
1693
1694         return sprintf(buf, "%d\n",
1695                        pwm_from_reg(data, data->pwm_duty[nr]));
1696 }
1697
1698 static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
1699                              char *buf)
1700 {
1701         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1702         struct it87_data *data = it87_update_device(dev);
1703         int nr = sensor_attr->index;
1704         unsigned int freq;
1705         int index;
1706
1707         if (IS_ERR(data))
1708                 return PTR_ERR(data);
1709
1710         if (has_pwm_freq2(data) && nr == 1)
1711                 index = (data->extra >> 4) & 0x07;
1712         else
1713                 index = (data->fan_ctl >> 4) & 0x07;
1714
1715         freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
1716
1717         return sprintf(buf, "%u\n", freq);
1718 }
1719
1720 static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1721                        const char *buf, size_t count)
1722 {
1723         struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1724         int nr = sattr->nr;
1725         int index = sattr->index;
1726
1727         struct it87_data *data = dev_get_drvdata(dev);
1728         long val;
1729         int err;
1730         u8 reg;
1731
1732         if (kstrtol(buf, 10, &val) < 0)
1733                 return -EINVAL;
1734
1735         err = it87_lock(data);
1736         if (err)
1737                 return err;
1738
1739         if (has_16bit_fans(data)) {
1740                 data->fan[nr][index] = FAN16_TO_REG(val);
1741                 data->write(data, data->REG_FAN_MIN[nr],
1742                             data->fan[nr][index] & 0xff);
1743                 data->write(data, data->REG_FANX_MIN[nr],
1744                             data->fan[nr][index] >> 8);
1745         } else {
1746                 reg = data->read(data, IT87_REG_FAN_DIV);
1747                 switch (nr) {
1748                 case 0:
1749                         data->fan_div[nr] = reg & 0x07;
1750                         break;
1751                 case 1:
1752                         data->fan_div[nr] = (reg >> 3) & 0x07;
1753                         break;
1754                 case 2:
1755                         data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
1756                         break;
1757                 }
1758                 data->fan[nr][index] =
1759                   FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
1760                 data->write(data, data->REG_FAN_MIN[nr], data->fan[nr][index]);
1761         }
1762         it87_unlock(data);
1763         return count;
1764 }
1765
1766 static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
1767                            const char *buf, size_t count)
1768 {
1769         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1770         struct it87_data *data = dev_get_drvdata(dev);
1771         int nr = sensor_attr->index;
1772         unsigned long val;
1773         int min, err;
1774         u8 old;
1775
1776         if (kstrtoul(buf, 10, &val) < 0)
1777                 return -EINVAL;
1778
1779         err = it87_lock(data);
1780         if (err)
1781                 return err;
1782
1783         old = data->read(data, IT87_REG_FAN_DIV);
1784
1785         /* Save fan min limit */
1786         min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1787
1788         switch (nr) {
1789         case 0:
1790         case 1:
1791                 data->fan_div[nr] = DIV_TO_REG(val);
1792                 break;
1793         case 2:
1794                 if (val < 8)
1795                         data->fan_div[nr] = 1;
1796                 else
1797                         data->fan_div[nr] = 3;
1798         }
1799         val = old & 0x80;
1800         val |= (data->fan_div[0] & 0x07);
1801         val |= (data->fan_div[1] & 0x07) << 3;
1802         if (data->fan_div[2] == 3)
1803                 val |= 0x1 << 6;
1804         data->write(data, IT87_REG_FAN_DIV, val);
1805
1806         /* Restore fan min limit */
1807         data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
1808         data->write(data, data->REG_FAN_MIN[nr], data->fan[nr][1]);
1809         it87_unlock(data);
1810         return count;
1811 }
1812
1813 /* Returns 0 if OK, -EINVAL otherwise */
1814 static int check_trip_points(struct device *dev, int nr)
1815 {
1816         const struct it87_data *data = dev_get_drvdata(dev);
1817         int i, err = 0;
1818
1819         if (has_old_autopwm(data)) {
1820                 for (i = 0; i < 3; i++) {
1821                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1822                                 err = -EINVAL;
1823                 }
1824                 for (i = 0; i < 2; i++) {
1825                         if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
1826                                 err = -EINVAL;
1827                 }
1828         } else if (has_newer_autopwm(data)) {
1829                 for (i = 1; i < 3; i++) {
1830                         if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1831                                 err = -EINVAL;
1832                 }
1833         }
1834
1835         if (err) {
1836                 dev_err(dev,
1837                         "Inconsistent trip points, not switching to automatic mode\n");
1838                 dev_err(dev, "Adjust the trip points and try again\n");
1839         }
1840         return err;
1841 }
1842
1843 static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr,
1844                               const char *buf, size_t count)
1845 {
1846         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1847         struct it87_data *data = dev_get_drvdata(dev);
1848         int nr = sensor_attr->index;
1849         long val;
1850         int err;
1851
1852         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
1853                 return -EINVAL;
1854
1855         /* Check trip points before switching to automatic mode */
1856         if (val == 2) {
1857                 if (check_trip_points(dev, nr) < 0)
1858                         return -EINVAL;
1859         }
1860
1861         err = it87_lock(data);
1862         if (err)
1863                 return err;
1864
1865         it87_update_pwm_ctrl(data, nr);
1866
1867         if (val == 0) {
1868                 if (nr < 3 && has_fanctl_onoff(data)) {
1869                         int tmp;
1870                         /* make sure the fan is on when in on/off mode */
1871                         tmp = data->read(data, IT87_REG_FAN_CTL);
1872                         data->write(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
1873                         /* set on/off mode */
1874                         data->fan_main_ctrl &= ~BIT(nr);
1875                         data->write(data, IT87_REG_FAN_MAIN_CTRL,
1876                                     data->fan_main_ctrl);
1877                 } else {
1878                         u8 ctrl;
1879
1880                         /* No on/off mode, set maximum pwm value */
1881                         data->pwm_duty[nr] = pwm_to_reg(data, 0xff);
1882                         data->write(data, IT87_REG_PWM_DUTY[nr],
1883                                     data->pwm_duty[nr]);
1884                         /* and set manual mode */
1885                         if (has_newer_autopwm(data)) {
1886                                 ctrl = temp_map_to_reg(data, nr,
1887                                                        data->pwm_temp_map[nr]);
1888                                 ctrl &= 0x7f;
1889                         } else {
1890                                 ctrl = data->pwm_duty[nr];
1891                         }
1892                         data->pwm_ctrl[nr] = ctrl;
1893                         data->write(data, data->REG_PWM[nr], ctrl);
1894                 }
1895         } else {
1896                 u8 ctrl;
1897
1898                 if (has_newer_autopwm(data)) {
1899                         ctrl = temp_map_to_reg(data, nr,
1900                                                data->pwm_temp_map[nr]);
1901                         if (val == 1)
1902                                 ctrl &= 0x7f;
1903                         else
1904                                 ctrl |= 0x80;
1905                 } else {
1906                         ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80);
1907                 }
1908                 data->pwm_ctrl[nr] = ctrl;
1909                 data->write(data, data->REG_PWM[nr], ctrl);
1910
1911                 if (has_fanctl_onoff(data) && nr < 3) {
1912                         /* set SmartGuardian mode */
1913                         data->fan_main_ctrl |= BIT(nr);
1914                         data->write(data, IT87_REG_FAN_MAIN_CTRL,
1915                                     data->fan_main_ctrl);
1916                 }
1917         }
1918         it87_unlock(data);
1919         return count;
1920 }
1921
1922 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1923                        const char *buf, size_t count)
1924 {
1925         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1926         struct it87_data *data = dev_get_drvdata(dev);
1927         int nr = sensor_attr->index;
1928         long val;
1929         int err;
1930
1931         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1932                 return -EINVAL;
1933
1934         err = it87_lock(data);
1935         if (err)
1936                 return err;
1937
1938         it87_update_pwm_ctrl(data, nr);
1939         if (has_newer_autopwm(data)) {
1940                 /*
1941                  * If we are in automatic mode, the PWM duty cycle register
1942                  * is read-only so we can't write the value.
1943                  */
1944                 if (data->pwm_ctrl[nr] & 0x80) {
1945                         count = -EBUSY;
1946                         goto unlock;
1947                 }
1948                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1949                 data->write(data, IT87_REG_PWM_DUTY[nr],
1950                             data->pwm_duty[nr]);
1951         } else {
1952                 data->pwm_duty[nr] = pwm_to_reg(data, val);
1953                 /*
1954                  * If we are in manual mode, write the duty cycle immediately;
1955                  * otherwise, just store it for later use.
1956                  */
1957                 if (!(data->pwm_ctrl[nr] & 0x80)) {
1958                         data->pwm_ctrl[nr] = data->pwm_duty[nr];
1959                         data->write(data, data->REG_PWM[nr],
1960                                     data->pwm_ctrl[nr]);
1961                 }
1962         }
1963 unlock:
1964         it87_unlock(data);
1965         return count;
1966 }
1967
1968 static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr,
1969                             const char *buf, size_t count)
1970 {
1971         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1972         struct it87_data *data = dev_get_drvdata(dev);
1973         int nr = sensor_attr->index;
1974         unsigned long val;
1975         int err;
1976         int i;
1977
1978         if (kstrtoul(buf, 10, &val) < 0)
1979                 return -EINVAL;
1980
1981         val = clamp_val(val, 0, 1000000);
1982         val *= has_newer_autopwm(data) ? 256 : 128;
1983
1984         /* Search for the nearest available frequency */
1985         for (i = 0; i < ARRAY_SIZE(pwm_freq) - 1; i++) {
1986                 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2)
1987                         break;
1988         }
1989
1990         err = it87_lock(data);
1991         if (err)
1992                 return err;
1993
1994         if (nr == 0) {
1995                 data->fan_ctl = data->read(data, IT87_REG_FAN_CTL) & 0x8f;
1996                 data->fan_ctl |= i << 4;
1997                 data->write(data, IT87_REG_FAN_CTL, data->fan_ctl);
1998         } else {
1999                 data->extra = data->read(data, IT87_REG_TEMP_EXTRA) & 0x8f;
2000                 data->extra |= i << 4;
2001                 data->write(data, IT87_REG_TEMP_EXTRA, data->extra);
2002         }
2003         it87_unlock(data);
2004         return count;
2005 }
2006
2007 static ssize_t show_pwm_temp_map(struct device *dev,
2008                                  struct device_attribute *attr, char *buf)
2009 {
2010         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
2011         struct it87_data *data = it87_update_device(dev);
2012         int nr = sensor_attr->index;
2013
2014         if (IS_ERR(data))
2015                 return PTR_ERR(data);
2016
2017         return sprintf(buf, "%d\n", data->pwm_temp_map[nr] + 1);
2018 }
2019
2020 static ssize_t set_pwm_temp_map(struct device *dev,
2021                                 struct device_attribute *attr, const char *buf,
2022                                 size_t count)
2023 {
2024         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
2025         struct it87_data *data = dev_get_drvdata(dev);
2026         int nr = sensor_attr->index;
2027         unsigned long val;
2028         int err;
2029         u8 map;
2030
2031         if (kstrtoul(buf, 10, &val) < 0)
2032                 return -EINVAL;
2033
2034         if (!val || val > data->pwm_num_temp_map)
2035                 return -EINVAL;
2036
2037         map = val - 1;
2038
2039         err = it87_lock(data);
2040         if (err)
2041                 return err;
2042
2043         it87_update_pwm_ctrl(data, nr);
2044         data->pwm_temp_map[nr] = map;
2045         /*
2046          * If we are in automatic mode, write the temp mapping immediately;
2047          * otherwise, just store it for later use.
2048          */
2049         if (data->pwm_ctrl[nr] & 0x80) {
2050                 data->pwm_ctrl[nr] = temp_map_to_reg(data, nr, map);
2051                 data->write(data, data->REG_PWM[nr], data->pwm_ctrl[nr]);
2052         }
2053         it87_unlock(data);
2054         return count;
2055 }
2056
2057 static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr,
2058                              char *buf)
2059 {
2060         struct it87_data *data = it87_update_device(dev);
2061         struct sensor_device_attribute_2 *sensor_attr =
2062                         to_sensor_dev_attr_2(attr);
2063         int nr = sensor_attr->nr;
2064         int point = sensor_attr->index;
2065
2066         if (IS_ERR(data))
2067                 return PTR_ERR(data);
2068
2069         return sprintf(buf, "%d\n",
2070                        pwm_from_reg(data, data->auto_pwm[nr][point]));
2071 }
2072
2073 static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr,
2074                             const char *buf, size_t count)
2075 {
2076         struct it87_data *data = dev_get_drvdata(dev);
2077         struct sensor_device_attribute_2 *sensor_attr =
2078                         to_sensor_dev_attr_2(attr);
2079         int nr = sensor_attr->nr;
2080         int point = sensor_attr->index;
2081         int regaddr;
2082         long val;
2083         int err;
2084
2085         if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
2086                 return -EINVAL;
2087
2088         err = it87_lock(data);
2089         if (err)
2090                 return err;
2091
2092         data->auto_pwm[nr][point] = pwm_to_reg(data, val);
2093         if (has_newer_autopwm(data))
2094                 regaddr = IT87_REG_AUTO_TEMP(nr, 3);
2095         else
2096                 regaddr = IT87_REG_AUTO_PWM(nr, point);
2097         data->write(data, regaddr, data->auto_pwm[nr][point]);
2098         it87_unlock(data);
2099         return count;
2100 }
2101
2102 static ssize_t show_auto_pwm_slope(struct device *dev,
2103                                    struct device_attribute *attr, char *buf)
2104 {
2105         struct it87_data *data = it87_update_device(dev);
2106         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
2107         int nr = sensor_attr->index;
2108
2109         if (IS_ERR(data))
2110                 return PTR_ERR(data);
2111
2112         return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f);
2113 }
2114
2115 static ssize_t set_auto_pwm_slope(struct device *dev,
2116                                   struct device_attribute *attr,
2117                                   const char *buf, size_t count)
2118 {
2119         struct it87_data *data = dev_get_drvdata(dev);
2120         struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
2121         int nr = sensor_attr->index;
2122         unsigned long val;
2123         int err;
2124
2125         if (kstrtoul(buf, 10, &val) < 0 || val > 127)
2126                 return -EINVAL;
2127
2128         err = it87_lock(data);
2129         if (err)
2130                 return err;
2131
2132         data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val;
2133         data->write(data, IT87_REG_AUTO_TEMP(nr, 4), data->auto_pwm[nr][1]);
2134         it87_unlock(data);
2135         return count;
2136 }
2137
2138 static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr,
2139                               char *buf)
2140 {
2141         struct it87_data *data = it87_update_device(dev);
2142         struct sensor_device_attribute_2 *sensor_attr =
2143                         to_sensor_dev_attr_2(attr);
2144         int nr = sensor_attr->nr;
2145         int point = sensor_attr->index;
2146         int reg;
2147
2148         if (IS_ERR(data))
2149                 return PTR_ERR(data);
2150
2151         if (has_old_autopwm(data) || point)
2152                 reg = data->auto_temp[nr][point];
2153         else
2154                 reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f);
2155
2156         return sprintf(buf, "%d\n", TEMP_FROM_REG(reg));
2157 }
2158
2159 static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr,
2160                              const char *buf, size_t count)
2161 {
2162         struct it87_data *data = dev_get_drvdata(dev);
2163         struct sensor_device_attribute_2 *sensor_attr =
2164                         to_sensor_dev_attr_2(attr);
2165         int nr = sensor_attr->nr;
2166         int point = sensor_attr->index;
2167         long val;
2168         int reg;
2169         int err;
2170
2171         if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
2172                 return -EINVAL;
2173
2174         err = it87_lock(data);
2175         if (err)
2176                 return err;
2177
2178         if (has_newer_autopwm(data) && !point) {
2179                 reg = data->auto_temp[nr][1] - TEMP_TO_REG(val);
2180                 reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0);
2181                 data->auto_temp[nr][0] = reg;
2182                 data->write(data, IT87_REG_AUTO_TEMP(nr, 5), reg);
2183         } else {
2184                 reg = TEMP_TO_REG(val);
2185                 data->auto_temp[nr][point] = reg;
2186                 if (has_newer_autopwm(data))
2187                         point--;
2188                 data->write(data, IT87_REG_AUTO_TEMP(nr, point), reg);
2189         }
2190         it87_unlock(data);
2191         return count;
2192 }
2193
2194 static SENSOR_DEVICE_ATTR_2(fan1_input, 0444, show_fan, NULL, 0, 0);
2195 static SENSOR_DEVICE_ATTR_2(fan1_min, 0644, show_fan, set_fan, 0, 1);
2196 static SENSOR_DEVICE_ATTR(fan1_div, 0644, show_fan_div, set_fan_div, 0);
2197
2198 static SENSOR_DEVICE_ATTR_2(fan2_input, 0444, show_fan, NULL, 1, 0);
2199 static SENSOR_DEVICE_ATTR_2(fan2_min, 0644, show_fan, set_fan, 1, 1);
2200 static SENSOR_DEVICE_ATTR(fan2_div, 0644, show_fan_div, set_fan_div, 1);
2201
2202 static SENSOR_DEVICE_ATTR_2(fan3_input, 0444, show_fan, NULL, 2, 0);
2203 static SENSOR_DEVICE_ATTR_2(fan3_min, 0644, show_fan, set_fan, 2, 1);
2204 static SENSOR_DEVICE_ATTR(fan3_div, 0644, show_fan_div, set_fan_div, 2);
2205
2206 static SENSOR_DEVICE_ATTR_2(fan4_input, 0444, show_fan, NULL, 3, 0);
2207 static SENSOR_DEVICE_ATTR_2(fan4_min, 0644, show_fan, set_fan, 3, 1);
2208
2209 static SENSOR_DEVICE_ATTR_2(fan5_input, 0444, show_fan, NULL, 4, 0);
2210 static SENSOR_DEVICE_ATTR_2(fan5_min, 0644, show_fan, set_fan, 4, 1);
2211
2212 static SENSOR_DEVICE_ATTR_2(fan6_input, 0444, show_fan, NULL, 5, 0);
2213 static SENSOR_DEVICE_ATTR_2(fan6_min, 0644, show_fan, set_fan, 5, 1);
2214
2215 static SENSOR_DEVICE_ATTR(pwm1_enable, 0644,
2216                           show_pwm_enable, set_pwm_enable, 0);
2217 static SENSOR_DEVICE_ATTR(pwm1, 0644, show_pwm, set_pwm, 0);
2218 static SENSOR_DEVICE_ATTR(pwm1_freq, 0644, show_pwm_freq, set_pwm_freq, 0);
2219 static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, 0444,
2220                           show_pwm_temp_map, set_pwm_temp_map, 0);
2221 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, 0644,
2222                             show_auto_pwm, set_auto_pwm, 0, 0);
2223 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, 0644,
2224                             show_auto_pwm, set_auto_pwm, 0, 1);
2225 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, 0644,
2226                             show_auto_pwm, set_auto_pwm, 0, 2);
2227 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, 0444,
2228                             show_auto_pwm, NULL, 0, 3);
2229 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, 0644,
2230                             show_auto_temp, set_auto_temp, 0, 1);
2231 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, 0644,
2232                             show_auto_temp, set_auto_temp, 0, 0);
2233 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, 0644,
2234                             show_auto_temp, set_auto_temp, 0, 2);
2235 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, 0644,
2236                             show_auto_temp, set_auto_temp, 0, 3);
2237 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, 0644,
2238                             show_auto_temp, set_auto_temp, 0, 4);
2239 static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, 0644,
2240                             show_auto_pwm, set_auto_pwm, 0, 0);
2241 static SENSOR_DEVICE_ATTR(pwm1_auto_slope, 0644,
2242                           show_auto_pwm_slope, set_auto_pwm_slope, 0);
2243
2244 static SENSOR_DEVICE_ATTR(pwm2_enable, 0644,
2245                           show_pwm_enable, set_pwm_enable, 1);
2246 static SENSOR_DEVICE_ATTR(pwm2, 0644, show_pwm, set_pwm, 1);
2247 static SENSOR_DEVICE_ATTR(pwm2_freq, 0444, show_pwm_freq, set_pwm_freq, 1);
2248 static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, 0444,
2249                           show_pwm_temp_map, set_pwm_temp_map, 1);
2250 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, 0644,
2251                             show_auto_pwm, set_auto_pwm, 1, 0);
2252 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, 0644,
2253                             show_auto_pwm, set_auto_pwm, 1, 1);
2254 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, 0644,
2255                             show_auto_pwm, set_auto_pwm, 1, 2);
2256 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, 0444,
2257                             show_auto_pwm, NULL, 1, 3);
2258 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, 0644,
2259                             show_auto_temp, set_auto_temp, 1, 1);
2260 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, 0644,
2261                             show_auto_temp, set_auto_temp, 1, 0);
2262 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, 0644,
2263                             show_auto_temp, set_auto_temp, 1, 2);
2264 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, 0644,
2265                             show_auto_temp, set_auto_temp, 1, 3);
2266 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, 0644,
2267                             show_auto_temp, set_auto_temp, 1, 4);
2268 static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, 0644,
2269                             show_auto_pwm, set_auto_pwm, 1, 0);
2270 static SENSOR_DEVICE_ATTR(pwm2_auto_slope, 0644,
2271                           show_auto_pwm_slope, set_auto_pwm_slope, 1);
2272
2273 static SENSOR_DEVICE_ATTR(pwm3_enable, 0644,
2274                           show_pwm_enable, set_pwm_enable, 2);
2275 static SENSOR_DEVICE_ATTR(pwm3, 0644, show_pwm, set_pwm, 2);
2276 static SENSOR_DEVICE_ATTR(pwm3_freq, 0444, show_pwm_freq, NULL, 2);
2277 static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, 0444,
2278                           show_pwm_temp_map, set_pwm_temp_map, 2);
2279 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, 0644,
2280                             show_auto_pwm, set_auto_pwm, 2, 0);
2281 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, 0644,
2282                             show_auto_pwm, set_auto_pwm, 2, 1);
2283 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, 0644,
2284                             show_auto_pwm, set_auto_pwm, 2, 2);
2285 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, 0444,
2286                             show_auto_pwm, NULL, 2, 3);
2287 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, 0644,
2288                             show_auto_temp, set_auto_temp, 2, 1);
2289 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, 0644,
2290                             show_auto_temp, set_auto_temp, 2, 0);
2291 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, 0644,
2292                             show_auto_temp, set_auto_temp, 2, 2);
2293 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, 0644,
2294                             show_auto_temp, set_auto_temp, 2, 3);
2295 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, 0644,
2296                             show_auto_temp, set_auto_temp, 2, 4);
2297 static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, 0644,
2298                             show_auto_pwm, set_auto_pwm, 2, 0);
2299 static SENSOR_DEVICE_ATTR(pwm3_auto_slope, 0644,
2300                           show_auto_pwm_slope, set_auto_pwm_slope, 2);
2301
2302 static SENSOR_DEVICE_ATTR(pwm4_enable, 0644,
2303                           show_pwm_enable, set_pwm_enable, 3);
2304 static SENSOR_DEVICE_ATTR(pwm4, 0644, show_pwm, set_pwm, 3);
2305 static SENSOR_DEVICE_ATTR(pwm4_freq, 0444, show_pwm_freq, NULL, 3);
2306 static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, 0444,
2307                           show_pwm_temp_map, set_pwm_temp_map, 3);
2308 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, 0644,
2309                             show_auto_temp, set_auto_temp, 2, 1);
2310 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, 0644,
2311                             show_auto_temp, set_auto_temp, 2, 0);
2312 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, 0644,
2313                             show_auto_temp, set_auto_temp, 2, 2);
2314 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, 0644,
2315                             show_auto_temp, set_auto_temp, 2, 3);
2316 static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, 0644,
2317                             show_auto_pwm, set_auto_pwm, 3, 0);
2318 static SENSOR_DEVICE_ATTR(pwm4_auto_slope, 0644,
2319                           show_auto_pwm_slope, set_auto_pwm_slope, 3);
2320
2321 static SENSOR_DEVICE_ATTR(pwm5_enable, 0644,
2322                           show_pwm_enable, set_pwm_enable, 4);
2323 static SENSOR_DEVICE_ATTR(pwm5, 0644, show_pwm, set_pwm, 4);
2324 static SENSOR_DEVICE_ATTR(pwm5_freq, 0444, show_pwm_freq, NULL, 4);
2325 static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, 0444,
2326                           show_pwm_temp_map, set_pwm_temp_map, 4);
2327 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, 0644,
2328                             show_auto_temp, set_auto_temp, 2, 1);
2329 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, 0644,
2330                             show_auto_temp, set_auto_temp, 2, 0);
2331 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, 0644,
2332                             show_auto_temp, set_auto_temp, 2, 2);
2333 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, 0644,
2334                             show_auto_temp, set_auto_temp, 2, 3);
2335 static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, 0644,
2336                             show_auto_pwm, set_auto_pwm, 4, 0);
2337 static SENSOR_DEVICE_ATTR(pwm5_auto_slope, 0644,
2338                           show_auto_pwm_slope, set_auto_pwm_slope, 4);
2339
2340 static SENSOR_DEVICE_ATTR(pwm6_enable, 0644,
2341                           show_pwm_enable, set_pwm_enable, 5);
2342 static SENSOR_DEVICE_ATTR(pwm6, 0644, show_pwm, set_pwm, 5);
2343 static SENSOR_DEVICE_ATTR(pwm6_freq, 0444, show_pwm_freq, NULL, 5);
2344 static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, 0444,
2345                           show_pwm_temp_map, set_pwm_temp_map, 5);
2346 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, 0644,
2347                             show_auto_temp, set_auto_temp, 2, 1);
2348 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, 0644,
2349                             show_auto_temp, set_auto_temp, 2, 0);
2350 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, 0644,
2351                             show_auto_temp, set_auto_temp, 2, 2);
2352 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, 0644,
2353                             show_auto_temp, set_auto_temp, 2, 3);
2354 static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, 0644,
2355                             show_auto_pwm, set_auto_pwm, 5, 0);
2356 static SENSOR_DEVICE_ATTR(pwm6_auto_slope, 0644,
2357                           show_auto_pwm_slope, set_auto_pwm_slope, 5);
2358
2359 /* Alarms */
2360 static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
2361                            char *buf)
2362 {
2363         struct it87_data *data = it87_update_device(dev);
2364
2365         if (IS_ERR(data))
2366                 return PTR_ERR(data);
2367
2368         return sprintf(buf, "%u\n", data->alarms);
2369 }
2370 static DEVICE_ATTR(alarms, 0444, show_alarms, NULL);
2371
2372 static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
2373                           char *buf)
2374 {
2375         struct it87_data *data = it87_update_device(dev);
2376         int bitnr = to_sensor_dev_attr(attr)->index;
2377
2378         if (IS_ERR(data))
2379                 return PTR_ERR(data);
2380
2381         return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
2382 }
2383
2384 static ssize_t clear_intrusion(struct device *dev,
2385                                struct device_attribute *attr, const char *buf,
2386                                size_t count)
2387 {
2388         struct it87_data *data = dev_get_drvdata(dev);
2389         int err, config;
2390         long val;
2391
2392         if (kstrtol(buf, 10, &val) < 0 || val != 0)
2393                 return -EINVAL;
2394
2395         err = it87_lock(data);
2396         if (err)
2397                 return err;
2398
2399         config = data->read(data, IT87_REG_CONFIG);
2400         config |= BIT(5);
2401         data->write(data, IT87_REG_CONFIG, config);
2402         /* Invalidate cache to force re-read */
2403         data->valid = 0;
2404         it87_unlock(data);
2405         return count;
2406 }
2407
2408 static SENSOR_DEVICE_ATTR(in0_alarm, 0444, show_alarm, NULL, 8);
2409 static SENSOR_DEVICE_ATTR(in1_alarm, 0444, show_alarm, NULL, 9);
2410 static SENSOR_DEVICE_ATTR(in2_alarm, 0444, show_alarm, NULL, 10);
2411 static SENSOR_DEVICE_ATTR(in3_alarm, 0444, show_alarm, NULL, 11);
2412 static SENSOR_DEVICE_ATTR(in4_alarm, 0444, show_alarm, NULL, 12);
2413 static SENSOR_DEVICE_ATTR(in5_alarm, 0444, show_alarm, NULL, 13);
2414 static SENSOR_DEVICE_ATTR(in6_alarm, 0444, show_alarm, NULL, 14);
2415 static SENSOR_DEVICE_ATTR(in7_alarm, 0444, show_alarm, NULL, 15);
2416 static SENSOR_DEVICE_ATTR(fan1_alarm, 0444, show_alarm, NULL, 0);
2417 static SENSOR_DEVICE_ATTR(fan2_alarm, 0444, show_alarm, NULL, 1);
2418 static SENSOR_DEVICE_ATTR(fan3_alarm, 0444, show_alarm, NULL, 2);
2419 static SENSOR_DEVICE_ATTR(fan4_alarm, 0444, show_alarm, NULL, 3);
2420 static SENSOR_DEVICE_ATTR(fan5_alarm, 0444, show_alarm, NULL, 6);
2421 static SENSOR_DEVICE_ATTR(fan6_alarm, 0444, show_alarm, NULL, 7);
2422 static SENSOR_DEVICE_ATTR(temp1_alarm, 0444, show_alarm, NULL, 16);
2423 static SENSOR_DEVICE_ATTR(temp2_alarm, 0444, show_alarm, NULL, 17);
2424 static SENSOR_DEVICE_ATTR(temp3_alarm, 0444, show_alarm, NULL, 18);
2425 static SENSOR_DEVICE_ATTR(temp4_alarm, 0444, show_alarm, NULL, 19);
2426 static SENSOR_DEVICE_ATTR(temp5_alarm, 0444, show_alarm, NULL, 20);
2427 static SENSOR_DEVICE_ATTR(temp6_alarm, 0444, show_alarm, NULL, 21);
2428 static SENSOR_DEVICE_ATTR(intrusion0_alarm, 0644,
2429                           show_alarm, clear_intrusion, 4);
2430
2431 static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
2432                          char *buf)
2433 {
2434         struct it87_data *data = it87_update_device(dev);
2435         int bitnr = to_sensor_dev_attr(attr)->index;
2436
2437         if (IS_ERR(data))
2438                 return PTR_ERR(data);
2439
2440         return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
2441 }
2442
2443 static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
2444                         const char *buf, size_t count)
2445 {
2446         int bitnr = to_sensor_dev_attr(attr)->index;
2447         struct it87_data *data = dev_get_drvdata(dev);
2448         long val;
2449         int err;
2450
2451         if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1))
2452                 return -EINVAL;
2453
2454         err = it87_lock(data);
2455         if (err)
2456                 return err;
2457
2458         data->beeps = data->read(data, IT87_REG_BEEP_ENABLE);
2459         if (val)
2460                 data->beeps |= BIT(bitnr);
2461         else
2462                 data->beeps &= ~BIT(bitnr);
2463         data->write(data, IT87_REG_BEEP_ENABLE, data->beeps);
2464         it87_unlock(data);
2465         return count;
2466 }
2467
2468 static SENSOR_DEVICE_ATTR(in0_beep, 0644,
2469                           show_beep, set_beep, 1);
2470 static SENSOR_DEVICE_ATTR(in1_beep, 0444, show_beep, NULL, 1);
2471 static SENSOR_DEVICE_ATTR(in2_beep, 0444, show_beep, NULL, 1);
2472 static SENSOR_DEVICE_ATTR(in3_beep, 0444, show_beep, NULL, 1);
2473 static SENSOR_DEVICE_ATTR(in4_beep, 0444, show_beep, NULL, 1);
2474 static SENSOR_DEVICE_ATTR(in5_beep, 0444, show_beep, NULL, 1);
2475 static SENSOR_DEVICE_ATTR(in6_beep, 0444, show_beep, NULL, 1);
2476 static SENSOR_DEVICE_ATTR(in7_beep, 0444, show_beep, NULL, 1);
2477 /* fanX_beep writability is set later */
2478 static SENSOR_DEVICE_ATTR(fan1_beep, 0444, show_beep, set_beep, 0);
2479 static SENSOR_DEVICE_ATTR(fan2_beep, 0444, show_beep, set_beep, 0);
2480 static SENSOR_DEVICE_ATTR(fan3_beep, 0444, show_beep, set_beep, 0);
2481 static SENSOR_DEVICE_ATTR(fan4_beep, 0444, show_beep, set_beep, 0);
2482 static SENSOR_DEVICE_ATTR(fan5_beep, 0444, show_beep, set_beep, 0);
2483 static SENSOR_DEVICE_ATTR(fan6_beep, 0444, show_beep, set_beep, 0);
2484 static SENSOR_DEVICE_ATTR(temp1_beep, 0644,
2485                           show_beep, set_beep, 2);
2486 static SENSOR_DEVICE_ATTR(temp2_beep, 0444, show_beep, NULL, 2);
2487 static SENSOR_DEVICE_ATTR(temp3_beep, 0444, show_beep, NULL, 2);
2488 static SENSOR_DEVICE_ATTR(temp4_beep, 0444, show_beep, NULL, 2);
2489 static SENSOR_DEVICE_ATTR(temp5_beep, 0444, show_beep, NULL, 2);
2490 static SENSOR_DEVICE_ATTR(temp6_beep, 0444, show_beep, NULL, 2);
2491
2492 static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
2493                             char *buf)
2494 {
2495         struct it87_data *data = dev_get_drvdata(dev);
2496
2497         return sprintf(buf, "%u\n", data->vrm);
2498 }
2499
2500 static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
2501                              const char *buf, size_t count)
2502 {
2503         struct it87_data *data = dev_get_drvdata(dev);
2504         unsigned long val;
2505
2506         if (kstrtoul(buf, 10, &val) < 0)
2507                 return -EINVAL;
2508
2509         data->vrm = val;
2510
2511         return count;
2512 }
2513 static DEVICE_ATTR(vrm, 0644, show_vrm_reg, store_vrm_reg);
2514
2515 static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
2516                             char *buf)
2517 {
2518         struct it87_data *data = it87_update_device(dev);
2519
2520         if (IS_ERR(data))
2521                 return PTR_ERR(data);
2522
2523         return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm));
2524 }
2525 static DEVICE_ATTR(cpu0_vid, 0444, show_vid_reg, NULL);
2526
2527 static ssize_t show_label(struct device *dev, struct device_attribute *attr,
2528                           char *buf)
2529 {
2530         static const char * const labels[] = {
2531                 "+5V",
2532                 "5VSB",
2533                 "Vbat",
2534                 "AVCC",
2535         };
2536         static const char * const labels_it8721[] = {
2537                 "+3.3V",
2538                 "3VSB",
2539                 "Vbat",
2540                 "+3.3V",
2541         };
2542         struct it87_data *data = dev_get_drvdata(dev);
2543         int nr = to_sensor_dev_attr(attr)->index;
2544         const char *label;
2545
2546         if (has_vin3_5v(data) && nr == 0)
2547                 label = labels[0];
2548         else if (has_12mv_adc(data) || has_10_9mv_adc(data) ||
2549                  has_11mv_adc(data))
2550                 label = labels_it8721[nr];
2551         else
2552                 label = labels[nr];
2553
2554         return sprintf(buf, "%s\n", label);
2555 }
2556 static SENSOR_DEVICE_ATTR(in3_label, 0444, show_label, NULL, 0);
2557 static SENSOR_DEVICE_ATTR(in7_label, 0444, show_label, NULL, 1);
2558 static SENSOR_DEVICE_ATTR(in8_label, 0444, show_label, NULL, 2);
2559 /* AVCC3 */
2560 static SENSOR_DEVICE_ATTR(in9_label, 0444, show_label, NULL, 3);
2561
2562 static umode_t it87_in_is_visible(struct kobject *kobj,
2563                                   struct attribute *attr, int index)
2564 {
2565         struct device *dev = container_of(kobj, struct device, kobj);
2566         struct it87_data *data = dev_get_drvdata(dev);
2567         int i = index / 5;      /* voltage index */
2568         int a = index % 5;      /* attribute index */
2569
2570         if (index >= 40) {      /* in8 and higher only have input attributes */
2571                 i = index - 40 + 8;
2572                 a = 0;
2573         }
2574
2575         if (!(data->has_in & BIT(i)))
2576                 return 0;
2577
2578         if (a == 4 && !data->has_beep)
2579                 return 0;
2580
2581         return attr->mode;
2582 }
2583
2584 static struct attribute *it87_attributes_in[] = {
2585         &sensor_dev_attr_in0_input.dev_attr.attr,
2586         &sensor_dev_attr_in0_min.dev_attr.attr,
2587         &sensor_dev_attr_in0_max.dev_attr.attr,
2588         &sensor_dev_attr_in0_alarm.dev_attr.attr,
2589         &sensor_dev_attr_in0_beep.dev_attr.attr,        /* 4 */
2590
2591         &sensor_dev_attr_in1_input.dev_attr.attr,
2592         &sensor_dev_attr_in1_min.dev_attr.attr,
2593         &sensor_dev_attr_in1_max.dev_attr.attr,
2594         &sensor_dev_attr_in1_alarm.dev_attr.attr,
2595         &sensor_dev_attr_in1_beep.dev_attr.attr,        /* 9 */
2596
2597         &sensor_dev_attr_in2_input.dev_attr.attr,
2598         &sensor_dev_attr_in2_min.dev_attr.attr,
2599         &sensor_dev_attr_in2_max.dev_attr.attr,
2600         &sensor_dev_attr_in2_alarm.dev_attr.attr,
2601         &sensor_dev_attr_in2_beep.dev_attr.attr,        /* 14 */
2602
2603         &sensor_dev_attr_in3_input.dev_attr.attr,
2604         &sensor_dev_attr_in3_min.dev_attr.attr,
2605         &sensor_dev_attr_in3_max.dev_attr.attr,
2606         &sensor_dev_attr_in3_alarm.dev_attr.attr,
2607         &sensor_dev_attr_in3_beep.dev_attr.attr,        /* 19 */
2608
2609         &sensor_dev_attr_in4_input.dev_attr.attr,
2610         &sensor_dev_attr_in4_min.dev_attr.attr,
2611         &sensor_dev_attr_in4_max.dev_attr.attr,
2612         &sensor_dev_attr_in4_alarm.dev_attr.attr,
2613         &sensor_dev_attr_in4_beep.dev_attr.attr,        /* 24 */
2614
2615         &sensor_dev_attr_in5_input.dev_attr.attr,
2616         &sensor_dev_attr_in5_min.dev_attr.attr,
2617         &sensor_dev_attr_in5_max.dev_attr.attr,
2618         &sensor_dev_attr_in5_alarm.dev_attr.attr,
2619         &sensor_dev_attr_in5_beep.dev_attr.attr,        /* 29 */
2620
2621         &sensor_dev_attr_in6_input.dev_attr.attr,
2622         &sensor_dev_attr_in6_min.dev_attr.attr,
2623         &sensor_dev_attr_in6_max.dev_attr.attr,
2624         &sensor_dev_attr_in6_alarm.dev_attr.attr,
2625         &sensor_dev_attr_in6_beep.dev_attr.attr,        /* 34 */
2626
2627         &sensor_dev_attr_in7_input.dev_attr.attr,
2628         &sensor_dev_attr_in7_min.dev_attr.attr,
2629         &sensor_dev_attr_in7_max.dev_attr.attr,
2630         &sensor_dev_attr_in7_alarm.dev_attr.attr,
2631         &sensor_dev_attr_in7_beep.dev_attr.attr,        /* 39 */
2632
2633         &sensor_dev_attr_in8_input.dev_attr.attr,       /* 40 */
2634         &sensor_dev_attr_in9_input.dev_attr.attr,       /* 41 */
2635         &sensor_dev_attr_in10_input.dev_attr.attr,      /* 42 */
2636         &sensor_dev_attr_in11_input.dev_attr.attr,      /* 43 */
2637         &sensor_dev_attr_in12_input.dev_attr.attr,      /* 44 */
2638         NULL
2639 };
2640
2641 static const struct attribute_group it87_group_in = {
2642         .attrs = it87_attributes_in,
2643         .is_visible = it87_in_is_visible,
2644 };
2645
2646 static umode_t it87_temp_is_visible(struct kobject *kobj,
2647                                     struct attribute *attr, int index)
2648 {
2649         struct device *dev = container_of(kobj, struct device, kobj);
2650         struct it87_data *data = dev_get_drvdata(dev);
2651         int i = index / 7;      /* temperature index */
2652         int a = index % 7;      /* attribute index */
2653
2654         if (!(data->has_temp & BIT(i)))
2655                 return 0;
2656
2657         if (a && i >= data->num_temp_limit)
2658                 return 0;
2659
2660         if (a == 3) {
2661                 int type = get_temp_type(data, i);
2662
2663                 if (type == 0)
2664                         return 0;
2665                 if (has_bank_sel(data))
2666                         return 0444;
2667                 return attr->mode;
2668         }
2669
2670         if (a == 5 && i >= data->num_temp_offset)
2671                 return 0;
2672
2673         if (a == 6 && !data->has_beep)
2674                 return 0;
2675
2676         return attr->mode;
2677 }
2678
2679 static struct attribute *it87_attributes_temp[] = {
2680         &sensor_dev_attr_temp1_input.dev_attr.attr,
2681         &sensor_dev_attr_temp1_max.dev_attr.attr,
2682         &sensor_dev_attr_temp1_min.dev_attr.attr,
2683         &sensor_dev_attr_temp1_type.dev_attr.attr,      /* 3 */
2684         &sensor_dev_attr_temp1_alarm.dev_attr.attr,
2685         &sensor_dev_attr_temp1_offset.dev_attr.attr,    /* 5 */
2686         &sensor_dev_attr_temp1_beep.dev_attr.attr,      /* 6 */
2687
2688         &sensor_dev_attr_temp2_input.dev_attr.attr,     /* 7 */
2689         &sensor_dev_attr_temp2_max.dev_attr.attr,
2690         &sensor_dev_attr_temp2_min.dev_attr.attr,
2691         &sensor_dev_attr_temp2_type.dev_attr.attr,
2692         &sensor_dev_attr_temp2_alarm.dev_attr.attr,
2693         &sensor_dev_attr_temp2_offset.dev_attr.attr,
2694         &sensor_dev_attr_temp2_beep.dev_attr.attr,
2695
2696         &sensor_dev_attr_temp3_input.dev_attr.attr,     /* 14 */
2697         &sensor_dev_attr_temp3_max.dev_attr.attr,
2698         &sensor_dev_attr_temp3_min.dev_attr.attr,
2699         &sensor_dev_attr_temp3_type.dev_attr.attr,
2700         &sensor_dev_attr_temp3_alarm.dev_attr.attr,
2701         &sensor_dev_attr_temp3_offset.dev_attr.attr,
2702         &sensor_dev_attr_temp3_beep.dev_attr.attr,
2703
2704         &sensor_dev_attr_temp4_input.dev_attr.attr,     /* 21 */
2705         &sensor_dev_attr_temp4_max.dev_attr.attr,
2706         &sensor_dev_attr_temp4_min.dev_attr.attr,
2707         &sensor_dev_attr_temp4_type.dev_attr.attr,
2708         &sensor_dev_attr_temp4_alarm.dev_attr.attr,
2709         &sensor_dev_attr_temp4_offset.dev_attr.attr,
2710         &sensor_dev_attr_temp4_beep.dev_attr.attr,
2711
2712         &sensor_dev_attr_temp5_input.dev_attr.attr,
2713         &sensor_dev_attr_temp5_max.dev_attr.attr,
2714         &sensor_dev_attr_temp5_min.dev_attr.attr,
2715         &sensor_dev_attr_temp5_type.dev_attr.attr,
2716         &sensor_dev_attr_temp5_alarm.dev_attr.attr,
2717         &sensor_dev_attr_temp5_offset.dev_attr.attr,
2718         &sensor_dev_attr_temp5_beep.dev_attr.attr,
2719
2720         &sensor_dev_attr_temp6_input.dev_attr.attr,
2721         &sensor_dev_attr_temp6_max.dev_attr.attr,
2722         &sensor_dev_attr_temp6_min.dev_attr.attr,
2723         &sensor_dev_attr_temp6_type.dev_attr.attr,
2724         &sensor_dev_attr_temp6_alarm.dev_attr.attr,
2725         &sensor_dev_attr_temp6_offset.dev_attr.attr,
2726         &sensor_dev_attr_temp6_beep.dev_attr.attr,
2727         NULL
2728 };
2729
2730 static const struct attribute_group it87_group_temp = {
2731         .attrs = it87_attributes_temp,
2732         .is_visible = it87_temp_is_visible,
2733 };
2734
2735 static umode_t it87_is_visible(struct kobject *kobj,
2736                                struct attribute *attr, int index)
2737 {
2738         struct device *dev = container_of(kobj, struct device, kobj);
2739         struct it87_data *data = dev_get_drvdata(dev);
2740
2741         if ((index == 2 || index == 3) && !data->has_vid)
2742                 return 0;
2743
2744         if (index > 3 && !(data->in_internal & BIT(index - 4)))
2745                 return 0;
2746
2747         return attr->mode;
2748 }
2749
2750 static struct attribute *it87_attributes[] = {
2751         &dev_attr_alarms.attr,
2752         &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
2753         &dev_attr_vrm.attr,                             /* 2 */
2754         &dev_attr_cpu0_vid.attr,                        /* 3 */
2755         &sensor_dev_attr_in3_label.dev_attr.attr,       /* 4 .. 7 */
2756         &sensor_dev_attr_in7_label.dev_attr.attr,
2757         &sensor_dev_attr_in8_label.dev_attr.attr,
2758         &sensor_dev_attr_in9_label.dev_attr.attr,
2759         NULL
2760 };
2761
2762 static const struct attribute_group it87_group = {
2763         .attrs = it87_attributes,
2764         .is_visible = it87_is_visible,
2765 };
2766
2767 static umode_t it87_fan_is_visible(struct kobject *kobj,
2768                                    struct attribute *attr, int index)
2769 {
2770         struct device *dev = container_of(kobj, struct device, kobj);
2771         struct it87_data *data = dev_get_drvdata(dev);
2772         int i = index / 5;      /* fan index */
2773         int a = index % 5;      /* attribute index */
2774
2775         if (index >= 15) {      /* fan 4..6 don't have divisor attributes */
2776                 i = (index - 15) / 4 + 3;
2777                 a = (index - 15) % 4;
2778         }
2779
2780         if (!(data->has_fan & BIT(i)))
2781                 return 0;
2782
2783         if (a == 3) {                           /* beep */
2784                 if (!data->has_beep)
2785                         return 0;
2786                 /* first fan beep attribute is writable */
2787                 if (i == __ffs(data->has_fan))
2788                         return attr->mode | 0200;
2789         }
2790
2791         if (a == 4 && has_16bit_fans(data))     /* divisor */
2792                 return 0;
2793
2794         return attr->mode;
2795 }
2796
2797 static struct attribute *it87_attributes_fan[] = {
2798         &sensor_dev_attr_fan1_input.dev_attr.attr,
2799         &sensor_dev_attr_fan1_min.dev_attr.attr,
2800         &sensor_dev_attr_fan1_alarm.dev_attr.attr,
2801         &sensor_dev_attr_fan1_beep.dev_attr.attr,       /* 3 */
2802         &sensor_dev_attr_fan1_div.dev_attr.attr,        /* 4 */
2803
2804         &sensor_dev_attr_fan2_input.dev_attr.attr,
2805         &sensor_dev_attr_fan2_min.dev_attr.attr,
2806         &sensor_dev_attr_fan2_alarm.dev_attr.attr,
2807         &sensor_dev_attr_fan2_beep.dev_attr.attr,
2808         &sensor_dev_attr_fan2_div.dev_attr.attr,        /* 9 */
2809
2810         &sensor_dev_attr_fan3_input.dev_attr.attr,
2811         &sensor_dev_attr_fan3_min.dev_attr.attr,
2812         &sensor_dev_attr_fan3_alarm.dev_attr.attr,
2813         &sensor_dev_attr_fan3_beep.dev_attr.attr,
2814         &sensor_dev_attr_fan3_div.dev_attr.attr,        /* 14 */
2815
2816         &sensor_dev_attr_fan4_input.dev_attr.attr,      /* 15 */
2817         &sensor_dev_attr_fan4_min.dev_attr.attr,
2818         &sensor_dev_attr_fan4_alarm.dev_attr.attr,
2819         &sensor_dev_attr_fan4_beep.dev_attr.attr,
2820
2821         &sensor_dev_attr_fan5_input.dev_attr.attr,      /* 19 */
2822         &sensor_dev_attr_fan5_min.dev_attr.attr,
2823         &sensor_dev_attr_fan5_alarm.dev_attr.attr,
2824         &sensor_dev_attr_fan5_beep.dev_attr.attr,
2825
2826         &sensor_dev_attr_fan6_input.dev_attr.attr,      /* 23 */
2827         &sensor_dev_attr_fan6_min.dev_attr.attr,
2828         &sensor_dev_attr_fan6_alarm.dev_attr.attr,
2829         &sensor_dev_attr_fan6_beep.dev_attr.attr,
2830         NULL
2831 };
2832
2833 static const struct attribute_group it87_group_fan = {
2834         .attrs = it87_attributes_fan,
2835         .is_visible = it87_fan_is_visible,
2836 };
2837
2838 static umode_t it87_pwm_is_visible(struct kobject *kobj,
2839                                    struct attribute *attr, int index)
2840 {
2841         struct device *dev = container_of(kobj, struct device, kobj);
2842         struct it87_data *data = dev_get_drvdata(dev);
2843         int i = index / 4;      /* pwm index */
2844         int a = index % 4;      /* attribute index */
2845
2846         if (!(data->has_pwm & BIT(i)))
2847                 return 0;
2848
2849         /* pwmX_auto_channels_temp is only writable if auto pwm is supported */
2850         if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data)))
2851                 return attr->mode | 0200;
2852
2853         /* pwm2_freq is writable if there are two pwm frequency selects */
2854         if (has_pwm_freq2(data) && i == 1 && a == 2)
2855                 return attr->mode | 0200;
2856
2857         return attr->mode;
2858 }
2859
2860 static struct attribute *it87_attributes_pwm[] = {
2861         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2862         &sensor_dev_attr_pwm1.dev_attr.attr,
2863         &sensor_dev_attr_pwm1_freq.dev_attr.attr,
2864         &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
2865
2866         &sensor_dev_attr_pwm2_enable.dev_attr.attr,
2867         &sensor_dev_attr_pwm2.dev_attr.attr,
2868         &sensor_dev_attr_pwm2_freq.dev_attr.attr,
2869         &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
2870
2871         &sensor_dev_attr_pwm3_enable.dev_attr.attr,
2872         &sensor_dev_attr_pwm3.dev_attr.attr,
2873         &sensor_dev_attr_pwm3_freq.dev_attr.attr,
2874         &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
2875
2876         &sensor_dev_attr_pwm4_enable.dev_attr.attr,
2877         &sensor_dev_attr_pwm4.dev_attr.attr,
2878         &sensor_dev_attr_pwm4_freq.dev_attr.attr,
2879         &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr,
2880
2881         &sensor_dev_attr_pwm5_enable.dev_attr.attr,
2882         &sensor_dev_attr_pwm5.dev_attr.attr,
2883         &sensor_dev_attr_pwm5_freq.dev_attr.attr,
2884         &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr,
2885
2886         &sensor_dev_attr_pwm6_enable.dev_attr.attr,
2887         &sensor_dev_attr_pwm6.dev_attr.attr,
2888         &sensor_dev_attr_pwm6_freq.dev_attr.attr,
2889         &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr,
2890
2891         NULL
2892 };
2893
2894 static const struct attribute_group it87_group_pwm = {
2895         .attrs = it87_attributes_pwm,
2896         .is_visible = it87_pwm_is_visible,
2897 };
2898
2899 static umode_t it87_auto_pwm_is_visible(struct kobject *kobj,
2900                                         struct attribute *attr, int index)
2901 {
2902         struct device *dev = container_of(kobj, struct device, kobj);
2903         struct it87_data *data = dev_get_drvdata(dev);
2904         int i = index / 11;     /* pwm index */
2905         int a = index % 11;     /* attribute index */
2906
2907         if (index >= 33) {      /* pwm 4..6 */
2908                 i = (index - 33) / 6 + 3;
2909                 a = (index - 33) % 6 + 4;
2910         }
2911
2912         if (!(data->has_pwm & BIT(i)))
2913                 return 0;
2914
2915         if (has_newer_autopwm(data)) {
2916                 if (a < 4)      /* no auto point pwm */
2917                         return 0;
2918                 if (a == 8)     /* no auto_point4 */
2919                         return 0;
2920         }
2921         if (has_old_autopwm(data)) {
2922                 if (a >= 9)     /* no pwm_auto_start, pwm_auto_slope */
2923                         return 0;
2924         }
2925
2926         return attr->mode;
2927 }
2928
2929 static struct attribute *it87_attributes_auto_pwm[] = {
2930         &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
2931         &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
2932         &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
2933         &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
2934         &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
2935         &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
2936         &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
2937         &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
2938         &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
2939         &sensor_dev_attr_pwm1_auto_start.dev_attr.attr,
2940         &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr,
2941
2942         &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr,    /* 11 */
2943         &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
2944         &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
2945         &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
2946         &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
2947         &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
2948         &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
2949         &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
2950         &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
2951         &sensor_dev_attr_pwm2_auto_start.dev_attr.attr,
2952         &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr,
2953
2954         &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr,    /* 22 */
2955         &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
2956         &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
2957         &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
2958         &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
2959         &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
2960         &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
2961         &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
2962         &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
2963         &sensor_dev_attr_pwm3_auto_start.dev_attr.attr,
2964         &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr,
2965
2966         &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr,   /* 33 */
2967         &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr,
2968         &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr,
2969         &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr,
2970         &sensor_dev_attr_pwm4_auto_start.dev_attr.attr,
2971         &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr,
2972
2973         &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr,
2974         &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr,
2975         &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr,
2976         &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr,
2977         &sensor_dev_attr_pwm5_auto_start.dev_attr.attr,
2978         &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr,
2979
2980         &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr,
2981         &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr,
2982         &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr,
2983         &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr,
2984         &sensor_dev_attr_pwm6_auto_start.dev_attr.attr,
2985         &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr,
2986
2987         NULL,
2988 };
2989
2990 static const struct attribute_group it87_group_auto_pwm = {
2991         .attrs = it87_attributes_auto_pwm,
2992         .is_visible = it87_auto_pwm_is_visible,
2993 };
2994
2995 /* SuperIO detection - will change isa_address if a chip is found */
2996 static int __init it87_find(int sioaddr, unsigned short *address,
2997                             phys_addr_t *mmio_address,
2998                             struct it87_sio_data *sio_data)
2999 {
3000         const struct it87_devices *config;
3001         phys_addr_t base = 0;
3002         bool doexit = true;
3003         char mmio_str[32];
3004         u16 chip_type;
3005         int err;
3006
3007         err = superio_enter(sioaddr);
3008         if (err)
3009                 return err;
3010
3011         sio_data->sioaddr = sioaddr;
3012
3013         err = -ENODEV;
3014         chip_type = superio_inw(sioaddr, DEVID);
3015         if (chip_type == 0xffff)
3016                 goto exit;
3017
3018         if (force_id)
3019                 chip_type = force_id;
3020
3021         switch (chip_type) {
3022         case IT8705F_DEVID:
3023                 sio_data->type = it87;
3024                 break;
3025         case IT8712F_DEVID:
3026                 sio_data->type = it8712;
3027                 break;
3028         case IT8716F_DEVID:
3029         case IT8726F_DEVID:
3030                 sio_data->type = it8716;
3031                 break;
3032         case IT8718F_DEVID:
3033                 sio_data->type = it8718;
3034                 break;
3035         case IT8720F_DEVID:
3036                 sio_data->type = it8720;
3037                 break;
3038         case IT8721F_DEVID:
3039                 sio_data->type = it8721;
3040                 break;
3041         case IT8728F_DEVID:
3042                 sio_data->type = it8728;
3043                 break;
3044         case IT8732F_DEVID:
3045                 sio_data->type = it8732;
3046                 break;
3047         case IT8736F_DEVID:
3048                 sio_data->type = it8736;
3049                 break;
3050         case IT8738E_DEVID:
3051                 sio_data->type = it8738;
3052                 break;
3053         case IT8792E_DEVID:
3054                 sio_data->type = it8792;
3055                 /*
3056                  * Disabling configuration mode on IT8792E can result in system
3057                  * hang-ups and access failures to the Super-IO chip at the
3058                  * second SIO address. Never exit configuration mode on this
3059                  * chip to avoid the problem.
3060                  */
3061                 doexit = false;
3062                 break;
3063         case IT8771E_DEVID:
3064                 sio_data->type = it8771;
3065                 break;
3066         case IT8772E_DEVID:
3067                 sio_data->type = it8772;
3068                 break;
3069         case IT8781F_DEVID:
3070                 sio_data->type = it8781;
3071                 break;
3072         case IT8782F_DEVID:
3073                 sio_data->type = it8782;
3074                 break;
3075         case IT8783E_DEVID:
3076                 sio_data->type = it8783;
3077                 break;
3078         case IT8786E_DEVID:
3079                 sio_data->type = it8786;
3080                 break;
3081         case IT8790E_DEVID:
3082                 sio_data->type = it8790;
3083                 doexit = false;         /* See IT8792E comment above */
3084                 break;
3085         case IT8603E_DEVID:
3086         case IT8623E_DEVID:
3087                 sio_data->type = it8603;
3088                 break;
3089         case IT8606E_DEVID:
3090                 sio_data->type = it8606;
3091                 break;
3092         case IT8607E_DEVID:
3093                 sio_data->type = it8607;
3094                 break;
3095         case IT8613E_DEVID:
3096                 sio_data->type = it8613;
3097                 break;
3098         case IT8620E_DEVID:
3099                 sio_data->type = it8620;
3100                 break;
3101         case IT8622E_DEVID:
3102                 sio_data->type = it8622;
3103                 break;
3104         case IT8625E_DEVID:
3105                 sio_data->type = it8625;
3106                 break;
3107         case IT8628E_DEVID:
3108                 sio_data->type = it8628;
3109                 break;
3110         case IT8655E_DEVID:
3111                 sio_data->type = it8655;
3112                 break;
3113         case IT8665E_DEVID:
3114                 sio_data->type = it8665;
3115                 break;
3116         case IT8686E_DEVID:
3117                 sio_data->type = it8686;
3118                 break;
3119         case 0xffff:    /* No device at all */
3120                 goto exit;
3121         default:
3122                 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
3123                 goto exit;
3124         }
3125
3126         superio_select(sioaddr, PME);
3127         if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) {
3128                 pr_info("Device not activated, skipping\n");
3129                 goto exit;
3130         }
3131
3132         *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1);
3133         if (*address == 0) {
3134                 pr_info("Base address not set, skipping\n");
3135                 goto exit;
3136         }
3137
3138         sio_data->doexit = doexit;
3139
3140         err = 0;
3141         sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
3142
3143         config = &it87_devices[sio_data->type];
3144
3145         if (has_mmio(config) && mmio) {
3146                 u8 reg;
3147
3148                 reg = superio_inb(sioaddr, IT87_EC_HWM_MIO_REG);
3149                 if (reg & BIT(5)) {
3150                         base = 0xf0000000 + ((reg & 0x0f) << 24);
3151                         base += (reg & 0xc0) << 14;
3152                 }
3153         }
3154         *mmio_address = base;
3155
3156         mmio_str[0] = '\0';
3157         if (base)
3158                 snprintf(mmio_str, sizeof(mmio_str), " [MMIO at %pa]", &base);
3159
3160         pr_info("Found %s chip at 0x%x%s, revision %d\n",
3161                 it87_devices[sio_data->type].model,
3162                 *address, mmio_str, sio_data->revision);
3163
3164         /* in7 (VSB or VCCH5V) is always internal on some chips */
3165         if (has_in7_internal(config))
3166                 sio_data->internal |= BIT(1);
3167
3168         /* in8 (Vbat) is always internal */
3169         sio_data->internal |= BIT(2);
3170
3171         /* in9 (AVCC3), always internal if supported */
3172         if (has_avcc3(config))
3173                 sio_data->internal |= BIT(3); /* in9 is AVCC */
3174         else
3175                 sio_data->skip_in |= BIT(9);
3176
3177         if (!has_four_pwm(config))
3178                 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5);
3179         else if (!has_five_pwm(config))
3180                 sio_data->skip_pwm |= BIT(4) | BIT(5);
3181         else if (!has_six_pwm(config))
3182                 sio_data->skip_pwm |= BIT(5);
3183
3184         if (!has_vid(config))
3185                 sio_data->skip_vid = 1;
3186
3187         /* Read GPIO config and VID value from LDN 7 (GPIO) */
3188         if (sio_data->type == it87) {
3189                 /* The IT8705F has a different LD number for GPIO */
3190                 superio_select(sioaddr, 5);
3191                 sio_data->beep_pin = superio_inb(sioaddr,
3192                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3193         } else if (sio_data->type == it8783) {
3194                 int reg25, reg27, reg2a, reg2c, regef;
3195
3196                 superio_select(sioaddr, GPIO);
3197
3198                 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3199                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3200                 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
3201                 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3202                 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG);
3203
3204                 /* Check if fan3 is there or not */
3205                 if ((reg27 & BIT(0)) || !(reg2c & BIT(2)))
3206                         sio_data->skip_fan |= BIT(2);
3207                 if ((reg25 & BIT(4)) ||
3208                     (!(reg2a & BIT(1)) && (regef & BIT(0))))
3209                         sio_data->skip_pwm |= BIT(2);
3210
3211                 /* Check if fan2 is there or not */
3212                 if (reg27 & BIT(7))
3213                         sio_data->skip_fan |= BIT(1);
3214                 if (reg27 & BIT(3))
3215                         sio_data->skip_pwm |= BIT(1);
3216
3217                 /* VIN5 */
3218                 if ((reg27 & BIT(0)) || (reg2c & BIT(2)))
3219                         sio_data->skip_in |= BIT(5); /* No VIN5 */
3220
3221                 /* VIN6 */
3222                 if (reg27 & BIT(1))
3223                         sio_data->skip_in |= BIT(6); /* No VIN6 */
3224
3225                 /*
3226                  * VIN7
3227                  * Does not depend on bit 2 of Reg2C, contrary to datasheet.
3228                  */
3229                 if (reg27 & BIT(2)) {
3230                         /*
3231                          * The data sheet is a bit unclear regarding the
3232                          * internal voltage divider for VCCH5V. It says
3233                          * "This bit enables and switches VIN7 (pin 91) to the
3234                          * internal voltage divider for VCCH5V".
3235                          * This is different to other chips, where the internal
3236                          * voltage divider would connect VIN7 to an internal
3237                          * voltage source. Maybe that is the case here as well.
3238                          *
3239                          * Since we don't know for sure, re-route it if that is
3240                          * not the case, and ask the user to report if the
3241                          * resulting voltage is sane.
3242                          */
3243                         if (!(reg2c & BIT(1))) {
3244                                 reg2c |= BIT(1);
3245                                 superio_outb(sioaddr, IT87_SIO_PINX2_REG,
3246                                              reg2c);
3247                                 pr_notice("Routing internal VCCH5V to in7.\n");
3248                         }
3249                         pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
3250                         pr_notice("Please report if it displays a reasonable voltage.\n");
3251                 }
3252
3253                 if (reg2c & BIT(0))
3254                         sio_data->internal |= BIT(0);
3255                 if (reg2c & BIT(1))
3256                         sio_data->internal |= BIT(1);
3257
3258                 sio_data->beep_pin = superio_inb(sioaddr,
3259                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3260         } else if (sio_data->type == it8603 || sio_data->type == it8606 ||
3261                    sio_data->type == it8607) {
3262                 int reg27, reg29;
3263
3264                 superio_select(sioaddr, GPIO);
3265
3266                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3267
3268                 /* Check if fan3 is there or not */
3269                 if (reg27 & BIT(6))
3270                         sio_data->skip_pwm |= BIT(2);
3271                 if (reg27 & BIT(7))
3272                         sio_data->skip_fan |= BIT(2);
3273
3274                 /* Check if fan2 is there or not */
3275                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3276                 if (reg29 & BIT(1))
3277                         sio_data->skip_pwm |= BIT(1);
3278                 if (reg29 & BIT(2))
3279                         sio_data->skip_fan |= BIT(1);
3280
3281                 switch (sio_data->type) {
3282                 case it8603:
3283                         sio_data->skip_in |= BIT(5); /* No VIN5 */
3284                         sio_data->skip_in |= BIT(6); /* No VIN6 */
3285                         break;
3286                 case it8607:
3287                         sio_data->skip_pwm |= BIT(0);/* No fan1 */
3288                         sio_data->skip_fan |= BIT(0);
3289                 default:
3290                         break;
3291                 }
3292
3293                 sio_data->beep_pin = superio_inb(sioaddr,
3294                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3295         } else if (sio_data->type == it8613) {
3296                 int reg27, reg29, reg2a;
3297
3298                 superio_select(sioaddr, GPIO);
3299
3300                 /* Check for pwm3, fan3, pwm5, fan5 */
3301                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3302                 if (reg27 & BIT(1))
3303                         sio_data->skip_fan |= BIT(4);
3304                 if (reg27 & BIT(3))
3305                         sio_data->skip_pwm |= BIT(4);
3306                 if (reg27 & BIT(6))
3307                         sio_data->skip_pwm |= BIT(2);
3308                 if (reg27 & BIT(7))
3309                         sio_data->skip_fan |= BIT(2);
3310
3311                 /* Check for pwm2, fan2 */
3312                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3313                 if (reg29 & BIT(1))
3314                         sio_data->skip_pwm |= BIT(1);
3315                 if (reg29 & BIT(2))
3316                         sio_data->skip_fan |= BIT(1);
3317
3318                 /* Check for pwm4, fan4 */
3319                 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
3320                 if (!(reg2a & BIT(0)) || (reg29 & BIT(7))) {
3321                         sio_data->skip_fan |= BIT(3);
3322                         sio_data->skip_pwm |= BIT(3);
3323                 }
3324
3325                 sio_data->skip_pwm |= BIT(0); /* No pwm1 */
3326                 sio_data->skip_fan |= BIT(0); /* No fan1 */
3327                 sio_data->skip_in |= BIT(3);  /* No VIN3 */
3328                 sio_data->skip_in |= BIT(6);  /* No VIN6 */
3329
3330                 sio_data->beep_pin = superio_inb(sioaddr,
3331                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3332         } else if (sio_data->type == it8620 || sio_data->type == it8628 ||
3333                    sio_data->type == it8686) {
3334                 int reg;
3335
3336                 superio_select(sioaddr, GPIO);
3337
3338                 /* Check for pwm5 */
3339                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3340                 if (reg & BIT(6))
3341                         sio_data->skip_pwm |= BIT(4);
3342
3343                 /* Check for fan4, fan5 */
3344                 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3345                 if (!(reg & BIT(5)))
3346                         sio_data->skip_fan |= BIT(3);
3347                 if (!(reg & BIT(4)))
3348                         sio_data->skip_fan |= BIT(4);
3349
3350                 /* Check for pwm3, fan3 */
3351                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3352                 if (reg & BIT(6))
3353                         sio_data->skip_pwm |= BIT(2);
3354                 if (reg & BIT(7))
3355                         sio_data->skip_fan |= BIT(2);
3356
3357                 /* Check for pwm4 */
3358                 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG);
3359                 if (reg & BIT(2))
3360                         sio_data->skip_pwm |= BIT(3);
3361
3362                 /* Check for pwm2, fan2 */
3363                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3364                 if (reg & BIT(1))
3365                         sio_data->skip_pwm |= BIT(1);
3366                 if (reg & BIT(2))
3367                         sio_data->skip_fan |= BIT(1);
3368                 /* Check for pwm6, fan6 */
3369                 if (!(reg & BIT(7))) {
3370                         sio_data->skip_pwm |= BIT(5);
3371                         sio_data->skip_fan |= BIT(5);
3372                 }
3373
3374                 /* Check if AVCC is on VIN3 */
3375                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3376                 if (reg & BIT(0)) {
3377                         /* For it8686, the bit just enables AVCC3 */
3378                         if (sio_data->type != it8686)
3379                                 sio_data->internal |= BIT(0);
3380                 } else {
3381                         sio_data->internal &= ~BIT(3);
3382                         sio_data->skip_in |= BIT(9);
3383                 }
3384
3385                 sio_data->beep_pin = superio_inb(sioaddr,
3386                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3387         } else if (sio_data->type == it8622) {
3388                 int reg;
3389
3390                 superio_select(sioaddr, GPIO);
3391
3392                 /* Check for pwm4, fan4 */
3393                 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3394                 if (reg & BIT(6))
3395                         sio_data->skip_fan |= BIT(3);
3396                 if (reg & BIT(5))
3397                         sio_data->skip_pwm |= BIT(3);
3398
3399                 /* Check for pwm3, fan3, pwm5, fan5 */
3400                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3401                 if (reg & BIT(6))
3402                         sio_data->skip_pwm |= BIT(2);
3403                 if (reg & BIT(7))
3404                         sio_data->skip_fan |= BIT(2);
3405                 if (reg & BIT(3))
3406                         sio_data->skip_pwm |= BIT(4);
3407                 if (reg & BIT(1))
3408                         sio_data->skip_fan |= BIT(4);
3409
3410                 /* Check for pwm2, fan2 */
3411                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3412                 if (reg & BIT(1))
3413                         sio_data->skip_pwm |= BIT(1);
3414                 if (reg & BIT(2))
3415                         sio_data->skip_fan |= BIT(1);
3416
3417                 /* Check for AVCC */
3418                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3419                 if (!(reg & BIT(0)))
3420                         sio_data->skip_in |= BIT(9);
3421
3422                 sio_data->beep_pin = superio_inb(sioaddr,
3423                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3424         } else if (sio_data->type == it8732 || sio_data->type == it8736 ||
3425                    sio_data->type == it8738) {
3426                 int reg;
3427
3428                 superio_select(sioaddr, GPIO);
3429
3430                 /* Check for pwm2, fan2 */
3431                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3432                 if (reg & BIT(1))
3433                         sio_data->skip_pwm |= BIT(1);
3434                 if (reg & BIT(2))
3435                         sio_data->skip_fan |= BIT(1);
3436
3437                 /* Check for pwm3, fan3, fan4 */
3438                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3439                 if (reg & BIT(6))
3440                         sio_data->skip_pwm |= BIT(2);
3441                 if (reg & BIT(7))
3442                         sio_data->skip_fan |= BIT(2);
3443                 if (reg & BIT(5))
3444                         sio_data->skip_fan |= BIT(3);
3445
3446                 /* Check if AVCC is on VIN3 */
3447                 if (sio_data->type != it8738) {
3448                         reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3449                         if (reg & BIT(0))
3450                                 sio_data->internal |= BIT(0);
3451                 }
3452
3453                 sio_data->beep_pin = superio_inb(sioaddr,
3454                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3455         } else if (sio_data->type == it8655) {
3456                 int reg;
3457
3458                 superio_select(sioaddr, GPIO);
3459
3460                 /* Check for pwm2 */
3461                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3462                 if (reg & BIT(1))
3463                         sio_data->skip_pwm |= BIT(1);
3464
3465                 /* Check for fan2 */
3466                 reg = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3467                 if (reg & BIT(4))
3468                         sio_data->skip_fan |= BIT(1);
3469
3470                 /* Check for pwm3, fan3 */
3471                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3472                 if (reg & BIT(6))
3473                         sio_data->skip_pwm |= BIT(2);
3474                 if (reg & BIT(7))
3475                         sio_data->skip_fan |= BIT(2);
3476
3477                 sio_data->beep_pin = superio_inb(sioaddr,
3478                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3479         } else if (sio_data->type == it8665 || sio_data->type == it8625) {
3480                 int reg27, reg29, reg2d, regd3;
3481
3482                 superio_select(sioaddr, GPIO);
3483
3484                 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3485                 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3486                 reg2d = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3487                 regd3 = superio_inb(sioaddr, IT87_SIO_GPIO9_REG);
3488
3489                 /* Check for pwm2 */
3490                 if (reg29 & BIT(1))
3491                         sio_data->skip_pwm |= BIT(1);
3492
3493                 /* Check for pwm3, fan3 */
3494                 if (reg27 & BIT(6))
3495                         sio_data->skip_pwm |= BIT(2);
3496                 if (reg27 & BIT(7))
3497                         sio_data->skip_fan |= BIT(2);
3498
3499                 /* Check for fan2, pwm4, fan4, pwm5, fan5 */
3500                 if (sio_data->type == it8625) {
3501                         int reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3502
3503                         if (reg29 & BIT(2))
3504                                 sio_data->skip_fan |= BIT(1);
3505                         if (reg25 & BIT(6))
3506                                 sio_data->skip_fan |= BIT(3);
3507                         if (reg25 & BIT(5))
3508                                 sio_data->skip_pwm |= BIT(3);
3509                         if (reg27 & BIT(3))
3510                                 sio_data->skip_pwm |= BIT(4);
3511                         if (!(reg27 & BIT(1)))
3512                                 sio_data->skip_fan |= BIT(4);
3513                 } else {
3514                         int reg26 = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3515
3516                         if (reg2d & BIT(4))
3517                                 sio_data->skip_fan |= BIT(1);
3518                         if (regd3 & BIT(2))
3519                                 sio_data->skip_pwm |= BIT(3);
3520                         if (regd3 & BIT(3))
3521                                 sio_data->skip_fan |= BIT(3);
3522                         if (reg26 & BIT(5))
3523                                 sio_data->skip_pwm |= BIT(4);
3524                         /*
3525                          * Table 6-1 in datasheet claims that FAN_TAC5 would
3526                          * be enabled with 26h[4]=0. This contradicts with the
3527                          * information in section 8.3.9 and with feedback from
3528                          * users.
3529                          */
3530                         if (!(reg26 & BIT(4)))
3531                                 sio_data->skip_fan |= BIT(4);
3532                 }
3533
3534                 /* Check for pwm6, fan6 */
3535                 if (regd3 & BIT(0))
3536                         sio_data->skip_pwm |= BIT(5);
3537                 if (regd3 & BIT(1))
3538                         sio_data->skip_fan |= BIT(5);
3539
3540                 sio_data->beep_pin = superio_inb(sioaddr,
3541                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3542         } else {
3543                 int reg;
3544                 bool uart6;
3545
3546                 superio_select(sioaddr, GPIO);
3547
3548                 /* Check for fan4, fan5 */
3549                 if (has_five_fans(config)) {
3550                         reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3551                         switch (sio_data->type) {
3552                         case it8718:
3553                                 if (reg & BIT(5))
3554                                         sio_data->skip_fan |= BIT(3);
3555                                 if (reg & BIT(4))
3556                                         sio_data->skip_fan |= BIT(4);
3557                                 break;
3558                         case it8720:
3559                         case it8721:
3560                         case it8728:
3561                                 if (!(reg & BIT(5)))
3562                                         sio_data->skip_fan |= BIT(3);
3563                                 if (!(reg & BIT(4)))
3564                                         sio_data->skip_fan |= BIT(4);
3565                                 break;
3566                         default:
3567                                 break;
3568                         }
3569                 }
3570
3571                 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3572                 if (!sio_data->skip_vid) {
3573                         /* We need at least 4 VID pins */
3574                         if (reg & 0x0f) {
3575                                 pr_info("VID is disabled (pins used for GPIO)\n");
3576                                 sio_data->skip_vid = 1;
3577                         }
3578                 }
3579
3580                 /* Check if fan3 is there or not */
3581                 if (reg & BIT(6))
3582                         sio_data->skip_pwm |= BIT(2);
3583                 if (reg & BIT(7))
3584                         sio_data->skip_fan |= BIT(2);
3585
3586                 /* Check if fan2 is there or not */
3587                 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3588                 if (reg & BIT(1))
3589                         sio_data->skip_pwm |= BIT(1);
3590                 if (reg & BIT(2))
3591                         sio_data->skip_fan |= BIT(1);
3592
3593                 if ((sio_data->type == it8718 || sio_data->type == it8720) &&
3594                     !(sio_data->skip_vid))
3595                         sio_data->vid_value = superio_inb(sioaddr,
3596                                                           IT87_SIO_VID_REG);
3597
3598                 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3599
3600                 uart6 = sio_data->type == it8782 && (reg & BIT(2));
3601
3602                 /*
3603                  * The IT8720F has no VIN7 pin, so VCCH should always be
3604                  * routed internally to VIN7 with an internal divider.
3605                  * Curiously, there still is a configuration bit to control
3606                  * this, which means it can be set incorrectly. And even
3607                  * more curiously, many boards out there are improperly
3608                  * configured, even though the IT8720F datasheet claims
3609                  * that the internal routing of VCCH to VIN7 is the default
3610                  * setting. So we force the internal routing in this case.
3611                  *
3612                  * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
3613                  * If UART6 is enabled, re-route VIN7 to the internal divider
3614                  * if that is not already the case.
3615                  */
3616                 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) {
3617                         reg |= BIT(1);
3618                         superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg);
3619                         pr_notice("Routing internal VCCH to in7\n");
3620                 }
3621                 if (reg & BIT(0))
3622                         sio_data->internal |= BIT(0);
3623                 if (reg & BIT(1))
3624                         sio_data->internal |= BIT(1);
3625
3626                 /*
3627                  * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
3628                  * While VIN7 can be routed to the internal voltage divider,
3629                  * VIN5 and VIN6 are not available if UART6 is enabled.
3630                  *
3631                  * Also, temp3 is not available if UART6 is enabled and TEMPIN3
3632                  * is the temperature source. Since we can not read the
3633                  * temperature source here, skip_temp is preliminary.
3634                  */
3635                 if (uart6) {
3636                         sio_data->skip_in |= BIT(5) | BIT(6);
3637                         sio_data->skip_temp |= BIT(2);
3638                 }
3639
3640                 sio_data->beep_pin = superio_inb(sioaddr,
3641                                                  IT87_SIO_BEEP_PIN_REG) & 0x3f;
3642         }
3643         if (sio_data->beep_pin)
3644                 pr_info("Beeping is supported\n");
3645
3646         if (config->smbus_bitmap && !base) {
3647                 u8 reg;
3648
3649                 superio_select(sioaddr, PME);
3650                 reg = superio_inb(sioaddr, IT87_SPECIAL_CFG_REG);
3651                 sio_data->ec_special_config = reg;
3652                 sio_data->smbus_bitmap = reg & config->smbus_bitmap;
3653         }
3654
3655 exit:
3656         superio_exit(sioaddr, doexit);
3657         return err;
3658 }
3659
3660 static void it87_init_regs(struct platform_device *pdev)
3661 {
3662         struct it87_data *data = platform_get_drvdata(pdev);
3663
3664         /* Initialize chip specific register pointers */
3665         switch (data->type) {
3666         case it8628:
3667         case it8686:
3668                 data->REG_FAN = IT87_REG_FAN;
3669                 data->REG_FANX = IT87_REG_FANX;
3670                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3671                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3672                 data->REG_PWM = IT87_REG_PWM;
3673                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET_8686;
3674                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW_8686;
3675                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH_8686;
3676                 break;
3677         case it8625:
3678         case it8655:
3679         case it8665:
3680                 data->REG_FAN = IT87_REG_FAN_8665;
3681                 data->REG_FANX = IT87_REG_FANX_8665;
3682                 data->REG_FAN_MIN = IT87_REG_FAN_MIN_8665;
3683                 data->REG_FANX_MIN = IT87_REG_FANX_MIN_8665;
3684                 data->REG_PWM = IT87_REG_PWM_8665;
3685                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3686                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3687                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3688                 break;
3689         case it8622:
3690                 data->REG_FAN = IT87_REG_FAN;
3691                 data->REG_FANX = IT87_REG_FANX;
3692                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3693                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3694                 data->REG_PWM = IT87_REG_PWM_8665;
3695                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3696                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3697                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3698                 break;
3699         case it8613:
3700                 data->REG_FAN = IT87_REG_FAN;
3701                 data->REG_FANX = IT87_REG_FANX;
3702                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3703                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3704                 data->REG_PWM = IT87_REG_PWM_8665;
3705                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3706                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3707                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3708                 break;
3709         default:
3710                 data->REG_FAN = IT87_REG_FAN;
3711                 data->REG_FANX = IT87_REG_FANX;
3712                 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3713                 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3714                 data->REG_PWM = IT87_REG_PWM;
3715                 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3716                 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3717                 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3718                 break;
3719         }
3720
3721         if (data->mmio) {
3722                 data->read = it87_mmio_read;
3723                 data->write = it87_mmio_write;
3724         } else if (has_bank_sel(data)) {
3725                 data->read = it87_io_read;
3726                 data->write = it87_io_write;
3727         } else {
3728                 data->read = _it87_io_read;
3729                 data->write = _it87_io_write;
3730         }
3731 }
3732
3733 /* Called when we have found a new IT87. */
3734 static void it87_init_device(struct platform_device *pdev)
3735 {
3736         struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
3737         struct it87_data *data = platform_get_drvdata(pdev);
3738         int tmp, i;
3739         u8 mask;
3740
3741         if (has_new_tempmap(data)) {
3742                 data->pwm_temp_map_shift = 3;
3743                 data->pwm_temp_map_mask = 0x07;
3744         } else {
3745                 data->pwm_temp_map_shift = 0;
3746                 data->pwm_temp_map_mask = 0x03;
3747         }
3748
3749         /*
3750          * For each PWM channel:
3751          * - If it is in automatic mode, setting to manual mode should set
3752          *   the fan to full speed by default.
3753          * - If it is in manual mode, we need a mapping to temperature
3754          *   channels to use when later setting to automatic mode later.
3755          *   Map to the first sensor by default (we are clueless.)
3756          * In both cases, the value can (and should) be changed by the user
3757          * prior to switching to a different mode.
3758          * Note that this is no longer needed for the IT8721F and later, as
3759          * these have separate registers for the temperature mapping and the
3760          * manual duty cycle.
3761          */
3762         for (i = 0; i < NUM_AUTO_PWM; i++) {
3763                 data->pwm_temp_map[i] = 0;
3764                 data->pwm_duty[i] = 0x7f;       /* Full speed */
3765                 data->auto_pwm[i][3] = 0x7f;    /* Full speed, hard-coded */
3766         }
3767
3768         /*
3769          * Some chips seem to have default value 0xff for all limit
3770          * registers. For low voltage limits it makes no sense and triggers
3771          * alarms, so change to 0 instead. For high temperature limits, it
3772          * means -1 degree C, which surprisingly doesn't trigger an alarm,
3773          * but is still confusing, so change to 127 degrees C.
3774          */
3775         for (i = 0; i < NUM_VIN_LIMIT; i++) {
3776                 tmp = data->read(data, IT87_REG_VIN_MIN(i));
3777                 if (tmp == 0xff)
3778                         data->write(data, IT87_REG_VIN_MIN(i), 0);
3779         }
3780         for (i = 0; i < data->num_temp_limit; i++) {
3781                 tmp = data->read(data, data->REG_TEMP_HIGH[i]);
3782                 if (tmp == 0xff)
3783                         data->write(data, data->REG_TEMP_HIGH[i], 127);
3784         }
3785
3786         /*
3787          * Temperature channels are not forcibly enabled, as they can be
3788          * set to two different sensor types and we can't guess which one
3789          * is correct for a given system. These channels can be enabled at
3790          * run-time through the temp{1-3}_type sysfs accessors if needed.
3791          */
3792
3793         /* Check if voltage monitors are reset manually or by some reason */
3794         tmp = data->read(data, IT87_REG_VIN_ENABLE);
3795         if ((tmp & 0xff) == 0) {
3796                 /* Enable all voltage monitors */
3797                 data->write(data, IT87_REG_VIN_ENABLE, 0xff);
3798         }
3799
3800         /* Check if tachometers are reset manually or by some reason */
3801         mask = 0x70 & ~(sio_data->skip_fan << 4);
3802         data->fan_main_ctrl = data->read(data, IT87_REG_FAN_MAIN_CTRL);
3803         if ((data->fan_main_ctrl & mask) == 0) {
3804                 /* Enable all fan tachometers */
3805                 data->fan_main_ctrl |= mask;
3806                 data->write(data, IT87_REG_FAN_MAIN_CTRL, data->fan_main_ctrl);
3807         }
3808         data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
3809
3810         tmp = data->read(data, IT87_REG_FAN_16BIT);
3811
3812         /* Set tachometers to 16-bit mode if needed */
3813         if (has_fan16_config(data)) {
3814                 if (~tmp & 0x07 & data->has_fan) {
3815                         dev_dbg(&pdev->dev,
3816                                 "Setting fan1-3 to 16-bit mode\n");
3817                         data->write(data, IT87_REG_FAN_16BIT, tmp | 0x07);
3818                 }
3819         }
3820
3821         /* Check for additional fans */
3822         if (has_four_fans(data) && (tmp & BIT(4)))
3823                 data->has_fan |= BIT(3); /* fan4 enabled */
3824         if (has_five_fans(data) && (tmp & BIT(5)))
3825                 data->has_fan |= BIT(4); /* fan5 enabled */
3826         if (has_six_fans(data)) {
3827                 switch (data->type) {
3828                 case it8620:
3829                 case it8628:
3830                 case it8686:
3831                         if (tmp & BIT(2))
3832                                 data->has_fan |= BIT(5); /* fan6 enabled */
3833                         break;
3834                 case it8625:
3835                 case it8665:
3836                         tmp = data->read(data, IT87_REG_FAN_DIV);
3837                         if (tmp & BIT(3))
3838                                 data->has_fan |= BIT(5); /* fan6 enabled */
3839                         break;
3840                 default:
3841                         break;
3842                 }
3843         }
3844
3845         /* Fan input pins may be used for alternative functions */
3846         data->has_fan &= ~sio_data->skip_fan;
3847
3848         /* Check if pwm6 is enabled */
3849         if (has_six_pwm(data)) {
3850                 switch (data->type) {
3851                 case it8620:
3852                 case it8686:
3853                         tmp = data->read(data, IT87_REG_FAN_DIV);
3854                         if (!(tmp & BIT(3)))
3855                                 sio_data->skip_pwm |= BIT(5);
3856                         break;
3857                 default:
3858                         break;
3859                 }
3860         }
3861
3862         if (has_bank_sel(data)) {
3863                 for (i = 0; i < 3; i++)
3864                         data->temp_src[i] =
3865                                 data->read(data, IT87_REG_TEMP_SRC1[i]);
3866                 data->temp_src[3] = data->read(data, IT87_REG_TEMP_SRC2);
3867         }
3868
3869         /* Start monitoring */
3870         data->write(data, IT87_REG_CONFIG,
3871                     (data->read(data, IT87_REG_CONFIG) & 0x3e) |
3872                                         (update_vbat ? 0x41 : 0x01));
3873 }
3874
3875 /* Return 1 if and only if the PWM interface is safe to use */
3876 static int it87_check_pwm(struct device *dev)
3877 {
3878         struct it87_data *data = dev_get_drvdata(dev);
3879         /*
3880          * Some BIOSes fail to correctly configure the IT87 fans. All fans off
3881          * and polarity set to active low is sign that this is the case so we
3882          * disable pwm control to protect the user.
3883          */
3884         int tmp = data->read(data, IT87_REG_FAN_CTL);
3885
3886         if ((tmp & 0x87) == 0) {
3887                 if (fix_pwm_polarity) {
3888                         /*
3889                          * The user asks us to attempt a chip reconfiguration.
3890                          * This means switching to active high polarity and
3891                          * inverting all fan speed values.
3892                          */
3893                         int i;
3894                         u8 pwm[3];
3895
3896                         for (i = 0; i < ARRAY_SIZE(pwm); i++)
3897                                 pwm[i] = data->read(data,
3898                                                          data->REG_PWM[i]);
3899
3900                         /*
3901                          * If any fan is in automatic pwm mode, the polarity
3902                          * might be correct, as suspicious as it seems, so we
3903                          * better don't change anything (but still disable the
3904                          * PWM interface).
3905                          */
3906                         if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
3907                                 dev_info(dev,
3908                                          "Reconfiguring PWM to active high polarity\n");
3909                                 data->write(data, IT87_REG_FAN_CTL, tmp | 0x87);
3910                                 for (i = 0; i < 3; i++)
3911                                         data->write(data, data->REG_PWM[i],
3912                                                     0x7f & ~pwm[i]);
3913                                 return 1;
3914                         }
3915
3916                         dev_info(dev,
3917                                  "PWM configuration is too broken to be fixed\n");
3918                 }
3919
3920                 dev_info(dev,
3921                          "Detected broken BIOS defaults, disabling PWM interface\n");
3922                 return 0;
3923         } else if (fix_pwm_polarity) {
3924                 dev_info(dev,
3925                          "PWM configuration looks sane, won't touch\n");
3926         }
3927
3928         return 1;
3929 }
3930
3931 static int it87_probe(struct platform_device *pdev)
3932 {
3933         struct it87_data *data;
3934         struct resource *res;
3935         struct device *dev = &pdev->dev;
3936         struct it87_sio_data *sio_data = dev_get_platdata(dev);
3937         int enable_pwm_interface;
3938         struct device *hwmon_dev;
3939         int err;
3940
3941         data = devm_kzalloc(dev, sizeof(struct it87_data), GFP_KERNEL);
3942         if (!data)
3943                 return -ENOMEM;
3944
3945         res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3946         if (res) {
3947                 if (!devm_request_region(dev, res->start, IT87_EC_EXTENT,
3948                                          DRVNAME)) {
3949                         dev_err(dev, "Failed to request region %pR\n", res);
3950                         return -EBUSY;
3951                 }
3952         } else {
3953                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3954                 data->mmio = devm_ioremap_resource(dev, res);
3955                 if (IS_ERR(data->mmio))
3956                         return PTR_ERR(data->mmio);
3957         }
3958
3959         data->addr = res->start;
3960         data->type = sio_data->type;
3961         data->sioaddr = sio_data->sioaddr;
3962         data->smbus_bitmap = sio_data->smbus_bitmap;
3963         data->ec_special_config = sio_data->ec_special_config;
3964         data->doexit = sio_data->doexit;
3965         data->features = it87_devices[sio_data->type].features;
3966         data->num_temp_limit = it87_devices[sio_data->type].num_temp_limit;
3967         data->num_temp_offset = it87_devices[sio_data->type].num_temp_offset;
3968         data->pwm_num_temp_map = it87_devices[sio_data->type].num_temp_map;
3969         data->peci_mask = it87_devices[sio_data->type].peci_mask;
3970         data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
3971
3972         /*
3973          * IT8705F Datasheet 0.4.1, 3h == Version G.
3974          * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
3975          * These are the first revisions with 16-bit tachometer support.
3976          */
3977         switch (data->type) {
3978         case it87:
3979                 if (sio_data->revision >= 0x03) {
3980                         data->features &= ~FEAT_OLD_AUTOPWM;
3981                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
3982                 }
3983                 break;
3984         case it8712:
3985                 if (sio_data->revision >= 0x08) {
3986                         data->features &= ~FEAT_OLD_AUTOPWM;
3987                         data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
3988                                           FEAT_FIVE_FANS;
3989                 }
3990                 break;
3991         default:
3992                 break;
3993         }
3994
3995         platform_set_drvdata(pdev, data);
3996
3997         mutex_init(&data->update_lock);
3998
3999         /* Initialize register pointers */
4000         it87_init_regs(pdev);
4001
4002         /*
4003          * We need to disable SMBus before we can read any registers in
4004          * the envmon address space, even if it is for chip identification
4005          * purposes. If the chip has SMBus client support, it likely also has
4006          * multi-page envmon registers, so we have to set the page anyway
4007          * before accessing those registers. Kind of a chicken-and-egg
4008          * problem.
4009          * Fortunately, the chip was already identified through the SIO
4010          * address space, only recent chips are affected, and this is just
4011          * an additional safeguard.
4012          */
4013         err = smbus_disable(data);
4014         if (err)
4015                 return err;
4016
4017         /* Now, we do the remaining detection. */
4018         if ((data->read(data, IT87_REG_CONFIG) & 0x80) ||
4019             data->read(data, IT87_REG_CHIPID) != 0x90) {
4020                 smbus_enable(data);
4021                 return -ENODEV;
4022         }
4023
4024         /* Check PWM configuration */
4025         enable_pwm_interface = it87_check_pwm(dev);
4026
4027         /* Starting with IT8721F, we handle scaling of internal voltages */
4028         if (has_scaling(data)) {
4029                 if (sio_data->internal & BIT(0))
4030                         data->in_scaled |= BIT(3);      /* in3 is AVCC */
4031                 if (sio_data->internal & BIT(1))
4032                         data->in_scaled |= BIT(7);      /* in7 is VSB */
4033                 if (sio_data->internal & BIT(2))
4034                         data->in_scaled |= BIT(8);      /* in8 is Vbat */
4035                 if (sio_data->internal & BIT(3))
4036                         data->in_scaled |= BIT(9);      /* in9 is AVCC */
4037         } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
4038                    sio_data->type == it8783) {
4039                 if (sio_data->internal & BIT(0))
4040                         data->in_scaled |= BIT(3);      /* in3 is VCC5V */
4041                 if (sio_data->internal & BIT(1))
4042                         data->in_scaled |= BIT(7);      /* in7 is VCCH5V */
4043         }
4044
4045         data->has_temp = 0x07;
4046         if (sio_data->skip_temp & BIT(2)) {
4047                 if (sio_data->type == it8782 &&
4048                     !(data->read(data, IT87_REG_TEMP_EXTRA) & 0x80))
4049                         data->has_temp &= ~BIT(2);
4050         }
4051
4052         data->in_internal = sio_data->internal;
4053         data->has_in = 0x3ff & ~sio_data->skip_in;
4054
4055         if (has_four_temp(data)) {
4056                 data->has_temp |= BIT(3);
4057         } else if (has_six_temp(data)) {
4058                 if (sio_data->type == it8655 || sio_data->type == it8665) {
4059                         data->has_temp |= BIT(3) | BIT(4) | BIT(5);
4060                 } else {
4061                         u8 reg = data->read(data, IT87_REG_TEMP456_ENABLE);
4062
4063                         /* Check for additional temperature sensors */
4064                         if ((reg & 0x03) >= 0x02)
4065                                 data->has_temp |= BIT(3);
4066                         if (((reg >> 2) & 0x03) >= 0x02)
4067                                 data->has_temp |= BIT(4);
4068                         if (((reg >> 4) & 0x03) >= 0x02)
4069                                 data->has_temp |= BIT(5);
4070
4071                         /* Check for additional voltage sensors */
4072                         if ((reg & 0x03) == 0x01)
4073                                 data->has_in |= BIT(10);
4074                         if (((reg >> 2) & 0x03) == 0x01)
4075                                 data->has_in |= BIT(11);
4076                         if (((reg >> 4) & 0x03) == 0x01)
4077                                 data->has_in |= BIT(12);
4078                 }
4079         }
4080
4081         data->has_beep = !!sio_data->beep_pin;
4082
4083         /* Initialize the IT87 chip */
4084         it87_init_device(pdev);
4085
4086         smbus_enable(data);
4087
4088         if (!sio_data->skip_vid) {
4089                 data->has_vid = true;
4090                 data->vrm = vid_which_vrm();
4091                 /* VID reading from Super-I/O config space if available */
4092                 data->vid = sio_data->vid_value;
4093         }
4094
4095         /* Prepare for sysfs hooks */
4096         data->groups[0] = &it87_group;
4097         data->groups[1] = &it87_group_in;
4098         data->groups[2] = &it87_group_temp;
4099         data->groups[3] = &it87_group_fan;
4100
4101         if (enable_pwm_interface) {
4102                 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1;
4103                 data->has_pwm &= ~sio_data->skip_pwm;
4104
4105                 data->groups[4] = &it87_group_pwm;
4106                 if (has_old_autopwm(data) || has_newer_autopwm(data))
4107                         data->groups[5] = &it87_group_auto_pwm;
4108         }
4109
4110         hwmon_dev = devm_hwmon_device_register_with_groups(dev,
4111                                         it87_devices[sio_data->type].name,
4112                                         data, data->groups);
4113         return PTR_ERR_OR_ZERO(hwmon_dev);
4114 }
4115
4116 static struct platform_driver it87_driver = {
4117         .driver = {
4118                 .name   = DRVNAME,
4119         },
4120         .probe  = it87_probe,
4121 };
4122
4123 static int __init it87_device_add(int index, unsigned short sio_address,
4124                                   phys_addr_t mmio_address,
4125                                   const struct it87_sio_data *sio_data)
4126 {
4127         struct platform_device *pdev;
4128         struct resource res = {
4129                 .name   = DRVNAME,
4130         };
4131         int err;
4132
4133         if (mmio_address) {
4134                 res.start = mmio_address;
4135                 res.end = mmio_address + 0x400 - 1;
4136                 res.flags = IORESOURCE_MEM;
4137         } else {
4138                 res.start = sio_address + IT87_EC_OFFSET;
4139                 res.end = sio_address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1;
4140                 res.flags = IORESOURCE_IO;
4141         }
4142
4143         err = acpi_check_resource_conflict(&res);
4144         if (err) {
4145                 if (!ignore_resource_conflict)
4146                         return err;
4147         }
4148
4149         pdev = platform_device_alloc(DRVNAME, sio_address);
4150         if (!pdev)
4151                 return -ENOMEM;
4152
4153         err = platform_device_add_resources(pdev, &res, 1);
4154         if (err) {
4155                 pr_err("Device resource addition failed (%d)\n", err);
4156                 goto exit_device_put;
4157         }
4158
4159         err = platform_device_add_data(pdev, sio_data,
4160                                        sizeof(struct it87_sio_data));
4161         if (err) {
4162                 pr_err("Platform data allocation failed\n");
4163                 goto exit_device_put;
4164         }
4165
4166         err = platform_device_add(pdev);
4167         if (err) {
4168                 pr_err("Device addition failed (%d)\n", err);
4169                 goto exit_device_put;
4170         }
4171
4172         it87_pdev[index] = pdev;
4173         return 0;
4174
4175 exit_device_put:
4176         platform_device_put(pdev);
4177         return err;
4178 }
4179
4180 struct it87_dmi_data {
4181         bool sio2_force_config; /* force sio2 into configuration mode   */
4182         u8 skip_pwm;            /* pwm channels to skip for this board  */
4183 };
4184
4185 /*
4186  * On various Gigabyte AM4 boards (AB350, AX370), the second Super-IO chip
4187  * (IT8792E) needs to be in configuration mode before accessing the first
4188  * due to a bug in IT8792E which otherwise results in LPC bus access errors.
4189  * This needs to be done before accessing the first Super-IO chip since
4190  * the second chip may have been accessed prior to loading this driver.
4191  *
4192  * The problem is also reported to affect IT8795E, which is used on X299 boards
4193  * and has the same chip ID as IT8792E (0x8733). It also appears to affect
4194  * systems with IT8790E, which is used on some Z97X-Gaming boards as well as
4195  * Z87X-OC.
4196  * DMI entries for those systems will be added as they become available and
4197  * as the problem is confirmed to affect those boards.
4198  */
4199 static struct it87_dmi_data gigabyte_sio2_force = {
4200         .sio2_force_config = true,
4201 };
4202
4203 /*
4204  * On the Shuttle SN68PT, FAN_CTL2 is apparently not
4205  * connected to a fan, but to something else. One user
4206  * has reported instant system power-off when changing
4207  * the PWM2 duty cycle, so we disable it.
4208  * I use the board name string as the trigger in case
4209  * the same board is ever used in other systems.
4210  */
4211 static struct it87_dmi_data nvidia_fn68pt = {
4212         .skip_pwm = BIT(1),
4213 };
4214
4215 static const struct dmi_system_id it87_dmi_table[] __initconst = {
4216         {
4217                 .matches = {
4218                         DMI_MATCH(DMI_SYS_VENDOR,
4219                                   "Gigabyte Technology Co., Ltd."),
4220                         DMI_MATCH(DMI_BOARD_NAME, "AB350"),
4221                 },
4222                 .driver_data = &gigabyte_sio2_force,
4223         },
4224         {
4225                 .matches = {
4226                         DMI_MATCH(DMI_SYS_VENDOR,
4227                                   "Gigabyte Technology Co., Ltd."),
4228                         DMI_MATCH(DMI_BOARD_NAME, "AX370"),
4229                 },
4230                 .driver_data = &gigabyte_sio2_force,
4231         },
4232         {
4233                 .matches = {
4234                         DMI_MATCH(DMI_SYS_VENDOR,
4235                                   "Gigabyte Technology Co., Ltd."),
4236                         DMI_MATCH(DMI_BOARD_NAME, "Z97X-Gaming G1"),
4237                 },
4238                 .driver_data = &gigabyte_sio2_force,
4239         },
4240         {
4241                 .matches = {
4242                         DMI_MATCH(DMI_BOARD_VENDOR, "nVIDIA"),
4243                         DMI_MATCH(DMI_BOARD_NAME, "FN68PT"),
4244                 },
4245                 .driver_data = &nvidia_fn68pt,
4246         },
4247         { }
4248 };
4249
4250 static int __init sm_it87_init(void)
4251 {
4252         const struct dmi_system_id *dmi = dmi_first_match(it87_dmi_table);
4253         struct it87_dmi_data *dmi_data = NULL;
4254         int sioaddr[2] = { REG_2E, REG_4E };
4255         struct it87_sio_data sio_data;
4256         unsigned short isa_address;
4257         phys_addr_t mmio_address;
4258         bool found = false;
4259         int i, err;
4260
4261         pr_info("it87 driver version %s\n", IT87_DRIVER_VERSION);
4262
4263         if (dmi)
4264                 dmi_data = dmi->driver_data;
4265
4266         err = platform_driver_register(&it87_driver);
4267         if (err)
4268                 return err;
4269
4270         if (dmi_data && dmi_data->sio2_force_config)
4271                 __superio_enter(REG_4E);
4272
4273         for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
4274                 memset(&sio_data, 0, sizeof(struct it87_sio_data));
4275                 isa_address = 0;
4276                 mmio_address = 0;
4277                 err = it87_find(sioaddr[i], &isa_address, &mmio_address,
4278                                 &sio_data);
4279                 if (err || isa_address == 0)
4280                         continue;
4281
4282                 if (dmi_data)
4283                         sio_data.skip_pwm |= dmi_data->skip_pwm;
4284                 err = it87_device_add(i, isa_address, mmio_address, &sio_data);
4285                 if (err)
4286                         goto exit_dev_unregister;
4287                 found = true;
4288         }
4289
4290         if (!found) {
4291                 err = -ENODEV;
4292                 goto exit_unregister;
4293         }
4294         return 0;
4295
4296 exit_dev_unregister:
4297         /* NULL check handled by platform_device_unregister */
4298         platform_device_unregister(it87_pdev[0]);
4299 exit_unregister:
4300         platform_driver_unregister(&it87_driver);
4301         return err;
4302 }
4303
4304 static void __exit sm_it87_exit(void)
4305 {
4306         /* NULL check handled by platform_device_unregister */
4307         platform_device_unregister(it87_pdev[1]);
4308         platform_device_unregister(it87_pdev[0]);
4309         platform_driver_unregister(&it87_driver);
4310 }
4311
4312 MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
4313 MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
4314 module_param(update_vbat, bool, 0000);
4315 MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
4316 module_param(fix_pwm_polarity, bool, 0000);
4317 MODULE_PARM_DESC(fix_pwm_polarity,
4318                  "Force PWM polarity to active high (DANGEROUS)");
4319 MODULE_LICENSE("GPL");
4320 MODULE_VERSION(IT87_DRIVER_VERSION);
4321
4322 module_init(sm_it87_init);
4323 module_exit(sm_it87_exit);