*
* Supports: IT8603E Super I/O chip w/LPC interface
* IT8607E Super I/O chip w/LPC interface
+ * IT8613E Super I/O chip w/LPC interface
* IT8620E Super I/O chip w/LPC interface
* IT8622E Super I/O chip w/LPC interface
* IT8623E Super I/O chip w/LPC interface
+ * IT8625E Super I/O chip w/LPC interface
* IT8628E Super I/O chip w/LPC interface
* IT8655E Super I/O chip w/LPC interface
* IT8665E Super I/O chip w/LPC interface
#include <linux/acpi.h>
#include <linux/io.h>
#include "compat.h"
+#include "version.h"
#define DRVNAME "it87"
-/* Necessary API not (yet) exported in upstream kernel */
-/* #define __IT87_USE_ACPI_MUTEX */
-
enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
it8771, it8772, it8781, it8782, it8783, it8786, it8790,
- it8792, it8603, it8607, it8620, it8622, it8628, it8655, it8665,
- it8686 };
+ it8792, it8603, it8607, it8613, it8620, it8622, it8625, it8628,
+ it8655, it8665, it8686 };
static unsigned short force_id;
module_param(force_id, ushort, 0);
MODULE_PARM_DESC(force_id, "Override the detected device ID");
+static bool ignore_resource_conflict;
+module_param(ignore_resource_conflict, bool, 0);
+MODULE_PARM_DESC(ignore_resource_conflict, "Ignore ACPI resource conflict");
+
static struct platform_device *it87_pdev[2];
-static bool it87_sio4e_broken;
-#ifdef __IT87_USE_ACPI_MUTEX
-static acpi_handle it87_acpi_sio_handle;
-static char *it87_acpi_sio_mutex;
-#endif
#define REG_2E 0x2e /* The register to read/write */
#define REG_4E 0x4e /* Secondary register to read/write */
outb(reg, ioreg);
val = inb(ioreg + 1);
- if (it87_sio4e_broken && ioreg == 0x4e && val == 0xff) {
- __superio_enter(ioreg);
- outb(reg, ioreg);
- val = inb(ioreg + 1);
- pr_warn("Retry access 0x4e:0x%x -> 0x%x\n", reg, val);
- }
return val;
}
static inline int superio_enter(int ioreg)
{
-#ifdef __IT87_USE_ACPI_MUTEX
- if (it87_acpi_sio_mutex) {
- acpi_status status;
-
- status = acpi_acquire_mutex(NULL, it87_acpi_sio_mutex, 0x10);
- if (ACPI_FAILURE(status)) {
- pr_err("Failed to acquire ACPI mutex\n");
- return -EBUSY;
- }
- }
-#endif
/*
* Try to reserve ioreg and ioreg + 1 for exclusive access.
*/
if (!request_muxed_region(ioreg, 2, DRVNAME))
- goto error;
+ return -EBUSY;
__superio_enter(ioreg);
return 0;
-
-error:
-#ifdef __IT87_USE_ACPI_MUTEX
- if (it87_acpi_sio_mutex)
- acpi_release_mutex(it87_acpi_sio_handle, NULL);
-#endif
- return -EBUSY;
}
-static inline void superio_exit(int ioreg)
+static inline void superio_exit(int ioreg, bool doexit)
{
- if (!it87_sio4e_broken || ioreg != 0x4e) {
+ if (doexit) {
outb(0x02, ioreg);
outb(0x02, ioreg + 1);
}
release_region(ioreg, 2);
-#ifdef __IT87_USE_ACPI_MUTEX
- if (it87_acpi_sio_mutex)
- acpi_release_mutex(it87_acpi_sio_handle, NULL);
-#endif
}
/* Logical device 4 registers */
#define IT8790E_DEVID 0x8790
#define IT8603E_DEVID 0x8603
#define IT8607E_DEVID 0x8607
+#define IT8613E_DEVID 0x8613
#define IT8620E_DEVID 0x8620
#define IT8622E_DEVID 0x8622
#define IT8623E_DEVID 0x8623
+#define IT8625E_DEVID 0x8625
#define IT8628E_DEVID 0x8628
#define IT8655E_DEVID 0x8655
#define IT8665E_DEVID 0x8665
#define IT8686E_DEVID 0x8686
-#define IT87_ACT_REG 0x30
-#define IT87_BASE_REG 0x60
-/* Logical device 7 registers (IT8712F and later) */
+/* Logical device 4 (Environmental Monitor) registers */
+#define IT87_ACT_REG 0x30
+#define IT87_BASE_REG 0x60
+#define IT87_SPECIAL_CFG_REG 0xf3 /* special configuration register */
+
+/* Logical device 7 (GPIO) registers (IT8712F and later) */
#define IT87_SIO_GPIO1_REG 0x25
#define IT87_SIO_GPIO2_REG 0x26
#define IT87_SIO_GPIO3_REG 0x27
const char * const suffix;
u32 features;
u8 num_temp_limit;
+ u8 num_temp_offset;
+ u8 num_temp_map; /* Number of temperature sources for pwm */
u8 peci_mask;
u8 old_peci_mask;
+ u8 smbus_bitmap; /* SMBus enable bits in extra config register */
+ u8 ec_special_config;
};
#define FEAT_12MV_ADC BIT(0)
#define FEAT_NEWER_AUTOPWM BIT(1)
#define FEAT_OLD_AUTOPWM BIT(2)
#define FEAT_16BIT_FANS BIT(3)
-#define FEAT_TEMP_OFFSET BIT(4)
#define FEAT_TEMP_PECI BIT(5)
#define FEAT_TEMP_OLD_PECI BIT(6)
#define FEAT_FAN16_CONFIG BIT(7) /* Need to enable 16-bit fans */
#define FEAT_SCALING BIT(22) /* Internal voltage scaling */
#define FEAT_FANCTL_ONOFF BIT(23) /* chip has FAN_CTL ON/OFF */
#define FEAT_11MV_ADC BIT(24)
+#define FEAT_NEW_TEMPMAP BIT(25) /* new temp input selection */
static const struct it87_devices it87_devices[] = {
[it87] = {
.features = FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF,
/* may need to overwrite */
.num_temp_limit = 3,
+ .num_temp_offset = 0,
+ .num_temp_map = 3,
},
[it8712] = {
.name = "it8712",
.features = FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF,
/* may need to overwrite */
.num_temp_limit = 3,
+ .num_temp_offset = 0,
+ .num_temp_map = 3,
},
[it8716] = {
.name = "it8716",
.suffix = "F",
- .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
+ .features = FEAT_16BIT_FANS | FEAT_VID
| FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2
| FEAT_FANCTL_ONOFF,
.num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
},
[it8718] = {
.name = "it8718",
.suffix = "F",
- .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
+ .features = FEAT_16BIT_FANS | FEAT_VID
| FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
| FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
.num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
.old_peci_mask = 0x4,
},
[it8720] = {
.name = "it8720",
.suffix = "F",
- .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
+ .features = FEAT_16BIT_FANS | FEAT_VID
| FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
| FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
.num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
.old_peci_mask = 0x4,
},
[it8721] = {
.name = "it8721",
.suffix = "F",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
+ | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
| FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
| FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
.num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
.peci_mask = 0x05,
.old_peci_mask = 0x02, /* Actually reports PCH */
},
.name = "it8728",
.suffix = "F",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
+ | FEAT_TEMP_PECI | FEAT_FIVE_FANS
| FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_SCALING
| FEAT_FANCTL_ONOFF,
- .num_temp_limit = 3,
+ .num_temp_limit = 6,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
.peci_mask = 0x07,
},
[it8732] = {
.name = "it8732",
.suffix = "F",
.features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
+ | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
| FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS
| FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF,
.num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
.peci_mask = 0x07,
.old_peci_mask = 0x02, /* Actually reports PCH */
},
.name = "it8771",
.suffix = "E",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
+ | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
| FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
/* PECI: guesswork */
/* 12mV ADC (OHM) */
/* 16 bit fans (OHM) */
/* three fans, always 16 bit (guesswork) */
.num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
.peci_mask = 0x07,
},
[it8772] = {
.name = "it8772",
.suffix = "E",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
+ | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
| FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
/* PECI (coreboot) */
/* 12mV ADC (HWSensors4, OHM) */
/* 16 bit fans (HWSensors4, OHM) */
/* three fans, always 16 bit (datasheet) */
.num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
.peci_mask = 0x07,
},
[it8781] = {
.name = "it8781",
.suffix = "F",
- .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
+ .features = FEAT_16BIT_FANS
| FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
| FEAT_FANCTL_ONOFF,
.num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
.old_peci_mask = 0x4,
},
[it8782] = {
.name = "it8782",
.suffix = "F",
- .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
+ .features = FEAT_16BIT_FANS
| FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
| FEAT_FANCTL_ONOFF,
.num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
.old_peci_mask = 0x4,
},
[it8783] = {
.name = "it8783",
.suffix = "E/F",
- .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
+ .features = FEAT_16BIT_FANS
| FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
| FEAT_FANCTL_ONOFF,
.num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
.old_peci_mask = 0x4,
},
[it8786] = {
.name = "it8786",
.suffix = "E",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
+ | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
| FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
.num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
.peci_mask = 0x07,
},
[it8790] = {
.name = "it8790",
.suffix = "E",
.features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
- | FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI
+ | FEAT_16BIT_FANS | FEAT_TEMP_PECI
| FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
.num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
.peci_mask = 0x07,
},
[it8792] = {
.name = "it8792",
.suffix = "E",
.features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
- | FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI
+ | FEAT_16BIT_FANS | FEAT_TEMP_PECI
| FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
.num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
.peci_mask = 0x07,
},
[it8603] = {
.name = "it8603",
.suffix = "E",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
+ | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
| FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
.num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 4,
.peci_mask = 0x07,
},
[it8607] = {
.name = "it8607",
.suffix = "E",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
+ | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL | FEAT_NEW_TEMPMAP
| FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING
| FEAT_FANCTL_ONOFF,
.num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 6,
+ .peci_mask = 0x07,
+ },
+ [it8613] = {
+ .name = "it8613",
+ .suffix = "E",
+ .features = FEAT_NEWER_AUTOPWM | FEAT_11MV_ADC | FEAT_16BIT_FANS
+ | FEAT_TEMP_PECI | FEAT_FIVE_FANS
+ | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
+ | FEAT_AVCC3 | FEAT_SCALING | FEAT_NEW_TEMPMAP,
+ .num_temp_limit = 6,
+ .num_temp_offset = 6,
+ .num_temp_map = 6,
.peci_mask = 0x07,
},
[it8620] = {
.name = "it8620",
.suffix = "E",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
+ | FEAT_TEMP_PECI | FEAT_SIX_FANS
| FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
| FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_SCALING
| FEAT_FANCTL_ONOFF,
.num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
.peci_mask = 0x07,
},
[it8622] = {
.name = "it8622",
.suffix = "E",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
+ | FEAT_TEMP_PECI | FEAT_FIVE_FANS
| FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
| FEAT_AVCC3 | FEAT_VIN3_5V | FEAT_SCALING,
.num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 4,
.peci_mask = 0x07,
},
+ [it8625] = {
+ .name = "it8625",
+ .suffix = "E",
+ .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
+ | FEAT_AVCC3 | FEAT_NEW_TEMPMAP
+ | FEAT_11MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
+ | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_SCALING,
+ .num_temp_limit = 6,
+ .num_temp_offset = 6,
+ .num_temp_map = 6,
+ .smbus_bitmap = BIT(1) | BIT(2),
+ },
[it8628] = {
.name = "it8628",
.suffix = "E",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
+ | FEAT_TEMP_PECI | FEAT_SIX_FANS
| FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
| FEAT_SIX_TEMP | FEAT_SCALING | FEAT_AVCC3
| FEAT_FANCTL_ONOFF,
- .num_temp_limit = 3,
+ .num_temp_limit = 6,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
.peci_mask = 0x07,
},
[it8655] = {
.name = "it8655",
.suffix = "E",
.features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_AVCC3
+ | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
| FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_BANK_SEL,
.num_temp_limit = 6,
- .peci_mask = 0x07,
+ .num_temp_offset = 6,
+ .num_temp_map = 6,
+ .smbus_bitmap = BIT(2),
},
[it8665] = {
.name = "it8665",
.suffix = "E",
.features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_AVCC3
+ | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
| FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
| FEAT_SIX_PWM | FEAT_BANK_SEL,
.num_temp_limit = 6,
- .peci_mask = 0x07,
+ .num_temp_offset = 6,
+ .num_temp_map = 6,
+ .smbus_bitmap = BIT(2),
},
[it8686] = {
.name = "it8686",
.suffix = "E",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
+ | FEAT_SIX_FANS | FEAT_NEW_TEMPMAP
| FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
| FEAT_SIX_TEMP | FEAT_BANK_SEL | FEAT_SCALING | FEAT_AVCC3,
.num_temp_limit = 6,
- .peci_mask = 0x07,
+ .num_temp_offset = 6,
+ .num_temp_map = 7,
+ .smbus_bitmap = BIT(1) | BIT(2),
},
};
#define has_10_9mv_adc(data) ((data)->features & FEAT_10_9MV_ADC)
#define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
#define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM)
-#define has_temp_offset(data) ((data)->features & FEAT_TEMP_OFFSET)
#define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
((data)->peci_mask & BIT(nr)))
#define has_temp_old_peci(data, nr) \
#define has_scaling(data) ((data)->features & FEAT_SCALING)
#define has_fanctl_onoff(data) ((data)->features & FEAT_FANCTL_ONOFF)
#define has_11mv_adc(data) ((data)->features & FEAT_11MV_ADC)
+#define has_new_tempmap(data) ((data)->features & FEAT_NEW_TEMPMAP)
struct it87_sio_data {
enum chips type;
+ u8 sioaddr;
+ u8 doexit;
/* Values read from Super-I/O config space */
u8 revision;
u8 vid_value;
u8 skip_fan;
u8 skip_pwm;
u8 skip_temp;
+ u8 smbus_bitmap;
+ u8 ec_special_config;
};
/*
const struct attribute_group *groups[7];
enum chips type;
u32 features;
- u8 bank;
u8 peci_mask;
u8 old_peci_mask;
+ u8 smbus_bitmap; /* !=0 if SMBus needs to be disabled */
+ u8 ec_special_config; /* EC special config register restore value */
+ u8 sioaddr; /* SIO port address */
+ bool doexit; /* true if exit from sio config is ok */
+
const u8 *REG_FAN;
const u8 *REG_FANX;
const u8 *REG_FAN_MIN;
u16 fan[NUM_FAN][2]; /* Register values, [nr][0]=fan, [1]=min */
u8 has_temp; /* Bitfield, temp sensors enabled */
s8 temp[NUM_TEMP][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
- u8 num_temp_limit; /* Number of temp limit/offset registers */
+ u8 num_temp_limit; /* Number of temperature limit registers */
+ u8 num_temp_offset; /* Number of temperature offset registers */
+ u8 temp_src[4]; /* Up to 4 temperature source registers */
u8 sensor; /* Register value (IT87_REG_TEMP_ENABLE) */
u8 extra; /* Register value (IT87_REG_TEMP_EXTRA) */
u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
u8 pwm_ctrl[NUM_PWM]; /* Register value */
u8 pwm_duty[NUM_PWM]; /* Manual PWM value set by user */
u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
+ u8 pwm_temp_map_mask; /* 0x03 for old, 0x07 for new temp map */
+ u8 pwm_temp_map_shift; /* 0 for old, 3 for new temp map */
+ u8 pwm_num_temp_map; /* from config data, 3..7 depending on chip */
/* Automatic fan speed control registers */
u8 auto_pwm[NUM_AUTO_PWM][4]; /* [nr][3] is hard-coded */
#define DIV_FROM_REG(val) BIT(val)
+static u8 temp_map_from_reg(const struct it87_data *data, u8 reg)
+{
+ u8 map;
+
+ map = (reg >> data->pwm_temp_map_shift) & data->pwm_temp_map_mask;
+ if (map >= data->pwm_num_temp_map) /* map is 0-based */
+ map = 0;
+
+ return map;
+}
+
+static u8 temp_map_to_reg(const struct it87_data *data, int nr, u8 map)
+{
+ u8 ctrl = data->pwm_ctrl[nr];
+
+ return (ctrl & ~(data->pwm_temp_map_mask << data->pwm_temp_map_shift)) |
+ (map << data->pwm_temp_map_shift);
+}
+
/*
* PWM base frequencies. The frequency has to be divided by either 128 or 256,
* depending on the chip type, to calculate the actual PWM frequency.
750000,
};
+static int smbus_disable(struct it87_data *data)
+{
+ int err;
+
+ if (data->smbus_bitmap) {
+ err = superio_enter(data->sioaddr);
+ if (err)
+ return err;
+ superio_select(data->sioaddr, PME);
+ superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG,
+ data->ec_special_config & ~data->smbus_bitmap);
+ superio_exit(data->sioaddr, data->doexit);
+ }
+ return 0;
+}
+
+static int smbus_enable(struct it87_data *data)
+{
+ int err;
+
+ if (data->smbus_bitmap) {
+ err = superio_enter(data->sioaddr);
+ if (err)
+ return err;
+
+ superio_select(data->sioaddr, PME);
+ superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG,
+ data->ec_special_config);
+ superio_exit(data->sioaddr, data->doexit);
+ }
+ return 0;
+}
+
static int _it87_read_value(struct it87_data *data, u8 reg)
{
outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
}
-static void it87_set_bank(struct it87_data *data, u8 bank)
+static u8 it87_set_bank(struct it87_data *data, u8 bank)
{
- if (has_bank_sel(data) && bank != data->bank) {
+ u8 _bank = bank;
+
+ if (has_bank_sel(data)) {
u8 breg = _it87_read_value(data, IT87_REG_BANK);
- breg &= 0x1f;
- breg |= (bank << 5);
- data->bank = bank;
- _it87_write_value(data, IT87_REG_BANK, breg);
+ _bank = breg >> 5;
+ if (bank != _bank) {
+ breg &= 0x1f;
+ breg |= (bank << 5);
+ _it87_write_value(data, IT87_REG_BANK, breg);
+ }
}
+ return _bank;
}
/*
* Must be called with data->update_lock held, except during initialization.
+ * Must be called with SMBus accesses disabled.
* We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
* would slow down the IT87 access and should not be necessary.
*/
static int it87_read_value(struct it87_data *data, u16 reg)
{
- it87_set_bank(data, reg >> 8);
- return _it87_read_value(data, reg & 0xff);
+ u8 bank;
+ int val;
+
+ bank = it87_set_bank(data, reg >> 8);
+ val = _it87_read_value(data, reg & 0xff);
+ it87_set_bank(data, bank);
+
+ return val;
}
/*
* Must be called with data->update_lock held, except during initialization.
+ * Must be called with SMBus accesses disabled
* We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
* would slow down the IT87 access and should not be necessary.
*/
static void it87_write_value(struct it87_data *data, u16 reg, u8 value)
{
- it87_set_bank(data, reg >> 8);
+ u8 bank;
+
+ bank = it87_set_bank(data, reg >> 8);
_it87_write_value(data, reg & 0xff, value);
+ it87_set_bank(data, bank);
}
static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
{
- data->pwm_ctrl[nr] = it87_read_value(data, data->REG_PWM[nr]);
+ u8 ctrl;
+
+ ctrl = it87_read_value(data, data->REG_PWM[nr]);
+ data->pwm_ctrl[nr] = ctrl;
if (has_newer_autopwm(data)) {
- data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
+ data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
data->pwm_duty[nr] = it87_read_value(data,
IT87_REG_PWM_DUTY[nr]);
} else {
- if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */
- data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
+ if (ctrl & 0x80) /* Automatic mode */
+ data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
else /* Manual mode */
- data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f;
+ data->pwm_duty[nr] = ctrl & 0x7f;
}
if (has_old_autopwm(data)) {
}
}
+static int it87_lock(struct it87_data *data)
+{
+ int err;
+
+ mutex_lock(&data->update_lock);
+ err = smbus_disable(data);
+ if (err)
+ mutex_unlock(&data->update_lock);
+ return err;
+}
+
+static void it87_unlock(struct it87_data *data)
+{
+ smbus_enable(data);
+ mutex_unlock(&data->update_lock);
+}
+
static struct it87_data *it87_update_device(struct device *dev)
{
struct it87_data *data = dev_get_drvdata(dev);
+ int err;
int i;
- mutex_lock(&data->update_lock);
+ err = it87_lock(data);
+ if (err)
+ return ERR_PTR(err);
if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
!data->valid) {
if (i >= data->num_temp_limit)
continue;
- if (has_temp_offset(data))
+ if (i < data->num_temp_offset)
data->temp[i][3] =
it87_read_value(data,
data->REG_TEMP_OFFSET[i]);
data->last_updated = jiffies;
data->valid = 1;
}
-
- mutex_unlock(&data->update_lock);
-
+ it87_unlock(data);
return data;
}
int index = sattr->index;
int nr = sattr->nr;
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
}
int index = sattr->index;
int nr = sattr->nr;
unsigned long val;
+ int err;
if (kstrtoul(buf, 10, &val) < 0)
return -EINVAL;
- mutex_lock(&data->update_lock);
+ err = it87_lock(data);
+ if (err)
+ return err;
+
data->in[nr][index] = in_to_reg(data, nr, val);
it87_write_value(data,
index == 1 ? IT87_REG_VIN_MIN(nr)
: IT87_REG_VIN_MAX(nr),
data->in[nr][index]);
- mutex_unlock(&data->update_lock);
+ it87_unlock(data);
return count;
}
int index = sattr->index;
struct it87_data *data = it87_update_device(dev);
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
}
struct it87_data *data = dev_get_drvdata(dev);
long val;
u8 reg, regval;
+ int err;
if (kstrtol(buf, 10, &val) < 0)
return -EINVAL;
- mutex_lock(&data->update_lock);
+ err = it87_lock(data);
+ if (err)
+ return err;
switch (index) {
default:
data->temp[nr][index] = TEMP_TO_REG(val);
it87_write_value(data, reg, data->temp[nr][index]);
- mutex_unlock(&data->update_lock);
+ it87_unlock(data);
return count;
}
static SENSOR_DEVICE_ATTR_2(temp6_offset, S_IRUGO | S_IWUSR, show_temp,
set_temp, 5, 3);
+static const u8 temp_types_8686[NUM_TEMP][9] = {
+ { 0, 8, 8, 8, 8, 8, 8, 8, 7 },
+ { 0, 6, 8, 8, 6, 0, 0, 0, 7 },
+ { 0, 6, 5, 8, 6, 0, 0, 0, 7 },
+ { 4, 8, 8, 8, 8, 8, 8, 8, 7 },
+ { 4, 6, 8, 8, 6, 0, 0, 0, 7 },
+ { 4, 6, 5, 8, 6, 0, 0, 0, 7 },
+};
+
static int get_temp_type(struct it87_data *data, int index)
{
u8 reg, extra;
int type = 0;
if (has_bank_sel(data)) {
- int s1reg = IT87_REG_TEMP_SRC1[index/2] >> ((index % 2) * 4);
u8 src1, src2;
- src1 = (it87_read_value(data, s1reg) >> ((index % 2) * 4)) & 0x0f;
- src2 = it87_read_value(data, IT87_REG_TEMP_SRC2);
+ src1 = (data->temp_src[index / 2] >> ((index % 2) * 4)) & 0x0f;
switch (data->type) {
case it8686:
- switch (src1) {
- case 0:
- if (index >= 3)
- return 4;
- break;
- case 1:
- if (index == 1 || index == 2 ||
- index == 4 || index == 5)
- return 6;
- break;
- case 2:
- if (index == 2 || index == 6)
- return 5;
- break;
- default:
- break;
- }
+ if (src1 < 9)
+ type = temp_types_8686[index][src1];
break;
+ case it8625:
+ if (index < 3)
+ break;
case it8655:
case it8665:
if (src1 < 3) {
index = src1;
break;
}
+ src2 = data->temp_src[3];
switch(src1) {
case 3:
type = (src2 & BIT(index)) ? 6 : 5;
return 0;
}
}
- if (index >= 3)
- return 0;
+ if (type || index >= 3)
+ return type;
reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
{
struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
struct it87_data *data = it87_update_device(dev);
- int type = get_temp_type(data, sensor_attr->index);
+ int type;
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
+ type = get_temp_type(data, sensor_attr->index);
return sprintf(buf, "%d\n", type);
}
struct it87_data *data = dev_get_drvdata(dev);
long val;
u8 reg, extra;
+ int err;
if (kstrtol(buf, 10, &val) < 0)
return -EINVAL;
+ err = it87_lock(data);
+ if (err)
+ return err;
+
reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
reg &= ~(1 << nr);
reg &= ~(8 << nr);
reg |= (nr + 1) << 6;
else if (has_temp_old_peci(data, nr) && val == 6)
extra |= 0x80;
- else if (val != 0)
- return -EINVAL;
+ else if (val != 0) {
+ count = -EINVAL;
+ goto unlock;
+ }
- mutex_lock(&data->update_lock);
data->sensor = reg;
data->extra = extra;
it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor);
if (has_temp_old_peci(data, nr))
it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
data->valid = 0; /* Force cache refresh */
- mutex_unlock(&data->update_lock);
+unlock:
+ it87_unlock(data);
return count;
}
int speed;
struct it87_data *data = it87_update_device(dev);
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
speed = has_16bit_fans(data) ?
FAN16_FROM_REG(data->fan[nr][index]) :
FAN_FROM_REG(data->fan[nr][index],
struct it87_data *data = it87_update_device(dev);
int nr = sensor_attr->index;
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
}
struct it87_data *data = it87_update_device(dev);
int nr = sensor_attr->index;
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
return sprintf(buf, "%d\n", pwm_mode(data, nr));
}
struct it87_data *data = it87_update_device(dev);
int nr = sensor_attr->index;
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
return sprintf(buf, "%d\n",
pwm_from_reg(data, data->pwm_duty[nr]));
}
unsigned int freq;
int index;
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
if (has_pwm_freq2(data) && nr == 1)
index = (data->extra >> 4) & 0x07;
else
struct it87_data *data = dev_get_drvdata(dev);
long val;
+ int err;
u8 reg;
if (kstrtol(buf, 10, &val) < 0)
return -EINVAL;
- mutex_lock(&data->update_lock);
+ err = it87_lock(data);
+ if (err)
+ return err;
if (has_16bit_fans(data)) {
data->fan[nr][index] = FAN16_TO_REG(val);
it87_write_value(data, data->REG_FAN_MIN[nr],
data->fan[nr][index]);
}
-
- mutex_unlock(&data->update_lock);
+ it87_unlock(data);
return count;
}
struct it87_data *data = dev_get_drvdata(dev);
int nr = sensor_attr->index;
unsigned long val;
- int min;
+ int min, err;
u8 old;
if (kstrtoul(buf, 10, &val) < 0)
return -EINVAL;
- mutex_lock(&data->update_lock);
+ err = it87_lock(data);
+ if (err)
+ return err;
+
old = it87_read_value(data, IT87_REG_FAN_DIV);
/* Save fan min limit */
/* Restore fan min limit */
data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
it87_write_value(data, data->REG_FAN_MIN[nr], data->fan[nr][1]);
-
- mutex_unlock(&data->update_lock);
+ it87_unlock(data);
return count;
}
struct it87_data *data = dev_get_drvdata(dev);
int nr = sensor_attr->index;
long val;
+ int err;
if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
return -EINVAL;
return -EINVAL;
}
- mutex_lock(&data->update_lock);
+ err = it87_lock(data);
+ if (err)
+ return err;;
+
+ it87_update_pwm_ctrl(data, nr);
if (val == 0) {
if (nr < 3 && has_fanctl_onoff(data)) {
data->pwm_duty[nr]);
/* and set manual mode */
if (has_newer_autopwm(data)) {
- ctrl = (data->pwm_ctrl[nr] & 0x7c) |
- data->pwm_temp_map[nr];
+ ctrl = temp_map_to_reg(data, nr,
+ data->pwm_temp_map[nr]);
+ ctrl &= 0x7f;
} else {
ctrl = data->pwm_duty[nr];
}
u8 ctrl;
if (has_newer_autopwm(data)) {
- ctrl = (data->pwm_ctrl[nr] & 0x7c) |
- data->pwm_temp_map[nr];
- if (val != 1)
+ ctrl = temp_map_to_reg(data, nr,
+ data->pwm_temp_map[nr]);
+ if (val == 1)
+ ctrl &= 0x7f;
+ else
ctrl |= 0x80;
} else {
ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80);
data->fan_main_ctrl);
}
}
-
- mutex_unlock(&data->update_lock);
+ it87_unlock(data);
return count;
}
struct it87_data *data = dev_get_drvdata(dev);
int nr = sensor_attr->index;
long val;
+ int err;
if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
return -EINVAL;
- mutex_lock(&data->update_lock);
+ err = it87_lock(data);
+ if (err)
+ return err;
+
it87_update_pwm_ctrl(data, nr);
if (has_newer_autopwm(data)) {
/*
* is read-only so we can't write the value.
*/
if (data->pwm_ctrl[nr] & 0x80) {
- mutex_unlock(&data->update_lock);
- return -EBUSY;
+ count = -EBUSY;
+ goto unlock;
}
data->pwm_duty[nr] = pwm_to_reg(data, val);
it87_write_value(data, IT87_REG_PWM_DUTY[nr],
data->pwm_ctrl[nr]);
}
}
- mutex_unlock(&data->update_lock);
+unlock:
+ it87_unlock(data);
return count;
}
struct it87_data *data = dev_get_drvdata(dev);
int nr = sensor_attr->index;
unsigned long val;
+ int err;
int i;
if (kstrtoul(buf, 10, &val) < 0)
break;
}
- mutex_lock(&data->update_lock);
+ err = it87_lock(data);
+ if (err)
+ return err;
+
if (nr == 0) {
data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f;
data->fan_ctl |= i << 4;
data->extra |= i << 4;
it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
}
- mutex_unlock(&data->update_lock);
-
+ it87_unlock(data);
return count;
}
struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
struct it87_data *data = it87_update_device(dev);
int nr = sensor_attr->index;
- int map;
- map = data->pwm_temp_map[nr];
- if (map >= 3)
- map = 0; /* Should never happen */
- if (nr >= 3) /* pwm channels 3..6 map to temp4..6 */
- map += 3;
+ if (IS_ERR(data))
+ return PTR_ERR(data);
- return sprintf(buf, "%d\n", (int)BIT(map));
+ return sprintf(buf, "%d\n", data->pwm_temp_map[nr] + 1);
}
static ssize_t set_pwm_temp_map(struct device *dev,
struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
struct it87_data *data = dev_get_drvdata(dev);
int nr = sensor_attr->index;
- long val;
- u8 reg;
+ unsigned long val;
+ int err;
+ u8 map;
- if (kstrtol(buf, 10, &val) < 0)
+ if (kstrtoul(buf, 10, &val) < 0)
return -EINVAL;
- if (nr >= 3)
- val -= 3;
-
- switch (val) {
- case BIT(0):
- reg = 0x00;
- break;
- case BIT(1):
- reg = 0x01;
- break;
- case BIT(2):
- reg = 0x02;
- break;
- default:
+ if (!val || val > data->pwm_num_temp_map)
return -EINVAL;
- }
- mutex_lock(&data->update_lock);
+ map = val - 1;
+
+ err = it87_lock(data);
+ if (err)
+ return err;
+
it87_update_pwm_ctrl(data, nr);
- data->pwm_temp_map[nr] = reg;
+ data->pwm_temp_map[nr] = map;
/*
* If we are in automatic mode, write the temp mapping immediately;
* otherwise, just store it for later use.
*/
if (data->pwm_ctrl[nr] & 0x80) {
- data->pwm_ctrl[nr] = (data->pwm_ctrl[nr] & 0xfc) |
- data->pwm_temp_map[nr];
+ data->pwm_ctrl[nr] = temp_map_to_reg(data, nr, map);
it87_write_value(data, data->REG_PWM[nr], data->pwm_ctrl[nr]);
}
- mutex_unlock(&data->update_lock);
+ it87_unlock(data);
return count;
}
int nr = sensor_attr->nr;
int point = sensor_attr->index;
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
return sprintf(buf, "%d\n",
pwm_from_reg(data, data->auto_pwm[nr][point]));
}
int point = sensor_attr->index;
int regaddr;
long val;
+ int err;
if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
return -EINVAL;
- mutex_lock(&data->update_lock);
+ err = it87_lock(data);
+ if (err)
+ return err;
+
data->auto_pwm[nr][point] = pwm_to_reg(data, val);
if (has_newer_autopwm(data))
regaddr = IT87_REG_AUTO_TEMP(nr, 3);
else
regaddr = IT87_REG_AUTO_PWM(nr, point);
it87_write_value(data, regaddr, data->auto_pwm[nr][point]);
- mutex_unlock(&data->update_lock);
+ it87_unlock(data);
return count;
}
struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
int nr = sensor_attr->index;
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f);
}
struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
int nr = sensor_attr->index;
unsigned long val;
+ int err;
if (kstrtoul(buf, 10, &val) < 0 || val > 127)
return -EINVAL;
- mutex_lock(&data->update_lock);
+ err = it87_lock(data);
+ if (err)
+ return err;
+
data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val;
it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 4),
data->auto_pwm[nr][1]);
- mutex_unlock(&data->update_lock);
+ it87_unlock(data);
return count;
}
int point = sensor_attr->index;
int reg;
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
if (has_old_autopwm(data) || point)
reg = data->auto_temp[nr][point];
else
int point = sensor_attr->index;
long val;
int reg;
+ int err;
if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
return -EINVAL;
- mutex_lock(&data->update_lock);
+ err = it87_lock(data);
+ if (err)
+ return err;
+
if (has_newer_autopwm(data) && !point) {
reg = data->auto_temp[nr][1] - TEMP_TO_REG(val);
reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0);
point--;
it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point), reg);
}
- mutex_unlock(&data->update_lock);
+ it87_unlock(data);
return count;
}
{
struct it87_data *data = it87_update_device(dev);
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
return sprintf(buf, "%u\n", data->alarms);
}
static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
struct it87_data *data = it87_update_device(dev);
int bitnr = to_sensor_dev_attr(attr)->index;
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
}
size_t count)
{
struct it87_data *data = dev_get_drvdata(dev);
- int config;
+ int err, config;
long val;
if (kstrtol(buf, 10, &val) < 0 || val != 0)
return -EINVAL;
- mutex_lock(&data->update_lock);
- config = it87_read_value(data, IT87_REG_CONFIG);
- if (config < 0) {
- count = config;
- } else {
- config |= BIT(5);
- it87_write_value(data, IT87_REG_CONFIG, config);
- /* Invalidate cache to force re-read */
- data->valid = 0;
- }
- mutex_unlock(&data->update_lock);
+ err = it87_lock(data);
+ if (err)
+ return err;
+ config = it87_read_value(data, IT87_REG_CONFIG);
+ config |= BIT(5);
+ it87_write_value(data, IT87_REG_CONFIG, config);
+ /* Invalidate cache to force re-read */
+ data->valid = 0;
+ it87_unlock(data);
return count;
}
struct it87_data *data = it87_update_device(dev);
int bitnr = to_sensor_dev_attr(attr)->index;
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
}
int bitnr = to_sensor_dev_attr(attr)->index;
struct it87_data *data = dev_get_drvdata(dev);
long val;
+ int err;
if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1))
return -EINVAL;
- mutex_lock(&data->update_lock);
+ err = it87_lock(data);
+ if (err)
+ return err;
+
data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
if (val)
data->beeps |= BIT(bitnr);
else
data->beeps &= ~BIT(bitnr);
it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps);
- mutex_unlock(&data->update_lock);
+ it87_unlock(data);
return count;
}
{
struct it87_data *data = it87_update_device(dev);
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm));
}
static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
return attr->mode;
}
- if (a == 5 && !has_temp_offset(data))
+ if (a == 5 && i >= data->num_temp_offset)
return 0;
if (a == 6 && !data->has_beep)
static int __init it87_find(int sioaddr, unsigned short *address,
struct it87_sio_data *sio_data)
{
- int err;
- u16 chip_type;
const struct it87_devices *config;
+ bool doexit = true;
+ u16 chip_type;
+ int err;
err = superio_enter(sioaddr);
if (err)
return err;
+ sio_data->sioaddr = sioaddr;
+
err = -ENODEV;
chip_type = superio_inw(sioaddr, DEVID);
if (chip_type == 0xffff)
break;
case IT8792E_DEVID:
sio_data->type = it8792;
+ /*
+ * Disabling configuration mode on IT8792E can result in system
+ * hang-ups and access failures to the Super-IO chip at the
+ * second SIO address. Never exit configuration mode on this
+ * chip to avoid the problem.
+ */
+ doexit = false;
break;
case IT8771E_DEVID:
sio_data->type = it8771;
break;
case IT8790E_DEVID:
sio_data->type = it8790;
+ doexit = false; /* See IT8792E comment above */
break;
case IT8603E_DEVID:
case IT8623E_DEVID:
case IT8607E_DEVID:
sio_data->type = it8607;
break;
+ case IT8613E_DEVID:
+ sio_data->type = it8613;
+ break;
case IT8620E_DEVID:
sio_data->type = it8620;
break;
case IT8622E_DEVID:
sio_data->type = it8622;
break;
+ case IT8625E_DEVID:
+ sio_data->type = it8625;
+ break;
case IT8628E_DEVID:
sio_data->type = it8628;
break;
goto exit;
}
+ sio_data->doexit = doexit;
+
err = 0;
sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
pr_info("Found IT%04x%s chip at 0x%x, revision %d\n", chip_type,
if (reg29 & BIT(2))
sio_data->skip_fan |= BIT(1);
- if (sio_data->type == it8603) {
+ switch (sio_data->type) {
+ case it8603:
sio_data->skip_in |= BIT(5); /* No VIN5 */
sio_data->skip_in |= BIT(6); /* No VIN6 */
+ break;
+ case it8607:
+ sio_data->skip_pwm |= BIT(0);/* No fan1 */
+ sio_data->skip_fan |= BIT(0);
+ default:
+ break;
+ }
+
+ sio_data->beep_pin = superio_inb(sioaddr,
+ IT87_SIO_BEEP_PIN_REG) & 0x3f;
+ } else if (sio_data->type == it8613) {
+ int reg27, reg29, reg2a;
+
+ superio_select(sioaddr, GPIO);
+
+ /* Check for pwm3, fan3, pwm5, fan5 */
+ reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
+ if (reg27 & BIT(1))
+ sio_data->skip_fan |= BIT(4);
+ if (reg27 & BIT(3))
+ sio_data->skip_pwm |= BIT(4);
+ if (reg27 & BIT(6))
+ sio_data->skip_pwm |= BIT(2);
+ if (reg27 & BIT(7))
+ sio_data->skip_fan |= BIT(2);
+
+ /* Check for pwm2, fan2 */
+ reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
+ if (reg29 & BIT(1))
+ sio_data->skip_pwm |= BIT(1);
+ if (reg29 & BIT(2))
+ sio_data->skip_fan |= BIT(1);
+
+ /* Check for pwm4, fan4 */
+ reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
+ if (!(reg2a & BIT(0)) || (reg29 & BIT(7))) {
+ sio_data->skip_fan |= BIT(3);
+ sio_data->skip_pwm |= BIT(3);
}
+ sio_data->skip_pwm |= BIT(0); /* No pwm1 */
+ sio_data->skip_fan |= BIT(0); /* No fan1 */
+ sio_data->skip_in |= BIT(3); /* No VIN3 */
+ sio_data->skip_in |= BIT(6); /* No VIN6 */
+
sio_data->beep_pin = superio_inb(sioaddr,
IT87_SIO_BEEP_PIN_REG) & 0x3f;
} else if (sio_data->type == it8620 || sio_data->type == it8628 ||
sio_data->beep_pin = superio_inb(sioaddr,
IT87_SIO_BEEP_PIN_REG) & 0x3f;
- } else if (sio_data->type == it8665) {
- int reg;
+ } else if (sio_data->type == it8665 || sio_data->type == it8625) {
+ int reg27, reg29, reg2d, regd3;
superio_select(sioaddr, GPIO);
- /* Check for pwm2 */
- reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
- if (reg & BIT(1))
- sio_data->skip_pwm |= BIT(1);
+ reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
+ reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
+ reg2d = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
+ regd3 = superio_inb(sioaddr, IT87_SIO_GPIO9_REG);
- /* Check for fan2 */
- reg = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
- if (reg & BIT(4))
+ /* Check for pwm2, fan2 */
+ if (reg29 & BIT(1))
+ sio_data->skip_pwm |= BIT(1);
+ /*
+ * Note: Table 6-1 in datasheet claims that FAN_TAC2
+ * would be enabled with 29h[2]=0.
+ */
+ if (reg2d & BIT(4))
sio_data->skip_fan |= BIT(1);
/* Check for pwm3, fan3 */
- reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
- if (reg & BIT(6))
+ if (reg27 & BIT(6))
sio_data->skip_pwm |= BIT(2);
- if (reg & BIT(7))
+ if (reg27 & BIT(7))
sio_data->skip_fan |= BIT(2);
- /* Check for pwm5, fan5 */
- reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
- if (reg & BIT(5))
- sio_data->skip_pwm |= BIT(4);
- if (!(reg & BIT(4)))
- sio_data->skip_fan |= BIT(4);
+ /* Check for pwm4, fan4, pwm5, fan5 */
+ if (sio_data->type == it8625) {
+ int reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
+
+ if (reg25 & BIT(6))
+ sio_data->skip_fan |= BIT(3);
+ if (reg25 & BIT(5))
+ sio_data->skip_pwm |= BIT(3);
+ if (reg27 & BIT(3))
+ sio_data->skip_pwm |= BIT(4);
+ if (reg27 & BIT(1))
+ sio_data->skip_fan |= BIT(4);
+ } else {
+ int reg26 = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
+
+ if (regd3 & BIT(2))
+ sio_data->skip_pwm |= BIT(3);
+ if (regd3 & BIT(3))
+ sio_data->skip_fan |= BIT(3);
+ if (reg26 & BIT(5))
+ sio_data->skip_pwm |= BIT(4);
+ if (reg26 & BIT(4))
+ sio_data->skip_fan |= BIT(4);
+ }
- /* Check for pwm4, fan4, pwm6, fan6 */
- reg = superio_inb(sioaddr, IT87_SIO_GPIO9_REG);
- if (reg & BIT(2))
- sio_data->skip_pwm |= BIT(3);
- if (reg & BIT(3))
- sio_data->skip_fan |= BIT(3);
- if (reg & BIT(0))
+ /* Check for pwm6, fan6 */
+ if (regd3 & BIT(0))
sio_data->skip_pwm |= BIT(5);
- if (reg & BIT(1))
+ if (regd3 & BIT(1))
sio_data->skip_fan |= BIT(5);
sio_data->beep_pin = superio_inb(sioaddr,
if (sio_data->beep_pin)
pr_info("Beeping is supported\n");
+ if (config->smbus_bitmap) {
+ u8 reg;
+
+ superio_select(sioaddr, PME);
+ reg = superio_inb(sioaddr, IT87_SPECIAL_CFG_REG);
+ sio_data->ec_special_config = reg;
+ sio_data->smbus_bitmap = reg & config->smbus_bitmap;
+ }
+
exit:
- superio_exit(sioaddr);
+ superio_exit(sioaddr, doexit);
return err;
}
-/* Called when we have found a new IT87. */
-static void it87_init_device(struct platform_device *pdev)
+static void it87_init_regs(struct platform_device *pdev)
{
- struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
struct it87_data *data = platform_get_drvdata(pdev);
- int tmp, i;
- u8 mask;
/* Initialize chip specific register pointers */
switch (data->type) {
+ case it8628:
case it8686:
data->REG_FAN = IT87_REG_FAN;
data->REG_FANX = IT87_REG_FANX;
data->REG_TEMP_LOW = IT87_REG_TEMP_LOW_8686;
data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH_8686;
break;
+ case it8625:
case it8655:
case it8665:
data->REG_FAN = IT87_REG_FAN_8665;
data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
break;
+ case it8613:
+ data->REG_FAN = IT87_REG_FAN;
+ data->REG_FANX = IT87_REG_FANX;
+ data->REG_FAN_MIN = IT87_REG_FAN_MIN;
+ data->REG_FANX_MIN = IT87_REG_FANX_MIN;
+ data->REG_PWM = IT87_REG_PWM_8665;
+ data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
+ data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
+ data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
+ break;
default:
data->REG_FAN = IT87_REG_FAN;
data->REG_FANX = IT87_REG_FANX;
data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
break;
}
+}
+
+/* Called when we have found a new IT87. */
+static void it87_init_device(struct platform_device *pdev)
+{
+ struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
+ struct it87_data *data = platform_get_drvdata(pdev);
+ int tmp, i;
+ u8 mask;
+
+ if (has_new_tempmap(data)) {
+ data->pwm_temp_map_shift = 3;
+ data->pwm_temp_map_mask = 0x07;
+ } else {
+ data->pwm_temp_map_shift = 0;
+ data->pwm_temp_map_mask = 0x03;
+ }
/*
* For each PWM channel:
* the fan to full speed by default.
* - If it is in manual mode, we need a mapping to temperature
* channels to use when later setting to automatic mode later.
- * Use a 1:1 mapping by default (we are clueless.)
+ * Map to the first sensor by default (we are clueless.)
* In both cases, the value can (and should) be changed by the user
* prior to switching to a different mode.
* Note that this is no longer needed for the IT8721F and later, as
* manual duty cycle.
*/
for (i = 0; i < NUM_AUTO_PWM; i++) {
- data->pwm_temp_map[i] = i;
+ data->pwm_temp_map[i] = 0;
data->pwm_duty[i] = 0x7f; /* Full speed */
data->auto_pwm[i][3] = 0x7f; /* Full speed, hard-coded */
}
if (tmp & BIT(2))
data->has_fan |= BIT(5); /* fan6 enabled */
break;
+ case it8625:
case it8665:
tmp = it87_read_value(data, IT87_REG_FAN_DIV);
if (tmp & BIT(3))
}
}
+ if (has_bank_sel(data)) {
+ for (i = 0; i < 3; i++)
+ data->temp_src[i] =
+ it87_read_value(data, IT87_REG_TEMP_SRC1[i]);
+ data->temp_src[3] = it87_read_value(data, IT87_REG_TEMP_SRC2);
+ }
+
/* Start monitoring */
it87_write_value(data, IT87_REG_CONFIG,
(it87_read_value(data, IT87_REG_CONFIG) & 0x3e)
struct it87_sio_data *sio_data = dev_get_platdata(dev);
int enable_pwm_interface;
struct device *hwmon_dev;
+ int err;
res = platform_get_resource(pdev, IORESOURCE_IO, 0);
if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT,
data->addr = res->start;
data->type = sio_data->type;
+ data->sioaddr = sio_data->sioaddr;
+ data->smbus_bitmap = sio_data->smbus_bitmap;
+ data->ec_special_config = sio_data->ec_special_config;
+ data->doexit = sio_data->doexit;
data->features = it87_devices[sio_data->type].features;
data->num_temp_limit = it87_devices[sio_data->type].num_temp_limit;
+ data->num_temp_offset = it87_devices[sio_data->type].num_temp_offset;
+ data->pwm_num_temp_map = it87_devices[sio_data->type].num_temp_map;
data->peci_mask = it87_devices[sio_data->type].peci_mask;
data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
- data->bank = 0xff;
/*
* IT8705F Datasheet 0.4.1, 3h == Version G.
break;
}
- /* Now, we do the remaining detection. */
- if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80) ||
- it87_read_value(data, IT87_REG_CHIPID) != 0x90)
- return -ENODEV;
-
platform_set_drvdata(pdev, data);
mutex_init(&data->update_lock);
+ /* Initialize register pointers */
+ it87_init_regs(pdev);
+
+ err = smbus_disable(data);
+ if (err)
+ return err;
+
+ /* Now, we do the remaining detection. */
+ if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80) ||
+ it87_read_value(data, IT87_REG_CHIPID) != 0x90) {
+ smbus_enable(data);
+ return -ENODEV;
+ }
+
/* Check PWM configuration */
enable_pwm_interface = it87_check_pwm(dev);
/* Initialize the IT87 chip */
it87_init_device(pdev);
+ smbus_enable(data);
+
if (!sio_data->skip_vid) {
data->has_vid = true;
data->vrm = vid_which_vrm();
int err;
err = acpi_check_resource_conflict(&res);
- if (err)
- return err;
+ if (err) {
+ if (!ignore_resource_conflict)
+ return err;
+ }
pdev = platform_device_alloc(DRVNAME, address);
if (!pdev)
}
struct it87_dmi_data {
- bool sio4e_broken; /* SIO accesses @ 0x4e are broken */
- char *sio_mutex; /* SIO ACPI mutex */
+ bool sio2_force_config; /* force sio2 into configuration mode */
u8 skip_pwm; /* pwm channels to skip for this board */
};
/*
- * On Gigabyte AB350 boards, accesses to the Super-IO chip
- * at address 0x4e/0x4f can result in a system hang.
- * Accesses to address 0x2e/0x2f need to be mutex protected.
+ * On various Gigabyte AM4 boards (AB350, AX370), the second Super-IO chip
+ * (IT8792E) needs to be in configuration mode before accessing the first
+ * due to a bug in IT8792E which otherwise results in LPC bus access errors.
+ * This needs to be done before accessing the first Super-IO chip since
+ * the second chip may have been accessed prior to loading this driver.
+ *
+ * The problem is also reported to affect IT8795E, which is used on X299 boards
+ * and has the same chip ID as IT8792E (0x8733). It also appears to affect
+ * systems with IT8790E, which is used on some Z97X-Gaming boards as well as
+ * Z87X-OC.
+ * DMI entries for those systems will be added as they become available and
+ * as the problem is confirmed to affect those boards.
*/
-static struct it87_dmi_data gigabyte_ab350_gaming = {
- .sio4e_broken = true,
- .sio_mutex = "\\_SB.PCI0.SBRG.SIO1.MUT0",
+static struct it87_dmi_data gigabyte_sio2_force = {
+ .sio2_force_config = true,
};
/*
{
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
- DMI_MATCH(DMI_BOARD_NAME, "AB350-Gaming-CF"),
+ DMI_MATCH(DMI_BOARD_NAME, "AB350"),
},
- .driver_data = &gigabyte_ab350_gaming,
+ .driver_data = &gigabyte_sio2_force,
},
{
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
- DMI_MATCH(DMI_BOARD_NAME, "AB350-Gaming 3-CF"),
+ DMI_MATCH(DMI_BOARD_NAME, "AX370"),
},
- .driver_data = &gigabyte_ab350_gaming,
+ .driver_data = &gigabyte_sio2_force,
+ },
+ {
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
+ DMI_MATCH(DMI_BOARD_NAME, "Z97X-Gaming G1"),
+ },
+ .driver_data = &gigabyte_sio2_force,
},
{
.matches = {
bool found = false;
int i, err;
+ pr_info("it87 driver version %s\n", IT87_DRIVER_VERSION);
+
if (dmi)
dmi_data = dmi->driver_data;
- if (dmi_data) {
- it87_sio4e_broken = dmi_data->sio4e_broken;
-#ifdef __IT87_USE_ACPI_MUTEX
- if (dmi_data->sio_mutex) {
- static acpi_status status;
-
- status = acpi_get_handle(NULL, dmi_data->sio_mutex,
- &it87_acpi_sio_handle);
- if (ACPI_SUCCESS(status)) {
- it87_acpi_sio_mutex = dmi_data->sio_mutex;
- pr_debug("Found ACPI SIO mutex %s\n",
- dmi_data->sio_mutex);
- } else {
- pr_warn("ACPI SIO mutex %s not found\n",
- dmi_data->sio_mutex);
- }
- }
-#endif /* __IT87_USE_ACPI_MUTEX */
- }
-
err = platform_driver_register(&it87_driver);
if (err)
return err;
+ if (dmi_data && dmi_data->sio2_force_config)
+ __superio_enter(REG_4E);
+
for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
memset(&sio_data, 0, sizeof(struct it87_sio_data));
isa_address = 0;
projects / groeck-it87 / blobdiff