* similar parts. The other devices are supported by different drivers.
*
* Supports: IT8603E Super I/O chip w/LPC interface
+ * IT8606E Super I/O chip w/LPC interface
* IT8607E Super I/O chip w/LPC interface
* IT8613E Super I/O chip w/LPC interface
* IT8620E Super I/O chip w/LPC interface
* IT8726F Super I/O chip w/LPC interface
* IT8728F Super I/O chip w/LPC interface
* IT8732F Super I/O chip w/LPC interface
+ * IT8736F Super I/O chip w/LPC interface
+ * IT8738E Super I/O chip w/LPC interface
* IT8758E Super I/O chip w/LPC interface
* IT8771E Super I/O chip w/LPC interface
* IT8772E Super I/O chip w/LPC interface
#define DRVNAME "it87"
enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
+ it8736, it8738,
it8771, it8772, it8781, it8782, it8783, it8786, it8790,
- it8792, it8603, it8607, it8613, it8620, it8622, it8625, it8628,
- it8655, it8665, it8686 };
+ it8792, it8603, it8606, it8607, it8613, it8620, it8622, it8625,
+ it8628, it8655, it8665, it8686 };
static unsigned short force_id;
module_param(force_id, ushort, 0000);
#define IT8726F_DEVID 0x8726
#define IT8728F_DEVID 0x8728
#define IT8732F_DEVID 0x8732
+#define IT8736F_DEVID 0x8736
+#define IT8738E_DEVID 0x8738
#define IT8792E_DEVID 0x8733
#define IT8771E_DEVID 0x8771
#define IT8772E_DEVID 0x8772
#define IT8786E_DEVID 0x8786
#define IT8790E_DEVID 0x8790
#define IT8603E_DEVID 0x8603
+#define IT8606E_DEVID 0x8606
#define IT8607E_DEVID 0x8607
#define IT8613E_DEVID 0x8613
#define IT8620E_DEVID 0x8620
/*----- The IT87 registers -----*/
-#define IT87_REG_CONFIG 0x00
+#define IT87_REG_CONFIG 0x00
-#define IT87_REG_ALARM1 0x01
-#define IT87_REG_ALARM2 0x02
-#define IT87_REG_ALARM3 0x03
+#define IT87_REG_ALARM1 0x01
+#define IT87_REG_ALARM2 0x02
+#define IT87_REG_ALARM3 0x03
#define IT87_REG_BANK 0x06
* The IT8718F and IT8720F have the VID value in a different register, in
* Super-I/O configuration space.
*/
-#define IT87_REG_VID 0x0a
+#define IT87_REG_VID 0x0a
+
+/* Interface Selection register on other chips */
+#define IT87_REG_IFSEL 0x0a
+
/*
* The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
* for fan divisors. Later IT8712F revisions must use 16-bit tachometer
* mode.
*/
-#define IT87_REG_FAN_DIV 0x0b
-#define IT87_REG_FAN_16BIT 0x0c
+#define IT87_REG_FAN_DIV 0x0b
+#define IT87_REG_FAN_16BIT 0x0c
/*
* Monitors:
static const u8 IT87_REG_TEMP_OFFSET_8686[] = {
0x56, 0x57, 0x59, 0x90, 0x91, 0x92 };
-#define IT87_REG_FAN_MAIN_CTRL 0x13
-#define IT87_REG_FAN_CTL 0x14
+#define IT87_REG_FAN_MAIN_CTRL 0x13
+#define IT87_REG_FAN_CTL 0x14
static const u8 IT87_REG_PWM[] = { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
static const u8 IT87_REG_PWM_8665[] = { 0x15, 0x16, 0x17, 0x1e, 0x1f, 0x92 };
static const u8 IT87_REG_VIN[] = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
-#define IT87_REG_TEMP(nr) (0x29 + (nr))
+#define IT87_REG_TEMP(nr) (0x29 + (nr))
-#define IT87_REG_VIN_MAX(nr) (0x30 + (nr) * 2)
-#define IT87_REG_VIN_MIN(nr) (0x31 + (nr) * 2)
+#define IT87_REG_VIN_MAX(nr) (0x30 + (nr) * 2)
+#define IT87_REG_VIN_MIN(nr) (0x31 + (nr) * 2)
static const u8 IT87_REG_TEMP_HIGH[] = { 0x40, 0x42, 0x44, 0x46, 0xb4, 0xb6 };
static const u8 IT87_REG_TEMP_LOW[] = { 0x41, 0x43, 0x45, 0x47, 0xb5, 0xb7 };
static const u8 IT87_REG_TEMP_LOW_8686[] = {
0x41, 0x43, 0x45, 0xb5, 0xb7, 0xb9 };
-#define IT87_REG_VIN_ENABLE 0x50
-#define IT87_REG_TEMP_ENABLE 0x51
-#define IT87_REG_TEMP_EXTRA 0x55
-#define IT87_REG_BEEP_ENABLE 0x5c
+#define IT87_REG_VIN_ENABLE 0x50
+#define IT87_REG_TEMP_ENABLE 0x51
+#define IT87_REG_TEMP_EXTRA 0x55
+#define IT87_REG_BEEP_ENABLE 0x5c
-#define IT87_REG_CHIPID 0x58
+#define IT87_REG_CHIPID 0x58
static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
struct it87_devices {
const char *name;
- const char * const suffix;
+ const char * const model;
u32 features;
u8 num_temp_limit;
u8 num_temp_offset;
static const struct it87_devices it87_devices[] = {
[it87] = {
.name = "it87",
- .suffix = "F",
+ .model = "IT87F",
.features = FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF,
/* may need to overwrite */
.num_temp_limit = 3,
},
[it8712] = {
.name = "it8712",
- .suffix = "F",
+ .model = "IT8712F",
.features = FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF,
/* may need to overwrite */
.num_temp_limit = 3,
},
[it8716] = {
.name = "it8716",
- .suffix = "F",
+ .model = "IT8716F",
.features = FEAT_16BIT_FANS | FEAT_VID
| FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2
| FEAT_FANCTL_ONOFF,
},
[it8718] = {
.name = "it8718",
- .suffix = "F",
+ .model = "IT8718F",
.features = FEAT_16BIT_FANS | FEAT_VID
| FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
| FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
},
[it8720] = {
.name = "it8720",
- .suffix = "F",
+ .model = "IT8720F",
.features = FEAT_16BIT_FANS | FEAT_VID
| FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
| FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
},
[it8721] = {
.name = "it8721",
- .suffix = "F",
+ .model = "IT8721F",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
| FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
| FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
},
[it8728] = {
.name = "it8728",
- .suffix = "F",
+ .model = "IT8728F",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
| FEAT_TEMP_PECI | FEAT_FIVE_FANS
| FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_SCALING
},
[it8732] = {
.name = "it8732",
- .suffix = "F",
+ .model = "IT8732F",
.features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
| FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
| FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS
- | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF,
+ | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF | FEAT_SCALING,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
+ .peci_mask = 0x07,
+ .old_peci_mask = 0x02, /* Actually reports PCH */
+ },
+ [it8736] = {
+ .name = "it8736",
+ .model = "IT8736F",
+ .features = FEAT_16BIT_FANS
+ | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
+ | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS
+ | FEAT_FANCTL_ONOFF | FEAT_SCALING,
.num_temp_limit = 3,
.num_temp_offset = 3,
.num_temp_map = 3,
.peci_mask = 0x07,
.old_peci_mask = 0x02, /* Actually reports PCH */
},
+ [it8738] = {
+ .name = "it8738",
+ .model = "IT8738E",
+ .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
+ | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
+ | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL
+ | FEAT_FANCTL_ONOFF | FEAT_SCALING
+ | FEAT_AVCC3,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
+ .peci_mask = 0x07,
+ .old_peci_mask = 0x02,
+ },
[it8771] = {
.name = "it8771",
- .suffix = "E",
+ .model = "IT8771E",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
| FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
| FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
},
[it8772] = {
.name = "it8772",
- .suffix = "E",
+ .model = "IT8772E",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
| FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
| FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
},
[it8781] = {
.name = "it8781",
- .suffix = "F",
+ .model = "IT8781F",
.features = FEAT_16BIT_FANS
| FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
| FEAT_FANCTL_ONOFF,
},
[it8782] = {
.name = "it8782",
- .suffix = "F",
+ .model = "IT8782F",
.features = FEAT_16BIT_FANS
| FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
| FEAT_FANCTL_ONOFF,
},
[it8783] = {
.name = "it8783",
- .suffix = "E/F",
+ .model = "IT8783E/F",
.features = FEAT_16BIT_FANS
| FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
| FEAT_FANCTL_ONOFF,
},
[it8786] = {
.name = "it8786",
- .suffix = "E",
+ .model = "IT8786E",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
| FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
| FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
},
[it8790] = {
.name = "it8790",
- .suffix = "E",
+ .model = "IT8790E",
.features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
| FEAT_16BIT_FANS | FEAT_TEMP_PECI
| FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
},
[it8792] = {
.name = "it8792",
- .suffix = "E",
+ .model = "IT8792E/IT8795E",
.features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
| FEAT_16BIT_FANS | FEAT_TEMP_PECI
| FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
},
[it8603] = {
.name = "it8603",
- .suffix = "E",
+ .model = "IT8603E",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
| FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
| FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
.num_temp_map = 4,
.peci_mask = 0x07,
},
+ [it8606] = {
+ .name = "it8606",
+ .model = "IT8606E",
+ .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
+ | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
+ | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .num_temp_map = 3,
+ .peci_mask = 0x07,
+ },
[it8607] = {
.name = "it8607",
- .suffix = "E",
+ .model = "IT8607E",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
| FEAT_TEMP_PECI | FEAT_IN7_INTERNAL | FEAT_NEW_TEMPMAP
| FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING
},
[it8613] = {
.name = "it8613",
- .suffix = "E",
+ .model = "IT8613E",
.features = FEAT_NEWER_AUTOPWM | FEAT_11MV_ADC | FEAT_16BIT_FANS
| FEAT_TEMP_PECI | FEAT_FIVE_FANS
| FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
},
[it8620] = {
.name = "it8620",
- .suffix = "E",
+ .model = "IT8620E",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
| FEAT_TEMP_PECI | FEAT_SIX_FANS
| FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
},
[it8622] = {
.name = "it8622",
- .suffix = "E",
+ .model = "IT8622E",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
| FEAT_TEMP_PECI | FEAT_FIVE_FANS | FEAT_FOUR_TEMP
| FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
},
[it8625] = {
.name = "it8625",
- .suffix = "E",
+ .model = "IT8625E",
.features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
| FEAT_AVCC3 | FEAT_NEW_TEMPMAP
| FEAT_11MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
},
[it8628] = {
.name = "it8628",
- .suffix = "E",
+ .model = "IT8628E",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
| FEAT_TEMP_PECI | FEAT_SIX_FANS
| FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
},
[it8655] = {
.name = "it8655",
- .suffix = "E",
+ .model = "IT8655E",
.features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
| FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
| FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_BANK_SEL
- | FEAT_MMIO,
+ | FEAT_SIX_TEMP | FEAT_MMIO,
.num_temp_limit = 6,
.num_temp_offset = 6,
.num_temp_map = 6,
},
[it8665] = {
.name = "it8665",
- .suffix = "E",
+ .model = "IT8665E",
.features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
| FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
| FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
- | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_MMIO,
+ | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_MMIO | FEAT_SIX_TEMP,
.num_temp_limit = 6,
.num_temp_offset = 6,
.num_temp_map = 6,
},
[it8686] = {
.name = "it8686",
- .suffix = "E",
+ .model = "IT8686E",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
| FEAT_SIX_FANS | FEAT_NEW_TEMPMAP
| FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
u8 old_peci_mask;
u8 smbus_bitmap; /* !=0 if SMBus needs to be disabled */
+ u8 saved_bank; /* saved bank register value */
u8 ec_special_config; /* EC special config register restore value */
u8 sioaddr; /* SIO port address */
bool doexit; /* true if exit from sio config is ok */
const u8 *REG_TEMP_HIGH;
unsigned short addr;
- const char *name;
struct mutex update_lock;
char valid; /* !=0 if following fields are valid */
unsigned long last_updated; /* In jiffies */
{
u8 map;
- map = (reg >> data->pwm_temp_map_shift) & data->pwm_temp_map_mask;
+ map = (reg >> data->pwm_temp_map_shift) & data->pwm_temp_map_mask;
if (map >= data->pwm_num_temp_map) /* map is 0-based */
map = 0;
750000,
};
+static int _it87_io_read(struct it87_data *data, u16 reg)
+{
+ outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
+ return inb_p(data->addr + IT87_DATA_REG_OFFSET);
+}
+
+static void _it87_io_write(struct it87_data *data, u16 reg, u8 value)
+{
+ outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
+ outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
+}
+
static int smbus_disable(struct it87_data *data)
{
int err;
superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG,
data->ec_special_config & ~data->smbus_bitmap);
superio_exit(data->sioaddr, data->doexit);
+ if (has_bank_sel(data) && !data->mmio)
+ data->saved_bank = _it87_io_read(data, IT87_REG_BANK);
}
return 0;
}
int err;
if (data->smbus_bitmap) {
+ if (has_bank_sel(data) && !data->mmio)
+ _it87_io_write(data, IT87_REG_BANK, data->saved_bank);
err = superio_enter(data->sioaddr);
if (err)
return err;
return 0;
}
-static int _it87_io_read(struct it87_data *data, u16 reg)
-{
- outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
- return inb_p(data->addr + IT87_DATA_REG_OFFSET);
-}
-
-static void _it87_io_write(struct it87_data *data, u16 reg, u8 value)
-{
- outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
- outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
-}
-
static u8 it87_io_set_bank(struct it87_data *data, u8 bank)
{
u8 _bank = bank;
static struct it87_data *it87_update_device(struct device *dev)
{
struct it87_data *data = dev_get_drvdata(dev);
+ struct it87_data *ret = data;
int err;
int i;
- err = it87_lock(data);
- if (err)
- return ERR_PTR(err);
+ mutex_lock(&data->update_lock);
if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
!data->valid) {
+ err = smbus_disable(data);
+ if (err) {
+ ret = ERR_PTR(err);
+ goto unlock;
+ }
if (update_vbat) {
/*
* Cleared after each update, so reenable. Value
if (!(data->has_fan & BIT(i)))
continue;
- data->fan[i][1] = data->read(data, data->REG_FAN_MIN[i]);
+ data->fan[i][1] = data->read(data,
+ data->REG_FAN_MIN[i]);
data->fan[i][0] = data->read(data, data->REG_FAN[i]);
/* Add high byte if in 16-bit mode */
if (has_16bit_fans(data)) {
}
data->last_updated = jiffies;
data->valid = 1;
+ smbus_enable(data);
}
- it87_unlock(data);
- return data;
+unlock:
+ mutex_unlock(&data->update_lock);
+ return ret;
}
static ssize_t show_in(struct device *dev, struct device_attribute *attr,
if (type)
return type;
- /* Dectect PECI vs. AMDTSI if possible */
+ /* Dectect PECI vs. AMDTSI */
ttype = 6;
- if ((has_temp_peci(data, index)) && data->type != it8721) {
- extra = data->read(data, 0x98); /* PCH/AMDTSI host status */
- if (extra & BIT(6))
+ if ((has_temp_peci(data, index)) || data->type == it8721 ||
+ data->type == it8720) {
+ extra = data->read(data, IT87_REG_IFSEL);
+ if ((extra & 0x70) == 0x40)
ttype = 5;
}
if ((has_temp_peci(data, index) && (reg >> 6 == index + 1)) ||
(has_temp_old_peci(data, index) && (extra & 0x80)))
type = ttype; /* Intel PECI or AMDTSI */
- if (reg & BIT(index))
+ else if (reg & BIT(index))
type = 3; /* thermal diode */
else if (reg & BIT(index + 3))
type = 4; /* thermistor */
val *= has_newer_autopwm(data) ? 256 : 128;
/* Search for the nearest available frequency */
- for (i = 0; i < 7; i++) {
+ for (i = 0; i < ARRAY_SIZE(pwm_freq) - 1; i++) {
if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2)
break;
}
/* SuperIO detection - will change isa_address if a chip is found */
static int __init it87_find(int sioaddr, unsigned short *address,
- phys_addr_t *mmio_address, struct it87_sio_data *sio_data)
+ phys_addr_t *mmio_address,
+ struct it87_sio_data *sio_data)
{
const struct it87_devices *config;
phys_addr_t base = 0;
case IT8732F_DEVID:
sio_data->type = it8732;
break;
+ case IT8736F_DEVID:
+ sio_data->type = it8736;
+ break;
+ case IT8738E_DEVID:
+ sio_data->type = it8738;
+ break;
case IT8792E_DEVID:
sio_data->type = it8792;
/*
case IT8623E_DEVID:
sio_data->type = it8603;
break;
+ case IT8606E_DEVID:
+ sio_data->type = it8606;
+ break;
case IT8607E_DEVID:
sio_data->type = it8607;
break;
if (base)
snprintf(mmio_str, sizeof(mmio_str), " [MMIO at %pa]", &base);
- pr_info("Found IT%04x%s chip at 0x%x%s, revision %d\n", chip_type,
- it87_devices[sio_data->type].suffix,
+ pr_info("Found %s chip at 0x%x%s, revision %d\n",
+ it87_devices[sio_data->type].model,
*address, mmio_str, sio_data->revision);
/* in7 (VSB or VCCH5V) is always internal on some chips */
sio_data->beep_pin = superio_inb(sioaddr,
IT87_SIO_BEEP_PIN_REG) & 0x3f;
- } else if (sio_data->type == it8603 || sio_data->type == it8607) {
+ } else if (sio_data->type == it8603 || sio_data->type == it8606 ||
+ sio_data->type == it8607) {
int reg27, reg29;
superio_select(sioaddr, GPIO);
sio_data->beep_pin = superio_inb(sioaddr,
IT87_SIO_BEEP_PIN_REG) & 0x3f;
- } else if (sio_data->type == it8732) {
+ } else if (sio_data->type == it8732 || sio_data->type == it8736 ||
+ sio_data->type == it8738) {
int reg;
superio_select(sioaddr, GPIO);
sio_data->skip_fan |= BIT(3);
/* Check if AVCC is on VIN3 */
- reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
- if (reg & BIT(0))
- sio_data->internal |= BIT(0);
+ if (sio_data->type != it8738) {
+ reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
+ if (reg & BIT(0))
+ sio_data->internal |= BIT(0);
+ }
sio_data->beep_pin = superio_inb(sioaddr,
IT87_SIO_BEEP_PIN_REG) & 0x3f;
reg2d = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
regd3 = superio_inb(sioaddr, IT87_SIO_GPIO9_REG);
- /* Check for pwm2, fan2 */
+ /* Check for pwm2 */
if (reg29 & BIT(1))
sio_data->skip_pwm |= BIT(1);
- /*
- * Note: Table 6-1 in datasheet claims that FAN_TAC2
- * would be enabled with 29h[2]=0.
- */
- if (reg2d & BIT(4))
- sio_data->skip_fan |= BIT(1);
/* Check for pwm3, fan3 */
if (reg27 & BIT(6))
if (reg27 & BIT(7))
sio_data->skip_fan |= BIT(2);
- /* Check for pwm4, fan4, pwm5, fan5 */
+ /* Check for fan2, pwm4, fan4, pwm5, fan5 */
if (sio_data->type == it8625) {
int reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
+ if (reg29 & BIT(2))
+ sio_data->skip_fan |= BIT(1);
if (reg25 & BIT(6))
sio_data->skip_fan |= BIT(3);
if (reg25 & BIT(5))
sio_data->skip_pwm |= BIT(3);
if (reg27 & BIT(3))
sio_data->skip_pwm |= BIT(4);
- if (reg27 & BIT(1))
+ if (!(reg27 & BIT(1)))
sio_data->skip_fan |= BIT(4);
} else {
int reg26 = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
+ if (reg2d & BIT(4))
+ sio_data->skip_fan |= BIT(1);
if (regd3 & BIT(2))
sio_data->skip_pwm |= BIT(3);
if (regd3 & BIT(3))
sio_data->skip_fan |= BIT(3);
if (reg26 & BIT(5))
sio_data->skip_pwm |= BIT(4);
- if (reg26 & BIT(4))
+ /*
+ * Table 6-1 in datasheet claims that FAN_TAC5 would
+ * be enabled with 26h[4]=0. This contradicts with the
+ * information in section 8.3.9 and with feedback from
+ * users.
+ */
+ if (!(reg26 & BIT(4)))
sio_data->skip_fan |= BIT(4);
}
/* Initialize register pointers */
it87_init_regs(pdev);
+ /*
+ * We need to disable SMBus before we can read any registers in
+ * the envmon address space, even if it is for chip identification
+ * purposes. If the chip has SMBus client support, it likely also has
+ * multi-page envmon registers, so we have to set the page anyway
+ * before accessing those registers. Kind of a chicken-and-egg
+ * problem.
+ * Fortunately, the chip was already identified through the SIO
+ * address space, only recent chips are affected, and this is just
+ * an additional safeguard.
+ */
err = smbus_disable(data);
if (err)
return err;
if (has_four_temp(data)) {
data->has_temp |= BIT(3);
} else if (has_six_temp(data)) {
- u8 reg = data->read(data, IT87_REG_TEMP456_ENABLE);
-
- /* Check for additional temperature sensors */
- if ((reg & 0x03) >= 0x02)
- data->has_temp |= BIT(3);
- if (((reg >> 2) & 0x03) >= 0x02)
- data->has_temp |= BIT(4);
- if (((reg >> 4) & 0x03) >= 0x02)
- data->has_temp |= BIT(5);
-
- /* Check for additional voltage sensors */
- if ((reg & 0x03) == 0x01)
- data->has_in |= BIT(10);
- if (((reg >> 2) & 0x03) == 0x01)
- data->has_in |= BIT(11);
- if (((reg >> 4) & 0x03) == 0x01)
- data->has_in |= BIT(12);
+ if (sio_data->type == it8655 || sio_data->type == it8665) {
+ data->has_temp |= BIT(3) | BIT(4) | BIT(5);
+ } else {
+ u8 reg = data->read(data, IT87_REG_TEMP456_ENABLE);
+
+ /* Check for additional temperature sensors */
+ if ((reg & 0x03) >= 0x02)
+ data->has_temp |= BIT(3);
+ if (((reg >> 2) & 0x03) >= 0x02)
+ data->has_temp |= BIT(4);
+ if (((reg >> 4) & 0x03) >= 0x02)
+ data->has_temp |= BIT(5);
+
+ /* Check for additional voltage sensors */
+ if ((reg & 0x03) == 0x01)
+ data->has_in |= BIT(10);
+ if (((reg >> 2) & 0x03) == 0x01)
+ data->has_in |= BIT(11);
+ if (((reg >> 4) & 0x03) == 0x01)
+ data->has_in |= BIT(12);
+ }
}
data->has_beep = !!sio_data->beep_pin;
static const struct dmi_system_id it87_dmi_table[] __initconst = {
{
.matches = {
- DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
+ DMI_MATCH(DMI_SYS_VENDOR,
+ "Gigabyte Technology Co., Ltd."),
DMI_MATCH(DMI_BOARD_NAME, "AB350"),
},
.driver_data = &gigabyte_sio2_force,
},
{
.matches = {
- DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
+ DMI_MATCH(DMI_SYS_VENDOR,
+ "Gigabyte Technology Co., Ltd."),
DMI_MATCH(DMI_BOARD_NAME, "AX370"),
},
.driver_data = &gigabyte_sio2_force,
},
{
.matches = {
- DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
+ DMI_MATCH(DMI_SYS_VENDOR,
+ "Gigabyte Technology Co., Ltd."),
DMI_MATCH(DMI_BOARD_NAME, "Z97X-Gaming G1"),
},
.driver_data = &gigabyte_sio2_force,
MODULE_PARM_DESC(fix_pwm_polarity,
"Force PWM polarity to active high (DANGEROUS)");
MODULE_LICENSE("GPL");
+MODULE_VERSION(IT87_DRIVER_VERSION);
module_init(sm_it87_init);
module_exit(sm_it87_exit);
projects / groeck-it87 / blobdiff