* similar parts. The other devices are supported by different drivers.
*
* Supports: IT8603E Super I/O chip w/LPC interface
+ * IT8607E Super I/O chip w/LPC interface
+ * IT8613E Super I/O chip w/LPC interface
* IT8620E Super I/O chip w/LPC interface
+ * IT8622E Super I/O chip w/LPC interface
* IT8623E Super I/O chip w/LPC interface
+ * IT8625E Super I/O chip w/LPC interface
* IT8628E Super I/O chip w/LPC interface
+ * IT8655E Super I/O chip w/LPC interface
+ * IT8665E Super I/O chip w/LPC interface
+ * IT8686E Super I/O chip w/LPC interface
* IT8705F Super I/O chip w/LPC interface
* IT8712F Super I/O chip w/LPC interface
* IT8716F Super I/O chip w/LPC interface
* IT8783E/F Super I/O chip w/LPC interface
* IT8786E Super I/O chip w/LPC interface
* IT8790E Super I/O chip w/LPC interface
+ * IT8792E Super I/O chip w/LPC interface
* Sis950 A clone of the IT8705F
*
* Copyright (C) 2001 Chris Gauthron
#define DRVNAME "it87"
+/* Necessary API not (yet) exported in upstream kernel */
+/* #define __IT87_USE_ACPI_MUTEX */
+
enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
- it8771, it8772, it8781, it8782, it8783, it8786, it8790, it8603,
- it8620, it8628 };
+ it8771, it8772, it8781, it8782, it8783, it8786, it8790,
+ it8792, it8603, it8607, it8613, it8620, it8622, it8625, it8628,
+ it8655, it8665, it8686 };
static unsigned short force_id;
module_param(force_id, ushort, 0);
MODULE_PARM_DESC(force_id, "Override the detected device ID");
+static unsigned short blacklist = 1;
+module_param(blacklist, ushort, 0);
+MODULE_PARM_DESC(blacklist,
+ "Enable/disable blacklist (1=enable, 0=disable, default 1)");
+
static struct platform_device *it87_pdev[2];
+static bool it87_sio4e_broken;
+#ifdef __IT87_USE_ACPI_MUTEX
+static acpi_handle it87_acpi_sio_handle;
+static char *it87_acpi_sio_mutex;
+#endif
#define REG_2E 0x2e /* The register to read/write */
#define REG_4E 0x4e /* Secondary register to read/write */
#define DEVID 0x20 /* Register: Device ID */
#define DEVREV 0x22 /* Register: Device Revision */
+static inline void __superio_enter(int ioreg)
+{
+ outb(0x87, ioreg);
+ outb(0x01, ioreg);
+ outb(0x55, ioreg);
+ outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
+}
+
static inline int superio_inb(int ioreg, int reg)
{
+ int val;
+
outb(reg, ioreg);
- return inb(ioreg + 1);
+ val = inb(ioreg + 1);
+ if (it87_sio4e_broken && ioreg == 0x4e && val == 0xff) {
+ __superio_enter(ioreg);
+ outb(reg, ioreg);
+ val = inb(ioreg + 1);
+ pr_warn("Retry access 0x4e:0x%x -> 0x%x\n", reg, val);
+ }
+
+ return val;
}
static inline void superio_outb(int ioreg, int reg, int val)
static int superio_inw(int ioreg, int reg)
{
- int val;
-
- outb(reg++, ioreg);
- val = inb(ioreg + 1) << 8;
- outb(reg, ioreg);
- val |= inb(ioreg + 1);
- return val;
+ return (superio_inb(ioreg, reg) << 8) | superio_inb(ioreg, reg + 1);
}
static inline void superio_select(int ioreg, int ldn)
static inline int superio_enter(int ioreg)
{
+#ifdef __IT87_USE_ACPI_MUTEX
+ if (it87_acpi_sio_mutex) {
+ acpi_status status;
+
+ status = acpi_acquire_mutex(NULL, it87_acpi_sio_mutex, 0x10);
+ if (ACPI_FAILURE(status)) {
+ pr_err("Failed to acquire ACPI mutex\n");
+ return -EBUSY;
+ }
+ }
+#endif
/*
* Try to reserve ioreg and ioreg + 1 for exclusive access.
*/
if (!request_muxed_region(ioreg, 2, DRVNAME))
- return -EBUSY;
+ goto error;
- outb(0x87, ioreg);
- outb(0x01, ioreg);
- outb(0x55, ioreg);
- outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
+ __superio_enter(ioreg);
return 0;
+
+error:
+#ifdef __IT87_USE_ACPI_MUTEX
+ if (it87_acpi_sio_mutex)
+ acpi_release_mutex(it87_acpi_sio_handle, NULL);
+#endif
+ return -EBUSY;
}
static inline void superio_exit(int ioreg)
{
- outb(0x02, ioreg);
- outb(0x02, ioreg + 1);
+ if (!it87_sio4e_broken || ioreg != 0x4e) {
+ outb(0x02, ioreg);
+ outb(0x02, ioreg + 1);
+ }
release_region(ioreg, 2);
+#ifdef __IT87_USE_ACPI_MUTEX
+ if (it87_acpi_sio_mutex)
+ acpi_release_mutex(it87_acpi_sio_handle, NULL);
+#endif
}
/* Logical device 4 registers */
#define IT8726F_DEVID 0x8726
#define IT8728F_DEVID 0x8728
#define IT8732F_DEVID 0x8732
+#define IT8792E_DEVID 0x8733
#define IT8771E_DEVID 0x8771
#define IT8772E_DEVID 0x8772
#define IT8781F_DEVID 0x8781
#define IT8786E_DEVID 0x8786
#define IT8790E_DEVID 0x8790
#define IT8603E_DEVID 0x8603
+#define IT8607E_DEVID 0x8607
+#define IT8613E_DEVID 0x8613
#define IT8620E_DEVID 0x8620
+#define IT8622E_DEVID 0x8622
#define IT8623E_DEVID 0x8623
+#define IT8625E_DEVID 0x8625
#define IT8628E_DEVID 0x8628
+#define IT8655E_DEVID 0x8655
+#define IT8665E_DEVID 0x8665
+#define IT8686E_DEVID 0x8686
#define IT87_ACT_REG 0x30
#define IT87_BASE_REG 0x60
#define IT87_SIO_GPIO3_REG 0x27
#define IT87_SIO_GPIO4_REG 0x28
#define IT87_SIO_GPIO5_REG 0x29
+#define IT87_SIO_GPIO9_REG 0xd3
#define IT87_SIO_PINX1_REG 0x2a /* Pin selection */
#define IT87_SIO_PINX2_REG 0x2c /* Pin selection */
+#define IT87_SIO_PINX4_REG 0x2d /* Pin selection */
#define IT87_SIO_SPI_REG 0xef /* SPI function pin select */
#define IT87_SIO_VID_REG 0xfc /* VID value */
#define IT87_SIO_BEEP_PIN_REG 0xf6 /* Beep pin mapping */
#define IT87_REG_ALARM2 0x02
#define IT87_REG_ALARM3 0x03
+#define IT87_REG_BANK 0x06
+
/*
* The IT8718F and IT8720F have the VID value in a different register, in
* Super-I/O configuration space.
* - up to 6 fan (1 to 6)
*/
-static const u8 IT87_REG_FAN[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
-static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
-static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
-static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
-static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59 };
+static const u8 IT87_REG_FAN[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
+static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
+static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
+static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
+
+static const u8 IT87_REG_FAN_8665[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x93 };
+static const u8 IT87_REG_FAN_MIN_8665[] =
+ { 0x10, 0x11, 0x12, 0x84, 0x86, 0xb2 };
+static const u8 IT87_REG_FANX_8665[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x94 };
+static const u8 IT87_REG_FANX_MIN_8665[] =
+ { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0xb3 };
+
+static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59, 0x5a, 0x90, 0x91 };
+
+static const u8 IT87_REG_TEMP_OFFSET_8686[] = { 0x56, 0x57, 0x59, 0x90, 0x91, 0x92 };
#define IT87_REG_FAN_MAIN_CTRL 0x13
#define IT87_REG_FAN_CTL 0x14
-static const u8 IT87_REG_PWM[] = { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
-static const u8 IT87_REG_PWM_DUTY[] = { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
+
+static const u8 IT87_REG_PWM[] = { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
+static const u8 IT87_REG_PWM_8665[] = { 0x15, 0x16, 0x17, 0x1e, 0x1f, 0x92 };
+
+static const u8 IT87_REG_PWM_DUTY[] = { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
static const u8 IT87_REG_VIN[] = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
#define IT87_REG_VIN_MAX(nr) (0x30 + (nr) * 2)
#define IT87_REG_VIN_MIN(nr) (0x31 + (nr) * 2)
-#define IT87_REG_TEMP_HIGH(nr) (0x40 + (nr) * 2)
-#define IT87_REG_TEMP_LOW(nr) (0x41 + (nr) * 2)
+
+static const u8 IT87_REG_TEMP_HIGH[] = { 0x40, 0x42, 0x44, 0x46, 0xb4, 0xb6 };
+static const u8 IT87_REG_TEMP_LOW[] = { 0x41, 0x43, 0x45, 0x47, 0xb5, 0xb7 };
+
+static const u8 IT87_REG_TEMP_HIGH_8686[] =
+ { 0x40, 0x42, 0x44, 0xb4, 0xb6, 0xb8 };
+static const u8 IT87_REG_TEMP_LOW_8686[] =
+ { 0x41, 0x43, 0x45, 0xb5, 0xb7, 0xb9 };
#define IT87_REG_VIN_ENABLE 0x50
#define IT87_REG_TEMP_ENABLE 0x51
#define IT87_REG_TEMP456_ENABLE 0x77
+static const u16 IT87_REG_TEMP_SRC1[] = { 0x21d, 0x21e, 0x21f };
+#define IT87_REG_TEMP_SRC2 0x23d
+
#define NUM_VIN ARRAY_SIZE(IT87_REG_VIN)
#define NUM_VIN_LIMIT 8
#define NUM_TEMP 6
-#define NUM_TEMP_OFFSET ARRAY_SIZE(IT87_REG_TEMP_OFFSET)
-#define NUM_TEMP_LIMIT 3
#define NUM_FAN ARRAY_SIZE(IT87_REG_FAN)
#define NUM_FAN_DIV 3
#define NUM_PWM ARRAY_SIZE(IT87_REG_PWM)
const char *name;
const char * const suffix;
u32 features;
+ u8 num_temp_limit;
+ u8 num_temp_offset;
u8 peci_mask;
u8 old_peci_mask;
};
#define FEAT_NEWER_AUTOPWM BIT(1)
#define FEAT_OLD_AUTOPWM BIT(2)
#define FEAT_16BIT_FANS BIT(3)
-#define FEAT_TEMP_OFFSET BIT(4)
#define FEAT_TEMP_PECI BIT(5)
#define FEAT_TEMP_OLD_PECI BIT(6)
#define FEAT_FAN16_CONFIG BIT(7) /* Need to enable 16-bit fans */
#define FEAT_SIX_FANS BIT(11) /* Supports six fans */
#define FEAT_10_9MV_ADC BIT(12)
#define FEAT_AVCC3 BIT(13) /* Chip supports in9/AVCC3 */
-#define FEAT_SIX_PWM BIT(14) /* Chip supports 6 pwm chn */
-#define FEAT_PWM_FREQ2 BIT(15) /* Separate pwm freq 2 */
-#define FEAT_SIX_TEMP BIT(16) /* Up to 6 temp sensors */
+#define FEAT_FIVE_PWM BIT(14) /* Chip supports 5 pwm chn */
+#define FEAT_SIX_PWM BIT(15) /* Chip supports 6 pwm chn */
+#define FEAT_PWM_FREQ2 BIT(16) /* Separate pwm freq 2 */
+#define FEAT_SIX_TEMP BIT(17) /* Up to 6 temp sensors */
+#define FEAT_VIN3_5V BIT(18) /* VIN3 connected to +5V */
+#define FEAT_FOUR_FANS BIT(19) /* Supports four fans */
+#define FEAT_FOUR_PWM BIT(20) /* Supports four fan controls */
+#define FEAT_BANK_SEL BIT(21) /* Chip has multi-bank support */
+#define FEAT_SCALING BIT(22) /* Internal voltage scaling */
+#define FEAT_FANCTL_ONOFF BIT(23) /* chip has FAN_CTL ON/OFF */
+#define FEAT_11MV_ADC BIT(24)
+#define FEAT_NEW_TEMPMAP BIT(25) /* new temp input selection */
static const struct it87_devices it87_devices[] = {
[it87] = {
.name = "it87",
.suffix = "F",
- .features = FEAT_OLD_AUTOPWM, /* may need to overwrite */
+ .features = FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF,
+ /* may need to overwrite */
+ .num_temp_limit = 3,
+ .num_temp_offset = 0,
},
[it8712] = {
.name = "it8712",
.suffix = "F",
- .features = FEAT_OLD_AUTOPWM | FEAT_VID,
+ .features = FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF,
/* may need to overwrite */
+ .num_temp_limit = 3,
+ .num_temp_offset = 0,
},
[it8716] = {
.name = "it8716",
.suffix = "F",
- .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
- | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2,
+ .features = FEAT_16BIT_FANS | FEAT_VID
+ | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2
+ | FEAT_FANCTL_ONOFF,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
},
[it8718] = {
.name = "it8718",
.suffix = "F",
- .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
+ .features = FEAT_16BIT_FANS | FEAT_VID
| FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
- | FEAT_PWM_FREQ2,
+ | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
.old_peci_mask = 0x4,
},
[it8720] = {
.name = "it8720",
.suffix = "F",
- .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID
+ .features = FEAT_16BIT_FANS | FEAT_VID
| FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
- | FEAT_PWM_FREQ2,
+ | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
.old_peci_mask = 0x4,
},
[it8721] = {
.name = "it8721",
.suffix = "F",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
+ | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
| FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
- | FEAT_PWM_FREQ2,
+ | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
.peci_mask = 0x05,
.old_peci_mask = 0x02, /* Actually reports PCH */
},
.name = "it8728",
.suffix = "F",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS
- | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2,
+ | FEAT_TEMP_PECI | FEAT_FIVE_FANS
+ | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_SCALING
+ | FEAT_FANCTL_ONOFF,
+ .num_temp_limit = 6,
+ .num_temp_offset = 3,
.peci_mask = 0x07,
},
[it8732] = {
.name = "it8732",
.suffix = "F",
.features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
- | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL,
+ | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
+ | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS
+ | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
.peci_mask = 0x07,
.old_peci_mask = 0x02, /* Actually reports PCH */
},
.name = "it8771",
.suffix = "E",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
- | FEAT_PWM_FREQ2,
+ | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
+ | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
/* PECI: guesswork */
/* 12mV ADC (OHM) */
/* 16 bit fans (OHM) */
/* three fans, always 16 bit (guesswork) */
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
.peci_mask = 0x07,
},
[it8772] = {
.name = "it8772",
.suffix = "E",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
- | FEAT_PWM_FREQ2,
+ | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
+ | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
/* PECI (coreboot) */
/* 12mV ADC (HWSensors4, OHM) */
/* 16 bit fans (HWSensors4, OHM) */
/* three fans, always 16 bit (datasheet) */
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
.peci_mask = 0x07,
},
[it8781] = {
.name = "it8781",
.suffix = "F",
- .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
- | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
+ .features = FEAT_16BIT_FANS
+ | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
+ | FEAT_FANCTL_ONOFF,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
.old_peci_mask = 0x4,
},
[it8782] = {
.name = "it8782",
.suffix = "F",
- .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
- | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
+ .features = FEAT_16BIT_FANS
+ | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
+ | FEAT_FANCTL_ONOFF,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
.old_peci_mask = 0x4,
},
[it8783] = {
.name = "it8783",
.suffix = "E/F",
- .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET
- | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2,
+ .features = FEAT_16BIT_FANS
+ | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
+ | FEAT_FANCTL_ONOFF,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
.old_peci_mask = 0x4,
},
[it8786] = {
.name = "it8786",
.suffix = "E",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
- | FEAT_PWM_FREQ2,
+ | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
+ | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
.peci_mask = 0x07,
},
[it8790] = {
.name = "it8790",
.suffix = "E",
- .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
- | FEAT_PWM_FREQ2,
+ .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
+ | FEAT_16BIT_FANS | FEAT_TEMP_PECI
+ | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .peci_mask = 0x07,
+ },
+ [it8792] = {
+ .name = "it8792",
+ .suffix = "E",
+ .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
+ | FEAT_16BIT_FANS | FEAT_TEMP_PECI
+ | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
.peci_mask = 0x07,
},
[it8603] = {
.name = "it8603",
.suffix = "E",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
- | FEAT_AVCC3 | FEAT_PWM_FREQ2,
+ | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
+ | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .peci_mask = 0x07,
+ },
+ [it8607] = {
+ .name = "it8607",
+ .suffix = "E",
+ .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
+ | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
+ | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING
+ | FEAT_FANCTL_ONOFF,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .peci_mask = 0x07,
+ },
+ [it8613] = {
+ .name = "it8613",
+ .suffix = "E",
+ .features = FEAT_NEWER_AUTOPWM | FEAT_11MV_ADC | FEAT_16BIT_FANS
+ | FEAT_TEMP_PECI | FEAT_FIVE_FANS
+ | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
+ | FEAT_AVCC3 | FEAT_SCALING | FEAT_NEW_TEMPMAP,
+ .num_temp_limit = 6,
+ .num_temp_offset = 6,
.peci_mask = 0x07,
},
[it8620] = {
.name = "it8620",
.suffix = "E",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
+ | FEAT_TEMP_PECI | FEAT_SIX_FANS
| FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
- | FEAT_SIX_TEMP,
+ | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_SCALING
+ | FEAT_FANCTL_ONOFF,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
+ .peci_mask = 0x07,
+ },
+ [it8622] = {
+ .name = "it8622",
+ .suffix = "E",
+ .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
+ | FEAT_TEMP_PECI | FEAT_FIVE_FANS
+ | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
+ | FEAT_AVCC3 | FEAT_VIN3_5V | FEAT_SCALING,
+ .num_temp_limit = 3,
+ .num_temp_offset = 3,
.peci_mask = 0x07,
},
+ [it8625] = {
+ .name = "it8625",
+ .suffix = "E",
+ .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
+ | FEAT_AVCC3 | FEAT_NEW_TEMPMAP
+ | FEAT_11MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
+ | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_SCALING,
+ .num_temp_limit = 6,
+ .num_temp_offset = 6,
+ },
[it8628] = {
.name = "it8628",
.suffix = "E",
.features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
- | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS
+ | FEAT_TEMP_PECI | FEAT_SIX_FANS
| FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
- | FEAT_SIX_TEMP,
+ | FEAT_SIX_TEMP | FEAT_SCALING | FEAT_AVCC3
+ | FEAT_FANCTL_ONOFF,
+ .num_temp_limit = 6,
+ .num_temp_offset = 3,
.peci_mask = 0x07,
},
+ [it8655] = {
+ .name = "it8655",
+ .suffix = "E",
+ .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
+ | FEAT_AVCC3 | FEAT_NEW_TEMPMAP
+ | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_BANK_SEL,
+ .num_temp_limit = 6,
+ .num_temp_offset = 6,
+ },
+ [it8665] = {
+ .name = "it8665",
+ .suffix = "E",
+ .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
+ | FEAT_AVCC3 | FEAT_NEW_TEMPMAP
+ | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
+ | FEAT_SIX_PWM | FEAT_BANK_SEL,
+ .num_temp_limit = 6,
+ .num_temp_offset = 6,
+ },
+ [it8686] = {
+ .name = "it8686",
+ .suffix = "E",
+ .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
+ | FEAT_SIX_FANS | FEAT_NEW_TEMPMAP
+ | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
+ | FEAT_SIX_TEMP | FEAT_BANK_SEL | FEAT_SCALING | FEAT_AVCC3,
+ .num_temp_limit = 6,
+ .num_temp_offset = 6,
+ },
};
#define has_16bit_fans(data) ((data)->features & FEAT_16BIT_FANS)
#define has_10_9mv_adc(data) ((data)->features & FEAT_10_9MV_ADC)
#define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
#define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM)
-#define has_temp_offset(data) ((data)->features & FEAT_TEMP_OFFSET)
#define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
((data)->peci_mask & BIT(nr)))
#define has_temp_old_peci(data, nr) \
#define has_in7_internal(data) ((data)->features & FEAT_IN7_INTERNAL)
#define has_six_fans(data) ((data)->features & FEAT_SIX_FANS)
#define has_avcc3(data) ((data)->features & FEAT_AVCC3)
+#define has_five_pwm(data) ((data)->features & (FEAT_FIVE_PWM \
+ | FEAT_SIX_PWM))
#define has_six_pwm(data) ((data)->features & FEAT_SIX_PWM)
#define has_pwm_freq2(data) ((data)->features & FEAT_PWM_FREQ2)
#define has_six_temp(data) ((data)->features & FEAT_SIX_TEMP)
+#define has_vin3_5v(data) ((data)->features & FEAT_VIN3_5V)
+#define has_four_fans(data) ((data)->features & (FEAT_FOUR_FANS | \
+ FEAT_FIVE_FANS | \
+ FEAT_SIX_FANS))
+#define has_four_pwm(data) ((data)->features & (FEAT_FOUR_PWM | \
+ FEAT_FIVE_PWM \
+ | FEAT_SIX_PWM))
+#define has_bank_sel(data) ((data)->features & FEAT_BANK_SEL)
+#define has_scaling(data) ((data)->features & FEAT_SCALING)
+#define has_fanctl_onoff(data) ((data)->features & FEAT_FANCTL_ONOFF)
+#define has_11mv_adc(data) ((data)->features & FEAT_11MV_ADC)
+#define has_new_tempmap(data) ((data)->features & FEAT_NEW_TEMPMAP)
struct it87_sio_data {
enum chips type;
struct it87_data {
const struct attribute_group *groups[7];
enum chips type;
- u16 features;
+ u32 features;
+ u8 bank;
u8 peci_mask;
u8 old_peci_mask;
+ const u8 *REG_FAN;
+ const u8 *REG_FANX;
+ const u8 *REG_FAN_MIN;
+ const u8 *REG_FANX_MIN;
+
+ const u8 *REG_PWM;
+
+ const u8 *REG_TEMP_OFFSET;
+ const u8 *REG_TEMP_LOW;
+ const u8 *REG_TEMP_HIGH;
+
unsigned short addr;
const char *name;
struct mutex update_lock;
u16 fan[NUM_FAN][2]; /* Register values, [nr][0]=fan, [1]=min */
u8 has_temp; /* Bitfield, temp sensors enabled */
s8 temp[NUM_TEMP][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
+ u8 num_temp_limit; /* Number of temperature limit registers */
+ u8 num_temp_offset; /* Number of temperature offset registers */
u8 sensor; /* Register value (IT87_REG_TEMP_ENABLE) */
u8 extra; /* Register value (IT87_REG_TEMP_EXTRA) */
u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
lsb = 120;
else if (has_10_9mv_adc(data))
lsb = 109;
+ else if (has_11mv_adc(data))
+ lsb = 110;
else
lsb = 160;
if (data->in_scaled & BIT(nr))
750000,
};
+static int _it87_read_value(struct it87_data *data, u8 reg)
+{
+ outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
+ return inb_p(data->addr + IT87_DATA_REG_OFFSET);
+}
+
+static void _it87_write_value(struct it87_data *data, u8 reg, u8 value)
+{
+ outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
+ outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
+}
+
+static void it87_set_bank(struct it87_data *data, u8 bank)
+{
+ if (has_bank_sel(data) && bank != data->bank) {
+ u8 breg = _it87_read_value(data, IT87_REG_BANK);
+
+ breg &= 0x1f;
+ breg |= (bank << 5);
+ data->bank = bank;
+ _it87_write_value(data, IT87_REG_BANK, breg);
+ }
+}
+
/*
* Must be called with data->update_lock held, except during initialization.
* We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
* would slow down the IT87 access and should not be necessary.
*/
-static int it87_read_value(struct it87_data *data, u8 reg)
+static int it87_read_value(struct it87_data *data, u16 reg)
{
- outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
- return inb_p(data->addr + IT87_DATA_REG_OFFSET);
+ it87_set_bank(data, reg >> 8);
+ return _it87_read_value(data, reg & 0xff);
}
/*
* We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
* would slow down the IT87 access and should not be necessary.
*/
-static void it87_write_value(struct it87_data *data, u8 reg, u8 value)
+static void it87_write_value(struct it87_data *data, u16 reg, u8 value)
{
- outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
- outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
+ it87_set_bank(data, reg >> 8);
+ _it87_write_value(data, reg & 0xff, value);
}
static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
{
- data->pwm_ctrl[nr] = it87_read_value(data, IT87_REG_PWM[nr]);
+ data->pwm_ctrl[nr] = it87_read_value(data, data->REG_PWM[nr]);
if (has_newer_autopwm(data)) {
- data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
+ if (has_new_tempmap(data))
+ data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x38;
+ else
+ data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
data->pwm_duty[nr] = it87_read_value(data,
IT87_REG_PWM_DUTY[nr]);
} else {
continue;
data->fan[i][1] =
- it87_read_value(data, IT87_REG_FAN_MIN[i]);
+ it87_read_value(data, data->REG_FAN_MIN[i]);
data->fan[i][0] = it87_read_value(data,
- IT87_REG_FAN[i]);
+ data->REG_FAN[i]);
/* Add high byte if in 16-bit mode */
if (has_16bit_fans(data)) {
data->fan[i][0] |= it87_read_value(data,
- IT87_REG_FANX[i]) << 8;
+ data->REG_FANX[i]) << 8;
data->fan[i][1] |= it87_read_value(data,
- IT87_REG_FANX_MIN[i]) << 8;
+ data->REG_FANX_MIN[i]) << 8;
}
}
for (i = 0; i < NUM_TEMP; i++) {
data->temp[i][0] =
it87_read_value(data, IT87_REG_TEMP(i));
- if (has_temp_offset(data) && i < NUM_TEMP_OFFSET)
+ if (i >= data->num_temp_limit)
+ continue;
+
+ if (i < data->num_temp_offset)
data->temp[i][3] =
it87_read_value(data,
- IT87_REG_TEMP_OFFSET[i]);
-
- if (i >= NUM_TEMP_LIMIT)
- continue;
+ data->REG_TEMP_OFFSET[i]);
data->temp[i][1] =
- it87_read_value(data, IT87_REG_TEMP_LOW(i));
+ it87_read_value(data, data->REG_TEMP_LOW[i]);
data->temp[i][2] =
- it87_read_value(data, IT87_REG_TEMP_HIGH(i));
+ it87_read_value(data, data->REG_TEMP_HIGH[i]);
}
/* Newer chips don't have clock dividers */
switch (index) {
default:
case 1:
- reg = IT87_REG_TEMP_LOW(nr);
+ reg = data->REG_TEMP_LOW[nr];
break;
case 2:
- reg = IT87_REG_TEMP_HIGH(nr);
+ reg = data->REG_TEMP_HIGH[nr];
break;
case 3:
regval = it87_read_value(data, IT87_REG_BEEP_ENABLE);
it87_write_value(data, IT87_REG_BEEP_ENABLE, regval);
}
data->valid = 0;
- reg = IT87_REG_TEMP_OFFSET[nr];
+ reg = data->REG_TEMP_OFFSET[nr];
break;
}
static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
set_temp, 2, 3);
static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0);
+static SENSOR_DEVICE_ATTR_2(temp4_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
+ 3, 1);
+static SENSOR_DEVICE_ATTR_2(temp4_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
+ 3, 2);
+static SENSOR_DEVICE_ATTR_2(temp4_offset, S_IRUGO | S_IWUSR, show_temp,
+ set_temp, 3, 3);
static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0);
+static SENSOR_DEVICE_ATTR_2(temp5_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
+ 4, 1);
+static SENSOR_DEVICE_ATTR_2(temp5_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
+ 4, 2);
+static SENSOR_DEVICE_ATTR_2(temp5_offset, S_IRUGO | S_IWUSR, show_temp,
+ set_temp, 4, 3);
static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0);
+static SENSOR_DEVICE_ATTR_2(temp6_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
+ 5, 1);
+static SENSOR_DEVICE_ATTR_2(temp6_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
+ 5, 2);
+static SENSOR_DEVICE_ATTR_2(temp6_offset, S_IRUGO | S_IWUSR, show_temp,
+ set_temp, 5, 3);
+
+static int get_temp_type(struct it87_data *data, int index)
+{
+ u8 reg, extra;
+ int type = 0;
+
+ if (has_bank_sel(data)) {
+ int s1reg = IT87_REG_TEMP_SRC1[index/2] >> ((index % 2) * 4);
+ u8 src1, src2;
+
+ src1 = (it87_read_value(data, s1reg) >> ((index % 2) * 4)) & 0x0f;
+ src2 = it87_read_value(data, IT87_REG_TEMP_SRC2);
+
+ switch (data->type) {
+ case it8686:
+ switch (src1) {
+ case 0:
+ if (index >= 3)
+ return 4;
+ break;
+ case 1:
+ if (index == 1 || index == 2 ||
+ index == 4 || index == 5)
+ return 6;
+ break;
+ case 2:
+ if (index == 2 || index == 6)
+ return 5;
+ break;
+ default:
+ break;
+ }
+ break;
+ case it8625:
+ if (index < 3)
+ break;
+ case it8655:
+ case it8665:
+ if (src1 < 3) {
+ index = src1;
+ break;
+ }
+ switch(src1) {
+ case 3:
+ type = (src2 & BIT(index)) ? 6 : 5;
+ break;
+ case 4 ... 8:
+ type = (src2 & BIT(index)) ? 4 : 6;
+ break;
+ case 9:
+ type = (src2 & BIT(index)) ? 5 : 0;
+ break;
+ default:
+ break;
+ }
+ return type;
+ default:
+ return 0;
+ }
+ }
+ if (index >= 3)
+ return 0;
+
+ reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
+ extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
+
+ if ((has_temp_peci(data, index) && (reg >> 6 == index + 1)) ||
+ (has_temp_old_peci(data, index) && (extra & 0x80)))
+ type = 6; /* Intel PECI */
+ if (reg & BIT(index))
+ type = 3; /* thermal diode */
+ else if (reg & BIT(index + 3))
+ type = 4; /* thermistor */
+
+ return type;
+}
static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
- int nr = sensor_attr->index;
struct it87_data *data = it87_update_device(dev);
- u8 reg = data->sensor; /* In case value is updated while used */
- u8 extra = data->extra;
+ int type = get_temp_type(data, sensor_attr->index);
- if ((has_temp_peci(data, nr) && (reg >> 6 == nr + 1)) ||
- (has_temp_old_peci(data, nr) && (extra & 0x80)))
- return sprintf(buf, "6\n"); /* Intel PECI */
- if (reg & (1 << nr))
- return sprintf(buf, "3\n"); /* thermal diode */
- if (reg & (8 << nr))
- return sprintf(buf, "4\n"); /* thermistor */
- return sprintf(buf, "0\n"); /* disabled */
+ return sprintf(buf, "%d\n", type);
}
static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
set_temp_type, 1);
static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
set_temp_type, 2);
+static SENSOR_DEVICE_ATTR(temp4_type, S_IRUGO | S_IWUSR, show_temp_type,
+ set_temp_type, 3);
+static SENSOR_DEVICE_ATTR(temp5_type, S_IRUGO | S_IWUSR, show_temp_type,
+ set_temp_type, 4);
+static SENSOR_DEVICE_ATTR(temp6_type, S_IRUGO | S_IWUSR, show_temp_type,
+ set_temp_type, 5);
/* 6 Fans */
static int pwm_mode(const struct it87_data *data, int nr)
{
- if (data->type != it8603 && nr < 3 && !(data->fan_main_ctrl & BIT(nr)))
+ if (has_fanctl_onoff(data) && nr < 3 &&
+ !(data->fan_main_ctrl & BIT(nr)))
return 0; /* Full speed */
- if (data->pwm_ctrl[nr] & 0x80) {
+ if (data->pwm_ctrl[nr] & 0x80)
return 2; /* Automatic mode */
- } else {
- if ((data->type == it8603 || nr >= 3) &&
- data->pwm_duty[nr] == pwm_to_reg(data, 0xff))
- return 0; /* Full speed */
- return 1; /* Manual mode */
- }
+ if ((!has_fanctl_onoff(data) || nr >= 3) &&
+ data->pwm_duty[nr] == pwm_to_reg(data, 0xff))
+ return 0; /* Full speed */
+
+ return 1; /* Manual mode */
}
static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
if (has_16bit_fans(data)) {
data->fan[nr][index] = FAN16_TO_REG(val);
- it87_write_value(data, IT87_REG_FAN_MIN[nr],
+ it87_write_value(data, data->REG_FAN_MIN[nr],
data->fan[nr][index] & 0xff);
- it87_write_value(data, IT87_REG_FANX_MIN[nr],
+ it87_write_value(data, data->REG_FANX_MIN[nr],
data->fan[nr][index] >> 8);
} else {
reg = it87_read_value(data, IT87_REG_FAN_DIV);
}
data->fan[nr][index] =
FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
- it87_write_value(data, IT87_REG_FAN_MIN[nr],
+ it87_write_value(data, data->REG_FAN_MIN[nr],
data->fan[nr][index]);
}
/* Restore fan min limit */
data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
- it87_write_value(data, IT87_REG_FAN_MIN[nr], data->fan[nr][1]);
+ it87_write_value(data, data->REG_FAN_MIN[nr], data->fan[nr][1]);
mutex_unlock(&data->update_lock);
return count;
mutex_lock(&data->update_lock);
if (val == 0) {
- if (nr < 3 && data->type != it8603) {
+ if (nr < 3 && has_fanctl_onoff(data)) {
int tmp;
/* make sure the fan is on when in on/off mode */
tmp = it87_read_value(data, IT87_REG_FAN_CTL);
it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
data->fan_main_ctrl);
} else {
+ u8 ctrl;
+
/* No on/off mode, set maximum pwm value */
data->pwm_duty[nr] = pwm_to_reg(data, 0xff);
it87_write_value(data, IT87_REG_PWM_DUTY[nr],
data->pwm_duty[nr]);
/* and set manual mode */
- data->pwm_ctrl[nr] = has_newer_autopwm(data) ?
- data->pwm_temp_map[nr] :
- data->pwm_duty[nr];
- it87_write_value(data, IT87_REG_PWM[nr],
- data->pwm_ctrl[nr]);
+ if (has_newer_autopwm(data)) {
+ ctrl = (data->pwm_ctrl[nr] & 0x7c) |
+ data->pwm_temp_map[nr];
+ } else {
+ ctrl = data->pwm_duty[nr];
+ }
+ data->pwm_ctrl[nr] = ctrl;
+ it87_write_value(data, data->REG_PWM[nr], ctrl);
}
} else {
- if (val == 1) /* Manual mode */
- data->pwm_ctrl[nr] = has_newer_autopwm(data) ?
- data->pwm_temp_map[nr] :
- data->pwm_duty[nr];
- else /* Automatic mode */
- data->pwm_ctrl[nr] = 0x80 | data->pwm_temp_map[nr];
- it87_write_value(data, IT87_REG_PWM[nr], data->pwm_ctrl[nr]);
-
- if (data->type != it8603 && nr < 3) {
+ u8 ctrl;
+
+ if (has_newer_autopwm(data)) {
+ ctrl = (data->pwm_ctrl[nr] & 0x7c) |
+ data->pwm_temp_map[nr];
+ if (val != 1)
+ ctrl |= 0x80;
+ } else {
+ ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80);
+ }
+ data->pwm_ctrl[nr] = ctrl;
+ it87_write_value(data, data->REG_PWM[nr], ctrl);
+
+ if (has_fanctl_onoff(data) && nr < 3) {
/* set SmartGuardian mode */
data->fan_main_ctrl |= BIT(nr);
it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
return -EINVAL;
mutex_lock(&data->update_lock);
+ it87_update_pwm_ctrl(data, nr);
if (has_newer_autopwm(data)) {
/*
* If we are in automatic mode, the PWM duty cycle register
*/
if (!(data->pwm_ctrl[nr] & 0x80)) {
data->pwm_ctrl[nr] = data->pwm_duty[nr];
- it87_write_value(data, IT87_REG_PWM[nr],
+ it87_write_value(data, data->REG_PWM[nr],
data->pwm_ctrl[nr]);
}
}
int map;
map = data->pwm_temp_map[nr];
- if (map >= 3)
- map = 0; /* Should never happen */
- if (nr >= 3) /* pwm channels 3..6 map to temp4..6 */
- map += 3;
+ if (has_new_tempmap(data)) {
+ map >>= 3;
+ if (map >= 6)
+ map = 0; /* Should never happen */
+ } else {
+ if (map >= 3)
+ map = 0; /* Should never happen */
+ if (nr >= 3) /* pwm channels 3..6 map to temp4..6 */
+ map += 3;
+ }
return sprintf(buf, "%d\n", (int)BIT(map));
}
if (kstrtol(buf, 10, &val) < 0)
return -EINVAL;
- if (nr >= 3)
+ if (nr >= 3 && !has_new_tempmap(data))
val -= 3;
switch (val) {
case BIT(2):
reg = 0x02;
break;
+ case BIT(3):
+ reg = 0x03;
+ break;
+ case BIT(4):
+ reg = 0x04;
+ break;
+ case BIT(5):
+ reg = 0x05;
+ break;
+ case BIT(6):
+ reg = 0x06;
+ break;
default:
return -EINVAL;
}
+ if (has_new_tempmap(data))
+ reg <<= 3;
+ else if (reg > 0x02)
+ return -EINVAL;
+
mutex_lock(&data->update_lock);
+ it87_update_pwm_ctrl(data, nr);
data->pwm_temp_map[nr] = reg;
/*
* If we are in automatic mode, write the temp mapping immediately;
* otherwise, just store it for later use.
*/
if (data->pwm_ctrl[nr] & 0x80) {
- data->pwm_ctrl[nr] = 0x80 | data->pwm_temp_map[nr];
- it87_write_value(data, IT87_REG_PWM[nr], data->pwm_ctrl[nr]);
+ u8 mask = has_new_tempmap(data) ? 0xc7 : 0xfc;
+
+ data->pwm_ctrl[nr] = (data->pwm_ctrl[nr] & mask) |
+ data->pwm_temp_map[nr];
+ it87_write_value(data, data->REG_PWM[nr], data->pwm_ctrl[nr]);
}
mutex_unlock(&data->update_lock);
return count;
static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
+static SENSOR_DEVICE_ATTR(temp4_alarm, S_IRUGO, show_alarm, NULL, 19);
+static SENSOR_DEVICE_ATTR(temp5_alarm, S_IRUGO, show_alarm, NULL, 20);
+static SENSOR_DEVICE_ATTR(temp6_alarm, S_IRUGO, show_alarm, NULL, 21);
static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
show_alarm, clear_intrusion, 4);
show_beep, set_beep, 2);
static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
+static SENSOR_DEVICE_ATTR(temp4_beep, S_IRUGO, show_beep, NULL, 2);
+static SENSOR_DEVICE_ATTR(temp5_beep, S_IRUGO, show_beep, NULL, 2);
+static SENSOR_DEVICE_ATTR(temp6_beep, S_IRUGO, show_beep, NULL, 2);
static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
char *buf)
"+5V",
"5VSB",
"Vbat",
+ "AVCC",
};
static const char * const labels_it8721[] = {
"+3.3V",
"3VSB",
"Vbat",
+ "+3.3V",
};
struct it87_data *data = dev_get_drvdata(dev);
int nr = to_sensor_dev_attr(attr)->index;
const char *label;
- if (has_12mv_adc(data) || has_10_9mv_adc(data))
+ if (has_vin3_5v(data) && nr == 0)
+ label = labels[0];
+ else if (has_12mv_adc(data) || has_10_9mv_adc(data) ||
+ has_11mv_adc(data))
label = labels_it8721[nr];
else
label = labels[nr];
static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
/* AVCC3 */
-static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 0);
+static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 3);
static umode_t it87_in_is_visible(struct kobject *kobj,
struct attribute *attr, int index)
&sensor_dev_attr_in8_input.dev_attr.attr, /* 40 */
&sensor_dev_attr_in9_input.dev_attr.attr, /* 41 */
- &sensor_dev_attr_in10_input.dev_attr.attr, /* 41 */
- &sensor_dev_attr_in11_input.dev_attr.attr, /* 41 */
- &sensor_dev_attr_in12_input.dev_attr.attr, /* 41 */
+ &sensor_dev_attr_in10_input.dev_attr.attr, /* 42 */
+ &sensor_dev_attr_in11_input.dev_attr.attr, /* 43 */
+ &sensor_dev_attr_in12_input.dev_attr.attr, /* 44 */
+ NULL
};
static const struct attribute_group it87_group_in = {
int i = index / 7; /* temperature index */
int a = index % 7; /* attribute index */
- if (index >= 21) {
- i = index - 21 + 3;
- a = 0;
- }
-
if (!(data->has_temp & BIT(i)))
return 0;
- if (a == 5 && !has_temp_offset(data))
+ if (a && i >= data->num_temp_limit)
+ return 0;
+
+ if (a == 3) {
+ int type = get_temp_type(data, i);
+
+ if (type == 0)
+ return 0;
+ if (has_bank_sel(data))
+ return 0444;
+ return attr->mode;
+ }
+
+ if (a == 5 && i >= data->num_temp_offset)
return 0;
if (a == 6 && !data->has_beep)
&sensor_dev_attr_temp1_input.dev_attr.attr,
&sensor_dev_attr_temp1_max.dev_attr.attr,
&sensor_dev_attr_temp1_min.dev_attr.attr,
- &sensor_dev_attr_temp1_type.dev_attr.attr,
+ &sensor_dev_attr_temp1_type.dev_attr.attr, /* 3 */
&sensor_dev_attr_temp1_alarm.dev_attr.attr,
&sensor_dev_attr_temp1_offset.dev_attr.attr, /* 5 */
&sensor_dev_attr_temp1_beep.dev_attr.attr, /* 6 */
&sensor_dev_attr_temp3_beep.dev_attr.attr,
&sensor_dev_attr_temp4_input.dev_attr.attr, /* 21 */
+ &sensor_dev_attr_temp4_max.dev_attr.attr,
+ &sensor_dev_attr_temp4_min.dev_attr.attr,
+ &sensor_dev_attr_temp4_type.dev_attr.attr,
+ &sensor_dev_attr_temp4_alarm.dev_attr.attr,
+ &sensor_dev_attr_temp4_offset.dev_attr.attr,
+ &sensor_dev_attr_temp4_beep.dev_attr.attr,
+
&sensor_dev_attr_temp5_input.dev_attr.attr,
+ &sensor_dev_attr_temp5_max.dev_attr.attr,
+ &sensor_dev_attr_temp5_min.dev_attr.attr,
+ &sensor_dev_attr_temp5_type.dev_attr.attr,
+ &sensor_dev_attr_temp5_alarm.dev_attr.attr,
+ &sensor_dev_attr_temp5_offset.dev_attr.attr,
+ &sensor_dev_attr_temp5_beep.dev_attr.attr,
+
&sensor_dev_attr_temp6_input.dev_attr.attr,
+ &sensor_dev_attr_temp6_max.dev_attr.attr,
+ &sensor_dev_attr_temp6_min.dev_attr.attr,
+ &sensor_dev_attr_temp6_type.dev_attr.attr,
+ &sensor_dev_attr_temp6_alarm.dev_attr.attr,
+ &sensor_dev_attr_temp6_offset.dev_attr.attr,
+ &sensor_dev_attr_temp6_beep.dev_attr.attr,
NULL
};
return 0;
}
if (has_old_autopwm(data)) {
- if (a >= 9) /* no pwm_auto_start, pwm_auto_slope */
+ if (a >= 9) /* no pwm_auto_start, pwm_auto_slope */
return 0;
}
{
int err;
u16 chip_type;
- const char *board_vendor, *board_name;
const struct it87_devices *config;
err = superio_enter(sioaddr);
return err;
err = -ENODEV;
- chip_type = force_id ? force_id : superio_inw(sioaddr, DEVID);
+ chip_type = superio_inw(sioaddr, DEVID);
+ if (chip_type == 0xffff)
+ goto exit;
+
+ if (force_id)
+ chip_type = force_id;
switch (chip_type) {
case IT8705F_DEVID:
case IT8732F_DEVID:
sio_data->type = it8732;
break;
+ case IT8792E_DEVID:
+ sio_data->type = it8792;
+ break;
case IT8771E_DEVID:
sio_data->type = it8771;
break;
case IT8623E_DEVID:
sio_data->type = it8603;
break;
+ case IT8607E_DEVID:
+ sio_data->type = it8607;
+ break;
+ case IT8613E_DEVID:
+ sio_data->type = it8613;
+ break;
case IT8620E_DEVID:
sio_data->type = it8620;
break;
+ case IT8622E_DEVID:
+ sio_data->type = it8622;
+ break;
+ case IT8625E_DEVID:
+ sio_data->type = it8625;
+ break;
case IT8628E_DEVID:
sio_data->type = it8628;
break;
+ case IT8655E_DEVID:
+ sio_data->type = it8655;
+ break;
+ case IT8665E_DEVID:
+ sio_data->type = it8665;
+ break;
+ case IT8686E_DEVID:
+ sio_data->type = it8686;
+ break;
case 0xffff: /* No device at all */
goto exit;
default:
else
sio_data->skip_in |= BIT(9);
- if (!has_six_pwm(config))
+ if (!has_four_pwm(config))
sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5);
+ else if (!has_five_pwm(config))
+ sio_data->skip_pwm |= BIT(4) | BIT(5);
+ else if (!has_six_pwm(config))
+ sio_data->skip_pwm |= BIT(5);
if (!has_vid(config))
sio_data->skip_vid = 1;
sio_data->beep_pin = superio_inb(sioaddr,
IT87_SIO_BEEP_PIN_REG) & 0x3f;
- } else if (sio_data->type == it8603) {
+ } else if (sio_data->type == it8603 || sio_data->type == it8607) {
int reg27, reg29;
superio_select(sioaddr, GPIO);
if (reg29 & BIT(2))
sio_data->skip_fan |= BIT(1);
- sio_data->skip_in |= BIT(5); /* No VIN5 */
- sio_data->skip_in |= BIT(6); /* No VIN6 */
+ switch (sio_data->type) {
+ case it8603:
+ sio_data->skip_in |= BIT(5); /* No VIN5 */
+ sio_data->skip_in |= BIT(6); /* No VIN6 */
+ break;
+ case it8607:
+ sio_data->skip_pwm |= BIT(0);/* No fan1 */
+ sio_data->skip_fan |= BIT(0);
+ default:
+ break;
+ }
sio_data->beep_pin = superio_inb(sioaddr,
IT87_SIO_BEEP_PIN_REG) & 0x3f;
- } else if (sio_data->type == it8620 || sio_data->type == it8628) {
+ } else if (sio_data->type == it8613) {
+ int reg27, reg29, reg2a;
+
+ superio_select(sioaddr, GPIO);
+
+ /* Check for pwm3, fan3, pwm5, fan5 */
+ reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
+ if (reg27 & BIT(1))
+ sio_data->skip_fan |= BIT(4);
+ if (reg27 & BIT(3))
+ sio_data->skip_pwm |= BIT(4);
+ if (reg27 & BIT(6))
+ sio_data->skip_pwm |= BIT(2);
+ if (reg27 & BIT(7))
+ sio_data->skip_fan |= BIT(2);
+
+ /* Check for pwm2, fan2 */
+ reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
+ if (reg29 & BIT(1))
+ sio_data->skip_pwm |= BIT(1);
+ if (reg29 & BIT(2))
+ sio_data->skip_fan |= BIT(1);
+
+ /* Check for pwm4, fan4 */
+ reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
+ if (!(reg2a & BIT(0)) || (reg29 & BIT(7))) {
+ sio_data->skip_fan |= BIT(3);
+ sio_data->skip_pwm |= BIT(3);
+ }
+
+ sio_data->skip_pwm |= BIT(0); /* No pwm1 */
+ sio_data->skip_fan |= BIT(0); /* No fan1 */
+ sio_data->skip_in |= BIT(3); /* No VIN3 */
+ sio_data->skip_in |= BIT(6); /* No VIN6 */
+
+ sio_data->beep_pin = superio_inb(sioaddr,
+ IT87_SIO_BEEP_PIN_REG) & 0x3f;
+ } else if (sio_data->type == it8620 || sio_data->type == it8628 ||
+ sio_data->type == it8686) {
int reg;
superio_select(sioaddr, GPIO);
/* Check for pwm4 */
reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG);
- if (!(reg & BIT(2)))
+ if (reg & BIT(2))
sio_data->skip_pwm |= BIT(3);
/* Check for pwm2, fan2 */
sio_data->skip_fan |= BIT(5);
}
+ /* Check if AVCC is on VIN3 */
+ reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
+ if (reg & BIT(0)) {
+ /* For it8686, the bit just enables AVCC3 */
+ if (sio_data->type != it8686)
+ sio_data->internal |= BIT(0);
+ } else {
+ sio_data->internal &= ~BIT(3);
+ sio_data->skip_in |= BIT(9);
+ }
+
+ sio_data->beep_pin = superio_inb(sioaddr,
+ IT87_SIO_BEEP_PIN_REG) & 0x3f;
+ } else if (sio_data->type == it8622) {
+ int reg;
+
+ superio_select(sioaddr, GPIO);
+
+ /* Check for pwm4, fan4 */
+ reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
+ if (reg & BIT(6))
+ sio_data->skip_fan |= BIT(3);
+ if (reg & BIT(5))
+ sio_data->skip_pwm |= BIT(3);
+
+ /* Check for pwm3, fan3, pwm5, fan5 */
+ reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
+ if (reg & BIT(6))
+ sio_data->skip_pwm |= BIT(2);
+ if (reg & BIT(7))
+ sio_data->skip_fan |= BIT(2);
+ if (reg & BIT(3))
+ sio_data->skip_pwm |= BIT(4);
+ if (reg & BIT(1))
+ sio_data->skip_fan |= BIT(4);
+
+ /* Check for pwm2, fan2 */
+ reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
+ if (reg & BIT(1))
+ sio_data->skip_pwm |= BIT(1);
+ if (reg & BIT(2))
+ sio_data->skip_fan |= BIT(1);
+
+ /* Check for AVCC */
+ reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
+ if (!(reg & BIT(0)))
+ sio_data->skip_in |= BIT(9);
+
+ sio_data->beep_pin = superio_inb(sioaddr,
+ IT87_SIO_BEEP_PIN_REG) & 0x3f;
+ } else if (sio_data->type == it8732) {
+ int reg;
+
+ superio_select(sioaddr, GPIO);
+
+ /* Check for pwm2, fan2 */
+ reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
+ if (reg & BIT(1))
+ sio_data->skip_pwm |= BIT(1);
+ if (reg & BIT(2))
+ sio_data->skip_fan |= BIT(1);
+
+ /* Check for pwm3, fan3, fan4 */
+ reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
+ if (reg & BIT(6))
+ sio_data->skip_pwm |= BIT(2);
+ if (reg & BIT(7))
+ sio_data->skip_fan |= BIT(2);
+ if (reg & BIT(5))
+ sio_data->skip_fan |= BIT(3);
+
+ /* Check if AVCC is on VIN3 */
+ reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
+ if (reg & BIT(0))
+ sio_data->internal |= BIT(0);
+
+ sio_data->beep_pin = superio_inb(sioaddr,
+ IT87_SIO_BEEP_PIN_REG) & 0x3f;
+ } else if (sio_data->type == it8655) {
+ int reg;
+
+ superio_select(sioaddr, GPIO);
+
+ /* Check for pwm2 */
+ reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
+ if (reg & BIT(1))
+ sio_data->skip_pwm |= BIT(1);
+
+ /* Check for fan2 */
+ reg = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
+ if (reg & BIT(4))
+ sio_data->skip_fan |= BIT(1);
+
+ /* Check for pwm3, fan3 */
+ reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
+ if (reg & BIT(6))
+ sio_data->skip_pwm |= BIT(2);
+ if (reg & BIT(7))
+ sio_data->skip_fan |= BIT(2);
+
+ sio_data->beep_pin = superio_inb(sioaddr,
+ IT87_SIO_BEEP_PIN_REG) & 0x3f;
+ } else if (sio_data->type == it8665 || sio_data->type == it8625) {
+ int reg27, reg29, reg2d, regd3;
+
+ superio_select(sioaddr, GPIO);
+
+ reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
+ reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
+ reg2d = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
+ regd3 = superio_inb(sioaddr, IT87_SIO_GPIO9_REG);
+
+ /* Check for pwm2, fan2 */
+ if (reg29 & BIT(1))
+ sio_data->skip_pwm |= BIT(1);
+ if (reg2d & BIT(4))
+ sio_data->skip_fan |= BIT(1);
+
+ /* Check for pwm3, fan3 */
+ if (reg27 & BIT(6))
+ sio_data->skip_pwm |= BIT(2);
+ if (reg27 & BIT(7))
+ sio_data->skip_fan |= BIT(2);
+
+ /* Check for pwm4, fan4, pwm5, fan5 */
+ if (sio_data->type == it8625) {
+ int reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
+
+ if (reg25 & BIT(6))
+ sio_data->skip_fan |= BIT(3);
+ if (reg25 & BIT(5))
+ sio_data->skip_pwm |= BIT(3);
+ if (reg27 & BIT(3))
+ sio_data->skip_pwm |= BIT(4);
+ if (reg27 & BIT(1))
+ sio_data->skip_fan |= BIT(4);
+ } else {
+ int reg26 = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
+
+ if (regd3 & BIT(2))
+ sio_data->skip_pwm |= BIT(3);
+ if (regd3 & BIT(3))
+ sio_data->skip_fan |= BIT(3);
+ if (reg26 & BIT(5))
+ sio_data->skip_pwm |= BIT(4);
+ if (!(reg26 & BIT(4)))
+ sio_data->skip_fan |= BIT(4);
+ }
+
+ /* Check for pwm6, fan6 */
+ if (regd3 & BIT(0))
+ sio_data->skip_pwm |= BIT(5);
+ if (regd3 & BIT(1))
+ sio_data->skip_fan |= BIT(5);
+
sio_data->beep_pin = superio_inb(sioaddr,
IT87_SIO_BEEP_PIN_REG) & 0x3f;
} else {
if (sio_data->beep_pin)
pr_info("Beeping is supported\n");
- /* Disable specific features based on DMI strings */
- board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR);
- board_name = dmi_get_system_info(DMI_BOARD_NAME);
- if (board_vendor && board_name) {
- if (strcmp(board_vendor, "nVIDIA") == 0 &&
- strcmp(board_name, "FN68PT") == 0) {
- /*
- * On the Shuttle SN68PT, FAN_CTL2 is apparently not
- * connected to a fan, but to something else. One user
- * has reported instant system power-off when changing
- * the PWM2 duty cycle, so we disable it.
- * I use the board name string as the trigger in case
- * the same board is ever used in other systems.
- */
- pr_info("Disabling pwm2 due to hardware constraints\n");
- sio_data->skip_pwm = BIT(1);
- }
- }
-
exit:
superio_exit(sioaddr);
return err;
}
+static void it87_init_regs(struct platform_device *pdev)
+{
+ struct it87_data *data = platform_get_drvdata(pdev);
+
+ /* Initialize chip specific register pointers */
+ switch (data->type) {
+ case it8628:
+ case it8686:
+ data->REG_FAN = IT87_REG_FAN;
+ data->REG_FANX = IT87_REG_FANX;
+ data->REG_FAN_MIN = IT87_REG_FAN_MIN;
+ data->REG_FANX_MIN = IT87_REG_FANX_MIN;
+ data->REG_PWM = IT87_REG_PWM;
+ data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET_8686;
+ data->REG_TEMP_LOW = IT87_REG_TEMP_LOW_8686;
+ data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH_8686;
+ break;
+ case it8625:
+ case it8655:
+ case it8665:
+ data->REG_FAN = IT87_REG_FAN_8665;
+ data->REG_FANX = IT87_REG_FANX_8665;
+ data->REG_FAN_MIN = IT87_REG_FAN_MIN_8665;
+ data->REG_FANX_MIN = IT87_REG_FANX_MIN_8665;
+ data->REG_PWM = IT87_REG_PWM_8665;
+ data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
+ data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
+ data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
+ break;
+ case it8622:
+ data->REG_FAN = IT87_REG_FAN;
+ data->REG_FANX = IT87_REG_FANX;
+ data->REG_FAN_MIN = IT87_REG_FAN_MIN;
+ data->REG_FANX_MIN = IT87_REG_FANX_MIN;
+ data->REG_PWM = IT87_REG_PWM_8665;
+ data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
+ data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
+ data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
+ break;
+ case it8613:
+ data->REG_FAN = IT87_REG_FAN;
+ data->REG_FANX = IT87_REG_FANX;
+ data->REG_FAN_MIN = IT87_REG_FAN_MIN;
+ data->REG_FANX_MIN = IT87_REG_FANX_MIN;
+ data->REG_PWM = IT87_REG_PWM_8665;
+ data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
+ data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
+ data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
+ break;
+ default:
+ data->REG_FAN = IT87_REG_FAN;
+ data->REG_FANX = IT87_REG_FANX;
+ data->REG_FAN_MIN = IT87_REG_FAN_MIN;
+ data->REG_FANX_MIN = IT87_REG_FANX_MIN;
+ data->REG_PWM = IT87_REG_PWM;
+ data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
+ data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
+ data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
+ break;
+ }
+}
+
/* Called when we have found a new IT87. */
static void it87_init_device(struct platform_device *pdev)
{
if (tmp == 0xff)
it87_write_value(data, IT87_REG_VIN_MIN(i), 0);
}
- for (i = 0; i < NUM_TEMP_LIMIT; i++) {
- tmp = it87_read_value(data, IT87_REG_TEMP_HIGH(i));
+ for (i = 0; i < data->num_temp_limit; i++) {
+ tmp = it87_read_value(data, data->REG_TEMP_HIGH[i]);
if (tmp == 0xff)
- it87_write_value(data, IT87_REG_TEMP_HIGH(i), 127);
+ it87_write_value(data, data->REG_TEMP_HIGH[i], 127);
}
/*
}
/* Check for additional fans */
- if (has_five_fans(data)) {
- if (tmp & BIT(4))
- data->has_fan |= BIT(3); /* fan4 enabled */
- if (tmp & BIT(5))
- data->has_fan |= BIT(4); /* fan5 enabled */
- if (has_six_fans(data) && (tmp & BIT(2)))
- data->has_fan |= BIT(5); /* fan6 enabled */
+ if (has_four_fans(data) && (tmp & BIT(4)))
+ data->has_fan |= BIT(3); /* fan4 enabled */
+ if (has_five_fans(data) && (tmp & BIT(5)))
+ data->has_fan |= BIT(4); /* fan5 enabled */
+ if (has_six_fans(data)) {
+ switch (data->type) {
+ case it8620:
+ case it8628:
+ case it8686:
+ if (tmp & BIT(2))
+ data->has_fan |= BIT(5); /* fan6 enabled */
+ break;
+ case it8625:
+ case it8665:
+ tmp = it87_read_value(data, IT87_REG_FAN_DIV);
+ if (tmp & BIT(3))
+ data->has_fan |= BIT(5); /* fan6 enabled */
+ break;
+ default:
+ break;
+ }
}
/* Fan input pins may be used for alternative functions */
data->has_fan &= ~sio_data->skip_fan;
- /* Check if pwm5, pwm6 are enabled */
+ /* Check if pwm6 is enabled */
if (has_six_pwm(data)) {
- /* The following code may be IT8620E specific */
- tmp = it87_read_value(data, IT87_REG_FAN_DIV);
- if ((tmp & 0xc0) == 0xc0)
- sio_data->skip_pwm |= BIT(4);
- if (!(tmp & BIT(3)))
- sio_data->skip_pwm |= BIT(5);
+ switch (data->type) {
+ case it8620:
+ case it8686:
+ tmp = it87_read_value(data, IT87_REG_FAN_DIV);
+ if (!(tmp & BIT(3)))
+ sio_data->skip_pwm |= BIT(5);
+ break;
+ default:
+ break;
+ }
}
/* Start monitoring */
for (i = 0; i < ARRAY_SIZE(pwm); i++)
pwm[i] = it87_read_value(data,
- IT87_REG_PWM[i]);
+ data->REG_PWM[i]);
/*
* If any fan is in automatic pwm mode, the polarity
tmp | 0x87);
for (i = 0; i < 3; i++)
it87_write_value(data,
- IT87_REG_PWM[i],
+ data->REG_PWM[i],
0x7f & ~pwm[i]);
return 1;
}
data->addr = res->start;
data->type = sio_data->type;
data->features = it87_devices[sio_data->type].features;
+ data->num_temp_limit = it87_devices[sio_data->type].num_temp_limit;
+ data->num_temp_offset = it87_devices[sio_data->type].num_temp_offset;
data->peci_mask = it87_devices[sio_data->type].peci_mask;
data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
+ data->bank = 0xff;
+
/*
* IT8705F Datasheet 0.4.1, 3h == Version G.
* IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
mutex_init(&data->update_lock);
+ /* Initialize register pointers */
+ it87_init_regs(pdev);
+
/* Check PWM configuration */
enable_pwm_interface = it87_check_pwm(dev);
/* Starting with IT8721F, we handle scaling of internal voltages */
- if (has_12mv_adc(data)) {
+ if (has_scaling(data)) {
if (sio_data->internal & BIT(0))
data->in_scaled |= BIT(3); /* in3 is AVCC */
if (sio_data->internal & BIT(1))
return err;
}
+struct it87_dmi_data {
+ bool sio4e_broken; /* SIO accesses @ 0x4e are broken */
+ char *sio_mutex; /* SIO ACPI mutex */
+ u8 skip_pwm; /* pwm channels to skip for this board */
+};
+
+/*
+ * On Gigabyte AB350 and AX370 boards, accesses to the Super-IO chip
+ * at address 0x4e/0x4f can result in a system hang.
+ * Accesses to address 0x2e/0x2f need to be mutex protected.
+ */
+static struct it87_dmi_data gigabyte_ab350_gaming = {
+ .sio4e_broken = true,
+ .sio_mutex = "\\_SB.PCI0.SBRG.SIO1.MUT0",
+};
+
+/*
+ * On the Shuttle SN68PT, FAN_CTL2 is apparently not
+ * connected to a fan, but to something else. One user
+ * has reported instant system power-off when changing
+ * the PWM2 duty cycle, so we disable it.
+ * I use the board name string as the trigger in case
+ * the same board is ever used in other systems.
+ */
+static struct it87_dmi_data nvidia_fn68pt = {
+ .skip_pwm = BIT(1),
+};
+
+static const struct dmi_system_id it87_dmi_table[] __initconst = {
+ {
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
+ DMI_MATCH(DMI_BOARD_NAME, "AB350-Gaming-CF"),
+ },
+ .driver_data = &gigabyte_ab350_gaming,
+ },
+ {
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
+ DMI_MATCH(DMI_BOARD_NAME, "AB350-Gaming 3-CF"),
+ },
+ .driver_data = &gigabyte_ab350_gaming,
+ },
+ {
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
+ DMI_MATCH(DMI_BOARD_NAME, "AB350M-D3H-CF"),
+ },
+ .driver_data = &gigabyte_ab350_gaming,
+ },
+ {
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
+ DMI_MATCH(DMI_BOARD_NAME, "AX370-Gaming K7"),
+ },
+ .driver_data = &gigabyte_ab350_gaming,
+ },
+ {
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
+ DMI_MATCH(DMI_BOARD_NAME, "AX370-Gaming 5"),
+ },
+ .driver_data = &gigabyte_ab350_gaming,
+ },
+ {
+ .matches = {
+ DMI_MATCH(DMI_BOARD_VENDOR, "nVIDIA"),
+ DMI_MATCH(DMI_BOARD_NAME, "FN68PT"),
+ },
+ .driver_data = &nvidia_fn68pt,
+ },
+ { }
+};
+
static int __init sm_it87_init(void)
{
+ const struct dmi_system_id *dmi = dmi_first_match(it87_dmi_table);
+ struct it87_dmi_data *dmi_data = NULL;
int sioaddr[2] = { REG_2E, REG_4E };
struct it87_sio_data sio_data;
unsigned short isa_address;
bool found = false;
int i, err;
+ if (dmi)
+ dmi_data = dmi->driver_data;
+
+ if (dmi_data) {
+ it87_sio4e_broken = dmi_data->sio4e_broken;
+#ifdef __IT87_USE_ACPI_MUTEX
+ if (dmi_data->sio_mutex) {
+ static acpi_status status;
+
+ status = acpi_get_handle(NULL, dmi_data->sio_mutex,
+ &it87_acpi_sio_handle);
+ if (ACPI_SUCCESS(status)) {
+ it87_acpi_sio_mutex = dmi_data->sio_mutex;
+ pr_debug("Found ACPI SIO mutex %s\n",
+ dmi_data->sio_mutex);
+ } else {
+ pr_warn("ACPI SIO mutex %s not found\n",
+ dmi_data->sio_mutex);
+ }
+ }
+#endif /* __IT87_USE_ACPI_MUTEX */
+ }
+
err = platform_driver_register(&it87_driver);
if (err)
return err;
for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
+ /*
+ * Accessing the second Super-IO chip can result in board
+ * hangs. Disable until we figure out what is going on.
+ */
+ if (blacklist && it87_sio4e_broken && sioaddr[i] == 0x4e)
+ continue;
memset(&sio_data, 0, sizeof(struct it87_sio_data));
isa_address = 0;
err = it87_find(sioaddr[i], &isa_address, &sio_data);
if (err || isa_address == 0)
continue;
+ if (dmi_data)
+ sio_data.skip_pwm |= dmi_data->skip_pwm;
err = it87_device_add(i, isa_address, &sio_data);
if (err)
goto exit_dev_unregister;
projects / groeck-it87 / blobdiff