#include <linux/acpi.h>
#include <linux/io.h>
#include "compat.h"
+#include "version.h"
#define DRVNAME "it87"
module_param(ignore_resource_conflict, bool, 0);
MODULE_PARM_DESC(ignore_resource_conflict, "Ignore ACPI resource conflict");
+static bool mmio;
+module_param(mmio, bool, 0);
+MODULE_PARM_DESC(mmio, "Use MMIO if available");
+
static struct platform_device *it87_pdev[2];
#define REG_2E 0x2e /* The register to read/write */
* Try to reserve ioreg and ioreg + 1 for exclusive access.
*/
if (!request_muxed_region(ioreg, 2, DRVNAME))
- goto error;
+ return -EBUSY;
__superio_enter(ioreg);
return 0;
-
-error:
- return -EBUSY;
}
static inline void superio_exit(int ioreg, bool doexit)
#define IT8655E_DEVID 0x8655
#define IT8665E_DEVID 0x8665
#define IT8686E_DEVID 0x8686
-#define IT87_ACT_REG 0x30
-#define IT87_BASE_REG 0x60
-/* Logical device 7 registers (IT8712F and later) */
+/* Logical device 4 (Environmental Monitor) registers */
+#define IT87_ACT_REG 0x30
+#define IT87_BASE_REG 0x60
+#define IT87_SPECIAL_CFG_REG 0xf3 /* special configuration register */
+
+/* Global configuration registers (IT8712F and later) */
+#define IT87_EC_HWM_MIO_REG 0x24 /* MMIO configuration register */
#define IT87_SIO_GPIO1_REG 0x25
#define IT87_SIO_GPIO2_REG 0x26
#define IT87_SIO_GPIO3_REG 0x27
#define IT87_SIO_PINX1_REG 0x2a /* Pin selection */
#define IT87_SIO_PINX2_REG 0x2c /* Pin selection */
#define IT87_SIO_PINX4_REG 0x2d /* Pin selection */
+
+/* Logical device 7 (GPIO) registers (IT8712F and later) */
#define IT87_SIO_SPI_REG 0xef /* SPI function pin select */
#define IT87_SIO_VID_REG 0xfc /* VID value */
#define IT87_SIO_BEEP_PIN_REG 0xf6 /* Beep pin mapping */
u8 num_temp_map; /* Number of temperature sources for pwm */
u8 peci_mask;
u8 old_peci_mask;
+ u8 smbus_bitmap; /* SMBus enable bits in extra config register */
+ u8 ec_special_config;
};
#define FEAT_12MV_ADC BIT(0)
#define FEAT_FANCTL_ONOFF BIT(23) /* chip has FAN_CTL ON/OFF */
#define FEAT_11MV_ADC BIT(24)
#define FEAT_NEW_TEMPMAP BIT(25) /* new temp input selection */
+#define FEAT_MMIO BIT(26) /* Chip supports MMIO */
static const struct it87_devices it87_devices[] = {
[it87] = {
.num_temp_limit = 3,
.num_temp_offset = 3,
.num_temp_map = 4,
- .peci_mask = 0x07,
+ .peci_mask = 0x0f,
+ .smbus_bitmap = BIT(1) | BIT(2),
},
[it8625] = {
.name = "it8625",
.num_temp_limit = 6,
.num_temp_offset = 6,
.num_temp_map = 6,
+ .smbus_bitmap = BIT(1) | BIT(2),
},
[it8628] = {
.name = "it8628",
.suffix = "E",
.features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
| FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
- | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_BANK_SEL,
+ | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_BANK_SEL
+ | FEAT_MMIO,
.num_temp_limit = 6,
.num_temp_offset = 6,
.num_temp_map = 6,
+ .smbus_bitmap = BIT(2),
},
[it8665] = {
.name = "it8665",
.features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
| FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
| FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
- | FEAT_SIX_PWM | FEAT_BANK_SEL,
+ | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_MMIO,
.num_temp_limit = 6,
.num_temp_offset = 6,
.num_temp_map = 6,
+ .smbus_bitmap = BIT(2),
},
[it8686] = {
.name = "it8686",
.num_temp_limit = 6,
.num_temp_offset = 6,
.num_temp_map = 7,
+ .smbus_bitmap = BIT(1) | BIT(2),
},
};
#define has_fanctl_onoff(data) ((data)->features & FEAT_FANCTL_ONOFF)
#define has_11mv_adc(data) ((data)->features & FEAT_11MV_ADC)
#define has_new_tempmap(data) ((data)->features & FEAT_NEW_TEMPMAP)
+#define has_mmio(data) ((data)->features & FEAT_MMIO)
struct it87_sio_data {
enum chips type;
+ u8 sioaddr;
+ u8 doexit;
/* Values read from Super-I/O config space */
u8 revision;
u8 vid_value;
u8 skip_fan;
u8 skip_pwm;
u8 skip_temp;
+ u8 smbus_bitmap;
+ u8 ec_special_config;
};
/*
u8 peci_mask;
u8 old_peci_mask;
+ u8 smbus_bitmap; /* !=0 if SMBus needs to be disabled */
+ u8 ec_special_config; /* EC special config register restore value */
+ u8 sioaddr; /* SIO port address */
+ bool doexit; /* true if exit from sio config is ok */
+
+ void __iomem *mmio; /* Remapped MMIO address if available */
+ int (*read)(struct it87_data *, u16);
+ void (*write)(struct it87_data *, u16, u8);
+
const u8 *REG_FAN;
const u8 *REG_FANX;
const u8 *REG_FAN_MIN;
750000,
};
-static int _it87_read_value(struct it87_data *data, u8 reg)
+static int smbus_disable(struct it87_data *data)
+{
+ int err;
+
+ if (data->smbus_bitmap) {
+ err = superio_enter(data->sioaddr);
+ if (err)
+ return err;
+ superio_select(data->sioaddr, PME);
+ superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG,
+ data->ec_special_config & ~data->smbus_bitmap);
+ superio_exit(data->sioaddr, data->doexit);
+ }
+ return 0;
+}
+
+static int smbus_enable(struct it87_data *data)
+{
+ int err;
+
+ if (data->smbus_bitmap) {
+ err = superio_enter(data->sioaddr);
+ if (err)
+ return err;
+
+ superio_select(data->sioaddr, PME);
+ superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG,
+ data->ec_special_config);
+ superio_exit(data->sioaddr, data->doexit);
+ }
+ return 0;
+}
+
+static int _it87_io_read(struct it87_data *data, u16 reg)
{
outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
return inb_p(data->addr + IT87_DATA_REG_OFFSET);
}
-static void _it87_write_value(struct it87_data *data, u8 reg, u8 value)
+static void _it87_io_write(struct it87_data *data, u16 reg, u8 value)
{
outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
}
-static u8 it87_set_bank(struct it87_data *data, u8 bank)
+static u8 it87_io_set_bank(struct it87_data *data, u8 bank)
{
u8 _bank = bank;
if (has_bank_sel(data)) {
- u8 breg = _it87_read_value(data, IT87_REG_BANK);
+ u8 breg = _it87_io_read(data, IT87_REG_BANK);
_bank = breg >> 5;
if (bank != _bank) {
breg &= 0x1f;
breg |= (bank << 5);
- _it87_write_value(data, IT87_REG_BANK, breg);
+ _it87_io_write(data, IT87_REG_BANK, breg);
}
}
return _bank;
/*
* Must be called with data->update_lock held, except during initialization.
+ * Must be called with SMBus accesses disabled.
* We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
* would slow down the IT87 access and should not be necessary.
*/
-static int it87_read_value(struct it87_data *data, u16 reg)
+static int it87_io_read(struct it87_data *data, u16 reg)
{
u8 bank;
int val;
- bank = it87_set_bank(data, reg >> 8);
- val = _it87_read_value(data, reg & 0xff);
- it87_set_bank(data, bank);
+ bank = it87_io_set_bank(data, reg >> 8);
+ val = _it87_io_read(data, reg & 0xff);
+ it87_io_set_bank(data, bank);
return val;
}
/*
* Must be called with data->update_lock held, except during initialization.
+ * Must be called with SMBus accesses disabled
* We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
* would slow down the IT87 access and should not be necessary.
*/
-static void it87_write_value(struct it87_data *data, u16 reg, u8 value)
+static void it87_io_write(struct it87_data *data, u16 reg, u8 value)
{
u8 bank;
- bank = it87_set_bank(data, reg >> 8);
- _it87_write_value(data, reg & 0xff, value);
- it87_set_bank(data, bank);
+ bank = it87_io_set_bank(data, reg >> 8);
+ _it87_io_write(data, reg & 0xff, value);
+ it87_io_set_bank(data, bank);
+}
+
+static int it87_mmio_read(struct it87_data *data, u16 reg)
+{
+ return readb(data->mmio + reg);
+}
+
+static void it87_mmio_write(struct it87_data *data, u16 reg, u8 value)
+{
+ writeb(value, data->mmio + reg);
}
static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
{
u8 ctrl;
- ctrl = it87_read_value(data, data->REG_PWM[nr]);
+ ctrl = data->read(data, data->REG_PWM[nr]);
data->pwm_ctrl[nr] = ctrl;
if (has_newer_autopwm(data)) {
data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
- data->pwm_duty[nr] = it87_read_value(data,
- IT87_REG_PWM_DUTY[nr]);
+ data->pwm_duty[nr] = data->read(data, IT87_REG_PWM_DUTY[nr]);
} else {
if (ctrl & 0x80) /* Automatic mode */
data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
int i;
for (i = 0; i < 5 ; i++)
- data->auto_temp[nr][i] = it87_read_value(data,
+ data->auto_temp[nr][i] = data->read(data,
IT87_REG_AUTO_TEMP(nr, i));
for (i = 0; i < 3 ; i++)
- data->auto_pwm[nr][i] = it87_read_value(data,
+ data->auto_pwm[nr][i] = data->read(data,
IT87_REG_AUTO_PWM(nr, i));
} else if (has_newer_autopwm(data)) {
int i;
* 3: fan max temperature (base + 2)
*/
data->auto_temp[nr][0] =
- it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 5));
+ data->read(data, IT87_REG_AUTO_TEMP(nr, 5));
for (i = 0; i < 3 ; i++)
data->auto_temp[nr][i + 1] =
- it87_read_value(data,
- IT87_REG_AUTO_TEMP(nr, i));
+ data->read(data, IT87_REG_AUTO_TEMP(nr, i));
/*
* 0: start pwm value (base + 3)
* 1: pwm slope (base + 4, 1/8th pwm)
*/
data->auto_pwm[nr][0] =
- it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 3));
+ data->read(data, IT87_REG_AUTO_TEMP(nr, 3));
data->auto_pwm[nr][1] =
- it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 4));
+ data->read(data, IT87_REG_AUTO_TEMP(nr, 4));
}
}
+static int it87_lock(struct it87_data *data)
+{
+ int err;
+
+ mutex_lock(&data->update_lock);
+ err = smbus_disable(data);
+ if (err)
+ mutex_unlock(&data->update_lock);
+ return err;
+}
+
+static void it87_unlock(struct it87_data *data)
+{
+ smbus_enable(data);
+ mutex_unlock(&data->update_lock);
+}
+
static struct it87_data *it87_update_device(struct device *dev)
{
struct it87_data *data = dev_get_drvdata(dev);
+ int err;
int i;
- mutex_lock(&data->update_lock);
+ err = it87_lock(data);
+ if (err)
+ return ERR_PTR(err);
if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
!data->valid) {
* Cleared after each update, so reenable. Value
* returned by this read will be previous value
*/
- it87_write_value(data, IT87_REG_CONFIG,
- it87_read_value(data, IT87_REG_CONFIG) | 0x40);
+ data->write(data, IT87_REG_CONFIG,
+ data->read(data, IT87_REG_CONFIG) | 0x40);
}
for (i = 0; i < NUM_VIN; i++) {
if (!(data->has_in & BIT(i)))
continue;
- data->in[i][0] =
- it87_read_value(data, IT87_REG_VIN[i]);
+ data->in[i][0] = data->read(data, IT87_REG_VIN[i]);
/* VBAT and AVCC don't have limit registers */
if (i >= NUM_VIN_LIMIT)
continue;
- data->in[i][1] =
- it87_read_value(data, IT87_REG_VIN_MIN(i));
- data->in[i][2] =
- it87_read_value(data, IT87_REG_VIN_MAX(i));
+ data->in[i][1] = data->read(data, IT87_REG_VIN_MIN(i));
+ data->in[i][2] = data->read(data, IT87_REG_VIN_MAX(i));
}
for (i = 0; i < NUM_FAN; i++) {
if (!(data->has_fan & BIT(i)))
continue;
- data->fan[i][1] =
- it87_read_value(data, data->REG_FAN_MIN[i]);
- data->fan[i][0] = it87_read_value(data,
- data->REG_FAN[i]);
+ data->fan[i][1] = data->read(data, data->REG_FAN_MIN[i]);
+ data->fan[i][0] = data->read(data, data->REG_FAN[i]);
/* Add high byte if in 16-bit mode */
if (has_16bit_fans(data)) {
- data->fan[i][0] |= it87_read_value(data,
+ data->fan[i][0] |= data->read(data,
data->REG_FANX[i]) << 8;
- data->fan[i][1] |= it87_read_value(data,
+ data->fan[i][1] |= data->read(data,
data->REG_FANX_MIN[i]) << 8;
}
}
if (!(data->has_temp & BIT(i)))
continue;
data->temp[i][0] =
- it87_read_value(data, IT87_REG_TEMP(i));
+ data->read(data, IT87_REG_TEMP(i));
if (i >= data->num_temp_limit)
continue;
if (i < data->num_temp_offset)
data->temp[i][3] =
- it87_read_value(data,
- data->REG_TEMP_OFFSET[i]);
+ data->read(data, data->REG_TEMP_OFFSET[i]);
data->temp[i][1] =
- it87_read_value(data, data->REG_TEMP_LOW[i]);
+ data->read(data, data->REG_TEMP_LOW[i]);
data->temp[i][2] =
- it87_read_value(data, data->REG_TEMP_HIGH[i]);
+ data->read(data, data->REG_TEMP_HIGH[i]);
}
/* Newer chips don't have clock dividers */
if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
- i = it87_read_value(data, IT87_REG_FAN_DIV);
+ i = data->read(data, IT87_REG_FAN_DIV);
data->fan_div[0] = i & 0x07;
data->fan_div[1] = (i >> 3) & 0x07;
data->fan_div[2] = (i & 0x40) ? 3 : 1;
}
data->alarms =
- it87_read_value(data, IT87_REG_ALARM1) |
- (it87_read_value(data, IT87_REG_ALARM2) << 8) |
- (it87_read_value(data, IT87_REG_ALARM3) << 16);
- data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
-
- data->fan_main_ctrl = it87_read_value(data,
- IT87_REG_FAN_MAIN_CTRL);
- data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL);
+ data->read(data, IT87_REG_ALARM1) |
+ (data->read(data, IT87_REG_ALARM2) << 8) |
+ (data->read(data, IT87_REG_ALARM3) << 16);
+ data->beeps = data->read(data, IT87_REG_BEEP_ENABLE);
+
+ data->fan_main_ctrl = data->read(data, IT87_REG_FAN_MAIN_CTRL);
+ data->fan_ctl = data->read(data, IT87_REG_FAN_CTL);
for (i = 0; i < NUM_PWM; i++) {
if (!(data->has_pwm & BIT(i)))
continue;
it87_update_pwm_ctrl(data, i);
}
- data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE);
- data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
+ data->sensor = data->read(data, IT87_REG_TEMP_ENABLE);
+ data->extra = data->read(data, IT87_REG_TEMP_EXTRA);
/*
* The IT8705F does not have VID capability.
* The IT8718F and later don't use IT87_REG_VID for the
* same purpose.
*/
if (data->type == it8712 || data->type == it8716) {
- data->vid = it87_read_value(data, IT87_REG_VID);
+ data->vid = data->read(data, IT87_REG_VID);
/*
* The older IT8712F revisions had only 5 VID pins,
* but we assume it is always safe to read 6 bits.
data->last_updated = jiffies;
data->valid = 1;
}
-
- mutex_unlock(&data->update_lock);
-
+ it87_unlock(data);
return data;
}
int index = sattr->index;
int nr = sattr->nr;
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
}
int index = sattr->index;
int nr = sattr->nr;
unsigned long val;
+ int err;
if (kstrtoul(buf, 10, &val) < 0)
return -EINVAL;
- mutex_lock(&data->update_lock);
+ err = it87_lock(data);
+ if (err)
+ return err;
+
data->in[nr][index] = in_to_reg(data, nr, val);
- it87_write_value(data,
- index == 1 ? IT87_REG_VIN_MIN(nr)
- : IT87_REG_VIN_MAX(nr),
- data->in[nr][index]);
- mutex_unlock(&data->update_lock);
+ data->write(data, index == 1 ? IT87_REG_VIN_MIN(nr)
+ : IT87_REG_VIN_MAX(nr),
+ data->in[nr][index]);
+ it87_unlock(data);
return count;
}
int index = sattr->index;
struct it87_data *data = it87_update_device(dev);
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
}
struct it87_data *data = dev_get_drvdata(dev);
long val;
u8 reg, regval;
+ int err;
if (kstrtol(buf, 10, &val) < 0)
return -EINVAL;
- mutex_lock(&data->update_lock);
+ err = it87_lock(data);
+ if (err)
+ return err;
switch (index) {
default:
reg = data->REG_TEMP_HIGH[nr];
break;
case 3:
- regval = it87_read_value(data, IT87_REG_BEEP_ENABLE);
+ regval = data->read(data, IT87_REG_BEEP_ENABLE);
if (!(regval & 0x80)) {
regval |= 0x80;
- it87_write_value(data, IT87_REG_BEEP_ENABLE, regval);
+ data->write(data, IT87_REG_BEEP_ENABLE, regval);
}
data->valid = 0;
reg = data->REG_TEMP_OFFSET[nr];
}
data->temp[nr][index] = TEMP_TO_REG(val);
- it87_write_value(data, reg, data->temp[nr][index]);
- mutex_unlock(&data->update_lock);
+ data->write(data, reg, data->temp[nr][index]);
+ it87_unlock(data);
return count;
}
static int get_temp_type(struct it87_data *data, int index)
{
u8 reg, extra;
- int type = 0;
+ int ttype, type = 0;
if (has_bank_sel(data)) {
u8 src1, src2;
return 0;
}
}
+ if (type)
+ return type;
+
+ /* Dectect PECI vs. AMDTSI if possible */
+ ttype = 6;
+ if ((has_temp_peci(data, index)) && data->type != it8721) {
+ extra = data->read(data, 0x98); /* PCH/AMDTSI host status */
+ if (extra & BIT(6))
+ ttype = 5;
+ }
+
+ reg = data->read(data, IT87_REG_TEMP_ENABLE);
+
+ /* Per chip special detection */
+ switch (data->type) {
+ case it8622:
+ if (!(reg & 0xc0) && index == 3)
+ type = ttype;
+ break;
+ default:
+ break;
+ }
+
if (type || index >= 3)
return type;
- reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
- extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
+ extra = data->read(data, IT87_REG_TEMP_EXTRA);
if ((has_temp_peci(data, index) && (reg >> 6 == index + 1)) ||
(has_temp_old_peci(data, index) && (extra & 0x80)))
- type = 6; /* Intel PECI */
+ type = ttype; /* Intel PECI or AMDTSI */
if (reg & BIT(index))
type = 3; /* thermal diode */
else if (reg & BIT(index + 3))
{
struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
struct it87_data *data = it87_update_device(dev);
- int type = get_temp_type(data, sensor_attr->index);
+ int type;
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
+ type = get_temp_type(data, sensor_attr->index);
return sprintf(buf, "%d\n", type);
}
struct it87_data *data = dev_get_drvdata(dev);
long val;
u8 reg, extra;
+ int err;
if (kstrtol(buf, 10, &val) < 0)
return -EINVAL;
- reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
+ err = it87_lock(data);
+ if (err)
+ return err;
+
+ reg = data->read(data, IT87_REG_TEMP_ENABLE);
reg &= ~(1 << nr);
reg &= ~(8 << nr);
if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
reg &= 0x3f;
- extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
+ extra = data->read(data, IT87_REG_TEMP_EXTRA);
if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
extra &= 0x7f;
if (val == 2) { /* backwards compatibility */
reg |= (nr + 1) << 6;
else if (has_temp_old_peci(data, nr) && val == 6)
extra |= 0x80;
- else if (val != 0)
- return -EINVAL;
+ else if (val != 0) {
+ count = -EINVAL;
+ goto unlock;
+ }
- mutex_lock(&data->update_lock);
data->sensor = reg;
data->extra = extra;
- it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor);
+ data->write(data, IT87_REG_TEMP_ENABLE, data->sensor);
if (has_temp_old_peci(data, nr))
- it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
+ data->write(data, IT87_REG_TEMP_EXTRA, data->extra);
data->valid = 0; /* Force cache refresh */
- mutex_unlock(&data->update_lock);
+unlock:
+ it87_unlock(data);
return count;
}
int speed;
struct it87_data *data = it87_update_device(dev);
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
speed = has_16bit_fans(data) ?
FAN16_FROM_REG(data->fan[nr][index]) :
FAN_FROM_REG(data->fan[nr][index],
struct it87_data *data = it87_update_device(dev);
int nr = sensor_attr->index;
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
}
struct it87_data *data = it87_update_device(dev);
int nr = sensor_attr->index;
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
return sprintf(buf, "%d\n", pwm_mode(data, nr));
}
struct it87_data *data = it87_update_device(dev);
int nr = sensor_attr->index;
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
return sprintf(buf, "%d\n",
pwm_from_reg(data, data->pwm_duty[nr]));
}
unsigned int freq;
int index;
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
if (has_pwm_freq2(data) && nr == 1)
index = (data->extra >> 4) & 0x07;
else
struct it87_data *data = dev_get_drvdata(dev);
long val;
+ int err;
u8 reg;
if (kstrtol(buf, 10, &val) < 0)
return -EINVAL;
- mutex_lock(&data->update_lock);
+ err = it87_lock(data);
+ if (err)
+ return err;
if (has_16bit_fans(data)) {
data->fan[nr][index] = FAN16_TO_REG(val);
- it87_write_value(data, data->REG_FAN_MIN[nr],
- data->fan[nr][index] & 0xff);
- it87_write_value(data, data->REG_FANX_MIN[nr],
- data->fan[nr][index] >> 8);
+ data->write(data, data->REG_FAN_MIN[nr],
+ data->fan[nr][index] & 0xff);
+ data->write(data, data->REG_FANX_MIN[nr],
+ data->fan[nr][index] >> 8);
} else {
- reg = it87_read_value(data, IT87_REG_FAN_DIV);
+ reg = data->read(data, IT87_REG_FAN_DIV);
switch (nr) {
case 0:
data->fan_div[nr] = reg & 0x07;
}
data->fan[nr][index] =
FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
- it87_write_value(data, data->REG_FAN_MIN[nr],
- data->fan[nr][index]);
+ data->write(data, data->REG_FAN_MIN[nr], data->fan[nr][index]);
}
-
- mutex_unlock(&data->update_lock);
+ it87_unlock(data);
return count;
}
struct it87_data *data = dev_get_drvdata(dev);
int nr = sensor_attr->index;
unsigned long val;
- int min;
+ int min, err;
u8 old;
if (kstrtoul(buf, 10, &val) < 0)
return -EINVAL;
- mutex_lock(&data->update_lock);
- old = it87_read_value(data, IT87_REG_FAN_DIV);
+ err = it87_lock(data);
+ if (err)
+ return err;
+
+ old = data->read(data, IT87_REG_FAN_DIV);
/* Save fan min limit */
min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
val |= (data->fan_div[1] & 0x07) << 3;
if (data->fan_div[2] == 3)
val |= 0x1 << 6;
- it87_write_value(data, IT87_REG_FAN_DIV, val);
+ data->write(data, IT87_REG_FAN_DIV, val);
/* Restore fan min limit */
data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
- it87_write_value(data, data->REG_FAN_MIN[nr], data->fan[nr][1]);
-
- mutex_unlock(&data->update_lock);
+ data->write(data, data->REG_FAN_MIN[nr], data->fan[nr][1]);
+ it87_unlock(data);
return count;
}
struct it87_data *data = dev_get_drvdata(dev);
int nr = sensor_attr->index;
long val;
+ int err;
if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
return -EINVAL;
return -EINVAL;
}
- mutex_lock(&data->update_lock);
+ err = it87_lock(data);
+ if (err)
+ return err;;
+
it87_update_pwm_ctrl(data, nr);
if (val == 0) {
if (nr < 3 && has_fanctl_onoff(data)) {
int tmp;
/* make sure the fan is on when in on/off mode */
- tmp = it87_read_value(data, IT87_REG_FAN_CTL);
- it87_write_value(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
+ tmp = data->read(data, IT87_REG_FAN_CTL);
+ data->write(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
/* set on/off mode */
data->fan_main_ctrl &= ~BIT(nr);
- it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
- data->fan_main_ctrl);
+ data->write(data, IT87_REG_FAN_MAIN_CTRL,
+ data->fan_main_ctrl);
} else {
u8 ctrl;
/* No on/off mode, set maximum pwm value */
data->pwm_duty[nr] = pwm_to_reg(data, 0xff);
- it87_write_value(data, IT87_REG_PWM_DUTY[nr],
- data->pwm_duty[nr]);
+ data->write(data, IT87_REG_PWM_DUTY[nr],
+ data->pwm_duty[nr]);
/* and set manual mode */
if (has_newer_autopwm(data)) {
ctrl = temp_map_to_reg(data, nr,
ctrl = data->pwm_duty[nr];
}
data->pwm_ctrl[nr] = ctrl;
- it87_write_value(data, data->REG_PWM[nr], ctrl);
+ data->write(data, data->REG_PWM[nr], ctrl);
}
} else {
u8 ctrl;
ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80);
}
data->pwm_ctrl[nr] = ctrl;
- it87_write_value(data, data->REG_PWM[nr], ctrl);
+ data->write(data, data->REG_PWM[nr], ctrl);
if (has_fanctl_onoff(data) && nr < 3) {
/* set SmartGuardian mode */
data->fan_main_ctrl |= BIT(nr);
- it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
- data->fan_main_ctrl);
+ data->write(data, IT87_REG_FAN_MAIN_CTRL,
+ data->fan_main_ctrl);
}
}
-
- mutex_unlock(&data->update_lock);
+ it87_unlock(data);
return count;
}
struct it87_data *data = dev_get_drvdata(dev);
int nr = sensor_attr->index;
long val;
+ int err;
if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
return -EINVAL;
- mutex_lock(&data->update_lock);
+ err = it87_lock(data);
+ if (err)
+ return err;
+
it87_update_pwm_ctrl(data, nr);
if (has_newer_autopwm(data)) {
/*
* is read-only so we can't write the value.
*/
if (data->pwm_ctrl[nr] & 0x80) {
- mutex_unlock(&data->update_lock);
- return -EBUSY;
+ count = -EBUSY;
+ goto unlock;
}
data->pwm_duty[nr] = pwm_to_reg(data, val);
- it87_write_value(data, IT87_REG_PWM_DUTY[nr],
- data->pwm_duty[nr]);
+ data->write(data, IT87_REG_PWM_DUTY[nr],
+ data->pwm_duty[nr]);
} else {
data->pwm_duty[nr] = pwm_to_reg(data, val);
/*
*/
if (!(data->pwm_ctrl[nr] & 0x80)) {
data->pwm_ctrl[nr] = data->pwm_duty[nr];
- it87_write_value(data, data->REG_PWM[nr],
- data->pwm_ctrl[nr]);
+ data->write(data, data->REG_PWM[nr],
+ data->pwm_ctrl[nr]);
}
}
- mutex_unlock(&data->update_lock);
+unlock:
+ it87_unlock(data);
return count;
}
struct it87_data *data = dev_get_drvdata(dev);
int nr = sensor_attr->index;
unsigned long val;
+ int err;
int i;
if (kstrtoul(buf, 10, &val) < 0)
break;
}
- mutex_lock(&data->update_lock);
+ err = it87_lock(data);
+ if (err)
+ return err;
+
if (nr == 0) {
- data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f;
+ data->fan_ctl = data->read(data, IT87_REG_FAN_CTL) & 0x8f;
data->fan_ctl |= i << 4;
- it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl);
+ data->write(data, IT87_REG_FAN_CTL, data->fan_ctl);
} else {
- data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x8f;
+ data->extra = data->read(data, IT87_REG_TEMP_EXTRA) & 0x8f;
data->extra |= i << 4;
- it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
+ data->write(data, IT87_REG_TEMP_EXTRA, data->extra);
}
- mutex_unlock(&data->update_lock);
-
+ it87_unlock(data);
return count;
}
struct it87_data *data = it87_update_device(dev);
int nr = sensor_attr->index;
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
return sprintf(buf, "%d\n", data->pwm_temp_map[nr] + 1);
}
struct it87_data *data = dev_get_drvdata(dev);
int nr = sensor_attr->index;
unsigned long val;
+ int err;
u8 map;
if (kstrtoul(buf, 10, &val) < 0)
map = val - 1;
- mutex_lock(&data->update_lock);
+ err = it87_lock(data);
+ if (err)
+ return err;
+
it87_update_pwm_ctrl(data, nr);
data->pwm_temp_map[nr] = map;
/*
*/
if (data->pwm_ctrl[nr] & 0x80) {
data->pwm_ctrl[nr] = temp_map_to_reg(data, nr, map);
- it87_write_value(data, data->REG_PWM[nr], data->pwm_ctrl[nr]);
+ data->write(data, data->REG_PWM[nr], data->pwm_ctrl[nr]);
}
- mutex_unlock(&data->update_lock);
+ it87_unlock(data);
return count;
}
int nr = sensor_attr->nr;
int point = sensor_attr->index;
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
return sprintf(buf, "%d\n",
pwm_from_reg(data, data->auto_pwm[nr][point]));
}
int point = sensor_attr->index;
int regaddr;
long val;
+ int err;
if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
return -EINVAL;
- mutex_lock(&data->update_lock);
+ err = it87_lock(data);
+ if (err)
+ return err;
+
data->auto_pwm[nr][point] = pwm_to_reg(data, val);
if (has_newer_autopwm(data))
regaddr = IT87_REG_AUTO_TEMP(nr, 3);
else
regaddr = IT87_REG_AUTO_PWM(nr, point);
- it87_write_value(data, regaddr, data->auto_pwm[nr][point]);
- mutex_unlock(&data->update_lock);
+ data->write(data, regaddr, data->auto_pwm[nr][point]);
+ it87_unlock(data);
return count;
}
struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
int nr = sensor_attr->index;
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f);
}
struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
int nr = sensor_attr->index;
unsigned long val;
+ int err;
if (kstrtoul(buf, 10, &val) < 0 || val > 127)
return -EINVAL;
- mutex_lock(&data->update_lock);
+ err = it87_lock(data);
+ if (err)
+ return err;
+
data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val;
- it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 4),
- data->auto_pwm[nr][1]);
- mutex_unlock(&data->update_lock);
+ data->write(data, IT87_REG_AUTO_TEMP(nr, 4), data->auto_pwm[nr][1]);
+ it87_unlock(data);
return count;
}
int point = sensor_attr->index;
int reg;
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
if (has_old_autopwm(data) || point)
reg = data->auto_temp[nr][point];
else
int point = sensor_attr->index;
long val;
int reg;
+ int err;
if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
return -EINVAL;
- mutex_lock(&data->update_lock);
+ err = it87_lock(data);
+ if (err)
+ return err;
+
if (has_newer_autopwm(data) && !point) {
reg = data->auto_temp[nr][1] - TEMP_TO_REG(val);
reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0);
data->auto_temp[nr][0] = reg;
- it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 5), reg);
+ data->write(data, IT87_REG_AUTO_TEMP(nr, 5), reg);
} else {
reg = TEMP_TO_REG(val);
data->auto_temp[nr][point] = reg;
if (has_newer_autopwm(data))
point--;
- it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point), reg);
+ data->write(data, IT87_REG_AUTO_TEMP(nr, point), reg);
}
- mutex_unlock(&data->update_lock);
+ it87_unlock(data);
return count;
}
{
struct it87_data *data = it87_update_device(dev);
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
return sprintf(buf, "%u\n", data->alarms);
}
static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
struct it87_data *data = it87_update_device(dev);
int bitnr = to_sensor_dev_attr(attr)->index;
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
}
size_t count)
{
struct it87_data *data = dev_get_drvdata(dev);
- int config;
+ int err, config;
long val;
if (kstrtol(buf, 10, &val) < 0 || val != 0)
return -EINVAL;
- mutex_lock(&data->update_lock);
- config = it87_read_value(data, IT87_REG_CONFIG);
- if (config < 0) {
- count = config;
- } else {
- config |= BIT(5);
- it87_write_value(data, IT87_REG_CONFIG, config);
- /* Invalidate cache to force re-read */
- data->valid = 0;
- }
- mutex_unlock(&data->update_lock);
+ err = it87_lock(data);
+ if (err)
+ return err;
+ config = data->read(data, IT87_REG_CONFIG);
+ config |= BIT(5);
+ data->write(data, IT87_REG_CONFIG, config);
+ /* Invalidate cache to force re-read */
+ data->valid = 0;
+ it87_unlock(data);
return count;
}
struct it87_data *data = it87_update_device(dev);
int bitnr = to_sensor_dev_attr(attr)->index;
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
}
int bitnr = to_sensor_dev_attr(attr)->index;
struct it87_data *data = dev_get_drvdata(dev);
long val;
+ int err;
if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1))
return -EINVAL;
- mutex_lock(&data->update_lock);
- data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
+ err = it87_lock(data);
+ if (err)
+ return err;
+
+ data->beeps = data->read(data, IT87_REG_BEEP_ENABLE);
if (val)
data->beeps |= BIT(bitnr);
else
data->beeps &= ~BIT(bitnr);
- it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps);
- mutex_unlock(&data->update_lock);
+ data->write(data, IT87_REG_BEEP_ENABLE, data->beeps);
+ it87_unlock(data);
return count;
}
{
struct it87_data *data = it87_update_device(dev);
+ if (IS_ERR(data))
+ return PTR_ERR(data);
+
return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm));
}
static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
/* SuperIO detection - will change isa_address if a chip is found */
static int __init it87_find(int sioaddr, unsigned short *address,
- struct it87_sio_data *sio_data)
+ phys_addr_t *mmio_address, struct it87_sio_data *sio_data)
{
const struct it87_devices *config;
+ phys_addr_t base = 0;
bool doexit = true;
+ char mmio_str[32];
u16 chip_type;
int err;
if (err)
return err;
+ sio_data->sioaddr = sioaddr;
+
err = -ENODEV;
chip_type = superio_inw(sioaddr, DEVID);
if (chip_type == 0xffff)
goto exit;
}
+ sio_data->doexit = doexit;
+
err = 0;
sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
- pr_info("Found IT%04x%s chip at 0x%x, revision %d\n", chip_type,
- it87_devices[sio_data->type].suffix,
- *address, sio_data->revision);
config = &it87_devices[sio_data->type];
+ if (has_mmio(config) && mmio) {
+ u8 reg;
+
+ reg = superio_inb(sioaddr, IT87_EC_HWM_MIO_REG);
+ if (reg & BIT(5)) {
+ base = 0xf0000000 + ((reg & 0x0f) << 24);
+ base += (reg & 0xc0) << 14;
+ }
+ }
+ *mmio_address = base;
+
+ mmio_str[0] = '\0';
+ if (base)
+ snprintf(mmio_str, sizeof(mmio_str), " [MMIO at %pa]", &base);
+
+ pr_info("Found IT%04x%s chip at 0x%x%s, revision %d\n", chip_type,
+ it87_devices[sio_data->type].suffix,
+ *address, mmio_str, sio_data->revision);
+
/* in7 (VSB or VCCH5V) is always internal on some chips */
if (has_in7_internal(config))
sio_data->internal |= BIT(1);
/* Check for pwm2, fan2 */
if (reg29 & BIT(1))
sio_data->skip_pwm |= BIT(1);
+ /*
+ * Note: Table 6-1 in datasheet claims that FAN_TAC2
+ * would be enabled with 29h[2]=0.
+ */
if (reg2d & BIT(4))
sio_data->skip_fan |= BIT(1);
sio_data->skip_fan |= BIT(3);
if (reg26 & BIT(5))
sio_data->skip_pwm |= BIT(4);
- if (!(reg26 & BIT(4)))
+ if (reg26 & BIT(4))
sio_data->skip_fan |= BIT(4);
}
if (sio_data->beep_pin)
pr_info("Beeping is supported\n");
+ if (config->smbus_bitmap && !base) {
+ u8 reg;
+
+ superio_select(sioaddr, PME);
+ reg = superio_inb(sioaddr, IT87_SPECIAL_CFG_REG);
+ sio_data->ec_special_config = reg;
+ sio_data->smbus_bitmap = reg & config->smbus_bitmap;
+ }
+
exit:
superio_exit(sioaddr, doexit);
return err;
data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
break;
}
+
+ if (data->mmio) {
+ data->read = it87_mmio_read;
+ data->write = it87_mmio_write;
+ } else if (has_bank_sel(data)) {
+ data->read = it87_io_read;
+ data->write = it87_io_write;
+ } else {
+ data->read = _it87_io_read;
+ data->write = _it87_io_write;
+ }
}
/* Called when we have found a new IT87. */
* but is still confusing, so change to 127 degrees C.
*/
for (i = 0; i < NUM_VIN_LIMIT; i++) {
- tmp = it87_read_value(data, IT87_REG_VIN_MIN(i));
+ tmp = data->read(data, IT87_REG_VIN_MIN(i));
if (tmp == 0xff)
- it87_write_value(data, IT87_REG_VIN_MIN(i), 0);
+ data->write(data, IT87_REG_VIN_MIN(i), 0);
}
for (i = 0; i < data->num_temp_limit; i++) {
- tmp = it87_read_value(data, data->REG_TEMP_HIGH[i]);
+ tmp = data->read(data, data->REG_TEMP_HIGH[i]);
if (tmp == 0xff)
- it87_write_value(data, data->REG_TEMP_HIGH[i], 127);
+ data->write(data, data->REG_TEMP_HIGH[i], 127);
}
/*
*/
/* Check if voltage monitors are reset manually or by some reason */
- tmp = it87_read_value(data, IT87_REG_VIN_ENABLE);
+ tmp = data->read(data, IT87_REG_VIN_ENABLE);
if ((tmp & 0xff) == 0) {
/* Enable all voltage monitors */
- it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff);
+ data->write(data, IT87_REG_VIN_ENABLE, 0xff);
}
/* Check if tachometers are reset manually or by some reason */
mask = 0x70 & ~(sio_data->skip_fan << 4);
- data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
+ data->fan_main_ctrl = data->read(data, IT87_REG_FAN_MAIN_CTRL);
if ((data->fan_main_ctrl & mask) == 0) {
/* Enable all fan tachometers */
data->fan_main_ctrl |= mask;
- it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
- data->fan_main_ctrl);
+ data->write(data, IT87_REG_FAN_MAIN_CTRL, data->fan_main_ctrl);
}
data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
- tmp = it87_read_value(data, IT87_REG_FAN_16BIT);
+ tmp = data->read(data, IT87_REG_FAN_16BIT);
/* Set tachometers to 16-bit mode if needed */
if (has_fan16_config(data)) {
if (~tmp & 0x07 & data->has_fan) {
dev_dbg(&pdev->dev,
"Setting fan1-3 to 16-bit mode\n");
- it87_write_value(data, IT87_REG_FAN_16BIT,
- tmp | 0x07);
+ data->write(data, IT87_REG_FAN_16BIT, tmp | 0x07);
}
}
break;
case it8625:
case it8665:
- tmp = it87_read_value(data, IT87_REG_FAN_DIV);
+ tmp = data->read(data, IT87_REG_FAN_DIV);
if (tmp & BIT(3))
data->has_fan |= BIT(5); /* fan6 enabled */
break;
switch (data->type) {
case it8620:
case it8686:
- tmp = it87_read_value(data, IT87_REG_FAN_DIV);
+ tmp = data->read(data, IT87_REG_FAN_DIV);
if (!(tmp & BIT(3)))
sio_data->skip_pwm |= BIT(5);
break;
if (has_bank_sel(data)) {
for (i = 0; i < 3; i++)
data->temp_src[i] =
- it87_read_value(data, IT87_REG_TEMP_SRC1[i]);
- data->temp_src[3] = it87_read_value(data, IT87_REG_TEMP_SRC2);
+ data->read(data, IT87_REG_TEMP_SRC1[i]);
+ data->temp_src[3] = data->read(data, IT87_REG_TEMP_SRC2);
}
/* Start monitoring */
- it87_write_value(data, IT87_REG_CONFIG,
- (it87_read_value(data, IT87_REG_CONFIG) & 0x3e)
- | (update_vbat ? 0x41 : 0x01));
+ data->write(data, IT87_REG_CONFIG,
+ (data->read(data, IT87_REG_CONFIG) & 0x3e) |
+ (update_vbat ? 0x41 : 0x01));
}
/* Return 1 if and only if the PWM interface is safe to use */
* and polarity set to active low is sign that this is the case so we
* disable pwm control to protect the user.
*/
- int tmp = it87_read_value(data, IT87_REG_FAN_CTL);
+ int tmp = data->read(data, IT87_REG_FAN_CTL);
if ((tmp & 0x87) == 0) {
if (fix_pwm_polarity) {
u8 pwm[3];
for (i = 0; i < ARRAY_SIZE(pwm); i++)
- pwm[i] = it87_read_value(data,
+ pwm[i] = data->read(data,
data->REG_PWM[i]);
/*
if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
dev_info(dev,
"Reconfiguring PWM to active high polarity\n");
- it87_write_value(data, IT87_REG_FAN_CTL,
- tmp | 0x87);
+ data->write(data, IT87_REG_FAN_CTL, tmp | 0x87);
for (i = 0; i < 3; i++)
- it87_write_value(data,
- data->REG_PWM[i],
- 0x7f & ~pwm[i]);
+ data->write(data, data->REG_PWM[i],
+ 0x7f & ~pwm[i]);
return 1;
}
struct it87_sio_data *sio_data = dev_get_platdata(dev);
int enable_pwm_interface;
struct device *hwmon_dev;
+ int err;
- res = platform_get_resource(pdev, IORESOURCE_IO, 0);
- if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT,
- DRVNAME)) {
- dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
- (unsigned long)res->start,
- (unsigned long)(res->start + IT87_EC_EXTENT - 1));
- return -EBUSY;
- }
-
- data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL);
+ data = devm_kzalloc(dev, sizeof(struct it87_data), GFP_KERNEL);
if (!data)
return -ENOMEM;
+ res = platform_get_resource(pdev, IORESOURCE_IO, 0);
+ if (res) {
+ if (!devm_request_region(dev, res->start, IT87_EC_EXTENT,
+ DRVNAME)) {
+ dev_err(dev, "Failed to request region %pR\n", res);
+ return -EBUSY;
+ }
+ } else {
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ data->mmio = devm_ioremap_resource(dev, res);
+ if (IS_ERR(data->mmio))
+ return PTR_ERR(data->mmio);
+ }
+
data->addr = res->start;
data->type = sio_data->type;
+ data->sioaddr = sio_data->sioaddr;
+ data->smbus_bitmap = sio_data->smbus_bitmap;
+ data->ec_special_config = sio_data->ec_special_config;
+ data->doexit = sio_data->doexit;
data->features = it87_devices[sio_data->type].features;
data->num_temp_limit = it87_devices[sio_data->type].num_temp_limit;
data->num_temp_offset = it87_devices[sio_data->type].num_temp_offset;
break;
}
- /* Now, we do the remaining detection. */
- if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80) ||
- it87_read_value(data, IT87_REG_CHIPID) != 0x90)
- return -ENODEV;
-
platform_set_drvdata(pdev, data);
mutex_init(&data->update_lock);
/* Initialize register pointers */
it87_init_regs(pdev);
+ err = smbus_disable(data);
+ if (err)
+ return err;
+
+ /* Now, we do the remaining detection. */
+ if ((data->read(data, IT87_REG_CONFIG) & 0x80) ||
+ data->read(data, IT87_REG_CHIPID) != 0x90) {
+ smbus_enable(data);
+ return -ENODEV;
+ }
+
/* Check PWM configuration */
enable_pwm_interface = it87_check_pwm(dev);
data->has_temp = 0x07;
if (sio_data->skip_temp & BIT(2)) {
if (sio_data->type == it8782 &&
- !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80))
+ !(data->read(data, IT87_REG_TEMP_EXTRA) & 0x80))
data->has_temp &= ~BIT(2);
}
data->has_in = 0x3ff & ~sio_data->skip_in;
if (has_six_temp(data)) {
- u8 reg = it87_read_value(data, IT87_REG_TEMP456_ENABLE);
+ u8 reg = data->read(data, IT87_REG_TEMP456_ENABLE);
/* Check for additional temperature sensors */
if ((reg & 0x03) >= 0x02)
/* Initialize the IT87 chip */
it87_init_device(pdev);
+ smbus_enable(data);
+
if (!sio_data->skip_vid) {
data->has_vid = true;
data->vrm = vid_which_vrm();
.probe = it87_probe,
};
-static int __init it87_device_add(int index, unsigned short address,
+static int __init it87_device_add(int index, unsigned short sio_address,
+ phys_addr_t mmio_address,
const struct it87_sio_data *sio_data)
{
struct platform_device *pdev;
struct resource res = {
- .start = address + IT87_EC_OFFSET,
- .end = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1,
.name = DRVNAME,
- .flags = IORESOURCE_IO,
};
int err;
+ if (mmio_address) {
+ res.start = mmio_address;
+ res.end = mmio_address + 0x400 - 1;
+ res.flags = IORESOURCE_MEM;
+ } else {
+ res.start = sio_address + IT87_EC_OFFSET;
+ res.end = sio_address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1;
+ res.flags = IORESOURCE_IO;
+ }
+
err = acpi_check_resource_conflict(&res);
if (err) {
if (!ignore_resource_conflict)
return err;
}
- pdev = platform_device_alloc(DRVNAME, address);
+ pdev = platform_device_alloc(DRVNAME, sio_address);
if (!pdev)
return -ENOMEM;
int sioaddr[2] = { REG_2E, REG_4E };
struct it87_sio_data sio_data;
unsigned short isa_address;
+ phys_addr_t mmio_address;
bool found = false;
int i, err;
+ pr_info("it87 driver version %s\n", IT87_DRIVER_VERSION);
+
if (dmi)
dmi_data = dmi->driver_data;
for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
memset(&sio_data, 0, sizeof(struct it87_sio_data));
isa_address = 0;
- err = it87_find(sioaddr[i], &isa_address, &sio_data);
+ mmio_address = 0;
+ err = it87_find(sioaddr[i], &isa_address, &mmio_address,
+ &sio_data);
if (err || isa_address == 0)
continue;
if (dmi_data)
sio_data.skip_pwm |= dmi_data->skip_pwm;
- err = it87_device_add(i, isa_address, &sio_data);
+ err = it87_device_add(i, isa_address, mmio_address, &sio_data);
if (err)
goto exit_dev_unregister;
found = true;
projects / groeck-it87 / blobdiff