From: Guenter Roeck Date: Sat, 7 Oct 2017 14:38:41 +0000 (-0700) Subject: Fix PECI/AMDTSI selection X-Git-Url: https://git.sur5r.net/?p=groeck-it87;a=commitdiff_plain;h=6582b4739f90e8efec31c7406a7826bdf314f8a8 Fix PECI/AMDTSI selection We can not use register 0x98 since it is typically not programmed on systems selecting PECI. Try register 0x0a (Interface Selection) which should be a better fit anyway. Signed-off-by: Guenter Roeck --- diff --git a/it87.c b/it87.c index 8a51027..7c1e7e4 100644 --- a/it87.c +++ b/it87.c @@ -258,6 +258,10 @@ static bool fix_pwm_polarity; * Super-I/O configuration space. */ #define IT87_REG_VID 0x0a + +/* Interface Selection register on other chips */ +#define IT87_REG_IFSEL 0x0a + /* * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b * for fan divisors. Later IT8712F revisions must use 16-bit tachometer @@ -1465,11 +1469,12 @@ static int get_temp_type(struct it87_data *data, int index) if (type) return type; - /* Dectect PECI vs. AMDTSI if possible */ + /* Dectect PECI vs. AMDTSI */ ttype = 6; - if ((has_temp_peci(data, index)) && data->type != it8721) { - extra = data->read(data, 0x98); /* PCH/AMDTSI host status */ - if (extra & BIT(6)) + if ((has_temp_peci(data, index)) || data->type == it8721 || + data->type == it8720) { + extra = data->read(data, IT87_REG_IFSEL); + if ((extra & 0x70) == 0x40) ttype = 5; }