target/stm32: make APCSW cacheable

Change-Id: I7c5c9720ded329848647f17db95f845e46c01c19
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4674
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

diff --git a/tcl/target/stm32f7x.cfg b/tcl/target/stm32f7x.cfg
index 562de30f6a1eb23e4f968351f733e93c591ea7a9..e06a34594f45040ea4e72ffb85dbffc4852e90d1 100755 (executable)
--- a/tcl/target/stm32f7x.cfg
+++ b/tcl/target/stm32f7x.cfg
@@ -145,3 +145,11 @@ $_TARGETNAME configure -event reset-start {
        # Reduce speed since CPU speed will slow down to 16MHz with the reset
        adapter_khz 2000
 }
+
+# Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
+# HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
+# makes the data access cacheable. This allows reading and writing data in the
+# CPU cache from the debugger, which is far more useful than going straight to
+# RAM when operating on typical variables, and is generally no worse when
+# operating on special memory locations.
+$_CHIPNAME.dap apcsw 0x08000000 0x08000000

diff --git a/tcl/target/stm32h7x.cfg b/tcl/target/stm32h7x.cfg
index 10477a5a70dd3da17d050b2bf606d08f5bce4074..e2ea8a84eb1c27e521927344cb8cf08ba40a37c5 100644 (file)
--- a/tcl/target/stm32h7x.cfg
+++ b/tcl/target/stm32h7x.cfg
@@ -92,3 +92,11 @@ $_TARGETNAME configure -event reset-init {
        # Clock after reset is HSI at 64 MHz, no need of PLL
        adapter_khz 4000
 }
+
+# Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
+# HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
+# makes the data access cacheable. This allows reading and writing data in the
+# CPU cache from the debugger, which is far more useful than going straight to
+# RAM when operating on typical variables, and is generally no worse when
+# operating on special memory locations.
+$_CHIPNAME.dap apcsw 0x08000000 0x08000000