tcl/target|board: move common AR9331 code to atheros_ar9331.cfg

The ar9331_25mhz_pll_init and ar9331_ddr1_init routines
can be used not only for TP-Link MR3020 board,
so move them to the common atheros_ar9331.cfg file.

Change-Id: I04090856b08151d6bb0f5ef9cc654efae1c81835
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Reviewed-on: http://openocd.zylin.com/2999
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>

diff --git a/tcl/board/tp-link_tl-mr3020.cfg b/tcl/board/tp-link_tl-mr3020.cfg
index 7e040b32538a9c9fe4fe55ff544b99d5ae4625a0..48fb698937aba9b2b1c6fddcc0085f0f14607a53 100644 (file)
--- a/tcl/board/tp-link_tl-mr3020.cfg
+++ b/tcl/board/tp-link_tl-mr3020.cfg
@@ -1,39 +1,5 @@
 source [find target/atheros_ar9331.cfg]
 
-proc ar9331_25mhz_pll_init {} {
-       mww 0xb8050008 0x00018004       ;# bypass PLL; AHB_POST_DIV - ratio 4
-       mww 0xb8050004 0x00000352       ;# 34000(ns)/40ns(25MHz) = 0x352 (850)
-       mww 0xb8050000 0x40818000       ;# Power down control for CPU PLL
-                                       ;# OUTDIV | REFDIV | DIV_INT
-       mww 0xb8050010 0x001003e8       ;# CPU PLL Dither FRAC Register
-                                       ;# (disabled?)
-       mww 0xb8050000 0x00818000       ;# Power on | OUTDIV | REFDIV | DIV_INT
-       mww 0xb8050008 0x00008000       ;# remove bypass;
-                                       ;# AHB_POST_DIV - ratio 2
-}
-
-proc ar9331_ddr1_init {} {
-       mww 0xb8000000 0x7fbc8cd0       ;# DDR_CONFIG - lots of DRAM confs
-       mww 0xb8000004 0x9dd0e6a8       ;# DDR_CONFIG2 - more DRAM confs
-
-       mww 0xb8000010 0x8      ;# Forces a PRECHARGE ALL cycle
-       mww 0xb8000008 0x133    ;# mode reg: 0x133 - default
-       mww 0xb8000010 0x1      ;# Forces an MRS update cycl
-       mww 0xb800000c 0x2      ;# Extended mode register value.
-                               ;# default 0x2 - Reset to weak driver, DLL on
-       mww 0xb8000010 0x2      ;# Forces an EMRS update cycle
-       mww 0xb8000010 0x8      ;# Forces a PRECHARGE ALL cycle
-       mww 0xb8000008 0x33     ;# mode reg: remove some bit?
-       mww 0xb8000010 0x1      ;# Forces an MRS update cycl
-       mww 0xb8000014 0x4186   ;# enable refres: bit(14) - set refresh rate
-       mww 0xb800001c 0x8      ;# This register is used along with DQ Lane 0,
-                               ;# DQ[7:0], DQS_0
-       mww 0xb8000020 0x9      ;# This register is used along with DQ Lane 1,
-                               ;# DQ[15:8], DQS_1.
-       mww 0xb8000018 0xff     ;# DDR read and capture bit mask.
-                               ;# Each bit represents a cycle of valid data.
-}
-
 $_TARGETNAME configure -event reset-init {
        ar9331_25mhz_pll_init
        sleep 1

diff --git a/tcl/target/atheros_ar9331.cfg b/tcl/target/atheros_ar9331.cfg
index c5609bb1d35b2f62aa34caa565b69a4215d7cf71..cd6918339176d851f2fa77b029e6bb38a3b448f1 100644 (file)
--- a/tcl/target/atheros_ar9331.cfg
+++ b/tcl/target/atheros_ar9331.cfg
@@ -14,3 +14,37 @@ jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
+
+proc ar9331_25mhz_pll_init {} {
+       mww 0xb8050008 0x00018004       ;# bypass PLL; AHB_POST_DIV - ratio 4
+       mww 0xb8050004 0x00000352       ;# 34000(ns)/40ns(25MHz) = 0x352 (850)
+       mww 0xb8050000 0x40818000       ;# Power down control for CPU PLL
+                                       ;# OUTDIV | REFDIV | DIV_INT
+       mww 0xb8050010 0x001003e8       ;# CPU PLL Dither FRAC Register
+                                       ;# (disabled?)
+       mww 0xb8050000 0x00818000       ;# Power on | OUTDIV | REFDIV | DIV_INT
+       mww 0xb8050008 0x00008000       ;# remove bypass;
+                                       ;# AHB_POST_DIV - ratio 2
+}
+
+proc ar9331_ddr1_init {} {
+       mww 0xb8000000 0x7fbc8cd0       ;# DDR_CONFIG - lots of DRAM confs
+       mww 0xb8000004 0x9dd0e6a8       ;# DDR_CONFIG2 - more DRAM confs
+
+       mww 0xb8000010 0x8      ;# Forces a PRECHARGE ALL cycle
+       mww 0xb8000008 0x133    ;# mode reg: 0x133 - default
+       mww 0xb8000010 0x1      ;# Forces an MRS update cycl
+       mww 0xb800000c 0x2      ;# Extended mode register value.
+                               ;# default 0x2 - Reset to weak driver, DLL on
+       mww 0xb8000010 0x2      ;# Forces an EMRS update cycle
+       mww 0xb8000010 0x8      ;# Forces a PRECHARGE ALL cycle
+       mww 0xb8000008 0x33     ;# mode reg: remove some bit?
+       mww 0xb8000010 0x1      ;# Forces an MRS update cycl
+       mww 0xb8000014 0x4186   ;# enable refres: bit(14) - set refresh rate
+       mww 0xb800001c 0x8      ;# This register is used along with DQ Lane 0,
+                               ;# DQ[7:0], DQS_0
+       mww 0xb8000020 0x9      ;# This register is used along with DQ Lane 1,
+                               ;# DQ[15:8], DQS_1.
+       mww 0xb8000018 0xff     ;# DDR read and capture bit mask.
+                               ;# Each bit represents a cycle of valid data.
+}