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(parent: f18ca51) | patch
armv7a: cache ttbcr and ttb0/1 on debug state entry
authorMatthias Welwarsky <matthias@welwarsky.de>
Sun, 15 Nov 2015 08:18:57 +0000 (09:18 +0100)
committerMatthias Welwarsky <matthias@welwarsky.de>
Sun, 11 Mar 2018 12:08:39 +0000 (12:08 +0000)
commitbfc5c764df145f68835543119865eabe462e19c2
treed48f4c6ee7f86d7823df002eaae7c4ef16fadb1btree | snapshot
parentf18ca510b3430a515f28f19ea6c6731a40022fb6commit | diff
armv7a: cache ttbcr and ttb0/1 on debug state entry

Instead of re-reading ttbcr and ttb0/1 whenever a virt2phys translation
is done, cache the values once when entering debug state. Use the cached
values in armv7a_mmu_translate_va().

Change-Id: I1bc5349ad2f19b2dd75bdd48468a2c1f1e028699
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3112
Tested-by: jenkins
src/target/armv7a.c diff | blob | history
src/target/armv7a.h diff | blob | history
Cloned from https://git.code.sf.net/p/openocd/code