X-Git-Url: https://git.sur5r.net/?p=u-boot;a=blobdiff_plain;f=arch%2Farm%2Fmach-socfpga%2Fmisc.c;h=68eeb292ce7375cd1a49942a593140aea68fa920;hp=fca86507f18beea0cc28ba4ca451a6bf11b1639c;hb=10f9e4b1c86bcc28b1a70ade88b487f639447eec;hpb=8b71e46ceab8b66208107de688cbb4dd25fe38cd

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index fca86507f1..68eeb292ce 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -204,3 +204,35 @@ int socfpga_eth_reset_common(void (*resetfn)(const u8 of_reset_id,
 	return 0;
 }
 #endif
+
+#ifndef CONFIG_SPL_BUILD
+static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc != 2)
+		return CMD_RET_USAGE;
+
+	argv++;
+
+	switch (*argv[0]) {
+	case 'e':	/* Enable */
+		do_bridge_reset(1);
+		break;
+	case 'd':	/* Disable */
+		do_bridge_reset(0);
+		break;
+	default:
+		return CMD_RET_USAGE;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	bridge, 2, 1, do_bridge,
+	"SoCFPGA HPS FPGA bridge control",
+	"enable  - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
+	"bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
+	""
+);
+
+#endif