From: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Date: Tue, 25 Mar 2008 12:30:07 +0000 (+0900)
Subject: [MIPS] Extend MIPS_MAX_CACHE_SIZE upto 64kB
X-Git-Tag: v1.3.3-rc1~171^2~1
X-Git-Url: https://git.sur5r.net/?p=u-boot;a=commitdiff_plain;h=373b16fc0c5ae34d28b9027f809ae3cbf45cdd15

[MIPS] Extend MIPS_MAX_CACHE_SIZE upto 64kB

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
---

diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S
index e6f31751bf..89ada716c3 100644
--- a/cpu/mips/cache.S
+++ b/cpu/mips/cache.S
@@ -1,5 +1,5 @@
 /*
- *  Cache-handling routined for MIPS 4K CPUs
+ *  Cache-handling routined for MIPS CPUs
  *
  *  Copyright (c) 2003	Wolfgang Denk <wd@denx.de>
  *
@@ -32,10 +32,14 @@
 
 #define RA		t8
 
-	/* 16KB is the maximum size of instruction and data caches on
-	 * MIPS 4K.
-	 */
-#define MIPS_MAX_CACHE_SIZE	0x4000
+/*
+ * 16kB is the maximum size of instruction and data caches on MIPS 4K,
+ * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience.
+ *
+ * Note that the above size is the maximum size of primary cache. U-Boot
+ * doesn't have L2 cache support for now.
+ */
+#define MIPS_MAX_CACHE_SIZE	0x10000
 
 #define INDEX_BASE	KSEG0