From: Marek Vasut <marek.vasut+renesas@gmail.com>
Date: Thu, 12 Apr 2018 13:48:54 +0000 (+0200)
Subject: ARM: rmobile: Fix LBSC programming offset on M2 Porter
X-Git-Tag: v2018.05-rc2~11^2~5
X-Git-Url: https://git.sur5r.net/?p=u-boot;a=commitdiff_plain;h=68b83cb76bae38e88cd460ccfb7ee5862d58947f

ARM: rmobile: Fix LBSC programming offset on M2 Porter

The offset of CSWCRx starts at 0x30, fix this.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---

diff --git a/board/renesas/porter/porter_spl.c b/board/renesas/porter/porter_spl.c
index f711aa9c35..4b4dd4d4aa 100644
--- a/board/renesas/porter/porter_spl.c
+++ b/board/renesas/porter/porter_spl.c
@@ -169,8 +169,8 @@ static void tpl_init_lbsc(void)
 	static const struct reg_config lbsc_config[] = {
 		{ 0x00, 0x00000020 },
 		{ 0x08, 0x00002020 },
-		{ 0x10, 0x2a103320 },
-		{ 0x18, 0xff70ff70 },
+		{ 0x30, 0x2a103320 },
+		{ 0x38, 0xff70ff70 },
 	};
 
 	static const u16 lbsc_offs[] = {