From: Alexey Brodkin <abrodkin@synopsys.com>
Date: Wed, 21 Feb 2018 09:58:00 +0000 (+0300)
Subject: arc: Fine-tune implementation of memory barriers
X-Git-Tag: v2018.05-rc1~10^2~21
X-Git-Url: https://git.sur5r.net/?p=u-boot;a=commitdiff_plain;h=71621525c3bf9ed2a73446ba505ad5b980b6b8bb

arc: Fine-tune implementation of memory barriers

We improve on 2 things:
 1. Only ARC HS family has "dmb" instructions so do compile-time
    check for automatically defined macro __ARCHS__.
    Previous check for ARCv2 ISA was not good enough because ARC EM
    family is v2 ISA as well but still "dmb" instaruction is not
    supported in EM family.

 2. Still if there's no dedicated instruction for memory barrier
    let's at least insert compile-time barrier to make sure
    compiler deosn't reorder critical memory operations.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
---

diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h
index a12303bc73..060cdf637b 100644
--- a/arch/arc/include/asm/io.h
+++ b/arch/arc/include/asm/io.h
@@ -10,7 +10,7 @@
 #include <linux/types.h>
 #include <asm/byteorder.h>
 
-#ifdef CONFIG_ISA_ARCV2
+#ifdef __ARCHS__
 
 /*
  * ARCv2 based HS38 cores are in-order issue, but still weakly ordered
@@ -42,12 +42,12 @@
 #define mb()	asm volatile("sync\n" : : : "memory")
 #endif
 
-#ifdef CONFIG_ISA_ARCV2
+#ifdef __ARCHS__
 #define __iormb()		rmb()
 #define __iowmb()		wmb()
 #else
-#define __iormb()		do { } while (0)
-#define __iowmb()		do { } while (0)
+#define __iormb()		asm volatile("" : : : "memory")
+#define __iowmb()		asm volatile("" : : : "memory")
 #endif
 
 static inline void sync(void)