u-boot
2 years agoMerge branch 'master' of git://git.denx.de/u-boot-sunxi master
Tom Rini [Tue, 17 Jul 2018 18:28:47 +0000 (14:28 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-sunxi

2 years agosunxi: Enable eMMC on Libre Computer Board ALL-H3-CC boards
Chen-Yu Tsai [Sat, 14 Jul 2018 13:55:45 +0000 (21:55 +0800)]
sunxi: Enable eMMC on Libre Computer Board ALL-H3-CC boards

The Libretech ALL-H3-CC has a high density connector for attaching
an eMMC module. The module form factor and connection is specific
to Libretech, and has provisions for split vmmc/vqmmc (core and I/O)
voltage supplies, but this board does not wire the vqmmc side. The
H2+/H3/H5 SoCs do not support alternate I/O voltages for eMMC either.
Only 3.3V is supported. A specific module that ties vqmmc to vmmc,
with both at 3.3V, must be used.

Given that a) eMMC is not designed to be hotplugged, b) power is
always provided on the pins, and c) MMC controllers can deal with
missing cards, we can enable this by default. If a module is attached
it will be picked up by the system.

The device tree change was also submitted to the Linux Kernel and
has already been queued up for 4.19.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2 years agoMerge branch 'master' of git://git.denx.de/u-boot-spi
Tom Rini [Mon, 16 Jul 2018 13:13:45 +0000 (09:13 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-spi

2 years agosf: add paired dev info for winbond w25q16jv
Ludwig Zenz [Thu, 5 Jul 2018 07:27:47 +0000 (09:27 +0200)]
sf: add paired dev info for winbond w25q16jv

This commit adds paired dev info for winbond w25q16jv
(tested w25q16jvssiq with a i.mx6 board)

Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2 years agosf: add Macronix mx25l1633e entry
Ludwig Zenz [Thu, 5 Jul 2018 07:27:46 +0000 (09:27 +0200)]
sf: add Macronix mx25l1633e entry

Add support for the Macronix mx25l1633e nor flash. (Tested on a imx6 board)

Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2 years agosf: add Gigadevice gd25q16c entry
Ludwig Zenz [Thu, 5 Jul 2018 07:27:45 +0000 (09:27 +0200)]
sf: add Gigadevice gd25q16c entry

Add support for the Gigadevice gd25q16c nor flash. (Tested on a imx6 board)

Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2 years agospi_flash: add a bunch of winbond flashes to id-table
Hannes Schmelzer [Tue, 26 Jun 2018 21:14:07 +0000 (23:14 +0200)]
spi_flash: add a bunch of winbond flashes to id-table

This commit adds the following flashes to the id-table

- W25Q16JV
- W25Q32JV
- W25Q64JV
- W25Q128JV
- W25Q256JV

Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2 years agozynqmp: zcu102: Add qspi driver support for ZynqMP zcu102 boards
Siva Durga Prasad Paladugu [Wed, 4 Jul 2018 12:01:24 +0000 (17:31 +0530)]
zynqmp: zcu102: Add qspi driver support for ZynqMP zcu102 boards

This patch adds qspi driver support for all ZynqMP ZCU102
boards.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2 years agospi: zynqmp_gqspi: Add support for ZynqMP qspi driver
Siva Durga Prasad Paladugu [Wed, 4 Jul 2018 12:01:23 +0000 (17:31 +0530)]
spi: zynqmp_gqspi: Add support for ZynqMP qspi driver

This patch adds qspi driver support for ZynqMP SoC. This
driver is responsible for communicating with qspi flash
devices.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
[jagan: removed GQSPI_MIO_NUM_ macros]
Reviewed-by: Jagan Teki <jagan@openedev.com>
2 years agospi: xilinx_spi: convert to livetree
Vipul Kumar [Sat, 30 Jun 2018 02:45:20 +0000 (08:15 +0530)]
spi: xilinx_spi: convert to livetree

Update the xilinx spi driver to support a live tree.

Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2 years agospi: xilinx_spi: Added support to read JEDEC-id twice at the boot time
Vipul Kumar [Sat, 30 Jun 2018 02:45:19 +0000 (08:15 +0530)]
spi: xilinx_spi: Added support to read JEDEC-id twice at the boot time

This patch is for the startup block issue in the spi controller.
SPI clock is passing through STARTUP block to FLASH. STARTUP block
don't provide clock as soon as QSPI provides command. So, first
command fails.

This patch added support to read JEDEC id in xilinx_spi_xfer ().

Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2 years agospi: xilinx_spi: Modify transfer logic xilinx_spi_xfer() function
Vipul Kumar [Sat, 30 Jun 2018 02:45:18 +0000 (08:15 +0530)]
spi: xilinx_spi: Modify transfer logic xilinx_spi_xfer() function

This patch modify xilinx_spi_xfer() function and add rxfifo() and
txfifo() functions to add the modularity so that these functions
can be used by other functions within the same file.

This patch also added support to read fifo_size from dts.

Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2 years agospi: xilinx: Read reg base address from DTS file
Michal Simek [Sat, 30 Jun 2018 02:45:17 +0000 (08:15 +0530)]
spi: xilinx: Read reg base address from DTS file

This patch added support to read register base address from DTS file.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2 years agoconfigs: Bananapi_M2_Ultra: enable gigabit ethernet
Lothar Felten [Fri, 13 Jul 2018 08:45:30 +0000 (10:45 +0200)]
configs: Bananapi_M2_Ultra: enable gigabit ethernet

Enable the gigabit ethernet for the Bananapi M2 Ultra board.
Tested on BananaPi M2 Berry (R40), custom board (V40)

Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@openedev.com>
2 years agosunxi: R40: add gigabit ethernet devicetree node
Lothar Felten [Fri, 13 Jul 2018 08:45:29 +0000 (10:45 +0200)]
sunxi: R40: add gigabit ethernet devicetree node

Add a device tree node for the Allwinner R40/V40 GMAC gigabit
ethernet interface.
The R40 SoC does not use the syscon register for GMAC settings.
The gigabit ethernet interface can only be routed to a fixed set of
pins.
Updated to match the Linux kernel's device tree.

Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@openedev.com>
2 years agonet: sun8i-emac: support R40 GMAC
Lothar Felten [Fri, 13 Jul 2018 08:45:28 +0000 (10:45 +0200)]
net: sun8i-emac: support R40 GMAC

Add support for the GMAC found in the Allwinner R40/V40 SoC.

The R40 GMAC interface is not controlled by the syscon register but
has a separate configuration register in the CCU.
The clock gate and reset bits are in a different register compared
to the other SoCs supported by this driver.
The driver uses the -gmac suffix for the R40 because the R40 also
has a different 100 MBit MAC (EMAC).

Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@openedev.com>
2 years agonet: sun8i-emac: set mux and clock by driver data
Lothar Felten [Fri, 13 Jul 2018 08:45:27 +0000 (10:45 +0200)]
net: sun8i-emac: set mux and clock by driver data

Use driver data->variant information to select device specific
pin mux and phy clock settings.

Suggested by Jagan Teki

Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
2 years agonet: sun8i-emac: fix printing NULL character
Lothar Felten [Fri, 13 Jul 2018 08:45:26 +0000 (10:45 +0200)]
net: sun8i-emac: fix printing NULL character

If the variant is not set and therefore NULL, do not attempt to print
the variant.

Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@openedev.com>
2 years agosunxi: R40: add gigabit ethernet clocks
Lothar Felten [Fri, 13 Jul 2018 08:45:25 +0000 (10:45 +0200)]
sunxi: R40: add gigabit ethernet clocks

Add clock control entries for the gigabit interface of the Allwinner
R40/V40 CPU

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
2 years agodm: sunxi: Use DM for MMC and SATA on all A10 boards
Adam Sampson [Sat, 30 Jun 2018 00:02:29 +0000 (01:02 +0100)]
dm: sunxi: Use DM for MMC and SATA on all A10 boards

Use the driver model for MMC and SATA, in preparation for CONFIG_BLK
defaulting to y.

Tested on A10 Cubieboard.

Signed-off-by: Adam Sampson <ats@offog.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2 years agodm: mmc: sunxi: Add A10/A20 compatible strings
Adam Sampson [Sat, 30 Jun 2018 00:02:28 +0000 (01:02 +0100)]
dm: mmc: sunxi: Add A10/A20 compatible strings

Commit dd27918c2252 ("dm: mmc: sunxi: Add support for driver model")
only added the allwinner,sun5i-a13-mmc compatible string for this
driver. The DM initialisation code here also works with (at least) A10
and A20, so add the appropriate compatible strings as per Linux 4.17's
driver.

Tested on A10 Cubieboard and A20 pcDuino3 Nano with CONFIG_DM_MMC.
(A20 worked already, because sun7i-a20.dtsi specifies both the A13 and
A20 strings.)

Signed-off-by: Adam Sampson <ats@offog.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2 years agosunxi: DT: A64: add proper SoPine baseboard device tree
Andre Przywara [Wed, 4 Jul 2018 13:16:39 +0000 (14:16 +0100)]
sunxi: DT: A64: add proper SoPine baseboard device tree

When the defconfig for the SoPine baseboard was added, there wasn't any
proper DT for the board yet, so we used the Pine64 DT as a placeholder.
Copy the DT file(s) meanwhile added in Linux over to U-Boot, and use
them in our defconfig.
This is as of v4.18-rc3, exactly Linux commit:
commit 7d556bfc49adddf2beb0d16c91945c3b8b783282
Author: Jagan Teki <jagannadh.teki@gmail.com>
Date:   Mon Dec 4 10:23:07 2017 +0530

    arm64: allwinner: a64-sopine: Fix to use dcdc1 regulator instead of vcc3v3

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2 years agosunxi: DT: H3: update board .dts files from Linux
Andre Przywara [Wed, 4 Jul 2018 13:16:38 +0000 (14:16 +0100)]
sunxi: DT: H3: update board .dts files from Linux

Update the .dts file for the various boards with an Allwinner H3 SoC.
This is as of v4.18-rc3, exactly Linux commit:
commit 721afaa2aeb860067decdddadc84ed16f42f2048 (HEAD)
Merge: 7c00e8ae041b 87815dda5593
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date:   Mon Jun 11 17:57:38 2018 -0700

    Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

This also includes the OrangePi Zero .dts, which technically has an
Allwinner H2+ SoC.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2 years agosunxi: DT: H5: update board .dts files from Linux
Andre Przywara [Wed, 4 Jul 2018 13:16:37 +0000 (14:16 +0100)]
sunxi: DT: H5: update board .dts files from Linux

Update the .dts file for the various boards with an Allwinner H5 SoC.
This is as of v4.18-rc3, exactly Linux commit:
commit af5d05bdc99c211729cba0a3d5417bccfa308caf
Author: Neil Armstrong <narmstrong@baylibre.com>
Date:   Tue Apr 24 13:47:14 2018 +0200

    arm64: dts: allwinner: Add dts file for Libre Computer Board ALL-H3-CC H5 ver.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2 years agosunxi: DT: update device tree files for Allwinner H3 and H5 SoCs
Andre Przywara [Wed, 4 Jul 2018 13:16:36 +0000 (14:16 +0100)]
sunxi: DT: update device tree files for Allwinner H3 and H5 SoCs

Update the device tree files from the Linux tree as of v4.18-rc3,
exactly Linux commit:
commit 55c5ba5e49a0a124ed416880e8227b493474495e
Author: Chen-Yu Tsai <wens@csie.org>
Date:   Tue Apr 24 19:34:22 2018 +0800

    arm64: dts: allwinner: h5: Add cpu0 label for first cpu

Since the H3 and H5 are very similar (aside from the actual ARM cores),
they share most the SoC .dtsi and thus have to be updated together.
One tiny change is the removal of the "arm/" prefix from the include
path in the sun50i-h5.dtsi, which is needed because we don't share the
same sophisticated DT directory layout of Linux.
Also we need to fix up the board .dts files already, since the .dtsi
removes some pins, so the .dts can't reference them anymore. This is to
maintain bisectability.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2 years agosunxi: DT: A64: update board .dts files from Linux
Andre Przywara [Wed, 4 Jul 2018 13:16:35 +0000 (14:16 +0100)]
sunxi: DT: A64: update board .dts files from Linux

Update the .dts files for the various boards with an Allwinner A64 SoC.
This is as of v4.18-rc3, exactly Linux commit:
commit 818668055c9d588c9a9d151e3b258ed1adacba0b
Author: Jagan Teki <jagan@amarulasolutions.com>
Date:   Mon Apr 23 12:02:39 2018 +0530

    arm64: dts: allwinner: a64: bananapi-m64: add usb otg

It updates the existing DT files, adds the newly added axp803.dtsi and
removes our temporary kludge file to get Ethernet support in U-Boot.
I left the amarula-relic alone, as this DT has not reached mainline yet.
The changes are not critical anyway, and the next sync will fix this.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2 years agosunxi: DT: A64: update device tree file for Allwinner A64 SoC
Andre Przywara [Wed, 4 Jul 2018 13:16:34 +0000 (14:16 +0100)]
sunxi: DT: A64: update device tree file for Allwinner A64 SoC

Updates the device tree file from the the Linux tree as of v4.18-rc3,
exactly Linux commit:
commit c1cff65f9b16b31e731e2e75bbe06638c86e1996
Author: Harald Geyer <harald@ccbib.org>
Date:   Thu Mar 15 16:25:08 2018 +0000

    arm64: dts: allwinner: a64: add simplefb for A64 SoC

This also pulls in the newly required include files for the clock and
reset bindings, also removes the now redundant part from our
*-u-boot.dtsi overlay file.
I kept the PWM node from U-Boot, as we recently gained this explicitly
for U-Boot's own usage and I don't want to regress here. This node is in
the queue for mainline Linux already, so the next sync will make it all
equal again.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2 years agomach-stm32: Rename CONFIG_SPL_RESET_SUPPORT to CONFIG_SPL_DM_RESET
Ley Foon Tan [Wed, 11 Jul 2018 09:56:57 +0000 (17:56 +0800)]
mach-stm32: Rename CONFIG_SPL_RESET_SUPPORT to CONFIG_SPL_DM_RESET

CONFIG_SPL_RESET_SUPPORT has been renamed to CONFIG_SPL_DM_RESET, update
this Kconfig file.

Fixes: bfc6bae8fa1f ("reset: Rename CONFIG_SPL_RESET_SUPPORT to CONFIG_SPL_DM_RESET")
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2 years agoMerge branch 'master' of git://git.denx.de/u-boot-socfpga
Tom Rini [Fri, 13 Jul 2018 13:05:05 +0000 (09:05 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-socfpga

- Update SPDX tag in arch/arm/mach-socfpga/spl_a10.c

Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agoMerge branch 'master' of git://git.denx.de/u-boot-i2c
Tom Rini [Thu, 12 Jul 2018 14:35:33 +0000 (10:35 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-i2c

2 years agoarm: socfpga: Fixes: include <debug_uart.h>
Ley Foon Tan [Thu, 12 Jul 2018 13:44:24 +0000 (21:44 +0800)]
arm: socfpga: Fixes: include <debug_uart.h>

Fix compilation warning when enable CONFIG_DEBUG_UART.

arch/arm/mach-socfpga/spl_s10.c: In function ‘board_init_f’:
arch/arm/mach-socfpga/spl_s10.c:146:2: warning: implicit declaration of function ‘debug_uart_init’; did you mean ‘part_init’? [-Wimplicit-function-declaration]
  debug_uart_init();

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2 years agoarm: socfpga: Fix: Compile MCR instruction on ARM 32-bit only
Ley Foon Tan [Thu, 12 Jul 2018 11:13:34 +0000 (19:13 +0800)]
arm: socfpga: Fix: Compile MCR instruction on ARM 32-bit only

MCR instruction only available in ARM 32-bit. So, compile MCR instruction
when ARM 32-bit is enabled.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2 years agoarm: dts: socfpga: stratix10: Fix memory node
Ley Foon Tan [Thu, 12 Jul 2018 11:13:33 +0000 (19:13 +0800)]
arm: dts: socfpga: stratix10: Fix memory node

Commit 5dfd5607af2114047bd ("ARM: socfpga: Pull DRAM size from DT") get
memory size from DT. So, we need to update memory size in memory node.
Otherwise, it cause U-boot hang.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2 years agoMerge branch 'master' of git://git.denx.de/u-boot-ubi
Tom Rini [Thu, 12 Jul 2018 13:47:39 +0000 (09:47 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-ubi

2 years agolpi2c: Add bus busy error handling
Ye Li [Sun, 8 Jul 2018 03:46:43 +0000 (11:46 +0800)]
lpi2c: Add bus busy error handling

When doing "i2c dev 4; i2c probe" with ENET daughter card connected
on iMX8QXP MEK board, we met a i2c bus busy issue, that the BBF of
lpi2c always show busy, but the master is idle, and stop is detected
(SDF set).

This patch addes a handling to re-init the lpi2c master for this
case. Then the issue can be worked around.

Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2 years agolpi2c: Fix bus stop problem in xfer
Ye Li [Sun, 8 Jul 2018 03:46:42 +0000 (11:46 +0800)]
lpi2c: Fix bus stop problem in xfer

In xfer function, both bus_i2c_read and bus_i2c_write will
send a STOP command.  This causes a problem when reading register
data from i2c device.

Generally two operations comprise the register data reading:
   1. Write the register address to i2c device.
      START | chip_addr | W | ACK | register_addr | ACK |

   2. Read the Data from i2c device.
      START | chip_addr | R | ACK | DATA          | NACK | STOP

The STOP command should happen at the end of the transfer, otherwise
we will always get data from register address 0

Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2 years agoimx: lpi2c: fix clock issue when NACK detected
Gao Pan [Sun, 8 Jul 2018 03:46:41 +0000 (11:46 +0800)]
imx: lpi2c: fix clock issue when NACK detected

For LPI2C IP, NACK is detected by the rising edge of the ninth clock.
In current uboot driver, once NACK is detected, it will reset and then
disable LPI2C master. As a result, we can never see the falling edge
of the ninth clock.

Signed-off-by: Gao Pan <pandy.gao@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2 years agoimx_lpi2c: Update lpi2c driver to support imx8
Ye Li [Sun, 8 Jul 2018 03:46:40 +0000 (11:46 +0800)]
imx_lpi2c: Update lpi2c driver to support imx8

Add compatible string for i.MX8 and move imx_lpi2c.h from mx7ulp directory
to u-boot include directory as a common header file.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2 years agoARM: socfpga: Assure correct ACTLR configuration
Marek Vasut [Tue, 29 May 2018 14:16:46 +0000 (16:16 +0200)]
ARM: socfpga: Assure correct ACTLR configuration

Make sure the ARM ACTLR register has correct configuration, otherwise
the Linux kernel refuses to boot. In particular, the "Write Full Line
of Zeroes" bit must be cleared.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2 years agoARM: socfpga: Make DRAM node available in SPL
Marek Vasut [Tue, 29 May 2018 16:02:22 +0000 (18:02 +0200)]
ARM: socfpga: Make DRAM node available in SPL

The SPL can also parse the DRAM configuration node to figure out the
memory layout, make sure it is available.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2 years agoARM: socfpga: Pull DRAM size from DT
Marek Vasut [Mon, 28 May 2018 15:09:45 +0000 (17:09 +0200)]
ARM: socfpga: Pull DRAM size from DT

Pull the DRAM size from DT instead of hardcoding it into U-Boot.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2 years agoddr: altera: Add ECC DRAM scrubbing support for Arria10
Marek Vasut [Mon, 28 May 2018 15:22:47 +0000 (17:22 +0200)]
ddr: altera: Add ECC DRAM scrubbing support for Arria10

The SDRAM must first be rewritten by zeroes if ECC is used to initialize
the ECC metadata. Make the CPU overwrite the DRAM with zeroes in such a
case. This scrubbing implementation turns the caches on temporarily, then
overwrites the whole RAM with zeroes, flushes the caches and turns them
off again. This provides satisfactory performance.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2 years agoddr: altera: Drop custom dram_bank_mmu_setup() on Arria10
Marek Vasut [Tue, 29 May 2018 16:04:15 +0000 (18:04 +0200)]
ddr: altera: Drop custom dram_bank_mmu_setup() on Arria10

This function was never used in SPL and the default implementation of
dram_bank_mmu_setup() does the same thing. The only difference is the
part which configures OCRAM as cachable, which doesn't really work as
it covers more than the OCRAM.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
2 years agoarm: socfpga: Add do_bridge_reset for Arria 10
Ley Foon Tan [Fri, 1 Jun 2018 08:13:19 +0000 (16:13 +0800)]
arm: socfpga: Add do_bridge_reset for Arria 10

Add do_bridge_reset() function for Arria 10, it is required by misc.c.

arch/arm/mach-socfpga/built-in.o: In function `do_bridge':
arch/arm/mach-socfpga/misc.c:221: undefined reference to `do_bridge_reset'
make[1]: *** [u-boot] Error 1

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2 years agoarm: socfpga: stratix10: Enable Stratix10 SoC build
Ley Foon Tan [Wed, 23 May 2018 16:17:32 +0000 (00:17 +0800)]
arm: socfpga: stratix10: Enable Stratix10 SoC build

Add build support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Conflicts:

arch/arm/Kconfig
arch/arm/mach-socfpga/Kconfig

2 years agoboard: altera: stratix10: Add socdk board support for Stratix10 SoC
Ley Foon Tan [Wed, 23 May 2018 16:17:31 +0000 (00:17 +0800)]
board: altera: stratix10: Add socdk board support for Stratix10 SoC

Add socdk board support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2 years agoddr: altera: stratix10: Add DDR support for Stratix10 SoC
Ley Foon Tan [Wed, 23 May 2018 16:17:30 +0000 (00:17 +0800)]
ddr: altera: stratix10: Add DDR support for Stratix10 SoC

Add DDR support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2 years agoarm: socfpga: stratix10: Add timer support for Stratix10 SoC
Ley Foon Tan [Wed, 23 May 2018 16:17:29 +0000 (00:17 +0800)]
arm: socfpga: stratix10: Add timer support for Stratix10 SoC

Add timer support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2 years agoarm: socfpga: stratix10: Add SPL driver for Stratix10 SoC
Ley Foon Tan [Wed, 23 May 2018 16:17:28 +0000 (00:17 +0800)]
arm: socfpga: stratix10: Add SPL driver for Stratix10 SoC

Add SPL driver support for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2 years agoarm: socfpga: Restructure the SPL file
Ley Foon Tan [Wed, 23 May 2018 16:17:27 +0000 (00:17 +0800)]
arm: socfpga: Restructure the SPL file

Restructure the SPL so each devices such as CV, A10 and S10
will have their own dedicated SPL file. SPL file determine
the HW initialization flow which is device specific

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2 years agoarm: socfpga: stratix10: Add MMU support for Stratix10 SoC
Ley Foon Tan [Wed, 23 May 2018 16:17:26 +0000 (00:17 +0800)]
arm: socfpga: stratix10: Add MMU support for Stratix10 SoC

Add MMU memory mapping table for Stratix SoC.

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Acked-by: Marek Vasut <marex@denx.de>
2 years agoarm: socfpga: stratix10: Add mailbox support for Stratix10 SoC
Ley Foon Tan [Wed, 23 May 2018 16:17:25 +0000 (00:17 +0800)]
arm: socfpga: stratix10: Add mailbox support for Stratix10 SoC

Add mailbox support for Stratix SoC

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2 years agoarm: socfpga: stratix10: Add misc support for Stratix10 SoC
Ley Foon Tan [Wed, 23 May 2018 16:17:24 +0000 (00:17 +0800)]
arm: socfpga: stratix10: Add misc support for Stratix10 SoC

Add misc support such as EMAC and cpu info printout for Stratix SoC

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2 years agoarm: socfpga: misc: Move bridge command to misc common
Ley Foon Tan [Wed, 23 May 2018 16:17:23 +0000 (00:17 +0800)]
arm: socfpga: misc: Move bridge command to misc common

Move bridge command to misc common driver, in preparation to used by
other platforms.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2 years agospi: cadence_qspi: Fix warning cast from pointer to integer of different size
Ley Foon Tan [Fri, 1 Jun 2018 08:52:20 +0000 (16:52 +0800)]
spi: cadence_qspi: Fix warning cast from pointer to integer of different size

Use "%p" to print cmdbuf.

Compilation warning as below:

  CC      spl/drivers/spi/cadence_qspi_apb.o
  LD      spl/lib/built-in.o
drivers/spi/cadence_qspi_apb.c: In function ‘cadence_qspi_apb_indirect_write_setup’:
drivers/spi/cadence_qspi_apb.c:696:18: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
          cmdlen, (unsigned int)cmdbuf);

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Acked-by: Marek Vasut <marex@denx.de>
2 years agospi: cadence_qspi: Fix compilation warning
Ley Foon Tan [Fri, 6 Jul 2018 02:39:14 +0000 (10:39 +0800)]
spi: cadence_qspi: Fix compilation warning

Use "%zu" for size_t data type.

Compilation warning as below:

In file included from include/linux/bug.h:7:0,
                 from include/common.h:26,
                 from drivers/spi/cadence_qspi.c:8:
drivers/spi/cadence_qspi.c: In function ‘cadence_spi_xfer’:
drivers/spi/cadence_qspi.c:211:8: warning: format ‘%d’ expects argument of type ‘int’, but argument 3 has type ‘size_t {aka long unsigned int}’ [-Wformat=]
  debug("%s: len=%d [bytes]\n", __func__, data_bytes);
        ^
include/linux/printk.h:37:21: note: in definition of macro ‘pr_fmt’
 #define pr_fmt(fmt) fmt
                     ^~~
include/log.h:142:2: note: in expansion of macro ‘debug_cond’
  debug_cond(_DEBUG, fmt, ##args)
  ^~~~~~~~~~
drivers/spi/cadence_qspi.c:211:2: note: in expansion of macro ‘debug’
  debug("%s: len=%d [bytes]\n", __func__, data_bytes);

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Acked-by: Marek Vasut <marex@denx.de>
2 years agoubifs: remove useless code
Christophe Kerello [Wed, 27 Jun 2018 08:06:59 +0000 (10:06 +0200)]
ubifs: remove useless code

By checking ubifs source code, s_instances parameter is not
used anymore. So, set this parameter and the associated source
code under __UBOOT__ compilation.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2 years agocmd: ubi: Add additional message upon UBI attach error
Stefan Roese [Tue, 26 Jun 2018 06:12:32 +0000 (08:12 +0200)]
cmd: ubi: Add additional message upon UBI attach error

When trying to attach an UBI MTD partition via "ubi part", it may happen
that the MTD partition defined in U-Boot (via mtdparts) is not big
enough than the one, where the UBI device has been created on. This
may lead to errors, which are not really descriptive to debug and
solve this issue, like:

ubi0 error: vtbl_check: too large reserved_pebs 1982, good PEBs 1020
ubi0 error: vtbl_check: volume table check failed: record 0, error 9

or:

ubi0 error: init_volumes: not enough PEBs, required 1738, available 1020
ubi0 error: ubi_wl_init: no enough physical eraseblocks (-718, need 1)
ubi0 error: ubi_attach_mtd_dev: failed to attach mtd1, error -12

Lets add an additional message upon attach failure, to aid the U-Boot
user to solve this problem.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Heiko Schocher <hs@denx.de>
2 years agocmd: ubi: print load size after establishing volume size
Stefan Agner [Mon, 25 Jun 2018 09:19:12 +0000 (11:19 +0200)]
cmd: ubi: print load size after establishing volume size

When using static volumes, the file size stored in the volume is
determined at runtime. Currently the ubi command prints the file
size specified on the console, which leads to a rather confusing
series of messages:
  # ubi read ${fdt_addr_r} testvol
  Read 0 bytes from volume testvol to 82000000
  No size specified -> Using max size (179924992)

Make sure to print the actual size read in any case:
  # ubi read ${fdt_addr_r} testvol
  No size specified -> Using max size (179924992)
  Read 179924992 bytes from volume testvol to 82000000

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2 years agoMerge branch 'master' of git://git.denx.de/u-boot-mips
Tom Rini [Thu, 12 Jul 2018 01:55:20 +0000 (21:55 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-mips

2 years agoMerge git://git.denx.de/u-boot-dm
Tom Rini [Wed, 11 Jul 2018 13:40:38 +0000 (09:40 -0400)]
Merge git://git.denx.de/u-boot-dm

2 years agoled: bcm6328: read base address in the parent node
Philippe Reynes [Thu, 28 Jun 2018 13:26:16 +0000 (15:26 +0200)]
led: bcm6328: read base address in the parent node

In the device tree, the address for the led is located
in the parent node (for exemple leds), not in the led node
(for exemple led@0).

The commit "led: bcm6328: convert to use live dt"
(sha1: 899455176058d673887a762aa38853188a030af4)
change this behaviour and read the address in the led node.

We fix this by reading the base address for led
in the parent node.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2 years agocpu: bmips: fix probe to get the address
Philippe Reynes [Fri, 22 Jun 2018 16:52:05 +0000 (18:52 +0200)]
cpu: bmips: fix probe to get the address

In the device tree, the address for cpu is located in
the node "cpus", not in the cpu node (for exemple cpu@0).
So when probing cpu, the cpu address must be read in the
cpu parent.

The commit "cpu: bmips: convert to use live dt"
(sha1: c444afbbefa103d567f197393d39ec0fcca21a0c)
change this behaviour and read the address in the
cpu node when probing cpu.

We fix this by reading the address in the cpu parent.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2 years agoMIPS: add MIPS Release 6 build coverage for Boston boards
Daniel Schwierzeck [Fri, 1 Jun 2018 09:57:37 +0000 (11:57 +0200)]
MIPS: add MIPS Release 6 build coverage for Boston boards

Now that Travis CI is building with gcc-7.3.0, we can add
build coverage for all combinations of MIPS Release 6
instruction sets (MIPS32, MIPS64, Big Endian, Little Endian).

Add mew default configs for Boston board for all MIPS Release 6
variants.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2 years agoMakefile: drop mention of *.cfgtmp
Baruch Siach [Thu, 21 Jun 2018 06:03:00 +0000 (09:03 +0300)]
Makefile: drop mention of *.cfgtmp

Since commit f916757300 (imx: Create distinct pre-processed mkimage
config files), *.cfgtmp files are no longer generated. There is no need
to remove them on the 'clean' target anymore.

Rename the .gitignore glob to *.cfgout.

Cc: Trent Piepho <tpiepho@impinj.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
2 years agomkimage: fit_image: Add support for SOURCE_DATE_EPOCH in signatures
Alex Kiernan [Wed, 20 Jun 2018 20:10:52 +0000 (20:10 +0000)]
mkimage: fit_image: Add support for SOURCE_DATE_EPOCH in signatures

When generating timestamps in signatures, use imagetool_get_source_date()
so we can be overridden by SOURCE_DATE_EPOCH to generate reproducible
images.

Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Reviewed-by: Simon Glass <sjg@chromum.org>
2 years agomkimage: Refactor imagetool_get_source_date to take command name
Alex Kiernan [Wed, 20 Jun 2018 20:10:51 +0000 (20:10 +0000)]
mkimage: Refactor imagetool_get_source_date to take command name

So we can use imagetool_get_source_date() from callers who do not have
the image tool params struct, just pass in the command name for the error
message.

Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Reviewed-by: Simon Glass <sjg@chromum.org>
2 years agocommon/memsize.c: Increase save array for supporting memory size > 4GB
Tien Fong Chee [Wed, 20 Jun 2018 07:06:20 +0000 (15:06 +0800)]
common/memsize.c: Increase save array for supporting memory size > 4GB

In ARM 64-bits, memory size can be supported is more than 4GB,
hence increasing save array is needed to cope with testing larger memory.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2 years agocmd: Kconfig: Move CONFIG_MP to Kconfig
Siva Durga Prasad Paladugu [Tue, 19 Jun 2018 10:24:23 +0000 (12:24 +0200)]
cmd: Kconfig: Move CONFIG_MP to Kconfig

This patch moves CONFIG_MP to Kconfig

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2 years agoMakefile: drop unused cpp_cfg macro
Baruch Siach [Mon, 18 Jun 2018 04:59:25 +0000 (07:59 +0300)]
Makefile: drop unused cpp_cfg macro

Commit e19b0fb4851f (kbuild: generate u-boot.cfg as a byproduct of
include/autoconf.mk) removed the use of the cpp_cfg macro in Makefile,
but forgot to remove its definition.

Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2 years agoomap3_logic: Change console from ttyO0 to ttyS0
Adam Ford [Fri, 15 Jun 2018 13:12:02 +0000 (08:12 -0500)]
omap3_logic: Change console from ttyO0 to ttyS0

Newer kernels have moved from ttyO0 to ttyS0, and when booting
it drops a notice:

  WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
  This ensures that you still see kernel messages. Please
  update your kernel commandline.

This patch updates the console to use ttyS0 and eliminate the
chatter.

Signed-off-by: Adam Ford <aford173@gmail.com>
2 years agocommon: print \n in initr_scsi()
Heinrich Schuchardt [Fri, 15 Jun 2018 05:01:26 +0000 (07:01 +0200)]
common: print \n in initr_scsi()

Typically init_scsi() does not output anything. So initr_scsi() should
provide a \n or we may see borked output like

SCSI:  Net:   No ethernet found.

as observed with sandbox_defconfig.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2 years agogpio: omap_gpio: Convert to auto-alloc feature when DT is supported
Adam Ford [Sun, 10 Jun 2018 14:29:51 +0000 (09:29 -0500)]
gpio: omap_gpio: Convert to auto-alloc feature when DT is supported

The omap_gpio driver has a TODO that says when every board is converted
to DM and DT, the omap_gpio_bind can stop using calloc and switch
to auto-alloc.

This patch converts this driver to auto-calloc when DT is enabled.

Signed-off-by: Adam Ford <aford173@gmail.com>
2 years agovboot: Do not use hashed-strings offset
Teddy Reed [Sat, 9 Jun 2018 15:45:20 +0000 (11:45 -0400)]
vboot: Do not use hashed-strings offset

The hashed-strings signature property includes two uint32_t values.
The first is unneeded as there should never be a start offset into the
strings region. The second, the size, is needed because the added
signature node appends to this region.

See tools/image-host.c, where a static 0 value is used for the offset.

Signed-off-by: Teddy Reed <teddy.reed@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2 years agovboot: Add FIT_SIGNATURE_MAX_SIZE protection
Teddy Reed [Sat, 9 Jun 2018 15:38:05 +0000 (11:38 -0400)]
vboot: Add FIT_SIGNATURE_MAX_SIZE protection

This adds a new config value FIT_SIGNATURE_MAX_SIZE, which controls the
max size of a FIT header's totalsize field. The field is checked before
signature checks are applied to protect from reading past the intended
FIT regions.

This field is not part of the vboot signature so it should be sanity
checked. If the field is corrupted then the structure or string region
reads may have unintended behavior, such as reading from device memory.
A default value of 256MB is set and intended to support most max storage
sizes.

Suggested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Teddy Reed <teddy.reed@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2 years agoboard: arm: Add support for Broadcom BCM7445
Thomas Fitzsimmons [Fri, 8 Jun 2018 21:59:45 +0000 (17:59 -0400)]
board: arm: Add support for Broadcom BCM7445

Add support for loading U-Boot on the Broadcom 7445 SoC.  This port
assumes Broadcom's BOLT bootloader is acting as the second stage
bootloader, and U-Boot is acting as the third stage bootloader, loaded
as an ELF program by BOLT.

Signed-off-by: Thomas Fitzsimmons <fitzsim@fitzsim.org>
Cc: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
2 years agospl: fit: verify images prior to post processing
Ben Whitten [Thu, 7 Jun 2018 10:37:27 +0000 (11:37 +0100)]
spl: fit: verify images prior to post processing

Verification of hashes needs to take place before any image post
processing, thus matching full FIT image processing.
This allows mechanisms such as encryption be applied to images
prior to fit generation at the spl level.

Signed-off-by: Ben Whitten <ben.whitten@lairdtech.com>
2 years agoconfigs: Remove empty #ifdef/#ifndef blocks from configs
Alex Kiernan [Sat, 2 Jun 2018 05:42:55 +0000 (05:42 +0000)]
configs: Remove empty #ifdef/#ifndef blocks from configs

Remove empty #ifdef/#ifndef..#endif blocks where the configuration they
guarded has been completely removed.

Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
2 years agospl: fit: Fix support for loading FPGA bitstream
Marek Vasut [Fri, 1 Jun 2018 21:19:29 +0000 (23:19 +0200)]
spl: fit: Fix support for loading FPGA bitstream

Move the FPGA loading from IS_ENABLED(CONFIG_SPL_OS_BOOT) &&
IS_ENABLED(CONFIG_SPL_GZIP) conditional. The FPGA loading can
be used without OS loading and GZIP support in SPL. This issue
was most likely induced by some merge conflict, so fix it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
2 years agospl: spi: Support full fitImage handling
Marek Vasut [Thu, 31 May 2018 15:59:29 +0000 (17:59 +0200)]
spl: spi: Support full fitImage handling

Handle the case where the full fitImage support is enabled. In this
case, the whole fitImage must be loaded up front as some parts of the
fitImage code require memory-mapped access to the entire fitImage.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
2 years agospl: fat: Support full fitImage handling
Marek Vasut [Thu, 31 May 2018 15:59:19 +0000 (17:59 +0200)]
spl: fat: Support full fitImage handling

Handle the case where the full fitImage support is enabled. In this
case, the whole fitImage must be loaded up front as some parts of the
fitImage code require memory-mapped access to the entire fitImage.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
2 years agofit: Verify all configuration signatures
Marek Vasut [Thu, 31 May 2018 15:59:07 +0000 (17:59 +0200)]
fit: Verify all configuration signatures

Rather than verifying configuration signature of the configuration node
containing the kernel image types, verify all configuration nodes, even
those that do not contain kernel images. This is useful when the nodes
contain ie. standalone OSes or U-Boot.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2 years agotest/py: vboot: Remove stderr redirect from openssl command
Paul Burton [Thu, 14 Sep 2017 21:34:50 +0000 (14:34 -0700)]
test/py: vboot: Remove stderr redirect from openssl command

The openssl command specified in test_with_algo() ultimately ends up
being run by RunAndLog::run(), which uses it to construct a Popen object
with the default shell=False. The stderr redirect in the command is
therefore simply passed to openssl as an argument. With at least openssl
1.1.0f this causes openssl, and therefore test_vboot, to fail with:

  genpkey: Use -help for summary.
  Exit code: 1

Any stderr output ought to be captured & stored in the RunAndLog
object's output field and returned from run() via run_and_log() to
test_with_algo() which then ignores it anyway, so we can drop the
shell-like redirection with no ill effects. With this fix test_vboot now
passes for me.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2 years agotest/py: hush_if_test: Use open() in place of file()
Paul Burton [Thu, 14 Sep 2017 21:34:49 +0000 (14:34 -0700)]
test/py: hush_if_test: Use open() in place of file()

In python 3.x the file() function has been removed. Use open() instead,
which works on both python 2.x & 3.x, and is described as the preferred
method of opening a file by python 2.x documentation anyway.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2 years agotest/py: fit: Open files as binary files
Paul Burton [Thu, 14 Sep 2017 21:34:48 +0000 (14:34 -0700)]
test/py: fit: Open files as binary files

The read_file() function in test_fit is used with files that are not
text files, as well as some that are. It is never used in a way that
requires it to decode text files to characters, so open all files in
binary mode such that read() doesn't attempt to decode characters for
files which are not text files.

Without this test_fit fails on python 3.x when reading an FDT in
run_fit_test() with:

  UnicodeDecodeError: 'utf-8' codec can't decode byte 0xd0 in position
                       0: invalid continuation byte

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2 years agotest/py: Import 'configparser' lower case to be python 3.x safe
Paul Burton [Thu, 14 Sep 2017 21:34:45 +0000 (14:34 -0700)]
test/py: Import 'configparser' lower case to be python 3.x safe

In python 3.x the configparser module is named with all lower case.
Import it as such in order to avoid errors when running on python 3.x,
and fall back to the CamelCase version in order to keep working with
python 2.x.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2 years agotest/py: Use range() rather than xrange()
Paul Burton [Thu, 14 Sep 2017 21:34:44 +0000 (14:34 -0700)]
test/py: Use range() rather than xrange()

In python 3.x the xrange() function has been removed, and range()
returns an iterator much like Python 2.x's xrange(). Simply use range()
in place of xrange() in order to work on both python 2.x & 3.x. This
will mean a small cost on python 2.x since range() will return a list
there rather than an iterator, but the cost should be negligible.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2 years agotest/py: Make print statements python 3.x safe
Paul Burton [Thu, 14 Sep 2017 21:34:43 +0000 (14:34 -0700)]
test/py: Make print statements python 3.x safe

In python 3.x print must be called as a function rather than used as a
statement. Update uses of print to the function call syntax in order to
be python 3.x safe.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2 years agoMerge git://git.denx.de/u-boot-dm
Tom Rini [Tue, 10 Jul 2018 14:29:14 +0000 (10:29 -0400)]
Merge git://git.denx.de/u-boot-dm

2 years agonet: designware: Add reset ctrl to driver
Ley Foon Tan [Thu, 14 Jun 2018 10:45:23 +0000 (18:45 +0800)]
net: designware: Add reset ctrl to driver

Add code to reset all reset signals as in Ethernet DT node. A reset
property is an optional feature, so only print out a warning and do not
fail if a reset property is not present.

If a reset property is discovered, then use it to deassert, thus
bringing the IP out of reset.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2 years agoserial: ns16550: Add reset ctrl to driver
Ley Foon Tan [Thu, 14 Jun 2018 10:45:22 +0000 (18:45 +0800)]
serial: ns16550: Add reset ctrl to driver

Add code to reset all reset signals as in serial DT node. A reset
property is an optional feature, so do not fail if a reset property is
not present.

If a reset property is discovered, then use it to deassert, thus
bringing the IP out of reset.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2 years agommc: dwmmc: socfpga: Add reset ctrl to driver
Ley Foon Tan [Thu, 14 Jun 2018 10:45:21 +0000 (18:45 +0800)]
mmc: dwmmc: socfpga: Add reset ctrl to driver

Add code to reset all reset signals as in mmc DT node. A reset property
is an optional feature, so only print out a warning and do not fail if a
reset property is not present.

If a reset property is discovered, then use it to deassert, thus
bringing the IP out of reset.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2 years agoinclude: reset: Change to use CONFIG_IS_ENABLED(DM_RESET)
Ley Foon Tan [Thu, 14 Jun 2018 10:45:20 +0000 (18:45 +0800)]
include: reset: Change to use CONFIG_IS_ENABLED(DM_RESET)

Change to use CONFIG_IS_ENABLED(DM_RESET), so this can work in SPL
build (CONFIG_SPL_DM_RESET) and U-boot build (CONFIG_DM_RESET).

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2 years agoreset: Rename CONFIG_SPL_RESET_SUPPORT to CONFIG_SPL_DM_RESET
Ley Foon Tan [Thu, 14 Jun 2018 10:45:19 +0000 (18:45 +0800)]
reset: Rename CONFIG_SPL_RESET_SUPPORT to CONFIG_SPL_DM_RESET

Rename CONFIG_SPL_RESET_SUPPORT to CONFIG_SPL_DM_RESET, so can use
CONFIG_IS_ENABLED(DM_RESET) checking in reset.h later.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2 years agoMAINTAINERS: Add entries for Actions Semi OWL family
Manivannan Sadhasivam [Thu, 14 Jun 2018 18:08:39 +0000 (23:38 +0530)]
MAINTAINERS: Add entries for Actions Semi OWL family

Add myself as the Maintainer for Actions Semi OWL family and its
relevant board, drivers.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2 years agoserial: Add Actions Semi OWL UART support
Manivannan Sadhasivam [Thu, 14 Jun 2018 18:08:38 +0000 (23:38 +0530)]
serial: Add Actions Semi OWL UART support

This commit adds Actions Semi OWL family UART support. This driver
relies on baudrate configured by primary bootloaders.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2 years agoarm: dts: bubblegum_96: Enable UART5 for serial console
Manivannan Sadhasivam [Thu, 14 Jun 2018 18:08:37 +0000 (23:38 +0530)]
arm: dts: bubblegum_96: Enable UART5 for serial console

This commit enables UART5 found in S900 SoC for serial console support.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2 years agoarm: dts: s900: Add UART node
Manivannan Sadhasivam [Thu, 14 Jun 2018 18:08:36 +0000 (23:38 +0530)]
arm: dts: s900: Add UART node

This commit adds UART node for Actions Semi S900 SoC.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2 years agoclk: Add Actions Semi OWL clock support
Manivannan Sadhasivam [Thu, 14 Jun 2018 18:08:35 +0000 (23:38 +0530)]
clk: Add Actions Semi OWL clock support

This commit adds Actions Semi OWL family base clock and S900 SoC
specific clock support. For S900 peripheral clock support, only UART
clock has been added for now.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2 years agoarm: dts: s900: Add Clock Management Unit (CMU) nodes
Manivannan Sadhasivam [Thu, 14 Jun 2018 18:08:34 +0000 (23:38 +0530)]
arm: dts: s900: Add Clock Management Unit (CMU) nodes

This commit adds Clock Management Unit (CMU) nodes for Actions Semi
S900 SoC.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>