1 //*****************************************************************************
\r
3 // hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.
\r
5 // Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
\r
7 // Software License Agreement
\r
9 // Luminary Micro, Inc. (LMI) is supplying this software for use solely and
\r
10 // exclusively on LMI's Stellaris Family of microcontroller products.
\r
12 // The software is owned by LMI and/or its suppliers, and is protected under
\r
13 // applicable copyright laws. All rights are reserved. Any use in violation
\r
14 // of the foregoing restrictions may subject the user to criminal sanctions
\r
15 // under applicable laws, as well as to civil liability for the breach of the
\r
16 // terms and conditions of this license.
\r
18 // THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
\r
19 // OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
\r
20 // MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
\r
21 // LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
\r
22 // CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
\r
24 // This is part of revision 635 of the Stellaris Driver Library.
\r
26 //*****************************************************************************
\r
28 #ifndef __HW_WATCHDOG_H__
\r
29 #define __HW_WATCHDOG_H__
\r
31 //*****************************************************************************
\r
33 // The following define the offsets of the Watchdog Timer registers.
\r
35 //*****************************************************************************
\r
36 #define WDT_O_LOAD 0x00000000 // Load register
\r
37 #define WDT_O_VALUE 0x00000004 // Current value register
\r
38 #define WDT_O_CTL 0x00000008 // Control register
\r
39 #define WDT_O_ICR 0x0000000C // Interrupt clear register
\r
40 #define WDT_O_RIS 0x00000010 // Raw interrupt status register
\r
41 #define WDT_O_MIS 0x00000014 // Masked interrupt status register
\r
42 #define WDT_O_TEST 0x00000418 // Test register
\r
43 #define WDT_O_LOCK 0x00000C00 // Lock register
\r
44 #define WDT_O_PeriphID4 0x00000FD0 //
\r
45 #define WDT_O_PeriphID5 0x00000FD4 //
\r
46 #define WDT_O_PeriphID6 0x00000FD8 //
\r
47 #define WDT_O_PeriphID7 0x00000FDC //
\r
48 #define WDT_O_PeriphID0 0x00000FE0 //
\r
49 #define WDT_O_PeriphID1 0x00000FE4 //
\r
50 #define WDT_O_PeriphID2 0x00000FE8 //
\r
51 #define WDT_O_PeriphID3 0x00000FEC //
\r
52 #define WDT_O_PCellID0 0x00000FF0 //
\r
53 #define WDT_O_PCellID1 0x00000FF4 //
\r
54 #define WDT_O_PCellID2 0x00000FF8 //
\r
55 #define WDT_O_PCellID3 0x00000FFC //
\r
57 //*****************************************************************************
\r
59 // The following define the bit fields in the WDT_CTL register.
\r
61 //*****************************************************************************
\r
62 #define WDT_CTL_RESEN 0x00000002 // Enable reset output
\r
63 #define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int
\r
65 //*****************************************************************************
\r
67 // The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS
\r
70 //*****************************************************************************
\r
71 #define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired
\r
73 //*****************************************************************************
\r
75 // The following define the bit fields in the WDT_TEST register.
\r
77 //*****************************************************************************
\r
78 #define WDT_TEST_STALL 0x00000100 // Watchdog stall enable
\r
80 #define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable
\r
83 //*****************************************************************************
\r
85 // The following define the bit fields in the WDT_LOCK register.
\r
87 //*****************************************************************************
\r
88 #define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked
\r
89 #define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked
\r
90 #define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer
\r
92 //*****************************************************************************
\r
94 // The following define the reset values for the WDT registers.
\r
96 //*****************************************************************************
\r
97 #define WDT_RV_LOAD 0xFFFFFFFF // Load register
\r
98 #define WDT_RV_VALUE 0xFFFFFFFF // Current value register
\r
99 #define WDT_RV_CTL 0x00000000 // Control register
\r
100 #define WDT_RV_RIS 0x00000000 // Raw interrupt status register
\r
101 #define WDT_RV_MIS 0x00000000 // Masked interrupt status register
\r
102 #define WDT_RV_LOCK 0x00000000 // Lock register
\r
103 #define WDT_RV_PeriphID4 0x00000000 //
\r
104 #define WDT_RV_PeriphID5 0x00000000 //
\r
105 #define WDT_RV_PeriphID6 0x00000000 //
\r
106 #define WDT_RV_PeriphID7 0x00000000 //
\r
107 #define WDT_RV_PeriphID0 0x00000005 //
\r
108 #define WDT_RV_PeriphID1 0x00000018 //
\r
109 #define WDT_RV_PeriphID2 0x00000018 //
\r
110 #define WDT_RV_PeriphID3 0x00000001 //
\r
111 #define WDT_RV_PCellID0 0x0000000D //
\r
112 #define WDT_RV_PCellID1 0x000000F0 //
\r
113 #define WDT_RV_PCellID2 0x00000005 //
\r
114 #define WDT_RV_PCellID3 0x000000B1 //
\r
116 #endif // __HW_WATCHDOG_H__
\r