git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@14 1d2547de-c912-0410-9cb9...

author richardbarry <richardbarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>

Thu, 8 Jun 2006 09:16:29 +0000 (09:16 +0000)

committer richardbarry <richardbarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>

Thu, 8 Jun 2006 09:16:29 +0000 (09:16 +0000)
author richardbarry <richardbarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Thu, 8 Jun 2006 09:16:29 +0000 (09:16 +0000)
committer richardbarry <richardbarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Thu, 8 Jun 2006 09:16:29 +0000 (09:16 +0000)
diff --git a/Demo/ARM7_AT91FR40008_GCC/FreeRTOSConfig.h b/Demo/ARM7_AT91FR40008_GCC/FreeRTOSConfig.h

index 4f801b9c97575fd11c3c10af4de7af763f2585ff..28db62a45b903a113c2b9cd524d28b2d9f86fed4 100644 (file)
--- a/Demo/ARM7_AT91FR40008_GCC/FreeRTOSConfig.h
+++ b/Demo/ARM7_AT91FR40008_GCC/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/ARM7_AT91FR40008_GCC/Makefile b/Demo/ARM7_AT91FR40008_GCC/Makefile

index 6fdc16bc991d1d19ee6326bcf7cdf37e293eb06f..0700a677dd966e1757a3ac320b1de0d77bfab347 100644 (file)
--- a/Demo/ARM7_AT91FR40008_GCC/Makefile
+++ b/Demo/ARM7_AT91FR40008_GCC/Makefile
@@ -1,4 +1,4 @@
-#      FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+#      FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  #\r
  #      This file is part of the FreeRTOS.org distribution.\r
  #\r
diff --git a/Demo/ARM7_AT91FR40008_GCC/ParTest/ParTest.c b/Demo/ARM7_AT91FR40008_GCC/ParTest/ParTest.c

index dbbc434fdb5803fbac0835134d30164234cc2213..a3d597722a993737d2c36f81fc64d4e005de039b 100644 (file)
--- a/Demo/ARM7_AT91FR40008_GCC/ParTest/ParTest.c
+++ b/Demo/ARM7_AT91FR40008_GCC/ParTest/ParTest.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/ARM7_AT91FR40008_GCC/main.c b/Demo/ARM7_AT91FR40008_GCC/main.c

index 83300f8ec0be06d355a7697e662be082318563a4..0c312734f0eb888849d861c7389fbf2ed0808a1b 100644 (file)
--- a/Demo/ARM7_AT91FR40008_GCC/main.c
+++ b/Demo/ARM7_AT91FR40008_GCC/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/ARM7_AT91FR40008_GCC/serial/serial.c b/Demo/ARM7_AT91FR40008_GCC/serial/serial.c

index e5e6e947e7c21735476595154f682a66e969f425..190b46bcab6bc83cfc1f0c41bf8bdd54569eedca 100644 (file)
--- a/Demo/ARM7_AT91FR40008_GCC/serial/serial.c
+++ b/Demo/ARM7_AT91FR40008_GCC/serial/serial.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/ARM7_AT91FR40008_GCC/serial/serialISR.c b/Demo/ARM7_AT91FR40008_GCC/serial/serialISR.c

index e337813076507c9a6635c9cb8d9402da671cada1..fc221d77fa464b760069d35e03009d4b459d2f6b 100644 (file)
--- a/Demo/ARM7_AT91FR40008_GCC/serial/serialISR.c
+++ b/Demo/ARM7_AT91FR40008_GCC/serial/serialISR.c
@@ -1,5 +1,5 @@
  /*\r
-  FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+  FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
    This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/ARM7_AT91SAM7S64_IAR/FreeRTOSConfig.h b/Demo/ARM7_AT91SAM7S64_IAR/FreeRTOSConfig.h

index 32a4c61fbbac444620ff80051609dc20495124a1..5ddf386946b1a5f16761acfb52592415578e2182 100644 (file)
--- a/Demo/ARM7_AT91SAM7S64_IAR/FreeRTOSConfig.h
+++ b/Demo/ARM7_AT91SAM7S64_IAR/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/ARM7_AT91SAM7S64_IAR/ParTest/ParTest.c b/Demo/ARM7_AT91SAM7S64_IAR/ParTest/ParTest.c

index ce94e1c898df3710bf193c705d84a778b9f4b18d..ce7d14a2e776b90327e48ce2bb4ee69089be079d 100644 (file)
--- a/Demo/ARM7_AT91SAM7S64_IAR/ParTest/ParTest.c
+++ b/Demo/ARM7_AT91SAM7S64_IAR/ParTest/ParTest.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/ARM7_AT91SAM7S64_IAR/USB/USBSample.c b/Demo/ARM7_AT91SAM7S64_IAR/USB/USBSample.c

index 77b23b77db5b1b956d3d5db1ca6559859a71dd5b..7098e8eff1ad68a384e4811c19b881d30502ac92 100644 (file)
--- a/Demo/ARM7_AT91SAM7S64_IAR/USB/USBSample.c
+++ b/Demo/ARM7_AT91SAM7S64_IAR/USB/USBSample.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/ARM7_AT91SAM7S64_IAR/main.c b/Demo/ARM7_AT91SAM7S64_IAR/main.c

index 138c69b72b448da21670c517ca8331864afb24cf..bcefe55d5376e7171f194f28a039a1fe4dc9689b 100644 (file)
--- a/Demo/ARM7_AT91SAM7S64_IAR/main.c
+++ b/Demo/ARM7_AT91SAM7S64_IAR/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/ARM7_AT91SAM7S64_IAR/serial/serial.c b/Demo/ARM7_AT91SAM7S64_IAR/serial/serial.c

index ed89bec3cef742dcf3e05f9b0af1f4f68fd9a958..fc605955259cf36071f6035a75ad750face10a4d 100644 (file)
--- a/Demo/ARM7_AT91SAM7S64_IAR/serial/serial.c
+++ b/Demo/ARM7_AT91SAM7S64_IAR/serial/serial.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/ARM7_LPC2106_GCC/FreeRTOSConfig.h b/Demo/ARM7_LPC2106_GCC/FreeRTOSConfig.h

index d367ff9fe0256db7153c61f63883e3be759e1eaa..e36beda8401db8d8d62282a2fda997327e7afe9f 100644 (file)
--- a/Demo/ARM7_LPC2106_GCC/FreeRTOSConfig.h
+++ b/Demo/ARM7_LPC2106_GCC/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/ARM7_LPC2106_GCC/Makefile b/Demo/ARM7_LPC2106_GCC/Makefile

index cab68f0bd8425b94955fd2cc6e4fc5cddfcac566..16b30730168063ee25c6f5be14f75dd177812688 100644 (file)
--- a/Demo/ARM7_LPC2106_GCC/Makefile
+++ b/Demo/ARM7_LPC2106_GCC/Makefile
@@ -1,4 +1,4 @@
-#      FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+#      FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  #\r
  #      This file is part of the FreeRTOS.org distribution.\r
  #\r
diff --git a/Demo/ARM7_LPC2106_GCC/ParTest/ParTest.c b/Demo/ARM7_LPC2106_GCC/ParTest/ParTest.c

index a25ba6612cd68fef9efcaba7f4b150c1f5775c27..bb8a589a27e446df5051f225c8b271ba876b5bac 100644 (file)
--- a/Demo/ARM7_LPC2106_GCC/ParTest/ParTest.c
+++ b/Demo/ARM7_LPC2106_GCC/ParTest/ParTest.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/ARM7_LPC2106_GCC/main.c b/Demo/ARM7_LPC2106_GCC/main.c

index 8b2be83d4155188274b9b08672e859b0e495a9f5..096bbdc68b07e6a069e491b2559d094f466c8c55 100644 (file)
--- a/Demo/ARM7_LPC2106_GCC/main.c
+++ b/Demo/ARM7_LPC2106_GCC/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/ARM7_LPC2106_GCC/serial/serial.c b/Demo/ARM7_LPC2106_GCC/serial/serial.c

index ca200dbc7079d18cbd6f5826c0bbf18eb7151565..26e949618efb7012be63eec5b7f4aec4b8631394 100644 (file)
--- a/Demo/ARM7_LPC2106_GCC/serial/serial.c
+++ b/Demo/ARM7_LPC2106_GCC/serial/serial.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/ARM7_LPC2106_GCC/serial/serialISR.c b/Demo/ARM7_LPC2106_GCC/serial/serialISR.c

index 4987ed67c45c782930a50f52a74db6bedc856127..f488b8ba8b3030f092a8a96c391a6b6f99d75c87 100644 (file)
--- a/Demo/ARM7_LPC2106_GCC/serial/serialISR.c
+++ b/Demo/ARM7_LPC2106_GCC/serial/serialISR.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/ARM7_LPC2129_IAR/FreeRTOSConfig.h b/Demo/ARM7_LPC2129_IAR/FreeRTOSConfig.h

index 471481e7e8c298752edec5ed5f57a1a26c4f93f2..070128d15d9640457d807b2d96c6809c9254225e 100644 (file)
--- a/Demo/ARM7_LPC2129_IAR/FreeRTOSConfig.h
+++ b/Demo/ARM7_LPC2129_IAR/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/ARM7_LPC2129_IAR/ParTest/ParTest.c b/Demo/ARM7_LPC2129_IAR/ParTest/ParTest.c

index aa824c8780e8d084d9278ddd104dde1044fb0469..799f300d51d276b344d9fb474a1de16d57050588 100644 (file)
--- a/Demo/ARM7_LPC2129_IAR/ParTest/ParTest.c
+++ b/Demo/ARM7_LPC2129_IAR/ParTest/ParTest.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/ARM7_LPC2129_IAR/main.c b/Demo/ARM7_LPC2129_IAR/main.c

index e4d0b8e2c0d8d15875d035779f2a4dffa6857039..8df3e18211ae302f6c50e8b6377153592c5ba86b 100644 (file)
--- a/Demo/ARM7_LPC2129_IAR/main.c
+++ b/Demo/ARM7_LPC2129_IAR/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/ARM7_LPC2129_IAR/serial/serial.c b/Demo/ARM7_LPC2129_IAR/serial/serial.c

index 41e2bc31ad0e639d8342863671616e9ed3060dd1..42a147a1e71d5aa62205a46aeb36476a38628b0f 100644 (file)
--- a/Demo/ARM7_LPC2129_IAR/serial/serial.c
+++ b/Demo/ARM7_LPC2129_IAR/serial/serial.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/ARM7_LPC2129_Keil/FreeRTOSConfig.h b/Demo/ARM7_LPC2129_Keil/FreeRTOSConfig.h

index bfdd2bbceb69e4c419f30198ae9136b3ca8eb413..c831b45274a8e9afb48cfc4ed19ceda602488ab4 100644 (file)
--- a/Demo/ARM7_LPC2129_Keil/FreeRTOSConfig.h
+++ b/Demo/ARM7_LPC2129_Keil/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/ARM7_LPC2129_Keil/ParTest/ParTest.c b/Demo/ARM7_LPC2129_Keil/ParTest/ParTest.c

index 24cd35cce13629d2371981f24c0b1735876a8683..d128ce67cb089cde9d22de644a5b1ce45d88f402 100644 (file)
--- a/Demo/ARM7_LPC2129_Keil/ParTest/ParTest.c
+++ b/Demo/ARM7_LPC2129_Keil/ParTest/ParTest.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/ARM7_LPC2129_Keil/main.c b/Demo/ARM7_LPC2129_Keil/main.c

index 769b401a42716aeda6489fe453a41e31dac35841..ffa53206b11b9aa5f032718d6a3670fd0e1dd8bc 100644 (file)
--- a/Demo/ARM7_LPC2129_Keil/main.c
+++ b/Demo/ARM7_LPC2129_Keil/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/ARM7_LPC2129_Keil/serial/serial.c b/Demo/ARM7_LPC2129_Keil/serial/serial.c

index 0636b13a2b19d13c6c453b38e0a6086d702ff7bc..c8bf1870f9235803a6e673a2a0c093ad2b39f7a0 100644 (file)
--- a/Demo/ARM7_LPC2129_Keil/serial/serial.c
+++ b/Demo/ARM7_LPC2129_Keil/serial/serial.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/ARM7_LPC2129_Keil/serial/serialISR.c b/Demo/ARM7_LPC2129_Keil/serial/serialISR.c

index 185649569bfced31eb5e32c2e9d24fa2510f18dd..3ced802e3af5af63950659b84d3dcbfaaa6c836d 100644 (file)
--- a/Demo/ARM7_LPC2129_Keil/serial/serialISR.c
+++ b/Demo/ARM7_LPC2129_Keil/serial/serialISR.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/ARM7_STR71x_IAR/FreeRTOSConfig.h b/Demo/ARM7_STR71x_IAR/FreeRTOSConfig.h

index faaee588ed37ccf439f189a3cf0fa35de200f3be..759d1e2dea74ebf98487d788e187ca7b674af4f9 100644 (file)
--- a/Demo/ARM7_STR71x_IAR/FreeRTOSConfig.h
+++ b/Demo/ARM7_STR71x_IAR/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/ARM7_STR71x_IAR/ParTest/ParTest.c b/Demo/ARM7_STR71x_IAR/ParTest/ParTest.c

index 467aac9ba808901899ecf083bd9d3993e3c120f0..f8d9d7d3e34fcc8be51d9ecbfb57654771d266c3 100644 (file)
--- a/Demo/ARM7_STR71x_IAR/ParTest/ParTest.c
+++ b/Demo/ARM7_STR71x_IAR/ParTest/ParTest.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/ARM7_STR71x_IAR/main.c b/Demo/ARM7_STR71x_IAR/main.c

index 7130d19bcf3092cda553a07ebed99827e21988d2..b30d8b1a5a5c2f8cb8be6076ceee769b87c3c40d 100644 (file)
--- a/Demo/ARM7_STR71x_IAR/main.c
+++ b/Demo/ARM7_STR71x_IAR/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/ARM7_STR71x_IAR/serial/serial.c b/Demo/ARM7_STR71x_IAR/serial/serial.c

index 1fda97c4f9d174c06657061dea54dffef3608e64..4e7da984a5bc46167874b1cf7420ce2ef6b17c32 100644 (file)
--- a/Demo/ARM7_STR71x_IAR/serial/serial.c
+++ b/Demo/ARM7_STR71x_IAR/serial/serial.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/AVR_ATMega323_IAR/FreeRTOSConfig.h b/Demo/AVR_ATMega323_IAR/FreeRTOSConfig.h

index b2b629f0475a8bacf45c95f2132e6df36d508086..f650298ffc18a49725c3fb4f241b370a1a11cb14 100644 (file)
--- a/Demo/AVR_ATMega323_IAR/FreeRTOSConfig.h
+++ b/Demo/AVR_ATMega323_IAR/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/AVR_ATMega323_IAR/ParTest/ParTest.c b/Demo/AVR_ATMega323_IAR/ParTest/ParTest.c

index f964abfa6a5a2da98a7ab91f1c36639e0ed1e13a..12ae5b42cb97c14423625c82a42d501ad9f7b2c5 100644 (file)
--- a/Demo/AVR_ATMega323_IAR/ParTest/ParTest.c
+++ b/Demo/AVR_ATMega323_IAR/ParTest/ParTest.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/AVR_ATMega323_IAR/main.c b/Demo/AVR_ATMega323_IAR/main.c

index a181ae748f73fe05434ea14310ceae48cf00718b..0c298ed60424623917c1eb2a8d2f1dab143eaec3 100644 (file)
--- a/Demo/AVR_ATMega323_IAR/main.c
+++ b/Demo/AVR_ATMega323_IAR/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/AVR_ATMega323_IAR/serial/serial.c b/Demo/AVR_ATMega323_IAR/serial/serial.c

index 44bc3b38c928e104e874c136ac25753120c5abdc..05b29dba53b0aafbe1c5c8a8b484b3dfad19d955 100644 (file)
--- a/Demo/AVR_ATMega323_IAR/serial/serial.c
+++ b/Demo/AVR_ATMega323_IAR/serial/serial.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/AVR_ATMega323_WinAVR/FreeRTOSConfig.h b/Demo/AVR_ATMega323_WinAVR/FreeRTOSConfig.h

index 54f202c37bb3023338a450f77fd47f60465d3f6f..5f2c1f76c4f7941a9fbc0c594562d63736f1cca9 100644 (file)
--- a/Demo/AVR_ATMega323_WinAVR/FreeRTOSConfig.h
+++ b/Demo/AVR_ATMega323_WinAVR/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/AVR_ATMega323_WinAVR/ParTest/ParTest.c b/Demo/AVR_ATMega323_WinAVR/ParTest/ParTest.c

index f964abfa6a5a2da98a7ab91f1c36639e0ed1e13a..12ae5b42cb97c14423625c82a42d501ad9f7b2c5 100644 (file)
--- a/Demo/AVR_ATMega323_WinAVR/ParTest/ParTest.c
+++ b/Demo/AVR_ATMega323_WinAVR/ParTest/ParTest.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/AVR_ATMega323_WinAVR/main.c b/Demo/AVR_ATMega323_WinAVR/main.c

index 7eec91b0cbda8e0d9c2ff507de2fdedf4b16905c..4b32039c8682986c6928c8fa2a3530f1c8291b67 100644 (file)
--- a/Demo/AVR_ATMega323_WinAVR/main.c
+++ b/Demo/AVR_ATMega323_WinAVR/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/AVR_ATMega323_WinAVR/serial/serial.c b/Demo/AVR_ATMega323_WinAVR/serial/serial.c

index 69c253e48e2386b6e8c09586d413cccd50722a19..0144a6c6043bfaa9f2906d3f6ee33e4122f99c3c 100644 (file)
--- a/Demo/AVR_ATMega323_WinAVR/serial/serial.c
+++ b/Demo/AVR_ATMega323_WinAVR/serial/serial.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/CORTEX_LM3S102_GCC/Demo1/FreeRTOSConfig.h b/Demo/CORTEX_LM3S102_GCC/Demo1/FreeRTOSConfig.h

index 6574fab45a0e1f1a4549aed70259f4b3f878cea1..80972dec3ae1ac00a0975536279854f695bd20d9 100644 (file)
--- a/Demo/CORTEX_LM3S102_GCC/Demo1/FreeRTOSConfig.h
+++ b/Demo/CORTEX_LM3S102_GCC/Demo1/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/CORTEX_LM3S102_GCC/Demo1/main.c b/Demo/CORTEX_LM3S102_GCC/Demo1/main.c

index bb5afd9de5f493d4291308832f19986922a9b15f..c1e7b2fe13bca5e1acfac8cde75796cf442694e9 100644 (file)
--- a/Demo/CORTEX_LM3S102_GCC/Demo1/main.c
+++ b/Demo/CORTEX_LM3S102_GCC/Demo1/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/CORTEX_LM3S102_GCC/Demo2/FreeRTOSConfig.h b/Demo/CORTEX_LM3S102_GCC/Demo2/FreeRTOSConfig.h

index 39c3ecb2bfe2c85048202e0133ceeb1486024b78..899df5e7bc58ff382203c5fb5ad621ffdc35c77a 100644 (file)
--- a/Demo/CORTEX_LM3S102_GCC/Demo2/FreeRTOSConfig.h
+++ b/Demo/CORTEX_LM3S102_GCC/Demo2/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/CORTEX_LM3S102_GCC/Demo2/main.c b/Demo/CORTEX_LM3S102_GCC/Demo2/main.c

index 77de7e1e183b5a038bd844863630498374ea1158..b43fc49693d4368211907e46eb7ce91560ac5d00 100644 (file)
--- a/Demo/CORTEX_LM3S102_GCC/Demo2/main.c
+++ b/Demo/CORTEX_LM3S102_GCC/Demo2/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/CORTEX_LM3S102_GCC/FreeRTOSConfig.h b/Demo/CORTEX_LM3S102_GCC/FreeRTOSConfig.h

index 6574fab45a0e1f1a4549aed70259f4b3f878cea1..80972dec3ae1ac00a0975536279854f695bd20d9 100644 (file)
--- a/Demo/CORTEX_LM3S102_GCC/FreeRTOSConfig.h
+++ b/Demo/CORTEX_LM3S102_GCC/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/CORTEX_LM3S102_GCC/ParTest/ParTest.c b/Demo/CORTEX_LM3S102_GCC/ParTest/ParTest.c

index 2e3983a6706e9908a1e7cc8d347d48c41339cdc6..0426f1fe0cea1ca40249eefd79eceb5e4cc60ed4 100644 (file)
--- a/Demo/CORTEX_LM3S102_GCC/ParTest/ParTest.c
+++ b/Demo/CORTEX_LM3S102_GCC/ParTest/ParTest.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/CORTEX_LM3S102_GCC/main.c b/Demo/CORTEX_LM3S102_GCC/main.c

index bb5afd9de5f493d4291308832f19986922a9b15f..c1e7b2fe13bca5e1acfac8cde75796cf442694e9 100644 (file)
--- a/Demo/CORTEX_LM3S102_GCC/main.c
+++ b/Demo/CORTEX_LM3S102_GCC/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/CORTEX_LM3S102_KEIL/Demo1/FreeRTOSConfig.h b/Demo/CORTEX_LM3S102_KEIL/Demo1/FreeRTOSConfig.h

index 6574fab45a0e1f1a4549aed70259f4b3f878cea1..80972dec3ae1ac00a0975536279854f695bd20d9 100644 (file)
--- a/Demo/CORTEX_LM3S102_KEIL/Demo1/FreeRTOSConfig.h
+++ b/Demo/CORTEX_LM3S102_KEIL/Demo1/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/CORTEX_LM3S102_KEIL/Demo1/main.c b/Demo/CORTEX_LM3S102_KEIL/Demo1/main.c

index 608dfbba80041904dab6751a15844f7faab39871..1a18a441ec3dfdb92201dea19f991f0bcdd0f7c5 100644 (file)
--- a/Demo/CORTEX_LM3S102_KEIL/Demo1/main.c
+++ b/Demo/CORTEX_LM3S102_KEIL/Demo1/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/CORTEX_LM3S102_KEIL/Demo2/FreeRTOSConfig.h b/Demo/CORTEX_LM3S102_KEIL/Demo2/FreeRTOSConfig.h

index 39c3ecb2bfe2c85048202e0133ceeb1486024b78..899df5e7bc58ff382203c5fb5ad621ffdc35c77a 100644 (file)
--- a/Demo/CORTEX_LM3S102_KEIL/Demo2/FreeRTOSConfig.h
+++ b/Demo/CORTEX_LM3S102_KEIL/Demo2/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/CORTEX_LM3S102_KEIL/Demo2/main.c b/Demo/CORTEX_LM3S102_KEIL/Demo2/main.c

index 09a6515b26e7a5d119c0162f4b3c68995f099467..a124a23a3cbea4f4f373d0b2158b87ecc3c176f4 100644 (file)
--- a/Demo/CORTEX_LM3S102_KEIL/Demo2/main.c
+++ b/Demo/CORTEX_LM3S102_KEIL/Demo2/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/CORTEX_LM3S102_KEIL/FreeRTOSConfig.h b/Demo/CORTEX_LM3S102_KEIL/FreeRTOSConfig.h

index 6574fab45a0e1f1a4549aed70259f4b3f878cea1..80972dec3ae1ac00a0975536279854f695bd20d9 100644 (file)
--- a/Demo/CORTEX_LM3S102_KEIL/FreeRTOSConfig.h
+++ b/Demo/CORTEX_LM3S102_KEIL/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/CORTEX_LM3S102_KEIL/ParTest/ParTest.c b/Demo/CORTEX_LM3S102_KEIL/ParTest/ParTest.c

index 2e3983a6706e9908a1e7cc8d347d48c41339cdc6..0426f1fe0cea1ca40249eefd79eceb5e4cc60ed4 100644 (file)
--- a/Demo/CORTEX_LM3S102_KEIL/ParTest/ParTest.c
+++ b/Demo/CORTEX_LM3S102_KEIL/ParTest/ParTest.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/CORTEX_LM3S102_KEIL/main.c b/Demo/CORTEX_LM3S102_KEIL/main.c

index 608dfbba80041904dab6751a15844f7faab39871..1a18a441ec3dfdb92201dea19f991f0bcdd0f7c5 100644 (file)
--- a/Demo/CORTEX_LM3S102_KEIL/main.c
+++ b/Demo/CORTEX_LM3S102_KEIL/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo1/FreeRTOSConfig.h b/Demo/CORTEX_LM3S102_Rowley/Demo1/FreeRTOSConfig.h

index 6574fab45a0e1f1a4549aed70259f4b3f878cea1..80972dec3ae1ac00a0975536279854f695bd20d9 100644 (file)
--- a/Demo/CORTEX_LM3S102_Rowley/Demo1/FreeRTOSConfig.h
+++ b/Demo/CORTEX_LM3S102_Rowley/Demo1/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo1/ParTest.c b/Demo/CORTEX_LM3S102_Rowley/Demo1/ParTest.c

index 2e3983a6706e9908a1e7cc8d347d48c41339cdc6..0426f1fe0cea1ca40249eefd79eceb5e4cc60ed4 100644 (file)
--- a/Demo/CORTEX_LM3S102_Rowley/Demo1/ParTest.c
+++ b/Demo/CORTEX_LM3S102_Rowley/Demo1/ParTest.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo1/main.c b/Demo/CORTEX_LM3S102_Rowley/Demo1/main.c

index d17fbf20121b559bb54317a43c1ff57f9be07399..8c2be4320307e9f7d6f9600b6bc93e46cc9b2f65 100644 (file)
--- a/Demo/CORTEX_LM3S102_Rowley/Demo1/main.c
+++ b/Demo/CORTEX_LM3S102_Rowley/Demo1/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo1/vectors.s b/Demo/CORTEX_LM3S102_Rowley/Demo1/vectors.s

index 66f29fb70b7ae59572913dbe7d54a564149c0e8b..2ff9827a2a8fd800b225d5b6cd0bde7c8539b4d7 100644 (file)
--- a/Demo/CORTEX_LM3S102_Rowley/Demo1/vectors.s
+++ b/Demo/CORTEX_LM3S102_Rowley/Demo1/vectors.s
@@ -25,7 +25,11 @@
  \r
  _vectors:\r
    .word __stack_end__\r
-  .word reset_handler\r
+#ifdef STARTUP_FROM_RESET\r
+  .word _start\r
+#else\r
+  .word reset_wait\r
+#endif /* STARTUP_FROM_RESET */\r
    .word NmiISR\r
    .word FaultISR\r
    .word 0 // Populate if using MemManage (MPU)\r
@@ -110,6 +114,6 @@ DEFAULT_ISR_HANDLER Analog_Comparator_2_ISR
  DEFAULT_ISR_HANDLER System_Control_ISR\r
  DEFAULT_ISR_HANDLER FLASH_Control_ISR\r
  \r
-\r
-\r
-\r
+#ifndef STARTUP_FROM_RESET\r
+DEFAULT_ISR_HANDLER reset_wait\r
+#endif /* STARTUP_FROM_RESET */\r
diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo2/FreeRTOSConfig.h b/Demo/CORTEX_LM3S102_Rowley/Demo2/FreeRTOSConfig.h

index 39c3ecb2bfe2c85048202e0133ceeb1486024b78..899df5e7bc58ff382203c5fb5ad621ffdc35c77a 100644 (file)
--- a/Demo/CORTEX_LM3S102_Rowley/Demo2/FreeRTOSConfig.h
+++ b/Demo/CORTEX_LM3S102_Rowley/Demo2/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo2/ParTest.c b/Demo/CORTEX_LM3S102_Rowley/Demo2/ParTest.c

index 2e3983a6706e9908a1e7cc8d347d48c41339cdc6..0426f1fe0cea1ca40249eefd79eceb5e4cc60ed4 100644 (file)
--- a/Demo/CORTEX_LM3S102_Rowley/Demo2/ParTest.c
+++ b/Demo/CORTEX_LM3S102_Rowley/Demo2/ParTest.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo2/main.c b/Demo/CORTEX_LM3S102_Rowley/Demo2/main.c

index 3f45733073dc5ed75164dc90c8b1b165aca0decf..e88c15b09acdb6fef3789ced9dd2c2849f9fb94b 100644 (file)
--- a/Demo/CORTEX_LM3S102_Rowley/Demo2/main.c
+++ b/Demo/CORTEX_LM3S102_Rowley/Demo2/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo2/vectors.s b/Demo/CORTEX_LM3S102_Rowley/Demo2/vectors.s

index 66f29fb70b7ae59572913dbe7d54a564149c0e8b..2ff9827a2a8fd800b225d5b6cd0bde7c8539b4d7 100644 (file)
--- a/Demo/CORTEX_LM3S102_Rowley/Demo2/vectors.s
+++ b/Demo/CORTEX_LM3S102_Rowley/Demo2/vectors.s
@@ -25,7 +25,11 @@
  \r
  _vectors:\r
    .word __stack_end__\r
-  .word reset_handler\r
+#ifdef STARTUP_FROM_RESET\r
+  .word _start\r
+#else\r
+  .word reset_wait\r
+#endif /* STARTUP_FROM_RESET */\r
    .word NmiISR\r
    .word FaultISR\r
    .word 0 // Populate if using MemManage (MPU)\r
@@ -110,6 +114,6 @@ DEFAULT_ISR_HANDLER Analog_Comparator_2_ISR
  DEFAULT_ISR_HANDLER System_Control_ISR\r
  DEFAULT_ISR_HANDLER FLASH_Control_ISR\r
  \r
-\r
-\r
-\r
+#ifndef STARTUP_FROM_RESET\r
+DEFAULT_ISR_HANDLER reset_wait\r
+#endif /* STARTUP_FROM_RESET */\r
diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo3/FreeRTOSConfig.h b/Demo/CORTEX_LM3S102_Rowley/Demo3/FreeRTOSConfig.h

index 79edc97d5041e4816bade835b14cd182516a13b9..51fe0aac070733c6680840eb83076b900f4740d0 100644 (file)
--- a/Demo/CORTEX_LM3S102_Rowley/Demo3/FreeRTOSConfig.h
+++ b/Demo/CORTEX_LM3S102_Rowley/Demo3/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo3/ParTest.c b/Demo/CORTEX_LM3S102_Rowley/Demo3/ParTest.c

index 5b1daa5a6010eedf196ab7b7a7b344c6d0aa4b90..64a61d7c88f589fb9c9a15197911ce8f68ef0d90 100644 (file)
--- a/Demo/CORTEX_LM3S102_Rowley/Demo3/ParTest.c
+++ b/Demo/CORTEX_LM3S102_Rowley/Demo3/ParTest.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo3/main.c b/Demo/CORTEX_LM3S102_Rowley/Demo3/main.c

index 632411330e54b1abaadcf631085881fedc5d75d6..1634c31d507087b2a85b9f12a2edd86639ac8e18 100644 (file)
--- a/Demo/CORTEX_LM3S102_Rowley/Demo3/main.c
+++ b/Demo/CORTEX_LM3S102_Rowley/Demo3/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/CORTEX_LM3S102_Rowley/Demo3/vectors.s b/Demo/CORTEX_LM3S102_Rowley/Demo3/vectors.s

index 08d7453398177f7122979ea2ba284fccdd9ac071..c06b1fefdf1070e1b4294e2139680fe628d68ea8 100644 (file)
--- a/Demo/CORTEX_LM3S102_Rowley/Demo3/vectors.s
+++ b/Demo/CORTEX_LM3S102_Rowley/Demo3/vectors.s
@@ -26,7 +26,11 @@
  \r
  _vectors:\r
    .word __stack_end__\r
-  .word reset_handler\r
+#ifdef STARTUP_FROM_RESET\r
+  .word _start\r
+#else\r
+  .word reset_wait\r
+#endif /* STARTUP_FROM_RESET */\r
    .word NmiISR\r
    .word FaultISR\r
    .word 0 // Populate if using MemManage (MPU)\r
@@ -111,6 +115,6 @@ DEFAULT_ISR_HANDLER Analog_Comparator_2_ISR
  DEFAULT_ISR_HANDLER System_Control_ISR\r
  DEFAULT_ISR_HANDLER FLASH_Control_ISR\r
  \r
-\r
-\r
-\r
+#ifndef STARTUP_FROM_RESET\r
+DEFAULT_ISR_HANDLER reset_wait\r
+#endif /* STARTUP_FROM_RESET */\r
diff --git a/Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzp b/Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzp

index 1111b0c89704ad6b17f2d62bd40635c7e4028515..dc51429e9709e83f20b2d908c62b37ba0c40f19a 100644 (file)
--- a/Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzp
+++ b/Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzp
@@ -1,7 +1,7 @@
  <!DOCTYPE CrossStudio_Project_File>
  <solution version="1" Name="RTOSDemo" >
    <project Name="Demo1" >
-    <configuration arm_library_instruction_set="Thumb" Target="LM3S101" property_groups_file_path="$(StudioDir)/targets/Luminary_LM3S/propertyGroups.xml" linker_memory_map_file="$(StudioDir)/targets/Luminary_LM3S/LM3S101_MemoryMap.xml" gcc_entry_point="reset_handler" build_remove_unused_symbols="Yes" arm_linker_fiq_stack_size="0" arm_architecture="v7M" project_directory="" arm_linker_irq_stack_size="0" link_include_startup_code="No" arm_target_flash_loader_type="LIBMEM RPC Loader" arm_instruction_set="Thumb" project_type="Executable" linker_printf_width_precision_supported="No" arm_linker_stack_size="128" Name="Common" arm_target_debug_interface_type="ADIv5" arm_linker_heap_size="128" />
+    <configuration arm_library_instruction_set="Thumb" Target="LM3S101" property_groups_file_path="$(StudioDir)/targets/Luminary_LM3S/propertyGroups.xml" linker_memory_map_file="$(StudioDir)/targets/Luminary_LM3S/LM3S101_MemoryMap.xml" gcc_entry_point="_start" build_remove_unused_symbols="Yes" arm_linker_fiq_stack_size="0" arm_architecture="v7M" linker_section_placement_file="$(StudioDir)/targets/Luminary_LM3S/flash_placement.xml" project_directory="" arm_linker_irq_stack_size="0" link_include_startup_code="No" arm_target_flash_loader_type="LIBMEM RPC Loader" arm_instruction_set="Thumb" project_type="Executable" linker_printf_width_precision_supported="No" arm_linker_stack_size="200" Name="Common" arm_target_debug_interface_type="ADIv5" arm_linker_heap_size="128" />
      <configuration arm_target_flash_loader_file_path="$(StudioDir)/targets/Luminary_LM3S/Release/Loader.elf" linker_section_placement_file="$(StudioDir)/targets/flash_placement.xml" target_reset_script="FLASHReset()" Name="Flash" Placement="Flash" />
      <configuration linker_section_placement_file="$(StudioDir)/targets/sram_placement.xml" Name="RAM" Placement="RAM" />
      <folder Name="Source Files" >
@@ -17,7 +17,7 @@
          <file file_name="../../Source/list.c" Name="list.c" />
          <file file_name="../../Source/queue.c" Name="queue.c" />
          <file file_name="../../Source/portable/GCC/ARM_CM3/port.c" Name="port.c" >
-          <configuration gcc_optimization_level="Level 2" Name="Flash Release" />
+          <configuration gcc_optimization_level="Level 1" Name="Flash Release" />
          </file>
          <file file_name="../../Source/portable/MemMang/heap_1.c" Name="heap_1.c" />
        </folder>
@@ -32,11 +32,12 @@
        </file>
        <file file_name="Demo1/vectors.s" Name="vectors.s" />
      </folder>
-    <configuration build_remove_unused_symbols="Yes" build_quietly="No" c_preprocessor_definitions="GCC_ARMCM3_LM3S102" linker_additional_files="$(ProjectDir)/hw_include/libdriver.a" c_user_include_directories="$(ProjectDir)/demo1;$(ProjectDir)/../common/include;$(ProjectDir)/hw_include" link_include_standard_libraries="Yes" gcc_optimization_level="Level 2" build_debug_information="Yes" arm_linker_stack_size="200" Name="Flash Release" c_system_include_directories="$(StudioDir)/include;$(ProjectDir)/../../source/include;$(ProjectDir)/../../source/portable/gcc/ARM_CM3" arm_use_gcc_libraries="No" linker_output_format="None" arm_linker_heap_size="0" />
+    <configuration linker_memory_map_file="$(StudioDir)/targets/Luminary_LM3S/LM3S101_MemoryMap.xml" gcc_entry_point="_start" build_remove_unused_symbols="Yes" build_quietly="No" c_preprocessor_definitions="" linker_section_placement_file="$(StudioDir)/targets/Luminary_LM3S/flash_placement.xml" linker_additional_files="$(ProjectDir)/hw_include/libdriver.a" c_user_include_directories="" link_include_standard_libraries="Yes" gcc_optimization_level="Level 2" build_debug_information="Yes" arm_linker_stack_size="200" Name="Flash Release" c_system_include_directories="" arm_use_gcc_libraries="No" arm_core_type="Cortex-M3" linker_output_format="None" arm_linker_heap_size="0" />
+    <configuration linker_section_placement_file="$(StudioDir)/targets/Luminary_LM3S/flash_placement.xml" linker_additional_files="$(ProjectDir)/hw_include/libdriver.a" Name="Flash Debug" arm_linker_heap_size="0" />
    </project>
-  <configuration inherited_configurations="Flash;Release" Name="Flash Release" />
+  <configuration inherited_configurations="Flash;Release" c_preprocessor_definitions="" Name="Flash Release" />
    <configuration c_preprocessor_definitions="__FLASH_BUILD" hidden="Yes" Name="Flash" />
-  <configuration c_preprocessor_definitions="NDEBUG" link_include_startup_code="No" gcc_optimization_level="Level 1" build_debug_information="No" hidden="Yes" Name="Release" />
+  <configuration c_preprocessor_definitions="NDEBUG;STARTUP_FROM_RESET" arm_architecture="v7M" link_include_startup_code="No" gcc_optimization_level="Level 1" build_debug_information="No" linker_printf_width_precision_supported="No" hidden="Yes" Name="Release" arm_core_type="Cortex-M3" />
    <project Name="Demo2" >
      <configuration arm_library_instruction_set="Thumb" Target="LM3S101" property_groups_file_path="$(StudioDir)/targets/Luminary_LM3S/propertyGroups.xml" linker_memory_map_file="$(StudioDir)/targets/Luminary_LM3S/LM3S101_MemoryMap.xml" gcc_entry_point="reset_handler" build_remove_unused_symbols="Yes" arm_linker_fiq_stack_size="0" arm_architecture="v7M" project_directory="" arm_linker_irq_stack_size="0" link_include_startup_code="No" arm_target_flash_loader_type="LIBMEM RPC Loader" arm_instruction_set="Thumb" project_type="Executable" linker_printf_width_precision_supported="No" arm_linker_stack_size="128" Name="Common" arm_target_debug_interface_type="ADIv5" arm_linker_heap_size="128" />
      <configuration arm_target_flash_loader_file_path="$(StudioDir)/targets/Luminary_LM3S/Release/Loader.elf" linker_section_placement_file="$(StudioDir)/targets/flash_placement.xml" target_reset_script="FLASHReset()" Name="Flash" Placement="Flash" />
@@ -54,7 +55,7 @@
          <file file_name="../../Source/list.c" Name="list.c" />
          <file file_name="../../Source/queue.c" Name="queue.c" />
          <file file_name="../../Source/portable/GCC/ARM_CM3/port.c" Name="port.c" >
-          <configuration gcc_optimization_level="Level 2" Name="Flash Release" />
+          <configuration gcc_optimization_level="Level 1" Name="Flash Release" />
          </file>
          <file file_name="../../Source/portable/MemMang/heap_1.c" Name="heap_1.c" />
        </folder>
@@ -69,7 +70,8 @@
        </file>
        <file file_name="Demo2/vectors.s" Name="vectors.s" />
      </folder>
-    <configuration build_remove_unused_symbols="Yes" build_quietly="No" c_preprocessor_definitions="GCC_ARMCM3_LM3S102" linker_additional_files="$(ProjectDir)/hw_include/libdriver.a" c_user_include_directories="$(ProjectDir)/demo2;$(ProjectDir)/../common/include;$(ProjectDir)/hw_include" link_include_standard_libraries="Yes" gcc_optimization_level="Level 2" build_debug_information="Yes" arm_linker_stack_size="200" Name="Flash Release" c_system_include_directories="$(StudioDir)/include;$(ProjectDir)/../../source/include;$(ProjectDir)/../../source/portable/gcc/ARM_CM3" arm_use_gcc_libraries="No" linker_output_format="None" arm_linker_heap_size="0" />
+    <configuration gcc_entry_point="_start" build_remove_unused_symbols="Yes" build_quietly="No" c_preprocessor_definitions="GCC_ARMCM3_LM3S102" linker_section_placement_file="$(StudioDir)/targets/Luminary_LM3S/flash_placement.xml" linker_additional_files="$(ProjectDir)/hw_include/libdriver.a" c_user_include_directories="$(ProjectDir)/demo2;$(ProjectDir)/../common/include;$(ProjectDir)/hw_include" link_include_standard_libraries="Yes" gcc_optimization_level="Level 2" build_debug_information="Yes" arm_linker_stack_size="200" Name="Flash Release" c_system_include_directories="$(StudioDir)/include;$(ProjectDir)/../../source/include;$(ProjectDir)/../../source/portable/gcc/ARM_CM3" arm_use_gcc_libraries="No" linker_output_format="None" arm_linker_heap_size="0" />
+    <configuration gcc_entry_point="_start" linker_section_placement_file="$(StudioDir)/targets/Luminary_LM3S/flash_placement.xml" linker_additional_files="$(ProjectDir)/hw_include/libdriver.a" arm_linker_stack_size="200" Name="Flash Debug" arm_linker_heap_size="0" />
    </project>
    <project Name="Demo3" >
      <configuration arm_library_instruction_set="Thumb" Target="LM3S101" property_groups_file_path="$(StudioDir)/targets/Luminary_LM3S/propertyGroups.xml" linker_memory_map_file="$(StudioDir)/targets/Luminary_LM3S/LM3S101_MemoryMap.xml" gcc_entry_point="reset_handler" build_remove_unused_symbols="Yes" arm_linker_fiq_stack_size="0" arm_architecture="v7M" project_directory="" arm_linker_irq_stack_size="0" link_include_startup_code="No" arm_target_flash_loader_type="LIBMEM RPC Loader" arm_instruction_set="Thumb" project_type="Executable" linker_printf_width_precision_supported="No" arm_linker_stack_size="128" Name="Common" arm_target_debug_interface_type="ADIv5" arm_linker_heap_size="128" />
@@ -99,6 +101,10 @@
        </file>
        <file file_name="Demo3/vectors.s" Name="vectors.s" />
      </folder>
-    <configuration build_remove_unused_symbols="Yes" build_quietly="No" c_preprocessor_definitions="GCC_ARMCM3_LM3S102" linker_additional_files="$(ProjectDir)/hw_include/libdriver.a" c_user_include_directories="$(ProjectDir)/demo3;$(ProjectDir)/../common/include;$(ProjectDir)/hw_include" link_include_standard_libraries="Yes" gcc_optimization_level="Level 1" build_debug_information="Yes" arm_linker_stack_size="200" Name="Flash Release" c_system_include_directories="$(StudioDir)/include;$(ProjectDir)/../../source/include;$(ProjectDir)/../../source/portable/gcc/ARM_CM3" arm_use_gcc_libraries="No" linker_output_format="None" arm_linker_heap_size="0" />
+    <configuration gcc_entry_point="_start" build_remove_unused_symbols="Yes" build_quietly="No" c_preprocessor_definitions="GCC_ARMCM3_LM3S102" linker_section_placement_file="$(StudioDir)/targets/Luminary_LM3S/flash_placement.xml" linker_additional_files="$(ProjectDir)/hw_include/libdriver.a" c_user_include_directories="$(ProjectDir)/demo3;$(ProjectDir)/../common/include;$(ProjectDir)/hw_include" link_include_standard_libraries="Yes" gcc_optimization_level="Level 2" build_debug_information="Yes" arm_linker_stack_size="200" Name="Flash Release" c_system_include_directories="$(StudioDir)/include;$(ProjectDir)/../../source/include;$(ProjectDir)/../../source/portable/gcc/ARM_CM3" arm_use_gcc_libraries="No" linker_output_format="None" arm_linker_heap_size="0" />
+    <configuration gcc_entry_point="_start" linker_section_placement_file="$(StudioDir)/targets/Luminary_LM3S/flash_placement.xml" linker_additional_files="$(ProjectDir)/hw_include/libdriver.a" arm_linker_stack_size="200" Name="Flash Debug" arm_linker_heap_size="0" />
    </project>
+  <configuration build_remove_unused_symbols="Yes" arm_architecture="v7M" linker_printf_width_precision_supported="No" hidden="Yes" Name="debug" arm_core_type="Cortex-M3" />
+  <configuration inherited_configurations="debug;Flash" gcc_optimization_level="Level 1" Name="Flash Debug" />
+  <configuration linker_memory_map_file="$(StudioDir)/targets/Luminary_LM3S/LM3S101_MemoryMap.xml" c_preprocessor_definitions="GCC_ARMCM3_LM3S102" arm_linker_fiq_stack_size="0" linker_section_placement_file="$(StudioDir)/targets/Luminary_LM3S/flash_placement.xml" linker_additional_files="$(ProjectDir)/hw_include/libdriver.a" c_user_include_directories="$(ProjectDir)/demo1;$(ProjectDir)/../common/include;$(ProjectDir)/hw_include" arm_linker_irq_stack_size="0" link_symbol_definitions="" arm_linker_stack_size="200" Name="Common" c_system_include_directories="$(StudioDir)/include;$(ProjectDir)/../../source/include;$(ProjectDir)/../../source/portable/gcc/ARM_CM3" />
  </solution>
diff --git a/Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzs b/Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzs

index 4bc06d1fc1314e66aa9fa79207a706545e370b1f..db7d6d992e0b7b003c6dd0418cd69bf5e349b9aa 100644 (file)
--- a/Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzs
+++ b/Demo/CORTEX_LM3S102_Rowley/RTOSDemo.hzs
@@ -23,7 +23,7 @@
   </Breakpoints>
   <ExecutionCountWindow/>
   <Memory1>
-  <MemoryWindow autoEvaluate="0" addressText="0xe000e014" numColumns="8" sizeText="4" dataSize="1" radix="16" addressSpace="" />
+  <MemoryWindow autoEvaluate="0" addressText="0x20000000" numColumns="8" sizeText="2048" dataSize="1" radix="16" addressSpace="" />
   </Memory1>
   <Memory2>
    <MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="" dataSize="1" radix="16" addressSpace="" />
@@ -38,11 +38,10 @@
    <ProjectSessionItem path="RTOSDemo" name="unnamed" />
    <ProjectSessionItem path="RTOSDemo;Demo1" name="unnamed" />
    <ProjectSessionItem path="RTOSDemo;Demo1;Source Files" name="unnamed" />
-  <ProjectSessionItem path="RTOSDemo;Demo1;Source Files;RTOS Source" name="unnamed" />
+  <ProjectSessionItem path="RTOSDemo;Demo1;Source Files;Demo Source" name="unnamed" />
+  <ProjectSessionItem path="RTOSDemo;Demo1;System Files" name="unnamed" />
+  <ProjectSessionItem path="RTOSDemo;Demo2" name="unnamed" />
    <ProjectSessionItem path="RTOSDemo;Demo3" name="unnamed" />
-  <ProjectSessionItem path="RTOSDemo;Demo3;Source Files" name="unnamed" />
-  <ProjectSessionItem path="RTOSDemo;Demo3;Source Files;Demo Source" name="unnamed" />
-  <ProjectSessionItem path="RTOSDemo;Demo3;System Files" name="unnamed" />
   </Project>
   <Register1>
    <RegisterWindow unsignedDisplays="" asciiDisplays="" octalDisplays="" openGroups="CPU - Current Mode" visibleGroups="CPU - Current Mode" decimalDisplays="" binaryDisplays="" />
@@ -62,10 +61,10 @@
   </TraceWindow>
   <Watch1>
    <Watches active="1" >
-   <Watchpoint evalMode="0" linenumber="0" evalType="1" radix="-1" name="pxTopOfStack" expression="pxTopOfStack" filename="" />
+   <Watchpoint evalMode="1" linenumber="0" evalType="1" radix="-1" name="ulglob" expression="ulglob" filename="" />
     <Watchpoint linenumber="0" radix="-1" name="uxCriticalNesting" expression="uxCriticalNesting" filename="" />
-   <Watchpoint evalMode="1" linenumber="0" evalType="1" radix="-1" name="xHandle" expression="xHandle" filename="" />
-   <Watchpoint linenumber="0" radix="-1" name="xTickCount" expression="xTickCount" filename="" />
+   <Watchpoint evalMode="1" linenumber="0" evalType="1" radix="-1" name="pxCurrentTCB" expression="pxCurrentTCB" filename="" />
+   <Watchpoint linenumber="0" radix="16" name="ul" expression="ul" filename="" />
    </Watches>
   </Watch1>
   <Watch2>
@@ -77,18 +76,8 @@
   <Watch4>
    <Watches active="0" />
   </Watch4>
- <Files>
-  <SessionOpenFile useTextEdit="1" useBinaryEdit="0" x="1" debugPath="C:\E\Dev\FreeRTOS\Source\portable\GCC\ARM_CM3\port.c" y="102" useHTMLEdit="0" path="C:\E\Dev\FreeRTOS\Source\portable\GCC\ARM_CM3\port.c" left="0" selected="1" name="unnamed" top="257" />
-  <SessionOpenFile useTextEdit="1" useBinaryEdit="0" x="0" debugPath="C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\Demo3\main.c" y="117" useHTMLEdit="0" path="C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\Demo3\main.c" left="0" selected="0" name="unnamed" top="82" />
-  <SessionOpenFile useTextEdit="1" useBinaryEdit="0" x="0" debugPath="C:\E\Dev\FreeRTOS\Source\croutine.c" y="275" useHTMLEdit="0" path="C:\E\Dev\FreeRTOS\Source\croutine.c" left="0" selected="0" name="unnamed" top="258" />
-  <SessionOpenFile useTextEdit="1" useBinaryEdit="0" x="0" debugPath="C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\Demo3\vectors.s" y="79" useHTMLEdit="0" path="C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\Demo3\vectors.s" left="0" selected="0" name="unnamed" top="44" />
-  <SessionOpenFile useTextEdit="1" useBinaryEdit="0" x="0" debugPath="C:\E\Dev\FreeRTOS\Source\tasks.c" y="1181" useHTMLEdit="0" path="C:\E\Dev\FreeRTOS\Source\tasks.c" left="0" selected="0" name="unnamed" top="1166" />
-  <SessionOpenFile useTextEdit="1" useBinaryEdit="0" x="51" debugPath="C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\demo3\FreeRTOSConfig.h" y="49" useHTMLEdit="0" path="C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\demo3\FreeRTOSConfig.h" left="0" selected="0" name="unnamed" top="24" />
-  <SessionOpenFile useTextEdit="1" useBinaryEdit="0" x="24" debugPath="C:\E\Dev\FreeRTOS\Source\portable\GCC\ARM_CM3\portmacro.h" y="66" useHTMLEdit="0" path="C:\E\Dev\FreeRTOS\Source\portable\GCC\ARM_CM3\portmacro.h" left="0" selected="0" name="unnamed" top="56" />
-  <SessionOpenFile useTextEdit="1" useBinaryEdit="0" x="13" debugPath="C:\E\Dev\FreeRTOS\source\include\croutine.h" y="294" useHTMLEdit="0" path="C:\E\Dev\FreeRTOS\source\include\croutine.h" left="0" selected="0" name="unnamed" top="271" />
-  <SessionOpenFile useTextEdit="1" useBinaryEdit="0" x="35" debugPath="C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\Demo3\ParTest.c" y="49" useHTMLEdit="0" path="C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\Demo3\ParTest.c" left="0" selected="0" name="unnamed" top="28" />
- </Files>
- <ARMCrossStudioWindow activeProject="Demo3" autoConnectTarget="/CrossFire LM3S102" debugSearchFileMap="C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\hw_include\src\gpio.c
+ <Files/>
+ <ARMCrossStudioWindow activeProject="Demo1" autoConnectTarget="/USB CrossConnect for ARM" debugSearchFileMap="C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\hw_include\src\gpio.c
  C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley_\hw_include\src\gpio.c
  C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\hw_include\src\interrupt.c
  C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley_\hw_include\src\interrupt.c
@@ -97,5 +86,5 @@ C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley_\hw_include\src\ssi.c
  C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\hw_include\src\sysctl.c
  
  C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\hw_include\src\uart.c
-C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley_\hw_include\src\uart.c" fileDialogInitialDirectory="C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\Demo3" fileDialogDefaultFilter="*.asm;*.s;*.inc" autoConnectCapabilities="1919" debugSearchPath="" buildConfiguration="Flash Release" />
+C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley_\hw_include\src\uart.c" fileDialogInitialDirectory="C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S102_Rowley\Demo3" fileDialogDefaultFilter="*.asm;*.s;*.inc" autoConnectCapabilities="1919" debugSearchPath="" buildConfiguration="Flash Debug" />
  </session>
diff --git a/Demo/CORTEX_LM3S316_IAR/FreeRTOSConfig.h b/Demo/CORTEX_LM3S316_IAR/FreeRTOSConfig.h

new file mode 100644 (file)

index 0000000..c8cbb9e
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/FreeRTOSConfig.h
@@ -0,0 +1,76 @@
+/*\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+       This file is part of the FreeRTOS.org distribution.\r
+\r
+       FreeRTOS.org is free software; you can redistribute it and/or modify\r
+       it under the terms of the GNU General Public License as published by\r
+       the Free Software Foundation; either version 2 of the License, or\r
+       (at your option) any later version.\r
+\r
+       FreeRTOS.org is distributed in the hope that it will be useful,\r
+       but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+       GNU General Public License for more details.\r
+\r
+       You should have received a copy of the GNU General Public License\r
+       along with FreeRTOS.org; if not, write to the Free Software\r
+       Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\r
+\r
+       A special exception to the GPL can be applied should you wish to distribute\r
+       a combined work that includes FreeRTOS.org, without being obliged to provide\r
+       the source code for any proprietary components.  See the licensing section \r
+       of http://www.FreeRTOS.org for full details of how and when the exception\r
+       can be applied.\r
+\r
+       ***************************************************************************\r
+       See http://www.FreeRTOS.org for documentation, latest information, license \r
+       and contact details.  Please ensure to read the configuration and relevant \r
+       port sections of the online documentation.\r
+       ***************************************************************************\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION           1\r
+#define configUSE_IDLE_HOOK                    1\r
+#define configUSE_TICK_HOOK                    0\r
+#define configCPU_CLOCK_HZ                     ( ( unsigned portLONG ) 20000000 )\r
+#define configTICK_RATE_HZ                     ( ( portTickType ) 1000 )\r
+#define configMINIMAL_STACK_SIZE       ( ( unsigned portSHORT ) 70 )\r
+#define configTOTAL_HEAP_SIZE          ( ( size_t ) ( 3000 ) )\r
+#define configMAX_TASK_NAME_LEN                ( 3 )\r
+#define configUSE_TRACE_FACILITY       0\r
+#define configUSE_16_BIT_TICKS         0\r
+#define configIDLE_SHOULD_YIELD                0\r
+#define configUSE_CO_ROUTINES          1\r
+\r
+#define configMAX_PRIORITIES           ( ( unsigned portBASE_TYPE ) 2 )\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+\r
+#define INCLUDE_vTaskPrioritySet               0\r
+#define INCLUDE_uxTaskPriorityGet              0\r
+#define INCLUDE_vTaskDelete                            0\r
+#define INCLUDE_vTaskCleanUpResources  0\r
+#define INCLUDE_vTaskSuspend                   0\r
+#define INCLUDE_vTaskDelayUntil                        0\r
+#define INCLUDE_vTaskDelay                             1\r
+\r
+\r
+\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
diff --git a/Demo/CORTEX_LM3S316_IAR/ParTest/ParTest.c b/Demo/CORTEX_LM3S316_IAR/ParTest/ParTest.c

new file mode 100644 (file)

index 0000000..0426f1f
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/ParTest/ParTest.c
@@ -0,0 +1,112 @@
+/*\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+       This file is part of the FreeRTOS.org distribution.\r
+\r
+       FreeRTOS.org is free software; you can redistribute it and/or modify\r
+       it under the terms of the GNU General Public License as published by\r
+       the Free Software Foundation; either version 2 of the License, or\r
+       (at your option) any later version.\r
+\r
+       FreeRTOS.org is distributed in the hope that it will be useful,\r
+       but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+       GNU General Public License for more details.\r
+\r
+       You should have received a copy of the GNU General Public License\r
+       along with FreeRTOS.org; if not, write to the Free Software\r
+       Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\r
+\r
+       A special exception to the GPL can be applied should you wish to distribute\r
+       a combined work that includes FreeRTOS.org, without being obliged to provide\r
+       the source code for any proprietary components.  See the licensing section \r
+       of http://www.FreeRTOS.org for full details of how and when the exception\r
+       can be applied.\r
+\r
+       ***************************************************************************\r
+       See http://www.FreeRTOS.org for documentation, latest information, license \r
+       and contact details.  Please ensure to read the configuration and relevant \r
+       port sections of the online documentation.\r
+       ***************************************************************************\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple parallel port IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+/*\r
+*/\r
+\r
+\r
+#include "FreeRTOS.h"\r
+#include "Task.h"\r
+#include "partest.h"\r
+\r
+#include "pdc.h"\r
+\r
+#define partstPINS     (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 Z | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)\r
+\r
+#define partstALL_OUTPUTS_OFF  ( ( unsigned portCHAR ) 0x00 )\r
+#define partstMAX_OUTPUT_LED   ( ( unsigned portCHAR ) 8 )\r
+\r
+static volatile unsigned portCHAR ucOutputValue = partstALL_OUTPUTS_OFF;\r
+\r
+void vParTestInitialise( void )\r
+{\r
+       PDCInit();\r
+       PDCWrite( PDC_LED, ucOutputValue );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )\r
+{\r
+unsigned portCHAR ucBit = ( unsigned portCHAR ) 1;\r
+\r
+       vTaskSuspendAll();\r
+       {\r
+               if( uxLED < partstMAX_OUTPUT_LED )\r
+               {\r
+                       ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED;\r
+\r
+                       if( xValue == pdFALSE )\r
+                       {\r
+                               ucBit ^= ( unsigned portCHAR ) 0xff;\r
+                               ucOutputValue &= ucBit;\r
+                       }\r
+                       else\r
+                       {\r
+                               ucOutputValue |= ucBit;\r
+                       }\r
+\r
+                       PDCWrite( PDC_LED, ucOutputValue );\r
+               }       \r
+       }\r
+       xTaskResumeAll();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )\r
+{\r
+unsigned portCHAR ucBit;\r
+\r
+       vTaskSuspendAll();\r
+       {\r
+               if( uxLED < partstMAX_OUTPUT_LED )\r
+               {\r
+                       ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED;\r
+\r
+                       if( ucOutputValue & ucBit )\r
+                       {\r
+                               ucOutputValue &= ~ucBit;\r
+                       }\r
+                       else\r
+                       {\r
+                               ucOutputValue |= ucBit;\r
+                       }\r
+\r
+                       PDCWrite( PDC_LED, ucOutputValue );\r
+               }\r
+       }\r
+       xTaskResumeAll();\r
+}\r
+\r
diff --git a/Demo/CORTEX_LM3S316_IAR/RTOSDemo.dep b/Demo/CORTEX_LM3S316_IAR/RTOSDemo.dep

new file mode 100644 (file)

index 0000000..0e25ef4
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/RTOSDemo.dep
@@ -0,0 +1,535 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+  <fileVersion>2</fileVersion>\r
+  <configuration>\r
+    <name>Debug</name>\r
+    <outputs>\r
+      <file>$PROJ_DIR$\..\..\Source\croutine.c</file>\r
+      <file>$PROJ_DIR$\ewarm\Obj\cspy.pbi</file>\r
+      <file>$PROJ_DIR$\ewarm\Exe\RTOSDemo.sim</file>\r
+      <file>$PROJ_DIR$\ewarm\Obj\commstest.r79</file>\r
+      <file>$PROJ_DIR$\ewarm\Obj\pdc.r79</file>\r
+      <file>$PROJ_DIR$\ewarm\Obj\list.r79</file>\r
+      <file>$PROJ_DIR$\hw_include\hw_ssi.h</file>\r
+      <file>$PROJ_DIR$\ewarm\List\RTOSDemo.map</file>\r
+      <file>$PROJ_DIR$\..\..\Source\include\projdefs.h</file>\r
+      <file>$TOOLKIT_DIR$\inc\stddef.h</file>\r
+      <file>$PROJ_DIR$\hw_include\hw_uart.h</file>\r
+      <file>$PROJ_DIR$\standalone.xcl</file>\r
+      <file>$PROJ_DIR$\hw_include\debug.h</file>\r
+      <file>$PROJ_DIR$\hw_include\hw_adc.h</file>\r
+      <file>$PROJ_DIR$\hw_include\hw_i2c.h</file>\r
+      <file>$PROJ_DIR$\ewarm\Obj\registertest.r79</file>\r
+      <file>$PROJ_DIR$\ewarm\Obj\commstest.pbi</file>\r
+      <file>$PROJ_DIR$\ewarm\Obj\crhook.pbi</file>\r
+      <file>$PROJ_DIR$\..\..\Source\include\FreeRTOS.h</file>\r
+      <file>$PROJ_DIR$\hw_include\interrupt.h</file>\r
+      <file>$PROJ_DIR$\..\Common\include\crhook.h</file>\r
+      <file>$PROJ_DIR$\ewarm\Obj\ParTest.pbi</file>\r
+      <file>$PROJ_DIR$\ewarm\Obj\tasks.pbi</file>\r
+      <file>$PROJ_DIR$\ewarm\Obj\startup.pbi</file>\r
+      <file>$PROJ_DIR$\ewarm\Obj\crflash.pbi</file>\r
+      <file>$PROJ_DIR$\..\Common\Minimal\crflash.c</file>\r
+      <file>$PROJ_DIR$\ewarm\Obj\startup.r79</file>\r
+      <file>$PROJ_DIR$\..\..\Source\include\task.h</file>\r
+      <file>$TOOLKIT_DIR$\inc\stdio.h</file>\r
+      <file>$PROJ_DIR$\ewarm\Obj\croutine.pbi</file>\r
+      <file>$PROJ_DIR$\hw_include\i2c.h</file>\r
+      <file>$TOOLKIT_DIR$\inc\ysizet.h</file>\r
+      <file>$TOOLKIT_DIR$\lib\dl7mptnnl8n.r79</file>\r
+      <file>$PROJ_DIR$\hw_include\gpio.h</file>\r
+      <file>$PROJ_DIR$\hw_include\adc.h</file>\r
+      <file>$PROJ_DIR$\..\..\Source\include\queue.h</file>\r
+      <file>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portmacro.h</file>\r
+      <file>$PROJ_DIR$\ewarm\Obj\portasm.r79</file>\r
+      <file>$PROJ_DIR$\ewarm\Obj\tasks.r79</file>\r
+      <file>$PROJ_DIR$\ewarm\Obj\cspy.r79</file>\r
+      <file>$PROJ_DIR$\ewarm\Obj\port.r79</file>\r
+      <file>$PROJ_DIR$\ewarm\Obj\queue.r79</file>\r
+      <file>$PROJ_DIR$\hw_include\hw_ints.h</file>\r
+      <file>$TOOLKIT_DIR$\inc\xencoding_limits.h</file>\r
+      <file>$PROJ_DIR$\ewarm\Obj\crhook.r79</file>\r
+      <file>$PROJ_DIR$\ewarm\Obj\qs_dk-lm3s316.pbi</file>\r
+      <file>$PROJ_DIR$\ewarm\Exe\RTOSDemo.d79</file>\r
+      <file>$PROJ_DIR$\ewarm\Obj\crflash.r79</file>\r
+      <file>$PROJ_DIR$\FreeRTOSConfig.h</file>\r
+      <file>$PROJ_DIR$\..\Common\include\partest.h</file>\r
+      <file>$PROJ_DIR$\hw_include\sysctl.h</file>\r
+      <file>$PROJ_DIR$\hw_include\pdc.h</file>\r
+      <file>$PROJ_DIR$\hw_include\DriverLib.h</file>\r
+      <file>$PROJ_DIR$\ewarm\Obj\ParTest.r79</file>\r
+      <file>$PROJ_DIR$\ewarm\Obj\RTOSDemo.pbd</file>\r
+      <file>$PROJ_DIR$\qs_dk-lm3s316.c</file>\r
+      <file>$TOOLKIT_DIR$\inc\yvals.h</file>\r
+      <file>$PROJ_DIR$\ewarm\Obj\main.r79</file>\r
+      <file>$PROJ_DIR$\hw_include\hw_types.h</file>\r
+      <file>$PROJ_DIR$\..\..\Source\include\portable.h</file>\r
+      <file>$PROJ_DIR$\ewarm\Obj\list.pbi</file>\r
+      <file>$PROJ_DIR$\..\..\Source\include\croutine.h</file>\r
+      <file>$PROJ_DIR$\hw_include\ssi.h</file>\r
+      <file>$TOOLKIT_DIR$\inc\stdlib.h</file>\r
+      <file>$PROJ_DIR$\ewarm\Obj\queue.pbi</file>\r
+      <file>$PROJ_DIR$\ewarm\Obj\pdc.pbi</file>\r
+      <file>$TOOLKIT_DIR$\inc\string.h</file>\r
+      <file>$PROJ_DIR$\startup.c</file>\r
+      <file>$TOOLKIT_DIR$\inc\DLib_Threads.h</file>\r
+      <file>$PROJ_DIR$\..\..\utils\cspy.c</file>\r
+      <file>$PROJ_DIR$\ewarm\Obj\heap_1.r79</file>\r
+      <file>$PROJ_DIR$\..\Common\Minimal\crhook.c</file>\r
+      <file>$PROJ_DIR$\commstest.h</file>\r
+      <file>$PROJ_DIR$\ewarm\Obj\heap_1.pbi</file>\r
+      <file>$TOOLKIT_DIR$\inc\DLib_Defaults.h</file>\r
+      <file>$TOOLKIT_DIR$\inc\DLib_Product.h</file>\r
+      <file>$PROJ_DIR$\ewarm\Obj\croutine.r79</file>\r
+      <file>$PROJ_DIR$\..\..\Source\include\list.h</file>\r
+      <file>$PROJ_DIR$\..\Common\include\crflash.h</file>\r
+      <file>$PROJ_DIR$\hw_include\diag.h</file>\r
+      <file>$PROJ_DIR$\ewarm\Obj\qs_dk-lm3s316.r79</file>\r
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+      <file>$PROJ_DIR$\..\..\utils\pdc.c</file>\r
+      <file>$PROJ_DIR$\hw_include\hw_nvic.h</file>\r
+      <file>$TOOLKIT_DIR$\lib\dl7mptnnl8n.h</file>\r
+      <file>$PROJ_DIR$\commstest.c</file>\r
+      <file>$PROJ_DIR$\main.c</file>\r
+      <file>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_1.c</file>\r
+      <file>$PROJ_DIR$\ParTest\ParTest.c</file>\r
+      <file>$PROJ_DIR$\registertest.s</file>\r
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+      <file>$PROJ_DIR$\..\..\Source\queue.c</file>\r
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+      <file>$PROJ_DIR$\ewarm\Obj\port.pbi</file>\r
+      <file>$PROJ_DIR$\hw_include\cspy.c</file>\r
+      <file>$PROJ_DIR$\hw_include\pdc.c</file>\r
+      <file>$PROJ_DIR$\hw_include\startup.c</file>\r
+    </outputs>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\croutine.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
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+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 29</file>\r
+        </tool>\r
+      </outputs>\r
+      <inputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 18 9 56 74 86 75 43 68 31 8 48 59 36 27 77 61</file>\r
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+          <name>BICOMP</name>\r
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+        </tool>\r
+      </inputs>\r
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+    <file>\r
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+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 47</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
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+      </outputs>\r
+      <inputs>\r
+        <tool>\r
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+      <outputs>\r
+        <tool>\r
+          <name>XLINK</name>\r
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+      <inputs>\r
+        <tool>\r
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+    <file>\r
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+      <inputs>\r
+        <tool>\r
+          <name>BILINK</name>\r
+          <file> 21 16 24 29 1 73 60 81 65 98 64 23 22</file>\r
+        </tool>\r
+      </inputs>\r
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+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 80</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
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+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\startup.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 26</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 23</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\utils\cspy.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 39</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 1</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\crhook.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 44</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 17</file>\r
+        </tool>\r
+      </outputs>\r
+      <inputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 18 9 56 74 86 75 43 68 31 8 48 59 36 61 77 35 20</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 18 9 56 74 75 43 68 31 8 48 59 36 61 77 35 20</file>\r
+        </tool>\r
+      </inputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\utils\pdc.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 4</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 65</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>[ROOT_NODE]</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>XLINK</name>\r
+          <file> 46 7 2</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\commstest.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 3</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 16</file>\r
+        </tool>\r
+      </outputs>\r
+      <inputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 18 9 56 74 86 75 43 68 31 8 48 59 36 27 77 35 61 49 52 42 10 82 58 85 6 14 13 33 19 50 83 62 51 30 34</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 18 9 56 74 75 43 68 31 8 48 59 36 27 77 35 61 49 52 42 10 82 58 85 6 14 13 33 19 50 83 62 51 30 34</file>\r
+        </tool>\r
+      </inputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\main.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 57</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 81</file>\r
+        </tool>\r
+      </outputs>\r
+      <inputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 28 56 74 86 75 43 68 31 18 9 8 48 59 36 27 77 35 61 49 78 72 52 42 10 82 58 85 6 14 13 33 19 50 83 62 51 30 34</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 28 56 74 75 43 68 31 18 9 8 48 59 36 27 77 35 61 49 78 72 52 42 10 82 58 85 6 14 13 33 19 50 83 62 51 30 34</file>\r
+        </tool>\r
+      </inputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_1.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 70</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 73</file>\r
+        </tool>\r
+      </outputs>\r
+      <inputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 63 56 74 86 75 43 68 31 18 9 8 48 59 36 27 77</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 63 56 74 75 43 68 31 18 9 8 48 59 36 27 77</file>\r
+        </tool>\r
+      </inputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\ParTest\ParTest.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 53</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 21</file>\r
+        </tool>\r
+      </outputs>\r
+      <inputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 18 9 56 74 86 75 43 68 31 8 48 59 36 27 77 49 51</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 18 9 56 74 75 43 68 31 8 48 59 36 27 77 49 51</file>\r
+        </tool>\r
+      </inputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\registertest.s</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>AARM</name>\r
+          <file> 15</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\list.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 5</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 60</file>\r
+        </tool>\r
+      </outputs>\r
+      <inputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 63 56 74 86 75 43 68 31 18 9 8 48 59 36 77</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 63 56 74 75 43 68 31 18 9 8 48 59 36 77</file>\r
+        </tool>\r
+      </inputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 40</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 98</file>\r
+        </tool>\r
+      </outputs>\r
+      <inputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 18 9 56 74 86 75 43 68 31 8 48 59 36 27 77</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 18 9 56 74 75 43 68 31 8 48 59 36 27 77</file>\r
+        </tool>\r
+      </inputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>AARM</name>\r
+          <file> 37</file>\r
+        </tool>\r
+      </outputs>\r
+      <inputs>\r
+        <tool>\r
+          <name>AARM</name>\r
+          <file> 48</file>\r
+        </tool>\r
+      </inputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\queue.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 41</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 64</file>\r
+        </tool>\r
+      </outputs>\r
+      <inputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 63 56 74 86 75 43 68 31 66 18 9 8 48 59 36 27 77 61</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 63 56 74 75 43 68 31 66 18 9 8 48 59 36 27 77 61</file>\r
+        </tool>\r
+      </inputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\tasks.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 38</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 22</file>\r
+        </tool>\r
+      </outputs>\r
+      <inputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 28 56 74 86 75 43 68 31 63 66 18 9 8 48 59 36 27 77</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 28 56 74 75 43 68 31 63 66 18 9 8 48 59 36 27 77</file>\r
+        </tool>\r
+      </inputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\hw_include\cspy.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 39</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 1</file>\r
+        </tool>\r
+      </outputs>\r
+      <inputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 79</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 79</file>\r
+        </tool>\r
+      </inputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\hw_include\pdc.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 4</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 65</file>\r
+        </tool>\r
+      </outputs>\r
+      <inputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 82 58 12 33 62 50 51</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 82 58 12 33 62 50 51</file>\r
+        </tool>\r
+      </inputs>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\hw_include\startup.c</name>\r
+      <outputs>\r
+        <tool>\r
+          <name>ICCARM</name>\r
+          <file> 26</file>\r
+        </tool>\r
+        <tool>\r
+          <name>BICOMP</name>\r
+          <file> 23</file>\r
+        </tool>\r
+      </outputs>\r
+    </file>\r
+  </configuration>\r
+</project>\r
+\r
+\r
diff --git a/Demo/CORTEX_LM3S316_IAR/RTOSDemo.ewd b/Demo/CORTEX_LM3S316_IAR/RTOSDemo.ewd

new file mode 100644 (file)

index 0000000..6ce3c33
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/RTOSDemo.ewd
@@ -0,0 +1,509 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+  <fileVersion>1</fileVersion>\r
+  <configuration>\r
+    <name>Debug</name>\r
+    <toolchain>\r
+      <name>ARM</name>\r
+    </toolchain>\r
+    <debug>1</debug>\r
+    <settings>\r
+      <name>C-SPY</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>13</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CInput</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CEndian</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCVariant</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MacFile</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>MemOverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>MemFile</name>\r
+          <state>$TOOLKIT_DIR$\CONFIG\iolm3s101.ddf</state>\r
+        </option>\r
+        <option>\r
+          <name>RunToEnable</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>RunToName</name>\r
+          <state>main</state>\r
+        </option>\r
+        <option>\r
+          <name>CExtraOptionsCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CExtraOptions</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>CFpuProcessor</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDDFArgumentProducer</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadSuppressDownload</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadVerifyAll</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>OCProductVersion</name>\r
+          <state>4.39B</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDynDriverList</name>\r
+          <state>JLINK_ID</state>\r
+        </option>\r
+        <option>\r
+          <name>OCLastSavedByProductVersion</name>\r
+          <state>4.39B</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDownloadAttachToProgram</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>FlashLoaders</name>\r
+          <state>,,,,(default),</state>\r
+        </option>\r
+        <option>\r
+          <name>UseFlashLoader</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ARMSIM_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>OCSimDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ANGEL_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CCAngelHeartbeat</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommunication</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommBaud</name>\r
+          <version>0</version>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>CAngelCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>ANGELTCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoAngelLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>AngelLogFile</name>\r
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>IARROM_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CRomLogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomLogFileEditB</name>\r
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommunication</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRomCommBaud</name>\r
+          <version>0</version>\r
+          <state>7</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>JLINK_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>6</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>JLinkSpeed</name>\r
+          <state>32</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkDoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkLogFile</name>\r
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkHWResetDelay</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>JLinkInitialSpeed</name>\r
+          <state>32</state>\r
+        </option>\r
+        <option>\r
+          <name>CCDoJlinkMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCScanChainNonARMDevices</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkIRLength</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkCommRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkTCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkResetRadio</name>\r
+          <state>2</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkResetInitSeq</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkSpeedRadioV2</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCUSBDevice</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchUndef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchData</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchPrefetch</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkBreakpointRadio</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkDoUpdateBreakpoints</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCJLinkUpdateBreakpoints</name>\r
+          <state>main</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>MACRAIGOR_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>jtag</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuSpeed</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>TCPIP</name>\r
+          <state>aaa.bbb.ccc.ddd</state>\r
+        </option>\r
+        <option>\r
+          <name>DoLogfile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>LogFile</name>\r
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>DoEmuMultiTarget</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuMultiTarget</name>\r
+          <state>0@ARM7TDMI</state>\r
+        </option>\r
+        <option>\r
+          <name>EmuHWReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CEmuCommBaud</name>\r
+          <version>0</version>\r
+          <state>4</state>\r
+        </option>\r
+        <option>\r
+          <name>CEmuCommPort</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>jtago</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>UnusedAddr</name>\r
+          <state>0x00800000</state>\r
+        </option>\r
+        <option>\r
+          <name>CCMacraigorHWResetDelay</name>\r
+          <state></state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>RDI_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>1</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CRDIDriverDll</name>\r
+          <state>Browse to your RDI driver</state>\r
+        </option>\r
+        <option>\r
+          <name>CRDILogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CRDILogFileEdit</name>\r
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDIHWReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchReset</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchUndef</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchSWI</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchData</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchPrefetch</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchIRQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDICatchFIQ</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCRDIUseETM</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>THIRDPARTY_ID</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CThirdPartyDriverDll</name>\r
+          <state>Browse to your third-party driver</state>\r
+        </option>\r
+        <option>\r
+          <name>CThirdPartyLogFileCheck</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CThirdPartyLogFileEditB</name>\r
+          <state>$TOOLKIT_DIR$\cspycomm.log</state>\r
+        </option>\r
+        <option>\r
+          <name>OCDriverInfo</name>\r
+          <state>1</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <debuggerPlugins>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Profiling\Profiling.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$EW_DIR$\common\plugins\Stack\stack.ewplugin</file>\r
+        <loadFlag>1</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+      <plugin>\r
+        <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin</file>\r
+        <loadFlag>0</loadFlag>\r
+      </plugin>\r
+    </debuggerPlugins>\r
+  </configuration>\r
+</project>\r
+\r
+\r
diff --git a/Demo/CORTEX_LM3S316_IAR/RTOSDemo.ewp b/Demo/CORTEX_LM3S316_IAR/RTOSDemo.ewp

new file mode 100644 (file)

index 0000000..b63c9c7
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/RTOSDemo.ewp
@@ -0,0 +1,891 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+  <fileVersion>1</fileVersion>\r
+  <configuration>\r
+    <name>Debug</name>\r
+    <toolchain>\r
+      <name>ARM</name>\r
+    </toolchain>\r
+    <debug>1</debug>\r
+    <settings>\r
+      <name>General</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>9</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>GProcessorMode</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>ExePath</name>\r
+          <state>ewarm\Exe</state>\r
+        </option>\r
+        <option>\r
+          <name>ObjPath</name>\r
+          <state>ewarm\Obj</state>\r
+        </option>\r
+        <option>\r
+          <name>ListPath</name>\r
+          <state>ewarm\List</state>\r
+        </option>\r
+        <option>\r
+          <name>Variant</name>\r
+          <version>5</version>\r
+          <state>25</state>\r
+        </option>\r
+        <option>\r
+          <name>GEndianMode</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GInterwork</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GStackAlign</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>Input variant</name>\r
+          <version>1</version>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>Input description</name>\r
+          <state>No specifier n, no float nor long long, no scan set, no assignment suppressing.</state>\r
+        </option>\r
+        <option>\r
+          <name>Output variant</name>\r
+          <version>0</version>\r
+          <state>3</state>\r
+        </option>\r
+        <option>\r
+          <name>Output description</name>\r
+          <state>No specifier a, A, no specifier n, no float nor long long, no flags.</state>\r
+        </option>\r
+        <option>\r
+          <name>GOutputBinary</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>FPU</name>\r
+          <version>0</version>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OGCoreOrChip</name>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>GRuntimeLibSelect</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>GRuntimeLibSelectSlave</name>\r
+          <version>0</version>\r
+          <state>1</state>\r
+        </option>\r
+        <option>\r
+          <name>RTDescription</name>\r
+          <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\r
+        </option>\r
+        <option>\r
+          <name>RTConfigPath</name>\r
+          <state>$TOOLKIT_DIR$\LIB\dl7mptnnl8n.h</state>\r
+        </option>\r
+        <option>\r
+          <name>RTLibraryPath</name>\r
+          <state>$TOOLKIT_DIR$\LIB\dl7mptnnl8n.r79</state>\r
+        </option>\r
+        <option>\r
+          <name>OGProductVersion</name>\r
+          <state>4.39B</state>\r
+        </option>\r
+        <option>\r
+          <name>OGLastSavedByProductVersion</name>\r
+          <state>4.40A</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraRules</name>\r
+          <version>0</version>\r
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralEnableMisra</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>GeneralMisraVerbose</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>OGChipSelectEditMenu</name>\r
+          <state>LM3S316       Luminary LM3S316</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>ICCARM</name>\r
+      <archiveVersion>2</archiveVersion>\r
+      <data>\r
+        <version>13</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>CCDefines</name>\r
+          <state>BUILD_ALL</state>\r
+          <state>ewarm</state>\r
+          <state>IAR_ARMCM3_LM</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocComments</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCPreprocLine</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCFile</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCMnemonics</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListCMessages</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>CCListAssFile</name>\r
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+      <data>\r
+        <version>0</version>\r
+        <wantNonLocal>1</wantNonLocal>\r
+        <debug>1</debug>\r
+        <option>\r
+          <name>XARInputs</name>\r
+          <state></state>\r
+        </option>\r
+        <option>\r
+          <name>XAROverride</name>\r
+          <state>0</state>\r
+        </option>\r
+        <option>\r
+          <name>XAROutput</name>\r
+          <state>###Unitialized###</state>\r
+        </option>\r
+      </data>\r
+    </settings>\r
+    <settings>\r
+      <name>BILINK</name>\r
+      <archiveVersion>0</archiveVersion>\r
+      <data/>\r
+    </settings>\r
+  </configuration>\r
+  <group>\r
+    <name>Demo Source</name>\r
+    <file>\r
+      <name>$PROJ_DIR$\commstest.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\Common\Minimal\crflash.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\main.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\ParTest\ParTest.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\registertest.s</name>\r
+    </file>\r
+  </group>\r
+  <group>\r
+    <name>FreeRTOS Source</name>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\croutine.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\portable\MemMang\heap_1.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\list.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\queue.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\..\..\Source\tasks.c</name>\r
+    </file>\r
+  </group>\r
+  <group>\r
+    <name>Libraries</name>\r
+    <file>\r
+      <name>$PROJ_DIR$\hw_include\driverlib.r79</name>\r
+    </file>\r
+  </group>\r
+  <group>\r
+    <name>Luminary Code</name>\r
+    <file>\r
+      <name>$PROJ_DIR$\hw_include\cspy.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\hw_include\pdc.c</name>\r
+    </file>\r
+    <file>\r
+      <name>$PROJ_DIR$\hw_include\startup.c</name>\r
+    </file>\r
+  </group>\r
+</project>\r
+\r
+\r
diff --git a/Demo/CORTEX_LM3S316_IAR/RTOSDemo.eww b/Demo/CORTEX_LM3S316_IAR/RTOSDemo.eww

new file mode 100644 (file)

index 0000000..239a938
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/RTOSDemo.eww
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<workspace>\r
+  <project>\r
+    <path>$WS_DIR$\RTOSDemo.ewp</path>\r
+  </project>\r
+  <batchBuild/>\r
+</workspace>\r
+\r
+\r
diff --git a/Demo/CORTEX_LM3S316_IAR/commstest.c b/Demo/CORTEX_LM3S316_IAR/commstest.c

new file mode 100644 (file)

index 0000000..af2cbeb
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/commstest.c
@@ -0,0 +1,294 @@
+/*\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+       This file is part of the FreeRTOS.org distribution.\r
+\r
+       FreeRTOS.org is free software; you can redistribute it and/or modify\r
+       it under the terms of the GNU General Public License as published by\r
+       the Free Software Foundation; either version 2 of the License, or\r
+       (at your option) any later version.\r
+\r
+       FreeRTOS.org is distributed in the hope that it will be useful,\r
+       but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+       GNU General Public License for more details.\r
+\r
+       You should have received a copy of the GNU General Public License\r
+       along with FreeRTOS.org; if not, write to the Free Software\r
+       Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\r
+\r
+       A special exception to the GPL can be applied should you wish to distribute\r
+       a combined work that includes FreeRTOS.org, without being obliged to provide\r
+       the source code for any proprietary components.  See the licensing section \r
+       of http://www.FreeRTOS.org for full details of how and when the exception\r
+       can be applied.\r
+\r
+       ***************************************************************************\r
+       See http://www.FreeRTOS.org for documentation, latest information, license \r
+       and contact details.  Please ensure to read the configuration and relevant \r
+       port sections of the online documentation.\r
+       ***************************************************************************\r
+*/\r
+\r
+/*\r
+ * The comms test Rx and Tx task and co-routine.  See the comments at the top\r
+ * of main.c for full information.\r
+ */\r
+\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "croutine.h"\r
+\r
+/* Demo application include files. */\r
+#include "partest.h"\r
+\r
+/* Library include files. */\r
+#include "DriverLib.h"\r
+\r
+/* The LED's toggled by the various tasks. */\r
+#define commsFAIL_LED                  ( 7 )\r
+#define commsRX_LED                    ( 6 )\r
+#define commsTX_LED                    ( 5 )\r
+\r
+/* The length of the queue used to pass received characters to the Comms Rx\r
+task. */\r
+#define commsRX_QUEUE_LEN                      ( 5 )\r
+\r
+/* The baud rate used by the UART comms tasks/co-routine. */\r
+#define commsBAUD_RATE                         ( 57600 )\r
+\r
+/* FIFO setting for the UART.  The FIFO is not used to create a better test. */\r
+#define commsFIFO_SET                          ( 0x10 )\r
+\r
+/* The string that is transmitted on the UART contains sequentially the \r
+characters from commsFIRST_TX_CHAR to commsLAST_TX_CHAR. */\r
+#define commsFIRST_TX_CHAR '0'\r
+#define commsLAST_TX_CHAR 'z'\r
+\r
+/* Just used to walk through the program memory in order that some random data\r
+can be generated. */\r
+#define commsTOTAL_PROGRAM_MEMORY ( ( unsigned portLONG * ) ( 8 * 1024 ) )\r
+#define commsFIRST_PROGRAM_BYTES ( ( unsigned portLONG * ) 4 )\r
+\r
+/* The time between transmissions of the string on UART 0.   This is pseudo\r
+random in order to generate a bit or randomness to when the interrupts occur.*/\r
+#define commsMIN_TX_DELAY                      ( 40 / portTICK_RATE_MS )\r
+#define commsMAX_TX_DELAY                      ( ( portTickType ) 0x7f )\r
+#define commsOFFSET_TIME                       ( ( portTickType ) 3 )\r
+\r
+/* The time the Comms Rx task should wait to receive a character.  This should\r
+be slightly longer than the time between transmissions.  If we do not receive\r
+a character after this time then there must be an error in the transmission or\r
+the timing of the transmission. */\r
+#define commsRX_DELAY                  ( commsMAX_TX_DELAY + 20 )\r
+\r
+\r
+static unsigned portBASE_TYPE uxCommsErrorStatus = pdPASS;\r
+\r
+/* The queue used to pass characters out of the ISR. */\r
+static xQueueHandle xCommsQueue;\r
+\r
+/* The next character to transmit. */\r
+static portCHAR cNextChar;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialInit( void )\r
+{\r
+       /* Create the queue used to communicate between the UART ISR and the Comms\r
+       Rx task. */\r
+       xCommsQueue = xQueueCreate( commsRX_QUEUE_LEN, sizeof( portCHAR ) );\r
+\r
+       /* Enable the UART.  GPIOA has already been initialised. */\r
+       SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);\r
+\r
+       /* Set GPIO A0 and A1 as peripheral function.  They are used to output the\r
+       UART signals. */\r
+       GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW );\r
+\r
+       /* Configure the UART for 8-N-1 operation. */\r
+       UARTConfigSet( UART0_BASE, commsBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE );\r
+\r
+       /* We dont want to use the fifo.  This is for test purposes to generate\r
+       as many interrupts as possible. */\r
+       HWREG( UART0_BASE + UART_O_LCR_H ) &= ~commsFIFO_SET;\r
+\r
+       /* Enable both Rx and Tx interrupts. */\r
+       HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX );\r
+       IntEnable( INT_UART0 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+{\r
+portTickType xDelayPeriod;\r
+static unsigned portLONG *pulRandomBytes = commsFIRST_PROGRAM_BYTES;\r
+\r
+       /* Co-routine MUST start with a call to crSTART. */\r
+       crSTART( xHandle );\r
+\r
+       for(;;)\r
+    {  \r
+               /* Was the previously transmitted string received correctly? */\r
+               if( uxCommsErrorStatus != pdPASS )\r
+               {\r
+                       /* An error was encountered so set the error LED. */\r
+                       vParTestSetLED( commsFAIL_LED, pdTRUE );\r
+               }\r
+\r
+               /* The next character to Tx is the first in the string. */\r
+               cNextChar = commsFIRST_TX_CHAR;\r
+\r
+               UARTIntDisable( UART0_BASE, UART_INT_TX );\r
+               {\r
+                       /* Send the first character. */\r
+                       if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) )\r
+                       {\r
+                               HWREG( UART0_BASE + UART_O_DR ) = cNextChar;\r
+                       }\r
+\r
+                       /* Move the variable to the char to Tx on so the ISR transmits\r
+                       the next character in the string once this one has completed. */\r
+                       cNextChar++;\r
+               }\r
+               UARTIntEnable(UART0_BASE, UART_INT_TX);\r
+\r
+               /* Toggle the LED to show a new string is being transmitted. */\r
+        vParTestToggleLED( commsTX_LED );\r
+\r
+               /* Delay before we start the string off again.  A pseudo-random delay\r
+               is used as this will provide a better test. */\r
+               xDelayPeriod = xTaskGetTickCount() + ( *pulRandomBytes );\r
+\r
+               pulRandomBytes++;\r
+               if( pulRandomBytes > commsTOTAL_PROGRAM_MEMORY )\r
+               {\r
+                       pulRandomBytes = commsFIRST_PROGRAM_BYTES;\r
+               }\r
+\r
+               /* Make sure we don't wait too long... */\r
+               xDelayPeriod &= commsMAX_TX_DELAY;\r
+\r
+               /* ...but we do want to wait. */\r
+               if( xDelayPeriod < commsMIN_TX_DELAY )\r
+               {\r
+                       xDelayPeriod = commsMIN_TX_DELAY;\r
+               }\r
+\r
+               /* Block for the random(ish) time. */\r
+               crDELAY( xHandle, xDelayPeriod );\r
+    }\r
+\r
+       /* Co-routine MUST end with a call to crEND. */\r
+       crEND();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vUART_ISR( void )\r
+{\r
+unsigned portLONG ulStatus;\r
+portCHAR cRxedChar;\r
+portBASE_TYPE xTaskWokenByPost = pdFALSE;\r
+\r
+       /* What caused the interrupt. */\r
+       ulStatus = UARTIntStatus( UART0_BASE, pdTRUE );\r
+\r
+       /* Clear the interrupt. */\r
+       UARTIntClear( UART0_BASE, ulStatus );\r
+\r
+       /* Was an Rx interrpt pending? */\r
+       if( ulStatus & UART_INT_RX )\r
+       {\r
+               if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) )\r
+               {\r
+                       /* Get the char from the buffer and post it onto the queue of\r
+                       Rxed chars.  Posting the character should wake the task that is \r
+                       blocked on the queue waiting for characters. */\r
+                       cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR );\r
+                       xTaskWokenByPost = xQueueSendFromISR( xCommsQueue, &cRxedChar, xTaskWokenByPost );\r
+               }               \r
+       }\r
+\r
+       /* Was a Tx interrupt pending? */\r
+       if( ulStatus & UART_INT_TX )\r
+       {\r
+               /* Send the next character in the string.  We are not using the FIFO. */\r
+               if( cNextChar <= commsLAST_TX_CHAR )\r
+               {\r
+                       if( !( HWREG( UART0_BASE + UART_O_FR ) & UART_FR_TXFF ) )\r
+                       {\r
+                               HWREG( UART0_BASE + UART_O_DR ) = cNextChar;\r
+                       }\r
+                       cNextChar++;\r
+               }\r
+       }\r
+       \r
+       if( xTaskWokenByPost )\r
+       {\r
+               /* If a task was woken by the character being received then we force\r
+               a context switch to occur in case the task is of higher priority than\r
+               the currently executing task (i.e. the task that this interrupt \r
+               interrupted.) */\r
+               portEND_SWITCHING_ISR( xTaskWokenByPost );\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vCommsRxTask( void * pvParameters )\r
+{\r
+static portCHAR cRxedChar, cExpectedChar;\r
+\r
+       /* Set the char we expect to receive to the start of the string. */\r
+       cExpectedChar = commsFIRST_TX_CHAR;\r
+\r
+       for( ;; )\r
+       {\r
+               /* Wait for a character to be received. */\r
+               xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, commsRX_DELAY );\r
+\r
+               /* Was the character recived (if any) the expected character. */\r
+               if( cRxedChar != cExpectedChar )\r
+               {\r
+                       /* Got an unexpected character.  This can sometimes occur when\r
+                       reseting the system using the debugger leaving characters already\r
+                       in the UART regsters. */\r
+                       uxCommsErrorStatus = pdFAIL;\r
+\r
+                       /* Resync by waiting for the end of the current string. */\r
+                       while( cRxedChar != commsLAST_TX_CHAR )\r
+                       {\r
+                               while( !xQueueReceive( xCommsQueue, ( void * ) &cRxedChar, portMAX_DELAY ) );\r
+                       }\r
+\r
+                       /* The next expected character is the start of the string again. */\r
+                       cExpectedChar = commsFIRST_TX_CHAR;\r
+               }\r
+               else\r
+               {\r
+                       if( cExpectedChar == commsLAST_TX_CHAR )\r
+                       {\r
+                               /* We have reached the end of the string - we now expect to \r
+                               receive the first character in the string again.   The LED is \r
+                               toggled to indicate that the entire string was received without\r
+                               error. */\r
+                               vParTestToggleLED( commsRX_LED );\r
+                               cExpectedChar = commsFIRST_TX_CHAR;\r
+                       }\r
+                       else\r
+                       {\r
+                               /* We got the expected character, we now expect to receive the\r
+                               next character in the string. */\r
+                               cExpectedChar++;\r
+                       }\r
+               }\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+unsigned portBASE_TYPE uxGetCommsStatus( void )\r
+{\r
+       return uxCommsErrorStatus;\r
+}\r
diff --git a/Demo/CORTEX_LM3S316_IAR/commstest.h b/Demo/CORTEX_LM3S316_IAR/commstest.h

new file mode 100644 (file)

index 0000000..12d7591
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/commstest.h
@@ -0,0 +1,54 @@
+/*\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+       This file is part of the FreeRTOS.org distribution.\r
+\r
+       FreeRTOS.org is free software; you can redistribute it and/or modify\r
+       it under the terms of the GNU General Public License as published by\r
+       the Free Software Foundation; either version 2 of the License, or\r
+       (at your option) any later version.\r
+\r
+       FreeRTOS.org is distributed in the hope that it will be useful,\r
+       but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+       GNU General Public License for more details.\r
+\r
+       You should have received a copy of the GNU General Public License\r
+       along with FreeRTOS.org; if not, write to the Free Software\r
+       Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\r
+\r
+       A special exception to the GPL can be applied should you wish to distribute\r
+       a combined work that includes FreeRTOS.org, without being obliged to provide\r
+       the source code for any proprietary components.  See the licensing section \r
+       of http://www.FreeRTOS.org for full details of how and when the exception\r
+       can be applied.\r
+\r
+       ***************************************************************************\r
+       See http://www.FreeRTOS.org for documentation, latest information, license \r
+       and contact details.  Please ensure to read the configuration and relevant \r
+       port sections of the online documentation.\r
+       ***************************************************************************\r
+*/\r
+\r
+#ifndef COMMS_TEST_H\r
+#define COMMS_TEST_H\r
+\r
+/*\r
+ * Initialisation routine for the UART.\r
+ */\r
+void vSerialInit( void );\r
+\r
+/*\r
+ * The task that receives the characters from UART 0.\r
+ */\r
+void vCommsRxTask( void * pvParameters );\r
+\r
+/*\r
+ * The co-routine that periodically initiates the transmission of the string on\r
+ * the UART.\r
+ */\r
+void vSerialTxCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex );\r
+\r
+unsigned portBASE_TYPE uxGetCommsStatus( void );\r
+\r
+#endif\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/DriverLib.h b/Demo/CORTEX_LM3S316_IAR/hw_include/DriverLib.h

new file mode 100644 (file)

index 0000000..6374ddc
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/DriverLib.h
@@ -0,0 +1,22 @@
+#ifndef INCLUDE_DRIVER_LIB_H\r
+#define INCLUDE_DRIVER_LIB_H\r
+\r
+#include "hw_ints.h"\r
+#include "hw_uart.h"\r
+#include "hw_memmap.h"\r
+#include "hw_types.h"\r
+#include "hw_nvic.h"\r
+#include "hw_ssi.h"\r
+#include "hw_i2c.h"\r
+#include "hw_adc.h"\r
+\r
+#include "gpio.h"\r
+#include "interrupt.h"\r
+#include "sysctl.h"\r
+#include "uart.h"\r
+#include "ssi.h"\r
+#include "pdc.h"\r
+#include "i2c.h"\r
+#include "adc.h"\r
+\r
+#endif\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/EULA.txt b/Demo/CORTEX_LM3S316_IAR/hw_include/EULA.txt

new file mode 100644 (file)

index 0000000..cba31f7
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/EULA.txt
@@ -0,0 +1,126 @@
+IMPORTANT.  Read the following LMI Software License Agreement ("Agreement")\r
+completely.\r
+\r
+LUMINARY MICRO SOFTWARE LICENSE AGREEMENT\r
+\r
+        This is a legal agreement between you (either as an individual or as an\r
+authorized representative of your employer) and Luminary Micro, Inc. ("LMI").\r
+It concerns your rights to use this file and any accompanying written materials\r
+(the "Software").  In consideration for LMI allowing you to access the\r
+Software, you are agreeing to be bound by the terms of this Agreement.  If you\r
+do not agree to all of the terms of this Agreement, do not download or use the\r
+Software.  If you change your mind later, stop using the Software and delete\r
+all copies of the Software in your possession or control.  Any copies of the\r
+Software that you have already distributed, where permitted, and do not destroy\r
+will continue to be governed by this Agreement.  Your prior use will also\r
+continue to be governed by this Agreement.\r
+\r
+1.      LICENSE GRANT.  LMI grants to you, free of charge, the non-exclusive,\r
+non-transferable right (1) to use the Software, (2) to reproduce the Software,\r
+(3) to prepare derivative works of the Software, (4) to distribute the Software\r
+and derivative works thereof in source (human-readable) form and object\r
+(machine-readable) form, and (5) to sublicense to others the right to use the\r
+distributed Software.  If you violate any of the terms or restrictions of this\r
+Agreement, LMI may immediately terminate this Agreement, and require that you\r
+stop using and delete all copies of the Software in your possession or control.\r
+\r
+2.      COPYRIGHT.  The Software is licensed to you, not sold. LMI owns the\r
+Software, and United States copyright laws and international treaty provisions\r
+protect the Software.  Therefore, you must treat the Software like any other\r
+copyrighted material (e.g. a book or musical recording).  You may not use or\r
+copy the Software for any other purpose than what is described in this\r
+Agreement.  Except as expressly provided herein, LMI does not grant to you any\r
+express or implied rights under any LMI or third-party patents, copyrights,\r
+trademarks, or trade secrets.  Additionally, you must reproduce and apply any\r
+copyright or other proprietary rights notices included on or embedded in the\r
+Software to any copies or derivative works made thereof, in whole or in part,\r
+if any.\r
+\r
+3.      SUPPORT.  LMI is NOT obligated to provide any support, upgrades or new\r
+releases of the Software.  If you wish, you may contact LMI and report problems\r
+and provide suggestions regarding the Software.  LMI has no obligation\r
+whatsoever to respond in any way to such a problem report or suggestion.  LMI\r
+may make changes to the Software at any time, without any obligation to notify\r
+or provide updated versions of the Software to you.\r
+\r
+4.      INDEMNITY.  You agree to fully defend and indemnify LMI from any and\r
+all claims, liabilities, and costs (including reasonable attorney\92s fees)\r
+related to (1) your use (including your sub-licensee\92s use, if permitted) of\r
+the Software or (2) your violation of the terms and conditions of this\r
+Agreement.\r
+\r
+5.      HIGH RISK ACTIVITIES.  You acknowledge that the Software is not fault\r
+tolerant and is not designed, manufactured or intended by LMI for incorporation\r
+into products intended for use or resale in on-line control equipment in\r
+hazardous, dangerous to life or potentially life-threatening environments\r
+requiring fail-safe performance, such as in the operation of nuclear\r
+facilities, aircraft navigation or communication systems, air traffic control,\r
+direct life support machines or weapons systems, in which the failure of\r
+products could lead directly to death, personal injury or severe physical or\r
+environmental damage ("High Risk Activities").  You specifically represent and\r
+warrant that you will not use the Software or any derivative work of the\r
+Software for High Risk Activities.\r
+\r
+6.      PRODUCT LABELING.  You are not authorized to use any LMI trademarks,\r
+brand names, or logos.\r
+\r
+7.      COMPLIANCE WITH LAWS; EXPORT RESTRICTIONS.  You must use the Software\r
+in accordance with all applicable U.S. laws, regulations and statutes.  You\r
+agree that neither you nor your licensees (if any) intend to or will, directly\r
+or indirectly, export or transmit the Software to any country in violation of\r
+U.S. export restrictions.\r
+\r
+8.      GOVERNMENT USE.  Use of the Software and any corresponding\r
+documentation, if any, is provided with RESTRICTED RIGHTS.  Use, duplication or\r
+disclosure by the Government is subject to restrictions as set forth in\r
+subparagraph (c)(1)(ii) of The Rights in Technical Data and Computer Software\r
+clause at DFARS 252.227-7013 or subparagraphs (c)(l) and (2) of the Commercial\r
+Computer Software--Restricted Rights at 48 CFR 52.227-19, as applicable.\r
+Manufacturer is Luminary Micro, Inc., 2499 S. Capital of Texas Hwy Ste A-100,\r
+Austin, Texas 78746.\r
+\r
+9.      DISCLAIMER OF WARRANTY.  TO THE MAXIMUM EXTENT PERMITTED BY LAW, LMI\r
+EXPRESSLY DISCLAIMS ANY WARRANTY FOR THE SOFTWARE.  THE SOFTWARE IS PROVIDED\r
+"AS IS", WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING,\r
+WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A\r
+PARTICULAR PURPOSE, OR NON-INFRINGEMENT.  YOU ASSUME THE ENTIRE RISK ARISING\r
+OUT OF THE USE OR PERFORMANCE OF THE SOFTWARE, OR ANY SYSTEMS YOU DESIGN USING\r
+THE SOFTWARE (IF ANY).  NOTHING IN THIS AGREEMENT MAY BE CONSTRUED AS A\r
+WARRANTY OR REPRESENTATION BY LMI THAT THE SOFTWARE OR ANY DERIVATIVE WORK\r
+DEVELOPED WITH OR INCORPORATING THE SOFTWARE WILL BE FREE FROM INFRINGEMENT OF\r
+THE INTELLECTUAL PROPERTY RIGHTS OF THIRD PARTIES.\r
+\r
+10.     LIMITATION OF LIABILITY.  IN NO EVENT WILL LMI BE LIABLE, WHETHER IN\r
+CONTRACT, TORT, OR OTHERWISE, FOR ANY INCIDENTAL, SPECIAL, INDIRECT,\r
+CONSEQUENTIAL OR PUNITIVE DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR\r
+ANY LOSS OF USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST PROFITS,\r
+SAVINGS, OR REVENUES TO THE FULL EXTENT SUCH MAY BE DISCLAIMED BY LAW.\r
+\r
+11.     CHOICE OF LAW; VENUE; LIMITATIONS.  You agree that the statutes and\r
+laws of the United States and the State of Texas, USA, without regard to\r
+conflicts of laws principles, will apply to all matters relating to this\r
+Agreement or the Software, and you agree that any litigation will be subject to\r
+the exclusive jurisdiction of the state or federal courts in Austin, Travis\r
+County, Texas, USA.  You agree that regardless of any statute or law to the\r
+contrary, any claim or cause of action arising out of or related to this\r
+Agreement or the Software must be filed within one (1) year after such claim or\r
+cause of action arose or be forever barred.\r
+\r
+12.     ENTIRE AGREEMENT.  This Agreement constitutes the entire agreement\r
+between you and LMI regarding the subject matter of this Agreement, and\r
+supersedes all prior communications, negotiations, understandings, agreements\r
+or representations, either written or oral, if any.  This Agreement may only be\r
+amended in written form, executed by you and LMI.\r
+\r
+13.     SEVERABILITY.  If any provision of this Agreement is held for any\r
+reason to be invalid or unenforceable, then the remaining provisions of this\r
+Agreement will be unimpaired and, unless a modification or replacement of the\r
+invalid or unenforceable provision is further held to deprive you or LMI of a\r
+material benefit, in which case the Agreement will immediately terminate, the\r
+invalid or unenforceable provision will be replaced with a provision that is\r
+valid and enforceable and that comes closest to the intention underlying the\r
+invalid or unenforceable provision.\r
+\r
+14.     NO WAIVER.  The waiver by LMI of any breach of any provision of this\r
+Agreement will not operate or be construed as a waiver of any other or a\r
+subsequent breach of the same or a different provision.\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/RTOSDemo_lnk.xcl b/Demo/CORTEX_LM3S316_IAR/hw_include/RTOSDemo_lnk.xcl

new file mode 100644 (file)

index 0000000..d937b98
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/RTOSDemo_lnk.xcl
@@ -0,0 +1,192 @@
+// Generated : 06/01/06 20:29:52\r
+//**********************************************************************\r
+// XLINK template command file to be used with the ICCARM C/C++ Compiler\r
+//\r
+// Usage:  xlink  -f lnkarm  <your_object_file(s)>\r
+//                -s <program start label>  <C/C++ runtime library>\r
+//\r
+// $Revision: 1.3 $\r
+//\r
+//**********************************************************************\r
+\r
+//*************************************************************************\r
+// In this file it is assumed that the system has the following\r
+// memory layout:\r
+//\r
+//   Exception vectors [0x000000--0x00001F]  RAM or ROM\r
+//   ROMSTART--ROMEND  [0x008000--0x0FFFFF]  ROM (or other non-volatile memory)\r
+//   RAMSTART--RAMEND  [0x100000--0x7FFFFF]  RAM (or other read/write memory)\r
+//\r
+// -------------\r
+// Code segments - may be placed anywhere in memory.\r
+// -------------\r
+//\r
+//   INTVEC     -- Exception vector table.\r
+//   SWITAB     -- Software interrupt vector table.\r
+//   ICODE      -- Startup (cstartup) and exception code.\r
+//   DIFUNCT    -- Dynamic initialization vectors used by C++.\r
+//   CODE       -- Compiler generated code.\r
+//   CODE_I     -- Compiler generated code declared __ramfunc (executes in RAM)\r
+//   CODE_ID    -- Initializer for CODE_I (ROM).\r
+//\r
+// -------------\r
+// Data segments - may be placed anywhere in memory.\r
+// -------------\r
+//\r
+//   CSTACK     -- The stack used by C/C++ programs (system and user mode).\r
+//   IRQ_STACK  -- The stack used by IRQ service routines.\r
+//   SVC_STACK  -- The stack used in supervisor mode\r
+//                 (Define other exception stacks as needed for\r
+//                 FIQ, ABT, UND).\r
+//   HEAP       -- The heap used by malloc and free in C and new and\r
+//                 delete in C++.\r
+//   INITTAB    -- Table containing addresses and sizes of segments that\r
+//                 need to be initialized at startup (by cstartup).\r
+//   CHECKSUM   -- The linker places checksum byte(s) in this segment,\r
+//                 when the -J linker command line option is used.\r
+//   DATA_y     -- Data objects.\r
+//\r
+// Where _y can be one of:\r
+//\r
+//   _AN        -- Holds uninitialized located objects, i.e. objects with\r
+//                 an absolute location given by the @ operator or the\r
+//                 #pragma location directive. Since these segments\r
+//                 contain objects which already have a fixed address,\r
+//                 they should not be mentioned in this linker command\r
+//                 file.\r
+//   _C         -- Constants (ROM).\r
+//   _I         -- Initialized data (RAM).\r
+//   _ID        -- The original content of _I (copied to _I by cstartup) (ROM).\r
+//   _N         -- Uninitialized data (RAM).\r
+//   _Z         -- Zero initialized data (RAM).\r
+//\r
+// Note:  Be sure to use end values for the defined address ranges.\r
+//        Otherwise, the linker may allocate space outside the\r
+//        intended memory range.\r
+//*************************************************************************\r
+\r
+//************************************************\r
+// Inform the linker about the CPU family used.\r
+//************************************************\r
+\r
+-carm\r
+\r
+//*************************************************************************\r
+// Segment placement - General information\r
+//\r
+// All numbers in the segment placement command lines below are interpreted\r
+// as hexadecimal unless they are immediately preceded by a '.', which\r
+// denotes decimal notation. \r
+//\r
+// When specifying the segment placement using the -P instead of the -Z\r
+// option, the linker is free to split each segment into its segment parts\r
+// and randomly place these parts within the given ranges in order to\r
+// achieve a more efficient memory usage. One disadvantage, however, is\r
+// that it is not possible to find the start or end address (using\r
+// the assembler operators .sfb./.sfe.) of a segment which has been split\r
+// and reformed. \r
+//\r
+// When generating an output file which is to be used for programming\r
+// external ROM/Flash devices, the -M linker option is very useful \r
+// (see xlink.pdf for details).\r
+//*************************************************************************\r
+\r
+\r
+//*************************************************************************\r
+// Read-only segments mapped to ROM.\r
+//*************************************************************************\r
+\r
+//************************************************\r
+// Address range for reset and exception\r
+// vectors (INTVEC).\r
+// The vector area is 32 bytes, \r
+// an additional 32 bytes is allocated for the\r
+// constant table used by ldr PC in cstartup.s79.\r
+//************************************************\r
+\r
+-Z(CODE)INTVEC=0-3F\r
+\r
+//************************************************\r
+// Startup code and exception routines (ICODE).\r
+//************************************************\r
+\r
+-Z(CODE)ICODE,DIFUNCT=8000-FFFFF\r
+-Z(CODE)SWITAB=8000-FFFFF\r
+\r
+//************************************************\r
+// Code segments may be placed anywhere.\r
+//************************************************\r
+\r
+-Z(CODE)CODE=8000-FFFFF\r
+\r
+//************************************************\r
+// Original ROM location for __ramfunc code copied\r
+// to and executed from RAM.\r
+//************************************************\r
+\r
+-Z(CONST)CODE_ID=8000-FFFFF\r
+\r
+//************************************************\r
+// Various constants and initializers.\r
+//************************************************\r
+\r
+-Z(CONST)INITTAB,DATA_ID,DATA_C=8000-FFFFF\r
+-Z(CONST)CHECKSUM=8000-FFFFF\r
+\r
+//*************************************************************************\r
+// Read/write segments mapped to RAM.\r
+//*************************************************************************\r
+\r
+//************************************************\r
+// Data segments.\r
+//************************************************\r
+\r
+-Z(DATA)DATA_I,DATA_Z,DATA_N=100000-7FFFFF\r
+\r
+//************************************************\r
+// __ramfunc code copied to and executed from RAM.\r
+//************************************************\r
+\r
+-Z(DATA)CODE_I=100000-7FFFFF\r
+\r
+//************************************************\r
+// ICCARM produces code for __ramfunc functions in\r
+// CODE_I segments. The -Q XLINK command line\r
+// option redirects XLINK to emit the code in the\r
+// CODE_ID segment instead, but to keep symbol and\r
+// debug information associated with the CODE_I\r
+// segment, where the code will execute.\r
+//************************************************\r
+\r
+-QCODE_I=CODE_ID\r
+\r
+//*************************************************************************\r
+// Stack and heap segments.\r
+//*************************************************************************\r
+\r
+-Z(DATA)CSTACK+200=100000-7FFFFF\r
+-Z(DATA)IRQ_STACK+100=100000-7FFFFF\r
+-Z(DATA)HEAP+8000=100000-7FFFFF\r
+\r
+//**********************************************************************\r
+// Output user defined segments\r
+//**********************************************************************\r
+\r
+\r
+\r
+//*************************************************************************\r
+// ELF/DWARF support.\r
+//\r
+// Uncomment the line "-Felf" below to generate ELF/DWARF output.\r
+// Available format specifiers are:\r
+//\r
+//   "-yn": Suppress DWARF debug output\r
+//   "-yp": Multiple ELF program sections\r
+//   "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag)\r
+//\r
+// "-Felf" and the format specifiers can also be supplied directly as\r
+// command line options, or selected from the Xlink Output tab in the\r
+// IAR Embedded Workbench.\r
+//*************************************************************************\r
+\r
+// -Felf\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/adc.h b/Demo/CORTEX_LM3S316_IAR/hw_include/adc.h

new file mode 100644 (file)

index 0000000..1825664
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/adc.h
@@ -0,0 +1,120 @@
+//*****************************************************************************\r
+//\r
+// adc.h - ADC headers for using the ADC driver functions.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __ADC_H__\r
+#define __ADC_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ADCSequenceConfigure as the ulTrigger\r
+// parameter.\r
+//\r
+//*****************************************************************************\r
+#define ADC_TRIGGER_PROCESSOR   0x00000000  // Processor event\r
+#define ADC_TRIGGER_COMP0       0x00000001  // Analog comparator 0 event\r
+#define ADC_TRIGGER_COMP1       0x00000002  // Analog comparator 1 event\r
+#define ADC_TRIGGER_COMP2       0x00000003  // Analog comparator 2 event\r
+#define ADC_TRIGGER_EXTERNAL    0x00000004  // External event\r
+#define ADC_TRIGGER_TIMER       0x00000005  // Timer event\r
+#define ADC_TRIGGER_PWM0        0x00000006  // PWM0 event\r
+#define ADC_TRIGGER_PWM1        0x00000007  // PWM1 event\r
+#define ADC_TRIGGER_PWM2        0x00000008  // PWM2 event\r
+#define ADC_TRIGGER_ALWAYS      0x0000000F  // Always event\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ADCSequenceStepConfigure as the ulConfig\r
+// parameter.\r
+//\r
+//*****************************************************************************\r
+#define ADC_CTL_TS              0x00000080  // Temperature sensor select\r
+#define ADC_CTL_IE              0x00000040  // Interrupt enable\r
+#define ADC_CTL_END             0x00000020  // Sequence end select\r
+#define ADC_CTL_D               0x00000010  // Differential select\r
+#define ADC_CTL_CH0             0x00000000  // Input channel 0\r
+#define ADC_CTL_CH1             0x00000001  // Input channel 1\r
+#define ADC_CTL_CH2             0x00000002  // Input channel 2\r
+#define ADC_CTL_CH3             0x00000003  // Input channel 3\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,\r
+                           void (*pfnHandler)(void));\r
+extern void ADCIntUnregister(unsigned long ulBase,\r
+                             unsigned long ulSequenceNum);\r
+extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum);\r
+extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum);\r
+extern unsigned long ADCIntStatus(unsigned long ulBase,\r
+                                  unsigned long ulSequenceNum,\r
+                                  tBoolean bMasked);\r
+extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum);\r
+extern void ADCSequenceEnable(unsigned long ulBase,\r
+                              unsigned long ulSequenceNum);\r
+extern void ADCSequenceDisable(unsigned long ulBase,\r
+                               unsigned long ulSequenceNum);\r
+extern void ADCSequenceConfigure(unsigned long ulBase,\r
+                                 unsigned long ulSequenceNum,\r
+                                 unsigned long ulTrigger,\r
+                                 unsigned long ulPriority);\r
+extern void ADCSequenceStepConfigure(unsigned long ulBase,\r
+                                     unsigned long ulSequenceNum,\r
+                                     unsigned long ulStep,\r
+                                     unsigned long ulConfig);\r
+extern long ADCSequenceOverflow(unsigned long ulBase,\r
+                                unsigned long ulSequenceNum);\r
+extern long ADCSequenceUnderflow(unsigned long ulBase,\r
+                                 unsigned long ulSequenceNum);\r
+extern long ADCSequenceDataGet(unsigned long ulBase,\r
+                               unsigned long ulSequenceNum,\r
+                               unsigned long *pulBuffer);\r
+extern void ADCProcessorTrigger(unsigned long ulBase,\r
+                                unsigned long ulSequenceNum);\r
+extern void ADCSoftwareOversampleConfigure(unsigned long ulBase,\r
+                                           unsigned long ulSequenceNum,\r
+                                           unsigned long ulFactor);\r
+extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase,\r
+                                               unsigned long ulSequenceNum,\r
+                                               unsigned long ulStep,\r
+                                               unsigned long ulConfig);\r
+extern void ADCSoftwareOversampleDataGet(unsigned long ulBase,\r
+                                         unsigned long ulSequenceNum,\r
+                                         unsigned long *pulBuffer,\r
+                                         unsigned long ulCount);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __ADC_H__\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/asmdefs.h b/Demo/CORTEX_LM3S316_IAR/hw_include/asmdefs.h

new file mode 100644 (file)

index 0000000..4a1018a
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/asmdefs.h
@@ -0,0 +1,130 @@
+//*****************************************************************************\r
+//\r
+// asmdefs.h - Macros to allow assembly code be portable among toolchains.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __ASMDEFS_H__\r
+#define __ASMDEFS_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The defines required for EW-ARM.\r
+//\r
+//*****************************************************************************\r
+#ifdef ewarm\r
+\r
+//\r
+// Section headers.\r
+//\r
+#define __TEXT__                rseg CODE:CODE(2)\r
+#define __DATA__                rseg DATA:DATA(2)\r
+#define __BSS__                 rseg DATA:DATA(2)\r
+\r
+//\r
+// Assembler nmenonics.\r
+//\r
+#define __ALIGN__               alignrom 4\r
+#define __END__                 end\r
+#define __EXPORT__              export\r
+#define __IMPORT__              import\r
+#define __LABEL__\r
+#define __STR__                 dcb\r
+#define __THUMB_LABEL__\r
+#define __WORD__                dcd\r
+\r
+#endif // ewarm\r
+\r
+//*****************************************************************************\r
+//\r
+// The defines required for GCC.\r
+//\r
+//*****************************************************************************\r
+#ifdef gcc\r
+\r
+//\r
+// The assembly code preamble required to put the assembler into the correct\r
+// configuration.\r
+//\r
+    .syntax unified\r
+    .thumb\r
+\r
+//\r
+// Section headers.\r
+//\r
+#define __TEXT__                .text\r
+#define __DATA__                .data\r
+#define __BSS__                 .bss\r
+\r
+//\r
+// Assembler nmenonics.\r
+//\r
+#define __ALIGN__               .balign 4\r
+#define __END__                 .end\r
+#define __EXPORT__              .globl\r
+#define __IMPORT__              .extern\r
+#define __LABEL__               :\r
+#define __STR__                 .ascii\r
+#define __THUMB_LABEL__         .thumb_func\r
+#define __WORD__                .word\r
+\r
+#endif // gcc\r
+\r
+//*****************************************************************************\r
+//\r
+// The defines required for RV-MDK.\r
+//\r
+//*****************************************************************************\r
+#ifdef rvmdk\r
+\r
+//\r
+// The assembly code preamble required to put the assembler into the correct\r
+// configuration.\r
+//\r
+    thumb\r
+    require8\r
+    preserve8\r
+\r
+//\r
+// Section headers.\r
+//\r
+#define __TEXT__                area ||.text||, code, readonly, align=2\r
+#define __DATA__                area ||.data||, data, align=2\r
+#define __BSS__                 area ||.bss||, noinit, align=2\r
+\r
+//\r
+// Assembler nmenonics.\r
+//\r
+#define __ALIGN__               align 4\r
+#define __END__                 end\r
+#define __EXPORT__              export\r
+#define __IMPORT__              import\r
+#define __LABEL__\r
+#define __STR__                 dcb\r
+#define __THUMB_LABEL__\r
+#define __WORD__                dcd\r
+\r
+#endif // rvmdk\r
+\r
+#endif // __ASMDEF_H__\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/comp.h b/Demo/CORTEX_LM3S316_IAR/hw_include/comp.h

new file mode 100644 (file)

index 0000000..19eda38
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/comp.h
@@ -0,0 +1,120 @@
+//*****************************************************************************\r
+//\r
+// comp.h - Prototypes for the analog comparator driver.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __COMP_H__\r
+#define __COMP_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ComparatorConfigure() as the ulConfig\r
+// parameter.  For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of\r
+// the values may be selected and ORed together will values from the other\r
+// groups.\r
+//\r
+//*****************************************************************************\r
+#define COMP_TRIG_NONE          0x00000000  // No ADC trigger\r
+#define COMP_TRIG_HIGH          0x00000880  // Trigger when high\r
+#define COMP_TRIG_LOW           0x00000800  // Trigger when low\r
+#define COMP_TRIG_FALL          0x00000820  // Trigger on falling edge\r
+#define COMP_TRIG_RISE          0x00000840  // Trigger on rising edge\r
+#define COMP_TRIG_BOTH          0x00000860  // Trigger on both edges\r
+#define COMP_INT_HIGH           0x00000010  // Interrupt when high\r
+#define COMP_INT_LOW            0x00000000  // Interrupt when low\r
+#define COMP_INT_FALL           0x00000004  // Interrupt on falling edge\r
+#define COMP_INT_RISE           0x00000008  // Interrupt on rising edge\r
+#define COMP_INT_BOTH           0x0000000C  // Interrupt on both edges\r
+#define COMP_ASRCP_PIN          0x00000000  // Dedicated Comp+ pin\r
+#define COMP_ASRCP_PIN0         0x00000200  // Comp0+ pin\r
+#define COMP_ASRCP_REF          0x00000400  // Internal voltage reference\r
+#define COMP_OUTPUT_NONE        0x00000000  // No comparator output\r
+#define COMP_OUTPUT_NORMAL      0x00000100  // Comparator output normal\r
+#define COMP_OUTPUT_INVERT      0x00000102  // Comparator output inverted\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to ComparatorSetRef() as the ulRef parameter.\r
+//\r
+//*****************************************************************************\r
+#define COMP_REF_OFF            0x00000000  // Turn off the internal reference\r
+#define COMP_REF_0V             0x00000300  // Internal reference of 0V\r
+#define COMP_REF_0_1375V        0x00000301  // Internal reference of 0.1375V\r
+#define COMP_REF_0_275V         0x00000302  // Internal reference of 0.275V\r
+#define COMP_REF_0_4125V        0x00000303  // Internal reference of 0.4125V\r
+#define COMP_REF_0_55V          0x00000304  // Internal reference of 0.55V\r
+#define COMP_REF_0_6875V        0x00000305  // Internal reference of 0.6875V\r
+#define COMP_REF_0_825V         0x00000306  // Internal reference of 0.825V\r
+#define COMP_REF_0_928125V      0x00000201  // Internal reference of 0.928125V\r
+#define COMP_REF_0_9625V        0x00000307  // Internal reference of 0.9625V\r
+#define COMP_REF_1_03125V       0x00000202  // Internal reference of 1.03125V\r
+#define COMP_REF_1_134375V      0x00000203  // Internal reference of 1.134375V\r
+#define COMP_REF_1_1V           0x00000308  // Internal reference of 1.1V\r
+#define COMP_REF_1_2375V        0x00000309  // Internal reference of 1.2375V\r
+#define COMP_REF_1_340625V      0x00000205  // Internal reference of 1.340625V\r
+#define COMP_REF_1_375V         0x0000030A  // Internal reference of 1.375V\r
+#define COMP_REF_1_44375V       0x00000206  // Internal reference of 1.44375V\r
+#define COMP_REF_1_5125V        0x0000030B  // Internal reference of 1.5125V\r
+#define COMP_REF_1_546875V      0x00000207  // Internal reference of 1.546875V\r
+#define COMP_REF_1_65V          0x0000030C  // Internal reference of 1.65V\r
+#define COMP_REF_1_753125V      0x00000209  // Internal reference of 1.753125V\r
+#define COMP_REF_1_7875V        0x0000030D  // Internal reference of 1.7875V\r
+#define COMP_REF_1_85625V       0x0000020A  // Internal reference of 1.85625V\r
+#define COMP_REF_1_925V         0x0000030E  // Internal reference of 1.925V\r
+#define COMP_REF_1_959375V      0x0000020B  // Internal reference of 1.959375V\r
+#define COMP_REF_2_0625V        0x0000030F  // Internal reference of 2.0625V\r
+#define COMP_REF_2_165625V      0x0000020D  // Internal reference of 2.165625V\r
+#define COMP_REF_2_26875V       0x0000020E  // Internal reference of 2.26875V\r
+#define COMP_REF_2_371875V      0x0000020F  // Internal reference of 2.371875V\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp,\r
+                                unsigned long ulConfig);\r
+extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef);\r
+extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp);\r
+extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp,\r
+                                  void (*pfnHandler)(void));\r
+extern void ComparatorIntUnregister(unsigned long ulBase,\r
+                                    unsigned long ulComp);\r
+extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp);\r
+extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp);\r
+extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp,\r
+                                    tBoolean bMasked);\r
+extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __COMP_H__\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/cpu.h b/Demo/CORTEX_LM3S316_IAR/hw_include/cpu.h

new file mode 100644 (file)

index 0000000..0a2e282
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/cpu.h
@@ -0,0 +1,40 @@
+//*****************************************************************************\r
+//\r
+// cpu.h - Prototypes for the CPU instruction wrapper functions.\r
+//\r
+// Copyright (c) 2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __CPU_H__\r
+#define __CPU_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes.\r
+//\r
+//*****************************************************************************\r
+extern void CPUcpsid(void);\r
+extern void CPUcpsie(void);\r
+extern void CPUwfi(void);\r
+\r
+#endif // __CPU_H__\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/cspy.c b/Demo/CORTEX_LM3S316_IAR/hw_include/cspy.c

new file mode 100644 (file)

index 0000000..398ae59
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/cspy.c
@@ -0,0 +1,119 @@
+//*****************************************************************************\r
+//\r
+// cspy.c - Routines for simply ignoring the debugger communciation APIs in\r
+//          C-Spy for now.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#include "diag.h"\r
+\r
+//*****************************************************************************\r
+//\r
+// Open a handle for stdio functions (both stdin and stdout).\r
+//\r
+//*****************************************************************************\r
+int\r
+DiagOpenStdio(void)\r
+{\r
+    return(-1);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// Open a host file system file.\r
+//\r
+//*****************************************************************************\r
+int\r
+DiagOpen(const char *pcName, int iMode)\r
+{\r
+    return(-1);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// Close a host file system file.\r
+//\r
+//*****************************************************************************\r
+int\r
+DiagClose(int iHandle)\r
+{\r
+    return(-1);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// Write data to a host file system file.\r
+//\r
+//*****************************************************************************\r
+int\r
+DiagWrite(int iHandle, const char *pcBuf, unsigned long ulLen, int iMode)\r
+{\r
+    return(-1);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// Read data from a host file system file.\r
+//\r
+//*****************************************************************************\r
+int\r
+DiagRead(int iHandle, char *pcBuf, unsigned long ulLen, int iMode)\r
+{\r
+    return(-1);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// Get the length of a host file system file.\r
+//\r
+//*****************************************************************************\r
+long\r
+DiagFlen(int iHandle)\r
+{\r
+    return(-1);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// Terminate the application.\r
+//\r
+//*****************************************************************************\r
+void\r
+DiagExit(int iRet)\r
+{\r
+    while(1)\r
+    {\r
+    }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// Get the command line arguments from the debugger.\r
+//\r
+//*****************************************************************************\r
+char *\r
+DiagCommandString(char *pcBuf, unsigned long ulLen)\r
+{\r
+    return(0);\r
+}\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/debug.h b/Demo/CORTEX_LM3S316_IAR/hw_include/debug.h

new file mode 100644 (file)

index 0000000..83dbbf3
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/debug.h
@@ -0,0 +1,56 @@
+//*****************************************************************************\r
+//\r
+// debug.h - Macros for assisting debug of the driver library.\r
+//\r
+// Copyright (c) 2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __DEBUG_H__\r
+#define __DEBUG_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototype for the function that is called when an invalid argument is passed\r
+// to an API.  This is only used when doing a DEBUG build.\r
+//\r
+//*****************************************************************************\r
+extern void __error__(char *pcFilename, unsigned long ulLine);\r
+\r
+//*****************************************************************************\r
+//\r
+// The ASSERT macro, which does the actual assertion checking.  Typically, this\r
+// will be for procedure arguments.\r
+//\r
+//*****************************************************************************\r
+#ifdef DEBUG\r
+#define ASSERT(expr) {                                      \\r
+                         if(!(expr))                        \\r
+                         {                                  \\r
+                             __error__(__FILE__, __LINE__); \\r
+                         }                                  \\r
+                     }\r
+#else\r
+#define ASSERT(expr)\r
+#endif\r
+\r
+#endif // __DEBUG_H__\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/diag.h b/Demo/CORTEX_LM3S316_IAR/hw_include/diag.h

new file mode 100644 (file)

index 0000000..5eda186
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/diag.h
@@ -0,0 +1,67 @@
+//*****************************************************************************\r
+//\r
+// diag.h - Prototypes for the diagnostic functions.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __DIAG_H__\r
+#define __DIAG_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed as the iMode parater to DiagOpen, DiagRead, and\r
+// DiagWrite.\r
+//\r
+//*****************************************************************************\r
+#define OPEN_R                  0           // read access\r
+#define OPEN_W                  4           // write access\r
+#define OPEN_A                  8           // append to file\r
+#define OPEN_B                  1           // binary access\r
+#define OPEN_PLUS               2           // read and write access\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern int DiagOpenStdio(void);\r
+extern int DiagOpen(const char *pcName, int iMode);\r
+extern int DiagClose(int iHandle);\r
+extern int DiagWrite(int iHandle, const char *pcBuf, unsigned long ulLen,\r
+                     int iMode);\r
+extern int DiagRead(int iHandle, char *pcBuf, unsigned long ulLen, int iMode);\r
+extern long DiagFlen(int iHandle);\r
+extern void DiagExit(int iRet);\r
+extern char *DiagCommandString(char *pcBuf, unsigned long ulLen);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __DIAG_H__\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/driverlib.r79 b/Demo/CORTEX_LM3S316_IAR/hw_include/driverlib.r79

new file mode 100644 (file)

index 0000000..188c42e

Binary files /dev/null and b/Demo/CORTEX_LM3S316_IAR/hw_include/driverlib.r79 differ
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/flash.h b/Demo/CORTEX_LM3S316_IAR/hw_include/flash.h

new file mode 100644 (file)

index 0000000..7220276
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/flash.h
@@ -0,0 +1,75 @@
+//*****************************************************************************\r
+//\r
+// flash.h - Prototypes for the flash driver.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __FLASH_H__\r
+#define __FLASH_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to FlashProtectSet(), and returned by\r
+// FlashProtectGet().\r
+//\r
+//*****************************************************************************\r
+typedef enum\r
+{\r
+    FlashReadWrite,                         // Flash can be read and written\r
+    FlashReadOnly,                          // Flash can only be read\r
+    FlashExecuteOnly                        // Flash can only be executed\r
+}\r
+tFlashProtection;\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern unsigned long FlashUsecGet(void);\r
+extern void FlashUsecSet(unsigned long ulClocks);\r
+extern long FlashErase(unsigned long ulAddress);\r
+extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress,\r
+                         unsigned long ulCount);\r
+extern tFlashProtection FlashProtectGet(unsigned long ulAddress);\r
+extern long FlashProtectSet(unsigned long ulAddress,\r
+                            tFlashProtection eProtect);\r
+extern long FlashProtectSave(void);\r
+extern void FlashIntRegister(void (*pfnHandler)(void));\r
+extern void FlashIntUnregister(void);\r
+extern void FlashIntEnable(unsigned long ulIntFlags);\r
+extern void FlashIntDisable(unsigned long ulIntFlags);\r
+extern unsigned long FlashIntGetStatus(tBoolean bMasked);\r
+extern void FlashIntClear(unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __FLASH_H__\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/gpio.h b/Demo/CORTEX_LM3S316_IAR/hw_include/gpio.h

new file mode 100644 (file)

index 0000000..598fec8
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/gpio.h
@@ -0,0 +1,136 @@
+//*****************************************************************************\r
+//\r
+// gpio.h - Defines and Macros for GPIO API.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __GPIO_H__\r
+#define __GPIO_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following values define the bit field for the ucPins argument to several\r
+// of the APIs.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_PIN_0              0x00000001  // GPIO pin 0\r
+#define GPIO_PIN_1              0x00000002  // GPIO pin 1\r
+#define GPIO_PIN_2              0x00000004  // GPIO pin 2\r
+#define GPIO_PIN_3              0x00000008  // GPIO pin 3\r
+#define GPIO_PIN_4              0x00000010  // GPIO pin 4\r
+#define GPIO_PIN_5              0x00000020  // GPIO pin 5\r
+#define GPIO_PIN_6              0x00000040  // GPIO pin 6\r
+#define GPIO_PIN_7              0x00000080  // GPIO pin 7\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and\r
+// returned from GPIODirModeGet.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_DIR_MODE_IN        0x00000000  // Pin is a GPIO input\r
+#define GPIO_DIR_MODE_OUT       0x00000001  // Pin is a GPIO output\r
+#define GPIO_DIR_MODE_HW        0x00000002  // Pin is a peripheral function\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and\r
+// returned from GPIOIntTypeGet.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_FALLING_EDGE       0x00000000  // Interrupt on falling edge\r
+#define GPIO_RISING_EDGE        0x00000004  // Interrupt on rising edge\r
+#define GPIO_BOTH_EDGES         0x00000001  // Interrupt on both edges\r
+#define GPIO_LOW_LEVEL          0x00000002  // Interrupt on low level\r
+#define GPIO_HIGH_LEVEL         0x00000007  // Interrupt on high level\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter,\r
+// and returned by GPIOPadConfigGet in the *pulStrength parameter.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_STRENGTH_2MA       0x00000001  // 2mA drive strength\r
+#define GPIO_STRENGTH_4MA       0x00000002  // 4mA drive strength\r
+#define GPIO_STRENGTH_8MA       0x00000004  // 8mA drive strength\r
+#define GPIO_STRENGTH_8MA_SC    0x0000000C  // 8mA drive with slew rate control\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter,\r
+// and returned by GPIOPadConfigGet in the *pulPadType parameter.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_PIN_TYPE_STD       0x00000008  // Push-pull\r
+#define GPIO_PIN_TYPE_STD_WPU   0x0000000A  // Push-pull with weak pull-up\r
+#define GPIO_PIN_TYPE_STD_WPD   0x0000000C  // Push-pull with weak pull-down\r
+#define GPIO_PIN_TYPE_OD        0x00000009  // Open-drain\r
+#define GPIO_PIN_TYPE_OD_WPU    0x0000000B  // Open-drain with weak pull-up\r
+#define GPIO_PIN_TYPE_OD_WPD    0x0000000D  // Open-drain with weak pull-down\r
+#define GPIO_PIN_TYPE_ANALOG    0x00000000  // Analog comparator\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,\r
+                           unsigned long ulPinIO);\r
+extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);\r
+extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,\r
+                           unsigned long ulIntType);\r
+extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);\r
+extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,\r
+                             unsigned long ulStrength,\r
+                             unsigned long ulPadType);\r
+extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,\r
+                             unsigned long *pulStrength,\r
+                             unsigned long *pulPadType);\r
+extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins);\r
+extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked);\r
+extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPortIntRegister(unsigned long ulPort,\r
+                                void (*pfIntHandler)(void));\r
+extern void GPIOPortIntUnregister(unsigned long ulPort);\r
+extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,\r
+                         unsigned char ucVal);\r
+extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);\r
+extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif //  __GPIO_H__\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_adc.h b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_adc.h

new file mode 100644 (file)

index 0000000..36b8204
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_adc.h
@@ -0,0 +1,329 @@
+//*****************************************************************************\r
+//\r
+// hw_adc.h - Macros used when accessing the ADC hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_ADC_H__\r
+#define __HW_ADC_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the ADC registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_O_ACTSS             0x00000000  // Active sample register\r
+#define ADC_O_RIS               0x00000004  // Raw interrupt status register\r
+#define ADC_O_IM                0x00000008  // Interrupt mask register\r
+#define ADC_O_ISC               0x0000000C  // Interrupt status/clear register\r
+#define ADC_O_OSTAT             0x00000010  // Overflow status register\r
+#define ADC_O_EMUX              0x00000014  // Event multiplexer select reg.\r
+#define ADC_O_USTAT             0x00000018  // Underflow status register\r
+#define ADC_O_SSPRI             0x00000020  // Channel priority register\r
+#define ADC_O_PSSI              0x00000028  // Processor sample initiate reg.\r
+#define ADC_O_SSMUX0            0x00000040  // Multiplexer select 0 register\r
+#define ADC_O_SSCTL0            0x00000044  // Sample sequence control 0 reg.\r
+#define ADC_O_SSFIFO0           0x00000048  // Result FIFO 0 register\r
+#define ADC_O_SSFSTAT0          0x0000004C  // FIFO 0 status register\r
+#define ADC_O_SSMUX1            0x00000060  // Multiplexer select 1 register\r
+#define ADC_O_SSCTL1            0x00000064  // Sample sequence control 1 reg.\r
+#define ADC_O_SSFIFO1           0x00000068  // Result FIFO 1 register\r
+#define ADC_O_SSFSTAT1          0x0000006C  // FIFO 1 status register\r
+#define ADC_O_SSMUX2            0x00000080  // Multiplexer select 2 register\r
+#define ADC_O_SSCTL2            0x00000084  // Sample sequence control 2 reg.\r
+#define ADC_O_SSFIFO2           0x00000088  // Result FIFO 2 register\r
+#define ADC_O_SSFSTAT2          0x0000008C  // FIFO 2 status register\r
+#define ADC_O_SSMUX3            0x000000A0  // Multiplexer select 3 register\r
+#define ADC_O_SSCTL3            0x000000A4  // Sample sequence control 3 reg.\r
+#define ADC_O_SSFIFO3           0x000000A8  // Result FIFO 3 register\r
+#define ADC_O_SSFSTAT3          0x000000AC  // FIFO 3 status register\r
+#define ADC_O_TMLB              0x00000100  // Test mode loopback register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the ADC sequence registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_O_SEQ               0x00000040  // Offset to the first sequence\r
+#define ADC_O_SEQ_STEP          0x00000020  // Increment to the next sequence\r
+#define ADC_O_X_SSMUX           0x00000000  // Multiplexer select register\r
+#define ADC_O_X_SSCTL           0x00000004  // Sample sequence control register\r
+#define ADC_O_X_SSFIFO          0x00000008  // Result FIFO register\r
+#define ADC_O_X_SSFSTAT         0x0000000C  // FIFO status register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_ACTSS register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_ACTSS_ASEN3         0x00000008  // Sample sequence 3 enable\r
+#define ADC_ACTSS_ASEN2         0x00000004  // Sample sequence 2 enable\r
+#define ADC_ACTSS_ASEN1         0x00000002  // Sample sequence 1 enable\r
+#define ADC_ACTSS_ASEN0         0x00000001  // Sample sequence 0 enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_RIS register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_RIS_INR3            0x00000008  // Sample sequence 3 interrupt\r
+#define ADC_RIS_INR2            0x00000004  // Sample sequence 2 interrupt\r
+#define ADC_RIS_INR1            0x00000002  // Sample sequence 1 interrupt\r
+#define ADC_RIS_INR0            0x00000001  // Sample sequence 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_IM register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_IM_MASK3            0x00000008  // Sample sequence 3 mask\r
+#define ADC_IM_MASK2            0x00000004  // Sample sequence 2 mask\r
+#define ADC_IM_MASK1            0x00000002  // Sample sequence 1 mask\r
+#define ADC_IM_MASK0            0x00000001  // Sample sequence 0 mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_ISC register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_ISC_IN3             0x00000008 // Sample sequence 3 interrupt\r
+#define ADC_ISC_IN2             0x00000004 // Sample sequence 2 interrupt\r
+#define ADC_ISC_IN1             0x00000002 // Sample sequence 1 interrupt\r
+#define ADC_ISC_IN0             0x00000001 // Sample sequence 0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_OSTAT register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_OSTAT_OV3           0x00000008  // Sample sequence 3 overflow\r
+#define ADC_OSTAT_OV2           0x00000004  // Sample sequence 2 overflow\r
+#define ADC_OSTAT_OV1           0x00000002  // Sample sequence 1 overflow\r
+#define ADC_OSTAT_OV0           0x00000001  // Sample sequence 0 overflow\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_EMUX register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_EMUX_EM3_MASK       0x0000F000  // Event mux 3 mask\r
+#define ADC_EMUX_EM3_PROCESSOR  0x00000000  // Processor event\r
+#define ADC_EMUX_EM3_COMP0      0x00001000  // Analog comparator 0 event\r
+#define ADC_EMUX_EM3_COMP1      0x00002000  // Analog comparator 1 event\r
+#define ADC_EMUX_EM3_COMP2      0x00003000  // Analog comparator 2 event\r
+#define ADC_EMUX_EM3_EXTERNAL   0x00004000  // External event\r
+#define ADC_EMUX_EM3_TIMER      0x00005000  // Timer event\r
+#define ADC_EMUX_EM3_PWM0       0x00006000  // PWM0 event\r
+#define ADC_EMUX_EM3_PWM1       0x00007000  // PWM1 event\r
+#define ADC_EMUX_EM3_PWM2       0x00008000  // PWM2 event\r
+#define ADC_EMUX_EM3_ALWAYS     0x0000F000  // Always event\r
+#define ADC_EMUX_EM2_MASK       0x00000F00  // Event mux 2 mask\r
+#define ADC_EMUX_EM2_PROCESSOR  0x00000000  // Processor event\r
+#define ADC_EMUX_EM2_COMP0      0x00000100  // Analog comparator 0 event\r
+#define ADC_EMUX_EM2_COMP1      0x00000200  // Analog comparator 1 event\r
+#define ADC_EMUX_EM2_COMP2      0x00000300  // Analog comparator 2 event\r
+#define ADC_EMUX_EM2_EXTERNAL   0x00000400  // External event\r
+#define ADC_EMUX_EM2_TIMER      0x00000500  // Timer event\r
+#define ADC_EMUX_EM2_PWM0       0x00000600  // PWM0 event\r
+#define ADC_EMUX_EM2_PWM1       0x00000700  // PWM1 event\r
+#define ADC_EMUX_EM2_PWM2       0x00000800  // PWM2 event\r
+#define ADC_EMUX_EM2_ALWAYS     0x00000F00  // Always event\r
+#define ADC_EMUX_EM1_MASK       0x000000F0  // Event mux 1 mask\r
+#define ADC_EMUX_EM1_PROCESSOR  0x00000000  // Processor event\r
+#define ADC_EMUX_EM1_COMP0      0x00000010  // Analog comparator 0 event\r
+#define ADC_EMUX_EM1_COMP1      0x00000020  // Analog comparator 1 event\r
+#define ADC_EMUX_EM1_COMP2      0x00000030  // Analog comparator 2 event\r
+#define ADC_EMUX_EM1_EXTERNAL   0x00000040  // External event\r
+#define ADC_EMUX_EM1_TIMER      0x00000050  // Timer event\r
+#define ADC_EMUX_EM1_PWM0       0x00000060  // PWM0 event\r
+#define ADC_EMUX_EM1_PWM1       0x00000070  // PWM1 event\r
+#define ADC_EMUX_EM1_PWM2       0x00000080  // PWM2 event\r
+#define ADC_EMUX_EM1_ALWAYS     0x000000F0  // Always event\r
+#define ADC_EMUX_EM0_MASK       0x0000000F  // Event mux 0 mask\r
+#define ADC_EMUX_EM0_PROCESSOR  0x00000000  // Processor event\r
+#define ADC_EMUX_EM0_COMP0      0x00000001  // Analog comparator 0 event\r
+#define ADC_EMUX_EM0_COMP1      0x00000002  // Analog comparator 1 event\r
+#define ADC_EMUX_EM0_COMP2      0x00000003  // Analog comparator 2 event\r
+#define ADC_EMUX_EM0_EXTERNAL   0x00000004  // External event\r
+#define ADC_EMUX_EM0_TIMER      0x00000005  // Timer event\r
+#define ADC_EMUX_EM0_PWM0       0x00000006  // PWM0 event\r
+#define ADC_EMUX_EM0_PWM1       0x00000007  // PWM1 event\r
+#define ADC_EMUX_EM0_PWM2       0x00000008  // PWM2 event\r
+#define ADC_EMUX_EM0_ALWAYS     0x0000000F  // Always event\r
+#define ADC_EMUX_EM0_SHIFT               0  // The shift for the first event\r
+#define ADC_EMUX_EM1_SHIFT               4  // The shift for the second event\r
+#define ADC_EMUX_EM2_SHIFT               8  // The shift for the third event\r
+#define ADC_EMUX_EM3_SHIFT              12  // The shift for the fourth event\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_USTAT register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_USTAT_UV3           0x00000008  // Sample sequence 3 underflow\r
+#define ADC_USTAT_UV2           0x00000004  // Sample sequence 2 underflow\r
+#define ADC_USTAT_UV1           0x00000002  // Sample sequence 1 underflow\r
+#define ADC_USTAT_UV0           0x00000001  // Sample sequence 0 underflow\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSPRI register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSPRI_SS3_MASK      0x00003000  // Sequencer 3 priority mask\r
+#define ADC_SSPRI_SS3_1ST       0x00000000  // First priority\r
+#define ADC_SSPRI_SS3_2ND       0x00001000  // Second priority\r
+#define ADC_SSPRI_SS3_3RD       0x00002000  // Third priority\r
+#define ADC_SSPRI_SS3_4TH       0x00003000  // Fourth priority\r
+#define ADC_SSPRI_SS2_MASK      0x00000300  // Sequencer 2 priority mask\r
+#define ADC_SSPRI_SS2_1ST       0x00000000  // First priority\r
+#define ADC_SSPRI_SS2_2ND       0x00000100  // Second priority\r
+#define ADC_SSPRI_SS2_3RD       0x00000200  // Third priority\r
+#define ADC_SSPRI_SS2_4TH       0x00000300  // Fourth priority\r
+#define ADC_SSPRI_SS1_MASK      0x00000030  // Sequencer 1 priority mask\r
+#define ADC_SSPRI_SS1_1ST       0x00000000  // First priority\r
+#define ADC_SSPRI_SS1_2ND       0x00000010  // Second priority\r
+#define ADC_SSPRI_SS1_3RD       0x00000020  // Third priority\r
+#define ADC_SSPRI_SS1_4TH       0x00000030  // Fourth priority\r
+#define ADC_SSPRI_SS0_MASK      0x00000003  // Sequencer 0 priority mask\r
+#define ADC_SSPRI_SS0_1ST       0x00000000  // First priority\r
+#define ADC_SSPRI_SS0_2ND       0x00000001  // Second priority\r
+#define ADC_SSPRI_SS0_3RD       0x00000002  // Third priority\r
+#define ADC_SSPRI_SS0_4TH       0x00000003  // Fourth priority\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_PSSI register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_PSSI_SS3            0x00000008  // Trigger sample sequencer 3\r
+#define ADC_PSSI_SS2            0x00000004  // Trigger sample sequencer 2\r
+#define ADC_PSSI_SS1            0x00000002  // Trigger sample sequencer 1\r
+#define ADC_PSSI_SS0            0x00000001  // Trigger sample sequencer 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSMUX0, ADC_SSMUX1,\r
+// ADC_SSMUX2, and ADC_SSMUX3 registers.  Not all fields are present in all\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSMUX_MUX7_MASK     0x30000000  // 8th mux select mask\r
+#define ADC_SSMUX_MUX6_MASK     0x03000000  // 7th mux select mask\r
+#define ADC_SSMUX_MUX5_MASK     0x00300000  // 6th mux select mask\r
+#define ADC_SSMUX_MUX4_MASK     0x00030000  // 5th mux select mask\r
+#define ADC_SSMUX_MUX3_MASK     0x00003000  // 4th mux select mask\r
+#define ADC_SSMUX_MUX2_MASK     0x00000300  // 3rd mux select mask\r
+#define ADC_SSMUX_MUX1_MASK     0x00000030  // 2nd mux select mask\r
+#define ADC_SSMUX_MUX0_MASK     0x00000003  // 1st mux select mask\r
+#define ADC_SSMUX_MUX7_SHIFT    28\r
+#define ADC_SSMUX_MUX6_SHIFT    24\r
+#define ADC_SSMUX_MUX5_SHIFT    20\r
+#define ADC_SSMUX_MUX4_SHIFT    16\r
+#define ADC_SSMUX_MUX3_SHIFT    12\r
+#define ADC_SSMUX_MUX2_SHIFT    8\r
+#define ADC_SSMUX_MUX1_SHIFT    4\r
+#define ADC_SSMUX_MUX0_SHIFT    0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSCTL0, ADC_SSCTL1,\r
+// ADC_SSCTL2, and ADC_SSCTL3 registers.  Not all fields are present in all\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSCTL_TS7           0x80000000  // 8th temperature sensor select\r
+#define ADC_SSCTL_IE7           0x40000000  // 8th interrupt enable\r
+#define ADC_SSCTL_END7          0x20000000  // 8th sequence end select\r
+#define ADC_SSCTL_D7            0x10000000  // 8th differential select\r
+#define ADC_SSCTL_TS6           0x08000000  // 7th temperature sensor select\r
+#define ADC_SSCTL_IE6           0x04000000  // 7th interrupt enable\r
+#define ADC_SSCTL_END6          0x02000000  // 7th sequence end select\r
+#define ADC_SSCTL_D6            0x01000000  // 7th differential select\r
+#define ADC_SSCTL_TS5           0x00800000  // 6th temperature sensor select\r
+#define ADC_SSCTL_IE5           0x00400000  // 6th interrupt enable\r
+#define ADC_SSCTL_END5          0x00200000  // 6th sequence end select\r
+#define ADC_SSCTL_D5            0x00100000  // 6th differential select\r
+#define ADC_SSCTL_TS4           0x00080000  // 5th temperature sensor select\r
+#define ADC_SSCTL_IE4           0x00040000  // 5th interrupt enable\r
+#define ADC_SSCTL_END4          0x00020000  // 5th sequence end select\r
+#define ADC_SSCTL_D4            0x00010000  // 5th differential select\r
+#define ADC_SSCTL_TS3           0x00008000  // 4th temperature sensor select\r
+#define ADC_SSCTL_IE3           0x00004000  // 4th interrupt enable\r
+#define ADC_SSCTL_END3          0x00002000  // 4th sequence end select\r
+#define ADC_SSCTL_D3            0x00001000  // 4th differential select\r
+#define ADC_SSCTL_TS2           0x00000800  // 3rd temperature sensor select\r
+#define ADC_SSCTL_IE2           0x00000400  // 3rd interrupt enable\r
+#define ADC_SSCTL_END2          0x00000200  // 3rd sequence end select\r
+#define ADC_SSCTL_D2            0x00000100  // 3rd differential select\r
+#define ADC_SSCTL_TS1           0x00000080  // 2nd temperature sensor select\r
+#define ADC_SSCTL_IE1           0x00000040  // 2nd interrupt enable\r
+#define ADC_SSCTL_END1          0x00000020  // 2nd sequence end select\r
+#define ADC_SSCTL_D1            0x00000010  // 2nd differential select\r
+#define ADC_SSCTL_TS0           0x00000008  // 1st temperature sensor select\r
+#define ADC_SSCTL_IE0           0x00000004  // 1st interrupt enable\r
+#define ADC_SSCTL_END0          0x00000002  // 1st sequence end select\r
+#define ADC_SSCTL_D0            0x00000001  // 1st differential select\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSFIFO0, ADC_SSFIFO1,\r
+// ADC_SSFIFO2, and ADC_SSFIFO3 registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSFIFO_DATA_MASK    0x000003FF  // Sample data\r
+#define ADC_SSFIFO_DATA_SHIFT   0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_SSFSTAT0, ADC_SSFSTAT1,\r
+// ADC_SSFSTAT2, and ADC_SSFSTAT3 registers.\r
+//\r
+//*****************************************************************************\r
+#define ADC_SSFSTAT_FULL        0x00001000  // FIFO is full\r
+#define ADC_SSFSTAT_EMPTY       0x00000100  // FIFO is empty\r
+#define ADC_SSFSTAT_HPTR        0x000000F0  // FIFO head pointer\r
+#define ADC_SSFSTAT_TPTR        0x0000000F  // FIFO tail pointer\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the ADC_TMLB register.\r
+//\r
+//*****************************************************************************\r
+#define ADC_TMLB_LB             0x00000001  // Loopback control signals\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the loopback ADC data.\r
+//\r
+//*****************************************************************************\r
+#define ADC_LB_CNT_MASK         0x000003C0  // Sample counter mask\r
+#define ADC_LB_CONT             0x00000020  // Continuation sample\r
+#define ADC_LB_DIFF             0x00000010  // Differential sample\r
+#define ADC_LB_TS               0x00000008  // Temperature sensor sample\r
+#define ADC_LB_MUX_MASK         0x00000007  // Input channel number mask\r
+#define ADC_LB_CNT_SHIFT        6           // Sample counter shift\r
+#define ADC_LB_MUX_SHIFT        0           // Input channel number shift\r
+\r
+#endif // __HW_ADC_H__\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_comp.h b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_comp.h

new file mode 100644 (file)

index 0000000..02487e6
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_comp.h
@@ -0,0 +1,118 @@
+//*****************************************************************************\r
+//\r
+// hw_comp.h - Macros used when accessing the comparator hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_COMP_H__\r
+#define __HW_COMP_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the comparator registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_O_MIS              0x00000000  // Interrupt status register\r
+#define COMP_O_RIS              0x00000004  // Raw interrupt status register\r
+#define COMP_O_INTEN            0x00000008  // Interrupt enable register\r
+#define COMP_O_REFCTL           0x00000010  // Reference voltage control reg.\r
+#define COMP_O_ACSTAT0          0x00000020  // Comp0 status register\r
+#define COMP_O_ACCTL0           0x00000024  // Comp0 control register\r
+#define COMP_O_ACSTAT1          0x00000040  // Comp1 status register\r
+#define COMP_O_ACCTL1           0x00000044  // Comp1 control register\r
+#define COMP_O_ACSTAT2          0x00000060  // Comp2 status register\r
+#define COMP_O_ACCTL2           0x00000064  // Comp2 control register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_MIS, COMP_RIS, and\r
+// COMP_INTEN registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_INT_2              0x00000004  // Comp2 interrupt\r
+#define COMP_INT_1              0x00000002  // Comp1 interrupt\r
+#define COMP_INT_0              0x00000001  // Comp0 interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_REFCTL register.\r
+//\r
+//*****************************************************************************\r
+#define COMP_REFCTL_EN          0x00000200  // Reference voltage enable\r
+#define COMP_REFCTL_RNG         0x00000100  // Reference voltage range\r
+#define COMP_REFCTL_VREF_MASK   0x0000000F  // Reference voltage select mask\r
+#define COMP_REFCTL_VREF_SHIFT  0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_ACSTAT0, COMP_ACSTAT1, and\r
+// COMP_ACSTAT2 registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_ACSTAT_OVAL        0x00000002  // Comparator output value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the COMP_ACCTL0, COMP_ACCTL1, and\r
+// COMP_ACCTL2 registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_ACCTL_TMASK        0x00000800  // Trigger enable\r
+#define COMP_ACCTL_ASRCP_MASK   0x00000600  // Vin+ source select mask\r
+#define COMP_ACCTL_ASRCP_PIN    0x00000000  // Dedicated Comp+ pin\r
+#define COMP_ACCTL_ASRCP_PIN0   0x00000200  // Comp0+ pin\r
+#define COMP_ACCTL_ASRCP_REF    0x00000400  // Internal voltage reference\r
+#define COMP_ACCTL_ASRCP_RES    0x00000600  // Reserved\r
+#define COMP_ACCTL_OEN          0x00000100  // Comparator output enable\r
+#define COMP_ACCTL_TSVAL        0x00000080  // Trigger polarity select\r
+#define COMP_ACCTL_TSEN_MASK    0x00000060  // Trigger sense mask\r
+#define COMP_ACCTL_TSEN_LEVEL   0x00000000  // Trigger is level sense\r
+#define COMP_ACCTL_TSEN_FALL    0x00000020  // Trigger is falling edge\r
+#define COMP_ACCTL_TSEN_RISE    0x00000040  // Trigger is rising edge\r
+#define COMP_ACCTL_TSEN_BOTH    0x00000060  // Trigger is both edges\r
+#define COMP_ACCTL_ISLVAL       0x00000010  // Interrupt polarity select\r
+#define COMP_ACCTL_ISEN_MASK    0x0000000C  // Interrupt sense mask\r
+#define COMP_ACCTL_ISEN_LEVEL   0x00000000  // Interrupt is level sense\r
+#define COMP_ACCTL_ISEN_FALL    0x00000004  // Interrupt is falling edge\r
+#define COMP_ACCTL_ISEN_RISE    0x00000008  // Interrupt is rising edge\r
+#define COMP_ACCTL_ISEN_BOTH    0x0000000C  // Interrupt is both edges\r
+#define COMP_ACCTL_CINV         0x00000002  // Comparator output invert\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values for the comparator registers.\r
+//\r
+//*****************************************************************************\r
+#define COMP_RV_MIS             0x00000000  // Interrupt status register\r
+#define COMP_RV_RIS             0x00000000  // Raw interrupt status register\r
+#define COMP_RV_INTEN           0x00000000  // Interrupt enable register\r
+#define COMP_RV_REFCTL          0x00000000  // Reference voltage control reg.\r
+#define COMP_RV_ACSTAT0         0x00000000  // Comp0 status register\r
+#define COMP_RV_ACCTL0          0x00000000  // Comp0 control register\r
+#define COMP_RV_ACSTAT1         0x00000000  // Comp1 status register\r
+#define COMP_RV_ACCTL1          0x00000000  // Comp1 control register\r
+#define COMP_RV_ACSTAT2         0x00000000  // Comp2 status register\r
+#define COMP_RV_ACCTL2          0x00000000  // Comp2 control register\r
+\r
+#endif // __HW_COMP_H__\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_flash.h b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_flash.h

new file mode 100644 (file)

index 0000000..2143551
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_flash.h
@@ -0,0 +1,139 @@
+//*****************************************************************************\r
+//\r
+// hw_flash.h - Macros used when accessing the flash controller.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_FLASH_H__\r
+#define __HW_FLASH_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the FLASH registers.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FMA               0x400FD000  // Memory address register\r
+#define FLASH_FMD               0x400FD004  // Memory data register\r
+#define FLASH_FMC               0x400FD008  // Memory control register\r
+#define FLASH_FCRIS             0x400FD00c  // Raw interrupt status register\r
+#define FLASH_FCIM              0x400FD010  // Interrupt mask register\r
+#define FLASH_FCMISC            0x400FD014  // Interrupt status register\r
+#define FLASH_FMPRE             0x400FE130  // FLASH read protect register\r
+#define FLASH_FMPPE             0x400FE134  // FLASH program protect register\r
+#define FLASH_USECRL            0x400FE140  // uSec reload register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FMC register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FMC_WRKEY_MASK    0xFFFF0000  // FLASH write key mask\r
+#define FLASH_FMC_WRKEY         0xA4420000  // FLASH write key\r
+#define FLASH_FMC_COMT          0x00000008  // Commit user register\r
+#define FLASH_FMC_MERASE        0x00000004  // Mass erase FLASH\r
+#define FLASH_FMC_ERASE         0x00000002  // Erase FLASH page\r
+#define FLASH_FMC_WRITE         0x00000001  // Write FLASH word\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FCRIS register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FCRIS_PROGRAM     0x00000002  // Programming status\r
+#define FLASH_FCRIS_ACCESS      0x00000001  // Invalid access status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FCIM register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FCIM_PROGRAM      0x00000002  // Programming mask\r
+#define FLASH_FCIM_ACCESS       0x00000001  // Invalid access mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FMIS register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FCMISC_PROGRAM    0x00000002  // Programming status\r
+#define FLASH_FCMISC_ACCESS     0x00000001  // Invalid access status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_FMPRE and FLASH_FMPPE\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_FMP_BLOCK_31      0x80000000  // Enable for block 31\r
+#define FLASH_FMP_BLOCK_30      0x40000000  // Enable for block 30\r
+#define FLASH_FMP_BLOCK_29      0x20000000  // Enable for block 29\r
+#define FLASH_FMP_BLOCK_28      0x10000000  // Enable for block 28\r
+#define FLASH_FMP_BLOCK_27      0x08000000  // Enable for block 27\r
+#define FLASH_FMP_BLOCK_26      0x04000000  // Enable for block 26\r
+#define FLASH_FMP_BLOCK_25      0x02000000  // Enable for block 25\r
+#define FLASH_FMP_BLOCK_24      0x01000000  // Enable for block 24\r
+#define FLASH_FMP_BLOCK_23      0x00800000  // Enable for block 23\r
+#define FLASH_FMP_BLOCK_22      0x00400000  // Enable for block 22\r
+#define FLASH_FMP_BLOCK_21      0x00200000  // Enable for block 21\r
+#define FLASH_FMP_BLOCK_20      0x00100000  // Enable for block 20\r
+#define FLASH_FMP_BLOCK_19      0x00080000  // Enable for block 19\r
+#define FLASH_FMP_BLOCK_18      0x00040000  // Enable for block 18\r
+#define FLASH_FMP_BLOCK_17      0x00020000  // Enable for block 17\r
+#define FLASH_FMP_BLOCK_16      0x00010000  // Enable for block 16\r
+#define FLASH_FMP_BLOCK_15      0x00008000  // Enable for block 15\r
+#define FLASH_FMP_BLOCK_14      0x00004000  // Enable for block 14\r
+#define FLASH_FMP_BLOCK_13      0x00002000  // Enable for block 13\r
+#define FLASH_FMP_BLOCK_12      0x00001000  // Enable for block 12\r
+#define FLASH_FMP_BLOCK_11      0x00000800  // Enable for block 11\r
+#define FLASH_FMP_BLOCK_10      0x00000400  // Enable for block 10\r
+#define FLASH_FMP_BLOCK_9       0x00000200  // Enable for block 9\r
+#define FLASH_FMP_BLOCK_8       0x00000100  // Enable for block 8\r
+#define FLASH_FMP_BLOCK_7       0x00000080  // Enable for block 7\r
+#define FLASH_FMP_BLOCK_6       0x00000040  // Enable for block 6\r
+#define FLASH_FMP_BLOCK_5       0x00000020  // Enable for block 5\r
+#define FLASH_FMP_BLOCK_4       0x00000010  // Enable for block 4\r
+#define FLASH_FMP_BLOCK_3       0x00000008  // Enable for block 3\r
+#define FLASH_FMP_BLOCK_2       0x00000004  // Enable for block 2\r
+#define FLASH_FMP_BLOCK_1       0x00000002  // Enable for block 1\r
+#define FLASH_FMP_BLOCK_0       0x00000001  // Enable for block 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the FLASH_USECRL register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_USECRL_MASK       0x000000FF  // Clock per uSec\r
+#define FLASH_USECRL_SHIFT      0\r
+\r
+//*****************************************************************************\r
+//\r
+// The erase size is the size of the FLASH block that is erased by an erase\r
+// operation, and the protect size is the size of the FLASH block that is\r
+// protected by each protection register.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_ERASE_SIZE        0x00000400\r
+#define FLASH_PROTECT_SIZE      0x00000800\r
+\r
+#endif // __HW_FLASH_H__\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_gpio.h b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_gpio.h

new file mode 100644 (file)

index 0000000..2f85bbc
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_gpio.h
@@ -0,0 +1,103 @@
+//*****************************************************************************\r
+//\r
+// hw_gpio.h - Defines and Macros for GPIO hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_GPIO_H__\r
+#define __HW_GPIO_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// GPIO Register Offsets.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_O_DATA             0x00000000  // Data register.\r
+#define GPIO_O_DIR              0x00000400  // Data direction register.\r
+#define GPIO_O_IS               0x00000404  // Interrupt sense register.\r
+#define GPIO_O_IBE              0x00000408  // Interrupt both edges register.\r
+#define GPIO_O_IEV              0x0000040C  // Intterupt event register.\r
+#define GPIO_O_IM               0x00000410  // Interrupt mask register.\r
+#define GPIO_O_RIS              0x00000414  // Raw interrupt status register.\r
+#define GPIO_O_MIS              0x00000418  // Masked interrupt status reg.\r
+#define GPIO_O_ICR              0x0000041C  // Interrupt clear register.\r
+#define GPIO_O_AFSEL            0x00000420  // Mode control select register.\r
+#define GPIO_O_DR2R             0x00000500  // 2ma drive select register.\r
+#define GPIO_O_DR4R             0x00000504  // 4ma drive select register.\r
+#define GPIO_O_DR8R             0x00000508  // 8ma drive select register.\r
+#define GPIO_O_ODR              0x0000050C  // Open drain select register.\r
+#define GPIO_O_PUR              0x00000510  // Pull up select register.\r
+#define GPIO_O_PDR              0x00000514  // Pull down select register.\r
+#define GPIO_O_SLR              0x00000518  // Slew rate control enable reg.\r
+#define GPIO_O_DEN              0x0000051C  // Digital input enable register.\r
+#define GPIO_O_PeriphID4        0x00000FD0  //\r
+#define GPIO_O_PeriphID5        0x00000FD4  //\r
+#define GPIO_O_PeriphID6        0x00000FD8  //\r
+#define GPIO_O_PeriphID7        0x00000FDC  //\r
+#define GPIO_O_PeriphID0        0x00000FE0  //\r
+#define GPIO_O_PeriphID1        0x00000FE4  //\r
+#define GPIO_O_PeriphID2        0x00000FE8  //\r
+#define GPIO_O_PeriphID3        0x00000FEC  //\r
+#define GPIO_O_PCellID0         0x00000FF0  //\r
+#define GPIO_O_PCellID1         0x00000FF4  //\r
+#define GPIO_O_PCellID2         0x00000FF8  //\r
+#define GPIO_O_PCellID3         0x00000FFC  //\r
+\r
+//*****************************************************************************\r
+//\r
+// GPIO Register reset values.\r
+//\r
+//*****************************************************************************\r
+#define GPIO_RV_DATA            0x00000000  // Data register reset value.\r
+#define GPIO_RV_DIR             0x00000000  // Data direction reg RV.\r
+#define GPIO_RV_IS              0x00000000  // Interrupt sense reg RV.\r
+#define GPIO_RV_IBE             0x00000000  // Interrupt both edges reg RV.\r
+#define GPIO_RV_IEV             0x00000000  // Intterupt event reg RV.\r
+#define GPIO_RV_IM              0x00000000  // Interrupt mask reg RV.\r
+#define GPIO_RV_RIS             0x00000000  // Raw interrupt status reg RV.\r
+#define GPIO_RV_MIS             0x00000000  // Masked interrupt status reg RV.\r
+#define GPIO_RV_IC              0x00000000  // Interrupt clear reg RV.\r
+#define GPIO_RV_AFSEL           0x00000000  // Mode control select reg RV.\r
+#define GPIO_RV_DR2R            0x000000FF  // 2ma drive select reg RV.\r
+#define GPIO_RV_DR4R            0x00000000  // 4ma drive select reg RV.\r
+#define GPIO_RV_DR8R            0x00000000  // 8ma drive select reg RV.\r
+#define GPIO_RV_ODR             0x00000000  // Open drain select reg RV.\r
+#define GPIO_RV_PUR             0x000000FF  // Pull up select reg RV.\r
+#define GPIO_RV_PDR             0x00000000  // Pull down select reg RV.\r
+#define GPIO_RV_SLR             0x00000000  // Slew rate control enable reg RV.\r
+#define GPIO_RV_DEN             0x000000FF  // Digital input enable reg RV.\r
+#define GPIO_RV_PeriphID4       0x00000000  //\r
+#define GPIO_RV_PeriphID5       0x00000000  //\r
+#define GPIO_RV_PeriphID6       0x00000000  //\r
+#define GPIO_RV_PeriphID7       0x00000000  //\r
+#define GPIO_RV_PeriphID0       0x00000061  //\r
+#define GPIO_RV_PeriphID1       0x00000010  //\r
+#define GPIO_RV_PeriphID2       0x00000004  //\r
+#define GPIO_RV_PeriphID3       0x00000000  //\r
+#define GPIO_RV_PCellID0        0x0000000D  //\r
+#define GPIO_RV_PCellID1        0x000000F0  //\r
+#define GPIO_RV_PCellID2        0x00000005  //\r
+#define GPIO_RV_PCellID3        0x000000B1  //\r
+\r
+#endif //  __HW_GPIO_H__\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_i2c.h b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_i2c.h

new file mode 100644 (file)

index 0000000..2a5f4fd
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_i2c.h
@@ -0,0 +1,189 @@
+//*****************************************************************************\r
+//\r
+// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_I2C_H__\r
+#define __HW_I2C_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the I2C master registers.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_O_SA         0x00000000  // Slave address register\r
+#define I2C_MASTER_O_CS         0x00000004  // Control and Status register\r
+#define I2C_MASTER_O_DR         0x00000008  // Data register\r
+#define I2C_MASTER_O_TPR        0x0000000C  // Timer period register\r
+#define I2C_MASTER_O_IMR        0x00000010  // Interrupt mask register\r
+#define I2C_MASTER_O_RIS        0x00000014  // Raw interrupt status register\r
+#define I2C_MASTER_O_MIS        0x00000018  // Masked interrupt status reg\r
+#define I2C_MASTER_O_MICR       0x0000001c  // Interrupt clear register\r
+#define I2C_MASTER_O_CR         0x00000020  // Configuration register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the I2C slave registers.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_O_OAR         0x00000000  // Own address register\r
+#define I2C_SLAVE_O_CSR         0x00000004  // Control/Status register\r
+#define I2C_SLAVE_O_DR          0x00000008  // Data register\r
+#define I2C_SLAVE_O_IM          0x0000000C  // Interrupt mask register\r
+#define I2C_SLAVE_O_RIS         0x00000010  // Raw interrupt status register\r
+#define I2C_SLAVE_O_MIS         0x00000014  // Masked interrupt status reg\r
+#define I2C_SLAVE_O_SICR        0x00000018  // Interrupt clear register\r
+\r
+//*****************************************************************************\r
+//\r
+// The followng define the bit fields in the I2C master slave address register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_SA_SA_MASK   0x000000FE  // Slave address\r
+#define I2C_MASTER_SA_RS        0x00000001  // Receive/send\r
+#define I2C_MASTER_SA_SA_SHIFT  1\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Control and Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_CS_ACK       0x00000008  // Acknowlegde\r
+#define I2C_MASTER_CS_STOP      0x00000004  // Stop\r
+#define I2C_MASTER_CS_START     0x00000002  // Start\r
+#define I2C_MASTER_CS_RUN       0x00000001  // Run\r
+#define I2C_MASTER_CS_BUS_BUSY  0x00000040  // Bus busy\r
+#define I2C_MASTER_CS_IDLE      0x00000020  // Idle\r
+#define I2C_MASTER_CS_ARB_LOST  0x00000010  // Lost arbitration\r
+#define I2C_MASTER_CS_DATA_ACK  0x00000008  // Data byte not acknowledged\r
+#define I2C_MASTER_CS_ADDR_ACK  0x00000004  // Address byte not acknowledged\r
+#define I2C_MASTER_CS_ERROR     0x00000002  // Error occurred\r
+#define I2C_MASTER_CS_BUSY      0x00000001  // Controller is TX/RX data\r
+#define I2C_MASTER_CS_ERR_MASK  0x0000001C\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define values used in determining the contents of the I2C\r
+// Master Timer Period register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_TPR_SCL_HP   0x00000004  // SCL high period\r
+#define I2C_MASTER_TPR_SCL_LP   0x00000006  // SCL low period\r
+#define I2C_SCL_STANDARD        100000      // SCL standard frequency\r
+#define I2C_SCL_FAST            400000      // SCL fast frequency\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Interrupt Mask\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_IMR_IM       0x00000001  // Master interrupt mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Raw Interrupt Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_RIS_RIS      0x00000001  // Master raw interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Masked Interrupt\r
+// Status register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_MIS_MIS      0x00000001  // Master masked interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Interrupt Clear\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_MICR_IC      0x00000001  // Master interrupt clear\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Master Configuration\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_CR_SFE       0x00000020  // Slave function enable\r
+#define I2C_MASTER_CR_MFE       0x00000010  // Master function enable\r
+#define I2C_MASTER_CR_LPBK      0x00000001  // Loopback enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Own Address register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F  // Slave address\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Control/Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_CSR_DA        0x00000001  // Enable the device\r
+#define I2C_SLAVE_CSR_TREQ      0x00000002  // Transmit request received\r
+#define I2C_SLAVE_CSR_RREQ      0x00000001  // Receive data from I2C master\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Interrupt Mask\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_IMR_IM       0x00000001  // Slave interrupt mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Raw Interrupt Status\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_RIS_RIS      0x00000001  // Slave raw interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Masked Interrupt\r
+// Status register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_MIS_MIS      0x00000001  // Slave masked interrupt status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the I2C Slave Interrupt Clear\r
+// register.\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_SICR_IC      0x00000001  // Slave interrupt clear\r
+\r
+#endif // __HW_I2C_H__\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_ints.h b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_ints.h

new file mode 100644 (file)

index 0000000..65ce141
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_ints.h
@@ -0,0 +1,96 @@
+//*****************************************************************************\r
+//\r
+// hw_ints.h - Macros that define the interrupt assignment on Stellaris.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_INTS_H__\r
+#define __HW_INTS_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the fault assignments.\r
+//\r
+//*****************************************************************************\r
+#define FAULT_NMI               2           // NMI fault\r
+#define FAULT_HARD              3           // Hard fault\r
+#define FAULT_MPU               4           // MPU fault\r
+#define FAULT_BUS               5           // Bus fault\r
+#define FAULT_USAGE             6           // Usage fault\r
+#define FAULT_SVCALL            11          // SVCall\r
+#define FAULT_DEBUG             12          // Debug monitor\r
+#define FAULT_PENDSV            14          // PendSV\r
+#define FAULT_SYSTICK           15          // System Tick\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the interrupt assignments.\r
+//\r
+//*****************************************************************************\r
+#define INT_GPIOA               16          // GPIO Port A\r
+#define INT_GPIOB               17          // GPIO Port B\r
+#define INT_GPIOC               18          // GPIO Port C\r
+#define INT_GPIOD               19          // GPIO Port D\r
+#define INT_GPIOE               20          // GPIO Port E\r
+#define INT_UART0               21          // UART0 Rx and Tx\r
+#define INT_UART1               22          // UART1 Rx and Tx\r
+#define INT_SSI                 23          // SSI Rx and Tx\r
+#define INT_I2C                 24          // I2C Master and Slave\r
+#define INT_PWM_FAULT           25          // PWM Fault\r
+#define INT_PWM0                26          // PWM Generator 0\r
+#define INT_PWM1                27          // PWM Generator 1\r
+#define INT_PWM2                28          // PWM Generator 2\r
+#define INT_ADC0                30          // ADC Sequence 0\r
+#define INT_ADC1                31          // ADC Sequence 1\r
+#define INT_ADC2                32          // ADC Sequence 2\r
+#define INT_ADC3                33          // ADC Sequence 3\r
+#define INT_WATCHDOG            34          // Watchdog timer\r
+#define INT_TIMER0A             35          // Timer 0 subtimer A\r
+#define INT_TIMER0B             36          // Timer 0 subtimer B\r
+#define INT_TIMER1A             37          // Timer 1 subtimer A\r
+#define INT_TIMER1B             38          // Timer 1 subtimer B\r
+#define INT_TIMER2A             39          // Timer 2 subtimer A\r
+#define INT_TIMER2B             40          // Timer 2 subtimer B\r
+#define INT_COMP0               41          // Analog Comparator 0\r
+#define INT_COMP1               42          // Analog Comparator 1\r
+#define INT_COMP2               43          // Analog Comparator 2\r
+#define INT_SYSCTL              44          // System Control (PLL, OSC, BO)\r
+#define INT_FLASH               45          // FLASH Control\r
+\r
+//*****************************************************************************\r
+//\r
+// The total number of interrupts.\r
+//\r
+//*****************************************************************************\r
+#define NUM_INTERRUPTS          46\r
+\r
+//*****************************************************************************\r
+//\r
+// The total number of priority levels.\r
+//\r
+//*****************************************************************************\r
+#define NUM_PRIORITY            8\r
+#define NUM_PRIORITY_BITS       3\r
+\r
+#endif // __HW_INTS_H__\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_memmap.h b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_memmap.h

new file mode 100644 (file)

index 0000000..9f701fc
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_memmap.h
@@ -0,0 +1,63 @@
+//*****************************************************************************\r
+//\r
+// hw_memmap.h - Macros defining the memory map of Stellaris.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_MEMMAP_H__\r
+#define __HW_MEMMAP_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the base address of the memories and peripherals.\r
+//\r
+//*****************************************************************************\r
+#define FLASH_BASE              0x00000000  // FLASH memory\r
+#define SRAM_BASE               0x20000000  // SRAM memory\r
+#define WATCHDOG_BASE           0x40000000  // Watchdog\r
+#define GPIO_PORTA_BASE         0x40004000  // GPIO Port A\r
+#define GPIO_PORTB_BASE         0x40005000  // GPIO Port B\r
+#define GPIO_PORTC_BASE         0x40006000  // GPIO Port C\r
+#define GPIO_PORTD_BASE         0x40007000  // GPIO Port D\r
+#define SSI_BASE                0x40008000  // SSI\r
+#define UART0_BASE              0x4000C000  // UART0\r
+#define UART1_BASE              0x4000D000  // UART1\r
+#define I2C_MASTER_BASE         0x40020000  // I2C Master\r
+#define I2C_SLAVE_BASE          0x40020800  // I2C Slave\r
+#define GPIO_PORTE_BASE         0x40024000  // GPIO Port E\r
+#define PWM_BASE                0x40028000  // PWM\r
+#define TIMER0_BASE             0x40030000  // Timer0\r
+#define TIMER1_BASE             0x40031000  // Timer1\r
+#define TIMER2_BASE             0x40032000  // Timer2\r
+#define ADC_BASE                0x40038000  // ADC\r
+#define COMP_BASE               0x4003C000  // Analog comparators\r
+#define FLASH_CTRL_BASE         0x400FD000  // FLASH Controller\r
+#define SYSCTL_BASE             0x400FE000  // System Control\r
+#define ITM_BASE                0xE0000000  // Instrumentation Trace Macrocell\r
+#define DWT_BASE                0xE0001000  // Data Watchpoint and Trace\r
+#define FPB_BASE                0xE0002000  // FLASH Patch and Breakpoint\r
+#define NVIC_BASE               0xE000E000  // Nested Vectored Interrupt Ctrl\r
+#define TPIU_BASE               0xE0040000  // Trace Port Interface Unit\r
+\r
+#endif // __HW_MEMMAP_H__\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_nvic.h b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_nvic.h

new file mode 100644 (file)

index 0000000..9e3154c
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_nvic.h
@@ -0,0 +1,830 @@
+//*****************************************************************************\r
+//\r
+// hw_nvic.h - Macros used when accessing the NVIC hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_NVIC_H__\r
+#define __HW_NVIC_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the addresses of the NVIC registers.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_INT_TYPE           0xE000E004  // Interrupt Controller Type Reg.\r
+#define NVIC_ST_CTRL            0xE000E010  // SysTick Control and Status Reg.\r
+#define NVIC_ST_RELOAD          0xE000E014  // SysTick Reload Value Register\r
+#define NVIC_ST_CURRENT         0xE000E018  // SysTick Current Value Register\r
+#define NVIC_ST_CAL             0xE000E01C  // SysTick Calibration Value Reg.\r
+#define NVIC_EN0                0xE000E100  // IRQ 0 to 31 Set Enable Register\r
+#define NVIC_DIS0               0xE000E180  // IRQ 0 to 31 Clear Enable Reg.\r
+#define NVIC_PEND0              0xE000E200  // IRQ 0 to 31 Set Pending Register\r
+#define NVIC_UNPEND0            0xE000E280  // IRQ 0 to 31 Clear Pending Reg.\r
+#define NVIC_ACTIVE0            0xE000E300  // IRQ 0 to 31 Active Register\r
+#define NVIC_PRI0               0xE000E400  // IRQ 0 to 3 Priority Register\r
+#define NVIC_PRI1               0xE000E404  // IRQ 4 to 7 Priority Register\r
+#define NVIC_PRI2               0xE000E408  // IRQ 8 to 11 Priority Register\r
+#define NVIC_PRI3               0xE000E40C  // IRQ 12 to 15 Priority Register\r
+#define NVIC_PRI4               0xE000E410  // IRQ 16 to 19 Priority Register\r
+#define NVIC_PRI5               0xE000E414  // IRQ 20 to 23 Priority Register\r
+#define NVIC_PRI6               0xE000E418  // IRQ 24 to 27 Priority Register\r
+#define NVIC_PRI7               0xE000E41C  // IRQ 28 to 31 Priority Register\r
+#define NVIC_CPUID              0xE000ED00  // CPUID Base Register\r
+#define NVIC_INT_CTRL           0xE000ED04  // Interrupt Control State Register\r
+#define NVIC_VTABLE             0xE000ED08  // Vector Table Offset Register\r
+#define NVIC_APINT              0xE000ED0C  // App. Int & Reset Control Reg.\r
+#define NVIC_SYS_CTRL           0xE000ED10  // System Control Register\r
+#define NVIC_CFG_CTRL           0xE000ED14  // Configuration Control Register\r
+#define NVIC_SYS_PRI1           0xE000ED18  // Sys. Handlers 4 to 7 Priority\r
+#define NVIC_SYS_PRI2           0xE000ED1C  // Sys. Handlers 8 to 11 Priority\r
+#define NVIC_SYS_PRI3           0xE000ED20  // Sys. Handlers 12 to 15 Priority\r
+#define NVIC_SYS_HND_CTRL       0xE000ED24  // System Handler Control and State\r
+#define NVIC_FAULT_STAT         0xE000ED28  // Configurable Fault Status Reg.\r
+#define NVIC_HFAULT_STAT        0xE000ED2C  // Hard Fault Status Register\r
+#define NVIC_DEBUG_STAT         0xE000ED30  // Debug Status Register\r
+#define NVIC_MM_ADDR            0xE000ED34  // Mem Manage Address Register\r
+#define NVIC_FAULT_ADDR         0xE000ED38  // Bus Fault Address Register\r
+#define NVIC_MPU_TYPE           0xE000ED90  // MPU Type Register\r
+#define NVIC_MPU_CTRL           0xE000ED94  // MPU Control Register\r
+#define NVIC_MPU_NUMBER         0xE000ED98  // MPU Region Number Register\r
+#define NVIC_MPU_BASE           0xE000ED9C  // MPU Region Base Address Register\r
+#define NVIC_MPU_ATTR           0xE000EDA0  // MPU Region Attribute & Size Reg.\r
+#define NVIC_DBG_CTRL           0xE000EDF0  // Debug Control and Status Reg.\r
+#define NVIC_DBG_XFER           0xE000EDF4  // Debug Core Reg. Transfer Select\r
+#define NVIC_DBG_DATA           0xE000EDF8  // Debug Core Register Data\r
+#define NVIC_DBG_INT            0xE000EDFC  // Debug Reset Interrupt Control\r
+#define NVIC_SW_TRIG            0xE000EF00  // Software Trigger Interrupt Reg.\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_INT_TYPE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_INT_TYPE_LINES_M   0x0000001F  // Number of interrupt lines (x32)\r
+#define NVIC_INT_TYPE_LINES_S   0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_CTRL_COUNT      0x00010000  // Count flag\r
+#define NVIC_ST_CTRL_CLK_SRC    0x00000004  // Clock Source\r
+#define NVIC_ST_CTRL_INTEN      0x00000002  // Interrupt enable\r
+#define NVIC_ST_CTRL_ENABLE     0x00000001  // Counter mode\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_RELOAD register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_RELOAD_M        0x00FFFFFF  // Counter load value\r
+#define NVIC_ST_RELOAD_S        0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_CURRENT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_CURRENT_M       0x00FFFFFF  // Counter current value\r
+#define NVIC_ST_CURRENT_S       0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ST_CAL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ST_CAL_NOREF       0x80000000  // No reference clock\r
+#define NVIC_ST_CAL_SKEW        0x40000000  // Clock skew\r
+#define NVIC_ST_CAL_ONEMS_M     0x00FFFFFF  // 1ms reference value\r
+#define NVIC_ST_CAL_ONEMS_S     0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EN0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EN0_INT31          0x80000000  // Interrupt 31 enable\r
+#define NVIC_EN0_INT30          0x40000000  // Interrupt 30 enable\r
+#define NVIC_EN0_INT29          0x20000000  // Interrupt 29 enable\r
+#define NVIC_EN0_INT28          0x10000000  // Interrupt 28 enable\r
+#define NVIC_EN0_INT27          0x08000000  // Interrupt 27 enable\r
+#define NVIC_EN0_INT26          0x04000000  // Interrupt 26 enable\r
+#define NVIC_EN0_INT25          0x02000000  // Interrupt 25 enable\r
+#define NVIC_EN0_INT24          0x01000000  // Interrupt 24 enable\r
+#define NVIC_EN0_INT23          0x00800000  // Interrupt 23 enable\r
+#define NVIC_EN0_INT22          0x00400000  // Interrupt 22 enable\r
+#define NVIC_EN0_INT21          0x00200000  // Interrupt 21 enable\r
+#define NVIC_EN0_INT20          0x00100000  // Interrupt 20 enable\r
+#define NVIC_EN0_INT19          0x00080000  // Interrupt 19 enable\r
+#define NVIC_EN0_INT18          0x00040000  // Interrupt 18 enable\r
+#define NVIC_EN0_INT17          0x00020000  // Interrupt 17 enable\r
+#define NVIC_EN0_INT16          0x00010000  // Interrupt 16 enable\r
+#define NVIC_EN0_INT15          0x00008000  // Interrupt 15 enable\r
+#define NVIC_EN0_INT14          0x00004000  // Interrupt 14 enable\r
+#define NVIC_EN0_INT13          0x00002000  // Interrupt 13 enable\r
+#define NVIC_EN0_INT12          0x00001000  // Interrupt 12 enable\r
+#define NVIC_EN0_INT11          0x00000800  // Interrupt 11 enable\r
+#define NVIC_EN0_INT10          0x00000400  // Interrupt 10 enable\r
+#define NVIC_EN0_INT9           0x00000200  // Interrupt 9 enable\r
+#define NVIC_EN0_INT8           0x00000100  // Interrupt 8 enable\r
+#define NVIC_EN0_INT7           0x00000080  // Interrupt 7 enable\r
+#define NVIC_EN0_INT6           0x00000040  // Interrupt 6 enable\r
+#define NVIC_EN0_INT5           0x00000020  // Interrupt 5 enable\r
+#define NVIC_EN0_INT4           0x00000010  // Interrupt 4 enable\r
+#define NVIC_EN0_INT3           0x00000008  // Interrupt 3 enable\r
+#define NVIC_EN0_INT2           0x00000004  // Interrupt 2 enable\r
+#define NVIC_EN0_INT1           0x00000002  // Interrupt 1 enable\r
+#define NVIC_EN0_INT0           0x00000001  // Interrupt 0 enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DIS0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DIS0_INT31         0x80000000  // Interrupt 31 disable\r
+#define NVIC_DIS0_INT30         0x40000000  // Interrupt 30 disable\r
+#define NVIC_DIS0_INT29         0x20000000  // Interrupt 29 disable\r
+#define NVIC_DIS0_INT28         0x10000000  // Interrupt 28 disable\r
+#define NVIC_DIS0_INT27         0x08000000  // Interrupt 27 disable\r
+#define NVIC_DIS0_INT26         0x04000000  // Interrupt 26 disable\r
+#define NVIC_DIS0_INT25         0x02000000  // Interrupt 25 disable\r
+#define NVIC_DIS0_INT24         0x01000000  // Interrupt 24 disable\r
+#define NVIC_DIS0_INT23         0x00800000  // Interrupt 23 disable\r
+#define NVIC_DIS0_INT22         0x00400000  // Interrupt 22 disable\r
+#define NVIC_DIS0_INT21         0x00200000  // Interrupt 21 disable\r
+#define NVIC_DIS0_INT20         0x00100000  // Interrupt 20 disable\r
+#define NVIC_DIS0_INT19         0x00080000  // Interrupt 19 disable\r
+#define NVIC_DIS0_INT18         0x00040000  // Interrupt 18 disable\r
+#define NVIC_DIS0_INT17         0x00020000  // Interrupt 17 disable\r
+#define NVIC_DIS0_INT16         0x00010000  // Interrupt 16 disable\r
+#define NVIC_DIS0_INT15         0x00008000  // Interrupt 15 disable\r
+#define NVIC_DIS0_INT14         0x00004000  // Interrupt 14 disable\r
+#define NVIC_DIS0_INT13         0x00002000  // Interrupt 13 disable\r
+#define NVIC_DIS0_INT12         0x00001000  // Interrupt 12 disable\r
+#define NVIC_DIS0_INT11         0x00000800  // Interrupt 11 disable\r
+#define NVIC_DIS0_INT10         0x00000400  // Interrupt 10 disable\r
+#define NVIC_DIS0_INT9          0x00000200  // Interrupt 9 disable\r
+#define NVIC_DIS0_INT8          0x00000100  // Interrupt 8 disable\r
+#define NVIC_DIS0_INT7          0x00000080  // Interrupt 7 disable\r
+#define NVIC_DIS0_INT6          0x00000040  // Interrupt 6 disable\r
+#define NVIC_DIS0_INT5          0x00000020  // Interrupt 5 disable\r
+#define NVIC_DIS0_INT4          0x00000010  // Interrupt 4 disable\r
+#define NVIC_DIS0_INT3          0x00000008  // Interrupt 3 disable\r
+#define NVIC_DIS0_INT2          0x00000004  // Interrupt 2 disable\r
+#define NVIC_DIS0_INT1          0x00000002  // Interrupt 1 disable\r
+#define NVIC_DIS0_INT0          0x00000001  // Interrupt 0 disable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PEND0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PEND0_INT31        0x80000000  // Interrupt 31 pend\r
+#define NVIC_PEND0_INT30        0x40000000  // Interrupt 30 pend\r
+#define NVIC_PEND0_INT29        0x20000000  // Interrupt 29 pend\r
+#define NVIC_PEND0_INT28        0x10000000  // Interrupt 28 pend\r
+#define NVIC_PEND0_INT27        0x08000000  // Interrupt 27 pend\r
+#define NVIC_PEND0_INT26        0x04000000  // Interrupt 26 pend\r
+#define NVIC_PEND0_INT25        0x02000000  // Interrupt 25 pend\r
+#define NVIC_PEND0_INT24        0x01000000  // Interrupt 24 pend\r
+#define NVIC_PEND0_INT23        0x00800000  // Interrupt 23 pend\r
+#define NVIC_PEND0_INT22        0x00400000  // Interrupt 22 pend\r
+#define NVIC_PEND0_INT21        0x00200000  // Interrupt 21 pend\r
+#define NVIC_PEND0_INT20        0x00100000  // Interrupt 20 pend\r
+#define NVIC_PEND0_INT19        0x00080000  // Interrupt 19 pend\r
+#define NVIC_PEND0_INT18        0x00040000  // Interrupt 18 pend\r
+#define NVIC_PEND0_INT17        0x00020000  // Interrupt 17 pend\r
+#define NVIC_PEND0_INT16        0x00010000  // Interrupt 16 pend\r
+#define NVIC_PEND0_INT15        0x00008000  // Interrupt 15 pend\r
+#define NVIC_PEND0_INT14        0x00004000  // Interrupt 14 pend\r
+#define NVIC_PEND0_INT13        0x00002000  // Interrupt 13 pend\r
+#define NVIC_PEND0_INT12        0x00001000  // Interrupt 12 pend\r
+#define NVIC_PEND0_INT11        0x00000800  // Interrupt 11 pend\r
+#define NVIC_PEND0_INT10        0x00000400  // Interrupt 10 pend\r
+#define NVIC_PEND0_INT9         0x00000200  // Interrupt 9 pend\r
+#define NVIC_PEND0_INT8         0x00000100  // Interrupt 8 pend\r
+#define NVIC_PEND0_INT7         0x00000080  // Interrupt 7 pend\r
+#define NVIC_PEND0_INT6         0x00000040  // Interrupt 6 pend\r
+#define NVIC_PEND0_INT5         0x00000020  // Interrupt 5 pend\r
+#define NVIC_PEND0_INT4         0x00000010  // Interrupt 4 pend\r
+#define NVIC_PEND0_INT3         0x00000008  // Interrupt 3 pend\r
+#define NVIC_PEND0_INT2         0x00000004  // Interrupt 2 pend\r
+#define NVIC_PEND0_INT1         0x00000002  // Interrupt 1 pend\r
+#define NVIC_PEND0_INT0         0x00000001  // Interrupt 0 pend\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_UNPEND0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_UNPEND0_INT31      0x80000000  // Interrupt 31 unpend\r
+#define NVIC_UNPEND0_INT30      0x40000000  // Interrupt 30 unpend\r
+#define NVIC_UNPEND0_INT29      0x20000000  // Interrupt 29 unpend\r
+#define NVIC_UNPEND0_INT28      0x10000000  // Interrupt 28 unpend\r
+#define NVIC_UNPEND0_INT27      0x08000000  // Interrupt 27 unpend\r
+#define NVIC_UNPEND0_INT26      0x04000000  // Interrupt 26 unpend\r
+#define NVIC_UNPEND0_INT25      0x02000000  // Interrupt 25 unpend\r
+#define NVIC_UNPEND0_INT24      0x01000000  // Interrupt 24 unpend\r
+#define NVIC_UNPEND0_INT23      0x00800000  // Interrupt 23 unpend\r
+#define NVIC_UNPEND0_INT22      0x00400000  // Interrupt 22 unpend\r
+#define NVIC_UNPEND0_INT21      0x00200000  // Interrupt 21 unpend\r
+#define NVIC_UNPEND0_INT20      0x00100000  // Interrupt 20 unpend\r
+#define NVIC_UNPEND0_INT19      0x00080000  // Interrupt 19 unpend\r
+#define NVIC_UNPEND0_INT18      0x00040000  // Interrupt 18 unpend\r
+#define NVIC_UNPEND0_INT17      0x00020000  // Interrupt 17 unpend\r
+#define NVIC_UNPEND0_INT16      0x00010000  // Interrupt 16 unpend\r
+#define NVIC_UNPEND0_INT15      0x00008000  // Interrupt 15 unpend\r
+#define NVIC_UNPEND0_INT14      0x00004000  // Interrupt 14 unpend\r
+#define NVIC_UNPEND0_INT13      0x00002000  // Interrupt 13 unpend\r
+#define NVIC_UNPEND0_INT12      0x00001000  // Interrupt 12 unpend\r
+#define NVIC_UNPEND0_INT11      0x00000800  // Interrupt 11 unpend\r
+#define NVIC_UNPEND0_INT10      0x00000400  // Interrupt 10 unpend\r
+#define NVIC_UNPEND0_INT9       0x00000200  // Interrupt 9 unpend\r
+#define NVIC_UNPEND0_INT8       0x00000100  // Interrupt 8 unpend\r
+#define NVIC_UNPEND0_INT7       0x00000080  // Interrupt 7 unpend\r
+#define NVIC_UNPEND0_INT6       0x00000040  // Interrupt 6 unpend\r
+#define NVIC_UNPEND0_INT5       0x00000020  // Interrupt 5 unpend\r
+#define NVIC_UNPEND0_INT4       0x00000010  // Interrupt 4 unpend\r
+#define NVIC_UNPEND0_INT3       0x00000008  // Interrupt 3 unpend\r
+#define NVIC_UNPEND0_INT2       0x00000004  // Interrupt 2 unpend\r
+#define NVIC_UNPEND0_INT1       0x00000002  // Interrupt 1 unpend\r
+#define NVIC_UNPEND0_INT0       0x00000001  // Interrupt 0 unpend\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_ACTIVE0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_ACTIVE0_INT31      0x80000000  // Interrupt 31 active\r
+#define NVIC_ACTIVE0_INT30      0x40000000  // Interrupt 30 active\r
+#define NVIC_ACTIVE0_INT29      0x20000000  // Interrupt 29 active\r
+#define NVIC_ACTIVE0_INT28      0x10000000  // Interrupt 28 active\r
+#define NVIC_ACTIVE0_INT27      0x08000000  // Interrupt 27 active\r
+#define NVIC_ACTIVE0_INT26      0x04000000  // Interrupt 26 active\r
+#define NVIC_ACTIVE0_INT25      0x02000000  // Interrupt 25 active\r
+#define NVIC_ACTIVE0_INT24      0x01000000  // Interrupt 24 active\r
+#define NVIC_ACTIVE0_INT23      0x00800000  // Interrupt 23 active\r
+#define NVIC_ACTIVE0_INT22      0x00400000  // Interrupt 22 active\r
+#define NVIC_ACTIVE0_INT21      0x00200000  // Interrupt 21 active\r
+#define NVIC_ACTIVE0_INT20      0x00100000  // Interrupt 20 active\r
+#define NVIC_ACTIVE0_INT19      0x00080000  // Interrupt 19 active\r
+#define NVIC_ACTIVE0_INT18      0x00040000  // Interrupt 18 active\r
+#define NVIC_ACTIVE0_INT17      0x00020000  // Interrupt 17 active\r
+#define NVIC_ACTIVE0_INT16      0x00010000  // Interrupt 16 active\r
+#define NVIC_ACTIVE0_INT15      0x00008000  // Interrupt 15 active\r
+#define NVIC_ACTIVE0_INT14      0x00004000  // Interrupt 14 active\r
+#define NVIC_ACTIVE0_INT13      0x00002000  // Interrupt 13 active\r
+#define NVIC_ACTIVE0_INT12      0x00001000  // Interrupt 12 active\r
+#define NVIC_ACTIVE0_INT11      0x00000800  // Interrupt 11 active\r
+#define NVIC_ACTIVE0_INT10      0x00000400  // Interrupt 10 active\r
+#define NVIC_ACTIVE0_INT9       0x00000200  // Interrupt 9 active\r
+#define NVIC_ACTIVE0_INT8       0x00000100  // Interrupt 8 active\r
+#define NVIC_ACTIVE0_INT7       0x00000080  // Interrupt 7 active\r
+#define NVIC_ACTIVE0_INT6       0x00000040  // Interrupt 6 active\r
+#define NVIC_ACTIVE0_INT5       0x00000020  // Interrupt 5 active\r
+#define NVIC_ACTIVE0_INT4       0x00000010  // Interrupt 4 active\r
+#define NVIC_ACTIVE0_INT3       0x00000008  // Interrupt 3 active\r
+#define NVIC_ACTIVE0_INT2       0x00000004  // Interrupt 2 active\r
+#define NVIC_ACTIVE0_INT1       0x00000002  // Interrupt 1 active\r
+#define NVIC_ACTIVE0_INT0       0x00000001  // Interrupt 0 active\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI0 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI0_INT3_M        0xFF000000  // Interrupt 3 priority mask\r
+#define NVIC_PRI0_INT2_M        0x00FF0000  // Interrupt 2 priority mask\r
+#define NVIC_PRI0_INT1_M        0x0000FF00  // Interrupt 1 priority mask\r
+#define NVIC_PRI0_INT0_M        0x000000FF  // Interrupt 0 priority mask\r
+#define NVIC_PRI0_INT3_S        24\r
+#define NVIC_PRI0_INT2_S        16\r
+#define NVIC_PRI0_INT1_S        8\r
+#define NVIC_PRI0_INT0_S        0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI1_INT7_M        0xFF000000  // Interrupt 7 priority mask\r
+#define NVIC_PRI1_INT6_M        0x00FF0000  // Interrupt 6 priority mask\r
+#define NVIC_PRI1_INT5_M        0x0000FF00  // Interrupt 5 priority mask\r
+#define NVIC_PRI1_INT4_M        0x000000FF  // Interrupt 4 priority mask\r
+#define NVIC_PRI1_INT7_S        24\r
+#define NVIC_PRI1_INT6_S        16\r
+#define NVIC_PRI1_INT5_S        8\r
+#define NVIC_PRI1_INT4_S        0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI2 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI2_INT11_M       0xFF000000  // Interrupt 11 priority mask\r
+#define NVIC_PRI2_INT10_M       0x00FF0000  // Interrupt 10 priority mask\r
+#define NVIC_PRI2_INT9_M        0x0000FF00  // Interrupt 9 priority mask\r
+#define NVIC_PRI2_INT8_M        0x000000FF  // Interrupt 8 priority mask\r
+#define NVIC_PRI2_INT11_S       24\r
+#define NVIC_PRI2_INT10_S       16\r
+#define NVIC_PRI2_INT9_S        8\r
+#define NVIC_PRI2_INT8_S        0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI3 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI3_INT15_M       0xFF000000  // Interrupt 15 priority mask\r
+#define NVIC_PRI3_INT14_M       0x00FF0000  // Interrupt 14 priority mask\r
+#define NVIC_PRI3_INT13_M       0x0000FF00  // Interrupt 13 priority mask\r
+#define NVIC_PRI3_INT12_M       0x000000FF  // Interrupt 12 priority mask\r
+#define NVIC_PRI3_INT15_S       24\r
+#define NVIC_PRI3_INT14_S       16\r
+#define NVIC_PRI3_INT13_S       8\r
+#define NVIC_PRI3_INT12_S       0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI4 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI4_INT19_M       0xFF000000  // Interrupt 19 priority mask\r
+#define NVIC_PRI4_INT18_M       0x00FF0000  // Interrupt 18 priority mask\r
+#define NVIC_PRI4_INT17_M       0x0000FF00  // Interrupt 17 priority mask\r
+#define NVIC_PRI4_INT16_M       0x000000FF  // Interrupt 16 priority mask\r
+#define NVIC_PRI4_INT19_S       24\r
+#define NVIC_PRI4_INT18_S       16\r
+#define NVIC_PRI4_INT17_S       8\r
+#define NVIC_PRI4_INT16_S       0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI5 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI5_INT23_M       0xFF000000  // Interrupt 23 priority mask\r
+#define NVIC_PRI5_INT22_M       0x00FF0000  // Interrupt 22 priority mask\r
+#define NVIC_PRI5_INT21_M       0x0000FF00  // Interrupt 21 priority mask\r
+#define NVIC_PRI5_INT20_M       0x000000FF  // Interrupt 20 priority mask\r
+#define NVIC_PRI5_INT23_S       24\r
+#define NVIC_PRI5_INT22_S       16\r
+#define NVIC_PRI5_INT21_S       8\r
+#define NVIC_PRI5_INT20_S       0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI6 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI6_INT27_M       0xFF000000  // Interrupt 27 priority mask\r
+#define NVIC_PRI6_INT26_M       0x00FF0000  // Interrupt 26 priority mask\r
+#define NVIC_PRI6_INT25_M       0x0000FF00  // Interrupt 25 priority mask\r
+#define NVIC_PRI6_INT24_M       0x000000FF  // Interrupt 24 priority mask\r
+#define NVIC_PRI6_INT27_S       24\r
+#define NVIC_PRI6_INT26_S       16\r
+#define NVIC_PRI6_INT25_S       8\r
+#define NVIC_PRI6_INT24_S       0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_PRI7 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_PRI7_INT31_M       0xFF000000  // Interrupt 31 priority mask\r
+#define NVIC_PRI7_INT30_M       0x00FF0000  // Interrupt 30 priority mask\r
+#define NVIC_PRI7_INT29_M       0x0000FF00  // Interrupt 29 priority mask\r
+#define NVIC_PRI7_INT28_M       0x000000FF  // Interrupt 28 priority mask\r
+#define NVIC_PRI7_INT31_S       24\r
+#define NVIC_PRI7_INT30_S       16\r
+#define NVIC_PRI7_INT29_S       8\r
+#define NVIC_PRI7_INT28_S       0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_CPUID register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_CPUID_IMP_M        0xFF000000  // Implementer\r
+#define NVIC_CPUID_VAR_M        0x00F00000  // Variant\r
+#define NVIC_CPUID_PARTNO_M     0x0000FFF0  // Processor part number\r
+#define NVIC_CPUID_REV_M        0x0000000F  // Revision\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_INT_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_INT_CTRL_NMI_SET   0x80000000  // Pend a NMI\r
+#define NVIC_INT_CTRL_PEND_SV   0x10000000  // Pend a PendSV\r
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000  // Unpend a PendSV\r
+#define NVIC_INT_CTRL_ISR_PRE   0x00800000  // Debug interrupt handling\r
+#define NVIC_INT_CTRL_ISR_PEND  0x00400000  // Debug interrupt pending\r
+#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000  // Highest pending exception\r
+#define NVIC_INT_CTRL_RET_BASE  0x00000800  // Return to base\r
+#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF  // Current active exception\r
+#define NVIC_INT_CTRL_VEC_PEN_S 12\r
+#define NVIC_INT_CTRL_VEC_ACT_S 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_VTABLE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_VTABLE_BASE        0x20000000  // Vector table base\r
+#define NVIC_VTABLE_OFFSET_M    0x1FFFFF00  // Vector table offset\r
+#define NVIC_VTABLE_OFFSET_S    8\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_APINT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_APINT_VECTKEY_M    0xFFFF0000  // Vector key mask\r
+#define NVIC_APINT_VECTKEY      0x05FA0000  // Vector key\r
+#define NVIC_APINT_ENDIANESS    0x00008000  // Data endianess\r
+#define NVIC_APINT_PRIGROUP_M   0x00000700  // Priority group\r
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000  // Priority group 7.1 split\r
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100  // Priority group 6.2 split\r
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200  // Priority group 5.3 split\r
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300  // Priority group 4.4 split\r
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400  // Priority group 3.5 split\r
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500  // Priority group 2.6 split\r
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600  // Priority group 1.7 split\r
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700  // Priority group 0.8 split\r
+#define NVIC_APINT_SYSRESETREQ  0x00000004  // System reset request\r
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002  // Clear active NMI/fault info\r
+#define NVIC_APINT_VECT_RESET   0x00000001  // System reset\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010  // Wakeup on pend\r
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004  // Deep sleep enable\r
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002  // Sleep on ISR exit\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_CFG_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100  // Ignore bus fault in NMI/fault\r
+#define NVIC_CFG_CTRL_DIV0      0x00000010  // Trap on divide by 0\r
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008  // Trap on unaligned access\r
+#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004  // Allow deep interrupt trigger\r
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002  // Allow main interrupt trigger\r
+#define NVIC_CFG_CTRL_BASE_THR  0x00000001  // Thread state control\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_PRI1 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_PRI1_RES_M     0xFF000000  // Priority of reserved handler\r
+#define NVIC_SYS_PRI1_USAGE_M   0x00FF0000  // Priority of usage fault handler\r
+#define NVIC_SYS_PRI1_BUS_M     0x0000FF00  // Priority of bus fault handler\r
+#define NVIC_SYS_PRI1_MEM_M     0x000000FF  // Priority of mem manage handler\r
+#define NVIC_SYS_PRI1_USAGE_S   16\r
+#define NVIC_SYS_PRI1_BUS_S     8\r
+#define NVIC_SYS_PRI1_MEM_S     0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_PRI2 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_PRI2_SVC_M     0xFF000000  // Priority of SVCall handler\r
+#define NVIC_SYS_PRI2_RES_M     0x00FFFFFF  // Priority of reserved handlers\r
+#define NVIC_SYS_PRI2_SVC_S     24\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_PRI3 register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_PRI3_TICK_M    0xFF000000  // Priority of Sys Tick handler\r
+#define NVIC_SYS_PRI3_PENDSV_M  0x00FF0000  // Priority of PendSV handler\r
+#define NVIC_SYS_PRI3_RES_M     0x0000FF00  // Priority of reserved handler\r
+#define NVIC_SYS_PRI3_DEBUG_M   0x000000FF  // Priority of debug handler\r
+#define NVIC_SYS_PRI3_TICK_S    24\r
+#define NVIC_SYS_PRI3_PENDSV_S  16\r
+#define NVIC_SYS_PRI3_DEBUG_S   0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SYS_HND_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000  // Usage fault enable\r
+#define NVIC_SYS_HND_CTRL_BUS   0x00020000  // Bus fault enable\r
+#define NVIC_SYS_HND_CTRL_MEM   0x00010000  // Mem manage fault enable\r
+#define NVIC_SYS_HND_CTRL_SVC   0x00008000  // SVCall is pended\r
+#define NVIC_SYS_HND_CTRL_BUSP  0x00004000  // Bus fault is pended\r
+#define NVIC_SYS_HND_CTRL_TICK  0x00000800  // Sys tick is active\r
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400  // PendSV is active\r
+#define NVIC_SYS_HND_CTRL_MON   0x00000100  // Monitor is active\r
+#define NVIC_SYS_HND_CTRL_SVCA  0x00000080  // SVCall is active\r
+#define NVIC_SYS_HND_CTRL_USGA  0x00000008  // Usage fault is active\r
+#define NVIC_SYS_HND_CTRL_BUSA  0x00000002  // Bus fault is active\r
+#define NVIC_SYS_HND_CTRL_MEMA  0x00000001  // Mem manage is active\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_FAULT_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_FAULT_STAT_DIV0    0x02000000  // Divide by zero fault\r
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000  // Unaligned access fault\r
+#define NVIC_FAULT_STAT_NOCP    0x00080000  // No coprocessor fault\r
+#define NVIC_FAULT_STAT_INVPC   0x00040000  // Invalid PC fault\r
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000  // Invalid state fault\r
+#define NVIC_FAULT_STAT_UNDEF   0x00010000  // Undefined instruction fault\r
+#define NVIC_FAULT_STAT_BFARV   0x00008000  // BFAR is valid\r
+#define NVIC_FAULT_STAT_BSTKE   0x00001000  // Stack bus fault\r
+#define NVIC_FAULT_STAT_BUSTKE  0x00000800  // Unstack bus fault\r
+#define NVIC_FAULT_STAT_IMPRE   0x00000400  // Imprecise data bus error\r
+#define NVIC_FAULT_STAT_PRECISE 0x00000200  // Precise data bus error\r
+#define NVIC_FAULT_STAT_IBUS    0x00000100  // Instruction bus fault\r
+#define NVIC_FAULT_STAT_MMARV   0x00000080  // MMAR is valid\r
+#define NVIC_FAULT_STAT_MSTKE   0x00000010  // Stack access violation\r
+#define NVIC_FAULT_STAT_MUSTKE  0x00000008  // Unstack access violation\r
+#define NVIC_FAULT_STAT_DERR    0x00000002  // Data access violation\r
+#define NVIC_FAULT_STAT_IERR    0x00000001  // Instruction access violation\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_HFAULT_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_HFAULT_STAT_DBG    0x80000000  // Debug event\r
+#define NVIC_HFAULT_STAT_FORCED 0x40000000  // Cannot execute fault handler\r
+#define NVIC_HFAULT_STAT_VECT   0x00000002  // Vector table read fault\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DEBUG_STAT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DEBUG_STAT_EXTRNL  0x00000010  // EDBGRQ asserted\r
+#define NVIC_DEBUG_STAT_VCATCH  0x00000008  // Vector catch\r
+#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004  // DWT match\r
+#define NVIC_DEBUG_STAT_BKPT    0x00000002  // Breakpoint instruction\r
+#define NVIC_DEBUG_STAT_HALTED  0x00000001  // Halt request\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MM_ADDR register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MM_ADDR_M          0xFFFFFFFF  // Data fault address\r
+#define NVIC_MM_ADDR_S          0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_FAULT_ADDR register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_FAULT_ADDR_M       0xFFFFFFFF  // Data bus fault address\r
+#define NVIC_FAULT_ADDR_S       0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EXC_STACK register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EXC_STACK_DEEP     0x00000001  // Exception stack\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_EXC_NUM register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_EXC_NUM_M          0x000003FF  // Exception number\r
+#define NVIC_EXC_NUM_S          0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_COPRO register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_COPRO_15_M         0xC0000000  // Coprocessor 15 access mask\r
+#define NVIC_COPRO_15_DENIED    0x00000000  // Coprocessor 15 access denied\r
+#define NVIC_COPRO_15_PRIV      0x40000000  // Coprocessor 15 privileged addess\r
+#define NVIC_COPRO_15_FULL      0xC0000000  // Coprocessor 15 full access\r
+#define NVIC_COPRO_14_M         0x30000000  // Coprocessor 14 access mask\r
+#define NVIC_COPRO_14_DENIED    0x00000000  // Coprocessor 14 access denied\r
+#define NVIC_COPRO_14_PRIV      0x10000000  // Coprocessor 14 privileged addess\r
+#define NVIC_COPRO_14_FULL      0x30000000  // Coprocessor 14 full access\r
+#define NVIC_COPRO_13_M         0x0C000000  // Coprocessor 13 access mask\r
+#define NVIC_COPRO_13_DENIED    0x00000000  // Coprocessor 13 access denied\r
+#define NVIC_COPRO_13_PRIV      0x04000000  // Coprocessor 13 privileged addess\r
+#define NVIC_COPRO_13_FULL      0x0C000000  // Coprocessor 13 full access\r
+#define NVIC_COPRO_12_M         0x03000000  // Coprocessor 12 access mask\r
+#define NVIC_COPRO_12_DENIED    0x00000000  // Coprocessor 12 access denied\r
+#define NVIC_COPRO_12_PRIV      0x01000000  // Coprocessor 12 privileged addess\r
+#define NVIC_COPRO_12_FULL      0x03000000  // Coprocessor 12 full access\r
+#define NVIC_COPRO_11_M         0x00C00000  // Coprocessor 11 access mask\r
+#define NVIC_COPRO_11_DENIED    0x00000000  // Coprocessor 11 access denied\r
+#define NVIC_COPRO_11_PRIV      0x00400000  // Coprocessor 11 privileged addess\r
+#define NVIC_COPRO_11_FULL      0x00C00000  // Coprocessor 11 full access\r
+#define NVIC_COPRO_10_M         0x00300000  // Coprocessor 10 access mask\r
+#define NVIC_COPRO_10_DENIED    0x00000000  // Coprocessor 10 access denied\r
+#define NVIC_COPRO_10_PRIV      0x00100000  // Coprocessor 10 privileged addess\r
+#define NVIC_COPRO_10_FULL      0x00300000  // Coprocessor 10 full access\r
+#define NVIC_COPRO_9_M          0x000C0000  // Coprocessor 9 access mask\r
+#define NVIC_COPRO_9_DENIED     0x00000000  // Coprocessor 9 access denied\r
+#define NVIC_COPRO_9_PRIV       0x00040000  // Coprocessor 9 privileged addess\r
+#define NVIC_COPRO_9_FULL       0x000C0000  // Coprocessor 9 full access\r
+#define NVIC_COPRO_8_M          0x00030000  // Coprocessor 8 access mask\r
+#define NVIC_COPRO_8_DENIED     0x00000000  // Coprocessor 8 access denied\r
+#define NVIC_COPRO_8_PRIV       0x00010000  // Coprocessor 8 privileged addess\r
+#define NVIC_COPRO_8_FULL       0x00030000  // Coprocessor 8 full access\r
+#define NVIC_COPRO_7_M          0x0000C000  // Coprocessor 7 access mask\r
+#define NVIC_COPRO_7_DENIED     0x00000000  // Coprocessor 7 access denied\r
+#define NVIC_COPRO_7_PRIV       0x00004000  // Coprocessor 7 privileged addess\r
+#define NVIC_COPRO_7_FULL       0x0000C000  // Coprocessor 7 full access\r
+#define NVIC_COPRO_6_M          0x00003000  // Coprocessor 6 access mask\r
+#define NVIC_COPRO_6_DENIED     0x00000000  // Coprocessor 6 access denied\r
+#define NVIC_COPRO_6_PRIV       0x00001000  // Coprocessor 6 privileged addess\r
+#define NVIC_COPRO_6_FULL       0x00003000  // Coprocessor 6 full access\r
+#define NVIC_COPRO_5_M          0x00000C00  // Coprocessor 5 access mask\r
+#define NVIC_COPRO_5_DENIED     0x00000000  // Coprocessor 5 access denied\r
+#define NVIC_COPRO_5_PRIV       0x00000400  // Coprocessor 5 privileged addess\r
+#define NVIC_COPRO_5_FULL       0x00000C00  // Coprocessor 5 full access\r
+#define NVIC_COPRO_4_M          0x00000300  // Coprocessor 4 access mask\r
+#define NVIC_COPRO_4_DENIED     0x00000000  // Coprocessor 4 access denied\r
+#define NVIC_COPRO_4_PRIV       0x00000100  // Coprocessor 4 privileged addess\r
+#define NVIC_COPRO_4_FULL       0x00000300  // Coprocessor 4 full access\r
+#define NVIC_COPRO_3_M          0x000000C0  // Coprocessor 3 access mask\r
+#define NVIC_COPRO_3_DENIED     0x00000000  // Coprocessor 3 access denied\r
+#define NVIC_COPRO_3_PRIV       0x00000040  // Coprocessor 3 privileged addess\r
+#define NVIC_COPRO_3_FULL       0x000000C0  // Coprocessor 3 full access\r
+#define NVIC_COPRO_2_M          0x00000030  // Coprocessor 2 access mask\r
+#define NVIC_COPRO_2_DENIED     0x00000000  // Coprocessor 2 access denied\r
+#define NVIC_COPRO_2_PRIV       0x00000010  // Coprocessor 2 privileged addess\r
+#define NVIC_COPRO_2_FULL       0x00000030  // Coprocessor 2 full access\r
+#define NVIC_COPRO_1_M          0x0000000C  // Coprocessor 1 access mask\r
+#define NVIC_COPRO_1_DENIED     0x00000000  // Coprocessor 1 access denied\r
+#define NVIC_COPRO_1_PRIV       0x00000004  // Coprocessor 1 privileged addess\r
+#define NVIC_COPRO_1_FULL       0x0000000C  // Coprocessor 1 full access\r
+#define NVIC_COPRO_0_M          0x00000003  // Coprocessor 0 access mask\r
+#define NVIC_COPRO_0_DENIED     0x00000000  // Coprocessor 0 access denied\r
+#define NVIC_COPRO_0_PRIV       0x00000001  // Coprocessor 0 privileged addess\r
+#define NVIC_COPRO_0_FULL       0x00000003  // Coprocessor 0 full access\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_TYPE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000  // Number of I regions\r
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00  // Number of D regions\r
+#define NVIC_MPU_TYPE_SEPARATE  0x00000001  // Separate or unified MPU\r
+#define NVIC_MPU_TYPE_IREGION_S 16\r
+#define NVIC_MPU_TYPE_DREGION_S 8\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_CTRL_HFNMIENA  0x00000002  // MPU enabled during faults\r
+#define NVIC_MPU_CTRL_ENABLE    0x00000001  // MPU enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_NUMBER register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_NUMBER_M       0x000000FF  // MPU region to access\r
+#define NVIC_MPU_NUMBER_S       0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_BASE register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_BASE_ADDR_M    0xFFFFFF00  // Base address\r
+#define NVIC_MPU_BASE_VALID     0x00000010  // Region number valid\r
+#define NVIC_MPU_BASE_REGION_M  0x0000000F  // Region number\r
+#define NVIC_MPU_BASE_ADDR_S    8\r
+#define NVIC_MPU_BASE_REGION_S  0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_MPU_ATTR register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_MPU_ATTR_ATTRS     0xFFFF0000  // Attributes\r
+#define NVIC_MPU_ATTR_SRD       0x0000FF00  // Sub-region disable\r
+#define NVIC_MPU_ATTR_SZENABLE  0x000000FF  // Region size\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_CTRL register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_CTRL_DBGKEY_M  0xFFFF0000  // Debug key mask\r
+#define NVIC_DBG_CTRL_DBGKEY    0xA05F0000  // Debug key\r
+#define NVIC_DBG_CTRL_MON_PEND  0x00008000  // Pend the monitor\r
+#define NVIC_DBG_CTRL_MON_REQ   0x00004000  // Monitor request\r
+#define NVIC_DBG_CTRL_MON_EN    0x00002000  // Debug monitor enable\r
+#define NVIC_DBG_CTRL_MONSTEP   0x00001000  // Monitor step the core\r
+#define NVIC_DBG_CTRL_S_SLEEP   0x00000400  // Core is sleeping\r
+#define NVIC_DBG_CTRL_S_HALT    0x00000200  // Core status on halt\r
+#define NVIC_DBG_CTRL_S_REGRDY  0x00000100  // Register read/write available\r
+#define NVIC_DBG_CTRL_S_LOCKUP  0x00000080  // Core is locked up\r
+#define NVIC_DBG_CTRL_C_RESET   0x00000010  // Reset the core\r
+#define NVIC_DBG_CTRL_C_MASKINT 0x00000008  // Mask interrupts when stepping\r
+#define NVIC_DBG_CTRL_C_STEP    0x00000004  // Step the core\r
+#define NVIC_DBG_CTRL_C_HALT    0x00000002  // Halt the core\r
+#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001  // Enable debug\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_XFER register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_XFER_REG_WNR   0x00010000  // Write or not read\r
+#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F  // Register\r
+#define NVIC_DBG_XFER_REG_R0    0x00000000  // Register R0\r
+#define NVIC_DBG_XFER_REG_R1    0x00000001  // Register R1\r
+#define NVIC_DBG_XFER_REG_R2    0x00000002  // Register R2\r
+#define NVIC_DBG_XFER_REG_R3    0x00000003  // Register R3\r
+#define NVIC_DBG_XFER_REG_R4    0x00000004  // Register R4\r
+#define NVIC_DBG_XFER_REG_R5    0x00000005  // Register R5\r
+#define NVIC_DBG_XFER_REG_R6    0x00000006  // Register R6\r
+#define NVIC_DBG_XFER_REG_R7    0x00000007  // Register R7\r
+#define NVIC_DBG_XFER_REG_R8    0x00000008  // Register R8\r
+#define NVIC_DBG_XFER_REG_R9    0x00000009  // Register R9\r
+#define NVIC_DBG_XFER_REG_R10   0x0000000A  // Register R10\r
+#define NVIC_DBG_XFER_REG_R11   0x0000000B  // Register R11\r
+#define NVIC_DBG_XFER_REG_R12   0x0000000C  // Register R12\r
+#define NVIC_DBG_XFER_REG_R13   0x0000000D  // Register R13\r
+#define NVIC_DBG_XFER_REG_R14   0x0000000E  // Register R14\r
+#define NVIC_DBG_XFER_REG_R15   0x0000000F  // Register R15\r
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010  // xPSR/Flags register\r
+#define NVIC_DBG_XFER_REG_MSP   0x00000011  // Main SP\r
+#define NVIC_DBG_XFER_REG_PSP   0x00000012  // Process SP\r
+#define NVIC_DBG_XFER_REG_DSP   0x00000013  // Deep SP\r
+#define NVIC_DBG_XFER_REG_CFBP  0x00000014  // Control/Fault/BasePri/PriMask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_DATA register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_DATA_M         0xFFFFFFFF  // Data temporary cache\r
+#define NVIC_DBG_DATA_S         0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_DBG_INT register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_DBG_INT_HARDERR    0x00000400  // Debug trap on hard fault\r
+#define NVIC_DBG_INT_INTERR     0x00000200  // Debug trap on interrupt errors\r
+#define NVIC_DBG_INT_BUSERR     0x00000100  // Debug trap on bus error\r
+#define NVIC_DBG_INT_STATERR    0x00000080  // Debug trap on usage fault state\r
+#define NVIC_DBG_INT_CHKERR     0x00000040  // Debug trap on usage fault check\r
+#define NVIC_DBG_INT_NOCPERR    0x00000020  // Debug trap on coprocessor error\r
+#define NVIC_DBG_INT_MMERR      0x00000010  // Debug trap on mem manage fault\r
+#define NVIC_DBG_INT_RESET      0x00000008  // Core reset status\r
+#define NVIC_DBG_INT_RSTPENDCLR 0x00000004  // Clear pending core reset\r
+#define NVIC_DBG_INT_RSTPENDING 0x00000002  // Core reset is pending\r
+#define NVIC_DBG_INT_RSTVCATCH  0x00000001  // Reset vector catch\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the NVIC_SW_TRIG register.\r
+//\r
+//*****************************************************************************\r
+#define NVIC_SW_TRIG_INTID_M    0x000003FF  // Interrupt to trigger\r
+#define NVIC_SW_TRIG_INTID_S    0\r
+\r
+#endif // __HW_NVIC_H__\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_pwm.h b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_pwm.h

new file mode 100644 (file)

index 0000000..b14172a
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_pwm.h
@@ -0,0 +1,260 @@
+//*****************************************************************************\r
+//\r
+// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_PWM_H__\r
+#define __HW_PWM_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Module Register Offsets.\r
+//\r
+//*****************************************************************************\r
+#define PWM_O_CTL               0x00000000  // PWM Master Control register\r
+#define PWM_O_SYNC              0x00000004  // PWM Time Base Sync register\r
+#define PWM_O_ENABLE            0x00000008  // PWM Output Enable register\r
+#define PWM_O_INVERT            0x0000000C  // PWM Output Inversion register\r
+#define PWM_O_FAULT             0x00000010  // PWM Output Fault register\r
+#define PWM_O_INTEN             0x00000014  // PWM Interrupt Enable register\r
+#define PWM_O_RIS               0x00000018  // PWM Interrupt Raw Status reg.\r
+#define PWM_O_ISC               0x0000001C  // PWM Interrupt Status register\r
+#define PWM_O_STATUS            0x00000020  // PWM Status register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Master Control register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_CTL_GLOBAL_SYNC2    0x00000004  // Global sync generator 2\r
+#define PWM_CTL_GLOBAL_SYNC1    0x00000002  // Global sync generator 1\r
+#define PWM_CTL_GLOBAL_SYNC0    0x00000001  // Global sync generator 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Time Base Sync register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_SYNC_SYNC2          0x00000004  // Reset generator 2 counter\r
+#define PWM_SYNC_SYNC1          0x00000002  // Reset generator 1 counter\r
+#define PWM_SYNC_SYNC0          0x00000001  // Reset generator 0 counter\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Output Enable register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_ENABLE_PWM5EN       0x00000020  // PWM5 pin enable\r
+#define PWM_ENABLE_PWM4EN       0x00000010  // PWM4 pin enable\r
+#define PWM_ENABLE_PWM3EN       0x00000008  // PWM3 pin enable\r
+#define PWM_ENABLE_PWM2EN       0x00000004  // PWM2 pin enable\r
+#define PWM_ENABLE_PWM1EN       0x00000002  // PWM1 pin enable\r
+#define PWM_ENABLE_PWM0EN       0x00000001  // PWM0 pin enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Inversion register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INVERT_PWM5INV      0x00000020  // PWM5 pin invert\r
+#define PWM_INVERT_PWM4INV      0x00000010  // PWM4 pin invert\r
+#define PWM_INVERT_PWM3INV      0x00000008  // PWM3 pin invert\r
+#define PWM_INVERT_PWM2INV      0x00000004  // PWM2 pin invert\r
+#define PWM_INVERT_PWM1INV      0x00000002  // PWM1 pin invert\r
+#define PWM_INVERT_PWM0INV      0x00000001  // PWM0 pin invert\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Fault register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_FAULT_FAULT5        0x00000020  // PWM5 pin fault\r
+#define PWM_FAULT_FAULT4        0x00000010  // PWM5 pin fault\r
+#define PWM_FAULT_FAULT3        0x00000008  // PWM5 pin fault\r
+#define PWM_FAULT_FAULT2        0x00000004  // PWM5 pin fault\r
+#define PWM_FAULT_FAULT1        0x00000002  // PWM5 pin fault\r
+#define PWM_FAULT_FAULT0        0x00000001  // PWM5 pin fault\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Interrupt Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INT_INTFAULT        0x00010000  // Fault interrupt pending\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the PWM Status register.\r
+//\r
+//*****************************************************************************\r
+#define PWM_STATUS_FAULT        0x00000001  // Fault status\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Generator standard offsets.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_0_OFFSET        0x00000040  // PWM0 base\r
+#define PWM_GEN_1_OFFSET        0x00000080  // PWM1 base\r
+#define PWM_GEN_2_OFFSET        0x000000C0  // PWM2 base\r
+\r
+#define PWM_O_X_CTL             0x00000000  // Gen Control Reg\r
+#define PWM_O_X_INTEN           0x00000004  // Gen Int/Trig Enable Reg\r
+#define PWM_O_X_RIS             0x00000008  // Gen Raw Int Status Reg\r
+#define PWM_O_X_ISC             0x0000000C  // Gen Int Status Reg\r
+#define PWM_O_X_LOAD            0x00000010  // Gen Load Reg\r
+#define PWM_O_X_COUNT           0x00000014  // Gen Counter Reg\r
+#define PWM_O_X_CMPA            0x00000018  // Gen Compare A Reg\r
+#define PWM_O_X_CMPB            0x0000001C  // Gen Compare B Reg\r
+#define PWM_O_X_GENA            0x00000020  // Gen Generator A Ctrl Reg\r
+#define PWM_O_X_GENB            0x00000024  // Gen Generator B Ctrl Reg\r
+#define PWM_O_X_DBCTL           0x00000028  // Gen Dead Band Ctrl Reg\r
+#define PWM_O_X_DBRISE          0x0000002C  // Gen DB Rising Edge Delay Reg\r
+#define PWM_O_X_DBFALL          0x00000030  // Gen DB Falling Edge Delay Reg\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Control Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_CTL_ENABLE        0x00000001  // Master enable for gen block\r
+#define PWM_X_CTL_MODE          0x00000002  // Counter mode, down or up/down\r
+#define PWM_X_CTL_DEBUG         0x00000004  // Debug mode\r
+#define PWM_X_CTL_LOADUPD       0x00000008  // Update mode for the load reg\r
+#define PWM_X_CTL_CMPAUPD       0x00000010  // Update mode for comp A reg\r
+#define PWM_X_CTL_CMPBUPD       0x00000020  // Update mode for comp B reg\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Interrupt/Trigger Enable Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_INTEN_INTCNTZERO  0x00000001  // Int if COUNT = 0\r
+#define PWM_X_INTEN_INTCNTLOAD  0x00000002  // Int if COUNT = LOAD\r
+#define PWM_X_INTEN_INTCMPAU    0x00000004  // Int if COUNT = CMPA U\r
+#define PWM_X_INTEN_INTCMPAD    0x00000008  // Int if COUNT = CMPA D\r
+#define PWM_X_INTEN_INTCMPBU    0x00000010  // Int if COUNT = CMPA U\r
+#define PWM_X_INTEN_INTCMPBD    0x00000020  // Int if COUNT = CMPA D\r
+#define PWM_X_INTEN_TRCNTZERO   0x00000100  // Trig if COUNT = 0\r
+#define PWM_X_INTEN_TRCNTLOAD   0x00000200  // Trig if COUNT = LOAD\r
+#define PWM_X_INTEN_TRCMPAU     0x00000400  // Trig if COUNT = CMPA U\r
+#define PWM_X_INTEN_TRCMPAD     0x00000800  // Trig if COUNT = CMPA D\r
+#define PWM_X_INTEN_TRCMPBU     0x00001000  // Trig if COUNT = CMPA U\r
+#define PWM_X_INTEN_TRCMPBD     0x00002000  // Trig if COUNT = CMPA D\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Raw Interrupt Status Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_RIS_INTCNTZERO    0x00000001  // PWM_X_COUNT = 0 int\r
+#define PWM_X_RIS_INTCNTLOAD    0x00000002  // PWM_X_COUNT = PWM_X_LOAD int\r
+#define PWM_X_RIS_INTCMPAU      0x00000004  // PWM_X_COUNT = PWM_X_CMPA U int\r
+#define PWM_X_RIS_INTCMPAD      0x00000008  // PWM_X_COUNT = PWM_X_CMPA D int\r
+#define PWM_X_RIS_INTCMPBU      0x00000010  // PWM_X_COUNT = PWM_X_CMPB U int\r
+#define PWM_X_RIS_INTCMPBD      0x00000020  // PWM_X_COUNT = PWM_X_CMPB D int\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Interrupt Status Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_INT_INTCNTZERO    0x00000001  // PWM_X_COUNT = 0 received\r
+#define PWM_X_INT_INTCNTLOAD    0x00000002  // PWM_X_COUNT = PWM_X_LOAD rcvd\r
+#define PWM_X_INT_INTCMPAU      0x00000004  // PWM_X_COUNT = PWM_X_CMPA U rcvd\r
+#define PWM_X_INT_INTCMPAD      0x00000008  // PWM_X_COUNT = PWM_X_CMPA D rcvd\r
+#define PWM_X_INT_INTCMPBU      0x00000010  // PWM_X_COUNT = PWM_X_CMPB U rcvd\r
+#define PWM_X_INT_INTCMPBD      0x00000020  // PWM_X_COUNT = PWM_X_CMPB D rcvd\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Generator A/B Control Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_X_GEN_Y_ACTZERO     0x00000003  // Act PWM_X_COUNT = 0\r
+#define PWM_X_GEN_Y_ACTLOAD     0x0000000C  // Act PWM_X_COUNT = PWM_X_LOAD\r
+#define PWM_X_GEN_Y_ACTCMPAU    0x00000030  // Act PWM_X_COUNT = PWM_X_CMPA U\r
+#define PWM_X_GEN_Y_ACTCMPAD    0x000000C0  // Act PWM_X_COUNT = PWM_X_CMPA D\r
+#define PWM_X_GEN_Y_ACTCMPBU    0x00000300  // Act PWM_X_COUNT = PWM_X_CMPB U\r
+#define PWM_X_GEN_Y_ACTCMPBD    0x00000C00  // Act PWM_X_COUNT = PWM_X_CMPB D\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Generator A/B Control Register action definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_ACT_NONE        0x0         // Do nothing\r
+#define PWM_GEN_ACT_INV         0x1         // Invert the output signal\r
+#define PWM_GEN_ACT_ZERO        0x2         // Set the output signal to zero\r
+#define PWM_GEN_ACT_ONE         0x3         // Set the output signal to one\r
+#define PWM_GEN_ACT_ZERO_SHIFT  0           // Shift amount for the zero action\r
+#define PWM_GEN_ACT_LOAD_SHIFT  2           // Shift amount for the load action\r
+#define PWM_GEN_ACT_A_UP_SHIFT  4           // Shift amount for the A up action\r
+#define PWM_GEN_ACT_A_DN_SHIFT  6           // Shift amount for the A dn action\r
+#define PWM_GEN_ACT_B_UP_SHIFT  8           // Shift amount for the B up action\r
+#define PWM_GEN_ACT_B_DN_SHIFT  10          // Shift amount for the B dn action\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM_X Dead Band Control Register bit definitions.\r
+//\r
+//*****************************************************************************\r
+#define PWM_DBCTL_ENABLE        0x00000001  // Enable dead band insertion\r
+\r
+//*****************************************************************************\r
+//\r
+// PWM Register reset values.\r
+//\r
+//*****************************************************************************\r
+#define PWM_RV_CTL              0x00000000  // Master control of the PWM module\r
+#define PWM_RV_SYNC             0x00000000  // Counter synch for PWM generators\r
+#define PWM_RV_ENABLE           0x00000000  // Master enable for the PWM\r
+                                            // output pins\r
+#define PWM_RV_INVERT           0x00000000  // Inversion control for\r
+                                            // PWM output pins\r
+#define PWM_RV_FAULT            0x00000000  // Fault handling for the PWM\r
+                                            // output pins\r
+#define PWM_RV_INTEN            0x00000000  // Interrupt enable\r
+#define PWM_RV_RIS              0x00000000  // Raw interrupt status\r
+#define PWM_RV_ISC              0x00000000  // Interrupt status and clearing\r
+#define PWM_RV_STATUS           0x00000000  // Status\r
+#define PWM_RV_X_CTL            0x00000000  // Master control of the PWM\r
+                                            // generator block\r
+#define PWM_RV_X_INTEN          0x00000000  // Interrupt and trigger enable\r
+#define PWM_RV_X_RIS            0x00000000  // Raw interrupt status\r
+#define PWM_RV_X_ISC            0x00000000  // Interrupt status and clearing\r
+#define PWM_RV_X_LOAD           0x00000000  // The load value for the counter\r
+#define PWM_RV_X_COUNT          0x00000000  // The current counter value\r
+#define PWM_RV_X_CMPA           0x00000000  // The comparator A value\r
+#define PWM_RV_X_CMPB           0x00000000  // The comparator B value\r
+#define PWM_RV_X_GENA           0x00000000  // Controls PWM generator A\r
+#define PWM_RV_X_GENB           0x00000000  // Controls PWM generator B\r
+#define PWM_RV_X_DBCTL          0x00000000  // Control the dead band generator\r
+#define PWM_RV_X_DBRISE         0x00000000  // The dead band rising edge delay\r
+                                            // count\r
+#define PWM_RV_X_DBFALL         0x00000000  // The dead band falling edge delay\r
+                                            // count\r
+\r
+#endif //  __HW_PWM_H__\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_ssi.h b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_ssi.h

new file mode 100644 (file)

index 0000000..c8a18fc
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_ssi.h
@@ -0,0 +1,120 @@
+//*****************************************************************************\r
+//\r
+// hw_ssi.h - Macros used when accessing the SSI hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_SSI_H__\r
+#define __HW_SSI_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the SSI registers.\r
+//\r
+//*****************************************************************************\r
+#define SSI_O_CR0               0x00000000  // Control register 0\r
+#define SSI_O_CR1               0x00000004  // Control register 1\r
+#define SSI_O_DR                0x00000008  // Data register\r
+#define SSI_O_SR                0x0000000C  // Status register\r
+#define SSI_O_CPSR              0x00000010  // Clock prescale register\r
+#define SSI_O_IM                0x00000014  // Int mask set and clear register\r
+#define SSI_O_RIS               0x00000018  // Raw interrupt register\r
+#define SSI_O_MIS               0x0000001C  // Masked interrupt register\r
+#define SSI_O_ICR               0x00000020  // Interrupt clear register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI Control register 0.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CR0_SCR             0x0000FF00  // Serial clock rate\r
+#define SSI_CR0_SPH             0x00000080  // SSPCLKOUT phase\r
+#define SSI_CR0_SPO             0x00000040  // SSPCLKOUT polarity\r
+#define SSI_CR0_FRF_MASK        0x00000030  // Frame format mask\r
+#define SSI_CR0_FRF_MOTO        0x00000000  // Motorola SPI frame format\r
+#define SSI_CR0_FRF_TI          0x00000010  // TI sync serial frame format\r
+#define SSI_CR0_FRF_NMW         0x00000020  // National Microwire frame format\r
+#define SSI_CR0_DSS             0x0000000F  // Data size select\r
+#define SSI_CR0_DSS_4           0x00000003  // 4 bit data\r
+#define SSI_CR0_DSS_5           0x00000004  // 5 bit data\r
+#define SSI_CR0_DSS_6           0x00000005  // 6 bit data\r
+#define SSI_CR0_DSS_7           0x00000006  // 7 bit data\r
+#define SSI_CR0_DSS_8           0x00000007  // 8 bit data\r
+#define SSI_CR0_DSS_9           0x00000008  // 9 bit data\r
+#define SSI_CR0_DSS_10          0x00000009  // 10 bit data\r
+#define SSI_CR0_DSS_11          0x0000000A  // 11 bit data\r
+#define SSI_CR0_DSS_12          0x0000000B  // 12 bit data\r
+#define SSI_CR0_DSS_13          0x0000000C  // 13 bit data\r
+#define SSI_CR0_DSS_14          0x0000000D  // 14 bit data\r
+#define SSI_CR0_DSS_15          0x0000000E  // 15 bit data\r
+#define SSI_CR0_DSS_16          0x0000000F  // 16 bit data\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI Control register 1.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CR1_SOD             0x00000008  // Slave mode output disable\r
+#define SSI_CR1_MS              0x00000004  // Master or slave mode select\r
+#define SSI_CR1_SSE             0x00000002  // Sync serial port enable\r
+#define SSI_CR1_LBM             0x00000001  // Loopback mode\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI Status register.\r
+//\r
+//*****************************************************************************\r
+#define SSI_SR_BSY              0x00000010  // SSI busy\r
+#define SSI_SR_RFF              0x00000008  // RX FIFO full\r
+#define SSI_SR_RNE              0x00000004  // RX FIFO not empty\r
+#define SSI_SR_TNF              0x00000002  // TX FIFO not full\r
+#define SSI_SR_TFE              0x00000001  // TX FIFO empty\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SSI clock prescale register.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CPSR_CPSDVSR_MASK   0x000000FF  // Clock prescale\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define information concerning the SSI Data register.\r
+//\r
+//*****************************************************************************\r
+#define TX_FIFO_SIZE            (8)         // Number of entries in the TX FIFO\r
+#define RX_FIFO_SIZE            (8)         // Number of entries in the RX FIFO\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the interrupt mask set and clear,\r
+// raw interrupt, masked interrupt, and interrupt clear registers.\r
+//\r
+//*****************************************************************************\r
+#define SSI_INT_TXFF            0x00000008  // TX FIFO interrupt\r
+#define SSI_INT_RXFF            0x00000004  // RX FIFO interrupt\r
+#define SSI_INT_RXTO            0x00000002  // RX timeout interrupt\r
+#define SSI_INT_RXOR            0x00000001  // RX overrun interrupt\r
+\r
+#endif // __HW_SSI_H__\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_sysctl.h b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_sysctl.h

new file mode 100644 (file)

index 0000000..9a8fff4
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_sysctl.h
@@ -0,0 +1,380 @@
+//*****************************************************************************\r
+//\r
+// hw_sysctl.h - Macros used when accessing the system control hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_SYSCTL_H__\r
+#define __HW_SYSCTL_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the system control registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID0             0x400fe000  // Device identification register 0\r
+#define SYSCTL_DID1             0x400fe004  // Device identification register 1\r
+#define SYSCTL_DC0              0x400fe008  // Device capabilities register 0\r
+#define SYSCTL_DC1              0x400fe010  // Device capabilities register 1\r
+#define SYSCTL_DC2              0x400fe014  // Device capabilities register 2\r
+#define SYSCTL_DC3              0x400fe018  // Device capabilities register 3\r
+#define SYSCTL_DC4              0x400fe01C  // Device capabilities register 4\r
+#define SYSCTL_PBORCTL          0x400fe030  // POR/BOR reset control register\r
+#define SYSCTL_LDOPCTL          0x400fe034  // LDO power control register\r
+#define SYSCTL_SRCR0            0x400fe040  // Software reset control reg 0\r
+#define SYSCTL_SRCR1            0x400fe044  // Software reset control reg 1\r
+#define SYSCTL_SRCR2            0x400fe048  // Software reset control reg 2\r
+#define SYSCTL_RIS              0x400fe050  // Raw interrupt status register\r
+#define SYSCTL_IMC              0x400fe054  // Interrupt mask/control register\r
+#define SYSCTL_MISC             0x400fe058  // Interrupt status register\r
+#define SYSCTL_RESC             0x400fe05c  // Reset cause register\r
+#define SYSCTL_RCC              0x400fe060  // Run-mode clock config register\r
+#define SYSCTL_PLLCFG           0x400fe064  // PLL configuration register\r
+#define SYSCTL_RCGC0            0x400fe100  // Run-mode clock gating register 0\r
+#define SYSCTL_RCGC1            0x400fe104  // Run-mode clock gating register 1\r
+#define SYSCTL_RCGC2            0x400fe108  // Run-mode clock gating register 2\r
+#define SYSCTL_SCGC0            0x400fe110  // Sleep-mode clock gating reg 0\r
+#define SYSCTL_SCGC1            0x400fe114  // Sleep-mode clock gating reg 1\r
+#define SYSCTL_SCGC2            0x400fe118  // Sleep-mode clock gating reg 2\r
+#define SYSCTL_DCGC0            0x400fe120  // Deep Sleep-mode clock gate reg 0\r
+#define SYSCTL_DCGC1            0x400fe124  // Deep Sleep-mode clock gate reg 1\r
+#define SYSCTL_DCGC2            0x400fe128  // Deep Sleep-mode clock gate reg 2\r
+#define SYSCTL_CLKVCLR          0x400fe150  // Clock verifcation clear register\r
+#define SYSCTL_LDOARST          0x400fe160  // LDO reset control register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DID0 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID0_VER_MASK    0x70000000  // DID0 version mask\r
+#define SYSCTL_DID0_VER_0       0x00000000  // DID0 version 0\r
+#define SYSCTL_DID0_MAJ_MASK    0x0000FF00  // Major revision mask\r
+#define SYSCTL_DID0_MAJ_A       0x00000000  // Major revision A\r
+#define SYSCTL_DID0_MAJ_B       0x00000100  // Major revision B\r
+#define SYSCTL_DID0_MIN_MASK    0x000000FF  // Minor revision mask\r
+#define SYSCTL_DID0_MIN_0       0x00000000  // Minor revision 0\r
+#define SYSCTL_DID0_MIN_1       0x00000001  // Minor revision 1\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DID1 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DID1_VER_MASK    0xF0000000  // Register version mask\r
+#define SYSCTL_DID1_FAM_MASK    0x0F000000  // Family mask\r
+#define SYSCTL_DID1_FAM_S       0x00000000  // Stellaris family\r
+#define SYSCTL_DID1_PRTNO_MASK  0x00FF0000  // Part number mask\r
+#define SYSCTL_DID1_PRTNO_101   0x00010000  // LM3S101\r
+#define SYSCTL_DID1_PRTNO_102   0x00020000  // LM3S102\r
+#define SYSCTL_DID1_PRTNO_301   0x00110000  // LM3S301\r
+#define SYSCTL_DID1_PRTNO_310   0x00120000  // LM3S310\r
+#define SYSCTL_DID1_PRTNO_315   0x00130000  // LM3S315\r
+#define SYSCTL_DID1_PRTNO_316   0x00140000  // LM3S316\r
+#define SYSCTL_DID1_TEMP_MASK   0x000000E0  // Temperature range mask\r
+#define SYSCTL_DID1_TEMP_C      0x00000000  // Commercial temp range (0..70C)\r
+#define SYSCTL_DID1_TEMP_I      0x00000020  // Industrial temp range (-40..85C)\r
+#define SYSCTL_DID1_PKG_MASK    0x00000018  // Package mask\r
+#define SYSCTL_DID1_PKG_28SOIC  0x00000000  // 28-pin SOIC\r
+#define SYSCTL_DID1_PKG_48QFP   0x00000008  // 48-pin QFP\r
+#define SYSCTL_DID1_ROHS        0x00000004  // Part is RoHS compliant\r
+#define SYSCTL_DID1_QUAL_MASK   0x00000003  // Qualification status mask\r
+#define SYSCTL_DID1_QUAL_ES     0x00000000  // Engineering sample (unqualified)\r
+#define SYSCTL_DID1_QUAL_PP     0x00000001  // Pilot production (unqualified)\r
+#define SYSCTL_DID1_QUAL_FQ     0x00000002  // Fully qualified\r
+#define SYSCTL_DID1_PRTNO_SHIFT 16\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC0 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC0_SRAMSZ_MASK  0xFFFF0000  // SRAM size mask\r
+#define SYSCTL_DC0_SRAMSZ_2KB   0x00070000  // 2kB of SRAM\r
+#define SYSCTL_DC0_SRAMSZ_4KB   0x000F0000  // 4kB of SRAM\r
+#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF  // Flash size mask\r
+#define SYSCTL_DC0_FLASHSZ_8KB  0x00000003  // 8kB of flash\r
+#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007  // 16kB of flash\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC1 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC1_PWM          0x00100000  // PWM module present\r
+#define SYSCTL_DC1_ADC          0x00010000  // ADC module present\r
+#define SYSCTL_DC1_SYSDIV_MASK  0x0000F000  // Minimum system divider mask\r
+#define SYSCTL_DC1_ADCSPD_MASK  0x00000F00  // ADC speed mask\r
+#define SYSCTL_DC1_ADCSPD_250K  0x00000100  // 250Ksps ADC\r
+#define SYSCTL_DC1_ADCSPD_125K  0x00000000  // 125Ksps ADC\r
+#define SYSCTL_DC1_MPU          0x00000080  // Cortex M3 MPU present\r
+#define SYSCTL_DC1_TEMP         0x00000020  // Temperature sensor present\r
+#define SYSCTL_DC1_PLL          0x00000010  // PLL present\r
+#define SYSCTL_DC1_WDOG         0x00000008  // Watchdog present\r
+#define SYSCTL_DC1_SWO          0x00000004  // Serial wire output present\r
+#define SYSCTL_DC1_SWD          0x00000002  // Serial wire debug present\r
+#define SYSCTL_DC1_JTAG         0x00000001  // JTAG debug present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC2 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC2_COMP2        0x04000000  // Analog comparator 2 present\r
+#define SYSCTL_DC2_COMP1        0x02000000  // Analog comparator 1 present\r
+#define SYSCTL_DC2_COMP0        0x01000000  // Analog comparator 0 present\r
+#define SYSCTL_DC2_TIMER2       0x00040000  // Timer 2 present\r
+#define SYSCTL_DC2_TIMER1       0x00020000  // Timer 1 present\r
+#define SYSCTL_DC2_TIMER0       0x00010000  // Timer 0 present\r
+#define SYSCTL_DC2_I2C          0x00001000  // I2C present\r
+#define SYSCTL_DC2_SSI          0x00000010  // SSI present\r
+#define SYSCTL_DC2_UART1        0x00000002  // UART 1 present\r
+#define SYSCTL_DC2_UART0        0x00000001  // UART 0 present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC3 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC3_32KHZ        0x80000000  // 32kHz pin present\r
+#define SYSCTL_DC3_CCP5         0x20000000  // CCP5 pin present\r
+#define SYSCTL_DC3_CCP4         0x10000000  // CCP4 pin present\r
+#define SYSCTL_DC3_CCP3         0x08000000  // CCP3 pin present\r
+#define SYSCTL_DC3_CCP2         0x04000000  // CCP2 pin present\r
+#define SYSCTL_DC3_CCP1         0x02000000  // CCP1 pin present\r
+#define SYSCTL_DC3_CCP0         0x01000000  // CCP0 pin present\r
+#define SYSCTL_DC3_ADC3         0x00080000  // ADC3 pin present\r
+#define SYSCTL_DC3_ADC2         0x00040000  // ADC2 pin present\r
+#define SYSCTL_DC3_ADC1         0x00020000  // ADC1 pin present\r
+#define SYSCTL_DC3_ADC0         0x00010000  // ADC0 pin present\r
+#define SYSCTL_DC3_C2O          0x00004000  // C2o pin present\r
+#define SYSCTL_DC3_C2PLUS       0x00002000  // C2+ pin present\r
+#define SYSCTL_DC3_C2MINUS      0x00001000  // C2- pin present\r
+#define SYSCTL_DC3_C1O          0x00000800  // C1o pin present\r
+#define SYSCTL_DC3_C1PLUS       0x00000400  // C1+ pin present\r
+#define SYSCTL_DC3_C1MINUS      0x00000200  // C1- pin present\r
+#define SYSCTL_DC3_C0O          0x00000100  // C0o pin present\r
+#define SYSCTL_DC3_C0PLUS       0x00000080  // C0+ pin present\r
+#define SYSCTL_DC3_C0MINUS      0x00000040  // C0- pin present\r
+#define SYSCTL_DC3_PWM5         0x00000020  // PWM5 pin present\r
+#define SYSCTL_DC3_PWM4         0x00000010  // PWM4 pin present\r
+#define SYSCTL_DC3_PWM3         0x00000008  // PWM3 pin present\r
+#define SYSCTL_DC3_PWM2         0x00000004  // PWM2 pin present\r
+#define SYSCTL_DC3_PWM1         0x00000002  // PWM1 pin present\r
+#define SYSCTL_DC3_PWM0         0x00000001  // PWM0 pin present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_DC4 register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_DC4_GPIOE        0x00000010  // GPIO port E present\r
+#define SYSCTL_DC4_GPIOD        0x00000008  // GPIO port D present\r
+#define SYSCTL_DC4_GPIOC        0x00000004  // GPIO port C present\r
+#define SYSCTL_DC4_GPIOB        0x00000002  // GPIO port B present\r
+#define SYSCTL_DC4_GPIOA        0x00000001  // GPIO port A present\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_PBORCTL register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC  // BOR wait timer\r
+#define SYSCTL_PBORCTL_BORIOR   0x00000002  // BOR interrupt or reset\r
+#define SYSCTL_PBORCTL_BORWT    0x00000001  // BOR wait and check for noise\r
+#define SYSCTL_PBORCTL_BOR_SH   2\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_LDOPCTL register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOPCTL_MASK     0x0000003F  // Voltage adjust mask\r
+#define SYSCTL_LDOPCTL_2_25V    0x00000005  // LDO output of 2.25V\r
+#define SYSCTL_LDOPCTL_2_30V    0x00000004  // LDO output of 2.30V\r
+#define SYSCTL_LDOPCTL_2_35V    0x00000003  // LDO output of 2.35V\r
+#define SYSCTL_LDOPCTL_2_40V    0x00000002  // LDO output of 2.40V\r
+#define SYSCTL_LDOPCTL_2_45V    0x00000001  // LDO output of 2.45V\r
+#define SYSCTL_LDOPCTL_2_50V    0x00000000  // LDO output of 2.50V\r
+#define SYSCTL_LDOPCTL_2_55V    0x0000001F  // LDO output of 2.55V\r
+#define SYSCTL_LDOPCTL_2_60V    0x0000001E  // LDO output of 2.60V\r
+#define SYSCTL_LDOPCTL_2_65V    0x0000001D  // LDO output of 2.65V\r
+#define SYSCTL_LDOPCTL_2_70V    0x0000001C  // LDO output of 2.70V\r
+#define SYSCTL_LDOPCTL_2_75V    0x0000001B  // LDO output of 2.75V\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_SRCR0, SYSCTL_RCGC0,\r
+// SYSCTL_SCGC0, and SYSCTL_DCGC0 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET0_PWM         0x00100000  // PWM module\r
+#define SYSCTL_SET0_ADC         0x00010000  // ADC module\r
+#define SYSCTL_SET0_WDOG        0x00000008  // Watchdog module\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_SRCR1, SYSCTL_RCGC1,\r
+// SYSCTL_SCGC1, and SYSCTL_DCGC1 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET1_COMP2       0x04000000  // Analog comparator module 2\r
+#define SYSCTL_SET1_COMP1       0x02000000  // Analog comparator module 1\r
+#define SYSCTL_SET1_COMP0       0x01000000  // Analog comparator module 0\r
+#define SYSCTL_SET1_TIMER2      0x00040000  // Timer module 2\r
+#define SYSCTL_SET1_TIMER1      0x00020000  // Timer module 1\r
+#define SYSCTL_SET1_TIMER0      0x00010000  // Timer module 0\r
+#define SYSCTL_SET1_I2C         0x00001000  // I2C module\r
+#define SYSCTL_SET1_SSI         0x00000010  // SSI module\r
+#define SYSCTL_SET1_UART1       0x00000002  // UART module 1\r
+#define SYSCTL_SET1_UART0       0x00000001  // UART module 0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_SRCR2, SYSCTL_RCGC2,\r
+// SYSCTL_SCGC2, and SYSCTL_DCGC2 registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SET2_GPIOE       0x00000010  // GPIO E module\r
+#define SYSCTL_SET2_GPIOD       0x00000008  // GPIO D module\r
+#define SYSCTL_SET2_GPIOC       0x00000004  // GPIO C module\r
+#define SYSCTL_SET2_GPIOB       0x00000002  // GPIO B module\r
+#define SYSCTL_SET2_GPIOA       0x00000001  // GIPO A module\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RIS, SYSCTL_IMC, and\r
+// SYSCTL_IMS registers.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_INT_PLL_LOCK     0x00000040  // PLL lock interrupt\r
+#define SYSCTL_INT_CUR_LIMIT    0x00000020  // Current limit interrupt\r
+#define SYSCTL_INT_IOSC_FAIL    0x00000010  // Internal oscillator failure int\r
+#define SYSCTL_INT_MOSC_FAIL    0x00000008  // Main oscillator failure int\r
+#define SYSCTL_INT_POR          0x00000004  // Power on reset interrupt\r
+#define SYSCTL_INT_BOR          0x00000002  // Brown out interrupt\r
+#define SYSCTL_INT_PLL_FAIL     0x00000001  // PLL failure interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RESC register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RESC_LDO         0x00000020  // LDO power OK lost reset\r
+#define SYSCTL_RESC_SW          0x00000010  // Software reset\r
+#define SYSCTL_RESC_WDOG        0x00000008  // Watchdog reset\r
+#define SYSCTL_RESC_BOR         0x00000004  // Brown-out reset\r
+#define SYSCTL_RESC_POR         0x00000002  // Power on reset\r
+#define SYSCTL_RESC_EXT         0x00000001  // External reset\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_RCC register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_RCC_ACG          0x08000000  // Automatic clock gating\r
+#define SYSCTL_RCC_SYSDIV_MASK  0x07800000  // System clock divider\r
+#define SYSCTL_RCC_SYSDIV_2     0x00800000  // System clock /2\r
+#define SYSCTL_RCC_SYSDIV_3     0x01000000  // System clock /3\r
+#define SYSCTL_RCC_SYSDIV_4     0x01800000  // System clock /4\r
+#define SYSCTL_RCC_SYSDIV_5     0x02000000  // System clock /5\r
+#define SYSCTL_RCC_SYSDIV_6     0x02800000  // System clock /6\r
+#define SYSCTL_RCC_SYSDIV_7     0x03000000  // System clock /7\r
+#define SYSCTL_RCC_SYSDIV_8     0x03800000  // System clock /8\r
+#define SYSCTL_RCC_SYSDIV_9     0x04000000  // System clock /9\r
+#define SYSCTL_RCC_SYSDIV_10    0x04800000  // System clock /10\r
+#define SYSCTL_RCC_SYSDIV_11    0x05000000  // System clock /11\r
+#define SYSCTL_RCC_SYSDIV_12    0x05800000  // System clock /12\r
+#define SYSCTL_RCC_SYSDIV_13    0x06000000  // System clock /13\r
+#define SYSCTL_RCC_SYSDIV_14    0x06800000  // System clock /14\r
+#define SYSCTL_RCC_SYSDIV_15    0x07000000  // System clock /15\r
+#define SYSCTL_RCC_SYSDIV_16    0x07800000  // System clock /16\r
+#define SYSCTL_RCC_USE_SYSDIV   0x00400000  // Use sytem clock divider\r
+#define SYSCTL_RCC_USE_PWMDIV   0x00100000  // Use PWM clock divider\r
+#define SYSCTL_RCC_PWMDIV_MASK  0x000E0000  // PWM clock divider\r
+#define SYSCTL_RCC_PWMDIV_2     0x00000000  // PWM clock /2\r
+#define SYSCTL_RCC_PWMDIV_4     0x00020000  // PWM clock /4\r
+#define SYSCTL_RCC_PWMDIV_8     0x00040000  // PWM clock /8\r
+#define SYSCTL_RCC_PWMDIV_16    0x00060000  // PWM clock /16\r
+#define SYSCTL_RCC_PWMDIV_32    0x00080000  // PWM clock /32\r
+#define SYSCTL_RCC_PWMDIV_64    0x000A0000  // PWM clock /64\r
+#define SYSCTL_RCC_PWRDN        0x00002000  // PLL power down\r
+#define SYSCTL_RCC_OE           0x00001000  // PLL output enable\r
+#define SYSCTL_RCC_BYPASS       0x00000800  // PLL bypass\r
+#define SYSCTL_RCC_PLLVER       0x00000400  // PLL verification timer enable\r
+#define SYSCTL_RCC_XTAL_MASK    0x000003C0  // Crystal attached to main osc\r
+#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100  // Using a 3.579545MHz crystal\r
+#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140  // Using a 3.6864MHz crystal\r
+#define SYSCTL_RCC_XTAL_4MHz    0x00000180  // Using a 4MHz crystal\r
+#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0  // Using a 4.096MHz crystal\r
+#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200  // Using a 4.9152MHz crystal\r
+#define SYSCTL_RCC_XTAL_5MHZ    0x00000240  // Using a 5MHz crystal\r
+#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280  // Using a 5.12MHz crystal\r
+#define SYSCTL_RCC_XTAL_6MHZ    0x000002C0  // Using a 6MHz crystal\r
+#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300  // Using a 6.144MHz crystal\r
+#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340  // Using a 7.3728MHz crystal\r
+#define SYSCTL_RCC_XTAL_8MHZ    0x00000380  // Using a 8MHz crystal\r
+#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0  // Using a 8.192MHz crystal\r
+#define SYSCTL_RCC_OSCSRC_MASK  0x00000030  // Oscillator input select\r
+#define SYSCTL_RCC_OSCSRC_MAIN  0x00000000  // Use the main oscillator\r
+#define SYSCTL_RCC_OSCSRC_INT   0x00000010  // Use the internal oscillator\r
+#define SYSCTL_RCC_OSCSRC_INT4  0x00000020  // Use the internal oscillator / 4\r
+#define SYSCTL_RCC_IOSCVER      0x00000008  // Int. osc. verification timer en\r
+#define SYSCTL_RCC_MOSCVER      0x00000004  // Main osc. verification timer en\r
+#define SYSCTL_RCC_IOSCDIS      0x00000002  // Internal oscillator disable\r
+#define SYSCTL_RCC_MOSCDIS      0x00000001  // Main oscillator disable\r
+#define SYSCTL_RCC_SYSDIV_SHIFT 23          // Shift to the SYSDIV field\r
+#define SYSCTL_RCC_PWMDIV_SHIFT 17          // Shift to the PWMDIV field\r
+#define SYSCTL_RCC_XTAL_SHIFT   6           // Shift to the XTAL field\r
+#define SYSCTL_RCC_OSCSRC_SHIFT 4           // Shift to the OSCSRC field\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_PLLCFG register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PLLCFG_OD_MASK   0x0000C000  // Output divider\r
+#define SYSCTL_PLLCFG_OD_1      0x00000000  // Output divider is 1\r
+#define SYSCTL_PLLCFG_OD_2      0x00004000  // Output divider is 2\r
+#define SYSCTL_PLLCFG_OD_4      0x00008000  // Output divider is 4\r
+#define SYSCTL_PLLCFG_F_MASK    0x00003FE0  // PLL multiplier\r
+#define SYSCTL_PLLCFG_R_MASK    0x0000001F  // Input predivider\r
+#define SYSCTL_PLLCFG_F_SHIFT   5\r
+#define SYSCTL_PLLCFG_R_SHIFT   0\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_CLKVCLR register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_CLKVCLR_CLR      0x00000001  // Clear clock verification fault\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the SYSCTL_LDOARST register.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOARST_ARST     0x00000001  // Allow LDO to reset device\r
+\r
+#endif // __HW_SYSCTL_H__\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_timer.h b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_timer.h

new file mode 100644 (file)

index 0000000..9954a9f
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_timer.h
@@ -0,0 +1,235 @@
+//*****************************************************************************\r
+//\r
+// hw_timer.h - Defines and macros used when accessing the timer.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_TIMER_H__\r
+#define __HW_TIMER_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the timer registers.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_O_CFG             0x00000000  // Configuration register\r
+#define TIMER_O_TAMR            0x00000004  // TimerA mode register\r
+#define TIMER_O_TBMR            0x00000008  // TimerB mode register\r
+#define TIMER_O_CTL             0x0000000C  // Control register\r
+#define TIMER_O_IMR             0x00000018  // Interrupt mask register\r
+#define TIMER_O_RIS             0x0000001C  // Interrupt status register\r
+#define TIMER_O_MIS             0x00000020  // Masked interrupt status reg.\r
+#define TIMER_O_ICR             0x00000024  // Interrupt clear register\r
+#define TIMER_O_TAILR           0x00000028  // TimerA interval load register\r
+#define TIMER_O_TBILR           0x0000002C  // TimerB interval load register\r
+#define TIMER_O_TAMATCHR        0x00000030  // TimerA match register\r
+#define TIMER_O_TBMATCHR        0x00000034  // TimerB match register\r
+#define TIMER_O_TAPR            0x00000038  // TimerA prescale register\r
+#define TIMER_O_TBPR            0x0000003C  // TimerB prescale register\r
+#define TIMER_O_TAPMR           0x00000040  // TimerA prescale match register\r
+#define TIMER_O_TBPMR           0x00000044  // TimerB prescale match register\r
+#define TIMER_O_TAR             0x00000048  // TimerA register\r
+#define TIMER_O_TBR             0x0000004C  // TimerB register\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values of the timer registers.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_RV_CFG            0x00000000  // Configuration register RV\r
+#define TIMER_RV_TAMR           0x00000000  // TimerA mode register RV\r
+#define TIMER_RV_TBMR           0x00000000  // TimerB mode register RV\r
+#define TIMER_RV_CTL            0x00000000  // Control register RV\r
+#define TIMER_RV_IMR            0x00000000  // Interrupt mask register RV\r
+#define TIMER_RV_RIS            0x00000000  // Interrupt status register RV\r
+#define TIMER_RV_MIS            0x00000000  // Masked interrupt status reg RV\r
+#define TIMER_RV_ICR            0x00000000  // Interrupt clear register RV\r
+#define TIMER_RV_TAILR          0xFFFFFFFF  // TimerA interval load reg RV\r
+#define TIMER_RV_TBILR          0x0000FFFF  // TimerB interval load reg RV\r
+#define TIMER_RV_TAMATCHR       0xFFFFFFFF  // TimerA match register RV\r
+#define TIMER_RV_TBMATCHR       0x0000FFFF  // TimerB match register RV\r
+#define TIMER_RV_TAPR           0x00000000  // TimerA prescale register RV\r
+#define TIMER_RV_TBPR           0x00000000  // TimerB prescale register RV\r
+#define TIMER_RV_TAPMR          0x00000000  // TimerA prescale match reg RV\r
+#define TIMER_RV_TBPMR          0x00000000  // TimerB prescale match regi RV\r
+#define TIMER_RV_TAR            0xFFFFFFFF  // TimerA register RV\r
+#define TIMER_RV_TBR            0x0000FFFF  // TimerB register RV\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_CFG register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CFG_CFG_MSK       0x00000007  // Configuration options mask\r
+#define TIMER_CFG_16_BIT        0x00000004  // Two 16 bit timers\r
+#define TIMER_CFG_32_BIT_RTC    0x00000001  // 32 bit RTC\r
+#define TIMER_CFG_32_BIT_TIMER  0x00000000  // 32 bit timer\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TnMR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TNMR_TNAMS        0x00000008  // Alternate mode select\r
+#define TIMER_TNMR_TNCMR        0x00000004  // Capture mode - count or time\r
+#define TIMER_TNMR_TNTMR_MSK    0x00000003  // Timer mode mask\r
+#define TIMER_TNMR_TNTMR_CAP    0x00000003  // Mode - capture\r
+#define TIMER_TNMR_TNTMR_PERIOD 0x00000002  // Mode - periodic\r
+#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001  // Mode - one shot\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_CTL register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CTL_TBPWML        0x00004000  // TimerB PWM output level invert\r
+#define TIMER_CTL_TBOTE         0x00002000  // TimerB output trigger enable\r
+#define TIMER_CTL_TBEVENT_MSK   0x00000C00  // TimerB event mode mask\r
+#define TIMER_CTL_TBEVENT_BOTH  0x00000C00  // TimerB event mode - both edges\r
+#define TIMER_CTL_TBEVENT_NEG   0x00000400  // TimerB event mode - neg edge\r
+#define TIMER_CTL_TBEVENT_POS   0x00000000  // TimerB event mode - pos edge\r
+#define TIMER_CTL_TBSTALL       0x00000200  // TimerB stall enable\r
+#define TIMER_CTL_TBEN          0x00000100  // TimerB enable\r
+#define TIMER_CTL_TAPWML        0x00000040  // TimerA PWM output level invert\r
+#define TIMER_CTL_TAOTE         0x00000020  // TimerA output trigger enable\r
+#define TIMER_CTL_RTCEN         0x00000010  // RTC counter enable\r
+#define TIMER_CTL_TAEVENT_MSK   0x0000000C  // TimerA event mode mask\r
+#define TIMER_CTL_TAEVENT_BOTH  0x0000000C  // TimerA event mode - both edges\r
+#define TIMER_CTL_TAEVENT_NEG   0x00000004  // TimerA event mode - neg edge\r
+#define TIMER_CTL_TAEVENT_POS   0x00000000  // TimerA event mode - pos edge\r
+#define TIMER_CTL_TASTALL       0x00000002  // TimerA stall enable\r
+#define TIMER_CTL_TAEN          0x00000001  // TimerA enable\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_IMR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_IMR_CBEIM         0x00000400  // CaptureB event interrupt mask\r
+#define TIMER_IMR_CBMIM         0x00000200  // CaptureB match interrupt mask\r
+#define TIMER_IMR_TBTOIM        0x00000100  // TimerB time out interrupt mask\r
+#define TIMER_IMR_RTCIM         0x00000008  // RTC interrupt mask\r
+#define TIMER_IMR_CAEIM         0x00000004  // CaptureA event interrupt mask\r
+#define TIMER_IMR_CAMIM         0x00000002  // CaptureA match interrupt mask\r
+#define TIMER_IMR_TATOIM        0x00000001  // TimerA time out interrupt mask\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_RIS register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_RIS_CBERIS        0x00000400  // CaptureB event raw int status\r
+#define TIMER_RIS_CBMRIS        0x00000200  // CaptureB match raw int status\r
+#define TIMER_RIS_TBTORIS       0x00000100  // TimerB time out raw int status\r
+#define TIMER_RIS_RTCRIS        0x00000008  // RTC raw int status\r
+#define TIMER_RIS_CAERIS        0x00000004  // CaptureA event raw int status\r
+#define TIMER_RIS_CAMRIS        0x00000002  // CaptureA match raw int status\r
+#define TIMER_RIS_TATORIS       0x00000001  // TimerA time out raw int status\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_MIS register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_RIS_CBEMIS        0x00000400  // CaptureB event masked int status\r
+#define TIMER_RIS_CBMMIS        0x00000200  // CaptureB match masked int status\r
+#define TIMER_RIS_TBTOMIS       0x00000100  // TimerB time out masked int stat\r
+#define TIMER_RIS_RTCMIS        0x00000008  // RTC masked int status\r
+#define TIMER_RIS_CAEMIS        0x00000004  // CaptureA event masked int status\r
+#define TIMER_RIS_CAMMIS        0x00000002  // CaptureA match masked int status\r
+#define TIMER_RIS_TATOMIS       0x00000001  // TimerA time out masked int stat\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_ICR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_ICR_CBECINT       0x00000400  // CaptureB event interrupt clear\r
+#define TIMER_ICR_CBMCINT       0x00000200  // CaptureB match interrupt clear\r
+#define TIMER_ICR_TBTOCINT      0x00000100  // TimerB time out interrupt clear\r
+#define TIMER_ICR_RTCCINT       0x00000008  // RTC interrupt clear\r
+#define TIMER_ICR_CAECINT       0x00000004  // CaptureA event interrupt clear\r
+#define TIMER_ICR_CAMCINT       0x00000002  // CaptureA match interrupt clear\r
+#define TIMER_ICR_TATOCINT      0x00000001  // TimerA time out interrupt clear\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TAILR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAILR_TAILRH      0xFFFF0000  // TimerB load val in 32 bit mode\r
+#define TIMER_TAILR_TAILRL      0x0000FFFF  // TimerA interval load value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TBILR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBILR_TBILRL      0x0000FFFF  // TimerB interval load value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TAMATCHR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAMATCHR_TAMRH    0xFFFF0000  // TimerB match val in 32 bit mode\r
+#define TIMER_TAMATCHR_TAMRL    0x0000FFFF  // TimerA match value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TBMATCHR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBMATCHR_TBMRL    0x0000FFFF  // TimerB match load value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TnPR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TNPR_TNPSR        0x000000FF  // TimerN prescale value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TnPMR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TNPMR_TNPSMR      0x000000FF  // TimerN prescale match value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the TIMER_TAR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TAR_TARH          0xFFFF0000  // TimerB val in 32 bit mode\r
+#define TIMER_TAR_TARL          0x0000FFFF  // TimerA value\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines the bit fields in the TIMER_TBR register.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_TBR_TBRL          0x0000FFFF  // TimerB value\r
+\r
+#endif // __HW_TIMER_H__\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_types.h b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_types.h

new file mode 100644 (file)

index 0000000..a3b9dcb
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_types.h
@@ -0,0 +1,67 @@
+//*****************************************************************************\r
+//\r
+// hw_types.h - Common types and macros.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_TYPES_H__\r
+#define __HW_TYPES_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// Define a boolean type, and values for true and false.\r
+//\r
+//*****************************************************************************\r
+typedef unsigned char tBoolean;\r
+\r
+#ifndef true\r
+#define true 1\r
+#endif\r
+\r
+#ifndef false\r
+#define false 0\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros for hardware access, both direct and via the bit-band region.\r
+//\r
+//*****************************************************************************\r
+#define HWREG(x)                                                              \\r
+        (*((volatile unsigned long *)(x)))\r
+#define HWREGH(x)                                                             \\r
+        (*((volatile unsigned short *)(x)))\r
+#define HWREGB(x)                                                             \\r
+        (*((volatile unsigned char *)(x)))\r
+#define HWREGBITW(x, b)                                                       \\r
+        HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 |                \\r
+              (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+#define HWREGBITH(x, b)                                                       \\r
+        HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 |               \\r
+               (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+#define HWREGBITB(x, b)                                                       \\r
+        HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 |               \\r
+               (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+\r
+#endif // __HW_TYPES_H__\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_uart.h b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_uart.h

new file mode 100644 (file)

index 0000000..99bdc3c
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_uart.h
@@ -0,0 +1,239 @@
+//*****************************************************************************\r
+//\r
+// hw_uart.h - Macros and defines used when accessing the UART hardware\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_UART_H__\r
+#define __HW_UART_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// UART Register Offsets.\r
+//\r
+//*****************************************************************************\r
+#define UART_O_DR               0x00000000  // Data Register\r
+#define UART_O_RSR              0x00000004  // Receive Status Register (read)\r
+#define UART_O_ECR              0x00000004  // Error Clear Register (write)\r
+#define UART_O_FR               0x00000018  // Flag Register (read only)\r
+#define UART_O_IBRD             0x00000024  // Integer Baud Rate Divisor Reg\r
+#define UART_O_FBRD             0x00000028  // Fractional Baud Rate Divisor Reg\r
+#define UART_O_LCR_H            0x0000002C  // Line Control Register, HIGH byte\r
+#define UART_O_CTL              0x00000030  // Control Register\r
+#define UART_O_IFLS             0x00000034  // Interrupt FIFO Level Select Reg\r
+#define UART_O_IM               0x00000038  // Interrupt Mask Set/Clear Reg\r
+#define UART_O_RIS              0x0000003C  // Raw Interrupt Status Register\r
+#define UART_O_MIS              0x00000040  // Masked Interrupt Status Register\r
+#define UART_O_ICR              0x00000044  // Interrupt Clear Register\r
+#define UART_O_PeriphID4        0x00000FD0  //\r
+#define UART_O_PeriphID5        0x00000FD4  //\r
+#define UART_O_PeriphID6        0x00000FD8  //\r
+#define UART_O_PeriphID7        0x00000FDC  //\r
+#define UART_O_PeriphID0        0x00000FE0  //\r
+#define UART_O_PeriphID1        0x00000FE4  //\r
+#define UART_O_PeriphID2        0x00000FE8  //\r
+#define UART_O_PeriphID3        0x00000FEC  //\r
+#define UART_O_PCellID0         0x00000FF0  //\r
+#define UART_O_PCellID1         0x00000FF4  //\r
+#define UART_O_PCellID2         0x00000FF8  //\r
+#define UART_O_PCellID3         0x00000FFC  //\r
+\r
+//*****************************************************************************\r
+//\r
+// Data Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_DR_OE              0x00000800  // Overrun Error\r
+#define UART_DR_BE              0x00000400  // Break Error\r
+#define UART_DR_PE              0x00000200  // Parity Error\r
+#define UART_DR_FE              0x00000100  // Framing Error\r
+#define UART_DR_DATA_MASK       0x000000FF  // UART data\r
+\r
+//*****************************************************************************\r
+//\r
+// Receive Status Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_RSR_OE             0x00000008  // Overrun Error\r
+#define UART_RSR_BE             0x00000004  // Break Error\r
+#define UART_RSR_PE             0x00000002  // Parity Error\r
+#define UART_RSR_FE             0x00000001  // Framing Error\r
+\r
+//*****************************************************************************\r
+//\r
+// Flag Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_FR_TXFE            0x00000080  // TX FIFO Empty\r
+#define UART_FR_RXFF            0x00000040  // RX FIFO Full\r
+#define UART_FR_TXFF            0x00000020  // TX FIFO Full\r
+#define UART_FR_RXFE            0x00000010  // RX FIFO Empty\r
+#define UART_FR_BUSY            0x00000008  // UART Busy\r
+\r
+//*****************************************************************************\r
+//\r
+// Integer baud-rate divisor\r
+//\r
+//*****************************************************************************\r
+#define UART_IBRD_DIVINT_MASK   0x0000FFFF  // Integer baud-rate divisor\r
+\r
+//*****************************************************************************\r
+//\r
+// Fractional baud-rate divisor\r
+//\r
+//*****************************************************************************\r
+#define UART_FBRD_DIVFRAC_MASK  0x0000003F  // Fractional baud-rate divisor\r
+\r
+//*****************************************************************************\r
+//\r
+// Line Control Register High bits\r
+//\r
+//*****************************************************************************\r
+#define UART_LCR_H_SPS          0x00000080  // Stick Parity Select\r
+#define UART_LCR_H_WLEN         0x00000060  // Word length\r
+#define UART_LCR_H_WLEN_8       0x00000060  // 8 bit data\r
+#define UART_LCR_H_WLEN_7       0x00000040  // 7 bit data\r
+#define UART_LCR_H_WLEN_6       0x00000020  // 6 bit data\r
+#define UART_LCR_H_WLEN_5       0x00000000  // 5 bit data\r
+#define UART_LCR_H_FEN          0x00000010  // Enable FIFO\r
+#define UART_LCR_H_STP2         0x00000008  // Two Stop Bits Select\r
+#define UART_LCR_H_EPS          0x00000004  // Even Parity Select\r
+#define UART_LCR_H_PEN          0x00000002  // Parity Enable\r
+#define UART_LCR_H_BRK          0x00000001  // Send Break\r
+\r
+//*****************************************************************************\r
+//\r
+// Control Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_CTL_RXE            0x00000200  // Receive Enable\r
+#define UART_CTL_TXE            0x00000100  // Transmit Enable\r
+#define UART_CTL_LBE            0x00000080  // Loopback Enable\r
+#define UART_CTL_UARTEN         0x00000001  // UART Enable\r
+\r
+//*****************************************************************************\r
+//\r
+// Interrupt FIFO Level Select Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_IFLS_RX1_8         0x00000000  // 1/8 Full\r
+#define UART_IFLS_RX2_8         0x00000010  // 1/4 Full\r
+#define UART_IFLS_RX4_8         0x00000020  // 1/2 Full\r
+#define UART_IFLS_RX6_8         0x00000030  // 3/4 Full\r
+#define UART_IFLS_RX7_8         0x00000040  // 7/8 Full\r
+#define UART_IFLS_TX1_8         0x00000000  // 1/8 Full\r
+#define UART_IFLS_TX2_8         0x00000001  // 1/4 Full\r
+#define UART_IFLS_TX4_8         0x00000002  // 1/2 Full\r
+#define UART_IFLS_TX6_8         0x00000003  // 3/4 Full\r
+#define UART_IFLS_TX7_8         0x00000004  // 7/8 Full\r
+\r
+//*****************************************************************************\r
+//\r
+// Interrupt Mask Set/Clear Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_IM_OEIM            0x00000400  // Overrun Error Interrupt Mask\r
+#define UART_IM_BEIM            0x00000200  // Break Error Interrupt Mask\r
+#define UART_IM_PEIM            0x00000100  // Parity Error Interrupt Mask\r
+#define UART_IM_FEIM            0x00000080  // Framing Error Interrupt Mask\r
+#define UART_IM_RTIM            0x00000040  // Receive Timeout Interrupt Mask\r
+#define UART_IM_TXIM            0x00000020  // Transmit Interrupt Mask\r
+#define UART_IM_RXIM            0x00000010  // Receive Interrupt Mask\r
+\r
+//*****************************************************************************\r
+//\r
+// Raw Interrupt Status Register\r
+//\r
+//*****************************************************************************\r
+#define UART_RIS_OERIS          0x00000400  // Overrun Error Interrupt Status\r
+#define UART_RIS_BERIS          0x00000200  // Break Error Interrupt Status\r
+#define UART_RIS_PERIS          0x00000100  // Parity Error Interrupt Status\r
+#define UART_RIS_FERIS          0x00000080  // Framing Error Interrupt Status\r
+#define UART_RIS_RTRIS          0x00000040  // Receive Timeout Interrupt Status\r
+#define UART_RIS_TXRIS          0x00000020  // Transmit Interrupt Status\r
+#define UART_RIS_RXRIS          0x00000010  // Receive Interrupt Status\r
+\r
+//*****************************************************************************\r
+//\r
+// Masked Interrupt Status Register\r
+//\r
+//*****************************************************************************\r
+#define UART_MIS_OEMIS          0x00000400  // Overrun Error Interrupt Status\r
+#define UART_MIS_BEMIS          0x00000200  // Break Error Interrupt Status\r
+#define UART_MIS_PEMIS          0x00000100  // Parity Error Interrupt Status\r
+#define UART_MIS_FEMIS          0x00000080  // Framing Error Interrupt Status\r
+#define UART_MIS_RTMIS          0x00000040  // Receive Timeout Interrupt Status\r
+#define UART_MIS_TXMIS          0x00000020  // Transmit Interrupt Status\r
+#define UART_MIS_RXMIS          0x00000010  // Receive Interrupt Status\r
+\r
+//*****************************************************************************\r
+//\r
+// Interrupt Clear Register bits\r
+//\r
+//*****************************************************************************\r
+#define UART_ICR_OEIC           0x00000400  // Overrun Error Interrupt Clear\r
+#define UART_ICR_BEIC           0x00000200  // Break Error Interrupt Clear\r
+#define UART_ICR_PEIC           0x00000100  // Parity Error Interrupt Clear\r
+#define UART_ICR_FEIC           0x00000080  // Framing Error Interrupt Clear\r
+#define UART_ICR_RTIC           0x00000040  // Receive Timeout Interrupt Clear\r
+#define UART_ICR_TXIC           0x00000020  // Transmit Interrupt Clear\r
+#define UART_ICR_RXIC           0x00000010  // Receive Interrupt Clear\r
+\r
+#define UART_RSR_ANY            (UART_RSR_OE |                                \\r
+                                 UART_RSR_BE |                                \\r
+                                 UART_RSR_PE |                                \\r
+                                 UART_RSR_FE)\r
+\r
+//*****************************************************************************\r
+//\r
+// Reset Values for UART Registers.\r
+//\r
+//*****************************************************************************\r
+#define UART_RV_DR              0x00000000\r
+#define UART_RV_RSR             0x00000000\r
+#define UART_RV_ECR             0x00000000\r
+#define UART_RV_FR              0x00000090\r
+#define UART_RV_IBRD            0x00000000\r
+#define UART_RV_FBRD            0x00000000\r
+#define UART_RV_LCR_H           0x00000000\r
+#define UART_RV_CTL             0x00000300\r
+#define UART_RV_IFLS            0x00000012\r
+#define UART_RV_IM              0x00000000\r
+#define UART_RV_RIS             0x00000000\r
+#define UART_RV_MIS             0x00000000\r
+#define UART_RV_ICR             0x00000000\r
+#define UART_RV_PeriphID4       0x00000000\r
+#define UART_RV_PeriphID5       0x00000000\r
+#define UART_RV_PeriphID6       0x00000000\r
+#define UART_RV_PeriphID7       0x00000000\r
+#define UART_RV_PeriphID0       0x00000011\r
+#define UART_RV_PeriphID1       0x00000000\r
+#define UART_RV_PeriphID2       0x00000018\r
+#define UART_RV_PeriphID3       0x00000001\r
+#define UART_RV_PCellID0        0x0000000D\r
+#define UART_RV_PCellID1        0x000000F0\r
+#define UART_RV_PCellID2        0x00000005\r
+#define UART_RV_PCellID3        0x000000B1\r
+\r
+#endif // __HW_UART_H__\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/hw_watchdog.h b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_watchdog.h

new file mode 100644 (file)

index 0000000..e9d3f0b
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/hw_watchdog.h
@@ -0,0 +1,116 @@
+//*****************************************************************************\r
+//\r
+// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __HW_WATCHDOG_H__\r
+#define __HW_WATCHDOG_H__\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the offsets of the Watchdog Timer registers.\r
+//\r
+//*****************************************************************************\r
+#define WDT_O_LOAD              0x00000000  // Load register\r
+#define WDT_O_VALUE             0x00000004  // Current value register\r
+#define WDT_O_CTL               0x00000008  // Control register\r
+#define WDT_O_ICR               0x0000000C  // Interrupt clear register\r
+#define WDT_O_RIS               0x00000010  // Raw interrupt status register\r
+#define WDT_O_MIS               0x00000014  // Masked interrupt status register\r
+#define WDT_O_TEST              0x00000418  // Test register\r
+#define WDT_O_LOCK              0x00000C00  // Lock register\r
+#define WDT_O_PeriphID4         0x00000FD0  //\r
+#define WDT_O_PeriphID5         0x00000FD4  //\r
+#define WDT_O_PeriphID6         0x00000FD8  //\r
+#define WDT_O_PeriphID7         0x00000FDC  //\r
+#define WDT_O_PeriphID0         0x00000FE0  //\r
+#define WDT_O_PeriphID1         0x00000FE4  //\r
+#define WDT_O_PeriphID2         0x00000FE8  //\r
+#define WDT_O_PeriphID3         0x00000FEC  //\r
+#define WDT_O_PCellID0          0x00000FF0  //\r
+#define WDT_O_PCellID1          0x00000FF4  //\r
+#define WDT_O_PCellID2          0x00000FF8  //\r
+#define WDT_O_PCellID3          0x00000FFC  //\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_CTL register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_CTL_RESEN           0x00000002  // Enable reset output\r
+#define WDT_CTL_INTEN           0x00000001  // Enable the WDT counter and int\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_ISR, WDT_RIS, and WDT_MIS\r
+// registers.\r
+//\r
+//*****************************************************************************\r
+#define WDT_INT_TIMEOUT         0x00000001  // Watchdog timer expired\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_TEST register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_TEST_STALL          0x00000100  // Watchdog stall enable\r
+#ifndef DEPRECATED\r
+#define WDT_TEST_STALL_EN       0x00000100  // Watchdog stall enable\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the bit fields in the WDT_LOCK register.\r
+//\r
+//*****************************************************************************\r
+#define WDT_LOCK_LOCKED         0x00000001  // Watchdog timer is locked\r
+#define WDT_LOCK_UNLOCKED       0x00000000  // Watchdog timer is unlocked\r
+#define WDT_LOCK_UNLOCK         0x1ACCE551  // Unlocks the watchdog timer\r
+\r
+//*****************************************************************************\r
+//\r
+// The following define the reset values for the WDT registers.\r
+//\r
+//*****************************************************************************\r
+#define WDT_RV_LOAD             0xFFFFFFFF  // Load register\r
+#define WDT_RV_VALUE            0xFFFFFFFF  // Current value register\r
+#define WDT_RV_CTL              0x00000000  // Control register\r
+#define WDT_RV_RIS              0x00000000  // Raw interrupt status register\r
+#define WDT_RV_MIS              0x00000000  // Masked interrupt status register\r
+#define WDT_RV_LOCK             0x00000000  // Lock register\r
+#define WDT_RV_PeriphID4        0x00000000  //\r
+#define WDT_RV_PeriphID5        0x00000000  //\r
+#define WDT_RV_PeriphID6        0x00000000  //\r
+#define WDT_RV_PeriphID7        0x00000000  //\r
+#define WDT_RV_PeriphID0        0x00000005  //\r
+#define WDT_RV_PeriphID1        0x00000018  //\r
+#define WDT_RV_PeriphID2        0x00000018  //\r
+#define WDT_RV_PeriphID3        0x00000001  //\r
+#define WDT_RV_PCellID0         0x0000000D  //\r
+#define WDT_RV_PCellID1         0x000000F0  //\r
+#define WDT_RV_PCellID2         0x00000005  //\r
+#define WDT_RV_PCellID3         0x000000B1  //\r
+\r
+#endif // __HW_WATCHDOG_H__\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/i2c.h b/Demo/CORTEX_LM3S316_IAR/hw_include/i2c.h

new file mode 100644 (file)

index 0000000..26bb1dd
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/i2c.h
@@ -0,0 +1,137 @@
+//*****************************************************************************\r
+//\r
+// i2c.h - Prototypes for the I2C Driver.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __I2C_H__\r
+#define __I2C_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines for the API.\r
+//\r
+//*****************************************************************************\r
+//*****************************************************************************\r
+//\r
+// Interrupt defines.\r
+//\r
+//*****************************************************************************\r
+#define I2C_INT_MASTER          0x00000001\r
+#define I2C_INT_SLAVE           0x00000002\r
+\r
+//*****************************************************************************\r
+//\r
+// I2C Master commands.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_CMD_SINGLE_SEND                                            \\r
+            (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_SINGLE_RECEIVE                                         \\r
+            (I2C_MASTER_CS_STOP | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_START                                       \\r
+            (I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_CONT                                        \\r
+            (I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_FINISH                                      \\r
+            (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP                                  \\r
+            (I2C_MASTER_CS_STOP)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_START                                    \\r
+            (I2C_MASTER_CS_ACK | I2C_MASTER_CS_START | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_CONT                                     \\r
+            (I2C_MASTER_CS_ACK | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH                                   \\r
+            (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)\r
+#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP                               \\r
+            (I2C_MASTER_CS_STOP | I2C_MASTER_CS_RUN)\r
+\r
+//*****************************************************************************\r
+//\r
+// I2C Master error status.\r
+//\r
+//*****************************************************************************\r
+#define I2C_MASTER_ERR_NONE     0\r
+#define I2C_MASTER_ERR_ADDR_ACK 0x00000004\r
+#define I2C_MASTER_ERR_DATA_ACK 0x00000008\r
+#define I2C_MASTER_ERR_ARB_LOST 0x00000010\r
+\r
+//*****************************************************************************\r
+//\r
+// I2C Slave action requests\r
+//\r
+//*****************************************************************************\r
+#define I2C_SLAVE_ACT_NONE      0\r
+#define I2C_SLAVE_ACT_RREQ      0x00000001  // Master has sent data\r
+#define I2C_SLAVE_ACT_TREQ      0x00000002  // Master has requested data\r
+\r
+//*****************************************************************************\r
+// Miscellaneous I2C driver definitions.\r
+//*****************************************************************************\r
+#define I2C_MASTER_MAX_RETRIES 1000        // Number of retries\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void));\r
+extern void I2CIntUnregister(unsigned long ulBase);\r
+extern tBoolean I2CMasterBusBusy(unsigned long ulBase);\r
+extern tBoolean I2CMasterBusy(unsigned long ulBase);\r
+extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd);\r
+extern unsigned long I2CMasterDataGet(unsigned long ulBase);\r
+extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData);\r
+extern void I2CMasterDisable(unsigned long ulBase);\r
+extern void I2CMasterEnable(unsigned long ulBase);\r
+extern unsigned long I2CMasterErr(unsigned long ulBase);\r
+extern void I2CMasterInit(unsigned long ulBase, tBoolean bFast);\r
+extern void I2CMasterIntClear(unsigned long ulBase);\r
+extern void I2CMasterIntDisable(unsigned long ulBase);\r
+extern void I2CMasterIntEnable(unsigned long ulBase);\r
+extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void I2CMasterSlaveAddrSet(unsigned long ulBase,\r
+                                  unsigned char ucSlaveAddr,\r
+                                  tBoolean bReceive);\r
+extern unsigned long I2CSlaveDataGet(unsigned long ulBase);\r
+extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData);\r
+extern void I2CSlaveDisable(unsigned long ulBase);\r
+extern void I2CSlaveEnable(unsigned long ulBase);\r
+extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr);\r
+extern void I2CSlaveIntClear(unsigned long ulBase);\r
+extern void I2CSlaveIntDisable(unsigned long ulBase);\r
+extern void I2CSlaveIntEnable(unsigned long ulBase);\r
+extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern unsigned long I2CSlaveStatus(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __I2C_H__\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/interrupt.h b/Demo/CORTEX_LM3S316_IAR/hw_include/interrupt.h

new file mode 100644 (file)

index 0000000..98f0f86
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/interrupt.h
@@ -0,0 +1,57 @@
+//*****************************************************************************\r
+//\r
+// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __INTERRUPT_H__\r
+#define __INTERRUPT_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void IntMasterEnable(void);\r
+extern void IntMasterDisable(void);\r
+extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void));\r
+extern void IntUnregister(unsigned long ulInterrupt);\r
+extern void IntPriorityGroupingSet(unsigned long ulBits);\r
+extern unsigned long IntPriorityGroupingGet(void);\r
+extern void IntPrioritySet(unsigned long ulInterrupt,\r
+                           unsigned char ucPriority);\r
+extern long IntPriorityGet(unsigned long ulInterrupt);\r
+extern void IntEnable(unsigned long ulInterrupt);\r
+extern void IntDisable(unsigned long ulInterrupt);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __INTERRUPT_H__\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/libdriver.a b/Demo/CORTEX_LM3S316_IAR/hw_include/libdriver.a

new file mode 100644 (file)

index 0000000..c465e8f

Binary files /dev/null and b/Demo/CORTEX_LM3S316_IAR/hw_include/libdriver.a differ
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/lnkarm.xcl b/Demo/CORTEX_LM3S316_IAR/hw_include/lnkarm.xcl

new file mode 100644 (file)

index 0000000..0dfdc1d
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/lnkarm.xcl
@@ -0,0 +1,196 @@
+//*************************************************************************\r
+// XLINK command file template for EWARM/ICCARM\r
+//\r
+// Usage:  xlink  -f lnkarm  <your_object_file(s)>\r
+//                -s <program start label>  <C/C++ runtime library>\r
+//\r
+// $Revision: 1.32 $\r
+//*************************************************************************\r
+\r
+//*************************************************************************\r
+// In this file it is assumed that the system has the following\r
+// memory layout:\r
+//\r
+//   Exception vectors [0x000000--0x00001F]  RAM or ROM\r
+//   ROMSTART--ROMEND  [0x008000--0x0FFFFF]  ROM (or other non-volatile memory)\r
+//   RAMSTART--RAMEND  [0x100000--0x7FFFFF]  RAM (or other read/write memory)\r
+//\r
+// -------------\r
+// Code segments - may be placed anywhere in memory.\r
+// -------------\r
+//\r
+//   INTVEC     -- Exception vector table.\r
+//   SWITAB     -- Software interrupt vector table.\r
+//   ICODE      -- Startup (cstartup) and exception code.\r
+//   DIFUNCT    -- Dynamic initialization vectors used by C++.\r
+//   CODE       -- Compiler generated code.\r
+//   CODE_I     -- Compiler generated code declared __ramfunc (executes in RAM)\r
+//   CODE_ID    -- Initializer for CODE_I (ROM).\r
+//\r
+// -------------\r
+// Data segments - may be placed anywhere in memory.\r
+// -------------\r
+//\r
+//   CSTACK     -- The stack used by C/C++ programs (system and user mode).\r
+//   IRQ_STACK  -- The stack used by IRQ service routines.\r
+//   SVC_STACK  -- The stack used in supervisor mode\r
+//                 (Define other exception stacks as needed for\r
+//                 FIQ, ABT, UND).\r
+//   HEAP       -- The heap used by malloc and free in C and new and\r
+//                 delete in C++.\r
+//   INITTAB    -- Table containing addresses and sizes of segments that\r
+//                 need to be initialized at startup (by cstartup).\r
+//   CHECKSUM   -- The linker places checksum byte(s) in this segment,\r
+//                 when the -J linker command line option is used.\r
+//   DATA_y     -- Data objects.\r
+//\r
+// Where _y can be one of:\r
+//\r
+//   _AN        -- Holds uninitialized located objects, i.e. objects with\r
+//                 an absolute location given by the @ operator or the\r
+//                 #pragma location directive. Since these segments\r
+//                 contain objects which already have a fixed address,\r
+//                 they should not be mentioned in this linker command\r
+//                 file.\r
+//   _C         -- Constants (ROM).\r
+//   _I         -- Initialized data (RAM).\r
+//   _ID        -- The original content of _I (copied to _I by cstartup) (ROM).\r
+//   _N         -- Uninitialized data (RAM).\r
+//   _Z         -- Zero initialized data (RAM).\r
+//\r
+// Note:  Be sure to use end values for the defined address ranges.\r
+//        Otherwise, the linker may allocate space outside the\r
+//        intended memory range.\r
+//*************************************************************************\r
+\r
+\r
+//************************************************\r
+// Inform the linker about the CPU family used.\r
+//************************************************\r
+\r
+-carm\r
+\r
+//*************************************************************************\r
+// Segment placement - General information\r
+//\r
+// All numbers in the segment placement command lines below are interpreted\r
+// as hexadecimal unless they are immediately preceded by a '.', which\r
+// denotes decimal notation. \r
+//\r
+// When specifying the segment placement using the -P instead of the -Z\r
+// option, the linker is free to split each segment into its segment parts\r
+// and randomly place these parts within the given ranges in order to\r
+// achieve a more efficient memory usage. One disadvantage, however, is\r
+// that it is not possible to find the start or end address (using\r
+// the assembler operators .sfb./.sfe.) of a segment which has been split\r
+// and reformed. \r
+//\r
+// When generating an output file which is to be used for programming\r
+// external ROM/Flash devices, the -M linker option is very useful \r
+// (see xlink.pdf for details).\r
+//*************************************************************************\r
+\r
+\r
+//*************************************************************************\r
+// Read-only segments mapped to ROM.\r
+//*************************************************************************\r
+\r
+-DROMSTART=08000\r
+-DROMEND=FFFFF\r
+\r
+//************************************************\r
+// Address range for reset and exception\r
+// vectors (INTVEC).\r
+// The vector area is 32 bytes, \r
+// an additional 32 bytes is allocated for the\r
+// constant table used by ldr PC in cstartup.s79.\r
+//************************************************\r
+\r
+-Z(CODE)INTVEC=00-3F\r
+\r
+//************************************************\r
+// Startup code and exception routines (ICODE).\r
+//************************************************\r
+\r
+-Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND\r
+-Z(CODE)SWITAB=ROMSTART-ROMEND\r
+\r
+//************************************************\r
+// Code segments may be placed anywhere.\r
+//************************************************\r
+\r
+-Z(CODE)CODE=ROMSTART-ROMEND\r
+\r
+//************************************************\r
+// Original ROM location for __ramfunc code copied\r
+// to and executed from RAM.\r
+//************************************************\r
+\r
+-Z(CONST)CODE_ID=ROMSTART-ROMEND\r
+\r
+//************************************************\r
+// Various constants and initializers.\r
+//************************************************\r
+\r
+-Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND\r
+-Z(CONST)CHECKSUM=ROMSTART-ROMEND\r
+\r
+//*************************************************************************\r
+// Read/write segments mapped to RAM.\r
+//*************************************************************************\r
+\r
+-DRAMSTART=100000\r
+-DRAMEND=7FFFFF\r
+\r
+//************************************************\r
+// Data segments.\r
+//************************************************\r
+\r
+-Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND\r
+\r
+//************************************************\r
+// __ramfunc code copied to and executed from RAM.\r
+//************************************************\r
+\r
+-Z(DATA)CODE_I=RAMSTART-RAMEND\r
+\r
+//************************************************\r
+// ICCARM produces code for __ramfunc functions in\r
+// CODE_I segments. The -Q XLINK command line\r
+// option redirects XLINK to emit the code in the\r
+// CODE_ID segment instead, but to keep symbol and\r
+// debug information associated with the CODE_I\r
+// segment, where the code will execute.\r
+//************************************************\r
+\r
+-QCODE_I=CODE_ID\r
+\r
+//*************************************************************************\r
+// Stack and heap segments.\r
+//*************************************************************************\r
+\r
+-D_CSTACK_SIZE=2000\r
+// -D_SVC_STACK_SIZE=10\r
+-D_IRQ_STACK_SIZE=100\r
+-D_HEAP_SIZE=8000\r
+\r
+-Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND\r
+// -Z(DATA)SVC_STACK+_SVC_STACK_SIZE=RAMSTART-RAMEND\r
+-Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE,HEAP+_HEAP_SIZE=RAMSTART-RAMEND\r
+\r
+//*************************************************************************\r
+// ELF/DWARF support.\r
+//\r
+// Uncomment the line "-Felf" below to generate ELF/DWARF output.\r
+// Available format specifiers are:\r
+//\r
+//   "-yn": Suppress DWARF debug output\r
+//   "-yp": Multiple ELF program sections\r
+//   "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag)\r
+//\r
+// "-Felf" and the format specifiers can also be supplied directly as\r
+// command line options, or selected from the Xlink Output tab in the\r
+// IAR Embedded Workbench.\r
+//*************************************************************************\r
+\r
+// -Felf\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/lnkarm_standalone.xcl b/Demo/CORTEX_LM3S316_IAR/hw_include/lnkarm_standalone.xcl

new file mode 100644 (file)

index 0000000..f2cc363
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/lnkarm_standalone.xcl
@@ -0,0 +1,192 @@
+//*************************************************************************\r
+// XLINK command file template for EWARM/ICCARM\r
+//\r
+// Usage:  xlink  -f lnkarm  <your_object_file(s)>\r
+//                -s <program start label>  <C/C++ runtime library>\r
+//\r
+// $Revision: 1.1 $\r
+//*************************************************************************\r
+\r
+//*************************************************************************\r
+// In this file it is assumed that the system has the following\r
+// memory layout:\r
+//\r
+//   ROMSTART--ROMEND  [00000000--00001FFF]  Flash\r
+//   RAMSTART--RAMEND  [20000000--200007FF]  RAM\r
+//\r
+// -------------\r
+// Code segments - may be placed anywhere in memory (except INTVEC).\r
+// -------------\r
+//\r
+//   INTVEC     -- Exception vector table.\r
+//   SWITAB     -- Software interrupt vector table.\r
+//   ICODE      -- Startup (cstartup) and exception code.\r
+//   DIFUNCT    -- Dynamic initialization vectors used by C++.\r
+//   CODE       -- Compiler generated code.\r
+//   CODE_I     -- Compiler generated code declared __ramfunc (executes in RAM)\r
+//   CODE_ID    -- Initializer for CODE_I (ROM).\r
+//\r
+// -------------\r
+// Data segments - may be placed anywhere in memory.\r
+// -------------\r
+//\r
+//   CSTACK     -- The stack used by C/C++ programs (system and user mode).\r
+//   HEAP       -- The heap used by malloc and free in C and new and\r
+//                 delete in C++.\r
+//   INITTAB    -- Table containing addresses and sizes of segments that\r
+//                 need to be initialized at startup (by cstartup).\r
+//   CHECKSUM   -- The linker places checksum byte(s) in this segment,\r
+//                 when the -J linker command line option is used.\r
+//   DATA_y     -- Data objects.\r
+//\r
+// Where _y can be one of:\r
+//\r
+//   _AN        -- Holds uninitialized located objects, i.e. objects with\r
+//                 an absolute location given by the @ operator or the\r
+//                 #pragma location directive. Since these segments\r
+//                 contain objects which already have a fixed address,\r
+//                 they should not be mentioned in this linker command\r
+//                 file.\r
+//   _C         -- Constants (ROM).\r
+//   _I         -- Initialized data (RAM).\r
+//   _ID        -- The original content of _I (copied to _I by cstartup) (ROM).\r
+//   _N         -- Uninitialized data (RAM).\r
+//   _Z         -- Zero initialized data (RAM).\r
+//\r
+// Note:  Be sure to use end values for the defined address ranges.\r
+//        Otherwise, the linker may allocate space outside the\r
+//        intended memory range.\r
+//*************************************************************************\r
+\r
+\r
+//************************************************\r
+// Inform the linker about the CPU family used.\r
+//************************************************\r
+\r
+-carm\r
+\r
+//*************************************************************************\r
+// Segment placement - General information\r
+//\r
+// All numbers in the segment placement command lines below are interpreted\r
+// as hexadecimal unless they are immediately preceded by a '.', which\r
+// denotes decimal notation. \r
+//\r
+// When specifying the segment placement using the -P instead of the -Z\r
+// option, the linker is free to split each segment into its segment parts\r
+// and randomly place these parts within the given ranges in order to\r
+// achieve a more efficient memory usage. One disadvantage, however, is\r
+// that it is not possible to find the start or end address (using\r
+// the assembler operators .sfb./.sfe.) of a segment which has been split\r
+// and reformed. \r
+//\r
+// When generating an output file which is to be used for programming\r
+// external ROM/Flash devices, the -M linker option is very useful \r
+// (see xlink.pdf for details).\r
+//*************************************************************************\r
+\r
+\r
+//*************************************************************************\r
+// Read-only segments mapped to ROM.\r
+//*************************************************************************\r
+\r
+-DROMSTART=00000000\r
+-DROMEND=00001FFF\r
+\r
+//************************************************\r
+// Address range for reset and exception\r
+// vectors (INTVEC).\r
+// The vector area is at least 8 bytes,\r
+// and is normally located at address 0.\r
+// It may be changed to a RAM address when\r
+// debugging in RAM (aligned to 2^7).\r
+//************************************************\r
+\r
+-Z(CODE)INTVEC=ROMSTART-ROMEND\r
+\r
+//************************************************\r
+// Startup code and exception routines (ICODE).\r
+//************************************************\r
+\r
+-Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND\r
+-Z(CODE)SWITAB=ROMSTART-ROMEND\r
+\r
+//************************************************\r
+// Code segments may be placed anywhere.\r
+//************************************************\r
+\r
+-Z(CODE)CODE=ROMSTART-ROMEND\r
+\r
+//************************************************\r
+// Original ROM location for __ramfunc code copied\r
+// to and executed from RAM.\r
+//************************************************\r
+\r
+-Z(CONST)CODE_ID=ROMSTART-ROMEND\r
+\r
+//************************************************\r
+// Various constants and initializers.\r
+//************************************************\r
+\r
+-Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND\r
+-Z(CONST)CHECKSUM=ROMSTART-ROMEND\r
+\r
+//*************************************************************************\r
+// Read/write segments mapped to RAM.\r
+//*************************************************************************\r
+\r
+-DRAMSTART=20000000\r
+-DRAMEND=200007FF\r
+\r
+//************************************************\r
+// Data segments.\r
+//************************************************\r
+\r
+-Z(DATA)VTABLE=RAMSTART-RAMEND\r
+\r
+-Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND\r
+\r
+//************************************************\r
+// __ramfunc code copied to and executed from RAM.\r
+//************************************************\r
+\r
+-Z(DATA)CODE_I=RAMSTART-RAMEND\r
+\r
+//************************************************\r
+// ICCARM produces code for __ramfunc functions in\r
+// CODE_I segments. The -Q XLINK command line\r
+// option redirects XLINK to emit the code in the\r
+// CODE_ID segment instead, but to keep symbol and\r
+// debug information associated with the CODE_I\r
+// segment, where the code will execute.\r
+//************************************************\r
+\r
+-QCODE_I=CODE_ID\r
+\r
+//*************************************************************************\r
+// Stack and heap segments.\r
+//*************************************************************************\r
+\r
+-D_CSTACK_SIZE=180\r
+-D_IRQ_STACK_SIZE=100\r
+-D_HEAP_SIZE=100\r
+\r
+-Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND\r
+-Z(DATA)HEAP+_HEAP_SIZE=RAMSTART-RAMEND\r
+\r
+//*************************************************************************\r
+// ELF/DWARF support.\r
+//\r
+// Uncomment the line "-Felf" below to generate ELF/DWARF output.\r
+// Available format specifiers are:\r
+//\r
+//   "-yn": Suppress DWARF debug output\r
+//   "-yp": Multiple ELF program sections\r
+//   "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag)\r
+//\r
+// "-Felf" and the format specifiers can also be supplied directly as\r
+// command line options, or selected from the Xlink Output tab in the\r
+// IAR Embedded Workbench.\r
+//*************************************************************************\r
+\r
+// -Felf\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/pdc.c b/Demo/CORTEX_LM3S316_IAR/hw_include/pdc.c

new file mode 100644 (file)

index 0000000..65271d5
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/pdc.c
@@ -0,0 +1,723 @@
+//*****************************************************************************\r
+//\r
+// pdc.c - Driver for the Peripheral Device Controller (PDC) on the Stellaris\r
+//         development board.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+//! \addtogroup utilities_api\r
+//! @{\r
+//\r
+//*****************************************************************************\r
+\r
+#include "hw_memmap.h"\r
+#include "hw_types.h"\r
+#include "debug.h"\r
+#include "gpio.h"\r
+#include "ssi.h"\r
+#include "sysctl.h"\r
+#include "pdc.h"\r
+\r
+//*****************************************************************************\r
+//\r
+//! Initializes the connection to the PDC.\r
+//!\r
+//! This function will enable clocking to the SSI and GPIO A modules, configure\r
+//! the GPIO pins to be used for an SSI interface, and it will configure the\r
+//! SSI as a 1 Mbps master device, operating in MOTO mode.  It will also enable\r
+//! the SSI module, and will enable the chip select for the PDC on the\r
+//! Stellaris development board.\r
+//!\r
+//! This function is contained in <tt>utils/pdc.c</tt>, with\r
+//! <tt>utils/pdc.h</tt> containing the API definition for use by applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+PDCInit(void)\r
+{\r
+    //\r
+    // Enable the peripherals used to drive the PDC.\r
+    //\r
+    SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI);\r
+    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);\r
+\r
+    //\r
+    // Configure the appropriate pins to be SSI instead of GPIO.\r
+    //\r
+    GPIODirModeSet(GPIO_PORTA_BASE, SSI_CLK | SSI_TX | SSI_RX,\r
+                   GPIO_DIR_MODE_HW);\r
+    GPIODirModeSet(GPIO_PORTA_BASE, SSI_CS, GPIO_DIR_MODE_OUT);\r
+    GPIOPadConfigSet(GPIO_PORTA_BASE, SSI_CLK, GPIO_STRENGTH_4MA,\r
+                     GPIO_PIN_TYPE_STD_WPU);\r
+\r
+    //\r
+    // Configure the SSI port.\r
+    //\r
+    SSIConfig(SSI_BASE, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8);\r
+    SSIEnable(SSI_BASE);\r
+\r
+    //\r
+    // Reset the PDC SSI state machine.  The chip select needs to be held low\r
+    // for 100ns; the procedure call overhead more than accounts for this time.\r
+    //\r
+    GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, 0);\r
+    GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, PDC_CS);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Read a PDC register.\r
+//!\r
+//! \param ucAddr specifies the PDC register to read.\r
+//!\r
+//! This function will perform the SSI transfers required to read a register in\r
+//! the PDC on the Stellaris development board.\r
+//!\r
+//! This function is contained in <tt>utils/pdc.c</tt>, with\r
+//! <tt>utils/pdc.h</tt> containing the API definition for use by applications.\r
+//!\r
+//! \return Returns the value read from the PDC.\r
+//\r
+//*****************************************************************************\r
+unsigned char\r
+PDCRead(unsigned char ucAddr)\r
+{\r
+    unsigned long ulTemp;\r
+\r
+    //\r
+    // Send address and read command.\r
+    //\r
+    SSIDataPut(SSI_BASE, (ucAddr & 0x0F) | PDC_RD);\r
+\r
+    //\r
+    // Dummy write to force read.\r
+    //\r
+    SSIDataPut(SSI_BASE, 0x00);\r
+\r
+    //\r
+    // Flush data read during address write.\r
+    //\r
+    SSIDataGet(SSI_BASE, &ulTemp);\r
+\r
+    //\r
+    // If the LCD control register or RAM is being read, then an additional\r
+    // byte needs to be transferred.\r
+    //\r
+    if((ucAddr == PDC_LCD_CSR) || (ucAddr == PDC_LCD_RAM))\r
+    {\r
+        //\r
+        // Dummy write to force read.\r
+        //\r
+        SSIDataPut(SSI_BASE, 0x00);\r
+\r
+        //\r
+        // Flush read data.\r
+        //\r
+        SSIDataGet(SSI_BASE, &ulTemp);\r
+    }\r
+\r
+    //\r
+    // Read valid data.\r
+    //\r
+    SSIDataGet(SSI_BASE, &ulTemp);\r
+\r
+    //\r
+    // Return the data read.\r
+    //\r
+    return(ulTemp & 0xFF);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Write a PDC register.\r
+//!\r
+//! \param ucAddr specifies the PDC register to write.\r
+//! \param ucData specifies the data to write.\r
+//!\r
+//! This function will perform the SSI transfers required to write a register\r
+//! in the PDC on the Stellaris development board.\r
+//!\r
+//! This function is contained in <tt>utils/pdc.c</tt>, with\r
+//! <tt>utils/pdc.h</tt> containing the API definition for use by applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+PDCWrite(unsigned char ucAddr, unsigned char ucData)\r
+{\r
+    unsigned long ulTemp;\r
+\r
+    //\r
+    // Send address and write command.\r
+    //\r
+    SSIDataPut(SSI_BASE, (ucAddr & 0x0F) | PDC_WR);\r
+\r
+    //\r
+    // Write the data.\r
+    //\r
+    SSIDataPut(SSI_BASE, ucData);\r
+\r
+    //\r
+    // Flush data read during address write.\r
+    //\r
+    SSIDataGet(SSI_BASE, &ulTemp);\r
+\r
+    //\r
+    // Flush data read during data write.\r
+    //\r
+    SSIDataGet(SSI_BASE, &ulTemp);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Read the current value of the PDC DIP switches.\r
+//!\r
+//! This function will read the current value of the DIP switches attached to\r
+//! the PDC on the Stellaris development board.\r
+//!\r
+//! This function is contained in <tt>utils/pdc.c</tt>, with\r
+//! <tt>utils/pdc.h</tt> containing the API definition for use by applications.\r
+//!\r
+//! \return The current state of the DIP switches.\r
+//\r
+//*****************************************************************************\r
+unsigned char\r
+PDCDIPRead(void)\r
+{\r
+    return(PDCRead(PDC_DSW));\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Write to the PDC LEDs.\r
+//!\r
+//! \param ucLED value to write to the LEDs.\r
+//!\r
+//! This function set the state of the LEDs connected to the PDC on the\r
+//! Stellaris development board.\r
+//!\r
+//! This function is contained in <tt>utils/pdc.c</tt>, with\r
+//! <tt>utils/pdc.h</tt> containing the API definition for use by applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+PDCLEDWrite(unsigned char ucLED)\r
+{\r
+    PDCWrite(PDC_LED, ucLED);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Read the current status of the PDC LEDs.\r
+//!\r
+//! This function will read the state of the LEDs connected to the PDC on the\r
+//! Stellaris development board.\r
+//!\r
+//! This function is contained in <tt>utils/pdc.c</tt>, with\r
+//! <tt>utils/pdc.h</tt> containing the API definition for use by applications.\r
+//!\r
+//! \return The value currently displayed by the LEDs.\r
+//\r
+//*****************************************************************************\r
+unsigned char\r
+PDCLEDRead(void)\r
+{\r
+    return(PDCRead(PDC_LED));\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Initializes the LCD display.\r
+//!\r
+//! This function will set up the LCD display for writing. It will set the\r
+//! data bus to 8 bits, set the number of lines to 2, and the font size to\r
+//! 5x10. It will also turn the display off, clear the display, turn the\r
+//! display back on, and enable the backlight.\r
+//!\r
+//! This function is contained in <tt>utils/pdc.c</tt>, with\r
+//! <tt>utils/pdc.h</tt> containing the API definition for use by applications.\r
+//!\r
+//! \note The PDC must be initialized via the PDCInit() function before this\r
+//! function can be called.  Also, it may be necessary to adjust the contrast\r
+//! potentiometer in order to discern any output on the LCD display.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+PDCLCDInit(void)\r
+{\r
+    unsigned char pucCfg[] =\r
+    {\r
+        0x3C,   // Number of lines = 2 / font = 5x10\r
+        0x08,   // Display off\r
+        0x01,   // Display clear\r
+        0x06,   // Entry mode [cursor dir][shift]\r
+        0x0C,   // Display on [display on][curson on][blinking on]\r
+    };\r
+    unsigned long ulIdx;\r
+\r
+    //\r
+    // Set the data bus width to eight bits.\r
+    //\r
+    PDCWrite(PDC_LCD_CSR, 0x30);\r
+\r
+    //\r
+    // Wait for 4.1ms by reading the PDC version register enough times to\r
+    // guarantee that amount of time has passed.\r
+    //\r
+    for(ulIdx = 0; ulIdx < 257; ulIdx++)\r
+    {\r
+        PDCRead(PDC_VER);\r
+    }\r
+\r
+    //\r
+    // Set the data bus width to eight bits.\r
+    //\r
+    PDCWrite(PDC_LCD_CSR, 0x30);\r
+\r
+    //\r
+    // Wait for 100us by reading the PDC version register enough times to\r
+    // guarantee that amount of time has passed.  This works out to 112us plus\r
+    // overhead.\r
+    //\r
+    for(ulIdx = 0; ulIdx < 7; ulIdx++)\r
+    {\r
+        PDCRead(PDC_VER);\r
+    }\r
+\r
+    //\r
+    // Set the data bus width to eight bits.\r
+    //\r
+    PDCWrite(PDC_LCD_CSR, 0x30);\r
+\r
+    //\r
+    // Configure the LCD.\r
+    //\r
+    for(ulIdx = 0; ulIdx < (sizeof(pucCfg) / sizeof(pucCfg[0])); ulIdx++)\r
+    {\r
+        //\r
+        // Wait until the LCD has finished executing any previous command.\r
+        //\r
+        while((PDCRead(PDC_LCD_CSR) & LCD_B_BUSY))\r
+        {\r
+        }\r
+\r
+        //\r
+        // Write the next configuration byte.\r
+        //\r
+        PDCWrite(PDC_LCD_CSR, pucCfg[ulIdx]);\r
+    }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Turns on the backlight.\r
+//!\r
+//! This function turns on the backlight on the LCD.\r
+//!\r
+//! This function is contained in <tt>utils/pdc.c</tt>, with\r
+//! <tt>utils/pdc.h</tt> containing the API definition for use by applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+PDCLCDBacklightOn(void)\r
+{\r
+    PDCWrite(PDC_CSR, 0x01);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Turn off the backlight.\r
+//!\r
+//! This function turns off the backlight on the LCD.\r
+//!\r
+//! This function is contained in <tt>utils/pdc.c</tt>, with\r
+//! <tt>utils/pdc.h</tt> containing the API definition for use by applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+PDCLCDBacklightOff(void)\r
+{\r
+    PDCWrite(PDC_CSR, 0x00);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Clear the screen.\r
+//!\r
+//! This function clears the contents of the LCD screen.  The cursor will be\r
+//! returned to the upper left corner.\r
+//!\r
+//! This function is contained in <tt>utils/pdc.c</tt>, with\r
+//! <tt>utils/pdc.h</tt> containing the API definition for use by applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+PDCLCDClear(void)\r
+{\r
+    //\r
+    // Wait until the LCD has finished executing any previous command.\r
+    //\r
+    while((PDCRead(PDC_LCD_CSR) & LCD_B_BUSY))\r
+    {\r
+    }\r
+\r
+    //\r
+    // Write the clear display command.\r
+    //\r
+    PDCWrite(PDC_LCD_CSR, LCD_CLEAR);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Write a character pattern to the LCD.\r
+//!\r
+//! \param ucChar is the character index to create.  Valid values are zero\r
+//! through seven.\r
+//! \param pucData is the data for the character pattern.  It contains eight\r
+//! bytes, with the first byte being the top row of the pattern.  In each byte,\r
+//! the LSB is the right pixel of the pattern.\r
+//!\r
+//! This function will write a character pattern into the LCD for use as a\r
+//! character to be displayed.  After writing the pattern, it can be used on\r
+//! the LCD by writing the corresponding character index to the display.\r
+//!\r
+//! This function is contained in <tt>utils/pdc.c</tt>, with\r
+//! <tt>utils/pdc.h</tt> containing the API definition for use by applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+PDCLCDCreateChar(unsigned char ucChar, unsigned char *pucData)\r
+{\r
+    //\r
+    // Check the arguments.\r
+    //\r
+    ASSERT(ucChar < 8);\r
+\r
+    //\r
+    // Wait until the LCD has finished executing any previous command.\r
+    //\r
+    while((PDCRead(PDC_LCD_CSR) & LCD_B_BUSY))\r
+    {\r
+    }\r
+\r
+    //\r
+    // Write the character pattern memory address.\r
+    //\r
+    PDCWrite(PDC_LCD_CSR, LCD_CGADDR + (ucChar * 8));\r
+\r
+    //\r
+    // Write the pattern to chacter pattern memory.\r
+    //\r
+    for(ucChar = 0; ucChar < 8; ucChar++)\r
+    {\r
+        //\r
+        // Wait until the LCD has finished executing any previous command.\r
+        //\r
+        while((PDCRead(PDC_LCD_CSR) & LCD_B_BUSY))\r
+        {\r
+        }\r
+\r
+        //\r
+        // Write this row of the pattern.\r
+        //\r
+        PDCWrite(PDC_LCD_RAM, *pucData++);\r
+    }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Set the position of the cursor.\r
+//!\r
+//! \param ucX is the horizontal position.  Valid values are zero through\r
+//! fifteen.\r
+//! \param ucY is the vertical position.. Valid values are zero and one.\r
+//!\r
+//! This function will move the cursor to the specified position.  All\r
+//! characters written to the LCD are placed at the current cursor position,\r
+//! which is automatically advanced.\r
+//!\r
+//! This function is contained in <tt>utils/pdc.c</tt>, with\r
+//! <tt>utils/pdc.h</tt> containing the API definition for use by applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+PDCLCDSetPos(unsigned char ucX, unsigned char ucY)\r
+{\r
+    //\r
+    // Check the arguments.\r
+    //\r
+    ASSERT(ucX < 16);\r
+    ASSERT(ucY < 2);\r
+\r
+    //\r
+    // Wait until the LCD has finished executing any previous command.\r
+    //\r
+    while((PDCRead(PDC_LCD_CSR) & LCD_B_BUSY))\r
+    {\r
+    }\r
+\r
+    //\r
+    // Set the cursor position.\r
+    //\r
+    PDCWrite(PDC_LCD_CSR, LCD_DDADDR | (0x40 * ucY) + ucX);\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Writes a string to the LCD display.\r
+//!\r
+//! \param pcStr pointer to the string to be displayed.\r
+//! \param ulCount is the number of characters to be displayed.\r
+//!\r
+//! This function will display a string on the LCD at the current cursor\r
+//! position.  It is the caller's responsibility to position the cursor to the\r
+//! place where the string should be displayed (either explicitly via\r
+//! PDCLCDSetPos() or implicitly from where the cursor was left after a\r
+//! previous call to PDCLCDWrite()), and to properly account for the LCD\r
+//! boundary (line wrapping is not automatically performed).  Null characters\r
+//! are not treated special and are written to the LCD, which interprets it as\r
+//! a special programmable character glyph (see PDCLCDCreateChar()).\r
+//!\r
+//! This function is contained in <tt>utils/pdc.c</tt>, with\r
+//! <tt>utils/pdc.h</tt> containing the API definition for use by applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+PDCLCDWrite(const char *pcStr, unsigned long ulCount)\r
+{\r
+    //\r
+    // Write the string to the LCD.\r
+    //\r
+    while(ulCount--)\r
+    {\r
+        //\r
+        // Wait until the LCD has finished executing any previous command.\r
+        //\r
+        while((PDCRead(PDC_LCD_CSR) & LCD_B_BUSY))\r
+        {\r
+        }\r
+\r
+        //\r
+        // Write this character to the LCD.\r
+        //\r
+        PDCWrite(PDC_LCD_RAM, *pcStr++);\r
+    }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Reads a GPIO direction register.\r
+//!\r
+//! \param ucIdx is the index of the GPIO direction register to read; valid\r
+//! values are 0, 1, and 2.\r
+//!\r
+//! This function reads one of the GPIO direction registers in the PDC.  The\r
+//! direction bit is set for pins that are outputs and clear for pins that are\r
+//! inputs.\r
+//!\r
+//! This function is contained in <tt>utils/pdc.c</tt>, with\r
+//! <tt>utils/pdc.h</tt> containing the API definition for use by applications.\r
+//!\r
+//! \return The contents of the direction register.\r
+//\r
+//*****************************************************************************\r
+unsigned char\r
+PDCGPIODirRead(unsigned char ucIdx)\r
+{\r
+    //\r
+    // Check the argument.\r
+    //\r
+    ASSERT((ucIdx == 0) || (ucIdx == 1) || (ucIdx == 2));\r
+\r
+    //\r
+    // Read the requested direction register.\r
+    //\r
+    if(ucIdx == 0)\r
+    {\r
+        return(PDCRead(PDC_GPXDIR));\r
+    }\r
+    else if(ucIdx == 1)\r
+    {\r
+        return(PDCRead(PDC_GPYDIR));\r
+    }\r
+    else\r
+    {\r
+        return(PDCRead(PDC_GPZDIR));\r
+    }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Write a GPIO direction register.\r
+//!\r
+//! \param ucIdx is the index of the GPIO direction register to write; valid\r
+//! values are 0, 1, and 2.\r
+//! \param ucValue is the value to write to the GPIO direction register.\r
+//!\r
+//! This function writes ones of the GPIO direction registers in the PDC.  The\r
+//! direction bit should be set for pins that are to be outputs and clear for\r
+//! pins that are to be inputs.\r
+//!\r
+//! This function is contained in <tt>utils/pdc.c</tt>, with\r
+//! <tt>utils/pdc.h</tt> containing the API definition for use by applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+PDCGPIODirWrite(unsigned char ucIdx, unsigned char ucValue)\r
+{\r
+    //\r
+    // Check the arguments.\r
+    //\r
+    ASSERT((ucIdx == 0) || (ucIdx == 1) || (ucIdx == 2));\r
+\r
+    //\r
+    // Write the requested direction register.\r
+    //\r
+    if(ucIdx == 0)\r
+    {\r
+        PDCWrite(PDC_GPXDIR, ucValue);\r
+    }\r
+    else if(ucIdx == 1)\r
+    {\r
+        PDCWrite(PDC_GPYDIR, ucValue);\r
+    }\r
+    else\r
+    {\r
+        PDCWrite(PDC_GPZDIR, ucValue);\r
+    }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Reads a GPIO data register.\r
+//!\r
+//! \param ucIdx is the index of the GPIO direction register to read; valid\r
+//! values are 0, 1, and 2.\r
+//!\r
+//! This function reads one of the GPIO data registers in the PDC.  The value\r
+//! returned for a pin is the value being driven out for outputs or the value\r
+//! being read for inputs.\r
+//!\r
+//! This function is contained in <tt>utils/pdc.c</tt>, with\r
+//! <tt>utils/pdc.h</tt> containing the API definition for use by applications.\r
+//!\r
+//! \return The contents of the data register.\r
+//\r
+//*****************************************************************************\r
+unsigned char\r
+PDCGPIORead(unsigned char ucIdx)\r
+{\r
+    //\r
+    // Check the argument.\r
+    //\r
+    ASSERT((ucIdx == 0) || (ucIdx == 1) || (ucIdx == 2));\r
+\r
+    //\r
+    // Read the requested data register.\r
+    //\r
+    if(ucIdx == 0)\r
+    {\r
+        return(PDCRead(PDC_GPXDAT));\r
+    }\r
+    else if(ucIdx == 1)\r
+    {\r
+        return(PDCRead(PDC_GPYDAT));\r
+    }\r
+    else\r
+    {\r
+        return(PDCRead(PDC_GPZDAT));\r
+    }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+//! Write a GPIO data register.\r
+//!\r
+//! \param ucIdx is the index of the GPIO data register to write; valid values\r
+//! are 0, 1, and 2.\r
+//! \param ucValue is the value to write to the GPIO data register.\r
+//!\r
+//! This function writes one of the GPIO direction registers in the PDC.  The\r
+//! written to a pin is driven out for output pins and ignored for input pins.\r
+//!\r
+//! This function is contained in <tt>utils/pdc.c</tt>, with\r
+//! <tt>utils/pdc.h</tt> containing the API definition for use by applications.\r
+//!\r
+//! \return None.\r
+//\r
+//*****************************************************************************\r
+void\r
+PDCGPIOWrite(unsigned char ucIdx, unsigned char ucValue)\r
+{\r
+    //\r
+    // Check the arguments.\r
+    //\r
+    ASSERT((ucIdx == 0) || (ucIdx == 1) || (ucIdx == 2));\r
+\r
+    //\r
+    // Write the requested data register.\r
+    //\r
+    if(ucIdx == 0)\r
+    {\r
+        PDCWrite(PDC_GPXDAT, ucValue);\r
+    }\r
+    else if(ucIdx == 1)\r
+    {\r
+        PDCWrite(PDC_GPYDAT, ucValue);\r
+    }\r
+    else\r
+    {\r
+        PDCWrite(PDC_GPZDAT, ucValue);\r
+    }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// Close the Doxygen group.\r
+//! @}\r
+//\r
+//*****************************************************************************\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/pdc.h b/Demo/CORTEX_LM3S316_IAR/hw_include/pdc.h

new file mode 100644 (file)

index 0000000..9529424
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/pdc.h
@@ -0,0 +1,124 @@
+//*****************************************************************************\r
+//\r
+// pdc.h - Stellaris development board Peripheral Device Controller definitions\r
+//         and prototypes.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __PDC_H__\r
+#define __PDC_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The registers within the peripheral device controller.\r
+//\r
+//*****************************************************************************\r
+#define PDC_VER                 0x0         // Version register\r
+#define PDC_CSR                 0x1         // Command/Status register\r
+#define PDC_DSW                 0x4         // DIP Switch register\r
+#define PDC_LED                 0x5         // LED register\r
+#define PDC_LCD_CSR             0x6         // LCD Command/Status register\r
+#define PDC_LCD_RAM             0x7         // LCD RAM register\r
+#define PDC_GPXDAT              0x8         // GPIO X Data register\r
+#define PDC_GPXDIR              0x9         // GPIO X Direction register\r
+#define PDC_GPYDAT              0xA         // GPIO Y Data register\r
+#define PDC_GPYDIR              0xB         // GPIO Y Direction register\r
+#define PDC_GPZDAT              0xC         // GPIO Z Data register\r
+#define PDC_GPZDIR              0xD         // GPIO Z Direction register\r
+\r
+//*****************************************************************************\r
+//\r
+// Flags indicating a read or write to the peripheral device controller.\r
+//\r
+//*****************************************************************************\r
+#define PDC_RD                  0x80        // PDC read command\r
+#define PDC_WR                  0x00        // PDC write command\r
+\r
+//*****************************************************************************\r
+//\r
+// LCD panel (Crystalfontz CFAH1602B) commands, RS = 0\r
+//\r
+//*****************************************************************************\r
+#define LCD_CLEAR               0x01        // Clear display (0 fill DDRAM).\r
+#define LCD_HOME                0x02        // Cursor home.\r
+#define LCD_MODE                0x04        // Set entry mode (cursor dir)\r
+#define LCD_ON                  0x08        // Set display, cursor, blinking\r
+                                            // on/off\r
+#define LCD_CUR                 0x10        // Cursor, display shift\r
+#define LCD_IF                  0x20        // Set interface data length,\r
+                                            // lines, font\r
+#define LCD_CGADDR              0x40        // Set CGRAM AC address\r
+#define LCD_DDADDR              0x80        // Set DDRAM AC address\r
+\r
+//*****************************************************************************\r
+//\r
+// LCD Status bit\r
+//\r
+//*****************************************************************************\r
+#define LCD_B_BUSY              0x80        // Busy flag.\r
+\r
+//*****************************************************************************\r
+//\r
+// The GPIO port A pin numbers for the various SSI signals.\r
+//\r
+//*****************************************************************************\r
+#define SSI_CS                  GPIO_PIN_3\r
+#define PDC_CS                  GPIO_PIN_3\r
+#define SSI_CLK                 GPIO_PIN_2\r
+#define SSI_TX                  GPIO_PIN_5\r
+#define SSI_RX                  GPIO_PIN_4\r
+\r
+//*****************************************************************************\r
+//\r
+// Function Prototypes\r
+//\r
+//*****************************************************************************\r
+extern void PDCInit(void);\r
+extern unsigned char PDCRead(unsigned char ucAddr);\r
+extern void PDCWrite(unsigned char ucAddr, unsigned char ucData);\r
+extern unsigned char PDCDIPRead(void);\r
+extern void PDCLEDWrite(unsigned char ucLED);\r
+extern unsigned char PDCLEDRead(void);\r
+extern void PDCLCDInit(void);\r
+extern void PDCLCDBacklightOn(void);\r
+extern void PDCLCDBacklightOff(void);\r
+extern void PDCLCDClear(void);\r
+extern void PDCLCDCreateChar(unsigned char ucChar, unsigned char *pucData);\r
+extern void PDCLCDSetPos(unsigned char ucX, unsigned char ucY);\r
+extern void PDCLCDWrite(const char *pcStr, unsigned long ulCount);\r
+extern unsigned char PDCGPIODirRead(unsigned char ucIdx);\r
+extern void PDCGPIODirWrite(unsigned char ucIdx, unsigned char ucValue);\r
+extern unsigned char PDCGPIORead(unsigned char ucIdx);\r
+extern void PDCGPIOWrite(unsigned char ucIdx, unsigned char ucValue);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __PDC_H__\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/pwm.h b/Demo/CORTEX_LM3S316_IAR/hw_include/pwm.h

new file mode 100644 (file)

index 0000000..13cd4e1
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/pwm.h
@@ -0,0 +1,161 @@
+//*****************************************************************************\r
+//\r
+// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __PWM_H__\r
+#define __PWM_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following defines are passed to PWMGenConfigure() as the ulConfig\r
+// parameter and specify the configuration of the PWM generator.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_MODE_DOWN       0x00000000  // Down count mode\r
+#define PWM_GEN_MODE_UP_DOWN    0x00000002  // Up/Down count mode\r
+#define PWM_GEN_MODE_SYNC       0x00000038  // Synchronous updates\r
+#define PWM_GEN_MODE_NO_SYNC    0x00000000  // Immediate updates\r
+#define PWM_GEN_MODE_DBG_RUN    0x00000004  // Continue running in debug mode\r
+#define PWM_GEN_MODE_DBG_STOP   0x00000000  // Stop running in debug mode\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines for enabling, disabling, and clearing PWM generator interrupts and\r
+// triggers.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INT_CNT_ZERO        0x00000001  // Int if COUNT = 0\r
+#define PWM_INT_CNT_LOAD        0x00000002  // Int if COUNT = LOAD\r
+#define PWM_INT_CNT_AU          0x00000004  // Int if COUNT = CMPA U\r
+#define PWM_INT_CNT_AD          0x00000008  // Int if COUNT = CMPA D\r
+#define PWM_INT_CNT_BU          0x00000010  // Int if COUNT = CMPA U\r
+#define PWM_INT_CNT_BD          0x00000020  // Int if COUNT = CMPA D\r
+#define PWM_TR_CNT_ZERO         0x00000100  // Trig if COUNT = 0\r
+#define PWM_TR_CNT_LOAD         0x00000200  // Trig if COUNT = LOAD\r
+#define PWM_TR_CNT_AU           0x00000400  // Trig if COUNT = CMPA U\r
+#define PWM_TR_CNT_AD           0x00000800  // Trig if COUNT = CMPA D\r
+#define PWM_TR_CNT_BU           0x00001000  // Trig if COUNT = CMPA U\r
+#define PWM_TR_CNT_BD           0x00002000  // Trig if COUNT = CMPA D\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines for enabling, disabling, and clearing PWM interrupts.\r
+//\r
+//*****************************************************************************\r
+#define PWM_INT_GEN_0           0x00000001  // Generator 0 interrupt\r
+#define PWM_INT_GEN_1           0x00000002  // Generator 1 interrupt\r
+#define PWM_INT_GEN_2           0x00000004  // Generator 2 interrupt\r
+#define PWM_INT_FAULT           0x00010000  // Fault interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines to identify the generators within a module.\r
+//\r
+//*****************************************************************************\r
+#define PWM_GEN_0               0x00000040  // Offset address of Gen0\r
+#define PWM_GEN_1               0x00000080  // Offset address of Gen1\r
+#define PWM_GEN_2               0x000000C0  // Offset address of Gen2\r
+\r
+#define PWM_GEN_0_BIT           0x00000001  // Bit-wise ID for Gen0\r
+#define PWM_GEN_1_BIT           0x00000002  // Bit-wise ID for Gen1\r
+#define PWM_GEN_2_BIT           0x00000004  // Bit-wise ID for Gen2\r
+\r
+//*****************************************************************************\r
+//\r
+// Defines to identify the outputs within a module.\r
+//\r
+//*****************************************************************************\r
+#define PWM_OUT_0               0x00000040  // Encoded offset address of PWM0\r
+#define PWM_OUT_1               0x00000041  // Encoded offset address of PWM1\r
+#define PWM_OUT_2               0x00000082  // Encoded offset address of PWM2\r
+#define PWM_OUT_3               0x00000083  // Encoded offset address of PWM3\r
+#define PWM_OUT_4               0x000000C4  // Encoded offset address of PWM4\r
+#define PWM_OUT_5               0x000000C5  // Encoded offset address of PWM5\r
+\r
+#define PWM_OUT_0_BIT           0x00000001  // Bit-wise ID for PWM0\r
+#define PWM_OUT_1_BIT           0x00000002  // Bit-wise ID for PWM1\r
+#define PWM_OUT_2_BIT           0x00000004  // Bit-wise ID for PWM2\r
+#define PWM_OUT_3_BIT           0x00000008  // Bit-wise ID for PWM3\r
+#define PWM_OUT_4_BIT           0x00000010  // Bit-wise ID for PWM4\r
+#define PWM_OUT_5_BIT           0x00000020  // Bit-wise ID for PWM5\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen,\r
+                            unsigned long ulConfig);\r
+extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen,\r
+                            unsigned long ulPeriod);\r
+extern unsigned long PWMGenPeriodGet(unsigned long ulBase,\r
+                                     unsigned long ulGen);\r
+extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut,\r
+                             unsigned long ulWidth);\r
+extern unsigned long PWMPulseWidthGet(unsigned long ulBase,\r
+                                      unsigned long ulPWMOut);\r
+extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen,\r
+                              unsigned short usRise, unsigned short usFall);\r
+extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits);\r
+extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits);\r
+extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits,\r
+                           tBoolean bEnable);\r
+extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits,\r
+                            tBoolean bInvert);\r
+extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits,\r
+                           tBoolean bFaultKill);\r
+extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen,\r
+                              void (*pfIntHandler)(void));\r
+extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen);\r
+extern void PWMFaultIntRegister(unsigned long ulBase,\r
+                                void (*pfIntHandler)(void));\r
+extern void PWMFaultIntUnregister(unsigned long ulBase);\r
+extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen,\r
+                                unsigned long ulIntTrig);\r
+extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen,\r
+                                 unsigned long ulIntTrig);\r
+extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen,\r
+                                     tBoolean bMasked);\r
+extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen,\r
+                           unsigned long ulInts);\r
+extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault);\r
+extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault);\r
+extern void PWMFaultIntClear(unsigned long ulBase);\r
+extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __PWM_H__\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/ssi.h b/Demo/CORTEX_LM3S316_IAR/hw_include/ssi.h

new file mode 100644 (file)

index 0000000..26094b9
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/ssi.h
@@ -0,0 +1,88 @@
+//*****************************************************************************\r
+//\r
+// ssi.h - Prototypes for the Synchronous Serial Interface Driver.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __SSI_H__\r
+#define __SSI_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear\r
+// as the ulIntFlags parameter, and returned by SSIIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define SSI_TXFF                0x00000008  // TX FIFO half empty or less\r
+#define SSI_RXFF                0x00000004  // RX FIFO half full or less\r
+#define SSI_RXTO                0x00000002  // RX timeout\r
+#define SSI_RXOR                0x00000001  // RX overrun\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to SSIConfig.\r
+//\r
+//*****************************************************************************\r
+#define SSI_FRF_MOTO_MODE_0     0x00000000  // Moto fmt, polarity 0, phase 0\r
+#define SSI_FRF_MOTO_MODE_1     0x00000002  // Moto fmt, polarity 0, phase 1\r
+#define SSI_FRF_MOTO_MODE_2     0x00000001  // Moto fmt, polarity 1, phase 0\r
+#define SSI_FRF_MOTO_MODE_3     0x00000003  // Moto fmt, polarity 1, phase 1\r
+#define SSI_FRF_TI              0x00000010  // TI frame format\r
+#define SSI_FRF_NMW             0x00000020  // National MicroWire frame format\r
+\r
+#define SSI_MODE_MASTER         0x00000000  // SSI master\r
+#define SSI_MODE_SLAVE          0x00000001  // SSI slave\r
+#define SSI_MODE_SLAVE_OD       0x00000002  // SSI slave with output disabled\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void SSIConfig(unsigned long ulBase, unsigned long ulProtocol,\r
+                      unsigned long ulMode, unsigned long ulBitRate,\r
+                      unsigned long ulDataWidth);\r
+extern void SSIDataGet(unsigned long ulBase, unsigned long *ulData);\r
+extern long SSIDataNonBlockingGet(unsigned long ulBase, unsigned long *ulData);\r
+extern void SSIDataPut(unsigned long ulBase, unsigned long ulData);\r
+extern long SSIDataNonBlockingPut(unsigned long ulBase, unsigned long ulData);\r
+extern void SSIDisable(unsigned long ulBase);\r
+extern void SSIEnable(unsigned long ulBase);\r
+extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void));\r
+extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void SSIIntUnregister(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __SSI_H__\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/startup.c b/Demo/CORTEX_LM3S316_IAR/hw_include/startup.c

new file mode 100644 (file)

index 0000000..b07961b
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/startup.c
@@ -0,0 +1,297 @@
+//*****************************************************************************\r
+//\r
+// startup.c - Boot code for Stellaris.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+//*****************************************************************************\r
+//\r
+// Enable the IAR extensions for this source file.\r
+//\r
+//*****************************************************************************\r
+#pragma language=extended\r
+\r
+//*****************************************************************************\r
+//\r
+// Forward declaration of the default fault handlers.\r
+//\r
+//*****************************************************************************\r
+void ResetISR(void);\r
+static void NmiSR(void);\r
+static void FaultISR(void);\r
+static void IntDefaultHandler(void);\r
+\r
+//*****************************************************************************\r
+//\r
+// External declaration for the interrupt handler used by the application.\r
+//\r
+//*****************************************************************************\r
+extern void xPortPendSVHandler(void);\r
+extern void xPortSysTickHandler(void);\r
+extern void vUART_ISR( void );\r
+\r
+//*****************************************************************************\r
+//\r
+// The entry point for the application.\r
+//\r
+//*****************************************************************************\r
+extern void main(void);\r
+\r
+//*****************************************************************************\r
+//\r
+// Reserve space for the system stack.\r
+//\r
+//*****************************************************************************\r
+#ifndef STACK_SIZE\r
+#define STACK_SIZE                              50\r
+#endif\r
+static unsigned long pulStack[STACK_SIZE] = { \r
+0xbbbbbbbb, \r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb, \r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb, \r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb, \r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb, \r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb,\r
+0xbbbbbbbb };\r
+//*****************************************************************************\r
+//\r
+// A union that describes the entries of the vector table.  The union is needed\r
+// since the first entry is the stack pointer and the remainder are function\r
+// pointers.\r
+//\r
+//*****************************************************************************\r
+typedef union\r
+{\r
+    void (*pfnHandler)(void);\r
+    unsigned long ulPtr;\r
+}\r
+uVectorEntry;\r
+\r
+//*****************************************************************************\r
+//\r
+// The minimal vector table for a Cortex M3.  Note that the proper constructs\r
+// must be placed on this to ensure that it ends up at physical address\r
+// 0x0000.0000.\r
+//\r
+//*****************************************************************************\r
+__root const uVectorEntry g_pfnVectors[] @ "INTVEC" =\r
+{\r
+    { .ulPtr = (unsigned long)pulStack + sizeof(pulStack) },\r
+                                            // The initial stack pointer\r
+    ResetISR,                               // The reset handler\r
+    NmiSR,                                  // The NMI handler\r
+    FaultISR,                               // The hard fault handler\r
+    IntDefaultHandler,                      // The MPU fault handler\r
+    IntDefaultHandler,                      // The bus fault handler\r
+    IntDefaultHandler,                      // The usage fault handler\r
+    0,                                      // Reserved\r
+    0,                                      // Reserved\r
+    0,                                      // Reserved\r
+    0,                                      // Reserved\r
+    IntDefaultHandler,                      // SVCall handler\r
+    IntDefaultHandler,                      // Debug monitor handler\r
+    0,                                      // Reserved\r
+    xPortPendSVHandler,                     // The PendSV handler\r
+    xPortSysTickHandler,                    // The SysTick handler\r
+    IntDefaultHandler,                      // GPIO Port A\r
+    IntDefaultHandler,                      // GPIO Port B\r
+    IntDefaultHandler,                      // GPIO Port C\r
+    IntDefaultHandler,                      // GPIO Port D\r
+    IntDefaultHandler,                      // GPIO Port E\r
+    vUART_ISR,                                 // UART0 Rx and Tx\r
+    IntDefaultHandler,                      // UART1 Rx and Tx\r
+    IntDefaultHandler,                      // SSI Rx and Tx\r
+    IntDefaultHandler,                      // I2C Master and Slave\r
+    IntDefaultHandler,                      // PWM Fault\r
+    IntDefaultHandler,                      // PWM Generator 0\r
+    IntDefaultHandler,                      // PWM Generator 1\r
+    IntDefaultHandler,                      // PWM Generator 2\r
+    0,                                      // Reserved\r
+    IntDefaultHandler,                      // ADC Sequence 0\r
+    IntDefaultHandler,                      // ADC Sequence 1\r
+    IntDefaultHandler,                      // ADC Sequence 2\r
+    IntDefaultHandler,                      // ADC Sequence 3\r
+    IntDefaultHandler,                      // Watchdog timer\r
+    IntDefaultHandler,                      // Timer 0 subtimer A\r
+    IntDefaultHandler,                      // Timer 0 subtimer B\r
+    IntDefaultHandler,                      // Timer 1 subtimer A\r
+    IntDefaultHandler,                      // Timer 1 subtimer B\r
+    IntDefaultHandler,                      // Timer 2 subtimer A\r
+    IntDefaultHandler,                      // Timer 2 subtimer B\r
+    IntDefaultHandler,                      // Analog Comparator 0\r
+    IntDefaultHandler,                      // Analog Comparator 1\r
+    IntDefaultHandler,                      // Analog Comparator 2\r
+    IntDefaultHandler,                      // System Control (PLL, OSC, BO)\r
+    IntDefaultHandler                       // FLASH Control\r
+};\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are constructs created by the linker, indicating where the\r
+// the "data" and "bss" segments reside in memory.  The initializers for the\r
+// for the "data" segment resides immediately following the "text" segment.\r
+//\r
+//*****************************************************************************\r
+#pragma segment="DATA_ID"\r
+#pragma segment="DATA_I"\r
+#pragma segment="DATA_Z"\r
+\r
+//*****************************************************************************\r
+//\r
+// This is the code that gets called when the processor first starts execution\r
+// following a reset event.  Only the absolutely necessary set is performed,\r
+// after which the application supplied entry() routine is called.  Any fancy\r
+// actions (such as making decisions based on the reset cause register, and\r
+// resetting the bits in that register) are left solely in the hands of the\r
+// application.\r
+//\r
+//*****************************************************************************\r
+void\r
+ResetISR(void)\r
+{\r
+    unsigned long *pulSrc, *pulDest, *pulEnd;\r
+\r
+    //\r
+    // Copy the data segment initializers from flash to SRAM.\r
+    //\r
+    pulSrc = __segment_begin("DATA_ID");\r
+    pulDest = __segment_begin("DATA_I");\r
+    pulEnd = __segment_end("DATA_I");\r
+    while(pulDest < pulEnd)\r
+    {\r
+        *pulDest++ = *pulSrc++;\r
+    }\r
+\r
+    //\r
+    // Zero fill the bss segment.\r
+    //\r
+    pulDest = __segment_begin("DATA_Z");\r
+    pulEnd = __segment_end("DATA_Z");\r
+    while(pulDest < pulEnd)\r
+    {\r
+        *pulDest++ = 0;\r
+    }\r
+\r
+    //\r
+    // Call the application's entry point.\r
+    //\r
+    main();\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// This is the code that gets called when the processor receives a NMI.  This\r
+// simply enters an infinite loop, preserving the system state for examination\r
+// by a debugger.\r
+//\r
+//*****************************************************************************\r
+static void\r
+NmiSR(void)\r
+{\r
+    //\r
+    // Enter an infinite loop.\r
+    //\r
+    while(1)\r
+    {\r
+    }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// This is the code that gets called when the processor receives a fault\r
+// interrupt.  This simply enters an infinite loop, preserving the system state\r
+// for examination by a debugger.\r
+//\r
+//*****************************************************************************\r
+static void\r
+FaultISR(void)\r
+{\r
+    //\r
+    // Enter an infinite loop.\r
+    //\r
+    while(1)\r
+    {\r
+    }\r
+}\r
+\r
+//*****************************************************************************\r
+//\r
+// This is the code that gets called when the processor receives an unexpected\r
+// interrupt.  This simply enters an infinite loop, preserving the system state\r
+// for examination by a debugger.\r
+//\r
+//*****************************************************************************\r
+static void\r
+IntDefaultHandler(void)\r
+{\r
+    //\r
+    // Go into an infinite loop.\r
+    //\r
+    while(1)\r
+    {\r
+    }\r
+}\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/sysctl.h b/Demo/CORTEX_LM3S316_IAR/hw_include/sysctl.h

new file mode 100644 (file)

index 0000000..c5e0650
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/sysctl.h
@@ -0,0 +1,266 @@
+//*****************************************************************************\r
+//\r
+// sysctl.h - Prototypes for the system control driver.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __SYSCTL_H__\r
+#define __SYSCTL_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the\r
+// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),\r
+// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the\r
+// ulPeripheral parameter.  The peripherals in the fourth group (upper nibble\r
+// is 3) can only be used with the SysCtlPeripheralPresent() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PERIPH_PWM       0x00100000  // PWM\r
+#define SYSCTL_PERIPH_ADC       0x00010000  // ADC\r
+#define SYSCTL_PERIPH_WDOG      0x00000008  // Watchdog\r
+#define SYSCTL_PERIPH_UART0     0x10000001  // UART 0\r
+#define SYSCTL_PERIPH_UART1     0x10000002  // UART 1\r
+#define SYSCTL_PERIPH_SSI       0x10000010  // SSI\r
+#define SYSCTL_PERIPH_I2C       0x10001000  // I2C\r
+#define SYSCTL_PERIPH_TIMER0    0x10010000  // Timer 0\r
+#define SYSCTL_PERIPH_TIMER1    0x10020000  // Timer 1\r
+#define SYSCTL_PERIPH_TIMER2    0x10040000  // Timer 2\r
+#define SYSCTL_PERIPH_COMP0     0x11000000  // Analog comparator 0\r
+#define SYSCTL_PERIPH_COMP1     0x12000000  // Analog comparator 1\r
+#define SYSCTL_PERIPH_COMP2     0x14000000  // Analog comparator 2\r
+#define SYSCTL_PERIPH_GPIOA     0x20000001  // GPIO A\r
+#define SYSCTL_PERIPH_GPIOB     0x20000002  // GPIO B\r
+#define SYSCTL_PERIPH_GPIOC     0x20000004  // GPIO C\r
+#define SYSCTL_PERIPH_GPIOD     0x20000008  // GPIO D\r
+#define SYSCTL_PERIPH_GPIOE     0x20000010  // GPIO E\r
+#define SYSCTL_PERIPH_MPU       0x30000080  // Cortex M3 MPU\r
+#define SYSCTL_PERIPH_TEMP      0x30000020  // Temperature sensor\r
+#define SYSCTL_PERIPH_PLL       0x30000010  // PLL\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlPinPresent() API\r
+// as the ulPin parameter.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PIN_PWM0         0x00000001  // PWM0 pin\r
+#define SYSCTL_PIN_PWM1         0x00000002  // PWM1 pin\r
+#define SYSCTL_PIN_PWM2         0x00000004  // PWM2 pin\r
+#define SYSCTL_PIN_PWM3         0x00000008  // PWM3 pin\r
+#define SYSCTL_PIN_PWM4         0x00000010  // PWM4 pin\r
+#define SYSCTL_PIN_PWM5         0x00000020  // PWM5 pin\r
+#define SYSCTL_PIN_C0MINUS      0x00000040  // C0- pin\r
+#define SYSCTL_PIN_C0PLUS       0x00000080  // C0+ pin\r
+#define SYSCTL_PIN_C0O          0x00000100  // C0o pin\r
+#define SYSCTL_PIN_C1MINUS      0x00000200  // C1- pin\r
+#define SYSCTL_PIN_C1PLUS       0x00000400  // C1+ pin\r
+#define SYSCTL_PIN_C1O          0x00000800  // C1o pin\r
+#define SYSCTL_PIN_C2MINUS      0x00001000  // C2- pin\r
+#define SYSCTL_PIN_C2PLUS       0x00002000  // C2+ pin\r
+#define SYSCTL_PIN_C2O          0x00004000  // C2o pin\r
+#define SYSCTL_PIN_ADC0         0x00010000  // ADC0 pin\r
+#define SYSCTL_PIN_ADC1         0x00020000  // ADC1 pin\r
+#define SYSCTL_PIN_ADC2         0x00040000  // ADC2 pin\r
+#define SYSCTL_PIN_ADC3         0x00080000  // ADC3 pin\r
+#define SYSCTL_PIN_CCP0         0x01000000  // CCP0 pin\r
+#define SYSCTL_PIN_CCP1         0x02000000  // CCP1 pin\r
+#define SYSCTL_PIN_CCP2         0x04000000  // CCP2 pin\r
+#define SYSCTL_PIN_CCP3         0x08000000  // CCP3 pin\r
+#define SYSCTL_PIN_CCP4         0x10000000  // CCP4 pin\r
+#define SYSCTL_PIN_CCP5         0x20000000  // CCP5 pin\r
+#define SYSCTL_PIN_32KHZ        0x80000000  // 32kHz pin\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlLDOSet() API as\r
+// the ulVoltage value, or returned by the SysCtlLDOGet() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDO_2_25V        0x00000005  // LDO output of 2.25V\r
+#define SYSCTL_LDO_2_30V        0x00000004  // LDO output of 2.30V\r
+#define SYSCTL_LDO_2_35V        0x00000003  // LDO output of 2.35V\r
+#define SYSCTL_LDO_2_40V        0x00000002  // LDO output of 2.40V\r
+#define SYSCTL_LDO_2_45V        0x00000001  // LDO output of 2.45V\r
+#define SYSCTL_LDO_2_50V        0x00000000  // LDO output of 2.50V\r
+#define SYSCTL_LDO_2_55V        0x0000001f  // LDO output of 2.55V\r
+#define SYSCTL_LDO_2_60V        0x0000001e  // LDO output of 2.60V\r
+#define SYSCTL_LDO_2_65V        0x0000001d  // LDO output of 2.65V\r
+#define SYSCTL_LDO_2_70V        0x0000001c  // LDO output of 2.70V\r
+#define SYSCTL_LDO_2_75V        0x0000001b  // LDO output of 2.75V\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlLDOConfigSet() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_LDOCFG_ARST      0x00000001  // Allow LDO failure to reset\r
+#define SYSCTL_LDOCFG_NORST     0x00000000  // Do not reset on LDO failure\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlIntEnable(),\r
+// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask\r
+// by the SysCtlIntStatus() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_INT_PLL_LOCK     0x00000040  // PLL lock interrupt\r
+#define SYSCTL_INT_CUR_LIMIT    0x00000020  // Current limit interrupt\r
+#define SYSCTL_INT_IOSC_FAIL    0x00000010  // Internal oscillator failure int\r
+#define SYSCTL_INT_MOSC_FAIL    0x00000008  // Main oscillator failure int\r
+#define SYSCTL_INT_POR          0x00000004  // Power on reset interrupt\r
+#define SYSCTL_INT_BOR          0x00000002  // Brown out interrupt\r
+#define SYSCTL_INT_PLL_FAIL     0x00000001  // PLL failure interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlResetCauseClear()\r
+// API or returned by the SysCtlResetCauseGet() API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_CAUSE_LDO        0x00000020  // LDO power not OK reset\r
+#define SYSCTL_CAUSE_SW         0x00000010  // Software reset\r
+#define SYSCTL_CAUSE_WDOG       0x00000008  // Watchdog reset\r
+#define SYSCTL_CAUSE_BOR        0x00000004  // Brown-out reset\r
+#define SYSCTL_CAUSE_POR        0x00000002  // Power on reset\r
+#define SYSCTL_CAUSE_EXT        0x00000001  // External reset\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlBrownOutConfigSet()\r
+// API as the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_BOR_RESET        0x00000002  // Reset instead of interrupting\r
+#define SYSCTL_BOR_RESAMPLE     0x00000001  // Resample BOR before asserting\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlPWMClockSet() API\r
+// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet()\r
+// API.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_PWMDIV_1         0x00000000  // PWM clock is processor clock /1\r
+#define SYSCTL_PWMDIV_2         0x00100000  // PWM clock is processor clock /2\r
+#define SYSCTL_PWMDIV_4         0x00120000  // PWM clock is processor clock /4\r
+#define SYSCTL_PWMDIV_8         0x00140000  // PWM clock is processor clock /8\r
+#define SYSCTL_PWMDIV_16        0x00160000  // PWM clock is processor clock /16\r
+#define SYSCTL_PWMDIV_32        0x00180000  // PWM clock is processor clock /32\r
+#define SYSCTL_PWMDIV_64        0x001A0000  // PWM clock is processor clock /64\r
+\r
+//*****************************************************************************\r
+//\r
+// The following are values that can be passed to the SysCtlClockSet() API as\r
+// the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define SYSCTL_SYSDIV_1         0x07800000  // Processor clock is osc/pll /1\r
+#define SYSCTL_SYSDIV_2         0x00C00000  // Processor clock is osc/pll /2\r
+#define SYSCTL_SYSDIV_3         0x01400000  // Processor clock is osc/pll /3\r
+#define SYSCTL_SYSDIV_4         0x01C00000  // Processor clock is osc/pll /4\r
+#define SYSCTL_SYSDIV_5         0x02400000  // Processor clock is osc/pll /5\r
+#define SYSCTL_SYSDIV_6         0x02C00000  // Processor clock is osc/pll /6\r
+#define SYSCTL_SYSDIV_7         0x03400000  // Processor clock is osc/pll /7\r
+#define SYSCTL_SYSDIV_8         0x03C00000  // Processor clock is osc/pll /8\r
+#define SYSCTL_SYSDIV_9         0x04400000  // Processor clock is osc/pll /9\r
+#define SYSCTL_SYSDIV_10        0x04C00000  // Processor clock is osc/pll /10\r
+#define SYSCTL_SYSDIV_11        0x05400000  // Processor clock is osc/pll /11\r
+#define SYSCTL_SYSDIV_12        0x05C00000  // Processor clock is osc/pll /12\r
+#define SYSCTL_SYSDIV_13        0x06400000  // Processor clock is osc/pll /13\r
+#define SYSCTL_SYSDIV_14        0x06C00000  // Processor clock is osc/pll /14\r
+#define SYSCTL_SYSDIV_15        0x07400000  // Processor clock is osc/pll /15\r
+#define SYSCTL_SYSDIV_16        0x07C00000  // Processor clock is osc/pll /16\r
+#define SYSCTL_USE_PLL          0x00000000  // System clock is the PLL clock\r
+#define SYSCTL_USE_OSC          0x00003800  // System clock is the osc clock\r
+#define SYSCTL_XTAL_3_57MHZ     0x00000100  // External crystal is 3.579545MHz\r
+#define SYSCTL_XTAL_3_68MHZ     0x00000140  // External crystal is 3.6864MHz\r
+#define SYSCTL_XTAL_4MHZ        0x00000180  // External crystal is 4MHz\r
+#define SYSCTL_XTAL_4_09MHZ     0x000001C0  // External crystal is 4.096MHz\r
+#define SYSCTL_XTAL_4_91MHZ     0x00000200  // External crystal is 4.9152MHz\r
+#define SYSCTL_XTAL_5MHZ        0x00000240  // External crystal is 5MHz\r
+#define SYSCTL_XTAL_5_12MHZ     0x00000280  // External crystal is 5.12MHz\r
+#define SYSCTL_XTAL_6MHZ        0x000002C0  // External crystal is 6MHz\r
+#define SYSCTL_XTAL_6_14MHZ     0x00000300  // External crystal is 6.144MHz\r
+#define SYSCTL_XTAL_7_37MHZ     0x00000340  // External crystal is 7.3728MHz\r
+#define SYSCTL_XTAL_8MHZ        0x00000380  // External crystal is 8MHz\r
+#define SYSCTL_XTAL_8_19MHZ     0x000003C0  // External crystal is 8.192MHz\r
+#define SYSCTL_OSC_MAIN         0x00000000  // Oscillator source is main osc\r
+#define SYSCTL_OSC_INT          0x00000010  // Oscillator source is int. osc\r
+#define SYSCTL_OSC_INT4         0x00000020  // Oscillator source is int. osc /4\r
+#define SYSCTL_INT_OSC_DIS      0x00000002  // Disable internal oscillator\r
+#define SYSCTL_MAIN_OSC_DIS     0x00000001  // Disable main oscillator\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern unsigned long SysCtlSRAMSizeGet(void);\r
+extern unsigned long SysCtlFlashSizeGet(void);\r
+extern tBoolean SysCtlPinPresent(unsigned long ulPin);\r
+extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralReset(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralEnable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralDisable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral);\r
+extern void SysCtlPeripheralClockGating(tBoolean bEnable);\r
+extern void SysCtlIntRegister(void (*pfnHandler)(void));\r
+extern void SysCtlIntUnregister(void);\r
+extern void SysCtlIntEnable(unsigned long ulInts);\r
+extern void SysCtlIntDisable(unsigned long ulInts);\r
+extern void SysCtlIntClear(unsigned long ulInts);\r
+extern unsigned long SysCtlIntStatus(tBoolean bMasked);\r
+extern void SysCtlLDOSet(unsigned long ulVoltage);\r
+extern unsigned long SysCtlLDOGet(void);\r
+extern void SysCtlLDOConfigSet(unsigned long ulConfig);\r
+extern void SysCtlReset(void);\r
+extern void SysCtlSleep(void);\r
+extern void SysCtlDeepSleep(void);\r
+extern unsigned long SysCtlResetCauseGet(void);\r
+extern void SysCtlResetCauseClear(unsigned long ulCauses);\r
+extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,\r
+                                    unsigned long ulDelay);\r
+extern void SysCtlClockSet(unsigned long ulConfig);\r
+extern unsigned long SysCtlClockGet(void);\r
+extern void SysCtlPWMClockSet(unsigned long ulConfig);\r
+extern unsigned long SysCtlPWMClockGet(void);\r
+extern void SysCtlIOSCVerificationSet(tBoolean bEnable);\r
+extern void SysCtlMOSCVerificationSet(tBoolean bEnable);\r
+extern void SysCtlPLLVerificationSet(tBoolean bEnable);\r
+extern void SysCtlClkVerificationClear(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __SYSCTL_H__\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/systick.h b/Demo/CORTEX_LM3S316_IAR/hw_include/systick.h

new file mode 100644 (file)

index 0000000..9056076
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/systick.h
@@ -0,0 +1,55 @@
+//*****************************************************************************\r
+//\r
+// systick.h - Prototypes for the SysTick driver.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __SYSTICK_H__\r
+#define __SYSTICK_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void SysTickEnable(void);\r
+extern void SysTickDisable(void);\r
+extern void SysTickIntRegister(void (*pfnHandler)(void));\r
+extern void SysTickIntUnregister(void);\r
+extern void SysTickIntEnable(void);\r
+extern void SysTickIntDisable(void);\r
+extern void SysTickPeriodSet(unsigned long ulPeriod);\r
+extern unsigned long SysTickPeriodGet(void);\r
+extern unsigned long SysTickValueGet(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __SYSTICK_H__\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/timer.h b/Demo/CORTEX_LM3S316_IAR/hw_include/timer.h

new file mode 100644 (file)

index 0000000..e604186
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/timer.h
@@ -0,0 +1,137 @@
+//*****************************************************************************\r
+//\r
+// timer.h - Prototypes for the timer module\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __TIMER_H__\r
+#define __TIMER_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerConfigure as the ulConfig parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CFG_32_BIT_OS     0x00000001  // 32-bit one-shot timer\r
+#define TIMER_CFG_32_BIT_PER    0x00000002  // 32-bit periodic timer\r
+#define TIMER_CFG_32_RTC        0x01000000  // 32-bit RTC timer\r
+#define TIMER_CFG_16_BIT_PAIR   0x04000000  // Two 16-bit timers\r
+#define TIMER_CFG_A_ONE_SHOT    0x00000001  // Timer A one-shot timer\r
+#define TIMER_CFG_A_PERIODIC    0x00000002  // Timer A periodic timer\r
+#define TIMER_CFG_A_CAP_COUNT   0x00000003  // Timer A event counter\r
+#define TIMER_CFG_A_CAP_TIME    0x00000007  // Timer A event timer\r
+#define TIMER_CFG_A_PWM         0x0000000A  // Timer A PWM output\r
+#define TIMER_CFG_B_ONE_SHOT    0x00000100  // Timer B one-shot timer\r
+#define TIMER_CFG_B_PERIODIC    0x00000200  // Timer B periodic timer\r
+#define TIMER_CFG_B_CAP_COUNT   0x00000300  // Timer B event counter\r
+#define TIMER_CFG_B_CAP_TIME    0x00000700  // Timer B event timer\r
+#define TIMER_CFG_B_PWM         0x00000A00  // Timer B PWM output\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerIntEnable, TimerIntDisable, and\r
+// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_CAPB_EVENT        0x00000400  // CaptureB event interrupt\r
+#define TIMER_CAPB_MATCH        0x00000200  // CaptureB match interrupt\r
+#define TIMER_TIMB_TIMEOUT      0x00000100  // TimerB time out interrupt\r
+#define TIMER_RTC_MATCH         0x00000008  // RTC interrupt mask\r
+#define TIMER_CAPA_EVENT        0x00000004  // CaptureA event interrupt\r
+#define TIMER_CAPA_MATCH        0x00000002  // CaptureA match interrupt\r
+#define TIMER_TIMA_TIMEOUT      0x00000001  // TimerA time out interrupt\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to TimerControlEvent as the ulEvent parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_EVENT_POS_EDGE    0x00000000  // Count positive edges\r
+#define TIMER_EVENT_NEG_EDGE    0x00000404  // Count negative edges\r
+#define TIMER_EVENT_BOTH_EDGES  0x00000C0C  // Count both edges\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to most of the timer APIs as the ulTimer\r
+// parameter.\r
+//\r
+//*****************************************************************************\r
+#define TIMER_A                 0x000000ff  // Timer A\r
+#define TIMER_B                 0x0000ff00  // Timer B\r
+#define TIMER_BOTH              0x0000ffff  // Timer Both\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);\r
+extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,\r
+                              tBoolean bInvert);\r
+extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,\r
+                                tBoolean bEnable);\r
+extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,\r
+                              unsigned long ulEvent);\r
+extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,\r
+                              tBoolean bStall);\r
+extern void TimerRTCEnable(unsigned long ulBase);\r
+extern void TimerRTCDisable(unsigned long ulBase);\r
+extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,\r
+                             unsigned long ulValue);\r
+extern unsigned long TimerPrescaleGet(unsigned long ulBase,\r
+                                      unsigned long ulTimer);\r
+extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
+                                  unsigned long ulValue);\r
+extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,\r
+                                           unsigned long ulTimer);\r
+extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,\r
+                         unsigned long ulValue);\r
+extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);\r
+extern unsigned long TimerValueGet(unsigned long ulBase,\r
+                                   unsigned long ulTimer);\r
+extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,\r
+                          unsigned long ulValue);\r
+extern unsigned long TimerMatchGet(unsigned long ulBase,\r
+                                   unsigned long ulTimer);\r
+extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,\r
+                             void (*pfnHandler)(void));\r
+extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);\r
+extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void TimerQuiesce(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __TIMER_H__\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/uart.h b/Demo/CORTEX_LM3S316_IAR/hw_include/uart.h

new file mode 100644 (file)

index 0000000..d90fba8
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/uart.h
@@ -0,0 +1,102 @@
+//*****************************************************************************\r
+//\r
+// uart.h - Defines and Macros for the UART.\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __UART_H__\r
+#define __UART_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear\r
+// as the ulIntFlags parameter, and returned from UARTIntStatus.\r
+//\r
+//*****************************************************************************\r
+#define UART_INT_OE             0x400       // Overrun Error Interrupt Mask\r
+#define UART_INT_BE             0x200       // Break Error Interrupt Mask\r
+#define UART_INT_PE             0x100       // Parity Error Interrupt Mask\r
+#define UART_INT_FE             0x080       // Framing Error Interrupt Mask\r
+#define UART_INT_RT             0x040       // Receive Timeout Interrupt Mask\r
+#define UART_INT_TX             0x020       // Transmit Interrupt Mask\r
+#define UART_INT_RX             0x010       // Receive Interrupt Mask\r
+\r
+//*****************************************************************************\r
+//\r
+// Values that can be passed to UARTConfigSet as the ulConfig parameter and\r
+// returned by UARTConfigGet in the pulConfig parameter.  Additionally, the\r
+// UART_CONFIG_PAR_* subset can be passed to UARTParityModeSet as the ulParity\r
+// parameter, and are returned by UARTParityModeGet.\r
+//\r
+//*****************************************************************************\r
+#define UART_CONFIG_WLEN_8      0x00000060  // 8 bit data\r
+#define UART_CONFIG_WLEN_7      0x00000040  // 7 bit data\r
+#define UART_CONFIG_WLEN_6      0x00000020  // 6 bit data\r
+#define UART_CONFIG_WLEN_5      0x00000000  // 5 bit data\r
+#define UART_CONFIG_STOP_ONE    0x00000000  // One stop bit\r
+#define UART_CONFIG_STOP_TWO    0x00000008  // Two stop bits\r
+#define UART_CONFIG_PAR_NONE    0x00000000  // No parity\r
+#define UART_CONFIG_PAR_EVEN    0x00000006  // Even parity\r
+#define UART_CONFIG_PAR_ODD     0x00000002  // Odd parity\r
+#define UART_CONFIG_PAR_ONE     0x00000086  // Parity bit is one\r
+#define UART_CONFIG_PAR_ZERO    0x00000082  // Parity bit is zero\r
+\r
+//*****************************************************************************\r
+//\r
+// API Function prototypes\r
+//\r
+//*****************************************************************************\r
+extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity);\r
+extern unsigned long UARTParityModeGet(unsigned long ulBase);\r
+extern void UARTConfigSet(unsigned long ulBase, unsigned long ulBaud,\r
+                          unsigned long ulConfig);\r
+extern void UARTConfigGet(unsigned long ulBase, unsigned long *pulBaud,\r
+                          unsigned long *pulConfig);\r
+extern void UARTEnable(unsigned long ulBase);\r
+extern void UARTDisable(unsigned long ulBase);\r
+extern tBoolean UARTCharsAvail(unsigned long ulBase);\r
+extern tBoolean UARTSpaceAvail(unsigned long ulBase);\r
+extern long UARTCharNonBlockingGet(unsigned long ulBase);\r
+extern long UARTCharGet(unsigned long ulBase);\r
+extern tBoolean UARTCharNonBlockingPut(unsigned long ulBase,\r
+                                       unsigned char ucData);\r
+extern void UARTCharPut(unsigned long ulBase, unsigned char ucData);\r
+extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState);\r
+extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void));\r
+extern void UARTIntUnregister(unsigned long ulBase);\r
+extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags);\r
+extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif //  __UART_H__\r
diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/watchdog.h b/Demo/CORTEX_LM3S316_IAR/hw_include/watchdog.h

new file mode 100644 (file)

index 0000000..4d6dcd2
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/hw_include/watchdog.h
@@ -0,0 +1,63 @@
+//*****************************************************************************\r
+//\r
+// watchdog.h - Prototypes for the Watchdog Timer API\r
+//\r
+// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+// Software License Agreement\r
+//\r
+// Luminary Micro, Inc. (LMI) is supplying this software for use solely and\r
+// exclusively on LMI's Stellaris Family of microcontroller products.\r
+//\r
+// The software is owned by LMI and/or its suppliers, and is protected under\r
+// applicable copyright laws.  All rights are reserved.  Any use in violation\r
+// of the foregoing restrictions may subject the user to criminal sanctions\r
+// under applicable laws, as well as to civil liability for the breach of the\r
+// terms and conditions of this license.\r
+//\r
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+//\r
+// This is part of revision 635 of the Stellaris Driver Library.\r
+//\r
+//*****************************************************************************\r
+\r
+#ifndef __WATCHDOG_H__\r
+#define __WATCHDOG_H__\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+//*****************************************************************************\r
+//\r
+// Prototypes for the APIs.\r
+//\r
+//*****************************************************************************\r
+extern tBoolean WatchdogRunning(unsigned long ulBase);\r
+extern void WatchdogEnable(unsigned long ulBase);\r
+extern void WatchdogResetEnable(unsigned long ulBase);\r
+extern void WatchdogResetDisable(unsigned long ulBase);\r
+extern void WatchdogLock(unsigned long ulBase);\r
+extern void WatchdogUnlock(unsigned long ulBase);\r
+extern tBoolean WatchdogLockState(unsigned long ulBase);\r
+extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal);\r
+extern unsigned long WatchdogReloadGet(unsigned long ulBase);\r
+extern unsigned long WatchdogValueGet(unsigned long ulBase);\r
+extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void));\r
+extern void WatchdogIntUnregister(unsigned long ulBase);\r
+extern void WatchdogIntEnable(unsigned long ulBase);\r
+extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked);\r
+extern void WatchdogIntClear(unsigned long ulBase);\r
+extern void WatchdogStallDisable(unsigned long ulBase);\r
+extern void WatchdogStallDisable(unsigned long ulBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif // __WATCHDOG_H__\r
diff --git a/Demo/CORTEX_LM3S316_IAR/main.c b/Demo/CORTEX_LM3S316_IAR/main.c

new file mode 100644 (file)

index 0000000..1f7cac7
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/main.c
@@ -0,0 +1,444 @@
+/*\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+       This file is part of the FreeRTOS.org distribution.\r
+\r
+       FreeRTOS.org is free software; you can redistribute it and/or modify\r
+       it under the terms of the GNU General Public License as published by\r
+       the Free Software Foundation; either version 2 of the License, or\r
+       (at your option) any later version.\r
+\r
+       FreeRTOS.org is distributed in the hope that it will be useful,\r
+       but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+       GNU General Public License for more details.\r
+\r
+       You should have received a copy of the GNU General Public License\r
+       along with FreeRTOS.org; if not, write to the Free Software\r
+       Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\r
+\r
+       A special exception to the GPL can be applied should you wish to distribute\r
+       a combined work that includes FreeRTOS.org, without being obliged to provide\r
+       the source code for any proprietary components.  See the licensing section \r
+       of http://www.FreeRTOS.org for full details of how and when the exception\r
+       can be applied.\r
+\r
+       ***************************************************************************\r
+       See http://www.FreeRTOS.org for documentation, latest information, license \r
+       and contact details.  Please ensure to read the configuration and relevant \r
+       port sections of the online documentation.\r
+       ***************************************************************************\r
+*/\r
+\r
+/* \r
+ * This demo application creates eight co-routines and four tasks (five \r
+ * including the idle task).  The co-routines execute as part of the idle task \r
+ * hook.  The application is limited in size to allow its compilation using\r
+ * the KickStart version of the IAR compiler.\r
+ *\r
+ * Six of the created co-routines are the standard 'co-routine flash' \r
+ * co-routines contained within the Demo/Common/Minimal/crflash.c file and \r
+ * documented on the FreeRTOS.org WEB site.  \r
+ *\r
+ * The 'LCD Task' waits on a message queue for messages informing it what and\r
+ * where to display text.  This is the only task that accesses the LCD\r
+ * so mutual exclusion is guaranteed.\r
+ *\r
+ * The 'LCD Message Task' periodically sends strings to the LCD Task using\r
+ * the message queue.  The strings are rotated to form a short message and\r
+ * are written to the top row of the LCD.\r
+ *\r
+ * The 'ADC Co-routine' periodically reads the ADC input that is connected to\r
+ * the light sensor, forms a short message from the value, and then sends this\r
+ * message to the LCD Task using the same message queue.  The ADC readings are\r
+ * displayed on the bottom row of the LCD.  \r
+ *\r
+ * The eighth co-routine and final task control the transmission and reception\r
+ * of a string to UART 0.  The co-routine periodically sends the first \r
+ * character of the string to the UART, with the UART's TxEnd interrupt being\r
+ * used to transmit the remaining characters.  The UART's RxEnd interrupt \r
+ * receives the characters and places them on a queue to be processed by the \r
+ * 'COMs Rx' task.  An error is latched should an unexpected character be \r
+ * received, or any character be received out of sequence.  \r
+ *\r
+ * A loopback connector is required to ensure that each character transmitted \r
+ * on the UART is also received on the same UART.  For test purposes the UART\r
+ * FIFO's are not utalised in order to maximise the interrupt overhead.  Also\r
+ * a pseudo random interval is used between the start of each transmission in \r
+ * order that the resultant interrupts are more randomly distributed and \r
+ * therefore more likely to highlight any problems.\r
+ *\r
+ * The flash co-routines control LED's zero to four.  LED five is toggled each\r
+ * time the string is transmitted on the UART.  LED six is toggled each time\r
+ * the string is CORRECTLY received on the UART.  LED seven is latched on \r
+ * should an error be detected in any task or co-routine.\r
+ *\r
+ * In addition the idle task makes repetitive calls to \r
+ * vSetAndCheckRegisters().  This simply loads the general purpose registers \r
+ * with a known value, then checks each register to ensure the held value is \r
+ * still correct.  As a low priority task this checking routine is likely to \r
+ * get repeatedly swapped in and out.  A register being found to contain an \r
+ * incorrect value is therefore indicative of an error in the task switching \r
+ * mechanism.\r
+ *\r
+ */\r
+\r
+/* standard include files. */\r
+#include <stdio.h>\r
+\r
+/* Scheduler include files. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "croutine.h"\r
+\r
+/* Demo application include files. */\r
+#include "partest.h"\r
+#include "crflash.h"\r
+#include "commstest.h"\r
+\r
+/* Library include files. */\r
+#include "DriverLib.h"\r
+\r
+/* The time to delay between writing each character to the LCD. */\r
+#define mainCHAR_WRITE_DELAY           ( 2 / portTICK_RATE_MS )\r
+\r
+/* The time to delay between writing each string to the LCD. */\r
+#define mainSTRING_WRITE_DELAY         ( 400 / portTICK_RATE_MS )\r
+\r
+#define mainADC_DELAY                          ( 200 / portTICK_RATE_MS )\r
+\r
+/* The number of flash co-routines to create. */\r
+#define mainNUM_FLASH_CO_ROUTINES      ( 5 )\r
+\r
+/* The length of the queue used to send messages to the LCD task. */\r
+#define mainLCD_QUEUE_LEN                      ( 3 )\r
+\r
+/* The priority of the co-routine used to initiate the transmission of the \r
+string on UART 0. */\r
+#define mainTX_CO_ROUTINE_PRIORITY     ( 1 )\r
+#define mainADC_CO_ROUTINE_PRIORITY    ( 2 )\r
+\r
+/* Only one of each co-routine is created so its index is not important. */\r
+#define mainTX_CO_ROUTINE_INDEX                ( 0 )\r
+#define mainADC_CO_ROUTINE_INDEX       ( 0 )\r
+\r
+/* The task priorities. */\r
+#define mainLCD_TASK_PRIORITY          ( tskIDLE_PRIORITY + 1 )\r
+#define mainMSG_TASK_PRIORITY          ( mainLCD_TASK_PRIORITY - 1 )\r
+#define mainCOMMS_RX_TASK_PRIORITY     ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* The LCD had two rows. */\r
+#define mainTOP_ROW            0\r
+#define mainBOTTOM_ROW         1\r
+\r
+/* Dimension for the buffer into which the ADC value string is written. */\r
+#define mainMAX_ADC_STRING_LEN 20\r
+\r
+/* The LED that is lit should an error be detected in any of the tasks or\r
+co-routines. */\r
+#define mainFAIL_LED                   ( 7 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The task that displays text on the LCD.\r
+ */\r
+static void prvLCDTask( void * pvParameters );\r
+\r
+/*\r
+ * The task that sends messages to be displayed on the top row of the LCD.\r
+ */\r
+static void prvLCDMessageTask( void * pvParameters );\r
+\r
+/*\r
+ * The co-routine that reads the ADC and sends messages for display on the\r
+ * bottom row of the LCD.\r
+ */\r
+static void prvADCCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex );\r
+\r
+/*\r
+ * Function to simply set a known value into the general purpose registers\r
+ * then read them back to ensure they remain set correctly.  An incorrect value\r
+ * being indicative of an error in the task switching mechanism.\r
+ */\r
+extern void vSetAndCheckRegisters( void );\r
+\r
+/*\r
+ * Latch the LED that indicates that an error has occurred. \r
+ */\r
+void vSetErrorLED( void );\r
+\r
+/*\r
+ * Thread safe write to the PDC.\r
+ */\r
+static void prvPDCWrite( portCHAR cAddress, portCHAR cData );\r
+\r
+/*\r
+ * Sets up the hardware used by the demo.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The structure that is passed on the LCD message queue. */\r
+typedef struct\r
+{\r
+       portCHAR **ppcMessageToDisplay; /*<< Points to a char* pointing to the message to display. */\r
+       portBASE_TYPE xRow;                             /*<< The row on which the message should be displayed. */\r
+} xLCDMessage;\r
+\r
+/* Error flag set to pdFAIL if an error is encountered in the tasks/co-routines\r
+defined within this file. */\r
+unsigned portBASE_TYPE uxErrorStatus = pdPASS;\r
+\r
+/* The queue used to transmit messages to the LCD task. */\r
+static xQueueHandle xLCDQueue;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Setup the hardware, create the tasks/co-routines, then start the scheduler.\r
+ */\r
+void main( void )\r
+{\r
+       /* Create the queue used by tasks wanting to write to the LCD. */\r
+       xLCDQueue = xQueueCreate( mainLCD_QUEUE_LEN, sizeof( xLCDMessage ) );\r
+\r
+       /* Setup the ports used by the demo and the clock. */\r
+       prvSetupHardware();\r
+\r
+       /* Create the co-routines that flash the LED's. */\r
+       vStartFlashCoRoutines( mainNUM_FLASH_CO_ROUTINES );\r
+\r
+       /* Create the co-routine that initiates the transmission of characters\r
+       on the UART and the task that receives them, as described at the top of\r
+       this file. */\r
+       xCoRoutineCreate( vSerialTxCoRoutine, mainTX_CO_ROUTINE_PRIORITY, mainTX_CO_ROUTINE_INDEX );\r
+       xTaskCreate( vCommsRxTask, "CMS", configMINIMAL_STACK_SIZE, NULL, mainCOMMS_RX_TASK_PRIORITY, NULL );\r
+\r
+       /* Create the task that waits for messages to display on the LCD, plus the\r
+       task and co-routine that send messages for display (as described at the top\r
+       of this file. */\r
+       xTaskCreate( prvLCDTask, "LCD", configMINIMAL_STACK_SIZE, ( void * ) &xLCDQueue, mainLCD_TASK_PRIORITY, NULL );\r
+       xTaskCreate( prvLCDMessageTask, "MSG", configMINIMAL_STACK_SIZE, ( void * ) &xLCDQueue, mainMSG_TASK_PRIORITY, NULL );\r
+       xCoRoutineCreate( prvADCCoRoutine, mainADC_CO_ROUTINE_PRIORITY, mainADC_CO_ROUTINE_INDEX );\r
+\r
+       /* Start the scheduler running the tasks and co-routines just created. */\r
+       vTaskStartScheduler();\r
+\r
+       /* Should not get here unless we did not have enough memory to start the\r
+       scheduler. */\r
+       for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvLCDMessageTask( void * pvParameters )\r
+{\r
+/* The strings that are written to the LCD. */\r
+portCHAR *pcStringsToDisplay[] = {                                                                             \r
+                                                                       "IAR             ",\r
+                                                                       "Stellaris       ",\r
+                                                                       "Demo            ",\r
+                                                                       "www.FreeRTOS.org",\r
+                                                                       ""\r
+                                                               };\r
+\r
+xQueueHandle *pxLCDQueue;      \r
+xLCDMessage xMessageToSend;\r
+portBASE_TYPE xIndex = 0;\r
+\r
+       /* To test the parameter passing mechanism, the queue on which messages are\r
+       posted is passed in as a parameter even though it is available as a file\r
+       scope variable anyway. */\r
+       pxLCDQueue = ( xQueueHandle * ) pvParameters;\r
+\r
+       for( ;; )\r
+       {\r
+               /* Wait until it is time to move onto the next string. */\r
+               vTaskDelay( mainSTRING_WRITE_DELAY );           \r
+               \r
+               /* Create the message object to send to the LCD task. */\r
+               xMessageToSend.ppcMessageToDisplay = &pcStringsToDisplay[ xIndex ];\r
+               xMessageToSend.xRow = mainTOP_ROW;\r
+               \r
+               /* Post the message to be displayed. */\r
+               if( !xQueueSend( *pxLCDQueue, ( void * ) &xMessageToSend, 0 ) )\r
+               {\r
+                       uxErrorStatus = pdFAIL;\r
+               }\r
+               \r
+               /* Move onto the next message, wrapping when necessary. */\r
+               xIndex++;               \r
+               if( *( pcStringsToDisplay[ xIndex ] ) == 0x00 )\r
+               {\r
+                       xIndex = 0;\r
+\r
+                       /* Delay longer before going back to the start of the messages. */\r
+                       vTaskDelay( mainSTRING_WRITE_DELAY * 2 );\r
+               }\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void prvLCDTask( void * pvParameters )\r
+{\r
+unsigned portBASE_TYPE uxIndex;\r
+xQueueHandle *pxLCDQueue;\r
+xLCDMessage xReceivedMessage;\r
+portCHAR *pcString;\r
+const unsigned portCHAR ucCFGData[] = {        \r
+                                                                                       0x30,   /* Set data bus to 8-bits. */\r
+                                                                                       0x30,\r
+                                                                                       0x30,\r
+                                                                                       0x3C,   /* Number of lines/font. */\r
+                                                                                       0x08,   /* Display off. */\r
+                                                                                       0x01,   /* Display clear. */\r
+                                                                                       0x06,   /* Entry mode [cursor dir][shift]. */\r
+                                                                                       0x0C    /* Display on [display on][curson on][blinking on]. */\r
+                                                                         };  \r
+\r
+       /* To test the parameter passing mechanism, the queue on which messages are\r
+       received is passed in as a parameter even though it is available as a file\r
+       scope variable anyway. */\r
+       pxLCDQueue = ( xQueueHandle * ) pvParameters;\r
+\r
+       /* Configure the LCD. */\r
+       uxIndex = 0;\r
+       while( uxIndex < sizeof( ucCFGData ) )\r
+       {\r
+               prvPDCWrite( PDC_LCD_CSR, ucCFGData[ uxIndex ] );\r
+               uxIndex++;\r
+               vTaskDelay( mainCHAR_WRITE_DELAY );\r
+       }\r
+\r
+       /* Turn the LCD Backlight on. */\r
+       prvPDCWrite( PDC_CSR, 0x01 );\r
+\r
+       /* Clear display. */\r
+       vTaskDelay( mainCHAR_WRITE_DELAY );\r
+       prvPDCWrite( PDC_LCD_CSR, LCD_CLEAR ); \r
+\r
+       uxIndex = 0;\r
+       for( ;; )    \r
+       {\r
+               /* Wait for a message to arrive. */\r
+               if( xQueueReceive( *pxLCDQueue, &xReceivedMessage, portMAX_DELAY ) )\r
+               {\r
+                       /* Which row does the received message say to write to? */\r
+                       PDCLCDSetPos( 0, xReceivedMessage.xRow );\r
+\r
+                       /* Where is the string we are going to display? */\r
+                       pcString = *xReceivedMessage.ppcMessageToDisplay;\r
+                       \r
+                       while( *pcString )\r
+                       {\r
+                               /* Don't write out the string too quickly as LCD's are usually \r
+                               pretty slow devices. */\r
+                               vTaskDelay( mainCHAR_WRITE_DELAY );\r
+                               prvPDCWrite( PDC_LCD_RAM, *pcString );\r
+                               pcString++;\r
+                       }               \r
+               }\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvADCCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+{\r
+static unsigned portLONG ulADCValue;\r
+static portCHAR cMessageBuffer[ mainMAX_ADC_STRING_LEN ];\r
+static portCHAR *pcMessage;\r
+static xLCDMessage xMessageToSend;\r
+\r
+       /* Co-routines MUST start with a call to crSTART(). */\r
+       crSTART( xHandle );\r
+       \r
+       for( ;; )\r
+       {\r
+               /* Start an ADC conversion. */\r
+               ADCProcessorTrigger( ADC_BASE, 0 );\r
+               \r
+               /* Simply delay - when we unblock the result should be available */     \r
+               crDELAY( xHandle, mainADC_DELAY );\r
+               \r
+               /* Get the ADC result. */\r
+               ADCSequenceDataGet( ADC_BASE, 0, &ulADCValue );\r
+\r
+               /* Create a string with the result. */          \r
+               sprintf( cMessageBuffer, "ADC = %d   ", ulADCValue );\r
+               pcMessage = cMessageBuffer;\r
+\r
+               /* Configure the message we are going to send for display. */\r
+               xMessageToSend.ppcMessageToDisplay = ( portCHAR** ) &pcMessage;\r
+               xMessageToSend.xRow = mainBOTTOM_ROW;\r
+               \r
+               /* Send the string to the LCD task for display.  We are sending\r
+               on a task queue so do not have the option to block. */\r
+               if( !xQueueSend( xLCDQueue, ( void * ) &xMessageToSend, 0 ) )\r
+               {\r
+                       uxErrorStatus = pdFAIL;\r
+               }               \r
+       }\r
+       \r
+       /* Co-routines MUST end with a call to crEND(). */\r
+       crEND();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+       /* Setup the PLL. */\r
+       SysCtlClockSet( SYSCTL_SYSDIV_10 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ );\r
+       \r
+       /* Initialise the hardware used to talk to the LCD, LED's and UART. */\r
+       PDCInit();\r
+       vParTestInitialise();\r
+       vSerialInit();\r
+\r
+       /* The ADC is used to read the light sensor. */\r
+       SysCtlPeripheralEnable( SYSCTL_PERIPH_ADC );\r
+    ADCSequenceConfigure( ADC_BASE, 3, ADC_TRIGGER_PROCESSOR, 0);\r
+    ADCSequenceStepConfigure( ADC_BASE, 0, 0, ADC_CTL_CH0 | ADC_CTL_END );\r
+    ADCSequenceEnable( ADC_BASE, 0 );\r
+\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvPDCWrite( portCHAR cAddress, portCHAR cData )\r
+{\r
+       vTaskSuspendAll();\r
+       {\r
+               PDCWrite( cAddress, cData );\r
+       }\r
+       xTaskResumeAll();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vSetErrorLED( void )\r
+{\r
+       vParTestSetLED( mainFAIL_LED, pdTRUE );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+       /* The co-routines are executed in the idle task using the idle task \r
+       hook. */\r
+       for( ;; )\r
+       {\r
+               /* Schedule the co-routines. */\r
+               vCoRoutineSchedule();\r
+\r
+               /* Run the register check function between each co-routine. */\r
+               vSetAndCheckRegisters();\r
+               \r
+               /* See if the comms task and co-routine has found any errors. */\r
+               if( uxGetCommsStatus() != pdPASS )\r
+               {\r
+                       vParTestSetLED( mainFAIL_LED, pdTRUE );\r
+               }\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
diff --git a/Demo/CORTEX_LM3S316_IAR/registertest.s b/Demo/CORTEX_LM3S316_IAR/registertest.s

new file mode 100644 (file)

index 0000000..7f27b5f
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/registertest.s
@@ -0,0 +1,60 @@
+       RSEG ICODE:CODE\r
+\r
+       EXTERN vSetErrorLED\r
+\r
+       PUBLIC vSetAndCheckRegisters\r
+\r
+vSetAndCheckRegisters:\r
+       /* Fill the general purpose registers with known values. */\r
+       mov r11, #10\r
+       add r0, r11, #1\r
+       add r1, r11, #2\r
+       add r2, r11, #3\r
+       add r3, r11, #4\r
+       add r4, r11, #5\r
+       add r5, r11, #6\r
+       add r6, r11, #7\r
+       add r7, r11, #8\r
+       add r8, r11, #9\r
+       add r9, r11, #10\r
+       add r10, r11, #11\r
+       add r12, r11, #12\r
+\r
+       /* Check the values are as expected. */\r
+       cmp r11, #10\r
+       bne set_error_led\r
+       cmp r0, #11\r
+       bne set_error_led\r
+       cmp r1, #12\r
+       bne set_error_led\r
+       cmp r2, #13\r
+       bne set_error_led\r
+       cmp r3, #14\r
+       bne set_error_led\r
+       cmp r4, #15\r
+       bne set_error_led\r
+       cmp r5, #16\r
+       bne set_error_led\r
+       cmp r6, #17\r
+       bne set_error_led\r
+       cmp r7, #18\r
+       bne set_error_led\r
+       cmp r8, #19\r
+       bne set_error_led\r
+       cmp r9, #20\r
+       bne set_error_led\r
+       cmp r10, #21\r
+       bne set_error_led\r
+       cmp r12, #22\r
+       bne set_error_led\r
+       bx lr\r
+\r
+set_error_led:\r
+       push {r14}\r
+       ldr r1, =vSetErrorLED\r
+       blx r1\r
+       pop {r14}\r
+       bx lr\r
+\r
+       END\r
+       \r
diff --git a/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.dbgdt b/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.dbgdt

new file mode 100644 (file)

index 0000000..f583dfc
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.dbgdt
@@ -0,0 +1,65 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<Project>\r
+  <Desktop>\r
+    <Static>\r
+      <Debug-Log><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows></Debug-Log>\r
+      <Workspace>\r
+        <ColumnWidths>\r
+          \r
+          \r
+          \r
+          \r
+        <Column0>274</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
+      </Workspace>\r
+      <Disassembly>\r
+        <PreferedWindows>\r
+          \r
+          \r
+          \r
+          \r
+        <Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows>\r
+        \r
+        \r
+        \r
+      <MixedMode>1</MixedMode><CodeCovEnabled>0</CodeCovEnabled><CodeCovShow>0</CodeCovShow></Disassembly>\r
+      <Build>\r
+        <ColumnWidth0>20</ColumnWidth0>\r
+        <ColumnWidth1>1004</ColumnWidth1>\r
+        <ColumnWidth2>267</ColumnWidth2>\r
+        <ColumnWidth3>66</ColumnWidth3>\r
+      <PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows><Window><Factory>Debug-Log</Factory></Window><Window><Factory>Breakpoints</Factory></Window></Windows></PreferedWindows></Build>\r
+    <Watch><Format><struct_types/><watch_formats/></Format><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><Column0>112</Column0><Column1>103</Column1><Column2>100</Column2><Column3>100</Column3></Watch><Register><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows></Register><QuickWatch><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><Column0>140</Column0><Column1>100</Column1><Column2>100</Column2><Column3>100</Column3></QuickWatch><Memory><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><FindDirection>1</FindDirection><FindAsHex>0</FindAsHex></Memory><Breakpoints><PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows><Window><Factory>Debug-Log</Factory></Window><Window><Factory>Build</Factory></Window></Windows></PreferedWindows></Breakpoints><STACK2><PreferedWindows><Position>1</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows></STACK2><CallStack><PreferedWindows><Position>1</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><ViewArgs>1</ViewArgs></CallStack></Static>\r
+    <Windows>\r
+      \r
+      \r
+    <Wnd2>\r
+        <Tabs>\r
+          <Tab>\r
+            <Identity>TabID-30594-29847</Identity>\r
+            <TabName>Workspace</TabName>\r
+            <Factory>Workspace</Factory>\r
+            <Session>\r
+              \r
+            <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/FreeRTOS Source</ExpandedNode><ExpandedNode>RTOSDemo/FreeRTOS Source/croutine.c</ExpandedNode></NodeDict></Session>\r
+          </Tab>\r
+        </Tabs>\r
+        \r
+      <SelectedTab>0</SelectedTab></Wnd2><Wnd3><Tabs><Tab><Identity>TabID-30273-20034</Identity><TabName>Debug Log</TabName><Factory>Debug-Log</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd3></Windows>\r
+    <Editor>\r
+      \r
+      \r
+      \r
+      \r
+    <Pane><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\main.c</Filename><XPos>0</XPos><YPos>182</YPos><SelStart>7817</SelStart><SelEnd>7817</SelEnd></Tab><ActiveTab>0</ActiveTab><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\FreeRTOSConfig.h</Filename><XPos>0</XPos><YPos>21</YPos><SelStart>1991</SelStart><SelEnd>1991</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\hw_include\startup.c</Filename><XPos>0</XPos><YPos>254</YPos><SelStart>9644</SelStart><SelEnd>9644</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\Source\tasks.c</Filename><XPos>0</XPos><YPos>733</YPos><SelStart>26424</SelStart><SelEnd>26424</SelEnd></Tab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>\r
+    <Positions>\r
+      \r
+      \r
+      \r
+      \r
+      \r
+    <Top><Row0><Sizes><Toolbar-00a0baa0><key>iaridepm1</key></Toolbar-00a0baa0><Toolbar-023fb418><key>debuggergui1</key></Toolbar-023fb418></Sizes></Row0></Top><Left><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>728</Bottom><Right>348</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>142857</sizeHorzCX><sizeHorzCY>205761</sizeHorzCY><sizeVertCX>250000</sizeVertCX><sizeVertCY>751029</sizeVertCY></Rect></Wnd2></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1402</Right><x>-2</x><y>-2</y><xscreen>1404</xscreen><yscreen>200</yscreen><sizeHorzCX>1002857</sizeHorzCX><sizeHorzCY>205761</sizeHorzCY><sizeVertCX>142857</sizeVertCX><sizeVertCY>205761</sizeVertCY></Rect></Wnd3></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
+  </Desktop>\r
+</Project>\r
+\r
+\r
diff --git a/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.dni b/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.dni

new file mode 100644 (file)

index 0000000..15689c4
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.dni
@@ -0,0 +1,32 @@
+[JLinkDriver]\r
+WatchCond=_ 0\r
+Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0\r
+Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0\r
+[DisAssemblyWindow]\r
+NumStates=_ 1\r
+State 1=_ 1\r
+[StackPlugin]\r
+Enabled=1\r
+OverflowWarningsEnabled=1\r
+WarningThreshold=90\r
+SpWarningsEnabled=1\r
+WarnHow=0\r
+UseTrigger=1\r
+TriggerName=main\r
+LimitSize=0\r
+ByteLimit=50\r
+[Log file]\r
+LoggingEnabled=_ 0\r
+LogFile=_ ""\r
+Category=_ 0\r
+[TermIOLog]\r
+LoggingEnabled=_ 0\r
+LogFile=_ ""\r
+[Disassemble mode]\r
+mode=1\r
+[Breakpoints]\r
+Bp0=_ "Log" "Memory8:0x20000850" 0 0 0 0 "" 0 "" 0\r
+Count=1\r
+[TraceHelper]\r
+Enabled=0\r
+ShowSource=1\r
diff --git a/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.wsdt b/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.wsdt

new file mode 100644 (file)

index 0000000..0642cf6
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.wsdt
@@ -0,0 +1,58 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<Workspace>\r
+  <ConfigDictionary>\r
+    \r
+  <CurrentConfigs><Project>RTOSDemo/Debug</Project></CurrentConfigs></ConfigDictionary>\r
+  <Desktop>\r
+    <Static>\r
+      <Workspace>\r
+        <ColumnWidths>\r
+          \r
+          \r
+          \r
+          \r
+        <Column0>186</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
+      </Workspace>\r
+      <Build>\r
+        \r
+        \r
+        \r
+        \r
+      <PreferedWindows><Position>3</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows><ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1004</ColumnWidth1><ColumnWidth2>267</ColumnWidth2><ColumnWidth3>66</ColumnWidth3></Build>\r
+      <TerminalIO/>\r
+      <Profiling/>\r
+    <Debug-Log/></Static>\r
+    <Windows>\r
+      \r
+      \r
+    <Wnd2>\r
+        <Tabs>\r
+          <Tab>\r
+            <Identity>TabID-2928-28933</Identity>\r
+            <TabName>Workspace</TabName>\r
+            <Factory>Workspace</Factory>\r
+            <Session>\r
+              \r
+            <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/Demo Source</ExpandedNode></NodeDict></Session>\r
+          </Tab>\r
+        </Tabs>\r
+        \r
+      <SelectedTab>0</SelectedTab></Wnd2><Wnd3><Tabs><Tab><Identity>TabID-24894-24921</Identity><TabName>Build</TabName><Factory>Build</Factory><Session/></Tab><Tab><Identity>TabID-10790-31422</Identity><TabName>Debug Log</TabName><Factory>Debug-Log</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd3></Windows>\r
+    <Editor>\r
+      \r
+      \r
+      \r
+      \r
+    <Pane><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\main.c</Filename><XPos>0</XPos><YPos>182</YPos><SelStart>7817</SelStart><SelEnd>7817</SelEnd></Tab><ActiveTab>0</ActiveTab><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\FreeRTOSConfig.h</Filename><XPos>0</XPos><YPos>21</YPos><SelStart>1991</SelStart><SelEnd>1991</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\hw_include\startup.c</Filename><XPos>0</XPos><YPos>254</YPos><SelStart>9644</SelStart><SelEnd>9644</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\Source\tasks.c</Filename><XPos>0</XPos><YPos>733</YPos><SelStart>26424</SelStart><SelEnd>26424</SelEnd></Tab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>\r
+    <Positions>\r
+      \r
+      \r
+      \r
+      \r
+      \r
+    <Top><Row0><Sizes><Toolbar-00a0baa0><key>iaridepm1</key></Toolbar-00a0baa0></Sizes></Row0><Row1><Sizes/></Row1></Top><Left><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>728</Bottom><Right>260</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>142857</sizeHorzCX><sizeHorzCY>205761</sizeHorzCY><sizeVertCX>187143</sizeVertCX><sizeVertCY>751029</sizeVertCY></Rect></Wnd2></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1402</Right><x>-2</x><y>-2</y><xscreen>1404</xscreen><yscreen>200</yscreen><sizeHorzCX>1002857</sizeHorzCX><sizeHorzCY>205761</sizeHorzCY><sizeVertCX>142857</sizeVertCX><sizeVertCY>205761</sizeVertCY></Rect></Wnd3></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
+  </Desktop>\r
+</Workspace>\r
+\r
+\r
diff --git a/Demo/CORTEX_LM3S316_IAR/settings/driverlib.wsdt b/Demo/CORTEX_LM3S316_IAR/settings/driverlib.wsdt

new file mode 100644 (file)

index 0000000..6deb801
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/settings/driverlib.wsdt
@@ -0,0 +1,51 @@
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<Workspace>\r
+  <ConfigDictionary>\r
+    \r
+    \r
+    \r
+  <CurrentConfigs><Project>qs_dk-lm3s316/Debug</Project></CurrentConfigs></ConfigDictionary>\r
+  <Desktop>\r
+    <Static>\r
+      <Workspace>\r
+        <ColumnWidths>\r
+          \r
+          \r
+          \r
+          \r
+        <Column0>253</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
+      </Workspace>\r
+    <Build><ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1004</ColumnWidth1><ColumnWidth2>267</ColumnWidth2><ColumnWidth3>66</ColumnWidth3></Build><TerminalIO/><Debug-Log/><Profiling/></Static>\r
+    <Windows>\r
+      \r
+    <Wnd0>\r
+        <Tabs>\r
+          <Tab>\r
+            <Identity>TabID-9985-21059</Identity>\r
+            <TabName>Workspace</TabName>\r
+            <Factory>Workspace</Factory>\r
+            <Session>\r
+              \r
+            <NodeDict/></Session>\r
+          </Tab>\r
+        </Tabs>\r
+        \r
+      <SelectedTab>0</SelectedTab></Wnd0><Wnd1><Tabs><Tab><Identity>TabID-31963-22489</Identity><TabName>Build</TabName><Factory>Build</Factory><Session/></Tab><Tab><Identity>TabID-12860-23630</Identity><TabName>Debug Log</TabName><Factory>Debug-Log</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd1></Windows>\r
+    <Editor>\r
+      \r
+      \r
+      \r
+      \r
+    <Pane><Tab><Factory>TextEditor</Factory><Filename>C:\Devtools\IAR Systems\Embedded Workbench 4.0\ARM\examples\Luminary\DK-LM3Sxxx\utils\cspy.c</Filename><XPos>0</XPos><YPos>42</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\Devtools\IAR Systems\Embedded Workbench 4.0\ARM\examples\Luminary\DK-LM3Sxxx\examples\qs_dk-lm3s102\startup.c</Filename><XPos>0</XPos><YPos>39</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\examples\qs_dk-lm3s101\qs_dk-lm3s101.c</Filename><XPos>0</XPos><YPos>284</YPos><SelStart>10179</SelStart><SelEnd>10179</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\utils\pdc.c</Filename><XPos>0</XPos><YPos>6</YPos><SelStart>1540</SelStart><SelEnd>1540</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\watchdog.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>1473</SelStart><SelEnd>1480</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\uart.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>1514</SelStart><SelEnd>1514</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\timer.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>1524</SelStart><SelEnd>1524</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\systick.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>1513</SelStart><SelEnd>1513</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\sysctl.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>1553</SelStart><SelEnd>1553</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\ssi.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>1530</SelStart><SelEnd>1530</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\pwm.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>1513</SelStart><SelEnd>1513</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\interrupt.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>1521</SelStart><SelEnd>1521</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\i2c.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>1526</SelStart><SelEnd>1526</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\gpio.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>1511</SelStart><SelEnd>1511</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\flash.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>1560</SelStart><SelEnd>1560</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\comp.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>1526</SelStart><SelEnd>1526</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\src\adc.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>1509</SelStart><SelEnd>1509</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\examples\qs_dk-lm3s316\qs_dk-lm3s316.c</Filename><XPos>0</XPos><YPos>572</YPos><SelStart>12923</SelStart><SelEnd>12923</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>C:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\utils\cspy.c</Filename><XPos>0</XPos><YPos>39</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd></Tab><ActiveTab>18</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>\r
+    <Positions>\r
+      \r
+      \r
+      \r
+      \r
+      \r
+    <Top><Row0><Sizes><Toolbar-00a0baa0><key>iaridepm1</key></Toolbar-00a0baa0></Sizes></Row0></Top><Left><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>728</Bottom><Right>327</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>142857</sizeHorzCX><sizeHorzCY>205761</sizeHorzCY><sizeVertCX>235000</sizeVertCX><sizeVertCY>751029</sizeVertCY></Rect></Wnd0></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1402</Right><x>-2</x><y>-2</y><xscreen>1404</xscreen><yscreen>200</yscreen><sizeHorzCX>1002857</sizeHorzCX><sizeHorzCY>205761</sizeHorzCY><sizeVertCX>142857</sizeVertCX><sizeVertCY>205761</sizeVertCY></Rect></Wnd1></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
+  </Desktop>\r
+</Workspace>\r
+\r
+\r
diff --git a/Demo/CORTEX_LM3S316_IAR/standalone.xcl b/Demo/CORTEX_LM3S316_IAR/standalone.xcl

new file mode 100644 (file)

index 0000000..fdd107a
--- /dev/null
+++ b/Demo/CORTEX_LM3S316_IAR/standalone.xcl
@@ -0,0 +1,37 @@
+//*****************************************************************************\r
+//\r
+// standalone.xcl - Linker script for EW-ARM.\r
+//\r
+// Copyright (c) 2006 Luminary Micro, Inc.  All rights reserved.\r
+//\r
+//*****************************************************************************\r
+\r
+//\r
+// Set the CPU type to ARM.\r
+//\r
+-carm\r
+\r
+//\r
+// Define the size of flash and SRAM.\r
+//\r
+-DROMSTART=00000000\r
+-DROMEND=0000FFFF\r
+-DRAMSTART=20000000\r
+-DRAMEND=20001FFF\r
+\r
+//\r
+// Define the sections to place into flash, and the order to place them.\r
+//\r
+-Z(CODE)INTVEC=ROMSTART-ROMEND\r
+-Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND\r
+-Z(CODE)CODE=ROMSTART-ROMEND\r
+-Z(CONST)CODE_ID=ROMSTART-ROMEND\r
+-Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND\r
+-Z(CONST)CHECKSUM=ROMSTART-ROMEND\r
+\r
+//\r
+// Define the sections to place into SRAM, and the order to place them.\r
+//\r
+-Z(DATA)VTABLE=RAMSTART-RAMEND\r
+-Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND\r
+-Z(DATA)CODE_I=RAMSTART-RAMEND\r
diff --git a/Demo/Common/Full/BlockQ.c b/Demo/Common/Full/BlockQ.c

index 340bfd88089edbd260228f332b2776e355e9b43c..d9aa67b82e9a4f2f216c526e7c3407be6e465d73 100644 (file)
--- a/Demo/Common/Full/BlockQ.c
+++ b/Demo/Common/Full/BlockQ.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
@@ -67,6 +67,11 @@ Changes from V2.0.0
  \r
         + Delay periods are now specified using variables and constants of\r
           portTickType rather than unsigned portLONG.\r
+\r
+Changes from V4.0.2\r
+\r
+       + The second set of tasks were created the wrong way around.  This has been\r
+         corrected.\r
  */\r
  \r
  \r
diff --git a/Demo/Common/Full/PollQ.c b/Demo/Common/Full/PollQ.c

index bfc81b31e45a829ca80e0f07b213c877b881c1cf..25fe7cf7eb6653d4d24522fc0659bb3e051af5b9 100644 (file)
--- a/Demo/Common/Full/PollQ.c
+++ b/Demo/Common/Full/PollQ.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/Full/comtest.c b/Demo/Common/Full/comtest.c

index 9000391a2cbfe5b074d94ee77bc6e94d526fb9a4..7face8d3837080b6fb92455193c465a7a6f31e48 100644 (file)
--- a/Demo/Common/Full/comtest.c
+++ b/Demo/Common/Full/comtest.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/Full/death.c b/Demo/Common/Full/death.c

index 4b12d707961b370f9a8099686abfeb66de0b1d2e..27caeaa39895f2db60e5b55660f89a71e6f3fd23 100644 (file)
--- a/Demo/Common/Full/death.c
+++ b/Demo/Common/Full/death.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/Full/dynamic.c b/Demo/Common/Full/dynamic.c

index f07007b7c101ac64a6847ca4dc4ca869e46aa111..e55f68c3cfee3ac4c42e82b4876b5dab18a14f71 100644 (file)
--- a/Demo/Common/Full/dynamic.c
+++ b/Demo/Common/Full/dynamic.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/Full/events.c b/Demo/Common/Full/events.c

index d613c26b02524a9966a6283b9e076848cbafd206..69df711be83bb0b9d13a2742ad7e4766af17d344 100644 (file)
--- a/Demo/Common/Full/events.c
+++ b/Demo/Common/Full/events.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/Full/flash.c b/Demo/Common/Full/flash.c

index 5ab3d27414534f52427c6de3d54037136386f95c..9b03407168a02f674a3acc4d232e1ae311d7d801 100644 (file)
--- a/Demo/Common/Full/flash.c
+++ b/Demo/Common/Full/flash.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/Full/flop.c b/Demo/Common/Full/flop.c

index 41878c28f13d621b27943cbce4da6ebea837e445..7b5c216641da3f305b5476cefc5702d907e9c9cd 100644 (file)
--- a/Demo/Common/Full/flop.c
+++ b/Demo/Common/Full/flop.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/Full/integer.c b/Demo/Common/Full/integer.c

index ef1a7c95bbae2a21af32082dcc215f431b839fbb..fd12111ef79292a8fc492cd56d421b646975a7b8 100644 (file)
--- a/Demo/Common/Full/integer.c
+++ b/Demo/Common/Full/integer.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/Full/print.c b/Demo/Common/Full/print.c

index 3c78c7770c5d637b62496038833f3ee1b1abc088..10a90707283e1642fadfd3baa36e455f52422248 100644 (file)
--- a/Demo/Common/Full/print.c
+++ b/Demo/Common/Full/print.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/Full/semtest.c b/Demo/Common/Full/semtest.c

index 074ba4ee80aa5dc081b9060997308afeb033e12c..c4c8f9a8a920aeeb4bb948e034b524d52c3955f2 100644 (file)
--- a/Demo/Common/Full/semtest.c
+++ b/Demo/Common/Full/semtest.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/Minimal/BlockQ.c b/Demo/Common/Minimal/BlockQ.c

index b118376b81dce969d81475267ba8b6e2777a11ee..bf08121f39e556bb4617bede7402fe0fe3c69531 100644 (file)
--- a/Demo/Common/Minimal/BlockQ.c
+++ b/Demo/Common/Minimal/BlockQ.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
@@ -54,6 +54,13 @@
   *\r
   */\r
  \r
+/* \r
+\r
+Changes from V4.0.2\r
+\r
+       + The second set of tasks were created the wrong way around.  This has been\r
+         corrected.\r
+*/\r
  \r
  \r
  #include <stdlib.h>\r
diff --git a/Demo/Common/Minimal/PollQ.c b/Demo/Common/Minimal/PollQ.c

index e27a12890c2087d24dad3c935640e10b5f9dc231..5741873e42642cf12e893777f40e1b3c05c555e4 100644 (file)
--- a/Demo/Common/Minimal/PollQ.c
+++ b/Demo/Common/Minimal/PollQ.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/Minimal/comtest.c b/Demo/Common/Minimal/comtest.c

index 8933d9f5b7ee6190dc54ee6a766b9fb55673145a..a9268776dce1ca680bf58819268e1be2a4bbe3cc 100644 (file)
--- a/Demo/Common/Minimal/comtest.c
+++ b/Demo/Common/Minimal/comtest.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/Minimal/crflash.c b/Demo/Common/Minimal/crflash.c

index 3927c6fd1b7a7991efbdc68b88c4368c88ea93ce..d3a580e0bfb76ca5be71c5585b246cb1bfac9338 100644 (file)
--- a/Demo/Common/Minimal/crflash.c
+++ b/Demo/Common/Minimal/crflash.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/Minimal/crhook.c b/Demo/Common/Minimal/crhook.c

index fc31a23f1bac24d7ef0127081a59cf7c361bcabb..70df10a216d7f2a1e605aed786c704545aa9184e 100644 (file)
--- a/Demo/Common/Minimal/crhook.c
+++ b/Demo/Common/Minimal/crhook.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/Minimal/death.c b/Demo/Common/Minimal/death.c

index bdc2cdcfcd888b139118d6608058a82e099599e0..9c6180031b3b03178cf98becf469d39b7f291564 100644 (file)
--- a/Demo/Common/Minimal/death.c
+++ b/Demo/Common/Minimal/death.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/Minimal/dynamic.c b/Demo/Common/Minimal/dynamic.c

index 57816b33b3b107964bfa740dbad69754f46db7a5..c2dadf9640afe264db4a1df94598e11641c6e993 100644 (file)
--- a/Demo/Common/Minimal/dynamic.c
+++ b/Demo/Common/Minimal/dynamic.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/Minimal/flash.c b/Demo/Common/Minimal/flash.c

index 46905be599452b905d7d63927b0e03713a2c9228..874fb0a52072c456adb93dac9753382c4804ed18 100644 (file)
--- a/Demo/Common/Minimal/flash.c
+++ b/Demo/Common/Minimal/flash.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/Minimal/flop.c b/Demo/Common/Minimal/flop.c

index ab3a949bfd23c757b368fb24a3dff23814223963..c3a066569044d04170009422135650a32ca4aa22 100644 (file)
--- a/Demo/Common/Minimal/flop.c
+++ b/Demo/Common/Minimal/flop.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/Minimal/integer.c b/Demo/Common/Minimal/integer.c

index 898c9e769426738d3016d587ab5aa3fb586fd5e5..88cc5942d40d31350ae0e67b7c51840b2d6ee9a6 100644 (file)
--- a/Demo/Common/Minimal/integer.c
+++ b/Demo/Common/Minimal/integer.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/Minimal/semtest.c b/Demo/Common/Minimal/semtest.c

index bceba4091aa3cec4b5d9f813c16c18e99acbca34..145f03a8f580b0e4037057d7a88a073276567418 100644 (file)
--- a/Demo/Common/Minimal/semtest.c
+++ b/Demo/Common/Minimal/semtest.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/include/BlockQ.h b/Demo/Common/include/BlockQ.h

index 32f86dced36d6d7aed1eef6ff7a6cdc4574db407..26c4c35e512e0edecd37aa4575c9840335d10396 100644 (file)
--- a/Demo/Common/include/BlockQ.h
+++ b/Demo/Common/include/BlockQ.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/include/PollQ.h b/Demo/Common/include/PollQ.h

index b1e4bf4b44a705216c86d2c24ed9d8ae05f518b1..6896e3d98f8128cc6f7d4d25a299ad6a24b4a5a4 100644 (file)
--- a/Demo/Common/include/PollQ.h
+++ b/Demo/Common/include/PollQ.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/include/comtest.h b/Demo/Common/include/comtest.h

index 43baf6897324520a7a4d65e808e3853bb0b5c94f..8e8200ca5b14073a9d687ab220a75c11cae3d7f7 100644 (file)
--- a/Demo/Common/include/comtest.h
+++ b/Demo/Common/include/comtest.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/include/comtest2.h b/Demo/Common/include/comtest2.h

index 563448d06f630c992c15b5b482ea3176a4881278..96132510443757b03ed47779684516b3a3aa3fc0 100644 (file)
--- a/Demo/Common/include/comtest2.h
+++ b/Demo/Common/include/comtest2.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/include/crflash.h b/Demo/Common/include/crflash.h

index 7188bee263eed7a24916b3114261c373d428f625..a8f5b3e2091b4bf5ac5a90b6f847ddb40733b0fb 100644 (file)
--- a/Demo/Common/include/crflash.h
+++ b/Demo/Common/include/crflash.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/include/crhook.h b/Demo/Common/include/crhook.h

index 28f956d65d8d1f8a1fcbbee586cba31afb19e09c..d6c837476b62bb170b8e5a773f8d2e287173573f 100644 (file)
--- a/Demo/Common/include/crhook.h
+++ b/Demo/Common/include/crhook.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/include/death.h b/Demo/Common/include/death.h

index ed8e65d3e7e79d6841c16dea70bcc22738b9a6cb..455bcfec56708024f44eeedaad7e11d327100539 100644 (file)
--- a/Demo/Common/include/death.h
+++ b/Demo/Common/include/death.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/include/dynamic.h b/Demo/Common/include/dynamic.h

index f8068a3bb40e016e5a3cd0a198bbeee638559570..8e45a77cba330ae5fa7882f3fea9d6afe671f611 100644 (file)
--- a/Demo/Common/include/dynamic.h
+++ b/Demo/Common/include/dynamic.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/include/fileIO.h b/Demo/Common/include/fileIO.h

index 6e154a7ed5ad347c13708c6816cba8881cdee25e..a0f4324429594b84a1f28af5fe4faf52a9b251e4 100644 (file)
--- a/Demo/Common/include/fileIO.h
+++ b/Demo/Common/include/fileIO.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/include/flash.h b/Demo/Common/include/flash.h

index 81559f56ecb63c94909ba5374c302420ce267b9e..c97daff95c8d7b3dec20172fc5b987587c280fb7 100644 (file)
--- a/Demo/Common/include/flash.h
+++ b/Demo/Common/include/flash.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/include/flop.h b/Demo/Common/include/flop.h

index 80fe9c3d22058373361a06d5175f6158a206deda..e6ca7fa553562b68828397aaba164f09b85d95c7 100644 (file)
--- a/Demo/Common/include/flop.h
+++ b/Demo/Common/include/flop.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/include/integer.h b/Demo/Common/include/integer.h

index 563a29dbf4e5da0adb1d5a2a5f184ba4065250ed..8e5040b2b08ccd1364350e06a9550e06968d1e11 100644 (file)
--- a/Demo/Common/include/integer.h
+++ b/Demo/Common/include/integer.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/include/mevents.h b/Demo/Common/include/mevents.h

index c5711bab605b1d9dced08ffbe344dc7dba8a461d..0044493f1a77bf13685ff418433be96e87c2c7f6 100644 (file)
--- a/Demo/Common/include/mevents.h
+++ b/Demo/Common/include/mevents.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/include/partest.h b/Demo/Common/include/partest.h

index f3b08c786bc897c10a290940e01c9a89de3745f8..41e6a2e98aa9286ad74285956b039a393502fd4e 100644 (file)
--- a/Demo/Common/include/partest.h
+++ b/Demo/Common/include/partest.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/include/print.h b/Demo/Common/include/print.h

index 612ee8ec531bacd9b168deb1ace2a4ea904e1a11..c3a16a7c576ee40d80912cee1175acd90ed59fff 100644 (file)
--- a/Demo/Common/include/print.h
+++ b/Demo/Common/include/print.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/include/semtest.h b/Demo/Common/include/semtest.h

index e3e31ee83446ef4cd11cb59904aabe7df35f46c7..51bd28136c89418a4530079e87403bbc2a22a6c4 100644 (file)
--- a/Demo/Common/include/semtest.h
+++ b/Demo/Common/include/semtest.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Common/include/serial.h b/Demo/Common/include/serial.h

index eb37d9e628a0d02e19ba8e983e304965a6ad157e..59e63a32bd2c52c99964c98ffc6386a2e683f938 100644 (file)
--- a/Demo/Common/include/serial.h
+++ b/Demo/Common/include/serial.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Cygnal/FreeRTOSConfig.h b/Demo/Cygnal/FreeRTOSConfig.h

index af7c0f2b635703ea8d1b1db554c0a63fca404b5c..2b5c3d133a1e6f1b66b9a7ef36cbe1fe1703e4e3 100644 (file)
--- a/Demo/Cygnal/FreeRTOSConfig.h
+++ b/Demo/Cygnal/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Cygnal/Makefile b/Demo/Cygnal/Makefile

index 127ecfffa936592416b99df22770ad4e8fcb4d5b..cdcea11f1307bd3ffd04629f37a81b5403ca469c 100644 (file)
--- a/Demo/Cygnal/Makefile
+++ b/Demo/Cygnal/Makefile
@@ -1,4 +1,4 @@
-#      FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+#      FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  #\r
  #      This file is part of the FreeRTOS.org distribution.\r
  #\r
diff --git a/Demo/Cygnal/ParTest/ParTest.c b/Demo/Cygnal/ParTest/ParTest.c

index 94acf7fa51a07c7adef05c281e5dfa94fb2a6791..1b0b53253e1d55461ef8d65af55e658ad6c786c3 100644 (file)
--- a/Demo/Cygnal/ParTest/ParTest.c
+++ b/Demo/Cygnal/ParTest/ParTest.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Cygnal/main.c b/Demo/Cygnal/main.c

index 38f0971b575658ce0e18052304a6cc00cd4dba64..c9ee2d6412b709d7da5b6690b79cfa57d5c53cda 100644 (file)
--- a/Demo/Cygnal/main.c
+++ b/Demo/Cygnal/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Cygnal/serial/serial.c b/Demo/Cygnal/serial/serial.c

index d401d42f8d90065a95827c823bb043cf4567538e..70c37e63f3ca2c28046fa60e777875b6a18fda0b 100644 (file)
--- a/Demo/Cygnal/serial/serial.c
+++ b/Demo/Cygnal/serial/serial.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Flshlite/FRConfig.h b/Demo/Flshlite/FRConfig.h

index 2a93271f10e3325d1d180d2212cea2529648d9d8..59eba9ec7dde349d2d4ceaa1219c1968458e8fef 100644 (file)
--- a/Demo/Flshlite/FRConfig.h
+++ b/Demo/Flshlite/FRConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Flshlite/FileIO/fileIO.c b/Demo/Flshlite/FileIO/fileIO.c

index e51d44ee736c46a5c6c6f95c8f36511f69567835..663b0e92bd697657d9b8cefb4b9a9db4408acd88 100644 (file)
--- a/Demo/Flshlite/FileIO/fileIO.c
+++ b/Demo/Flshlite/FileIO/fileIO.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Flshlite/FreeRTOSConfig.h b/Demo/Flshlite/FreeRTOSConfig.h

index 4870fb59a1cdab5dd463e241a8d777c38fc3093d..ddcc0fe6c33b20b0d7db5b2d06ae8d5c2e67bd33 100644 (file)
--- a/Demo/Flshlite/FreeRTOSConfig.h
+++ b/Demo/Flshlite/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Flshlite/ParTest/ParTest.c b/Demo/Flshlite/ParTest/ParTest.c

index 9dae6fe6ec7c7321f6480ab15383db757cb8d665..a1611c3e577948aff74460fb7e62babbe10d0658 100644 (file)
--- a/Demo/Flshlite/ParTest/ParTest.c
+++ b/Demo/Flshlite/ParTest/ParTest.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Flshlite/main.c b/Demo/Flshlite/main.c

index f4bc04f4a243295fedb4ab9b574765570a7426db..4f73bde6cccbc5eb3d8e256df04d44f4c799b39d 100644 (file)
--- a/Demo/Flshlite/main.c
+++ b/Demo/Flshlite/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/Flshlite/serial/serial.c b/Demo/Flshlite/serial/serial.c

index 1b43cd84803d79203efe046c2f5862571afb2498..30c162aa45d7e0862d9c29b8edef36d242dca6e7 100644 (file)
--- a/Demo/Flshlite/serial/serial.c
+++ b/Demo/Flshlite/serial/serial.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/H8S/RTOSDemo/FreeRTOSConfig.h b/Demo/H8S/RTOSDemo/FreeRTOSConfig.h

index 8e38499e46846f8d52e046c4cb838db23d63d6aa..b30a3c8f13ba6c55841aea1e2a80007c9e9ab8c8 100644 (file)
--- a/Demo/H8S/RTOSDemo/FreeRTOSConfig.h
+++ b/Demo/H8S/RTOSDemo/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/H8S/RTOSDemo/ParTest/ParTest.c b/Demo/H8S/RTOSDemo/ParTest/ParTest.c

index dbdfd85bd9f0ac6cb6b672b1576c2400d707c680..82d5e5cea9cec5a3b52a9c7e582f89386db2364f 100644 (file)
--- a/Demo/H8S/RTOSDemo/ParTest/ParTest.c
+++ b/Demo/H8S/RTOSDemo/ParTest/ParTest.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/H8S/RTOSDemo/main.c b/Demo/H8S/RTOSDemo/main.c

index c5991b8464e82b2d829179f1febfda0c7392ef62..d3efd20990f2aba51c1dff227251e05bff85c7be 100644 (file)
--- a/Demo/H8S/RTOSDemo/main.c
+++ b/Demo/H8S/RTOSDemo/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/H8S/RTOSDemo/serial/serial.c b/Demo/H8S/RTOSDemo/serial/serial.c

index ed5cc09008025db9a78c1e27dda68f1e98bb12d8..44fab6fb93547805af6c56237ab23916ed2cb0dc 100644 (file)
--- a/Demo/H8S/RTOSDemo/serial/serial.c
+++ b/Demo/H8S/RTOSDemo/serial/serial.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/HCS12_CodeWarrior_banked/FreeRTOSConfig.h b/Demo/HCS12_CodeWarrior_banked/FreeRTOSConfig.h

index 4513a25bc89fbbf2356a00df63c590c042d37a66..7d1453cda82a6aeee6777286016247376393b102 100644 (file)
--- a/Demo/HCS12_CodeWarrior_banked/FreeRTOSConfig.h
+++ b/Demo/HCS12_CodeWarrior_banked/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/HCS12_CodeWarrior_banked/ParTest/ParTest.c b/Demo/HCS12_CodeWarrior_banked/ParTest/ParTest.c

index f0873c5a7d1586f0eb7d1c24f2b33d1a59227cec..31e832d59d0ab6b8019e488b93df9a28885e6937 100644 (file)
--- a/Demo/HCS12_CodeWarrior_banked/ParTest/ParTest.c
+++ b/Demo/HCS12_CodeWarrior_banked/ParTest/ParTest.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/HCS12_CodeWarrior_banked/main.c b/Demo/HCS12_CodeWarrior_banked/main.c

index 75e55790d778e6909adcc82986f677be887329dc..20b103105eca7da7d69a7216d546a5b25e741eda 100644 (file)
--- a/Demo/HCS12_CodeWarrior_banked/main.c
+++ b/Demo/HCS12_CodeWarrior_banked/main.c
@@ -1,6 +1,6 @@
  \r
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/HCS12_CodeWarrior_banked/serial/serial.c b/Demo/HCS12_CodeWarrior_banked/serial/serial.c

index c8ac2521eff45dcc1dcbad6a20c5e6d7e7ccd48c..10f9a72fd6260942ba41bce36b45135b041ed0d9 100644 (file)
--- a/Demo/HCS12_CodeWarrior_banked/serial/serial.c
+++ b/Demo/HCS12_CodeWarrior_banked/serial/serial.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/HCS12_CodeWarrior_small/FreeRTOSConfig.h b/Demo/HCS12_CodeWarrior_small/FreeRTOSConfig.h

index 35242f5603bcc311f6043e3373f5c5accbaaa961..61d9cd18835acbed330785fd23d715bd2abf87e1 100644 (file)
--- a/Demo/HCS12_CodeWarrior_small/FreeRTOSConfig.h
+++ b/Demo/HCS12_CodeWarrior_small/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/HCS12_CodeWarrior_small/ParTest/ParTest.c b/Demo/HCS12_CodeWarrior_small/ParTest/ParTest.c

index f0873c5a7d1586f0eb7d1c24f2b33d1a59227cec..31e832d59d0ab6b8019e488b93df9a28885e6937 100644 (file)
--- a/Demo/HCS12_CodeWarrior_small/ParTest/ParTest.c
+++ b/Demo/HCS12_CodeWarrior_small/ParTest/ParTest.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/HCS12_CodeWarrior_small/main.c b/Demo/HCS12_CodeWarrior_small/main.c

index 7c8790521789c6674cd79f0e5a54b9eb11656596..1a0bf6a6086f8346a0b18a0cda9000f3b33886cd 100644 (file)
--- a/Demo/HCS12_CodeWarrior_small/main.c
+++ b/Demo/HCS12_CodeWarrior_small/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/HCS12_CodeWarrior_small/serial/serial.c b/Demo/HCS12_CodeWarrior_small/serial/serial.c

index 61626e8a22f00466193a480961336f9279126eb0..9bdc23c2b1c0514dc0caa4b01bee48c5e9ca59f6 100644 (file)
--- a/Demo/HCS12_CodeWarrior_small/serial/serial.c
+++ b/Demo/HCS12_CodeWarrior_small/serial/serial.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/HCS12_GCC_banked/FreeRTOSConfig.h b/Demo/HCS12_GCC_banked/FreeRTOSConfig.h

index 95d4b79c2ca65b9aa56bc7e593a167a91415da45..efa566122fc6e8d9cea2161d2e409348468dbdd1 100644 (file)
--- a/Demo/HCS12_GCC_banked/FreeRTOSConfig.h
+++ b/Demo/HCS12_GCC_banked/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2005 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2005 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/HCS12_GCC_banked/ParTest.c b/Demo/HCS12_GCC_banked/ParTest.c

index 4c56744739b88ae14e417b42de628de74c83dcb8..9432f0d874c1f3bfaa2155d2b6407ca92540cbc7 100644 (file)
--- a/Demo/HCS12_GCC_banked/ParTest.c
+++ b/Demo/HCS12_GCC_banked/ParTest.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2005 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2005 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/HCS12_GCC_banked/main.c b/Demo/HCS12_GCC_banked/main.c

index fde119a4856386ee4c760269fe229f7aafad6a98..40c37f8207718b6ea79c8ceacf41d78fb71c5c31 100644 (file)
--- a/Demo/HCS12_GCC_banked/main.c
+++ b/Demo/HCS12_GCC_banked/main.c
@@ -1,6 +1,6 @@
  \r
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2005 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2005 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/HCS12_GCC_banked/startup.c b/Demo/HCS12_GCC_banked/startup.c

index 6fdda580ca8a9dbe216f2f22ba0188946ebb2d33..0ba95860f7aa91fea975a59048f63d5a63cb5cbe 100644 (file)
--- a/Demo/HCS12_GCC_banked/startup.c
+++ b/Demo/HCS12_GCC_banked/startup.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2005 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2005 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/MicroBlaze/FreeRTOSConfig.h b/Demo/MicroBlaze/FreeRTOSConfig.h

index cef95d750d2c8926bfa9df134be270d3d7426e74..548312865a5798413f36fabf5e1d874772d016c8 100644 (file)
--- a/Demo/MicroBlaze/FreeRTOSConfig.h
+++ b/Demo/MicroBlaze/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/MicroBlaze/ParTest/ParTest.c b/Demo/MicroBlaze/ParTest/ParTest.c

index d03b2f3ca336dc7889ecdd83ba43cd02fbf0d19c..88f42dc3d7db490aedc63facd9cb5711ba7a7ac1 100644 (file)
--- a/Demo/MicroBlaze/ParTest/ParTest.c
+++ b/Demo/MicroBlaze/ParTest/ParTest.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/MicroBlaze/main.c b/Demo/MicroBlaze/main.c

index 9c02144fe668135d0d10dce40c544ae10955d10a..3820261255471e0256496c7795e27e7ced4bf3be 100644 (file)
--- a/Demo/MicroBlaze/main.c
+++ b/Demo/MicroBlaze/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/MicroBlaze/serial/serial.c b/Demo/MicroBlaze/serial/serial.c

index 7688cb0835aa477e28db53b6e5db7cf7afa4be53..5b1131cfb0a130c32d59a24bb199d0cfbd9a3893 100644 (file)
--- a/Demo/MicroBlaze/serial/serial.c
+++ b/Demo/MicroBlaze/serial/serial.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PC/FRConfig.h b/Demo/PC/FRConfig.h

index 19f144456ac0c1cf80cca2f2ae4f60d020592428..d59d233cb15e449e5eeb874ff79d97241ebae2e7 100644 (file)
--- a/Demo/PC/FRConfig.h
+++ b/Demo/PC/FRConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PC/FileIO/fileIO.c b/Demo/PC/FileIO/fileIO.c

index c67c8958d875e4dc184011ec2ff24afbd81de5fd..887bd5b24ecb4074fd60026e428f13cfefc6eb3a 100644 (file)
--- a/Demo/PC/FileIO/fileIO.c
+++ b/Demo/PC/FileIO/fileIO.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PC/FreeRTOSConfig.h b/Demo/PC/FreeRTOSConfig.h

index b0d54a735ee3abab686cd14cde90acd61c576860..7d0d2dcc3c61e593c4e94772826f31feefeca626 100644 (file)
--- a/Demo/PC/FreeRTOSConfig.h
+++ b/Demo/PC/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PC/ParTest/ParTest.c b/Demo/PC/ParTest/ParTest.c

index 463f6d9c2d148b8935dd20b93432ade20dc36ec8..f429645da320692d6cab7096b5f829a8eebbba91 100644 (file)
--- a/Demo/PC/ParTest/ParTest.c
+++ b/Demo/PC/ParTest/ParTest.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PC/main.c b/Demo/PC/main.c

index 5a16336a2a1fd4a28c81834b16515c2fbe23edd7..f70aeeede00f04ebcd52d945c29737dd679e5ae9 100644 (file)
--- a/Demo/PC/main.c
+++ b/Demo/PC/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PC/serial/serial.c b/Demo/PC/serial/serial.c

index 5e8d30ab8c31927000efd5f1964a1729f3e20544..4a36870466214be090bd1d10e2b24668209e1047 100644 (file)
--- a/Demo/PC/serial/serial.c
+++ b/Demo/PC/serial/serial.c
@@ -5,7 +5,7 @@
         http://dzcomm.sourceforge.net\r
  \r
  \r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_MPLAB/FreeRTOSConfig.h b/Demo/PIC18_MPLAB/FreeRTOSConfig.h

index f82f1b13fc4255f1f4ea3774911004ee31c6fb8c..e7b54823eceed28b989a7058b70913dc5fe8e33c 100644 (file)
--- a/Demo/PIC18_MPLAB/FreeRTOSConfig.h
+++ b/Demo/PIC18_MPLAB/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_MPLAB/ParTest/ParTest.c b/Demo/PIC18_MPLAB/ParTest/ParTest.c

index 6e53b7a818ce336ea5bc56f6d225478b1de4b39a..354466681f341c74111fce1d3c3eb8c46951aa8a 100644 (file)
--- a/Demo/PIC18_MPLAB/ParTest/ParTest.c
+++ b/Demo/PIC18_MPLAB/ParTest/ParTest.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_MPLAB/main1.c b/Demo/PIC18_MPLAB/main1.c

index ea6f0f9d0128cbf32d47cb54afe25d0838604b51..5a6e445f4080649c82bc7e781d9835c5286afa3e 100644 (file)
--- a/Demo/PIC18_MPLAB/main1.c
+++ b/Demo/PIC18_MPLAB/main1.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_MPLAB/main2.c b/Demo/PIC18_MPLAB/main2.c

index 2f2c63730a99a3c3bfac0bd415b128036951a92f..4a893c52f130e7f9cbed604d4b839f1bb02fa877 100644 (file)
--- a/Demo/PIC18_MPLAB/main2.c
+++ b/Demo/PIC18_MPLAB/main2.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_MPLAB/main3.c b/Demo/PIC18_MPLAB/main3.c

index 5afd8b0f2b95789edd8ab4f74902263366e66e72..bf777bc36423ea091c19b75f7ab3296b052208f8 100644 (file)
--- a/Demo/PIC18_MPLAB/main3.c
+++ b/Demo/PIC18_MPLAB/main3.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_MPLAB/serial/serial.c b/Demo/PIC18_MPLAB/serial/serial.c

index a62a1638c415af3490f2a9f4cddd680a73bdc312..c6c3ad384c75818bc7d0e84f90840e96749062d2 100644 (file)
--- a/Demo/PIC18_MPLAB/serial/serial.c
+++ b/Demo/PIC18_MPLAB/serial/serial.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo1/FreeRTOSConfig.h b/Demo/PIC18_WizC/Demo1/FreeRTOSConfig.h

index 8503a6340d0251cdd9edec384b9a08b98cedcc12..3f73d30124114506f9196187d109628ebf780c68 100644 (file)
--- a/Demo/PIC18_WizC/Demo1/FreeRTOSConfig.h
+++ b/Demo/PIC18_WizC/Demo1/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo1/WIZCmake.h b/Demo/PIC18_WizC/Demo1/WIZCmake.h

index 168b6aee72a420e267cb74bdea7d920302c96fdc..3404f762c4093b6efc5602b06cd4dacab576b7e8 100644 (file)
--- a/Demo/PIC18_WizC/Demo1/WIZCmake.h
+++ b/Demo/PIC18_WizC/Demo1/WIZCmake.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo1/fuses.c b/Demo/PIC18_WizC/Demo1/fuses.c

index 66ee9498949d69f7e840a4ce686f009ef3b85728..29a48ae88c80920f5c8c7329b7c437260a43fe96 100644 (file)
--- a/Demo/PIC18_WizC/Demo1/fuses.c
+++ b/Demo/PIC18_WizC/Demo1/fuses.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo1/interrupt.c b/Demo/PIC18_WizC/Demo1/interrupt.c

index 6d9227aa7bc5bfd5b4d226016a537a9b7e13c1ee..f098f5510d7e9545ab0c6514531ba63abaf7337d 100644 (file)
--- a/Demo/PIC18_WizC/Demo1/interrupt.c
+++ b/Demo/PIC18_WizC/Demo1/interrupt.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo1/main.c b/Demo/PIC18_WizC/Demo1/main.c

index bbe8e93391a06ed69807aea5aebe20b4152eb1db..50bbb31b04ff8d5979b4aa7a45d690f6ab3112bf 100644 (file)
--- a/Demo/PIC18_WizC/Demo1/main.c
+++ b/Demo/PIC18_WizC/Demo1/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo2/FreeRTOSConfig.h b/Demo/PIC18_WizC/Demo2/FreeRTOSConfig.h

index 768ddb94aa23dbfb904d84194e00645ddb37500e..bc31f7f571ccd53f3e1cb802194fdeb09a4a096f 100644 (file)
--- a/Demo/PIC18_WizC/Demo2/FreeRTOSConfig.h
+++ b/Demo/PIC18_WizC/Demo2/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo2/WIZCmake.h b/Demo/PIC18_WizC/Demo2/WIZCmake.h

index 610b10dfdffbf6750e23e861f1e5d673368db499..73c36374f2e13f38ad9511f4e326e906bf1fad4d 100644 (file)
--- a/Demo/PIC18_WizC/Demo2/WIZCmake.h
+++ b/Demo/PIC18_WizC/Demo2/WIZCmake.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo2/fuses.c b/Demo/PIC18_WizC/Demo2/fuses.c

index 66ee9498949d69f7e840a4ce686f009ef3b85728..29a48ae88c80920f5c8c7329b7c437260a43fe96 100644 (file)
--- a/Demo/PIC18_WizC/Demo2/fuses.c
+++ b/Demo/PIC18_WizC/Demo2/fuses.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo2/interrupt.c b/Demo/PIC18_WizC/Demo2/interrupt.c

index 45c7fcbf3870e58267c9cb18c103708c4816008d..e7df82437bef909cd98207c92ebddc8af4de61a8 100644 (file)
--- a/Demo/PIC18_WizC/Demo2/interrupt.c
+++ b/Demo/PIC18_WizC/Demo2/interrupt.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo2/main.c b/Demo/PIC18_WizC/Demo2/main.c

index 439ce303968e8f883e4931deb60b242c4a8a1588..0fa53ec34c0f89ff4cc23ca6b4b300f4067d9711 100644 (file)
--- a/Demo/PIC18_WizC/Demo2/main.c
+++ b/Demo/PIC18_WizC/Demo2/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo3/FreeRTOSConfig.h b/Demo/PIC18_WizC/Demo3/FreeRTOSConfig.h

index 43d5f6770a2467dccca459ca3c23b30a0259a790..bd390585bdc9dabd304b3c162b021ddbb0eef6e1 100644 (file)
--- a/Demo/PIC18_WizC/Demo3/FreeRTOSConfig.h
+++ b/Demo/PIC18_WizC/Demo3/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo3/WIZCmake.h b/Demo/PIC18_WizC/Demo3/WIZCmake.h

index 610b10dfdffbf6750e23e861f1e5d673368db499..73c36374f2e13f38ad9511f4e326e906bf1fad4d 100644 (file)
--- a/Demo/PIC18_WizC/Demo3/WIZCmake.h
+++ b/Demo/PIC18_WizC/Demo3/WIZCmake.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo3/fuses.c b/Demo/PIC18_WizC/Demo3/fuses.c

index 66ee9498949d69f7e840a4ce686f009ef3b85728..29a48ae88c80920f5c8c7329b7c437260a43fe96 100644 (file)
--- a/Demo/PIC18_WizC/Demo3/fuses.c
+++ b/Demo/PIC18_WizC/Demo3/fuses.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo3/interrupt.c b/Demo/PIC18_WizC/Demo3/interrupt.c

index 45c7fcbf3870e58267c9cb18c103708c4816008d..e7df82437bef909cd98207c92ebddc8af4de61a8 100644 (file)
--- a/Demo/PIC18_WizC/Demo3/interrupt.c
+++ b/Demo/PIC18_WizC/Demo3/interrupt.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo3/main.c b/Demo/PIC18_WizC/Demo3/main.c

index 0908f8f65845472e2eafb7c4edb8459345e0f797..54395c38c9a16d42784b5223c267d9e6fd3a0822 100644 (file)
--- a/Demo/PIC18_WizC/Demo3/main.c
+++ b/Demo/PIC18_WizC/Demo3/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo4/FreeRTOSConfig.h b/Demo/PIC18_WizC/Demo4/FreeRTOSConfig.h

index 7c191638a6c2205cd6534480d1e3beb7074dc944..f8db712bd1adb2cdf430b6904c7b8fcc30964726 100644 (file)
--- a/Demo/PIC18_WizC/Demo4/FreeRTOSConfig.h
+++ b/Demo/PIC18_WizC/Demo4/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo4/WIZCmake.h b/Demo/PIC18_WizC/Demo4/WIZCmake.h

index 610b10dfdffbf6750e23e861f1e5d673368db499..73c36374f2e13f38ad9511f4e326e906bf1fad4d 100644 (file)
--- a/Demo/PIC18_WizC/Demo4/WIZCmake.h
+++ b/Demo/PIC18_WizC/Demo4/WIZCmake.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo4/fuses.c b/Demo/PIC18_WizC/Demo4/fuses.c

index 66ee9498949d69f7e840a4ce686f009ef3b85728..29a48ae88c80920f5c8c7329b7c437260a43fe96 100644 (file)
--- a/Demo/PIC18_WizC/Demo4/fuses.c
+++ b/Demo/PIC18_WizC/Demo4/fuses.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo4/interrupt.c b/Demo/PIC18_WizC/Demo4/interrupt.c

index 45c7fcbf3870e58267c9cb18c103708c4816008d..e7df82437bef909cd98207c92ebddc8af4de61a8 100644 (file)
--- a/Demo/PIC18_WizC/Demo4/interrupt.c
+++ b/Demo/PIC18_WizC/Demo4/interrupt.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo4/main.c b/Demo/PIC18_WizC/Demo4/main.c

index f1599596a9f33d5d08d438a309a2de1bc51984b7..44be73b09d427da23e8de1a2ab356f248fab8fbe 100644 (file)
--- a/Demo/PIC18_WizC/Demo4/main.c
+++ b/Demo/PIC18_WizC/Demo4/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo5/FreeRTOSConfig.h b/Demo/PIC18_WizC/Demo5/FreeRTOSConfig.h

index 6fbc7a46497b2e04ca954019cf55ef4b3bdba279..6c5f39f254e653406b4a758de9af44e515571e41 100644 (file)
--- a/Demo/PIC18_WizC/Demo5/FreeRTOSConfig.h
+++ b/Demo/PIC18_WizC/Demo5/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo5/WIZCmake.h b/Demo/PIC18_WizC/Demo5/WIZCmake.h

index 610b10dfdffbf6750e23e861f1e5d673368db499..73c36374f2e13f38ad9511f4e326e906bf1fad4d 100644 (file)
--- a/Demo/PIC18_WizC/Demo5/WIZCmake.h
+++ b/Demo/PIC18_WizC/Demo5/WIZCmake.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo5/fuses.c b/Demo/PIC18_WizC/Demo5/fuses.c

index 66ee9498949d69f7e840a4ce686f009ef3b85728..29a48ae88c80920f5c8c7329b7c437260a43fe96 100644 (file)
--- a/Demo/PIC18_WizC/Demo5/fuses.c
+++ b/Demo/PIC18_WizC/Demo5/fuses.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo5/interrupt.c b/Demo/PIC18_WizC/Demo5/interrupt.c

index 45c7fcbf3870e58267c9cb18c103708c4816008d..e7df82437bef909cd98207c92ebddc8af4de61a8 100644 (file)
--- a/Demo/PIC18_WizC/Demo5/interrupt.c
+++ b/Demo/PIC18_WizC/Demo5/interrupt.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo5/main.c b/Demo/PIC18_WizC/Demo5/main.c

index f565ab903cc560365dc1a8644513c6fbc69b941d..4d67cbdd5f249b5669b4269f8fb9bdb14a3612c2 100644 (file)
--- a/Demo/PIC18_WizC/Demo5/main.c
+++ b/Demo/PIC18_WizC/Demo5/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo6/FreeRTOSConfig.h b/Demo/PIC18_WizC/Demo6/FreeRTOSConfig.h

index 3f24e0356a4d14af2f351f8c6cf18283e246a1ca..712bb2a3691ef2cf801a467f4b0373dd07408070 100644 (file)
--- a/Demo/PIC18_WizC/Demo6/FreeRTOSConfig.h
+++ b/Demo/PIC18_WizC/Demo6/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo6/WIZCmake.h b/Demo/PIC18_WizC/Demo6/WIZCmake.h

index 610b10dfdffbf6750e23e861f1e5d673368db499..73c36374f2e13f38ad9511f4e326e906bf1fad4d 100644 (file)
--- a/Demo/PIC18_WizC/Demo6/WIZCmake.h
+++ b/Demo/PIC18_WizC/Demo6/WIZCmake.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo6/fuses.c b/Demo/PIC18_WizC/Demo6/fuses.c

index 66ee9498949d69f7e840a4ce686f009ef3b85728..29a48ae88c80920f5c8c7329b7c437260a43fe96 100644 (file)
--- a/Demo/PIC18_WizC/Demo6/fuses.c
+++ b/Demo/PIC18_WizC/Demo6/fuses.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo6/interrupt.c b/Demo/PIC18_WizC/Demo6/interrupt.c

index 45c7fcbf3870e58267c9cb18c103708c4816008d..e7df82437bef909cd98207c92ebddc8af4de61a8 100644 (file)
--- a/Demo/PIC18_WizC/Demo6/interrupt.c
+++ b/Demo/PIC18_WizC/Demo6/interrupt.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo6/main.c b/Demo/PIC18_WizC/Demo6/main.c

index 5a7bb620f7d2d97bc47bf67aa7ca765968b2fbb5..27a12731b9ab84eb64af047c02d875f2b7f819cf 100644 (file)
--- a/Demo/PIC18_WizC/Demo6/main.c
+++ b/Demo/PIC18_WizC/Demo6/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo7/FreeRTOSConfig.h b/Demo/PIC18_WizC/Demo7/FreeRTOSConfig.h

index 450b3c5b97570cc7a054a5bc394973cce55ad7fa..a1e2c6ff91ae314b9e7059d83d36dde52cb38337 100644 (file)
--- a/Demo/PIC18_WizC/Demo7/FreeRTOSConfig.h
+++ b/Demo/PIC18_WizC/Demo7/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo7/WIZCmake.h b/Demo/PIC18_WizC/Demo7/WIZCmake.h

index 610b10dfdffbf6750e23e861f1e5d673368db499..73c36374f2e13f38ad9511f4e326e906bf1fad4d 100644 (file)
--- a/Demo/PIC18_WizC/Demo7/WIZCmake.h
+++ b/Demo/PIC18_WizC/Demo7/WIZCmake.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo7/fuses.c b/Demo/PIC18_WizC/Demo7/fuses.c

index 66ee9498949d69f7e840a4ce686f009ef3b85728..29a48ae88c80920f5c8c7329b7c437260a43fe96 100644 (file)
--- a/Demo/PIC18_WizC/Demo7/fuses.c
+++ b/Demo/PIC18_WizC/Demo7/fuses.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo7/interrupt.c b/Demo/PIC18_WizC/Demo7/interrupt.c

index 45c7fcbf3870e58267c9cb18c103708c4816008d..e7df82437bef909cd98207c92ebddc8af4de61a8 100644 (file)
--- a/Demo/PIC18_WizC/Demo7/interrupt.c
+++ b/Demo/PIC18_WizC/Demo7/interrupt.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/Demo7/main.c b/Demo/PIC18_WizC/Demo7/main.c

index 26180e33dbd41ae18d659ce56061781526473629..f6eb205df7d0f6a91444aa24fbacd74d24be1212 100644 (file)
--- a/Demo/PIC18_WizC/Demo7/main.c
+++ b/Demo/PIC18_WizC/Demo7/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/ParTest/ParTest.c b/Demo/PIC18_WizC/ParTest/ParTest.c

index c1d6429a8ff586850f27240e8f84cdad47e27460..0ecfe00bd750ed22f660d199e3d882ee03690040 100644 (file)
--- a/Demo/PIC18_WizC/ParTest/ParTest.c
+++ b/Demo/PIC18_WizC/ParTest/ParTest.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/serial/isrSerialRx.c b/Demo/PIC18_WizC/serial/isrSerialRx.c

index 55c72caeb58bfe1b8097a16d2a8a81c534d4472f..192dd0d91e3a8bd9e2e1e0442473dbfad6bbc30f 100644 (file)
--- a/Demo/PIC18_WizC/serial/isrSerialRx.c
+++ b/Demo/PIC18_WizC/serial/isrSerialRx.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/serial/isrSerialTx.c b/Demo/PIC18_WizC/serial/isrSerialTx.c

index 0d97853950e82a3b2e562b81bda1b02f576b575e..f8b52ef0f7ce9e54d3caf6ed1cbc94e3632d0155 100644 (file)
--- a/Demo/PIC18_WizC/serial/isrSerialTx.c
+++ b/Demo/PIC18_WizC/serial/isrSerialTx.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/PIC18_WizC/serial/serial.c b/Demo/PIC18_WizC/serial/serial.c

index 0f98684b5be50acea57715cb025470e23fd4f956..2d8d2f008ce0308e8a2dac21bd320d1a65262a7f 100644 (file)
--- a/Demo/PIC18_WizC/serial/serial.c
+++ b/Demo/PIC18_WizC/serial/serial.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/WizNET_DEMO_GCC_ARM7/FreeRTOSConfig.h b/Demo/WizNET_DEMO_GCC_ARM7/FreeRTOSConfig.h

index 8886633bbdcc1e494a60f35c80130be1fa8d75a5..a159709e70cf4e96632b973ec6e5ac60ec516d17 100644 (file)
--- a/Demo/WizNET_DEMO_GCC_ARM7/FreeRTOSConfig.h
+++ b/Demo/WizNET_DEMO_GCC_ARM7/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/WizNET_DEMO_GCC_ARM7/HTTP_Serv.c b/Demo/WizNET_DEMO_GCC_ARM7/HTTP_Serv.c

index 434e4ac27a67f4fa4eebfb317aef2ae203959b4b..06eba2718c41a4785ea0b7e10d638e1d456a5738 100644 (file)
--- a/Demo/WizNET_DEMO_GCC_ARM7/HTTP_Serv.c
+++ b/Demo/WizNET_DEMO_GCC_ARM7/HTTP_Serv.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/WizNET_DEMO_GCC_ARM7/HTTP_Serv.h b/Demo/WizNET_DEMO_GCC_ARM7/HTTP_Serv.h

index 7637b2c5c61d99a6044d0939aa43bf0726d4fac7..ba1b67c7a3a536fe0e0fe00d92df8892a1bb6e2e 100644 (file)
--- a/Demo/WizNET_DEMO_GCC_ARM7/HTTP_Serv.h
+++ b/Demo/WizNET_DEMO_GCC_ARM7/HTTP_Serv.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/WizNET_DEMO_GCC_ARM7/Makefile b/Demo/WizNET_DEMO_GCC_ARM7/Makefile

index 226572e9948fa705a2b5c167aa53f895a505cafe..1b7af5402907b7cdebb4c53d9266ec46676aa719 100644 (file)
--- a/Demo/WizNET_DEMO_GCC_ARM7/Makefile
+++ b/Demo/WizNET_DEMO_GCC_ARM7/Makefile
@@ -1,4 +1,4 @@
-#      FreeRTOS.org V4.0.2 - copyright (C) 2003-2006 Richard Barry.\r
+#      FreeRTOS.org V4.0.3 - copyright (C) 2003-2006 Richard Barry.\r
  #\r
  #      This file is part of the FreeRTOS.org distribution.\r
  #\r
diff --git a/Demo/WizNET_DEMO_GCC_ARM7/TCP.c b/Demo/WizNET_DEMO_GCC_ARM7/TCP.c

index 8943fcb50d96062aa8b4adbcf145d76255df4dc1..69cff554839b415c3955964b8cf2dbc739f54647 100644 (file)
--- a/Demo/WizNET_DEMO_GCC_ARM7/TCP.c
+++ b/Demo/WizNET_DEMO_GCC_ARM7/TCP.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/WizNET_DEMO_GCC_ARM7/TCP.h b/Demo/WizNET_DEMO_GCC_ARM7/TCP.h

index fc83594c6c01802b1276c780173f536d06f78920..0b2375a0c9515289ca6f4beaba5797e72d9a91c2 100644 (file)
--- a/Demo/WizNET_DEMO_GCC_ARM7/TCP.h
+++ b/Demo/WizNET_DEMO_GCC_ARM7/TCP.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/WizNET_DEMO_GCC_ARM7/TCPISR.c b/Demo/WizNET_DEMO_GCC_ARM7/TCPISR.c

index c47b14d07bb1075dd07dd3e1cf056d0e7a98ba4a..1eea6268b5426f27828d7161c6ff5590155e0c76 100644 (file)
--- a/Demo/WizNET_DEMO_GCC_ARM7/TCPISR.c
+++ b/Demo/WizNET_DEMO_GCC_ARM7/TCPISR.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/WizNET_DEMO_GCC_ARM7/html_pages.h b/Demo/WizNET_DEMO_GCC_ARM7/html_pages.h

index 8d2097d3a65796eb39ed70b3fadc1dc675b6b987..547ccce7790d218ac54992222a3261346e5b2833 100644 (file)
--- a/Demo/WizNET_DEMO_GCC_ARM7/html_pages.h
+++ b/Demo/WizNET_DEMO_GCC_ARM7/html_pages.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/WizNET_DEMO_GCC_ARM7/i2c.c b/Demo/WizNET_DEMO_GCC_ARM7/i2c.c

index c876a12e60164cfe3f20d9762768a5aadc8f4794..43b14c31139ae3930d7577e4ee9b3850cd980926 100644 (file)
--- a/Demo/WizNET_DEMO_GCC_ARM7/i2c.c
+++ b/Demo/WizNET_DEMO_GCC_ARM7/i2c.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/WizNET_DEMO_GCC_ARM7/i2c.h b/Demo/WizNET_DEMO_GCC_ARM7/i2c.h

index b78b1825705d9318cee9ee3eecd3ffa824e06ed1..5851b5a9f31f5da42df50382cc5e86259765c0b2 100644 (file)
--- a/Demo/WizNET_DEMO_GCC_ARM7/i2c.h
+++ b/Demo/WizNET_DEMO_GCC_ARM7/i2c.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/WizNET_DEMO_GCC_ARM7/i2cISR.c b/Demo/WizNET_DEMO_GCC_ARM7/i2cISR.c

index 0132d1ece2395f356c3f5e80b3d69c937acb36c8..4443be186a0ef46297b0efb1fd24974471fd66f7 100644 (file)
--- a/Demo/WizNET_DEMO_GCC_ARM7/i2cISR.c
+++ b/Demo/WizNET_DEMO_GCC_ARM7/i2cISR.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/WizNET_DEMO_GCC_ARM7/main.c b/Demo/WizNET_DEMO_GCC_ARM7/main.c

index 65f27e8b45f9304f1d62dac7a80998a956b657cc..dd8b5f82ce22ca5baf03dee63461deed0c5a417f 100644 (file)
--- a/Demo/WizNET_DEMO_GCC_ARM7/main.c
+++ b/Demo/WizNET_DEMO_GCC_ARM7/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/WizNET_DEMO_TERN_186/FreeRTOSConfig.h b/Demo/WizNET_DEMO_TERN_186/FreeRTOSConfig.h

index 932f9b7505f874e1e200f978e3d1a9db13eba201..a105ec754c30e7670a2e98df02f570f464770d0e 100644 (file)
--- a/Demo/WizNET_DEMO_TERN_186/FreeRTOSConfig.h
+++ b/Demo/WizNET_DEMO_TERN_186/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/WizNET_DEMO_TERN_186/HTTPTask.c b/Demo/WizNET_DEMO_TERN_186/HTTPTask.c

index 3c19a7c8b6e04d2e33b8ccf2db5f4445b96180af..a469df706c65f47d739c5d097420e720531af8ef 100644 (file)
--- a/Demo/WizNET_DEMO_TERN_186/HTTPTask.c
+++ b/Demo/WizNET_DEMO_TERN_186/HTTPTask.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/WizNET_DEMO_TERN_186/HTTPTask.h b/Demo/WizNET_DEMO_TERN_186/HTTPTask.h

index cb0edb2b8aa79e928809fad3ca8aadddb1bca790..91f28f4463e53d00442ec2342ae7a6602c11b0ce 100644 (file)
--- a/Demo/WizNET_DEMO_TERN_186/HTTPTask.h
+++ b/Demo/WizNET_DEMO_TERN_186/HTTPTask.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/WizNET_DEMO_TERN_186/main.c b/Demo/WizNET_DEMO_TERN_186/main.c

index 79f3d47e93d6de0daddf3693b80f97ad42f0abcc..2d2d68574835e8874f23af244f698b72fb90e974 100644 (file)
--- a/Demo/WizNET_DEMO_TERN_186/main.c
+++ b/Demo/WizNET_DEMO_TERN_186/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/WizNET_DEMO_TERN_186/serial/serial.c b/Demo/WizNET_DEMO_TERN_186/serial/serial.c

index 88922b46a237e3bffdbc0ec53e4f38870c6430dd..9527368ecd47d2118eded5bdbebdf44f35ce8a7a 100644 (file)
--- a/Demo/WizNET_DEMO_TERN_186/serial/serial.c
+++ b/Demo/WizNET_DEMO_TERN_186/serial/serial.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/BasicWEB.c b/Demo/lwIP_Demo_Rowley_ARM7/BasicWEB.c

index d8b5248466baeab87a1d4bdb19caa8fef61d7b02..410dae57bb018104f6d05b36d9e1b6d8778089ba 100644 (file)
--- a/Demo/lwIP_Demo_Rowley_ARM7/BasicWEB.c
+++ b/Demo/lwIP_Demo_Rowley_ARM7/BasicWEB.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/BasicWEB.h b/Demo/lwIP_Demo_Rowley_ARM7/BasicWEB.h

index 3f83383fbb03ebfc4184023c751dd37721c7163b..0b23b5e2e7fb7a72b453e5a7e132e628efe5fd6e 100644 (file)
--- a/Demo/lwIP_Demo_Rowley_ARM7/BasicWEB.h
+++ b/Demo/lwIP_Demo_Rowley_ARM7/BasicWEB.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC.c b/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC.c

index edc045d75c28b985df97c3db942623fa4a5e6ec1..91e322996706429e474f0c4512eedd8d82703065 100644 (file)
--- a/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC.c
+++ b/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC.h b/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC.h

index de0afc1ea56a38670e4d4a73ffc716d152d8d972..beeea7be828988678ffb611caea421c9f22ae6f8 100644 (file)
--- a/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC.h
+++ b/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC_ISR.c b/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC_ISR.c

index 5e9ca5b9d9a45062508ed6c0ff07127f4b68bdf0..caa44ea2938c12f57bbe490c9c2a5fe7886abc13 100644 (file)
--- a/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC_ISR.c
+++ b/Demo/lwIP_Demo_Rowley_ARM7/EMAC/SAM7_EMAC_ISR.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/FreeRTOSConfig.h b/Demo/lwIP_Demo_Rowley_ARM7/FreeRTOSConfig.h

index 4e7bf39de5bff337f8142d265bd749f1e8ad71ea..7d6a66dd889a92b55eaf2456765097440090c09c 100644 (file)
--- a/Demo/lwIP_Demo_Rowley_ARM7/FreeRTOSConfig.h
+++ b/Demo/lwIP_Demo_Rowley_ARM7/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
@@ -54,7 +54,7 @@
  #define configTICK_RATE_HZ                     ( ( portTickType ) 1000 )\r
  #define configMAX_PRIORITIES           ( ( unsigned portBASE_TYPE ) 5 )\r
  #define configMINIMAL_STACK_SIZE       ( ( unsigned portSHORT ) 110 )\r
-#define configTOTAL_HEAP_SIZE          ( ( size_t ) 24000 )\r
+#define configTOTAL_HEAP_SIZE          ( ( size_t ) 22000 )\r
  #define configMAX_TASK_NAME_LEN                ( 16 )\r
  #define configUSE_TRACE_FACILITY       1\r
  #define configUSE_16_BIT_TICKS         0\r
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/ParTest/ParTest.c b/Demo/lwIP_Demo_Rowley_ARM7/ParTest/ParTest.c

index 071d49afe2afc79dfdb6f8640cd53dee72409725..9d70bc0ba862cd21c1dea4a73de8b889d23c11ab 100644 (file)
--- a/Demo/lwIP_Demo_Rowley_ARM7/ParTest/ParTest.c
+++ b/Demo/lwIP_Demo_Rowley_ARM7/ParTest/ParTest.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/USB/USB-CDC.c b/Demo/lwIP_Demo_Rowley_ARM7/USB/USB-CDC.c

index 3a57c2feb18cc5a4d5b1499182c9e26942f6418c..50ccfadf49ed9327665c798e06337164518ec037 100644 (file)
--- a/Demo/lwIP_Demo_Rowley_ARM7/USB/USB-CDC.c
+++ b/Demo/lwIP_Demo_Rowley_ARM7/USB/USB-CDC.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/USB/USB-CDC.h b/Demo/lwIP_Demo_Rowley_ARM7/USB/USB-CDC.h

index 374b83cccf20efafafa386eaa77b613646c3a180..96ef5940b16031c3d0954b3a50b1c214ed6db85a 100644 (file)
--- a/Demo/lwIP_Demo_Rowley_ARM7/USB/USB-CDC.h
+++ b/Demo/lwIP_Demo_Rowley_ARM7/USB/USB-CDC.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/USB/USBIsr.c b/Demo/lwIP_Demo_Rowley_ARM7/USB/USBIsr.c

index db9e56ff5bd5fa8013444f23d32722535a19fbad..2761bbc50b581fd1b0d714bc1493c2e4f4a5c36c 100644 (file)
--- a/Demo/lwIP_Demo_Rowley_ARM7/USB/USBIsr.c
+++ b/Demo/lwIP_Demo_Rowley_ARM7/USB/USBIsr.c
@@ -1,5 +1,5 @@
  /*\r
-  FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+  FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
    This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/USB/descriptors.h b/Demo/lwIP_Demo_Rowley_ARM7/USB/descriptors.h

index dc8813c1e782a2c69272f15e6c3e7a0269c9b80b..05d36f8f45c7e579b2e550ed990758a87c313b55 100644 (file)
--- a/Demo/lwIP_Demo_Rowley_ARM7/USB/descriptors.h
+++ b/Demo/lwIP_Demo_Rowley_ARM7/USB/descriptors.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/USB/usb.h b/Demo/lwIP_Demo_Rowley_ARM7/USB/usb.h

index ffe51e94a7aa42e2eb2409cf83a3828513ae9f45..4b2af857305791d5e85d6f2d277570a77658eb4e 100644 (file)
--- a/Demo/lwIP_Demo_Rowley_ARM7/USB/usb.h
+++ b/Demo/lwIP_Demo_Rowley_ARM7/USB/usb.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/main.c b/Demo/lwIP_Demo_Rowley_ARM7/main.c

index 8eb4c1cd54fa89c2ef179c8cb714394a64b1ab9d..d68e7d26ae094a25589d26c5f5ae20b13739a800 100644 (file)
--- a/Demo/lwIP_Demo_Rowley_ARM7/main.c
+++ b/Demo/lwIP_Demo_Rowley_ARM7/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/makefile b/Demo/lwIP_Demo_Rowley_ARM7/makefile

index 8b7ad49c0401129273c3185e0f80858c99a81313..9d92789033405be57b33079e8f90cdd834f81c76 100644 (file)
--- a/Demo/lwIP_Demo_Rowley_ARM7/makefile
+++ b/Demo/lwIP_Demo_Rowley_ARM7/makefile
@@ -1,4 +1,4 @@
-#      FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+#      FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  #\r
  #      This file is part of the FreeRTOS.org distribution.\r
  #\r
@@ -32,8 +32,8 @@ CC=arm-elf-gcc
  OBJCOPY=arm-elf-objcopy\r
  ARCH=arm-elf-ar\r
  CRT0=boot.s\r
-DEBUG=\r
-OPTIM=-Os\r
+DEBUG=-g\r
+OPTIM=-O0\r
  LDSCRIPT=atmel-rom.ld\r
  \r
  #\r
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/rtosdemo.hzp b/Demo/lwIP_Demo_Rowley_ARM7/rtosdemo.hzp

index 8b5dad655475712cc198a731f0074405de4db850..8cb2ecbd2df9a1382dbf921af31db734f010331a 100644 (file)
--- a/Demo/lwIP_Demo_Rowley_ARM7/rtosdemo.hzp
+++ b/Demo/lwIP_Demo_Rowley_ARM7/rtosdemo.hzp
@@ -71,8 +71,10 @@
        <file file_name="AT91SAM7_Target.js" Name="AT91SAM7_Target.js" >
          <configuration Name="Common" file_type="Reset Script" />
        </file>
+      <file file_name="threads.js" Name="threads.js" />
      </folder>
      <configuration arm_target_loader_reset_after_download="Yes" target_reset_script="FLASHReset()" arm_target_flash_loader_type="Comms Channel Loader" Name="THUMB Flash Debug" />
+    <configuration gcc_optimization_level="Level 1" build_debug_information="Yes" Name="THUMB Flash Release" />
    </project>
    <configuration build_quietly="Yes" inherited_configurations="THUMB;Flash;Debug" Name="THUMB Flash Debug" />
    <configuration arm_library_instruction_set="THUMB" c_preprocessor_definitions="__THUMB" arm_instruction_set="THUMB" hidden="Yes" Name="THUMB" />
@@ -80,5 +82,5 @@
    <configuration c_preprocessor_definitions="DEBUG" link_include_startup_code="No" gcc_optimization_level="None" build_debug_information="Yes" Name="Debug" />
    <configuration inherited_configurations="THUMB;Flash;Release" gcc_optimization_level="Level 2" Name="THUMB Flash Release" />
    <configuration c_preprocessor_definitions="NDEBUG" link_include_startup_code="No" gcc_optimization_level="Level 1" build_debug_information="No" Name="Release" />
-  <configuration arm_library_instruction_set="THUMB" gcc_entry_point="0x100000" build_quietly="Yes" c_preprocessor_definitions="SAM7_GCC;THUMB_INTERWORK;SUPERVISOR_START" c_user_include_directories=".;$(ProjectDir)/EMAC;$(ProjectDir)/../common/include;$(ProjectDir)/USB" link_include_startup_code="Yes" arm_instruction_set="THUMB" c_preprocessor_undefinitions="" c_additional_options="-Wall ;-Wextra;-Wstrict-prototypes ;-Wmissing-prototypes ;-Wmissing-declarations;-Wno-strict-aliasing" arm_linker_stack_size="0" Name="Common" c_system_include_directories="$(StudioDir)/include;$(ProjectDir)/lwip-1.1.0/src/include;$(ProjectDir)/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X;$(ProjectDir);$(ProjectDir)/../../source/include;$(ProjectDir)/../../source/portable/GCC/ARM7_AT91SAM7S;$(ProjectDir)/lwip-1.1.0\\src\\include\\ipv4" arm_linker_heap_size="0" />
+  <configuration arm_library_instruction_set="THUMB" gcc_entry_point="0x100000" build_quietly="Yes" c_preprocessor_definitions="SAM7_GCC;THUMB_INTERWORK;SUPERVISOR_START" c_user_include_directories=".;$(ProjectDir)/EMAC;$(ProjectDir)/../common/include;$(ProjectDir)/USB" link_include_startup_code="Yes" arm_instruction_set="THUMB" c_preprocessor_undefinitions="" c_additional_options="-Wall;-Wextra;-Wstrict-prototypes;-Wmissing-prototypes;-Wmissing-declarations;-Wno-strict-aliasing" arm_linker_stack_size="0" Name="Common" c_system_include_directories="$(StudioDir)/include;$(ProjectDir)/lwip-1.1.0/src/include;$(ProjectDir)/lwip-1.1.0/contrib/port/FreeRTOS/AT91SAM7X;$(ProjectDir);$(ProjectDir)/../../source/include;$(ProjectDir)/../../source/portable/GCC/ARM7_AT91SAM7S;$(ProjectDir)/lwip-1.1.0\\src\\include\\ipv4" arm_linker_heap_size="0" />
  </solution>
diff --git a/Demo/lwIP_Demo_Rowley_ARM7/rtosdemo.hzs b/Demo/lwIP_Demo_Rowley_ARM7/rtosdemo.hzs

index 9a2732c91ed89ee97c89aee341feacdf0b783086..c6f7b80c2155e55bd2ac943c5767ed6d4401a424 100644 (file)
--- a/Demo/lwIP_Demo_Rowley_ARM7/rtosdemo.hzs
+++ b/Demo/lwIP_Demo_Rowley_ARM7/rtosdemo.hzs
@@ -1,6 +1,26 @@
  <!DOCTYPE CrossStudio_for_ARM_Session_File>
  <session>
- <Breakpoints/>
+ <Autos>
+  <Watches active="0" />
+ </Autos>
+ <Bookmarks/>
+ <Breakpoints>
+  <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="ARM Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="4" mask="0" comparison="0" expression="D_Abort" filename="" />
+  <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="ARM Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="3" mask="0" comparison="0" expression="FIQ" filename="" />
+  <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="ARM Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="3" mask="0" comparison="0" expression="IRQ" filename="" />
+  <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="ARM Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="4" mask="0" comparison="0" expression="P_Abort" filename="" />
+  <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="ARM Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="3" mask="0" comparison="0" expression="Reset" filename="" />
+  <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="ARM Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="3" mask="0" comparison="0" expression="SWI" filename="" />
+  <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="ARM Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="4" mask="0" comparison="0" expression="Undef" filename="" />
+  <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="Cortex-M3 Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="4" mask="0" comparison="0" expression="BusFault" filename="" />
+  <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="Cortex-M3 Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="4" mask="0" comparison="0" expression="ExceptionEntryReturnFault" filename="" />
+  <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="Cortex-M3 Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="4" mask="0" comparison="0" expression="HardFault" filename="" />
+  <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="Cortex-M3 Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="4" mask="0" comparison="0" expression="MemManage" filename="" />
+  <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="Cortex-M3 Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="3" mask="0" comparison="0" expression="Reset" filename="" />
+  <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="Cortex-M3 Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="4" mask="0" comparison="0" expression="UsageFault_CheckingError" filename="" />
+  <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="Cortex-M3 Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="4" mask="0" comparison="0" expression="UsageFault_Coprocessor" filename="" />
+  <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="Cortex-M3 Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="4" mask="0" comparison="0" expression="UsageFault_StateError" filename="" />
+ </Breakpoints>
   <ExecutionCountWindow/>
   <Memory1>
    <MemoryWindow autoEvaluate="0" addressText="0x102248" numColumns="8" sizeText="128" dataSize="1" radix="16" addressSpace="" />
@@ -18,21 +38,18 @@
    <ProjectSessionItem path="rtosdemo" name="unnamed" />
    <ProjectSessionItem path="rtosdemo;rtosdemo" name="unnamed" />
    <ProjectSessionItem path="rtosdemo;rtosdemo;Source Files" name="unnamed" />
-  <ProjectSessionItem path="rtosdemo;rtosdemo;Source Files;Demo App" name="unnamed" />
-  <ProjectSessionItem path="rtosdemo;rtosdemo;Source Files;FreeRTOS kernel" name="unnamed" />
-  <ProjectSessionItem path="rtosdemo;rtosdemo;Source Files;lwIP" name="unnamed" />
   </Project>
   <Register1>
-  <RegisterWindow unsignedDisplays="" asciiDisplays="" octalDisplays="" visibleGroups="CPU - Current Mode" decimalDisplays="" binaryDisplays="" />
+  <RegisterWindow unsignedDisplays="" asciiDisplays="" octalDisplays="" openGroups="" visibleGroups="CPU - Current Mode" decimalDisplays="" binaryDisplays="" />
   </Register1>
   <Register2>
-  <RegisterWindow unsignedDisplays="" asciiDisplays="" octalDisplays="" visibleGroups="" decimalDisplays="" binaryDisplays="" />
+  <RegisterWindow unsignedDisplays="" asciiDisplays="" octalDisplays="" openGroups="" visibleGroups="" decimalDisplays="" binaryDisplays="" />
   </Register2>
   <Register3>
-  <RegisterWindow unsignedDisplays="" asciiDisplays="" octalDisplays="" visibleGroups="" decimalDisplays="" binaryDisplays="" />
+  <RegisterWindow unsignedDisplays="" asciiDisplays="" octalDisplays="" openGroups="" visibleGroups="" decimalDisplays="" binaryDisplays="" />
   </Register3>
   <Register4>
-  <RegisterWindow unsignedDisplays="" asciiDisplays="" octalDisplays="" visibleGroups="" decimalDisplays="" binaryDisplays="" />
+  <RegisterWindow unsignedDisplays="" asciiDisplays="" octalDisplays="" openGroups="" visibleGroups="" decimalDisplays="" binaryDisplays="" />
   </Register4>
   <SourceNavigatorWindow/>
   <TraceWindow>
@@ -56,5 +73,5 @@
    <Watches active="0" />
   </Watch4>
   <Files/>
- <ARMCrossStudioWindow activeProject="rtosdemo" ignoreExceptions="IRQ;FIQ;SWI" autoConnectTarget="" debugSearchFileMap="" fileDialogInitialDirectory="E:\Dev\FreeRTOS\Demo\Common\Minimal" fileDialogDefaultFilter="*.cpp;*.cxx;*.cc;*.c;*.h" debugSearchPath="" buildConfiguration="THUMB Flash Release" />
+ <ARMCrossStudioWindow activeProject="rtosdemo" autoConnectTarget="/USB CrossConnect for ARM" debugSearchFileMap="" fileDialogInitialDirectory="C:\E\Dev\FreeRTOS\Demo\lwIP_Demo_Rowley_ARM7" fileDialogDefaultFilter="*.js" autoConnectCapabilities="1407" debugSearchPath="" buildConfiguration="THUMB Flash Release" />
  </session>
diff --git a/Demo/msp430_CrossWorks/FreeRTOSConfig.h b/Demo/msp430_CrossWorks/FreeRTOSConfig.h

index 5c56b2198aeda4f371adf2a91cb0469be4fcb630..cf31cab397ade8cdb9cc77ddea5088e1b7eb2279 100644 (file)
--- a/Demo/msp430_CrossWorks/FreeRTOSConfig.h
+++ b/Demo/msp430_CrossWorks/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/msp430_CrossWorks/ParTest/ParTest.c b/Demo/msp430_CrossWorks/ParTest/ParTest.c

index 34140faafd0307afa4c223ffbd88effa61a73ded..9d6b5145a4e56ac6d5ae96d0ce8099884ede350e 100644 (file)
--- a/Demo/msp430_CrossWorks/ParTest/ParTest.c
+++ b/Demo/msp430_CrossWorks/ParTest/ParTest.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/msp430_CrossWorks/main.c b/Demo/msp430_CrossWorks/main.c

index 9ea2e4ae9f5f30db935a097f028b6a76eca82dd1..1178e6cd4d158a76069e328006d06c0670253de7 100644 (file)
--- a/Demo/msp430_CrossWorks/main.c
+++ b/Demo/msp430_CrossWorks/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/msp430_CrossWorks/serial/serial.c b/Demo/msp430_CrossWorks/serial/serial.c

index ff626c08aecd54b9b24a86aa016926fbc1bdafa5..67bb4e247e6ffd18e3d8b394ed0002513ac633a2 100644 (file)
--- a/Demo/msp430_CrossWorks/serial/serial.c
+++ b/Demo/msp430_CrossWorks/serial/serial.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/msp430_GCC/FreeRTOSConfig.h b/Demo/msp430_GCC/FreeRTOSConfig.h

index 592f473ce0a4f37cdfb7235d8ad513014b4e2149..095982a42af60a3cdd42c715b2bfa31f18e8c2d7 100644 (file)
--- a/Demo/msp430_GCC/FreeRTOSConfig.h
+++ b/Demo/msp430_GCC/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/msp430_GCC/ParTest/ParTest.c b/Demo/msp430_GCC/ParTest/ParTest.c

index f44e9243720a67179aee98939aeeef8f93b02012..43b58ab96d5b51ead1bfc039962c6972a2759cb8 100644 (file)
--- a/Demo/msp430_GCC/ParTest/ParTest.c
+++ b/Demo/msp430_GCC/ParTest/ParTest.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/msp430_GCC/main.c b/Demo/msp430_GCC/main.c

index edcc13bbed7189e3e1336cb5223e827d7ea638ff..679539e4f6012fe273a40327fedcb8fd77ca182b 100644 (file)
--- a/Demo/msp430_GCC/main.c
+++ b/Demo/msp430_GCC/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/msp430_GCC/makefile b/Demo/msp430_GCC/makefile

index 400399c16a1b5551145554564dcd0a4980dfb7e3..91a7be564f01c62da2e95abcbfd49d0f32824743 100644 (file)
--- a/Demo/msp430_GCC/makefile
+++ b/Demo/msp430_GCC/makefile
@@ -1,4 +1,4 @@
-#      FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+#      FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  #\r
  #      This file is part of the FreeRTOS.org distribution.\r
  #\r
diff --git a/Demo/msp430_GCC/serial/serial.c b/Demo/msp430_GCC/serial/serial.c

index dca044894a714a949f544021b28b8dc3f2948e4a..8773336cf85bfd57a2044f5ed225834e312f6c00 100644 (file)
--- a/Demo/msp430_GCC/serial/serial.c
+++ b/Demo/msp430_GCC/serial/serial.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/uIP_Demo_IAR_ARM7/EMAC/EMAClISR.s79 b/Demo/uIP_Demo_IAR_ARM7/EMAC/EMAClISR.s79

index a5b288c83832a8cd390527ed5d5b8f0b271d2297..dae84b6541982bdbc863e15c9c874446c079780b 100644 (file)
--- a/Demo/uIP_Demo_IAR_ARM7/EMAC/EMAClISR.s79
+++ b/Demo/uIP_Demo_IAR_ARM7/EMAC/EMAClISR.s79
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/uIP_Demo_IAR_ARM7/EMAC/SAM7_EMAC.c b/Demo/uIP_Demo_IAR_ARM7/EMAC/SAM7_EMAC.c

index 49760d27e035b4ff8ba998808479029edfbbfb4a..4c175be53b15ce6a0b983fd1ed35a5e1fab897f5 100644 (file)
--- a/Demo/uIP_Demo_IAR_ARM7/EMAC/SAM7_EMAC.c
+++ b/Demo/uIP_Demo_IAR_ARM7/EMAC/SAM7_EMAC.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/uIP_Demo_IAR_ARM7/FreeRTOSConfig.h b/Demo/uIP_Demo_IAR_ARM7/FreeRTOSConfig.h

index f267c03984d00d8767c046d8a8f838f8f2289c6c..a371e39534a30db8481265e2c853be2c2529dedd 100644 (file)
--- a/Demo/uIP_Demo_IAR_ARM7/FreeRTOSConfig.h
+++ b/Demo/uIP_Demo_IAR_ARM7/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/uIP_Demo_IAR_ARM7/ParTest/ParTest.c b/Demo/uIP_Demo_IAR_ARM7/ParTest/ParTest.c

index ba03464a5104b18f9db77ce0cb792c51d18767db..9c2f982b66523026d781f4de35e11022df5916ba 100644 (file)
--- a/Demo/uIP_Demo_IAR_ARM7/ParTest/ParTest.c
+++ b/Demo/uIP_Demo_IAR_ARM7/ParTest/ParTest.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/uIP_Demo_IAR_ARM7/main.c b/Demo/uIP_Demo_IAR_ARM7/main.c

index 6bc2bd126fb81f07d015b06550dc419af2a081d0..c1884c011e209f19825e00c0a3418a58a93265ba 100644 (file)
--- a/Demo/uIP_Demo_IAR_ARM7/main.c
+++ b/Demo/uIP_Demo_IAR_ARM7/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/uIP_Demo_Rowley_ARM7/FreeRTOSConfig.h b/Demo/uIP_Demo_Rowley_ARM7/FreeRTOSConfig.h

index 33f69433f51722b1911a50d25fb4077022335bde..12c8176a2e10b170deba4022cdd13c4ed7335509 100644 (file)
--- a/Demo/uIP_Demo_Rowley_ARM7/FreeRTOSConfig.h
+++ b/Demo/uIP_Demo_Rowley_ARM7/FreeRTOSConfig.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/uIP_Demo_Rowley_ARM7/Philips_LPC210X_Startup.s b/Demo/uIP_Demo_Rowley_ARM7/Philips_LPC210X_Startup.s

new file mode 100644 (file)

index 0000000..47debb7
--- /dev/null
+++ b/Demo/uIP_Demo_Rowley_ARM7/Philips_LPC210X_Startup.s
@@ -0,0 +1,213 @@
+/*****************************************************************************\r
+ * Copyright (c) 2001, 2002 Rowley Associates Limited.                       *\r
+ *                                                                           *\r
+ * This file may be distributed under the terms of the License Agreement     *\r
+ * provided with this software.                                              *\r
+ *                                                                           *\r
+ * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE   *\r
+ * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *\r
+ *****************************************************************************/\r
+\r
+/*****************************************************************************\r
+ *                           Preprocessor Definitions\r
+ *                           ------------------------\r
+ *\r
+ * VECTORED_IRQ_INTERRUPTS\r
+ *\r
+ *   Enable vectored IRQ interrupts. If defined, the PC register will be loaded\r
+ *   with the contents of the VICVectAddr register on an IRQ exception.\r
+ *\r
+ * USE_PLL\r
+ *\r
+ *   If defined, connect PLL as processor clock source. If undefined, the \r
+ *   oscillator clock will be used.\r
+ *\r
+ * PLLCFG_VAL\r
+ *\r
+ *   Override the default PLL configuration (multiplier = 5, divider = 2)\r
+ *   by defining PLLCFG_VAL.\r
+ *\r
+ * USE_MAM\r
+ *\r
+ *   If defined then the memory accelerator module (MAM) will be enabled.\r
+ *\r
+ * MAMCR_VAL & MAMTIM_VAL\r
+ * \r
+ *   Override the default MAM configuration (fully enabled, 3 fetch cycles)\r
+ *   by defining MAMCR_VAL and MAMTIM_VAL.\r
+ *\r
+ * VPBDIV_VAL\r
+ *\r
+ *   If defined then this value will be used to configure the VPB divider.\r
+ *\r
+ * SRAM_EXCEPTIONS\r
+ *\r
+ *   If defined, enable copying and re-mapping of interrupt vectors from User \r
+ *   FLASH to SRAM. If undefined, interrupt vectors will be mapped in User \r
+ *   FLASH.\r
+ *\r
+ *****************************************************************************/\r
+\r
+#ifndef PLLCFG_VAL\r
+#define PLLCFG_VAL 0x24 \r
+#endif\r
+\r
+#ifndef MAMCR_VAL\r
+#define MAMCR_VAL 2\r
+#endif\r
+\r
+#ifndef MAMTIM_VAL\r
+#define MAMTIM_VAL 3\r
+#endif\r
+\r
+#define MAMCR_OFFS   0x000\r
+#define MAMTIM_OFFS  0x004\r
+\r
+#define PLLCON_OFFS  0x080\r
+#define PLLCFG_OFFS  0x084\r
+#define PLLSTAT_OFFS 0x088\r
+#define PLLFEED_OFFS 0x08C\r
+\r
+#define VPBDIV_OFFS  0x100\r
+\r
+  .section .vectors, "ax"\r
+  .code 32\r
+  .align 0\r
+\r
+/*****************************************************************************\r
+ * Exception Vectors                                                         *\r
+ *****************************************************************************/\r
+_vectors:\r
+  ldr pc, [pc, #reset_handler_address - . - 8]  /* reset */\r
+  ldr pc, [pc, #undef_handler_address - . - 8]  /* undefined instruction */\r
+  ldr pc, [pc, #swi_handler_address - . - 8]    /* swi handler */\r
+  ldr pc, [pc, #pabort_handler_address - . - 8] /* abort prefetch */\r
+  ldr pc, [pc, #dabort_handler_address - . - 8] /* abort data */\r
+#ifdef VECTORED_IRQ_INTERRUPTS\r
+  .word 0xB9205F84                              /* boot loader checksum */\r
+  ldr pc, [pc, #-0xFF0]                         /* irq handler */\r
+#else\r
+  .word 0xB8A06F60                              /* boot loader checksum */\r
+  ldr pc, [pc, #irq_handler_address - . - 8]    /* irq handler */\r
+#endif\r
+  ldr pc, [pc, #fiq_handler_address - . - 8]    /* fiq handler */\r
+\r
+reset_handler_address:\r
+  .word reset_handler\r
+undef_handler_address:\r
+  .word undef_handler\r
+swi_handler_address:\r
+  .word swi_handler\r
+pabort_handler_address:\r
+  .word pabort_handler\r
+dabort_handler_address:\r
+  .word dabort_handler\r
+irq_handler_address:\r
+  .word irq_handler\r
+fiq_handler_address:\r
+  .word fiq_handler\r
+\r
+  .section .init, "ax"\r
+  .code 32\r
+  .align 0\r
+\r
+/******************************************************************************\r
+ *                                                                            *\r
+ * Default exception handlers                                                 *\r
+ *                                                                            *\r
+ ******************************************************************************/\r
+\r
+reset_handler:\r
+#if defined(USE_PLL) || defined(USE_MAM) || defined(VPBDIV_VAL)\r
+  ldr r0, =0xE01FC000\r
+#endif\r
+#if defined(USE_PLL)\r
+  /* Configure PLL Multiplier/Divider */\r
+  ldr r1, =PLLCFG_VAL\r
+  str r1, [r0, #PLLCFG_OFFS]\r
+  /* Enable PLL */\r
+  mov r1, #0x1\r
+  str r1, [r0, #PLLCON_OFFS]\r
+  mov r1, #0xAA\r
+  str r1, [r0, #PLLFEED_OFFS]\r
+  mov r1, #0x55\r
+  str r1, [r0, #PLLFEED_OFFS]\r
+  /* Wait for PLL to lock */\r
+pll_lock_loop:\r
+  ldr r1, [r0, #PLLSTAT_OFFS]\r
+  tst r1, #0x400\r
+  beq pll_lock_loop\r
+  /* PLL Locked, connect PLL as clock source */\r
+  mov r1, #0x3\r
+  str r1, [r0, #PLLCON_OFFS]\r
+  mov r1, #0xAA\r
+  str r1, [r0, #PLLFEED_OFFS]\r
+  mov r1, #0x55\r
+  str r1, [r0, #PLLFEED_OFFS]\r
+#endif\r
+\r
+#if defined(USE_MAM)\r
+  mov r1, #0\r
+  str r1, [r0, #MAMCR_OFFS]\r
+  ldr r1, =MAMTIM_VAL\r
+  str r1, [r0, #MAMTIM_OFFS]\r
+  ldr r1, =MAMCR_VAL\r
+  str r1, [r0, #MAMCR_OFFS]\r
+#endif\r
+\r
+#if defined(VPBDIV_VAL)\r
+  ldr r1, =VPBDIV_VAL\r
+  str r1, [r0, #VPBDIV_OFFS]\r
+#endif\r
+\r
+#if defined(SRAM_EXCEPTIONS)\r
+  /* Copy exception vectors into SRAM */\r
+  mov r8, #0x40000000\r
+  ldr r9, =_vectors\r
+  ldmia r9!, {r0-r7}\r
+  stmia r8!, {r0-r7}\r
+  ldmia r9!, {r0-r6}\r
+  stmia r8!, {r0-r6}\r
+\r
+  /* Re-map interrupt vectors from SRAM */\r
+  ldr r0, MEMMAP\r
+  mov r1, #2 /* User RAM Mode. Interrupt vectors are re-mapped from SRAM */\r
+  str r1, [r0]\r
+#endif /* SRAM_EXCEPTIONS */\r
+  \r
+  b _start\r
+\r
+#ifdef SRAM_EXCEPTIONS\r
+MEMMAP:\r
+  .word 0xE01FC040\r
+#endif\r
+\r
+/******************************************************************************\r
+ *                                                                            *\r
+ * Default exception handlers                                                 *\r
+ * These are declared weak symbols so they can be redefined in user code.     * \r
+ *                                                                            *\r
+ ******************************************************************************/\r
+\r
+undef_handler:\r
+  b undef_handler\r
+  \r
+swi_handler:\r
+  b swi_handler\r
+  \r
+pabort_handler:\r
+  b pabort_handler\r
+  \r
+dabort_handler:\r
+  b dabort_handler\r
+  \r
+irq_handler:\r
+  b irq_handler\r
+  \r
+fiq_handler:\r
+  b fiq_handler\r
+\r
+  .weak undef_handler, swi_handler, pabort_handler, dabort_handler, irq_handler, fiq_handler\r
+                                                    \r
+\r
+                  \r
diff --git a/Demo/uIP_Demo_Rowley_ARM7/main.c b/Demo/uIP_Demo_Rowley_ARM7/main.c

index 2bb943a4b419cda3394a6d855119cb52e0487aee..77513a7fb158af00a0379258cbad50d74277bea7 100644 (file)
--- a/Demo/uIP_Demo_Rowley_ARM7/main.c
+++ b/Demo/uIP_Demo_Rowley_ARM7/main.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Demo/uIP_Demo_Rowley_ARM7/rtosdemo.hzp b/Demo/uIP_Demo_Rowley_ARM7/rtosdemo.hzp

index aff3c5c6dd731f398ac1a455d8cdd96cd6ff1992..e995765da3c0c468440765a4257c7844040dd53c 100644 (file)
--- a/Demo/uIP_Demo_Rowley_ARM7/rtosdemo.hzp
+++ b/Demo/uIP_Demo_Rowley_ARM7/rtosdemo.hzp
@@ -1,7 +1,7 @@
  <!DOCTYPE CrossStudio_Project_File>
  <solution version="1" Name="rtosdemo" >
    <project Name="rtosdemo" >
-    <configuration Target="LPC2124" property_groups_file_path="$(StudioDir)/targets/Philips_LPC210X/propertyGroups.xml" linker_memory_map_file="$(StudioDir)/targets/Philips_LPC210X/Philips_LPC2124_MemoryMap.xml" c_preprocessor_definitions="OSCILLATOR_CLOCK_FREQUENCY=14745600;THUMB_INTERWORK;SUPERVISOR_START;VECTORED_IRQ_INTERRUPTS;GCC_ARM7" c_user_include_directories="../../Source/include;../../Demo/uIP_Demo_Rowley_ARM7;../../Demo/Common/Include;uip;." project_directory="" link_include_startup_code="No" project_type="Executable" c_additional_options="" Name="Common" />
+    <configuration arm_target_loader_parameter="14745600" Target="LPC2124" property_groups_file_path="$(StudioDir)/targets/Philips_LPC210X/propertyGroups.xml" oscillator_frequency="14.7456MHz" linker_memory_map_file="$(StudioDir)/targets/Philips_LPC210X/Philips_LPC2124_MemoryMap.xml" gcc_entry_point="_start" c_preprocessor_definitions="THUMB_INTERWORK;SUPERVISOR_START;VECTORED_IRQ_INTERRUPTS;GCC_ARM7" c_user_include_directories="../../Source/include;../../Demo/uIP_Demo_Rowley_ARM7;../../Demo/Common/Include;uip;." project_directory="" link_include_startup_code="No" project_type="Executable" c_additional_options="" Name="Common" />
      <configuration target_reset_script="SRAMReset()" Name="RAM" />
      <configuration arm_target_flash_loader_file_path="$(StudioDir)/targets/Philips_LPC210X/Release/Loader.exe" target_reset_script="FLASHReset()" Name="Flash" />
      <folder Name="uIP Source" >
@@ -20,11 +20,11 @@
      <folder Name="System Files" >
        <configuration filter="" Name="Common" />
        <file file_name="$(StudioDir)/source/crt0.s" Name="crt0.s" />
-      <file file_name="$(StudioDir)/targets/Philips_LPC210X/Philips_LPC210X_Startup.s" Name="Philips_LPC210X_Startup.s" />
        <file file_name="$(StudioDir)/targets/Philips_LPC210X/Philips_LPC210X_Target.js" Name="Philips_LPC210X_Target.js" >
          <configuration Name="Common" file_type="Reset Script" />
        </file>
        <file file_name="flash_placement.xml" Name="flash_placement.xml" />
+      <file file_name="Philips_LPC210X_Startup.s" Name="Philips_LPC210X_Startup.s" />
      </folder>
      <folder Name="FreeRTOS Source" >
        <configuration filter="" Name="Common" />
@@ -45,6 +45,7 @@
        <file file_name="../Common/Minimal/PollQ.c" Name="PollQ.c" />
      </folder>
      <configuration c_preprocessor_definitions="" c_user_include_directories="" Name="Debug" />
+    <configuration arm_target_loader_parameter="14745600" oscillator_frequency="14.7456MHz" Name="THUMB Flash Debug" linker_output_format="hex" />
    </project>
    <configuration inherited_configurations="THUMB;Flash;Debug" Name="THUMB Flash Debug" />
    <configuration arm_library_instruction_set="THUMB" c_preprocessor_definitions="__THUMB" arm_instruction_set="THUMB" hidden="Yes" Name="THUMB" />
diff --git a/Demo/uIP_Demo_Rowley_ARM7/rtosdemo.hzs b/Demo/uIP_Demo_Rowley_ARM7/rtosdemo.hzs

index 8d14df8d1890af0d8aef7d1964d1093fd42ab5cd..61e9d913b67beb8ab453bb07db7925ac8a421a9f 100644 (file)
--- a/Demo/uIP_Demo_Rowley_ARM7/rtosdemo.hzs
+++ b/Demo/uIP_Demo_Rowley_ARM7/rtosdemo.hzs
@@ -1,6 +1,26 @@
  <!DOCTYPE CrossStudio_for_ARM_Session_File>
  <session>
- <Breakpoints/>
+ <Autos>
+  <Watches active="0" />
+ </Autos>
+ <Bookmarks/>
+ <Breakpoints>
+  <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="ARM Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="D_Abort" filename="" />
+  <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="ARM Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="3" mask="0" comparison="0" expression="FIQ" filename="" />
+  <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="ARM Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="3" mask="0" comparison="0" expression="IRQ" filename="" />
+  <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="ARM Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="P_Abort" filename="" />
+  <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="ARM Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="3" mask="0" comparison="0" expression="Reset" filename="" />
+  <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="ARM Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="3" mask="0" comparison="0" expression="SWI" filename="" />
+  <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="ARM Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="Undef" filename="" />
+  <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="Cortex-M3 Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="BusFault" filename="" />
+  <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="Cortex-M3 Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="ExceptionEntryReturnFault" filename="" />
+  <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="Cortex-M3 Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="HardFault" filename="" />
+  <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="Cortex-M3 Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="MemManage" filename="" />
+  <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="Cortex-M3 Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="3" mask="0" comparison="0" expression="Reset" filename="" />
+  <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="Cortex-M3 Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="UsageFault_CheckingError" filename="" />
+  <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="Cortex-M3 Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="UsageFault_Coprocessor" filename="" />
+  <BreakpointListItem actiontype="0" chainFrom="" line="-1" length="0" triggertype="0" useHWbreakpoint="false" group="Cortex-M3 Exceptions" breakdatatype="5" value="0" name="unnamed" counter="0" state="2" mask="0" comparison="0" expression="UsageFault_StateError" filename="" />
+ </Breakpoints>
   <ExecutionCountWindow/>
   <Memory1>
    <MemoryWindow autoEvaluate="0" addressText="" numColumns="8" sizeText="128" dataSize="1" radix="16" addressSpace="" />
@@ -17,11 +37,11 @@
   <Project>
    <ProjectSessionItem path="rtosdemo" name="unnamed" />
    <ProjectSessionItem path="rtosdemo;rtosdemo" name="unnamed" />
-  <ProjectSessionItem path="rtosdemo;rtosdemo;FreeRTOS Source" name="unnamed" />
-  <ProjectSessionItem path="rtosdemo;rtosdemo;uIP Source" name="unnamed" />
+  <ProjectSessionItem path="rtosdemo;rtosdemo;Demo App Source" name="unnamed" />
+  <ProjectSessionItem path="rtosdemo;rtosdemo;System Files" name="unnamed" />
   </Project>
   <Register1>
-  <RegisterWindow unsignedDisplays="" asciiDisplays="" octalDisplays="" openGroups="CPU - Current Mode" visibleGroups="CPU - Current Mode" decimalDisplays="" binaryDisplays="" />
+  <RegisterWindow unsignedDisplays="" asciiDisplays="" octalDisplays="" openGroups="" visibleGroups="CPU - Current Mode" decimalDisplays="" binaryDisplays="" />
   </Register1>
   <Register2>
    <RegisterWindow unsignedDisplays="" asciiDisplays="" octalDisplays="" openGroups="" visibleGroups="" decimalDisplays="" binaryDisplays="" />
@@ -49,7 +69,8 @@
    <Watches active="0" />
   </Watch4>
   <Files>
-  <SessionOpenFile useTextEdit="1" useBinaryEdit="0" x="0" debugPath="E:\Dev\FreeRTOS\Source\portable\GCC\ARM7_LPC2000\port.c" y="0" useHTMLEdit="0" path="E:\Dev\FreeRTOS\Source\portable\GCC\ARM7_LPC2000\port.c" left="0" selected="0" name="unnamed" top="0" />
+  <SessionOpenFile useTextEdit="1" useBinaryEdit="0" x="0" debugPath="C:\E\Dev\_FreeRTOS\Demo\uIP_Demo_Rowley_ARM7\main.c" y="219" useHTMLEdit="0" path="C:\E\Dev\_FreeRTOS\Demo\uIP_Demo_Rowley_ARM7\main.c" left="0" selected="0" name="unnamed" top="200" />
+  <SessionOpenFile useTextEdit="1" useBinaryEdit="0" x="0" debugPath="C:\E\Dev\_FreeRTOS\Demo\uIP_Demo_Rowley_ARM7\Philips_LPC210X_Startup.s" y="119" useHTMLEdit="0" path="C:\E\Dev\_FreeRTOS\Demo\uIP_Demo_Rowley_ARM7\Philips_LPC210X_Startup.s" left="0" selected="1" name="unnamed" top="34" />
   </Files>
- <ARMCrossStudioWindow activeProject="rtosdemo" ignoreExceptions="IRQ;FIQ;SWI" autoConnectTarget="/ARM Simulators/Simulator, LPC22xx" debugSearchFileMap="" fileDialogInitialDirectory="D:\FreeRTOS\Demo\uIP_Demo_Rowley_ARM7\uip" fileDialogDefaultFilter="*" autoConnectCapabilities="4543" debugSearchPath="" buildConfiguration="Release" />
+ <ARMCrossStudioWindow activeProject="rtosdemo" autoConnectTarget="/USB CrossConnect for ARM" debugSearchFileMap="" fileDialogInitialDirectory="C:\E\Dev\_FreeRTOS\Demo\uIP_Demo_Rowley_ARM7" fileDialogDefaultFilter="*" autoConnectCapabilities="0" debugSearchPath="" buildConfiguration="THUMB Flash Debug" />
  </session>
diff --git a/Demo/uIP_Demo_Rowley_ARM7/uip/cs8900a.c b/Demo/uIP_Demo_Rowley_ARM7/uip/cs8900a.c

index 3ae1b162f40a2181171e163d3b718893b1ca8837..331463a7811d580978db5df0118906af505202a1 100644 (file)
--- a/Demo/uIP_Demo_Rowley_ARM7/uip/cs8900a.c
+++ b/Demo/uIP_Demo_Rowley_ARM7/uip/cs8900a.c
@@ -1,6 +1,6 @@
  // cs8900a.c: device driver for the CS8900a chip in 8-bit mode.\r
  \r
-#include <targets/LPC210x.h>\r
+#include <LPC210x.h>\r
  \r
  #include "cs8900a.h"\r
  #include "uip.h"\r
@@ -270,25 +270,31 @@ const TInitSeq InitSeq[] =
  void\r
  cs8900a_write(unsigned addr, unsigned int data)\r
  {\r
-  IODIR |= 0xff << 16;                           // Data port to output\r
+  GPIO_IODIR |= 0xff << 16;                           // Data port to output\r
  \r
-  IOCLR = 0xf << 4;                              // Put address on bus\r
-  IOSET = addr << 4;\r
+  GPIO_IOCLR = 0xf << 4;                              // Put address on bus\r
+  GPIO_IOSET = addr << 4;\r
    \r
-  IOCLR = 0xff << 16;                            // Write low order byte to data bus\r
-  IOSET = data << 16;\r
-\r
-  IOCLR = IOW;                                   // Toggle IOW-signal\r
-  IOSET = IOW;\r
-\r
-  IOCLR = 0xf << 4;\r
-  IOSET = ((addr | 1) << 4);                     // And put next address on bus\r
-\r
-  IOCLR = 0xff << 16;                            // Write high order byte to data bus\r
-  IOSET = data >> 8 << 16;\r
-\r
-  IOCLR = IOW;                                   // Toggle IOW-signal\r
-  IOSET = IOW;\r
+  GPIO_IOCLR = 0xff << 16;                            // Write low order byte to data bus\r
+  GPIO_IOSET = data << 16;\r
+\r
+  asm volatile ( "NOP" );\r
+  GPIO_IOCLR = IOW;                                   // Toggle IOW-signal\r
+  asm volatile ( "NOP" );\r
+  GPIO_IOSET = IOW;\r
+  asm volatile ( "NOP" );\r
+\r
+  GPIO_IOCLR = 0xf << 4;\r
+  GPIO_IOSET = ((addr | 1) << 4);                     // And put next address on bus\r
+\r
+  GPIO_IOCLR = 0xff << 16;                            // Write high order byte to data bus\r
+  GPIO_IOSET = data >> 8 << 16;\r
+\r
+  asm volatile ( "NOP" );\r
+  GPIO_IOCLR = IOW;                                   // Toggle IOW-signal\r
+  asm volatile ( "NOP" );\r
+  GPIO_IOSET = IOW;\r
+  asm volatile ( "NOP" );\r
  }\r
  \r
  // Reads a word in little-endian byte order from a specified port-address\r
@@ -297,20 +303,24 @@ cs8900a_read(unsigned addr)
  {\r
    unsigned int value;\r
  \r
-  IODIR &= ~(0xff << 16);                        // Data port to input\r
+  GPIO_IODIR &= ~(0xff << 16);                        // Data port to input\r
  \r
-  IOCLR = 0xf << 4;                              // Put address on bus\r
-  IOSET = addr << 4;\r
+  GPIO_IOCLR = 0xf << 4;                              // Put address on bus\r
+  GPIO_IOSET = addr << 4;\r
  \r
-  IOCLR = IOR;                                   // IOR-signal low\r
-  value = (IOPIN >> 16) & 0xff;                  // get low order byte from data bus\r
-  IOSET = IOR;\r
+  asm volatile ( "NOP" );\r
+  GPIO_IOCLR = IOR;                                   // IOR-signal low\r
+  asm volatile ( "NOP" );\r
+  value = (GPIO_IOPIN >> 16) & 0xff;                  // get low order byte from data bus\r
+  GPIO_IOSET = IOR;\r
  \r
-  IOSET = 1 << 4;                                // IOR high and put next address on bus\r
+  GPIO_IOSET = 1 << 4;                                // IOR high and put next address on bus\r
  \r
-  IOCLR = IOR;                                   // IOR-signal low\r
-  value |= ((IOPIN >> 8) & 0xff00);              // get high order byte from data bus\r
-  IOSET = IOR;                                   // IOR-signal low\r
+  asm volatile ( "NOP" );\r
+  GPIO_IOCLR = IOR;                                   // IOR-signal low\r
+  asm volatile ( "NOP" );\r
+  value |= ((GPIO_IOPIN >> 8) & 0xff00);              // get high order byte from data bus\r
+  GPIO_IOSET = IOR;                                   // IOR-signal low\r
    \r
    return value;\r
  }\r
@@ -321,20 +331,24 @@ cs8900a_read_addr_high_first(unsigned addr)
  {\r
    unsigned int value;\r
  \r
-  IODIR &= ~(0xff << 16);                        // Data port to input\r
+  GPIO_IODIR &= ~(0xff << 16);                        // Data port to input\r
  \r
-  IOCLR = 0xf << 4;                              // Put address on bus\r
-  IOSET = (addr+1) << 4;\r
+  GPIO_IOCLR = 0xf << 4;                              // Put address on bus\r
+  GPIO_IOSET = (addr+1) << 4;\r
  \r
-  IOCLR = IOR;                                   // IOR-signal low\r
-  value = ((IOPIN >> 8) & 0xff00);               // get high order byte from data bus\r
-  IOSET = IOR;                                   // IOR-signal high\r
+  asm volatile ( "NOP" );\r
+  GPIO_IOCLR = IOR;                                   // IOR-signal low\r
+  asm volatile ( "NOP" );\r
+  value = ((GPIO_IOPIN >> 8) & 0xff00);               // get high order byte from data bus\r
+  GPIO_IOSET = IOR;                                   // IOR-signal high\r
  \r
-  IOCLR = 1 << 4;                                // Put low address on bus\r
+  GPIO_IOCLR = 1 << 4;                                // Put low address on bus\r
  \r
-  IOCLR = IOR;                                   // IOR-signal low\r
-  value |= (IOPIN >> 16) & 0xff;                 // get low order byte from data bus\r
-  IOSET = IOR;\r
+  asm volatile ( "NOP" );\r
+  GPIO_IOCLR = IOR;                                   // IOR-signal low\r
+  asm volatile ( "NOP" );\r
+  value |= (GPIO_IOPIN >> 16) & 0xff;                 // get low order byte from data bus\r
+  GPIO_IOSET = IOR;\r
  \r
    return value;\r
  }\r
@@ -345,16 +359,16 @@ cs8900a_init(void)
    int i;\r
  \r
    // Reset outputs, control lines high\r
-  IOSET = IOR | IOW;\r
+  GPIO_IOSET = IOR | IOW;\r
  \r
    // No LEDs on.\r
-  IOSET = LED_RED | LED_YELLOW | LED_GREEN;\r
+  GPIO_IOSET = LED_RED | LED_YELLOW | LED_GREEN;\r
  \r
    // Port 3 as output (all pins but RS232)\r
-  IODIR = ~0U; // everything to output.\r
+  GPIO_IODIR = ~0U; // everything to output.\r
  \r
    // Reset outputs\r
-  IOCLR = 0xff << 16;  // clear data outputs\r
+  GPIO_IOCLR = 0xff << 16;  // clear data outputs\r
  \r
    // Reset the CS8900A\r
    cs8900a_write(ADD_PORT, PP_SelfCTL);\r
@@ -378,7 +392,7 @@ cs8900a_send(void)
  {\r
    unsigned u;\r
  \r
-  IOCLR = LED_RED;  // Light RED LED when frame starting\r
+  GPIO_IOCLR = LED_RED;  // Light RED LED when frame starting\r
  \r
    // Transmit command\r
    cs8900a_write(TX_CMD_PORT, TX_START_ALL_BYTES);\r
@@ -394,7 +408,7 @@ cs8900a_send(void)
          break;\r
        if (u -- == 0)\r
          {\r
-          IOSET = LED_RED;  // Extinguish RED LED on end of frame\r
+          GPIO_IOSET = LED_RED;  // Extinguish RED LED on end of frame\r
            return;\r
          }\r
  \r
@@ -402,33 +416,37 @@ cs8900a_send(void)
        skip_frame();\r
      }\r
  \r
-  IODIR |= 0xff << 16;                           // Data port to output\r
+  GPIO_IODIR |= 0xff << 16;                           // Data port to output\r
  \r
    // Send 40+14=54 bytes of header\r
    for (u = 0; u < 54; u += 2)\r
      {\r
-      IOCLR = 0xf << 4;                              // Put address on bus\r
-      IOSET = TX_FRAME_PORT << 4;\r
+      GPIO_IOCLR = 0xf << 4;                              // Put address on bus\r
+      GPIO_IOSET = TX_FRAME_PORT << 4;\r
  \r
-      IOCLR = 0xff << 16;                            // Write low order byte to data bus\r
-      IOSET = uip_buf[u] << 16;                      // write low order byte to data bus\r
+      GPIO_IOCLR = 0xff << 16;                            // Write low order byte to data bus\r
+      GPIO_IOSET = uip_buf[u] << 16;                      // write low order byte to data bus\r
  \r
-      IOCLR = IOW;                                   // Toggle IOW-signal\r
-      IOSET = IOW;\r
+      asm volatile ( "NOP" );\r
+      GPIO_IOCLR = IOW;                                   // Toggle IOW-signal\r
+      asm volatile ( "NOP" );\r
+      GPIO_IOSET = IOW;\r
  \r
-      IOCLR = 0xf << 4;                              // Put address on bus\r
-      IOSET = (TX_FRAME_PORT | 1) << 4;              // and put next address on bus\r
+      GPIO_IOCLR = 0xf << 4;                              // Put address on bus\r
+      GPIO_IOSET = (TX_FRAME_PORT | 1) << 4;              // and put next address on bus\r
  \r
-      IOCLR = 0xff << 16;                            // Write low order byte to data bus\r
-      IOSET = uip_buf[u+1] << 16;                    // write low order byte to data bus\r
+      GPIO_IOCLR = 0xff << 16;                            // Write low order byte to data bus\r
+      GPIO_IOSET = uip_buf[u+1] << 16;                    // write low order byte to data bus\r
  \r
-      IOCLR = IOW;                                   // Toggle IOW-signal\r
-      IOSET = IOW;\r
+      asm volatile ( "NOP" );\r
+         GPIO_IOCLR = IOW;                                   // Toggle IOW-signal\r
+      asm volatile ( "NOP" );\r
+      GPIO_IOSET = IOW;\r
      }\r
  \r
    if (uip_len <= 54)\r
      {\r
-      IOSET = LED_RED;  // Extinguish RED LED on end of frame\r
+      GPIO_IOSET = LED_RED;  // Extinguish RED LED on end of frame\r
        return;\r
      }\r
  \r
@@ -437,26 +455,30 @@ cs8900a_send(void)
    for (u = 0; u < uip_len; u += 2)\r
      {\r
  \r
-      IOCLR = 0xf << 4;                          // Put address on bus\r
-      IOSET = TX_FRAME_PORT << 4;\r
+      GPIO_IOCLR = 0xf << 4;                          // Put address on bus\r
+      GPIO_IOSET = TX_FRAME_PORT << 4;\r
  \r
-      IOCLR = 0xff << 16;                        // Write low order byte to data bus\r
-      IOSET = uip_appdata[u] << 16;              // write low order byte to data bus\r
+      GPIO_IOCLR = 0xff << 16;                        // Write low order byte to data bus\r
+      GPIO_IOSET = uip_appdata[u] << 16;              // write low order byte to data bus\r
  \r
-      IOCLR = IOW;                               // Toggle IOW-signal\r
-      IOSET = IOW;\r
+      asm volatile ( "NOP" );\r
+         GPIO_IOCLR = IOW;                               // Toggle IOW-signal\r
+      asm volatile ( "NOP" );\r
+      GPIO_IOSET = IOW;\r
  \r
-      IOCLR = 0xf << 4;                          // Put address on bus\r
-      IOSET = (TX_FRAME_PORT | 1) << 4;          // and put next address on bus\r
+      GPIO_IOCLR = 0xf << 4;                          // Put address on bus\r
+      GPIO_IOSET = (TX_FRAME_PORT | 1) << 4;          // and put next address on bus\r
  \r
-      IOCLR = 0xff << 16;                        // Write low order byte to data bus\r
-      IOSET = uip_appdata[u+1] << 16;            // write low order byte to data bus\r
+      GPIO_IOCLR = 0xff << 16;                        // Write low order byte to data bus\r
+      GPIO_IOSET = uip_appdata[u+1] << 16;            // write low order byte to data bus\r
  \r
-      IOCLR = IOW;                               // Toggle IOW-signal\r
-      IOSET = IOW;\r
+      asm volatile ( "NOP" );\r
+         GPIO_IOCLR = IOW;                               // Toggle IOW-signal\r
+      asm volatile ( "NOP" );\r
+      GPIO_IOSET = IOW;\r
      }\r
  \r
-  IOSET = LED_RED;  // Extinguish RED LED on end of frame\r
+  GPIO_IOSET = LED_RED;  // Extinguish RED LED on end of frame\r
  }\r
  \r
  static void\r
@@ -477,7 +499,7 @@ cs8900a_poll(void)
    if ((cs8900a_read(DATA_PORT) & 0xd00) == 0)\r
      return 0;\r
  \r
-  IOCLR = LED_GREEN;  // Light GREED LED when frame coming in.\r
+  GPIO_IOCLR = LED_GREEN;  // Light GREED LED when frame coming in.\r
  \r
    // Read receiver status and discard it.\r
    cs8900a_read_addr_high_first(RX_FRAME_PORT);\r
@@ -493,30 +515,32 @@ cs8900a_poll(void)
      }\r
  \r
    // Data port to input\r
-  IODIR &= ~(0xff << 16);\r
+  GPIO_IODIR &= ~(0xff << 16);\r
  \r
-  IOCLR = 0xf << 4;                          // put address on bus\r
-  IOSET = RX_FRAME_PORT << 4; \r
+  GPIO_IOCLR = 0xf << 4;                          // put address on bus\r
+  GPIO_IOSET = RX_FRAME_PORT << 4; \r
  \r
    // Read bytes into uip_buf\r
    u = 0;\r
    while (u < len)\r
      {\r
-      IOCLR = 1 << 4;                            // put address on bus\r
+      GPIO_IOCLR = 1 << 4;                            // put address on bus\r
  \r
-      IOCLR = IOR;                               // IOR-signal low\r
-      uip_buf[u] = IOPIN >> 16;                // get high order byte from data bus\r
-      IOSET = IOR;                               // IOR-signal high\r
+      GPIO_IOCLR = IOR;                               // IOR-signal low\r
+      uip_buf[u] = GPIO_IOPIN >> 16;                // get high order byte from data bus\r
+      asm volatile ( "NOP" );\r
+      GPIO_IOSET = IOR;                               // IOR-signal high\r
  \r
-      IOSET = 1 << 4;                            // put address on bus\r
+      GPIO_IOSET = 1 << 4;                            // put address on bus\r
  \r
-      IOCLR = IOR;                               // IOR-signal low\r
-      uip_buf[u+1] = IOPIN >> 16;                  // get high order byte from data bus\r
-      IOSET = IOR;                               // IOR-signal high\r
+      GPIO_IOCLR = IOR;                               // IOR-signal low\r
+      asm volatile ( "NOP" );\r
+      uip_buf[u+1] = GPIO_IOPIN >> 16;                  // get high order byte from data bus\r
+      GPIO_IOSET = IOR;                               // IOR-signal high\r
        u += 2;\r
      }\r
  \r
-  IOSET = LED_GREEN;  // Extinguish GREED LED when frame finished.\r
+  GPIO_IOSET = LED_GREEN;  // Extinguish GREED LED when frame finished.\r
    return len;\r
  }\r
  \r
diff --git a/License/license.txt b/License/license.txt

index 41a77abc494a1c86cb53c3964deb85afcb6767af..1787b6ad159677badbd70278e408b22a0b2b980b 100644 (file)
--- a/License/license.txt
+++ b/License/license.txt
@@ -27,11 +27,12 @@ and are NOT COVERED BY THE GPL.
     adhered to.\r
  \r
  4) All files contained within the FreeRTOS\Demo\CORTEX_LM3S102_GCC\hw_include\r
-   directory.  The copyright of these files is owned by Luminary Micro.\r
-   Permission has been granted by Luminary Micro for these files to be \r
-   included in the FreeRTOS download.  Users must ensure the license \r
-   conditions stated at the top of the human readable files are understood \r
-   and adhered at all times for all files in that directory.\r
+   and FreeRTOS\Demo\CORTEX_LM3S316_IAR\hw_include directories.  The \r
+   copyright of these files is owned by Luminary Micro.  Permission has been \r
+   granted by Luminary Micro for these files to be included in the FreeRTOS \r
+   download.  Users must ensure the license conditions stated in the EULA.txt\r
+   file located in the same directories is understood and adhered at all \r
+   times for all files in those directories.\r
  \r
  5) The files contained within FreeRTOS\Demo\WizNET_DEMO_TERN_186\tern_code,\r
     which are slightly modified versions of code provided by and copyright to\r
diff --git a/Source/croutine.c b/Source/croutine.c

index ef7bc9227e2ed326679fea676ae7f404f70662bb..27ab0122b07b8515b02722fb27a98e93e7f5bc22 100644 (file)
--- a/Source/croutine.c
+++ b/Source/croutine.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/include/FreeRTOS.h b/Source/include/FreeRTOS.h

index bce527569e62034f8d0553f6cd4d155900c0abef..f85391ad0994ddb0d04db41ebe4a9c858bd382ac 100644 (file)
--- a/Source/include/FreeRTOS.h
+++ b/Source/include/FreeRTOS.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/include/croutine.h b/Source/include/croutine.h

index 0e06def2a8c0fe340754d96e005ea7269b5dbf70..9b52faba48c58f81464887e7d6293e51400fd7db 100644 (file)
--- a/Source/include/croutine.h
+++ b/Source/include/croutine.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/include/list.h b/Source/include/list.h

index 3d53b8dba4d7e314e01d89198a2a7a616827e48c..bb4bb6f0c18f2a7258c14160ac1be058c1965209 100644 (file)
--- a/Source/include/list.h
+++ b/Source/include/list.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/include/portable.h b/Source/include/portable.h

index be2d9dfcf45541bfef63a6187d34ce1cd4e63ab9..f08e5685ad2fb62c53657a8772417a7d1b587479 100644 (file)
--- a/Source/include/portable.h
+++ b/Source/include/portable.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
@@ -117,6 +117,10 @@
         #include "../../Source/portable/GCC/ARM_CM3/portmacro.h"\r
  #endif\r
  \r
+#ifdef IAR_ARMCM3_LM\r
+       #include "../../Source/portable/IAR/ARM_CM3/portmacro.h"\r
+#endif\r
+       \r
  #ifdef HCS12_CODE_WARRIOR\r
         #include "../../Source/portable/CodeWarrior/HCS12/portmacro.h"\r
  #endif \r
diff --git a/Source/include/projdefs.h b/Source/include/projdefs.h

index b1ecb57acae656646ebcc28445a288346189654b..0a9e49965653739b45e848932be3072c1ec5da6e 100644 (file)
--- a/Source/include/projdefs.h
+++ b/Source/include/projdefs.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/include/queue.h b/Source/include/queue.h

index 7e4e534bf5223d6f988735b248c468e74accd288..1adfa6e5772a858616584bec2d0fab32d47f089c 100644 (file)
--- a/Source/include/queue.h
+++ b/Source/include/queue.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/include/semphr.h b/Source/include/semphr.h

index 820bb3de6d698100e86f80f276e292aed75cb424..34ccf329d53e73ad5f39d2e94c943f5a61503325 100644 (file)
--- a/Source/include/semphr.h
+++ b/Source/include/semphr.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/include/task.h b/Source/include/task.h

index b80b2e023abeb562e969215b550a76b8407b83f9..79ba28940e3ce1fe99ef0b97cde37a44b9a2532b 100644 (file)
--- a/Source/include/task.h
+++ b/Source/include/task.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
@@ -40,7 +40,7 @@
   * MACROS AND DEFINITIONS\r
   *----------------------------------------------------------*/\r
  \r
-#define tskKERNEL_VERSION_NUMBER "V4.0.2"\r
+#define tskKERNEL_VERSION_NUMBER "V4.0.3"\r
  \r
  /**\r
   * task. h\r
diff --git a/Source/list.c b/Source/list.c

index e5ca6aa6dddf7339b81f3366ef5f214626dbc8cf..bd81688fa419b38c45e508eb6479cc60846a0dbb 100644 (file)
--- a/Source/list.c
+++ b/Source/list.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/BCC/16BitDOS/Flsh186/port.c b/Source/portable/BCC/16BitDOS/Flsh186/port.c

index e91403af51e43c682602ee960fc06ab541715af8..6a89d5a35a8b5813c0ddb9e61be0fd8d66f7cc62 100644 (file)
--- a/Source/portable/BCC/16BitDOS/Flsh186/port.c
+++ b/Source/portable/BCC/16BitDOS/Flsh186/port.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/BCC/16BitDOS/Flsh186/prtmacro.h b/Source/portable/BCC/16BitDOS/Flsh186/prtmacro.h

index ba3148042c0f16884a8eb53257bc813e7c07fcd6..271d0e925b7ef2607120230d2f0576770bd738d2 100644 (file)
--- a/Source/portable/BCC/16BitDOS/Flsh186/prtmacro.h
+++ b/Source/portable/BCC/16BitDOS/Flsh186/prtmacro.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/BCC/16BitDOS/PC/port.c b/Source/portable/BCC/16BitDOS/PC/port.c

index 1d0cc0e7fdd07b8fe940b773004a10e97b1475e7..1d016059938ebb3a8424ca4276ca84cb4711b5e9 100644 (file)
--- a/Source/portable/BCC/16BitDOS/PC/port.c
+++ b/Source/portable/BCC/16BitDOS/PC/port.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/BCC/16BitDOS/PC/prtmacro.h b/Source/portable/BCC/16BitDOS/PC/prtmacro.h

index 5c533dd7935dfd9ac7b2d43c96fb33909b8b6e3a..f8afa0e5ce29845d1f50c98adc59bb177a9f5828 100644 (file)
--- a/Source/portable/BCC/16BitDOS/PC/prtmacro.h
+++ b/Source/portable/BCC/16BitDOS/PC/prtmacro.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/BCC/16BitDOS/common/portasm.h b/Source/portable/BCC/16BitDOS/common/portasm.h

index d76908f39dfa6cac57ffe4c35a3125e0a495e3d4..07c735a37634178589eaad8b32530dd8899c8e11 100644 (file)
--- a/Source/portable/BCC/16BitDOS/common/portasm.h
+++ b/Source/portable/BCC/16BitDOS/common/portasm.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/BCC/16BitDOS/common/portcomn.c b/Source/portable/BCC/16BitDOS/common/portcomn.c

index 9cc696c77ec912fca241e46d6e3da87482e00587..f3060cd801a09c0324325e5abf5b99bf8cecd691 100644 (file)
--- a/Source/portable/BCC/16BitDOS/common/portcomn.c
+++ b/Source/portable/BCC/16BitDOS/common/portcomn.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/CodeWarrior/HCS12/port.c b/Source/portable/CodeWarrior/HCS12/port.c

index 9aac6b4831d77830348afe5d502471598ad809a4..607d89a382b63f88a19adc47b83cfdecc90debff 100644 (file)
--- a/Source/portable/CodeWarrior/HCS12/port.c
+++ b/Source/portable/CodeWarrior/HCS12/port.c
@@ -1,5 +1,5 @@
  /* \r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/CodeWarrior/HCS12/portmacro.h b/Source/portable/CodeWarrior/HCS12/portmacro.h

index ca8fc0e3dbc43778ce233e5167b05d541a65e19e..44d9945d3b8c6cd84776095a5c18deda661e3802 100644 (file)
--- a/Source/portable/CodeWarrior/HCS12/portmacro.h
+++ b/Source/portable/CodeWarrior/HCS12/portmacro.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/GCC/ARM7_AT91FR40008/port.c b/Source/portable/GCC/ARM7_AT91FR40008/port.c

index c876a0c008dd8aabf68c63af08daa46612e2302a..d55b0d83c3c8d3e7e27f8a0ac3bdd4549389eb25 100644 (file)
--- a/Source/portable/GCC/ARM7_AT91FR40008/port.c
+++ b/Source/portable/GCC/ARM7_AT91FR40008/port.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/GCC/ARM7_AT91FR40008/portISR.c b/Source/portable/GCC/ARM7_AT91FR40008/portISR.c

index 351e013a5541293f615730a8b46b9b467a211676..62d0193c1c2a77e5a6af878b440130f799876f08 100644 (file)
--- a/Source/portable/GCC/ARM7_AT91FR40008/portISR.c
+++ b/Source/portable/GCC/ARM7_AT91FR40008/portISR.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h b/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h

index e372471020bf9e1da070085a52bb85306d23b906..1ca5a9372f2be37c3e81291811c31da16abc11cb 100644 (file)
--- a/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h
+++ b/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/GCC/ARM7_AT91SAM7S/port.c b/Source/portable/GCC/ARM7_AT91SAM7S/port.c

index 0cab44f13637f5973d863d9b0e69540aa39ace5c..fc2161fa6a1831a3b900151ed218fb7280514c7a 100644 (file)
--- a/Source/portable/GCC/ARM7_AT91SAM7S/port.c
+++ b/Source/portable/GCC/ARM7_AT91SAM7S/port.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/GCC/ARM7_AT91SAM7S/portISR.c b/Source/portable/GCC/ARM7_AT91SAM7S/portISR.c

index 3c0885ef8f9dca0abc57a039687f462b244f57dd..64bd12048d038ce67798fb5cb945fe2ed2ac8734 100644 (file)
--- a/Source/portable/GCC/ARM7_AT91SAM7S/portISR.c
+++ b/Source/portable/GCC/ARM7_AT91SAM7S/portISR.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h b/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h

index c84501940ebff1055e6f9a9bbd418cc82c19116e..8e9f35cc95c97a20e1febb5fba4951fb06b40f9b 100644 (file)
--- a/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h
+++ b/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/GCC/ARM7_LPC2000/port.c b/Source/portable/GCC/ARM7_LPC2000/port.c

index e6b2f2e11fa0d5a84f2d0509ec5afff49623032d..0761c1973a8583cc5de031f033bef31ba61ab206 100644 (file)
--- a/Source/portable/GCC/ARM7_LPC2000/port.c
+++ b/Source/portable/GCC/ARM7_LPC2000/port.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/GCC/ARM7_LPC2000/portISR.c b/Source/portable/GCC/ARM7_LPC2000/portISR.c

index 02884c7a887bde1fc29d2838d8cd360536ef7725..5f60d6ac4a3429b0b308c3e40433768aaeb1e1fc 100644 (file)
--- a/Source/portable/GCC/ARM7_LPC2000/portISR.c
+++ b/Source/portable/GCC/ARM7_LPC2000/portISR.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/GCC/ARM7_LPC2000/portmacro.h b/Source/portable/GCC/ARM7_LPC2000/portmacro.h

index 7c98e220b0a96253e232f3cce9bbb7899a92d666..11a3ba566f3d9ec6a4f007379dca771c1831dec4 100644 (file)
--- a/Source/portable/GCC/ARM7_LPC2000/portmacro.h
+++ b/Source/portable/GCC/ARM7_LPC2000/portmacro.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/GCC/ARM_CM3/port.c b/Source/portable/GCC/ARM_CM3/port.c

index 2de4e07de903919aa13d9e0963e1e156b1627758..3b364b29911e143b5122ae24310ae3ade5af154d 100644 (file)
--- a/Source/portable/GCC/ARM_CM3/port.c
+++ b/Source/portable/GCC/ARM_CM3/port.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/GCC/ARM_CM3/portmacro.h b/Source/portable/GCC/ARM_CM3/portmacro.h

index d1fa1f7d81c88c4a1a1d76dac605839b6686afb0..6b2f4a45677dd4644226612fb4086ed4aaa52367 100644 (file)
--- a/Source/portable/GCC/ARM_CM3/portmacro.h
+++ b/Source/portable/GCC/ARM_CM3/portmacro.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/GCC/ATMega323/port.c b/Source/portable/GCC/ATMega323/port.c

index 9edfe9af4245421fa2683bd54cda1d753c204143..2120b1ea2d3c0b32922f237dde2b12179bae70ab 100644 (file)
--- a/Source/portable/GCC/ATMega323/port.c
+++ b/Source/portable/GCC/ATMega323/port.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/GCC/ATMega323/portmacro.h b/Source/portable/GCC/ATMega323/portmacro.h

index 7b4bbe82fdbb47abda0c45394073f107f488012b..edcc54359ea0362efd52d63e861c2e3cc0f36679 100644 (file)
--- a/Source/portable/GCC/ATMega323/portmacro.h
+++ b/Source/portable/GCC/ATMega323/portmacro.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/GCC/H8S2329/port.c b/Source/portable/GCC/H8S2329/port.c

index 1d7b9b27893d6eaa168082843b216eb1d807c44e..acff4884d264b7dcc4355cec1c46007f1ebb709f 100644 (file)
--- a/Source/portable/GCC/H8S2329/port.c
+++ b/Source/portable/GCC/H8S2329/port.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/GCC/H8S2329/portmacro.h b/Source/portable/GCC/H8S2329/portmacro.h

index b4d0f9edb6acb9e259033f6a5ef7a8f122ae3aa2..712203d780d5b6557d468afaa95547e4cb2e3cdb 100644 (file)
--- a/Source/portable/GCC/H8S2329/portmacro.h
+++ b/Source/portable/GCC/H8S2329/portmacro.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/GCC/HCS12/port.c b/Source/portable/GCC/HCS12/port.c

index 824afbbaf155529da368c730426842db8368fdc3..95e8064360b47fc0b25f5ddb43df5c23d6105ae3 100644 (file)
--- a/Source/portable/GCC/HCS12/port.c
+++ b/Source/portable/GCC/HCS12/port.c
@@ -1,5 +1,5 @@
  /* \r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003 - 2005 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003 - 2005 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/GCC/HCS12/portmacro.h b/Source/portable/GCC/HCS12/portmacro.h

index 850eb82cf44758914acdd4825d15c2be24411923..18de746613bfbb1f21232334768b845576b95e3b 100644 (file)
--- a/Source/portable/GCC/HCS12/portmacro.h
+++ b/Source/portable/GCC/HCS12/portmacro.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003 - 2005 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003 - 2005 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/GCC/MSP430F449/port.c b/Source/portable/GCC/MSP430F449/port.c

index e754e4b4feb8746dce08c72347b8e5f3adc8a32c..b07afacd5ff9ab49c45154521dc24079f46e0a34 100644 (file)
--- a/Source/portable/GCC/MSP430F449/port.c
+++ b/Source/portable/GCC/MSP430F449/port.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/GCC/MSP430F449/portmacro.h b/Source/portable/GCC/MSP430F449/portmacro.h

index e6b6015b9873507364d4ff71dd7c6c2815b48356..45d54b7b05027f9e73cde76220663ecaeba94f33 100644 (file)
--- a/Source/portable/GCC/MSP430F449/portmacro.h
+++ b/Source/portable/GCC/MSP430F449/portmacro.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/GCC/MicroBlaze/port.c b/Source/portable/GCC/MicroBlaze/port.c

index efc702ecda0c31f7d2c6944136b88091ab23a67b..deaec8b7841312b3a77483b5f78661b0fc4b0468 100644 (file)
--- a/Source/portable/GCC/MicroBlaze/port.c
+++ b/Source/portable/GCC/MicroBlaze/port.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/GCC/MicroBlaze/portmacro.h b/Source/portable/GCC/MicroBlaze/portmacro.h

index 7eef09c57247c3f0c2c86e1c5be7e781a8f50197..846fd1cc495b2a7d07d2dacdf60a7156cfd71845 100644 (file)
--- a/Source/portable/GCC/MicroBlaze/portmacro.h
+++ b/Source/portable/GCC/MicroBlaze/portmacro.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/IAR/ARM_CM3/port.c b/Source/portable/IAR/ARM_CM3/port.c

new file mode 100644 (file)

index 0000000..8040085
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM3/port.c
@@ -0,0 +1,170 @@
+/*\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+       This file is part of the FreeRTOS.org distribution.\r
+\r
+       FreeRTOS.org is free software; you can redistribute it and/or modify\r
+       it under the terms of the GNU General Public License as published by\r
+       the Free Software Foundation; either version 2 of the License, or\r
+       (at your option) any later version.\r
+\r
+       FreeRTOS.org is distributed in the hope that it will be useful,\r
+       but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+       GNU General Public License for more details.\r
+\r
+       You should have received a copy of the GNU General Public License\r
+       along with FreeRTOS.org; if not, write to the Free Software\r
+       Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\r
+\r
+       A special exception to the GPL can be applied should you wish to distribute\r
+       a combined work that includes FreeRTOS.org, without being obliged to provide\r
+       the source code for any proprietary components.  See the licensing section \r
+       of http://www.FreeRTOS.org for full details of how and when the exception\r
+       can be applied.\r
+\r
+       ***************************************************************************\r
+       See http://www.FreeRTOS.org for documentation, latest information, license \r
+       and contact details.  Please ensure to read the configuration and relevant \r
+       port sections of the online documentation.\r
+       ***************************************************************************\r
+*/\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * Implementation of functions defined in portable.h for the ARM CM3 port.\r
+ *----------------------------------------------------------*/\r
+\r
+/* Scheduler includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Constants required to manipulate the NVIC. */\r
+#define portNVIC_SYSTICK_CTRL          ( ( volatile unsigned portLONG *) 0xe000e010 )\r
+#define portNVIC_SYSTICK_LOAD          ( ( volatile unsigned portLONG *) 0xe000e014 )\r
+#define portNVIC_INT_CTRL                      ( ( volatile unsigned portLONG *) 0xe000ed04 )\r
+#define portNVIC_SYSPRI2                       ( ( volatile unsigned portLONG *) 0xe000ed20 )\r
+#define portNVIC_SYSPRI1                       ( ( volatile unsigned portLONG *) 0xe000ed1c )\r
+#define portNVIC_SYSTICK_CLK           0x00000004\r
+#define portNVIC_SYSTICK_INT           0x00000002\r
+#define portNVIC_SYSTICK_ENABLE                0x00000001\r
+#define portNVIC_PENDSVSET                     0x10000000\r
+#define portNVIC_PENDSV_PRI                    0x00ff0000\r
+#define portNVIC_SVCALL_PRI                    0xff000000\r
+#define portNVIC_SYSTICK_PRI           0xff000000\r
+\r
+/* Constants required to set up the initial stack. */\r
+#define portINITIAL_XPSR                       ( 0x01000000 )\r
+\r
+/* Each task maintains its own interrupt status in the critical nesting\r
+variable. */\r
+unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
+\r
+/* \r
+ * Setup the timer to generate the tick interrupts.\r
+ */\r
+static void prvSetupTimerInterrupt( void );\r
+\r
+/*\r
+ * Set the MSP/PSP to a known value.\r
+ */\r
+extern void vSetMSP( unsigned long ulValue );\r
+extern void vSetPSP( unsigned long ulValue );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * See header file for description. \r
+ */\r
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
+{\r
+       /* Simulate the stack frame as it would be created by a context switch\r
+       interrupt. */\r
+       *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
+       pxTopOfStack--;\r
+       *pxTopOfStack = ( portSTACK_TYPE ) pxCode;      /* PC */\r
+       pxTopOfStack--;\r
+       *pxTopOfStack = 0xfffffffd;     /* LR */\r
+       pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
+       *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;        /* R0 */\r
+       pxTopOfStack -= 9;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
+       *pxTopOfStack = 0x00000000; /* uxCriticalNesting. */\r
+\r
+       return pxTopOfStack;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* \r
+ * See header file for description. \r
+ */\r
+portBASE_TYPE xPortStartScheduler( void )\r
+{\r
+       /* Make PendSV, CallSV and SysTick the lowest priority interrupts. */\r
+       *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;\r
+       *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;\r
+\r
+       /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
+       here already. */\r
+       prvSetupTimerInterrupt();\r
+       \r
+       /* Start the first task. */\r
+       vSetPSP( 0 );\r
+       vSetMSP( *((unsigned portLONG *) 0 ) );\r
+       *(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET;\r
+\r
+       /* Enable interrupts */\r
+       portENABLE_INTERRUPTS();\r
+\r
+       /* Should not get here! */\r
+       return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEndScheduler( void )\r
+{\r
+       /* It is unlikely that the CM3 port will require this function as there\r
+       is nothing to return to.  */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortYieldFromISR( void )\r
+{\r
+       /* Set a PendSV to request a context switch. */\r
+       *(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET;\r
+\r
+       /* This function is also called in response to a Yield(), so we want\r
+       the yield to occur immediately. */\r
+       portENABLE_INTERRUPTS();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortEnterCritical( void )\r
+{\r
+       portDISABLE_INTERRUPTS();\r
+       uxCriticalNesting++;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortExitCritical( void )\r
+{\r
+       uxCriticalNesting--;\r
+       if( uxCriticalNesting == 0 )\r
+       {\r
+               portENABLE_INTERRUPTS();\r
+       }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+/*\r
+ * Setup the systick timer to generate the tick interrupts at the required\r
+ * frequency.\r
+ */\r
+void prvSetupTimerInterrupt( void )\r
+{\r
+       /* Configure SysTick to interrupt at the requested rate. */\r
+       *(portNVIC_SYSTICK_LOAD) = configCPU_CLOCK_HZ / configTICK_RATE_HZ;\r
+       *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
+}\r
+\r
+\r
diff --git a/Source/portable/IAR/ARM_CM3/portasm.s b/Source/portable/IAR/ARM_CM3/portasm.s

new file mode 100644 (file)

index 0000000..a809e3a
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM3/portasm.s
@@ -0,0 +1,129 @@
+/*\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+       This file is part of the FreeRTOS.org distribution.\r
+\r
+       FreeRTOS.org is free software; you can redistribute it and/or modify\r
+       it under the terms of the GNU General Public License as published by\r
+       the Free Software Foundation; either version 2 of the License, or\r
+       (at your option) any later version.\r
+\r
+       FreeRTOS.org is distributed in the hope that it will be useful,\r
+       but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+       GNU General Public License for more details.\r
+\r
+       You should have received a copy of the GNU General Public License\r
+       along with FreeRTOS.org; if not, write to the Free Software\r
+       Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\r
+\r
+       A special exception to the GPL can be applied should you wish to distribute\r
+       a combined work that includes FreeRTOS.org, without being obliged to provide\r
+       the source code for any proprietary components.  See the licensing section \r
+       of http://www.FreeRTOS.org for full details of how and when the exception\r
+       can be applied.\r
+\r
+       ***************************************************************************\r
+       See http://www.FreeRTOS.org for documentation, latest information, license \r
+       and contact details.  Please ensure to read the configuration and relevant \r
+       port sections of the online documentation.\r
+       ***************************************************************************\r
+*/\r
+#include <FreeRTOSConfig.h>\r
+       \r
+       RSEG ICODE:CODE\r
+\r
+       EXTERN vPortYieldFromISR\r
+       EXTERN vTaskSwitchContext\r
+       EXTERN vTaskIncrementTick\r
+       EXTERN uxCriticalNesting\r
+       EXTERN pxCurrentTCB\r
+\r
+       PUBLIC vSetPSP\r
+       PUBLIC vSetMSP\r
+       PUBLIC xPortPendSVHandler\r
+       PUBLIC xPortSysTickHandler\r
+\r
+\r
+vSetPSP:\r
+       msr psp, r0\r
+       bx lr\r
+/*-----------------------------------------------------------*/\r
+\r
+vSetMSP\r
+       msr msp, r0\r
+       bx lr\r
+/*-----------------------------------------------------------*/\r
+\r
+xPortPendSVHandler:\r
+       mrs r0, psp\r
+       cbz r0, no_save\r
+       /* Save the context into the TCB. */                                    \r
+       sub r0, r0, #0x20\r
+       stm r0, {r4-r11}\r
+       nop\r
+       sub r0, r0, #0x04\r
+       ldr r1, =uxCriticalNesting\r
+       ldr r1, [r1]\r
+       str R1, [r0, #0x00]\r
+       ldr r1, =pxCurrentTCB\r
+       ldr r1, [r1]\r
+       str r0, [r1]\r
+no_save:\r
+       ldr r0, =vTaskSwitchContext\r
+       push {r14}\r
+       cpsid i\r
+       blx r0\r
+       cpsie i\r
+       pop {r14}\r
+       \r
+       /* Restore the context. */      \r
+       ldr r1, =pxCurrentTCB\r
+       ldr r1, [r1]\r
+       ldr r0, [r1]\r
+       ldm r0, {r1, r4-r11}\r
+       nop\r
+       ldr r2, =uxCriticalNesting\r
+       str r1, [r2]\r
+       add r0, r0, #0x24\r
+       msr psp, r0\r
+       orr r14, r14, #0xd\r
+       /* Exit with interrupts in the state required by the task. */   \r
+       cbnz r1, sv_disable_interrupts\r
+       bx r14\r
+       \r
+sv_disable_interrupts:\r
+       cpsid i\r
+       bx r14\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+xPortSysTickHandler:\r
+       /* Call the scheduler tick function. */\r
+       ldr r0, =vTaskIncrementTick\r
+       push {r14}\r
+       cpsid i\r
+       blx r0\r
+       cpsie i\r
+       pop {r14} \r
+       \r
+       /* If using preemption, also force a context switch. */\r
+       #if configUSE_PREEMPTION == 1\r
+               push {r14}\r
+               ldr r0, =vPortYieldFromISR\r
+               blx r0\r
+               pop {r14} \r
+       #endif\r
+\r
+       /* Exit with interrupts in the correct state. */\r
+    ldr r2, =uxCriticalNesting\r
+       ldr r2, [r2]\r
+       cbnz r2, tick_disable_interrupts\r
+       bx r14 \r
+\r
+tick_disable_interrupts:\r
+       cpsid i\r
+       bx r14\r
+\r
+       END\r
+/*-----------------------------------------------------------*/\r
diff --git a/Source/portable/IAR/ARM_CM3/portmacro.h b/Source/portable/IAR/ARM_CM3/portmacro.h

new file mode 100644 (file)

index 0000000..c2736bd
--- /dev/null
+++ b/Source/portable/IAR/ARM_CM3/portmacro.h
@@ -0,0 +1,101 @@
+/*\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
+\r
+       This file is part of the FreeRTOS.org distribution.\r
+\r
+       FreeRTOS.org is free software; you can redistribute it and/or modify\r
+       it under the terms of the GNU General Public License as published by\r
+       the Free Software Foundation; either version 2 of the License, or\r
+       (at your option) any later version.\r
+\r
+       FreeRTOS.org is distributed in the hope that it will be useful,\r
+       but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
+       GNU General Public License for more details.\r
+\r
+       You should have received a copy of the GNU General Public License\r
+       along with FreeRTOS.org; if not, write to the Free Software\r
+       Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\r
+\r
+       A special exception to the GPL can be applied should you wish to distribute\r
+       a combined work that includes FreeRTOS.org, without being obliged to provide\r
+       the source code for any proprietary components.  See the licensing section \r
+       of http://www.FreeRTOS.org for full details of how and when the exception\r
+       can be applied.\r
+\r
+       ***************************************************************************\r
+       See http://www.FreeRTOS.org for documentation, latest information, license \r
+       and contact details.  Please ensure to read the configuration and relevant \r
+       port sections of the online documentation.\r
+       ***************************************************************************\r
+*/\r
+\r
+\r
+#ifndef PORTMACRO_H\r
+#define PORTMACRO_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Port specific definitions.  \r
+ *\r
+ * The settings in this file configure FreeRTOS correctly for the\r
+ * given hardware and compiler.\r
+ *\r
+ * These settings should not be altered.\r
+ *-----------------------------------------------------------\r
+ */\r
+\r
+/* Type definitions. */\r
+#define portCHAR               char\r
+#define portFLOAT              float\r
+#define portDOUBLE             double\r
+#define portLONG               long\r
+#define portSHORT              short\r
+#define portSTACK_TYPE unsigned portLONG\r
+#define portBASE_TYPE  long\r
+\r
+#if( configUSE_16_BIT_TICKS == 1 )\r
+       typedef unsigned portSHORT portTickType;\r
+       #define portMAX_DELAY ( portTickType ) 0xffff\r
+#else\r
+       typedef unsigned portLONG portTickType;\r
+       #define portMAX_DELAY ( portTickType ) 0xffffffff\r
+#endif\r
+/*-----------------------------------------------------------*/        \r
+\r
+/* Architecture specifics. */\r
+#define portSTACK_GROWTH                       ( -1 )\r
+#define portTICK_RATE_MS                       ( ( portTickType ) 1000 / configTICK_RATE_HZ )          \r
+#define portBYTE_ALIGNMENT                     4\r
+/*-----------------------------------------------------------*/        \r
+\r
+\r
+/* Scheduler utilities. */\r
+extern void vPortYieldFromISR( void );\r
+\r
+#define portYIELD()                                    vPortYieldFromISR()\r
+\r
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYieldFromISR()\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+/* Critical section management. */\r
+\r
+extern void vPortEnableInterrupts( void );\r
+extern void vPortEnterCritical( void );\r
+extern void vPortExitCritical( void );\r
+\r
+#define portDISABLE_INTERRUPTS()       __asm ( "cpsid i" )\r
+#define portENABLE_INTERRUPTS()                __asm ( "cpsie i" )\r
+#define portENTER_CRITICAL()           vPortEnterCritical()\r
+#define portEXIT_CRITICAL()                    vPortExitCritical()\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Task function macros as described on the FreeRTOS.org WEB site. */\r
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\r
+\r
+#define inline\r
+#define portNOP()\r
+\r
+#endif /* PORTMACRO_H */\r
+\r
diff --git a/Source/portable/IAR/ATMega323/port.c b/Source/portable/IAR/ATMega323/port.c

index 688f6fb6d24de66c662ddf343f96f66c5a8ac85f..c65f9ed1aa5ca98b01a9a649b9cb900889cc9e2a 100644 (file)
--- a/Source/portable/IAR/ATMega323/port.c
+++ b/Source/portable/IAR/ATMega323/port.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/IAR/ATMega323/portmacro.h b/Source/portable/IAR/ATMega323/portmacro.h

index c9b19293fd2263b0cf6ca86701278f25c90473be..08211c5b267cc458e10455117573f16f5764d2d2 100644 (file)
--- a/Source/portable/IAR/ATMega323/portmacro.h
+++ b/Source/portable/IAR/ATMega323/portmacro.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/IAR/ATMega323/portmacro.s90 b/Source/portable/IAR/ATMega323/portmacro.s90

index ea2fef4283e9f4b4e86d5f859c5811928f0af6db..ed252106af83f77c08c9a12b1a8faa8fa637222a 100644 (file)
--- a/Source/portable/IAR/ATMega323/portmacro.s90
+++ b/Source/portable/IAR/ATMega323/portmacro.s90
@@ -1,4 +1,4 @@
-;      FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+;      FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  ;\r
  ;      This file is part of the FreeRTOS.org distribution.\r
  ;\r
diff --git a/Source/portable/IAR/AtmelSAM7S64/port.c b/Source/portable/IAR/AtmelSAM7S64/port.c

index fb669e1f813ccbe0503f5ccb2443edb69a2e2c9f..a45521f9b3376ae9ef5e2539061e1dff351148a5 100644 (file)
--- a/Source/portable/IAR/AtmelSAM7S64/port.c
+++ b/Source/portable/IAR/AtmelSAM7S64/port.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/IAR/AtmelSAM7S64/portmacro.h b/Source/portable/IAR/AtmelSAM7S64/portmacro.h

index dbb603d857c83c3269c8355fa5d20b5d4b5cca70..b7c0ec7161872e206fa248e9943276d932a20546 100644 (file)
--- a/Source/portable/IAR/AtmelSAM7S64/portmacro.h
+++ b/Source/portable/IAR/AtmelSAM7S64/portmacro.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/IAR/LPC2000/port.c b/Source/portable/IAR/LPC2000/port.c

index de8175785052fd4755b7f4ea2c9cd1f5e410f47f..db409be28ca6905eca0313b6820e0db700ca69e3 100644 (file)
--- a/Source/portable/IAR/LPC2000/port.c
+++ b/Source/portable/IAR/LPC2000/port.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/IAR/LPC2000/portmacro.h b/Source/portable/IAR/LPC2000/portmacro.h

index dbb603d857c83c3269c8355fa5d20b5d4b5cca70..b7c0ec7161872e206fa248e9943276d932a20546 100644 (file)
--- a/Source/portable/IAR/LPC2000/portmacro.h
+++ b/Source/portable/IAR/LPC2000/portmacro.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/IAR/STR71x/port.c b/Source/portable/IAR/STR71x/port.c

index 45ff4961d58e006fa4e54eabf5bb154edd5944f5..fe49421b478115997fe393141365738218e37ae2 100644 (file)
--- a/Source/portable/IAR/STR71x/port.c
+++ b/Source/portable/IAR/STR71x/port.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/IAR/STR71x/portmacro.h b/Source/portable/IAR/STR71x/portmacro.h

index a2f3239e9e361f75eb8258b864707fa92aff8974..84cc8e59f4d21de95e01874fb7daf2e0432112e6 100644 (file)
--- a/Source/portable/IAR/STR71x/portmacro.h
+++ b/Source/portable/IAR/STR71x/portmacro.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/Keil/ARM7/port.c b/Source/portable/Keil/ARM7/port.c

index 0d76bfb265adf044316efbd123d8edc9e0df5e9e..042e361e35926f2464c791c9ef1e60ce80d08b30 100644 (file)
--- a/Source/portable/Keil/ARM7/port.c
+++ b/Source/portable/Keil/ARM7/port.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/Keil/ARM7/portISR.c b/Source/portable/Keil/ARM7/portISR.c

index 24a7a32c6c54424b31a95a1bec42de46e174751a..ca12f7c47f580f68d3ed8046ad91b03a4b215741 100644 (file)
--- a/Source/portable/Keil/ARM7/portISR.c
+++ b/Source/portable/Keil/ARM7/portISR.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/Keil/ARM7/portmacro.h b/Source/portable/Keil/ARM7/portmacro.h

index 6393c9cceeacc0cfd660e4e192050f3806d52cd5..e651a332697793d252a59047eafc7208ae26a392 100644 (file)
--- a/Source/portable/Keil/ARM7/portmacro.h
+++ b/Source/portable/Keil/ARM7/portmacro.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/MPLAB/PIC18F/port.c b/Source/portable/MPLAB/PIC18F/port.c

index 0bc30d8fa5e07376f5051c9cafce3a3a2b537de2..d29bf267ac63da00138be6f077ebe9bdef139313 100644 (file)
--- a/Source/portable/MPLAB/PIC18F/port.c
+++ b/Source/portable/MPLAB/PIC18F/port.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/MPLAB/PIC18F/portmacro.h b/Source/portable/MPLAB/PIC18F/portmacro.h

index c23fa0996added872c3cbd574f09bf6a22df1c2b..8b9c3aa876330a27eb26f2a36da9a5f5859e1423 100644 (file)
--- a/Source/portable/MPLAB/PIC18F/portmacro.h
+++ b/Source/portable/MPLAB/PIC18F/portmacro.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/MemMang/heap_1.c b/Source/portable/MemMang/heap_1.c

index bd8e2a03298725a9eab1489ba0a6a1369f99366e..67b5a52125131527648bb42dff677420254fc6f7 100644 (file)
--- a/Source/portable/MemMang/heap_1.c
+++ b/Source/portable/MemMang/heap_1.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/MemMang/heap_2.c b/Source/portable/MemMang/heap_2.c

index 6a1b00a7cd7b93b47fcdb959cdcdfe86a7a913dc..e3ec0ddeecd18bebefbc3bf0ec004a306db361e2 100644 (file)
--- a/Source/portable/MemMang/heap_2.c
+++ b/Source/portable/MemMang/heap_2.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/MemMang/heap_3.c b/Source/portable/MemMang/heap_3.c

index cca72608d2649ea7931eb73736f2d18b77515d86..1af9f6c1f2daf336eb45acc33faca51c35e972ad 100644 (file)
--- a/Source/portable/MemMang/heap_3.c
+++ b/Source/portable/MemMang/heap_3.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/Paradigm/Tern_EE/large_untested/port.c b/Source/portable/Paradigm/Tern_EE/large_untested/port.c

index c752694175179929ef9efdc9792296e8df50bba6..f827ce50ce8c94a49c05f53cc495c7f9a54c9fea 100644 (file)
--- a/Source/portable/Paradigm/Tern_EE/large_untested/port.c
+++ b/Source/portable/Paradigm/Tern_EE/large_untested/port.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/Paradigm/Tern_EE/large_untested/portasm.h b/Source/portable/Paradigm/Tern_EE/large_untested/portasm.h

index a0cd72730822247d77f7174753f1a64eeb31b714..6f13fe37a5dffd5a5eb3b1103815f4e0dffb4fd5 100644 (file)
--- a/Source/portable/Paradigm/Tern_EE/large_untested/portasm.h
+++ b/Source/portable/Paradigm/Tern_EE/large_untested/portasm.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/Paradigm/Tern_EE/large_untested/portmacro.h b/Source/portable/Paradigm/Tern_EE/large_untested/portmacro.h

index 163721152dc61ba72707efadab03561d81ba3340..8d5e8680cf433bdb4be4624927d250a1800f9abe 100644 (file)
--- a/Source/portable/Paradigm/Tern_EE/large_untested/portmacro.h
+++ b/Source/portable/Paradigm/Tern_EE/large_untested/portmacro.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/Paradigm/Tern_EE/small/PORTASM.bak b/Source/portable/Paradigm/Tern_EE/small/PORTASM.bak

index 9f943d03298c61e87201b718bdb1bbc7376dcfe7..c58a10b1e0196602c7f79a3b2b5c3921bea86aae 100644 (file)
--- a/Source/portable/Paradigm/Tern_EE/small/PORTASM.bak
+++ b/Source/portable/Paradigm/Tern_EE/small/PORTASM.bak
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/Paradigm/Tern_EE/small/port.bak b/Source/portable/Paradigm/Tern_EE/small/port.bak

index ab47b05dbc77966bcff16cbf07b1415f93f53a2d..f25fabd4d062f371551667c3f8edc58c645b9247 100644 (file)
--- a/Source/portable/Paradigm/Tern_EE/small/port.bak
+++ b/Source/portable/Paradigm/Tern_EE/small/port.bak
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/Paradigm/Tern_EE/small/port.c b/Source/portable/Paradigm/Tern_EE/small/port.c

index 3cb1de74deb3af9fb65f6b6cdd2f6684f77ae0f1..aef9c16e3964030325ec69091692ae3769a6f917 100644 (file)
--- a/Source/portable/Paradigm/Tern_EE/small/port.c
+++ b/Source/portable/Paradigm/Tern_EE/small/port.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/Paradigm/Tern_EE/small/portasm.h b/Source/portable/Paradigm/Tern_EE/small/portasm.h

index 546e54284f3e0f9624c02bf10e0aa1e0b7d46d81..7cc269fcf26740c2d9b20b2f242344cabea04ba0 100644 (file)
--- a/Source/portable/Paradigm/Tern_EE/small/portasm.h
+++ b/Source/portable/Paradigm/Tern_EE/small/portasm.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/Paradigm/Tern_EE/small/portmacro.h b/Source/portable/Paradigm/Tern_EE/small/portmacro.h

index 9f18dee727303a87e83e6a7edd3e727de7dd2a52..947bbbbe4bde2da2f39d7cbf74c0fccaa215502e 100644 (file)
--- a/Source/portable/Paradigm/Tern_EE/small/portmacro.h
+++ b/Source/portable/Paradigm/Tern_EE/small/portmacro.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/RVDS/ARM_CM3/port.c b/Source/portable/RVDS/ARM_CM3/port.c

index 1a4cdd7b5235f8901404e2f50105bc901eff422b..6473ab9c6abaed37d8077bcc1eba684cfca43aa0 100644 (file)
--- a/Source/portable/RVDS/ARM_CM3/port.c
+++ b/Source/portable/RVDS/ARM_CM3/port.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/RVDS/ARM_CM3/portmacro.h b/Source/portable/RVDS/ARM_CM3/portmacro.h

index b39f523f911961becb6c9af208e9f63ae95f738a..5efc8cc942af40b74968ab51598c3561954728d2 100644 (file)
--- a/Source/portable/RVDS/ARM_CM3/portmacro.h
+++ b/Source/portable/RVDS/ARM_CM3/portmacro.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/Rowley/MSP430F449/Port1/port.c b/Source/portable/Rowley/MSP430F449/Port1/port.c

index 5dd06833df042a5b28ef25e2189f19fafd45acbd..8a96ebcac6e9048ef286b8d88f8ea18ca6f3c20e 100644 (file)
--- a/Source/portable/Rowley/MSP430F449/Port1/port.c
+++ b/Source/portable/Rowley/MSP430F449/Port1/port.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/Rowley/MSP430F449/Port1/portmacro.h b/Source/portable/Rowley/MSP430F449/Port1/portmacro.h

index 201c2944fcedb393dcdb7492afe06a08a527b8e4..6f112880b1e9b777a9e139b75e07f2bdcdb5d8f7 100644 (file)
--- a/Source/portable/Rowley/MSP430F449/Port1/portmacro.h
+++ b/Source/portable/Rowley/MSP430F449/Port1/portmacro.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/Rowley/MSP430F449/Port2/port.c b/Source/portable/Rowley/MSP430F449/Port2/port.c

index ab89c9cf93210b844fb381303a8248a90fdb0ca4..4f2664c477f0749a7d3c69119c8aeb7d274c122e 100644 (file)
--- a/Source/portable/Rowley/MSP430F449/Port2/port.c
+++ b/Source/portable/Rowley/MSP430F449/Port2/port.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/Rowley/MSP430F449/Port2/portmacro.h b/Source/portable/Rowley/MSP430F449/Port2/portmacro.h

index bcfed6a78451d837e306c9c4fd9680f2249f1011..69f7c26d73fe89afde34eac52591014fb889983f 100644 (file)
--- a/Source/portable/Rowley/MSP430F449/Port2/portmacro.h
+++ b/Source/portable/Rowley/MSP430F449/Port2/portmacro.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/Rowley/MSP430F449/port.c b/Source/portable/Rowley/MSP430F449/port.c

index 5dd06833df042a5b28ef25e2189f19fafd45acbd..8a96ebcac6e9048ef286b8d88f8ea18ca6f3c20e 100644 (file)
--- a/Source/portable/Rowley/MSP430F449/port.c
+++ b/Source/portable/Rowley/MSP430F449/port.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/Rowley/MSP430F449/portmacro.h b/Source/portable/Rowley/MSP430F449/portmacro.h

index 0fa8b4e7844b6119dfe789c71d15398a7f7bae87..bc88ea02322d4d82bbfa0c4c8d411b15a697d116 100644 (file)
--- a/Source/portable/Rowley/MSP430F449/portmacro.h
+++ b/Source/portable/Rowley/MSP430F449/portmacro.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/SDCC/Cygnal/port.c b/Source/portable/SDCC/Cygnal/port.c

index 0cd19d89428b0b22bf7541723502c65a8176c412..10095973a5652283f328d18e0f27448fcd773100 100644 (file)
--- a/Source/portable/SDCC/Cygnal/port.c
+++ b/Source/portable/SDCC/Cygnal/port.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/SDCC/Cygnal/portmacro.h b/Source/portable/SDCC/Cygnal/portmacro.h

index 93cbe4174cd1c5338fff989009b99e7f8f11bd38..37b80b5aa6461cbdf0a0dec36d30d1510709d347 100644 (file)
--- a/Source/portable/SDCC/Cygnal/portmacro.h
+++ b/Source/portable/SDCC/Cygnal/portmacro.h
@@ -1,5 +1,5 @@
  /* \r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/WizC/PIC18/Drivers/Tick/Tick.c b/Source/portable/WizC/PIC18/Drivers/Tick/Tick.c

index 660a3aea89d13dcdba460474786205221bcbb26f..062bbd125dd9ae62c50d35bc810bedd84a71f576 100644 (file)
--- a/Source/portable/WizC/PIC18/Drivers/Tick/Tick.c
+++ b/Source/portable/WizC/PIC18/Drivers/Tick/Tick.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/WizC/PIC18/Drivers/Tick/isrTick.c b/Source/portable/WizC/PIC18/Drivers/Tick/isrTick.c

index a0d70258c027473efe3ceb6342ca7c350958c892..ab9d476f8940dea31f8a8ba6ab36c87abd9a0625 100644 (file)
--- a/Source/portable/WizC/PIC18/Drivers/Tick/isrTick.c
+++ b/Source/portable/WizC/PIC18/Drivers/Tick/isrTick.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/WizC/PIC18/addFreeRTOS.h b/Source/portable/WizC/PIC18/addFreeRTOS.h

index 87d2962865786e21d5a2a0672b91bff643c62de9..6868cb56ccd0e463038530f416c1267385ffd62a 100644 (file)
--- a/Source/portable/WizC/PIC18/addFreeRTOS.h
+++ b/Source/portable/WizC/PIC18/addFreeRTOS.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/WizC/PIC18/port.c b/Source/portable/WizC/PIC18/port.c

index 283c411f5e9fbdacb985ac93504bdb6a6e58ccf8..3a6d63fa319cc8453dbb38b36273155e75c662ac 100644 (file)
--- a/Source/portable/WizC/PIC18/port.c
+++ b/Source/portable/WizC/PIC18/port.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/WizC/PIC18/portmacro.h b/Source/portable/WizC/PIC18/portmacro.h

index b11404348586b84203411cf095a47d2a73c2a0f0..61d5733223807084e2aa5cc8e375341084a50b34 100644 (file)
--- a/Source/portable/WizC/PIC18/portmacro.h
+++ b/Source/portable/WizC/PIC18/portmacro.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/oWatcom/16BitDOS/Flsh186/port.c b/Source/portable/oWatcom/16BitDOS/Flsh186/port.c

index 4ed307ca4988c96b0a2537e925af792b37896057..77b87d1426f67c3a59afd05e48361e81c03bbb0c 100644 (file)
--- a/Source/portable/oWatcom/16BitDOS/Flsh186/port.c
+++ b/Source/portable/oWatcom/16BitDOS/Flsh186/port.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/oWatcom/16BitDOS/Flsh186/portmacro.h b/Source/portable/oWatcom/16BitDOS/Flsh186/portmacro.h

index 39121f9d70e92deb0eec606c370db5785fd69740..1bb063c5b148113c23b4ee1e7d4252a9d8a86ec9 100644 (file)
--- a/Source/portable/oWatcom/16BitDOS/Flsh186/portmacro.h
+++ b/Source/portable/oWatcom/16BitDOS/Flsh186/portmacro.h
@@ -1,5 +1,5 @@
  /*\r
-    FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+    FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
      This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/oWatcom/16BitDOS/PC/port.c b/Source/portable/oWatcom/16BitDOS/PC/port.c

index 1add941f4e459d9d3c66e750a4eba34e38cfc28c..16bee94540cf54539fae4470921957e5b7ef3501 100644 (file)
--- a/Source/portable/oWatcom/16BitDOS/PC/port.c
+++ b/Source/portable/oWatcom/16BitDOS/PC/port.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/oWatcom/16BitDOS/PC/portmacro.h b/Source/portable/oWatcom/16BitDOS/PC/portmacro.h

index 5a0f93bffc1002570fcb23dae1bc2e342483a153..853c73942d19abc6dfa0564118126552cc46bd30 100644 (file)
--- a/Source/portable/oWatcom/16BitDOS/PC/portmacro.h
+++ b/Source/portable/oWatcom/16BitDOS/PC/portmacro.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/oWatcom/16BitDOS/common/portasm.h b/Source/portable/oWatcom/16BitDOS/common/portasm.h

index 7e5bce3dfa2c85539017b0ecbad40e7c16dd8946..7e3e992c88d7d786bfeeafb39c3ec34c21ebfddb 100644 (file)
--- a/Source/portable/oWatcom/16BitDOS/common/portasm.h
+++ b/Source/portable/oWatcom/16BitDOS/common/portasm.h
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/portable/oWatcom/16BitDOS/common/portcomn.c b/Source/portable/oWatcom/16BitDOS/common/portcomn.c

index d92930b0f0cacc4d87cc95071509855a42c8b1fa..9848cc08039c7550c8534cedd6dcda42e29623fc 100644 (file)
--- a/Source/portable/oWatcom/16BitDOS/common/portcomn.c
+++ b/Source/portable/oWatcom/16BitDOS/common/portcomn.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/queue.c b/Source/queue.c

index 770ad536ba38d39b99274a379fe620ec30ab66f6..0c94c18e7c23f0fbcfca6e5cf34a0def29ca0201 100644 (file)
--- a/Source/queue.c
+++ b/Source/queue.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
diff --git a/Source/tasks.c b/Source/tasks.c

index 693460a9b6023af1026923678656524d2dcf5431..72819f18d2b70301f094db38dab59e93891ae260 100644 (file)
--- a/Source/tasks.c
+++ b/Source/tasks.c
@@ -1,5 +1,5 @@
  /*\r
-       FreeRTOS.org V4.0.2 - Copyright (C) 2003-2006 Richard Barry.\r
+       FreeRTOS.org V4.0.3 - Copyright (C) 2003-2006 Richard Barry.\r
  \r
         This file is part of the FreeRTOS.org distribution.\r
  \r
author	richardbarry <richardbarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
	Thu, 8 Jun 2006 09:16:29 +0000 (09:16 +0000)
committer	richardbarry <richardbarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
	Thu, 8 Jun 2006 09:16:29 +0000 (09:16 +0000)