1 //*****************************************************************************
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3 // startup.c - Boot code for Stellaris.
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5 // Copyright (c) 2005,2006 Luminary Micro, Inc. All rights reserved.
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7 // Software License Agreement
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9 // Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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10 // exclusively on LMI's Stellaris Family of microcontroller products.
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12 // The software is owned by LMI and/or its suppliers, and is protected under
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13 // applicable copyright laws. All rights are reserved. Any use in violation
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14 // of the foregoing restrictions may subject the user to criminal sanctions
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15 // under applicable laws, as well as to civil liability for the breach of the
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16 // terms and conditions of this license.
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18 // THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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19 // OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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20 // MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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21 // LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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22 // CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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24 // This is part of revision 635 of the Stellaris Driver Library.
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26 //*****************************************************************************
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28 //*****************************************************************************
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30 // Enable the IAR extensions for this source file.
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32 //*****************************************************************************
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33 #pragma language=extended
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35 //*****************************************************************************
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37 // Forward declaration of the default fault handlers.
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39 //*****************************************************************************
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40 void ResetISR(void);
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41 static void NmiSR(void);
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42 static void FaultISR(void);
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43 static void IntDefaultHandler(void);
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45 //*****************************************************************************
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47 // External declaration for the interrupt handler used by the application.
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49 //*****************************************************************************
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50 extern void xPortPendSVHandler(void);
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51 extern void xPortSysTickHandler(void);
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52 extern void vUART_ISR( void );
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54 //*****************************************************************************
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56 // The entry point for the application.
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58 //*****************************************************************************
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59 extern void main(void);
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61 //*****************************************************************************
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63 // Reserve space for the system stack.
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65 //*****************************************************************************
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67 #define STACK_SIZE 50
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69 static unsigned long pulStack[STACK_SIZE] = {
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120 //*****************************************************************************
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122 // A union that describes the entries of the vector table. The union is needed
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123 // since the first entry is the stack pointer and the remainder are function
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126 //*****************************************************************************
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129 void (*pfnHandler)(void);
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130 unsigned long ulPtr;
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134 //*****************************************************************************
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136 // The minimal vector table for a Cortex M3. Note that the proper constructs
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137 // must be placed on this to ensure that it ends up at physical address
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140 //*****************************************************************************
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141 __root const uVectorEntry g_pfnVectors[] @ "INTVEC" =
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143 { .ulPtr = (unsigned long)pulStack + sizeof(pulStack) },
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144 // The initial stack pointer
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145 ResetISR, // The reset handler
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146 NmiSR, // The NMI handler
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147 FaultISR, // The hard fault handler
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148 IntDefaultHandler, // The MPU fault handler
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149 IntDefaultHandler, // The bus fault handler
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150 IntDefaultHandler, // The usage fault handler
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155 IntDefaultHandler, // SVCall handler
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156 IntDefaultHandler, // Debug monitor handler
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158 xPortPendSVHandler, // The PendSV handler
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159 xPortSysTickHandler, // The SysTick handler
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160 IntDefaultHandler, // GPIO Port A
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161 IntDefaultHandler, // GPIO Port B
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162 IntDefaultHandler, // GPIO Port C
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163 IntDefaultHandler, // GPIO Port D
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164 IntDefaultHandler, // GPIO Port E
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165 vUART_ISR, // UART0 Rx and Tx
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166 IntDefaultHandler, // UART1 Rx and Tx
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167 IntDefaultHandler, // SSI Rx and Tx
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168 IntDefaultHandler, // I2C Master and Slave
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169 IntDefaultHandler, // PWM Fault
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170 IntDefaultHandler, // PWM Generator 0
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171 IntDefaultHandler, // PWM Generator 1
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172 IntDefaultHandler, // PWM Generator 2
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174 IntDefaultHandler, // ADC Sequence 0
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175 IntDefaultHandler, // ADC Sequence 1
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176 IntDefaultHandler, // ADC Sequence 2
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177 IntDefaultHandler, // ADC Sequence 3
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178 IntDefaultHandler, // Watchdog timer
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179 IntDefaultHandler, // Timer 0 subtimer A
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180 IntDefaultHandler, // Timer 0 subtimer B
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181 IntDefaultHandler, // Timer 1 subtimer A
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182 IntDefaultHandler, // Timer 1 subtimer B
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183 IntDefaultHandler, // Timer 2 subtimer A
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184 IntDefaultHandler, // Timer 2 subtimer B
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185 IntDefaultHandler, // Analog Comparator 0
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186 IntDefaultHandler, // Analog Comparator 1
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187 IntDefaultHandler, // Analog Comparator 2
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188 IntDefaultHandler, // System Control (PLL, OSC, BO)
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189 IntDefaultHandler // FLASH Control
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192 //*****************************************************************************
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194 // The following are constructs created by the linker, indicating where the
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195 // the "data" and "bss" segments reside in memory. The initializers for the
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196 // for the "data" segment resides immediately following the "text" segment.
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198 //*****************************************************************************
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199 #pragma segment="DATA_ID"
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200 #pragma segment="DATA_I"
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201 #pragma segment="DATA_Z"
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203 //*****************************************************************************
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205 // This is the code that gets called when the processor first starts execution
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206 // following a reset event. Only the absolutely necessary set is performed,
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207 // after which the application supplied entry() routine is called. Any fancy
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208 // actions (such as making decisions based on the reset cause register, and
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209 // resetting the bits in that register) are left solely in the hands of the
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212 //*****************************************************************************
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216 unsigned long *pulSrc, *pulDest, *pulEnd;
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219 // Copy the data segment initializers from flash to SRAM.
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221 pulSrc = __segment_begin("DATA_ID");
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222 pulDest = __segment_begin("DATA_I");
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223 pulEnd = __segment_end("DATA_I");
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224 while(pulDest < pulEnd)
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226 *pulDest++ = *pulSrc++;
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230 // Zero fill the bss segment.
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232 pulDest = __segment_begin("DATA_Z");
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233 pulEnd = __segment_end("DATA_Z");
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234 while(pulDest < pulEnd)
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240 // Call the application's entry point.
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245 //*****************************************************************************
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247 // This is the code that gets called when the processor receives a NMI. This
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248 // simply enters an infinite loop, preserving the system state for examination
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251 //*****************************************************************************
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256 // Enter an infinite loop.
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263 //*****************************************************************************
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265 // This is the code that gets called when the processor receives a fault
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266 // interrupt. This simply enters an infinite loop, preserving the system state
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267 // for examination by a debugger.
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269 //*****************************************************************************
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274 // Enter an infinite loop.
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281 //*****************************************************************************
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283 // This is the code that gets called when the processor receives an unexpected
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284 // interrupt. This simply enters an infinite loop, preserving the system state
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285 // for examination by a debugger.
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287 //*****************************************************************************
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289 IntDefaultHandler(void)
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292 // Go into an infinite loop.
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