2 FreeRTOS V7.5.1 - Copyright (C) 2013 Real Time Engineers Ltd.
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4 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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6 ***************************************************************************
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8 * FreeRTOS provides completely free yet professionally developed, *
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9 * robust, strictly quality controlled, supported, and cross *
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10 * platform software that has become a de facto standard. *
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12 * Help yourself get started quickly and support the FreeRTOS *
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13 * project by purchasing a FreeRTOS tutorial book, reference *
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14 * manual, or both from: http://www.FreeRTOS.org/Documentation *
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18 ***************************************************************************
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20 This file is part of the FreeRTOS distribution.
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22 FreeRTOS is free software; you can redistribute it and/or modify it under
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23 the terms of the GNU General Public License (version 2) as published by the
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24 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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26 >>! NOTE: The modification to the GPL is included to allow you to distribute
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27 >>! a combined work that includes FreeRTOS without being obliged to provide
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28 >>! the source code for proprietary components outside of the FreeRTOS
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31 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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32 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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33 FOR A PARTICULAR PURPOSE. Full license text is available from the following
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34 link: http://www.freertos.org/a00114.html
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38 ***************************************************************************
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40 * Having a problem? Start by reading the FAQ "My application does *
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41 * not run, what could be wrong?" *
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43 * http://www.FreeRTOS.org/FAQHelp.html *
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45 ***************************************************************************
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47 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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48 license and Real Time Engineers Ltd. contact details.
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50 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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51 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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52 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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54 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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55 Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
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56 licenses offer ticketed support, indemnification and middleware.
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58 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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59 engineered and independently SIL3 certified version for use in safety and
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60 mission critical applications that require provable dependability.
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65 /* Scheduler includes. */
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66 #include "FreeRTOS.h"
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70 /* Demo app includes. */
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71 #include "USBSample.h"
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73 #define usbINT_CLEAR_MASK (AT91C_UDP_TXCOMP | AT91C_UDP_STALLSENT | AT91C_UDP_RXSETUP | AT91C_UDP_RX_DATA_BK0 | AT91C_UDP_RX_DATA_BK1 )
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75 #define usbCSR_CLEAR_BIT( pulValueNow, ulBit ) \
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77 /* Set TXCOMP, RX_DATA_BK0, RXSETUP, */ \
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78 /* STALLSENT and RX_DATA_BK1 to 1 so the */ \
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79 /* write has no effect. */ \
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80 ( * ( ( unsigned long * ) pulValueNow ) ) |= ( unsigned long ) 0x4f; \
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82 /* Clear the FORCE_STALL and TXPKTRDY bits */ \
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83 /* so the write has no effect. */ \
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84 ( * ( ( unsigned long * ) pulValueNow ) ) &= ( unsigned long ) 0xffffffcf; \
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86 /* Clear whichever bit we want clear. */ \
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87 ( * ( ( unsigned long * ) pulValueNow ) ) &= ( ~ulBit ); \
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91 /*-----------------------------------------------------------*/
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97 void vUSB_ISR_Wrapper( void ) __attribute__((naked));
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100 * Actual ISR handler. This must be separate from the entry point as the stack
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103 void vUSB_ISR_Handler( void ) __attribute__((noinline));
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105 /*-----------------------------------------------------------*/
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107 /* Array in which the USB interrupt status is passed between the ISR and task. */
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108 static xISRStatus xISRMessages[ usbQUEUE_LENGTH + 1 ];
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110 /* Queue used to pass messages between the ISR and the task. */
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111 extern xQueueHandle xUSBInterruptQueue;
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113 /*-----------------------------------------------------------*/
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115 void vUSB_ISR_Handler( void )
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117 portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
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118 static volatile unsigned long ulNextMessage = 0;
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119 xISRStatus *pxMessage;
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120 unsigned long ulTemp, ulRxBytes;
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122 /* To reduce the amount of time spent in this interrupt it would be
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123 possible to defer the majority of this processing to an 'interrupt task',
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124 that is a task that runs at a higher priority than any of the application
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127 /* Take the next message from the queue. Note that usbQUEUE_LENGTH *must*
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128 be all 1's, as in 0x01, 0x03, 0x07, etc. */
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129 pxMessage = &( xISRMessages[ ( ulNextMessage & usbQUEUE_LENGTH ) ] );
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132 /* Take a snapshot of the current USB state for processing at the task
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134 pxMessage->ulISR = AT91C_BASE_UDP->UDP_ISR;
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135 pxMessage->ulCSR0 = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ];
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137 /* Clear the interrupts from the ICR register. The bus end interrupt is
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138 cleared separately as it does not appear in the mask register. */
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139 AT91C_BASE_UDP->UDP_ICR = AT91C_BASE_UDP->UDP_IMR | AT91C_UDP_ENDBUSRES;
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141 /* If there are bytes in the FIFO then we have to retrieve them here.
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142 Ideally this would be done at the task level. However we need to clear the
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143 RXSETUP interrupt before leaving the ISR, and this may cause the data in
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144 the FIFO to be overwritten. Also the DIR bit has to be changed before the
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145 RXSETUP bit is cleared (as per the SAM7 manual). */
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146 ulTemp = pxMessage->ulCSR0;
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148 /* Are there any bytes in the FIFO? */
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149 ulRxBytes = ulTemp >> 16;
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150 ulRxBytes &= usbRX_COUNT_MASK;
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152 /* With this minimal implementation we are only interested in receiving
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153 setup bytes on the control end point. */
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154 if( ( ulRxBytes > 0 ) && ( ulTemp & AT91C_UDP_RXSETUP ) )
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156 /* Take off 1 for a zero based index. */
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157 while( ulRxBytes > 0 )
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160 pxMessage->ucFifoData[ ulRxBytes ] = AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_0 ];
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163 /* The direction must be changed first. */
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164 usbCSR_SET_BIT( &ulTemp, ( AT91C_UDP_DIR ) );
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165 AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulTemp;
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168 /* Must write zero's to TXCOMP, STALLSENT, RXSETUP, and the RX DATA
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169 registers to clear the interrupts in the CSR register. */
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170 usbCSR_CLEAR_BIT( &ulTemp, usbINT_CLEAR_MASK );
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171 AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] = ulTemp;
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173 /* Also clear the interrupts in the CSR1 register. */
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174 ulTemp = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ];
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175 usbCSR_CLEAR_BIT( &ulTemp, usbINT_CLEAR_MASK );
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176 AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] = ulTemp;
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178 /* The message now contains the entire state and optional data from
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179 the USB interrupt. This can now be posted on the Rx queue ready for
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180 processing at the task level. */
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181 xQueueSendFromISR( xUSBInterruptQueue, &pxMessage, &xHigherPriorityTaskWoken );
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183 /* We may want to switch to the USB task, if this message has made
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184 it the highest priority task that is ready to execute. */
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185 if( xHigherPriorityTaskWoken )
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187 portYIELD_FROM_ISR();
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190 /* Clear the AIC ready for the next interrupt. */
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191 AT91C_BASE_AIC->AIC_EOICR = 0;
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193 /*-----------------------------------------------------------*/
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195 void vUSB_ISR_Wrapper( void )
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197 /* Save the context of the interrupted task. */
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198 portSAVE_CONTEXT();
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200 /* Call the handler itself. This must be a separate function as it uses
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202 __asm volatile ("bl vUSB_ISR_Handler");
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204 /* Restore the context of the task that is going to
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205 execute next. This might not be the same as the originally
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206 interrupted task.*/
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207 portRESTORE_CONTEXT();
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