1 -- *****************************************************************************
\r
3 -- BSDL file for design top
\r
5 -- Created by Synopsys Version I-2013.12-SP3 (Apr 18, 2014)
\r
10 -- Date: Thu Feb 5 23:41:59 2015
\r
12 -- *****************************************************************************
\r
17 -- This section identifies the default device package selected.
\r
19 generic (PHYSICAL_PIN_MAP: string:= "BGA289");
\r
21 -- This section declares all the ports in the design.
\r
151 DDR_D : inout bit_vector (0 to 31);
\r
152 DDR_DQS : inout bit_vector (0 to 3);
\r
153 DDR_DQSN : inout bit_vector (0 to 3);
\r
157 DDR_CLKN : out bit;
\r
160 DDR_RESETN : out bit;
\r
163 DDR_A : out bit_vector (0 to 13);
\r
164 DDR_BA : out bit_vector (0 to 2);
\r
165 DDR_DQM : out bit_vector (0 to 3);
\r
166 -- ADVREFN : linkage bit;
\r
167 ADVREFP : linkage bit;
\r
168 CLK_AUDIO : linkage bit;
\r
169 COMPN : linkage bit;
\r
170 COMPP : linkage bit;
\r
171 DDR_CAL : linkage bit;
\r
172 DDR_VREF : linkage bit; -- DDR_VREFB0 : linkage bit;
\r
173 -- DDR_VREFB1 : linkage bit;
\r
174 -- DDR_VREFB2 : linkage bit;
\r
175 -- DDR_VREFB3 : linkage bit;
\r
176 -- DDR_VREFCM : linkage bit;
\r
177 HHSDMA : linkage bit;
\r
178 HHSDMB : linkage bit;
\r
179 HHSDMSTRC : linkage bit;
\r
180 HHSDPA : linkage bit;
\r
181 HHSDPB : linkage bit;
\r
182 HHSDPDATC : linkage bit;
\r
184 NRST : linkage bit;
\r
186 SDCAL : linkage bit;
\r
187 SHDN : linkage bit;
\r
190 WKUP : linkage bit;
\r
192 XIN32 : linkage bit;
\r
193 XOUT : linkage bit;
\r
194 XOUT32 : linkage bit;
\r
195 -- tst_drst_ana : linkage bit; -- NC Port
\r
196 -- tst_drst_ddr : linkage bit; -- NC Port
\r
197 -- tst_drst_iop0 : linkage bit; -- NC Port
\r
198 -- tst_drst_iop1 : linkage bit; -- NC Port
\r
199 -- tst_drst_iop2 : linkage bit; -- NC Port
\r
200 -- tst_drst_isi : linkage bit; -- NC Port
\r
201 -- tst_drst_osc : linkage bit; -- NC Port
\r
202 -- tst_drst_sdhc : linkage bit; -- NC Port
\r
203 -- tst_lft_plla : linkage bit; -- NC Port
\r
204 -- tst_lft_utmi : linkage bit; -- NC Port
\r
205 -- tst_por_1v2 : linkage bit; -- NC Port
\r
206 -- tst_por_1v8 : linkage bit; -- NC Port
\r
207 -- tst_por_bu : linkage bit; -- NC Port
\r
208 -- tst_psw_bu : linkage bit; -- NC Port
\r
209 -- tst_psw_fuse : linkage bit; -- NC Port
\r
210 PIOBU : linkage bit_vector (0 to 7)
\r
213 use STD_1149_1_1994.all;
\r
215 attribute COMPONENT_CONFORMANCE of top: entity is "STD_1149_1_1993";
\r
217 attribute PIN_MAP of top: entity is PHYSICAL_PIN_MAP;
\r
219 -- This section specifies the pin map for each port. This information is
\r
220 -- extracted from the port-to-pin map file that was read in using the
\r
221 -- "read_pin_map" command.
\r
223 constant BGA289: PIN_MAP_STRING :=
\r
351 "DDR_D : (B12, A12, C12, A13, A14, C13, A15, B15, G17, G16, " &
\r
352 "H17, K17, K16, J13, K14, K15, B8, B9, C9, A9, A10, D10, B11, A11, " &
\r
353 "J12, H10, J11, K11, L13, L11, L12, M17)," &
\r
354 "DDR_DQS : (B13, J17, C10, L17)," &
\r
355 "DDR_DQSN : (B14, J16, B10, L16)," &
\r
359 "DDR_CLKN : D17," &
\r
362 "DDR_RESETN : E16," &
\r
365 "DDR_A : (F12, C17, B17, B16, C16, G14, F14, F11, C14, D13, " &
\r
366 "C15, A16, A17, G11)," &
\r
367 "DDR_BA : (H12, H13, F17)," &
\r
368 "DDR_DQM : (C11, G15, C8, H11)," &
\r
370 "CLK_AUDIO : U3," &
\r
376 "HHSDMSTRC : U10," &
\r
379 "HHSDPDATC : T9," &
\r
392 "PIOBU : (R3, N8, R2, R5, R4, P5, P6, M8)";
\r
394 -- This section specifies the differential IO port groupings.
\r
396 attribute PORT_GROUPING of top: entity is
\r
397 "Differential_Voltage ( " &
\r
398 "(DDR_CLK,DDR_CLKN))";
\r
400 -- This section specifies the TAP ports. For the TAP TCK port, the parameters in
\r
401 -- the brackets are:
\r
402 -- First Field : Maximum TCK frequency.
\r
403 -- Second Field: Allowable states TCK may be stopped in.
\r
405 attribute TAP_SCAN_CLOCK of PD14: signal is (10.0e6, BOTH);
\r
406 attribute TAP_SCAN_IN of PD15: signal is true;
\r
407 attribute TAP_SCAN_MODE of PD17: signal is true;
\r
408 attribute TAP_SCAN_OUT of PD16: signal is true;
\r
409 attribute TAP_SCAN_RESET of PD18: signal is true;
\r
411 -- Specifies the compliance enable patterns for the design. It lists a set of
\r
412 -- design ports and the values that they should be set to, in order to enable
\r
413 -- compliance to IEEE Std 1149.1
\r
415 attribute COMPLIANCE_PATTERNS of top: entity is
\r
416 "(JTAGSEL, TST) (10)";
\r
418 -- Specifies the number of bits in the instruction register.
\r
420 attribute INSTRUCTION_LENGTH of top: entity is 4;
\r
422 -- Specifies the boundary-scan instructions implemented in the design and their
\r
425 attribute INSTRUCTION_OPCODE of top: entity is
\r
426 "BYPASS (1111, 0001, 0101, 0110, 1100, 0111, 1101, 1000, 1001, 1011, " &
\r
434 -- Specifies the bit pattern that is loaded into the instruction register when
\r
435 -- the TAP controller passes through the Capture-IR state. The standard mandates
\r
436 -- that the two LSBs must be "01". The remaining bits are design specific.
\r
438 attribute INSTRUCTION_CAPTURE of top: entity is "0001";
\r
440 -- Specifies the bit pattern that is loaded into the DEVICE_ID register during
\r
441 -- the IDCODE instruction when the TAP controller passes through the Capture-DR
\r
444 attribute IDCODE_REGISTER of top: entity is
\r
446 -- 4-bit version number
\r
447 "0101101100111111" &
\r
448 -- 16-bit part number
\r
450 -- 11-bit identity of the manufacturer
\r
452 -- Required by IEEE Std 1149.1
\r
454 -- This section specifies the test data register placed between TDI and TDO for
\r
455 -- each implemented instruction.
\r
457 attribute REGISTER_ACCESS of top: entity is
\r
458 "BYPASS (BYPASS)," &
\r
459 "BOUNDARY (EXTEST, SAMPLE, INTEST)," &
\r
460 "DEVICE_ID (IDCODE)," &
\r
461 "UTDR1[41] (RUNBIST)";
\r
463 -- Specifies the length of the boundary scan register.
\r
465 attribute BOUNDARY_LENGTH of top: entity is 374;
\r
467 -- The following list specifies the characteristics of each cell in the boundary
\r
468 -- scan register from TDI to TDO. The following is a description of the label
\r
470 -- num : Is the cell number.
\r
471 -- cell : Is the cell type as defined by the standard.
\r
472 -- port : Is the design port name. Control cells do not have a port
\r
474 -- function: Is the function of the cell as defined by the standard. Is one
\r
475 -- of input, output2, output3, bidir, control or controlr.
\r
476 -- safe : Specifies the value that the BSR cell should be loaded with
\r
477 -- for safe operation when the software might otherwise choose a
\r
479 -- ccell : The control cell number. Specifies the control cell that
\r
480 -- drives the output enable for this port.
\r
481 -- disval : Specifies the value that is loaded into the control cell to
\r
482 -- disable the output enable for the corresponding port.
\r
483 -- rslt : Resulting state. Shows the state of the driver when it is
\r
486 attribute BOUNDARY_REGISTER of top: entity is
\r
488 -- num cell port function safe [ccell disval rslt]
\r
490 "373 (BC_1, *, control, 1), " &
\r
491 "372 (BC_7, PD13, bidir, X, 373, 1, Z), " &
\r
492 "371 (BC_1, *, control, 1), " &
\r
493 "370 (BC_7, PD12, bidir, X, 371, 1, Z), " &
\r
494 "369 (BC_1, *, control, 1), " &
\r
495 "368 (BC_7, PD11, bidir, X, 369, 1, Z), " &
\r
496 "367 (BC_1, *, control, 1), " &
\r
497 "366 (BC_7, PD19, bidir, X, 367, 1, Z), " &
\r
498 "365 (BC_1, *, control, 1), " &
\r
499 "364 (BC_7, PD20, bidir, X, 365, 1, Z), " &
\r
500 "363 (BC_1, *, control, 1), " &
\r
501 "362 (BC_7, PD24, bidir, X, 363, 1, Z), " &
\r
502 "361 (BC_1, *, control, 1), " &
\r
503 "360 (BC_7, PD21, bidir, X, 361, 1, Z), " &
\r
504 "359 (BC_1, *, control, 1), " &
\r
505 "358 (BC_7, PD25, bidir, X, 359, 1, Z), " &
\r
506 "357 (BC_1, *, control, 1), " &
\r
507 "356 (BC_7, PD26, bidir, X, 357, 1, Z), " &
\r
508 "355 (BC_1, *, control, 1), " &
\r
509 "354 (BC_7, PD22, bidir, X, 355, 1, Z), " &
\r
510 "353 (BC_1, *, control, 1), " &
\r
511 "352 (BC_7, PD27, bidir, X, 353, 1, Z), " &
\r
512 "351 (BC_1, *, control, 1), " &
\r
513 "350 (BC_7, PD23, bidir, X, 351, 1, Z), " &
\r
514 "349 (BC_1, *, control, 1), " &
\r
515 "348 (BC_7, PD28, bidir, X, 349, 1, Z), " &
\r
516 "347 (BC_1, *, control, 1), " &
\r
517 "346 (BC_7, PD30, bidir, X, 347, 1, Z), " &
\r
518 "345 (BC_1, *, control, 1), " &
\r
519 "344 (BC_7, PD29, bidir, X, 345, 1, Z), " &
\r
520 "343 (BC_1, *, control, 1), " &
\r
521 "342 (BC_7, PD31, bidir, X, 343, 1, Z), " &
\r
522 "341 (BC_1, *, control, 1), " &
\r
523 "340 (BC_7, PA0, bidir, X, 341, 1, Z), " &
\r
524 "339 (BC_1, *, control, 1), " &
\r
525 "338 (BC_7, PA1, bidir, X, 339, 1, Z), " &
\r
526 "337 (BC_1, *, control, 1), " &
\r
527 "336 (BC_7, PA2, bidir, X, 337, 1, Z), " &
\r
528 "335 (BC_1, *, control, 1), " &
\r
529 "334 (BC_7, PA3, bidir, X, 335, 1, Z), " &
\r
530 "333 (BC_1, *, control, 1), " &
\r
531 "332 (BC_7, PA4, bidir, X, 333, 1, Z), " &
\r
532 "331 (BC_1, *, control, 1), " &
\r
533 "330 (BC_7, PA5, bidir, X, 331, 1, Z), " &
\r
534 "329 (BC_1, *, control, 1), " &
\r
535 "328 (BC_7, PA6, bidir, X, 329, 1, Z), " &
\r
536 "327 (BC_1, *, control, 1), " &
\r
537 "326 (BC_7, PA7, bidir, X, 327, 1, Z), " &
\r
538 "325 (BC_1, *, control, 1), " &
\r
539 "324 (BC_7, PA8, bidir, X, 325, 1, Z), " &
\r
540 "323 (BC_1, *, control, 1), " &
\r
541 "322 (BC_7, PA9, bidir, X, 323, 1, Z), " &
\r
542 "321 (BC_1, *, control, 1), " &
\r
543 "320 (BC_7, PA10, bidir, X, 321, 1, Z), " &
\r
544 "319 (BC_1, *, control, 1), " &
\r
545 "318 (BC_7, PA18, bidir, X, 319, 1, Z), " &
\r
546 "317 (BC_1, *, control, 1), " &
\r
547 "316 (BC_7, PA20, bidir, X, 317, 1, Z), " &
\r
548 "315 (BC_1, *, control, 1), " &
\r
549 "314 (BC_7, PA19, bidir, X, 315, 1, Z), " &
\r
550 "313 (BC_1, *, control, 1), " &
\r
551 "312 (BC_7, PA21, bidir, X, 313, 1, Z), " &
\r
552 "311 (BC_1, *, control, 1), " &
\r
553 "310 (BC_7, PA22, bidir, X, 311, 1, Z), " &
\r
554 "309 (BC_1, *, control, 1), " &
\r
555 "308 (BC_7, PA23, bidir, X, 309, 1, Z), " &
\r
556 "307 (BC_1, *, control, 1), " &
\r
557 "306 (BC_7, PA24, bidir, X, 307, 1, Z), " &
\r
558 "305 (BC_1, *, control, 1), " &
\r
559 "304 (BC_7, PA25, bidir, X, 305, 1, Z), " &
\r
560 "303 (BC_1, *, control, 1), " &
\r
561 "302 (BC_7, PA26, bidir, X, 303, 1, Z), " &
\r
562 "301 (BC_1, *, control, 1), " &
\r
563 "300 (BC_7, PA27, bidir, X, 301, 1, Z), " &
\r
564 "299 (BC_1, *, control, 1), " &
\r
565 "298 (BC_7, PA28, bidir, X, 299, 1, Z), " &
\r
566 "297 (BC_1, *, control, 1), " &
\r
567 "296 (BC_7, PA30, bidir, X, 297, 1, Z), " &
\r
568 "295 (BC_1, *, control, 1), " &
\r
569 "294 (BC_7, PA29, bidir, X, 295, 1, Z), " &
\r
570 "293 (BC_1, *, control, 1), " &
\r
571 "292 (BC_7, PA31, bidir, X, 293, 1, Z), " &
\r
572 "291 (BC_1, *, control, 1), " &
\r
573 "290 (BC_7, PC0, bidir, X, 291, 1, Z), " &
\r
574 "289 (BC_1, *, control, 1), " &
\r
575 "288 (BC_7, PA11, bidir, X, 289, 1, Z), " &
\r
576 "287 (BC_1, *, control, 1), " &
\r
577 "286 (BC_7, PC1, bidir, X, 287, 1, Z), " &
\r
578 "285 (BC_1, *, control, 1), " &
\r
579 "284 (BC_7, PA13, bidir, X, 285, 1, Z), " &
\r
580 "283 (BC_1, *, control, 1), " &
\r
581 "282 (BC_7, PA12, bidir, X, 283, 1, Z), " &
\r
582 "281 (BC_1, *, control, 1), " &
\r
583 "280 (BC_7, PC2, bidir, X, 281, 1, Z), " &
\r
584 "279 (BC_1, *, control, 1), " &
\r
585 "278 (BC_7, PA14, bidir, X, 279, 1, Z), " &
\r
586 "277 (BC_1, *, control, 1), " &
\r
587 "276 (BC_7, PA15, bidir, X, 277, 1, Z), " &
\r
588 "275 (BC_1, *, control, 1), " &
\r
589 "274 (BC_7, PC3, bidir, X, 275, 1, Z), " &
\r
590 "273 (BC_1, *, control, 1), " &
\r
591 "272 (BC_7, PC4, bidir, X, 273, 1, Z), " &
\r
592 "271 (BC_1, *, control, 1), " &
\r
593 "270 (BC_7, PA16, bidir, X, 271, 1, Z), " &
\r
594 "269 (BC_1, *, control, 1), " &
\r
595 "268 (BC_7, PA17, bidir, X, 269, 1, Z), " &
\r
596 "267 (BC_1, *, control, 1), " &
\r
597 "266 (BC_7, PC5, bidir, X, 267, 1, Z), " &
\r
598 "265 (BC_1, *, control, 1), " &
\r
599 "264 (BC_7, PC7, bidir, X, 265, 1, Z), " &
\r
600 "263 (BC_1, *, control, 1), " &
\r
601 "262 (BC_7, PC6, bidir, X, 263, 1, Z), " &
\r
602 "261 (BC_1, *, control, 1), " &
\r
603 "260 (BC_7, PC8, bidir, X, 261, 1, Z), " &
\r
604 "259 (BC_1, *, control, 1), " &
\r
605 "258 (BC_7, DDR_D(31), bidir, X, 259, 1, Z), " &
\r
606 "257 (BC_1, *, control, 1), " &
\r
607 "256 (BC_7, DDR_D(30), bidir, X, 257, 1, Z), " &
\r
608 "255 (BC_1, *, control, 1), " &
\r
609 "254 (BC_7, DDR_D(29), bidir, X, 255, 1, Z), " &
\r
610 "253 (BC_1, *, control, 1), " &
\r
611 "252 (BC_7, DDR_D(28), bidir, X, 253, 1, Z), " &
\r
612 "251 (BC_1, *, control, 1), " &
\r
613 "250 (BC_7, DDR_DQS(3), bidir, X, 251, 1, Z), " &
\r
614 "249 (BC_1, *, control, 1), " &
\r
615 "248 (BC_7, DDR_D(27), bidir, X, 249, 1, Z), " &
\r
616 "247 (BC_1, *, control, 1), " &
\r
617 "246 (BC_7, DDR_D(26), bidir, X, 247, 1, Z), " &
\r
618 "245 (BC_1, *, control, 1), " &
\r
619 "244 (BC_7, DDR_D(25), bidir, X, 245, 1, Z), " &
\r
620 "243 (BC_1, *, control, 1), " &
\r
621 "242 (BC_7, DDR_D(24), bidir, X, 243, 1, Z), " &
\r
622 "241 (BC_0, *, control, 1), " &
\r
623 "240 (BC_0, DDR_DQM(3), output3, X, 241, 1, Z), " &
\r
624 "239 (BC_1, *, control, 1), " &
\r
625 "238 (BC_7, DDR_D(15), bidir, X, 239, 1, Z), " &
\r
626 "237 (BC_1, *, control, 1), " &
\r
627 "236 (BC_7, DDR_D(14), bidir, X, 237, 1, Z), " &
\r
628 "235 (BC_1, *, control, 1), " &
\r
629 "234 (BC_7, DDR_D(13), bidir, X, 235, 1, Z), " &
\r
630 "233 (BC_1, *, control, 1), " &
\r
631 "232 (BC_7, DDR_D(12), bidir, X, 233, 1, Z), " &
\r
632 "231 (BC_1, *, control, 1), " &
\r
633 "230 (BC_7, DDR_DQS(1), bidir, X, 231, 1, Z), " &
\r
634 "229 (BC_1, *, control, 1), " &
\r
635 "228 (BC_7, DDR_D(11), bidir, X, 229, 1, Z), " &
\r
636 "227 (BC_1, *, control, 1), " &
\r
637 "226 (BC_7, DDR_D(10), bidir, X, 227, 1, Z), " &
\r
638 "225 (BC_1, *, control, 1), " &
\r
639 "224 (BC_7, DDR_D(9), bidir, X, 225, 1, Z), " &
\r
640 "223 (BC_1, *, control, 1), " &
\r
641 "222 (BC_7, DDR_D(8), bidir, X, 223, 1, Z), " &
\r
642 "221 (BC_0, *, control, 1), " &
\r
643 "220 (BC_0, DDR_DQM(1), output3, X, 221, 1, Z), " &
\r
644 "219 (BC_0, *, control, 1), " &
\r
645 "218 (BC_0, DDR_BA(2), output3, X, 219, 1, Z), " &
\r
646 "217 (BC_0, *, control, 1), " &
\r
647 "216 (BC_0, DDR_BA(1), output3, X, 217, 1, Z), " &
\r
648 "215 (BC_0, *, control, 1), " &
\r
649 "214 (BC_0, DDR_BA(0), output3, X, 215, 1, Z), " &
\r
650 "213 (BC_0, *, control, 1), " &
\r
651 "212 (BC_0, DDR_CKE, output3, X, 213, 1, Z), " &
\r
652 "211 (BC_0, *, control, 1), " &
\r
653 "210 (BC_0, DDR_CS, output3, X, 211, 1, Z), " &
\r
654 "209 (BC_0, *, control, 1), " &
\r
655 "208 (BC_0, DDR_A(13), output3, X, 209, 1, Z), " &
\r
656 "207 (BC_0, *, control, 1), " &
\r
657 "206 (BC_0, DDR_RESETN, output3, X, 207, 1, Z), " &
\r
658 "205 (BC_0, *, control, 1), " &
\r
659 "204 (BC_0, DDR_A(5), output3, X, 205, 1, Z), " &
\r
660 "203 (BC_0, *, control, 1), " &
\r
661 "202 (BC_0, DDR_A(6), output3, X, 203, 1, Z), " &
\r
662 "201 (BC_0, *, control, 1), " &
\r
663 "200 (BC_0, DDR_RAS, output3, X, 201, 1, Z), " &
\r
664 "199 (BC_0, *, control, 1), " &
\r
665 "198 (BC_0, DDR_CAS, output3, X, 199, 1, Z), " &
\r
666 "197 (BC_0, *, control, 1), " &
\r
667 "196 (BC_0, DDR_WE, output3, X, 197, 1, Z), " &
\r
668 "195 (BC_0, *, control, 1), " &
\r
669 "194 (BC_0, DDR_CLK, output3, X, 195, 1, Z), " &
\r
670 "193 (BC_0, *, control, 1), " &
\r
671 "192 (BC_0, DDR_A(0), output3, X, 193, 1, Z), " &
\r
672 "191 (BC_0, *, control, 1), " &
\r
673 "190 (BC_0, DDR_A(1), output3, X, 191, 1, Z), " &
\r
674 "189 (BC_0, *, control, 1), " &
\r
675 "188 (BC_0, DDR_A(2), output3, X, 189, 1, Z), " &
\r
676 "187 (BC_0, *, control, 1), " &
\r
677 "186 (BC_0, DDR_A(3), output3, X, 187, 1, Z), " &
\r
678 "185 (BC_0, *, control, 1), " &
\r
679 "184 (BC_0, DDR_A(4), output3, X, 185, 1, Z), " &
\r
680 "183 (BC_0, *, control, 1), " &
\r
681 "182 (BC_0, DDR_A(12), output3, X, 183, 1, Z), " &
\r
682 "181 (BC_0, *, control, 1), " &
\r
683 "180 (BC_0, DDR_A(11), output3, X, 181, 1, Z), " &
\r
684 "179 (BC_0, *, control, 1), " &
\r
685 "178 (BC_0, DDR_A(10), output3, X, 179, 1, Z), " &
\r
686 "177 (BC_0, *, control, 1), " &
\r
687 "176 (BC_0, DDR_A(9), output3, X, 177, 1, Z), " &
\r
688 "175 (BC_0, *, control, 1), " &
\r
689 "174 (BC_0, DDR_A(8), output3, X, 175, 1, Z), " &
\r
690 "173 (BC_0, *, control, 1), " &
\r
691 "172 (BC_0, DDR_A(7), output3, X, 173, 1, Z), " &
\r
692 "171 (BC_1, *, control, 1), " &
\r
693 "170 (BC_7, DDR_D(7), bidir, X, 171, 1, Z), " &
\r
694 "169 (BC_1, *, control, 1), " &
\r
695 "168 (BC_7, DDR_D(6), bidir, X, 169, 1, Z), " &
\r
696 "167 (BC_1, *, control, 1), " &
\r
697 "166 (BC_7, DDR_D(5), bidir, X, 167, 1, Z), " &
\r
698 "165 (BC_1, *, control, 1), " &
\r
699 "164 (BC_7, DDR_D(4), bidir, X, 165, 1, Z), " &
\r
700 "163 (BC_1, *, control, 1), " &
\r
701 "162 (BC_7, DDR_DQS(0), bidir, X, 163, 1, Z), " &
\r
702 "161 (BC_1, *, control, 1), " &
\r
703 "160 (BC_7, DDR_D(3), bidir, X, 161, 1, Z), " &
\r
704 "159 (BC_1, *, control, 1), " &
\r
705 "158 (BC_7, DDR_D(2), bidir, X, 159, 1, Z), " &
\r
706 "157 (BC_1, *, control, 1), " &
\r
707 "156 (BC_7, DDR_D(1), bidir, X, 157, 1, Z), " &
\r
708 "155 (BC_1, *, control, 1), " &
\r
709 "154 (BC_7, DDR_D(0), bidir, X, 155, 1, Z), " &
\r
710 "153 (BC_0, *, control, 1), " &
\r
711 "152 (BC_0, DDR_DQM(0), output3, X, 153, 1, Z), " &
\r
712 "151 (BC_1, *, control, 1), " &
\r
713 "150 (BC_7, DDR_D(23), bidir, X, 151, 1, Z), " &
\r
714 "149 (BC_1, *, control, 1), " &
\r
715 "148 (BC_7, DDR_D(22), bidir, X, 149, 1, Z), " &
\r
716 "147 (BC_1, *, control, 1), " &
\r
717 "146 (BC_7, DDR_D(21), bidir, X, 147, 1, Z), " &
\r
718 "145 (BC_1, *, control, 1), " &
\r
719 "144 (BC_7, DDR_D(20), bidir, X, 145, 1, Z), " &
\r
720 "143 (BC_1, *, control, 1), " &
\r
721 "142 (BC_7, DDR_DQS(2), bidir, X, 143, 1, Z), " &
\r
722 "141 (BC_1, *, control, 1), " &
\r
723 "140 (BC_7, DDR_D(19), bidir, X, 141, 1, Z), " &
\r
724 "139 (BC_1, *, control, 1), " &
\r
725 "138 (BC_7, DDR_D(18), bidir, X, 139, 1, Z), " &
\r
726 "137 (BC_1, *, control, 1), " &
\r
727 "136 (BC_7, DDR_D(17), bidir, X, 137, 1, Z), " &
\r
728 "135 (BC_1, *, control, 1), " &
\r
729 "134 (BC_7, DDR_D(16), bidir, X, 135, 1, Z), " &
\r
730 "133 (BC_0, *, control, 1), " &
\r
731 "132 (BC_0, DDR_DQM(2), output3, X, 133, 1, Z), " &
\r
732 "131 (BC_1, *, control, 1), " &
\r
733 "130 (BC_7, PD0, bidir, X, 131, 1, Z), " &
\r
734 "129 (BC_1, *, control, 1), " &
\r
735 "128 (BC_7, PD1, bidir, X, 129, 1, Z), " &
\r
736 "127 (BC_1, *, control, 1), " &
\r
737 "126 (BC_7, PD2, bidir, X, 127, 1, Z), " &
\r
738 "125 (BC_1, *, control, 1), " &
\r
739 "124 (BC_7, PC26, bidir, X, 125, 1, Z), " &
\r
740 "123 (BC_1, *, control, 1), " &
\r
741 "122 (BC_7, PC27, bidir, X, 123, 1, Z), " &
\r
742 "121 (BC_1, *, control, 1), " &
\r
743 "120 (BC_7, PC28, bidir, X, 121, 1, Z), " &
\r
744 "119 (BC_1, *, control, 1), " &
\r
745 "118 (BC_7, PC29, bidir, X, 119, 1, Z), " &
\r
746 "117 (BC_1, *, control, 1), " &
\r
747 "116 (BC_7, PC30, bidir, X, 117, 1, Z), " &
\r
748 "115 (BC_1, *, control, 1), " &
\r
749 "114 (BC_7, PC31, bidir, X, 115, 1, Z), " &
\r
750 "113 (BC_1, *, control, 1), " &
\r
751 "112 (BC_7, PB0, bidir, X, 113, 1, Z), " &
\r
752 "111 (BC_1, *, control, 1), " &
\r
753 "110 (BC_7, PB2, bidir, X, 111, 1, Z), " &
\r
754 "109 (BC_1, *, control, 1), " &
\r
755 "108 (BC_7, PB1, bidir, X, 109, 1, Z), " &
\r
756 "107 (BC_1, *, control, 1), " &
\r
757 "106 (BC_7, PB3, bidir, X, 107, 1, Z), " &
\r
758 "105 (BC_1, *, control, 1), " &
\r
759 "104 (BC_7, PB4, bidir, X, 105, 1, Z), " &
\r
760 "103 (BC_1, *, control, 1), " &
\r
761 "102 (BC_7, PB5, bidir, X, 103, 1, Z), " &
\r
762 "101 (BC_1, *, control, 1), " &
\r
763 "100 (BC_7, PB6, bidir, X, 101, 1, Z), " &
\r
764 "99 (BC_1, *, control, 1), " &
\r
765 "98 (BC_7, PB8, bidir, X, 99, 1, Z), " &
\r
766 "97 (BC_1, *, control, 1), " &
\r
767 "96 (BC_7, PB7, bidir, X, 97, 1, Z), " &
\r
768 "95 (BC_1, *, control, 1), " &
\r
769 "94 (BC_7, PB10, bidir, X, 95, 1, Z), " &
\r
770 "93 (BC_1, *, control, 1), " &
\r
771 "92 (BC_7, PB9, bidir, X, 93, 1, Z), " &
\r
772 "91 (BC_1, *, control, 1), " &
\r
773 "90 (BC_7, PB11, bidir, X, 91, 1, Z), " &
\r
774 "89 (BC_1, *, control, 1), " &
\r
775 "88 (BC_7, PB12, bidir, X, 89, 1, Z), " &
\r
776 "87 (BC_1, *, control, 1), " &
\r
777 "86 (BC_7, PB14, bidir, X, 87, 1, Z), " &
\r
778 "85 (BC_1, *, control, 1), " &
\r
779 "84 (BC_7, PB13, bidir, X, 85, 1, Z), " &
\r
780 "83 (BC_1, *, control, 1), " &
\r
781 "82 (BC_7, PB15, bidir, X, 83, 1, Z), " &
\r
782 "81 (BC_1, *, control, 1), " &
\r
783 "80 (BC_7, PB16, bidir, X, 81, 1, Z), " &
\r
784 "79 (BC_1, *, control, 1), " &
\r
785 "78 (BC_7, PB17, bidir, X, 79, 1, Z), " &
\r
786 "77 (BC_1, *, control, 1), " &
\r
787 "76 (BC_7, PB19, bidir, X, 77, 1, Z), " &
\r
788 "75 (BC_1, *, control, 1), " &
\r
789 "74 (BC_7, PB18, bidir, X, 75, 1, Z), " &
\r
790 "73 (BC_1, *, control, 1), " &
\r
791 "72 (BC_7, PB20, bidir, X, 73, 1, Z), " &
\r
792 "71 (BC_1, *, control, 1), " &
\r
793 "70 (BC_7, PB21, bidir, X, 71, 1, Z), " &
\r
794 "69 (BC_1, *, control, 1), " &
\r
795 "68 (BC_7, PB23, bidir, X, 69, 1, Z), " &
\r
796 "67 (BC_1, *, control, 1), " &
\r
797 "66 (BC_7, PB22, bidir, X, 67, 1, Z), " &
\r
798 "65 (BC_1, *, control, 1), " &
\r
799 "64 (BC_7, PB25, bidir, X, 65, 1, Z), " &
\r
800 "63 (BC_1, *, control, 1), " &
\r
801 "62 (BC_7, PB24, bidir, X, 63, 1, Z), " &
\r
802 "61 (BC_1, *, control, 1), " &
\r
803 "60 (BC_7, PB26, bidir, X, 61, 1, Z), " &
\r
804 "59 (BC_1, *, control, 1), " &
\r
805 "58 (BC_7, PB28, bidir, X, 59, 1, Z), " &
\r
806 "57 (BC_1, *, control, 1), " &
\r
807 "56 (BC_7, PB27, bidir, X, 57, 1, Z), " &
\r
808 "55 (BC_1, *, control, 1), " &
\r
809 "54 (BC_7, PB30, bidir, X, 55, 1, Z), " &
\r
810 "53 (BC_1, *, control, 1), " &
\r
811 "52 (BC_7, PB29, bidir, X, 53, 1, Z), " &
\r
812 "51 (BC_1, *, control, 1), " &
\r
813 "50 (BC_7, PB31, bidir, X, 51, 1, Z), " &
\r
814 "49 (BC_1, *, control, 1), " &
\r
815 "48 (BC_7, PC9, bidir, X, 49, 1, Z), " &
\r
816 "47 (BC_1, *, control, 1), " &
\r
817 "46 (BC_7, PC11, bidir, X, 47, 1, Z), " &
\r
818 "45 (BC_1, *, control, 1), " &
\r
819 "44 (BC_7, PC10, bidir, X, 45, 1, Z), " &
\r
820 "43 (BC_1, *, control, 1), " &
\r
821 "42 (BC_7, PC12, bidir, X, 43, 1, Z), " &
\r
822 "41 (BC_1, *, control, 1), " &
\r
823 "40 (BC_7, PC13, bidir, X, 41, 1, Z), " &
\r
824 "39 (BC_1, *, control, 1), " &
\r
825 "38 (BC_7, PC14, bidir, X, 39, 1, Z), " &
\r
826 "37 (BC_1, *, control, 1), " &
\r
827 "36 (BC_7, PC15, bidir, X, 37, 1, Z), " &
\r
828 "35 (BC_1, *, control, 1), " &
\r
829 "34 (BC_7, PC17, bidir, X, 35, 1, Z), " &
\r
830 "33 (BC_1, *, control, 1), " &
\r
831 "32 (BC_7, PC16, bidir, X, 33, 1, Z), " &
\r
832 "31 (BC_1, *, control, 1), " &
\r
833 "30 (BC_7, PC19, bidir, X, 31, 1, Z), " &
\r
834 "29 (BC_1, *, control, 1), " &
\r
835 "28 (BC_7, PC18, bidir, X, 29, 1, Z), " &
\r
836 "27 (BC_1, *, control, 1), " &
\r
837 "26 (BC_7, PC20, bidir, X, 27, 1, Z), " &
\r
838 "25 (BC_1, *, control, 1), " &
\r
839 "24 (BC_7, PC21, bidir, X, 25, 1, Z), " &
\r
840 "23 (BC_1, *, control, 1), " &
\r
841 "22 (BC_7, PC22, bidir, X, 23, 1, Z), " &
\r
842 "21 (BC_1, *, control, 1), " &
\r
843 "20 (BC_7, PC23, bidir, X, 21, 1, Z), " &
\r
844 "19 (BC_1, *, control, 1), " &
\r
845 "18 (BC_7, PC24, bidir, X, 19, 1, Z), " &
\r
846 "17 (BC_1, *, control, 1), " &
\r
847 "16 (BC_7, PC25, bidir, X, 17, 1, Z), " &
\r
848 "15 (BC_1, *, control, 1), " &
\r
849 "14 (BC_7, PD10, bidir, X, 15, 1, Z), " &
\r
850 "13 (BC_1, *, control, 1), " &
\r
851 "12 (BC_7, PD9, bidir, X, 13, 1, Z), " &
\r
852 "11 (BC_1, *, control, 1), " &
\r
853 "10 (BC_7, PD8, bidir, X, 11, 1, Z), " &
\r
854 "9 (BC_1, *, control, 1), " &
\r
855 "8 (BC_7, PD7, bidir, X, 9, 1, Z), " &
\r
856 "7 (BC_1, *, control, 1), " &
\r
857 "6 (BC_7, PD6, bidir, X, 7, 1, Z), " &
\r
858 "5 (BC_1, *, control, 1), " &
\r
859 "4 (BC_7, PD5, bidir, X, 5, 1, Z), " &
\r
860 "3 (BC_1, *, control, 1), " &
\r
861 "2 (BC_7, PD4, bidir, X, 3, 1, Z), " &
\r
862 "1 (BC_1, *, control, 1), " &
\r
863 "0 (BC_7, PD3, bidir, X, 1, 1, Z) ";
\r
projects / freertos / blob